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authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-17 16:15:55 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-17 16:15:55 -0500
commit8dea78da5cee153b8af9c07a2745f6c55057fe12 (patch)
treea8f4d49d63b1ecc92f2fddceba0655b2472c5bd9 /arch/arm/boot/dts
parent406089d01562f1e2bf9f089fd7637009ebaad589 (diff)
Patched in Tegra support.
Diffstat (limited to 'arch/arm/boot/dts')
-rw-r--r--arch/arm/boot/dts/Makefile166
-rw-r--r--arch/arm/boot/dts/aks-cdu.dts113
-rw-r--r--arch/arm/boot/dts/am335x-bone.dts138
-rw-r--r--arch/arm/boot/dts/am335x-evm.dts246
-rw-r--r--arch/arm/boot/dts/am335x-evmsk.dts250
-rw-r--r--arch/arm/boot/dts/am33xx.dtsi389
-rw-r--r--arch/arm/boot/dts/am3517-evm.dts32
-rw-r--r--arch/arm/boot/dts/am3517_mt_ventoux.dts27
-rw-r--r--arch/arm/boot/dts/animeo_ip.dts178
-rw-r--r--arch/arm/boot/dts/armada-370-db.dts63
-rw-r--r--arch/arm/boot/dts/armada-370-mirabox.dts56
-rw-r--r--arch/arm/boot/dts/armada-370-xp.dtsi136
-rw-r--r--arch/arm/boot/dts/armada-370.dtsi136
-rw-r--r--arch/arm/boot/dts/armada-xp-db.dts94
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78230.dtsi76
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78260.dtsi97
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78460.dtsi112
-rw-r--r--arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts125
-rw-r--r--arch/arm/boot/dts/armada-xp.dtsi138
-rw-r--r--arch/arm/boot/dts/at91rm9200.dtsi349
-rw-r--r--arch/arm/boot/dts/at91rm9200ek.dts79
-rw-r--r--arch/arm/boot/dts/at91sam9260.dtsi536
-rw-r--r--arch/arm/boot/dts/at91sam9263.dtsi469
-rw-r--r--arch/arm/boot/dts/at91sam9263ek.dts185
-rw-r--r--arch/arm/boot/dts/at91sam9g15.dtsi28
-rw-r--r--arch/arm/boot/dts/at91sam9g15ek.dts16
-rw-r--r--arch/arm/boot/dts/at91sam9g20.dtsi30
-rw-r--r--arch/arm/boot/dts/at91sam9g20ek.dts29
-rw-r--r--arch/arm/boot/dts/at91sam9g20ek_2mmc.dts55
-rw-r--r--arch/arm/boot/dts/at91sam9g20ek_common.dtsi202
-rw-r--r--arch/arm/boot/dts/at91sam9g25.dtsi28
-rw-r--r--arch/arm/boot/dts/at91sam9g25ek.dts16
-rw-r--r--arch/arm/boot/dts/at91sam9g35.dtsi28
-rw-r--r--arch/arm/boot/dts/at91sam9g35ek.dts16
-rw-r--r--arch/arm/boot/dts/at91sam9g45.dtsi545
-rw-r--r--arch/arm/boot/dts/at91sam9m10g45ek.dts212
-rw-r--r--arch/arm/boot/dts/at91sam9n12.dtsi400
-rw-r--r--arch/arm/boot/dts/at91sam9n12ek.dts114
-rw-r--r--arch/arm/boot/dts/at91sam9x25.dtsi49
-rw-r--r--arch/arm/boot/dts/at91sam9x25ek.dts16
-rw-r--r--arch/arm/boot/dts/at91sam9x35.dtsi28
-rw-r--r--arch/arm/boot/dts/at91sam9x35ek.dts16
-rw-r--r--arch/arm/boot/dts/at91sam9x5.dtsi548
-rw-r--r--arch/arm/boot/dts/at91sam9x5cm.dtsi74
-rw-r--r--arch/arm/boot/dts/at91sam9x5ek.dtsi101
-rw-r--r--arch/arm/boot/dts/bcm11351-brt.dts30
-rw-r--r--arch/arm/boot/dts/bcm11351.dtsi50
-rw-r--r--arch/arm/boot/dts/bcm2835-rpi-b.dts27
-rw-r--r--arch/arm/boot/dts/bcm2835.dtsi67
-rw-r--r--arch/arm/boot/dts/ccu9540.dts72
-rw-r--r--arch/arm/boot/dts/cros5250-common.dtsi184
-rw-r--r--arch/arm/boot/dts/da850-enbw-cmc.dts30
-rw-r--r--arch/arm/boot/dts/da850-evm.dts28
-rw-r--r--arch/arm/boot/dts/da850.dtsi60
-rw-r--r--arch/arm/boot/dts/dbx5x0.dtsi688
-rw-r--r--arch/arm/boot/dts/dove-cm-a510.dts38
-rw-r--r--arch/arm/boot/dts/dove-cubox.dts52
-rw-r--r--arch/arm/boot/dts/dove-dove-db.dts38
-rw-r--r--arch/arm/boot/dts/dove.dtsi234
-rw-r--r--arch/arm/boot/dts/ea3250.dts281
-rw-r--r--arch/arm/boot/dts/ecx-2000.dts108
-rw-r--r--arch/arm/boot/dts/ecx-common.dtsi237
-rw-r--r--arch/arm/boot/dts/elpida_ecb240abacn.dtsi67
-rw-r--r--arch/arm/boot/dts/emev2-kzm9d.dts26
-rw-r--r--arch/arm/boot/dts/emev2.dtsi63
-rw-r--r--arch/arm/boot/dts/ethernut5.dts84
-rw-r--r--arch/arm/boot/dts/evk-pro3.dts53
-rw-r--r--arch/arm/boot/dts/exynos4.dtsi292
-rw-r--r--arch/arm/boot/dts/exynos4210-origen.dts124
-rw-r--r--arch/arm/boot/dts/exynos4210-pinctrl.dtsi735
-rw-r--r--arch/arm/boot/dts/exynos4210-smdkv310.dts192
-rw-r--r--arch/arm/boot/dts/exynos4210-trats.dts292
-rw-r--r--arch/arm/boot/dts/exynos4210.dtsi79
-rw-r--r--arch/arm/boot/dts/exynos4212.dtsi28
-rw-r--r--arch/arm/boot/dts/exynos4412-smdk4412.dts45
-rw-r--r--arch/arm/boot/dts/exynos4412.dtsi28
-rw-r--r--arch/arm/boot/dts/exynos4x12-pinctrl.dtsi965
-rw-r--r--arch/arm/boot/dts/exynos4x12.dtsi69
-rw-r--r--arch/arm/boot/dts/exynos5250-smdk5250.dts207
-rw-r--r--arch/arm/boot/dts/exynos5250-snow.dts43
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi586
-rw-r--r--arch/arm/boot/dts/exynos5440-ssdk5440.dts46
-rw-r--r--arch/arm/boot/dts/exynos5440.dtsi159
-rw-r--r--arch/arm/boot/dts/ge863-pro3.dtsi52
-rw-r--r--arch/arm/boot/dts/highbank.dts126
-rw-r--r--arch/arm/boot/dts/href.dtsi273
-rw-r--r--arch/arm/boot/dts/hrefprev60.dts48
-rw-r--r--arch/arm/boot/dts/hrefv60plus.dts210
-rw-r--r--arch/arm/boot/dts/imx23-evk.dts106
-rw-r--r--arch/arm/boot/dts/imx23-olinuxino.dts120
-rw-r--r--arch/arm/boot/dts/imx23-stmp378x_devb.dts78
-rw-r--r--arch/arm/boot/dts/imx23.dtsi479
-rw-r--r--arch/arm/boot/dts/imx25-karo-tx25.dts44
-rw-r--r--arch/arm/boot/dts/imx25.dtsi515
-rw-r--r--arch/arm/boot/dts/imx27-3ds.dts37
-rw-r--r--arch/arm/boot/dts/imx27-apf27.dts89
-rw-r--r--arch/arm/boot/dts/imx27-phytec-phycore.dts73
-rw-r--r--arch/arm/boot/dts/imx27.dtsi241
-rw-r--r--arch/arm/boot/dts/imx28-apf28.dts85
-rw-r--r--arch/arm/boot/dts/imx28-apf28dev.dts154
-rw-r--r--arch/arm/boot/dts/imx28-apx4devkit.dts198
-rw-r--r--arch/arm/boot/dts/imx28-cfa10036.dts98
-rw-r--r--arch/arm/boot/dts/imx28-cfa10049.dts156
-rw-r--r--arch/arm/boot/dts/imx28-evk.dts316
-rw-r--r--arch/arm/boot/dts/imx28-m28evk.dts277
-rw-r--r--arch/arm/boot/dts/imx28-sps1.dts169
-rw-r--r--arch/arm/boot/dts/imx28-tx28.dts116
-rw-r--r--arch/arm/boot/dts/imx28.dtsi953
-rw-r--r--arch/arm/boot/dts/imx31-bug.dts31
-rw-r--r--arch/arm/boot/dts/imx31.dtsi88
-rw-r--r--arch/arm/boot/dts/imx51-babbage.dts283
-rw-r--r--arch/arm/boot/dts/imx51.dtsi561
-rw-r--r--arch/arm/boot/dts/imx53-ard.dts164
-rw-r--r--arch/arm/boot/dts/imx53-evk.dts134
-rw-r--r--arch/arm/boot/dts/imx53-qsb.dts278
-rw-r--r--arch/arm/boot/dts/imx53-smd.dts190
-rw-r--r--arch/arm/boot/dts/imx53.dtsi668
-rw-r--r--arch/arm/boot/dts/imx6q-arm2.dts110
-rw-r--r--arch/arm/boot/dts/imx6q-sabreauto.dts64
-rw-r--r--arch/arm/boot/dts/imx6q-sabrelite.dts178
-rw-r--r--arch/arm/boot/dts/imx6q-sabresd.dts94
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi1060
-rw-r--r--arch/arm/boot/dts/integrator.dtsi76
-rw-r--r--arch/arm/boot/dts/integratorap.dts73
-rw-r--r--arch/arm/boot/dts/integratorcp.dts115
-rw-r--r--arch/arm/boot/dts/kirkwood-6281.dtsi44
-rw-r--r--arch/arm/boot/dts/kirkwood-6282.dtsi46
-rw-r--r--arch/arm/boot/dts/kirkwood-98dx4122.dtsi31
-rw-r--r--arch/arm/boot/dts/kirkwood-dns320.dts54
-rw-r--r--arch/arm/boot/dts/kirkwood-dns325.dts57
-rw-r--r--arch/arm/boot/dts/kirkwood-dnskw.dtsi219
-rw-r--r--arch/arm/boot/dts/kirkwood-dockstar.dts94
-rw-r--r--arch/arm/boot/dts/kirkwood-dreamplug.dts95
-rw-r--r--arch/arm/boot/dts/kirkwood-goflexnet.dts172
-rw-r--r--arch/arm/boot/dts/kirkwood-ib62x0.dts122
-rw-r--r--arch/arm/boot/dts/kirkwood-iconnect.dts171
-rw-r--r--arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts194
-rw-r--r--arch/arm/boot/dts/kirkwood-is2.dts30
-rw-r--r--arch/arm/boot/dts/kirkwood-km_kirkwood.dts46
-rw-r--r--arch/arm/boot/dts/kirkwood-lschlv2.dts20
-rw-r--r--arch/arm/boot/dts/kirkwood-lsxhl.dts20
-rw-r--r--arch/arm/boot/dts/kirkwood-lsxl.dtsi203
-rw-r--r--arch/arm/boot/dts/kirkwood-mplcec4.dts178
-rw-r--r--arch/arm/boot/dts/kirkwood-ns2-common.dtsi63
-rw-r--r--arch/arm/boot/dts/kirkwood-ns2.dts30
-rw-r--r--arch/arm/boot/dts/kirkwood-ns2lite.dts30
-rw-r--r--arch/arm/boot/dts/kirkwood-ns2max.dts49
-rw-r--r--arch/arm/boot/dts/kirkwood-ns2mini.dts49
-rw-r--r--arch/arm/boot/dts/kirkwood-nsa310.dts144
-rw-r--r--arch/arm/boot/dts/kirkwood-openblocks_a6.dts98
-rw-r--r--arch/arm/boot/dts/kirkwood-topkick.dts102
-rw-r--r--arch/arm/boot/dts/kirkwood-ts219-6281.dts52
-rw-r--r--arch/arm/boot/dts/kirkwood-ts219-6282.dts52
-rw-r--r--arch/arm/boot/dts/kirkwood-ts219.dtsi78
-rw-r--r--arch/arm/boot/dts/kirkwood.dtsi195
-rw-r--r--arch/arm/boot/dts/kizbox.dts138
-rw-r--r--arch/arm/boot/dts/lpc32xx.dtsi295
-rw-r--r--arch/arm/boot/dts/mmp2-brownstone.dts38
-rw-r--r--arch/arm/boot/dts/mmp2.dtsi225
-rw-r--r--arch/arm/boot/dts/msm8660-surf.dts41
-rw-r--r--arch/arm/boot/dts/msm8960-cdp.dts41
-rw-r--r--arch/arm/boot/dts/omap2.dtsi155
-rw-r--r--arch/arm/boot/dts/omap2420-h4.dts20
-rw-r--r--arch/arm/boot/dts/omap2420.dtsi60
-rw-r--r--arch/arm/boot/dts/omap2430.dtsi101
-rw-r--r--arch/arm/boot/dts/omap3-beagle-xm.dts109
-rw-r--r--arch/arm/boot/dts/omap3-beagle.dts67
-rw-r--r--arch/arm/boot/dts/omap3-evm.dts61
-rw-r--r--arch/arm/boot/dts/omap3-overo.dtsi57
-rw-r--r--arch/arm/boot/dts/omap3-tobi.dts35
-rw-r--r--arch/arm/boot/dts/omap3.dtsi401
-rw-r--r--arch/arm/boot/dts/omap36xx.dtsi25
-rw-r--r--arch/arm/boot/dts/omap4-panda-a4.dts17
-rw-r--r--arch/arm/boot/dts/omap4-panda-es.dts33
-rw-r--r--arch/arm/boot/dts/omap4-panda.dts208
-rw-r--r--arch/arm/boot/dts/omap4-sdp-es23plus.dts17
-rw-r--r--arch/arm/boot/dts/omap4-sdp.dts430
-rw-r--r--arch/arm/boot/dts/omap4-var-som.dts96
-rw-r--r--arch/arm/boot/dts/omap4.dtsi533
-rw-r--r--arch/arm/boot/dts/omap5-evm.dts153
-rw-r--r--arch/arm/boot/dts/omap5.dtsi500
-rw-r--r--arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts55
-rw-r--r--arch/arm/boot/dts/orion5x.dtsi98
-rw-r--r--arch/arm/boot/dts/phy3250.dts202
-rw-r--r--arch/arm/boot/dts/picoxcell-pc3x2.dtsi249
-rw-r--r--arch/arm/boot/dts/picoxcell-pc3x3.dtsi365
-rw-r--r--arch/arm/boot/dts/picoxcell-pc7302-pc3x2.dts86
-rw-r--r--arch/arm/boot/dts/picoxcell-pc7302-pc3x3.dts92
-rw-r--r--arch/arm/boot/dts/pm9g45.dts165
-rw-r--r--arch/arm/boot/dts/prima2-evb.dts37
-rw-r--r--arch/arm/boot/dts/prima2.dtsi640
-rw-r--r--arch/arm/boot/dts/pxa168-aspenite.dts38
-rw-r--r--arch/arm/boot/dts/pxa168.dtsi133
-rw-r--r--arch/arm/boot/dts/pxa27x.dtsi14
-rw-r--r--arch/arm/boot/dts/pxa2xx.dtsi132
-rw-r--r--arch/arm/boot/dts/pxa3xx.dtsi32
-rw-r--r--arch/arm/boot/dts/pxa910-dkb.dts175
-rw-r--r--arch/arm/boot/dts/pxa910.dtsi149
-rw-r--r--arch/arm/boot/dts/r8a7740-armadillo800eva.dts22
-rw-r--r--arch/arm/boot/dts/r8a7740.dtsi21
-rw-r--r--arch/arm/boot/dts/samsung_k3pe0e000b.dtsi67
-rw-r--r--arch/arm/boot/dts/sh7372-mackerel.dts22
-rw-r--r--arch/arm/boot/dts/sh7372.dtsi21
-rw-r--r--arch/arm/boot/dts/sh73a0-kzm9g.dts22
-rw-r--r--arch/arm/boot/dts/snowball.dts350
-rw-r--r--arch/arm/boot/dts/socfpga.dtsi157
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5.dts34
-rw-r--r--arch/arm/boot/dts/spear1310-evb.dts423
-rw-r--r--arch/arm/boot/dts/spear1310.dtsi229
-rw-r--r--arch/arm/boot/dts/spear1340-evb.dts521
-rw-r--r--arch/arm/boot/dts/spear1340.dtsi143
-rw-r--r--arch/arm/boot/dts/spear13xx.dtsi313
-rw-r--r--arch/arm/boot/dts/spear300-evb.dts255
-rw-r--r--arch/arm/boot/dts/spear300.dtsi89
-rw-r--r--arch/arm/boot/dts/spear310-evb.dts208
-rw-r--r--arch/arm/boot/dts/spear310.dtsi118
-rw-r--r--arch/arm/boot/dts/spear320-evb.dts207
-rw-r--r--arch/arm/boot/dts/spear320-hmi.dts305
-rw-r--r--arch/arm/boot/dts/spear320.dtsi147
-rw-r--r--arch/arm/boot/dts/spear3xx.dtsi153
-rw-r--r--arch/arm/boot/dts/spear600-evb.dts116
-rw-r--r--arch/arm/boot/dts/spear600.dtsi205
-rw-r--r--arch/arm/boot/dts/stuib.dtsi78
-rw-r--r--arch/arm/boot/dts/sun4i-a10-cubieboard.dts38
-rw-r--r--arch/arm/boot/dts/sun4i-a10.dtsi19
-rw-r--r--arch/arm/boot/dts/sun5i-a13-olinuxino.dts30
-rw-r--r--arch/arm/boot/dts/sun5i-a13.dtsi20
-rw-r--r--arch/arm/boot/dts/sunxi.dtsi80
-rw-r--r--arch/arm/boot/dts/tegra20-harmony.dts540
-rw-r--r--arch/arm/boot/dts/tegra20-medcom-wide.dts58
-rw-r--r--arch/arm/boot/dts/tegra20-paz00.dts489
-rw-r--r--arch/arm/boot/dts/tegra20-plutux.dts56
-rw-r--r--arch/arm/boot/dts/tegra20-seaboard.dts658
-rw-r--r--arch/arm/boot/dts/tegra20-tamonten.dtsi490
-rw-r--r--arch/arm/boot/dts/tegra20-tec.dts56
-rw-r--r--arch/arm/boot/dts/tegra20-trimslice.dts354
-rw-r--r--arch/arm/boot/dts/tegra20-ventana.dts596
-rw-r--r--arch/arm/boot/dts/tegra20-whistler.dts552
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi403
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu-a02.dts93
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu-a04.dts104
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu.dtsi487
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi456
-rw-r--r--arch/arm/boot/dts/testcases/tests-phandle.dtsi39
-rw-r--r--arch/arm/boot/dts/testcases/tests.dtsi1
-rw-r--r--arch/arm/boot/dts/tny_a9260.dts15
-rw-r--r--arch/arm/boot/dts/tny_a9260_common.dtsi83
-rw-r--r--arch/arm/boot/dts/tny_a9263.dts97
-rw-r--r--arch/arm/boot/dts/tny_a9g20.dts15
-rw-r--r--arch/arm/boot/dts/tps65217.dtsi56
-rw-r--r--arch/arm/boot/dts/tps65910.dtsi86
-rw-r--r--arch/arm/boot/dts/twl4030.dtsi78
-rw-r--r--arch/arm/boot/dts/twl6030.dtsi94
-rw-r--r--arch/arm/boot/dts/u9540.dts72
-rw-r--r--arch/arm/boot/dts/usb_a9260.dts23
-rw-r--r--arch/arm/boot/dts/usb_a9260_common.dtsi117
-rw-r--r--arch/arm/boot/dts/usb_a9263.dts131
-rw-r--r--arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi96
-rw-r--r--arch/arm/boot/dts/usb_a9g20.dts30
-rw-r--r--arch/arm/boot/dts/versatile-ab.dts2
-rw-r--r--arch/arm/boot/dts/versatile-pb.dts4
-rw-r--r--arch/arm/boot/dts/vexpress-v2m-rs1.dtsi340
-rw-r--r--arch/arm/boot/dts/vexpress-v2m.dtsi339
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts283
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts368
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca5s.dts245
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca9.dts327
-rw-r--r--arch/arm/boot/dts/vt8500-bv07.dts36
-rw-r--r--arch/arm/boot/dts/vt8500.dtsi116
-rw-r--r--arch/arm/boot/dts/wm8505-ref.dts36
-rw-r--r--arch/arm/boot/dts/wm8505.dtsi143
-rw-r--r--arch/arm/boot/dts/wm8650-mid.dts36
-rw-r--r--arch/arm/boot/dts/wm8650.dtsi147
-rw-r--r--arch/arm/boot/dts/xenvm-4.2.dts68
-rw-r--r--arch/arm/boot/dts/zynq-7000.dtsi166
-rw-r--r--arch/arm/boot/dts/zynq-zc702.dts44
276 files changed, 64 insertions, 45058 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
deleted file mode 100644
index 5ebb44fe826..00000000000
--- a/arch/arm/boot/dts/Makefile
+++ /dev/null
@@ -1,166 +0,0 @@
1ifeq ($(CONFIG_OF),y)
2
3# Keep at91 dtb files sorted alphabetically for each SoC
4# rm9200
5dtb-$(CONFIG_ARCH_AT91) += at91rm9200ek.dtb
6# sam9260
7dtb-$(CONFIG_ARCH_AT91) += animeo_ip.dtb
8dtb-$(CONFIG_ARCH_AT91) += aks-cdu.dtb
9dtb-$(CONFIG_ARCH_AT91) += ethernut5.dtb
10dtb-$(CONFIG_ARCH_AT91) += evk-pro3.dtb
11dtb-$(CONFIG_ARCH_AT91) += tny_a9260.dtb
12dtb-$(CONFIG_ARCH_AT91) += usb_a9260.dtb
13# sam9263
14dtb-$(CONFIG_ARCH_AT91) += at91sam9263ek.dtb
15dtb-$(CONFIG_ARCH_AT91) += tny_a9263.dtb
16dtb-$(CONFIG_ARCH_AT91) += usb_a9263.dtb
17# sam9g20
18dtb-$(CONFIG_ARCH_AT91) += at91sam9g20ek.dtb
19dtb-$(CONFIG_ARCH_AT91) += at91sam9g20ek_2mmc.dtb
20dtb-$(CONFIG_ARCH_AT91) += kizbox.dtb
21dtb-$(CONFIG_ARCH_AT91) += tny_a9g20.dtb
22dtb-$(CONFIG_ARCH_AT91) += usb_a9g20.dtb
23# sam9g45
24dtb-$(CONFIG_ARCH_AT91) += at91sam9m10g45ek.dtb
25dtb-$(CONFIG_ARCH_AT91) += pm9g45.dtb
26# sam9n12
27dtb-$(CONFIG_ARCH_AT91) += at91sam9n12ek.dtb
28# sam9x5
29dtb-$(CONFIG_ARCH_AT91) += at91sam9g15ek.dtb
30dtb-$(CONFIG_ARCH_AT91) += at91sam9g25ek.dtb
31dtb-$(CONFIG_ARCH_AT91) += at91sam9g35ek.dtb
32dtb-$(CONFIG_ARCH_AT91) += at91sam9x25ek.dtb
33dtb-$(CONFIG_ARCH_AT91) += at91sam9x35ek.dtb
34
35dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
36dtb-$(CONFIG_ARCH_BCM) += bcm11351-brt.dtb
37dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
38 da850-evm.dtb
39dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
40 dove-cubox.dtb \
41 dove-dove-db.dtb
42dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
43 exynos4210-smdkv310.dtb \
44 exynos4210-trats.dtb \
45 exynos4412-smdk4412.dtb \
46 exynos5250-smdk5250.dtb \
47 exynos5250-snow.dtb \
48 exynos5440-ssdk5440.dtb
49dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
50 ecx-2000.dtb
51dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
52 integratorcp.dtb
53dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
54dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-dns320.dtb \
55 kirkwood-dns325.dtb \
56 kirkwood-dockstar.dtb \
57 kirkwood-dreamplug.dtb \
58 kirkwood-goflexnet.dtb \
59 kirkwood-ib62x0.dtb \
60 kirkwood-iconnect.dtb \
61 kirkwood-iomega_ix2_200.dtb \
62 kirkwood-is2.dtb \
63 kirkwood-km_kirkwood.dtb \
64 kirkwood-lschlv2.dtb \
65 kirkwood-lsxhl.dtb \
66 kirkwood-mplcec4.dtb \
67 kirkwood-ns2.dtb \
68 kirkwood-ns2lite.dtb \
69 kirkwood-ns2max.dtb \
70 kirkwood-ns2mini.dtb \
71 kirkwood-nsa310.dtb \
72 kirkwood-topkick.dtb \
73 kirkwood-ts219-6281.dtb \
74 kirkwood-ts219-6282.dtb \
75 kirkwood-openblocks_a6.dtb
76dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \
77 msm8960-cdp.dtb
78dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
79 armada-370-mirabox.dtb \
80 armada-xp-db.dtb \
81 armada-xp-openblocks-ax3-4.dtb
82dtb-$(CONFIG_ARCH_MXC) += imx51-babbage.dtb \
83 imx53-ard.dtb \
84 imx53-evk.dtb \
85 imx53-qsb.dtb \
86 imx53-smd.dtb \
87 imx6q-arm2.dtb \
88 imx6q-sabreauto.dtb \
89 imx6q-sabrelite.dtb \
90 imx6q-sabresd.dtb
91dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
92 imx23-olinuxino.dtb \
93 imx23-stmp378x_devb.dtb \
94 imx28-apf28.dtb \
95 imx28-apf28dev.dtb \
96 imx28-apx4devkit.dtb \
97 imx28-cfa10036.dtb \
98 imx28-cfa10049.dtb \
99 imx28-evk.dtb \
100 imx28-m28evk.dtb \
101 imx28-sps1.dtb \
102 imx28-tx28.dtb
103dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
104 omap3-beagle.dtb \
105 omap3-beagle-xm.dtb \
106 omap3-evm.dtb \
107 omap3-tobi.dtb \
108 omap4-panda.dtb \
109 omap4-panda-a4.dtb \
110 omap4-panda-es.dtb \
111 omap4-var-som.dtb \
112 omap4-sdp.dtb \
113 omap5-evm.dtb \
114 am335x-evm.dtb \
115 am335x-evmsk.dtb \
116 am335x-bone.dtb
117dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
118dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
119dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \
120 hrefprev60.dtb \
121 hrefv60plus.dtb \
122 ccu9540.dtb
123dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
124 r8a7740-armadillo800eva.dtb \
125 sh73a0-kzm9g.dtb \
126 sh7372-mackerel.dtb
127dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \
128 spear1340-evb.dtb
129dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
130 spear310-evb.dtb \
131 spear320-evb.dtb \
132 spear320-hmi.dtb
133dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
134dtb-$(CONFIG_ARCH_SUNXI) += sun4i-a10-cubieboard.dtb \
135 sun5i-a13-olinuxino.dtb
136dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
137 tegra20-medcom-wide.dtb \
138 tegra20-paz00.dtb \
139 tegra20-plutux.dtb \
140 tegra20-seaboard.dtb \
141 tegra20-tec.dtb \
142 tegra20-trimslice.dtb \
143 tegra20-ventana.dtb \
144 tegra20-whistler.dtb \
145 tegra30-cardhu-a02.dtb \
146 tegra30-cardhu-a04.dtb
147dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \
148 vexpress-v2p-ca9.dtb \
149 vexpress-v2p-ca15-tc1.dtb \
150 vexpress-v2p-ca15_a7.dtb \
151 xenvm-4.2.dtb
152dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \
153 wm8505-ref.dtb \
154 wm8650-mid.dtb
155dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb
156
157targets += dtbs
158targets += $(dtb-y)
159endif
160
161# *.dtb used to be generated in the directory above. Clean out the
162# old build results so people don't accidentally use them.
163dtbs: $(addprefix $(obj)/, $(dtb-y))
164 $(Q)rm -f $(obj)/../*.dtb
165
166clean-files := *.dtb
diff --git a/arch/arm/boot/dts/aks-cdu.dts b/arch/arm/boot/dts/aks-cdu.dts
deleted file mode 100644
index 29b9f15e759..00000000000
--- a/arch/arm/boot/dts/aks-cdu.dts
+++ /dev/null
@@ -1,113 +0,0 @@
1/*
2 * aks-cdu.dts - Device Tree file for AK signal CDU
3 *
4 * Copyright (C) 2012 AK signal Brno a.s.
5 * 2012 Jiri Prchal <jiri.prchal@aksignal.cz>
6 *
7 * Licensed under GPLv2 or later.
8 */
9
10/dts-v1/;
11
12/include/ "ge863-pro3.dtsi"
13
14/ {
15 chosen {
16 bootargs = "console=ttyS0,115200 ubi.mtd=4 root=ubi0:rootfs rootfstype=ubifs";
17 };
18
19 ahb {
20 apb {
21 usart0: serial@fffb0000 {
22 status = "okay";
23 };
24
25 usart1: serial@fffb4000 {
26 status = "okay";
27 linux,rs485-enabled-at-boot-time;
28 rs485-rts-delay = <0 0>;
29 };
30
31 usart2: serial@fffb8000 {
32 status = "okay";
33 linux,rs485-enabled-at-boot-time;
34 rs485-rts-delay = <0 0>;
35 };
36
37 usart3: serial@fffd0000 {
38 status = "okay";
39 linux,rs485-enabled-at-boot-time;
40 rs485-rts-delay = <0 0>;
41 };
42
43 macb0: ethernet@fffc4000 {
44 phy-mode = "rmii";
45 status = "okay";
46 };
47
48 usb1: gadget@fffa4000 {
49 atmel,vbus-gpio = <&pioC 15 0>;
50 status = "okay";
51 };
52 };
53
54 usb0: ohci@00500000 {
55 num-ports = <2>;
56 status = "okay";
57 };
58
59 nand0: nand@40000000 {
60 nand-bus-width = <8>;
61 nand-ecc-mode = "soft";
62 nand-on-flash-bbt;
63 status = "okay";
64
65 bootstrap@0 {
66 label = "bootstrap";
67 reg = <0x0 0x40000>;
68 };
69
70 uboot@40000 {
71 label = "uboot";
72 reg = <0x40000 0x80000>;
73 };
74 ubootenv@c0000 {
75 label = "ubootenv";
76 reg = <0xc0000 0x40000>;
77 };
78 kernel@100000 {
79 label = "kernel";
80 reg = <0x100000 0x400000>;
81 };
82 rootfs@500000 {
83 label = "rootfs";
84 reg = <0x500000 0x7b00000>;
85 };
86 };
87 };
88
89 leds {
90 compatible = "gpio-leds";
91
92 red {
93 gpios = <&pioC 10 0>;
94 linux,default-trigger = "none";
95 };
96
97 green {
98 gpios = <&pioA 5 1>;
99 linux,default-trigger = "none";
100 default-state = "on";
101 };
102
103 yellow {
104 gpios = <&pioB 20 1>;
105 linux,default-trigger = "none";
106 };
107
108 blue {
109 gpios = <&pioB 21 1>;
110 linux,default-trigger = "none";
111 };
112 };
113};
diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
deleted file mode 100644
index 11b240c5d32..00000000000
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ /dev/null
@@ -1,138 +0,0 @@
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10/include/ "am33xx.dtsi"
11
12/ {
13 model = "TI AM335x BeagleBone";
14 compatible = "ti,am335x-bone", "ti,am33xx";
15
16 cpus {
17 cpu@0 {
18 cpu0-supply = <&dcdc2_reg>;
19 };
20 };
21
22 memory {
23 device_type = "memory";
24 reg = <0x80000000 0x10000000>; /* 256 MB */
25 };
26
27 am33xx_pinmux: pinmux@44e10800 {
28 pinctrl-names = "default";
29 pinctrl-0 = <&user_leds_s0>;
30
31 user_leds_s0: user_leds_s0 {
32 pinctrl-single,pins = <
33 0x54 0x7 /* gpmc_a5.gpio1_21, OUTPUT | MODE7 */
34 0x58 0x17 /* gpmc_a6.gpio1_22, OUTPUT_PULLUP | MODE7 */
35 0x5c 0x7 /* gpmc_a7.gpio1_23, OUTPUT | MODE7 */
36 0x60 0x17 /* gpmc_a8.gpio1_24, OUTPUT_PULLUP | MODE7 */
37 >;
38 };
39 };
40
41 ocp {
42 uart1: serial@44e09000 {
43 status = "okay";
44 };
45
46 i2c1: i2c@44e0b000 {
47 status = "okay";
48 clock-frequency = <400000>;
49
50 tps: tps@24 {
51 reg = <0x24>;
52 };
53
54 };
55 };
56
57 leds {
58 compatible = "gpio-leds";
59
60 led@2 {
61 label = "beaglebone:green:heartbeat";
62 gpios = <&gpio2 21 0>;
63 linux,default-trigger = "heartbeat";
64 default-state = "off";
65 };
66
67 led@3 {
68 label = "beaglebone:green:mmc0";
69 gpios = <&gpio2 22 0>;
70 linux,default-trigger = "mmc0";
71 default-state = "off";
72 };
73
74 led@4 {
75 label = "beaglebone:green:usr2";
76 gpios = <&gpio2 23 0>;
77 default-state = "off";
78 };
79
80 led@5 {
81 label = "beaglebone:green:usr3";
82 gpios = <&gpio2 24 0>;
83 default-state = "off";
84 };
85 };
86};
87
88/include/ "tps65217.dtsi"
89
90&tps {
91 regulators {
92 dcdc1_reg: regulator@0 {
93 regulator-always-on;
94 };
95
96 dcdc2_reg: regulator@1 {
97 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
98 regulator-name = "vdd_mpu";
99 regulator-min-microvolt = <925000>;
100 regulator-max-microvolt = <1325000>;
101 regulator-boot-on;
102 regulator-always-on;
103 };
104
105 dcdc3_reg: regulator@2 {
106 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
107 regulator-name = "vdd_core";
108 regulator-min-microvolt = <925000>;
109 regulator-max-microvolt = <1150000>;
110 regulator-boot-on;
111 regulator-always-on;
112 };
113
114 ldo1_reg: regulator@3 {
115 regulator-always-on;
116 };
117
118 ldo2_reg: regulator@4 {
119 regulator-always-on;
120 };
121
122 ldo3_reg: regulator@5 {
123 regulator-always-on;
124 };
125
126 ldo4_reg: regulator@6 {
127 regulator-always-on;
128 };
129 };
130};
131
132&cpsw_emac0 {
133 phy_id = <&davinci_mdio>, <0>;
134};
135
136&cpsw_emac1 {
137 phy_id = <&davinci_mdio>, <1>;
138};
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
deleted file mode 100644
index d6496440fce..00000000000
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ /dev/null
@@ -1,246 +0,0 @@
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10/include/ "am33xx.dtsi"
11
12/ {
13 model = "TI AM335x EVM";
14 compatible = "ti,am335x-evm", "ti,am33xx";
15
16 cpus {
17 cpu@0 {
18 cpu0-supply = <&vdd1_reg>;
19 };
20 };
21
22 memory {
23 device_type = "memory";
24 reg = <0x80000000 0x10000000>; /* 256 MB */
25 };
26
27 am33xx_pinmux: pinmux@44e10800 {
28 pinctrl-names = "default";
29 pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0>;
30
31 matrix_keypad_s0: matrix_keypad_s0 {
32 pinctrl-single,pins = <
33 0x54 0x7 /* gpmc_a5.gpio1_21, OUTPUT | MODE7 */
34 0x58 0x7 /* gpmc_a6.gpio1_22, OUTPUT | MODE7 */
35 0x64 0x27 /* gpmc_a9.gpio1_25, INPUT | MODE7 */
36 0x68 0x27 /* gpmc_a10.gpio1_26, INPUT | MODE7 */
37 0x6c 0x27 /* gpmc_a11.gpio1_27, INPUT | MODE7 */
38 >;
39 };
40
41 volume_keys_s0: volume_keys_s0 {
42 pinctrl-single,pins = <
43 0x150 0x27 /* spi0_sclk.gpio0_2, INPUT | MODE7 */
44 0x154 0x27 /* spi0_d0.gpio0_3, INPUT | MODE7 */
45 >;
46 };
47 };
48
49 ocp {
50 uart1: serial@44e09000 {
51 status = "okay";
52 };
53
54 i2c1: i2c@44e0b000 {
55 status = "okay";
56 clock-frequency = <400000>;
57
58 tps: tps@2d {
59 reg = <0x2d>;
60 };
61 };
62
63 i2c2: i2c@4802a000 {
64 status = "okay";
65 clock-frequency = <100000>;
66
67 lis331dlh: lis331dlh@18 {
68 compatible = "st,lis331dlh", "st,lis3lv02d";
69 reg = <0x18>;
70 Vdd-supply = <&lis3_reg>;
71 Vdd_IO-supply = <&lis3_reg>;
72
73 st,click-single-x;
74 st,click-single-y;
75 st,click-single-z;
76 st,click-thresh-x = <10>;
77 st,click-thresh-y = <10>;
78 st,click-thresh-z = <10>;
79 st,irq1-click;
80 st,irq2-click;
81 st,wakeup-x-lo;
82 st,wakeup-x-hi;
83 st,wakeup-y-lo;
84 st,wakeup-y-hi;
85 st,wakeup-z-lo;
86 st,wakeup-z-hi;
87 st,min-limit-x = <120>;
88 st,min-limit-y = <120>;
89 st,min-limit-z = <140>;
90 st,max-limit-x = <550>;
91 st,max-limit-y = <550>;
92 st,max-limit-z = <750>;
93 };
94
95 tsl2550: tsl2550@39 {
96 compatible = "taos,tsl2550";
97 reg = <0x39>;
98 };
99
100 tmp275: tmp275@48 {
101 compatible = "ti,tmp275";
102 reg = <0x48>;
103 };
104 };
105 };
106
107 vbat: fixedregulator@0 {
108 compatible = "regulator-fixed";
109 regulator-name = "vbat";
110 regulator-min-microvolt = <5000000>;
111 regulator-max-microvolt = <5000000>;
112 regulator-boot-on;
113 };
114
115 lis3_reg: fixedregulator@1 {
116 compatible = "regulator-fixed";
117 regulator-name = "lis3_reg";
118 regulator-boot-on;
119 };
120
121 matrix_keypad: matrix_keypad@0 {
122 compatible = "gpio-matrix-keypad";
123 debounce-delay-ms = <5>;
124 col-scan-delay-us = <2>;
125
126 row-gpios = <&gpio2 25 0 /* Bank1, pin25 */
127 &gpio2 26 0 /* Bank1, pin26 */
128 &gpio2 27 0>; /* Bank1, pin27 */
129
130 col-gpios = <&gpio2 21 0 /* Bank1, pin21 */
131 &gpio2 22 0>; /* Bank1, pin22 */
132
133 linux,keymap = <0x0000008b /* MENU */
134 0x0100009e /* BACK */
135 0x02000069 /* LEFT */
136 0x0001006a /* RIGHT */
137 0x0101001c /* ENTER */
138 0x0201006c>; /* DOWN */
139 };
140
141 gpio_keys: volume_keys@0 {
142 compatible = "gpio-keys";
143 #address-cells = <1>;
144 #size-cells = <0>;
145 autorepeat;
146
147 switch@9 {
148 label = "volume-up";
149 linux,code = <115>;
150 gpios = <&gpio1 2 1>;
151 gpio-key,wakeup;
152 };
153
154 switch@10 {
155 label = "volume-down";
156 linux,code = <114>;
157 gpios = <&gpio1 3 1>;
158 gpio-key,wakeup;
159 };
160 };
161};
162
163/include/ "tps65910.dtsi"
164
165&tps {
166 vcc1-supply = <&vbat>;
167 vcc2-supply = <&vbat>;
168 vcc3-supply = <&vbat>;
169 vcc4-supply = <&vbat>;
170 vcc5-supply = <&vbat>;
171 vcc6-supply = <&vbat>;
172 vcc7-supply = <&vbat>;
173 vccio-supply = <&vbat>;
174
175 regulators {
176 vrtc_reg: regulator@0 {
177 regulator-always-on;
178 };
179
180 vio_reg: regulator@1 {
181 regulator-always-on;
182 };
183
184 vdd1_reg: regulator@2 {
185 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
186 regulator-name = "vdd_mpu";
187 regulator-min-microvolt = <912500>;
188 regulator-max-microvolt = <1312500>;
189 regulator-boot-on;
190 regulator-always-on;
191 };
192
193 vdd2_reg: regulator@3 {
194 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
195 regulator-name = "vdd_core";
196 regulator-min-microvolt = <912500>;
197 regulator-max-microvolt = <1150000>;
198 regulator-boot-on;
199 regulator-always-on;
200 };
201
202 vdd3_reg: regulator@4 {
203 regulator-always-on;
204 };
205
206 vdig1_reg: regulator@5 {
207 regulator-always-on;
208 };
209
210 vdig2_reg: regulator@6 {
211 regulator-always-on;
212 };
213
214 vpll_reg: regulator@7 {
215 regulator-always-on;
216 };
217
218 vdac_reg: regulator@8 {
219 regulator-always-on;
220 };
221
222 vaux1_reg: regulator@9 {
223 regulator-always-on;
224 };
225
226 vaux2_reg: regulator@10 {
227 regulator-always-on;
228 };
229
230 vaux33_reg: regulator@11 {
231 regulator-always-on;
232 };
233
234 vmmc_reg: regulator@12 {
235 regulator-always-on;
236 };
237 };
238};
239
240&cpsw_emac0 {
241 phy_id = <&davinci_mdio>, <0>;
242};
243
244&cpsw_emac1 {
245 phy_id = <&davinci_mdio>, <1>;
246};
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
deleted file mode 100644
index f5a6162a4ff..00000000000
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ /dev/null
@@ -1,250 +0,0 @@
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * AM335x Starter Kit
11 * http://www.ti.com/tool/tmdssk3358
12 */
13
14/dts-v1/;
15
16/include/ "am33xx.dtsi"
17
18/ {
19 model = "TI AM335x EVM-SK";
20 compatible = "ti,am335x-evmsk", "ti,am33xx";
21
22 cpus {
23 cpu@0 {
24 cpu0-supply = <&vdd1_reg>;
25 };
26 };
27
28 memory {
29 device_type = "memory";
30 reg = <0x80000000 0x10000000>; /* 256 MB */
31 };
32
33 am33xx_pinmux: pinmux@44e10800 {
34 pinctrl-names = "default";
35 pinctrl-0 = <&user_leds_s0 &gpio_keys_s0>;
36
37 user_leds_s0: user_leds_s0 {
38 pinctrl-single,pins = <
39 0x10 0x7 /* gpmc_ad4.gpio1_4, OUTPUT | MODE7 */
40 0x14 0x7 /* gpmc_ad5.gpio1_5, OUTPUT | MODE7 */
41 0x18 0x7 /* gpmc_ad6.gpio1_6, OUTPUT | MODE7 */
42 0x1c 0x7 /* gpmc_ad7.gpio1_7, OUTPUT | MODE7 */
43 >;
44 };
45
46 gpio_keys_s0: gpio_keys_s0 {
47 pinctrl-single,pins = <
48 0x94 0x27 /* gpmc_oen_ren.gpio2_3, INPUT | MODE7 */
49 0x90 0x27 /* gpmc_advn_ale.gpio2_2, INPUT | MODE7 */
50 0x70 0x27 /* gpmc_wait0.gpio0_30, INPUT | MODE7 */
51 0x9c 0x27 /* gpmc_ben0_cle.gpio2_5, INPUT | MODE7 */
52 >;
53 };
54 };
55
56 ocp {
57 uart1: serial@44e09000 {
58 status = "okay";
59 };
60
61 i2c1: i2c@44e0b000 {
62 status = "okay";
63 clock-frequency = <400000>;
64
65 tps: tps@2d {
66 reg = <0x2d>;
67 };
68
69 lis331dlh: lis331dlh@18 {
70 compatible = "st,lis331dlh", "st,lis3lv02d";
71 reg = <0x18>;
72 Vdd-supply = <&lis3_reg>;
73 Vdd_IO-supply = <&lis3_reg>;
74
75 st,click-single-x;
76 st,click-single-y;
77 st,click-single-z;
78 st,click-thresh-x = <10>;
79 st,click-thresh-y = <10>;
80 st,click-thresh-z = <10>;
81 st,irq1-click;
82 st,irq2-click;
83 st,wakeup-x-lo;
84 st,wakeup-x-hi;
85 st,wakeup-y-lo;
86 st,wakeup-y-hi;
87 st,wakeup-z-lo;
88 st,wakeup-z-hi;
89 st,min-limit-x = <120>;
90 st,min-limit-y = <120>;
91 st,min-limit-z = <140>;
92 st,max-limit-x = <550>;
93 st,max-limit-y = <550>;
94 st,max-limit-z = <750>;
95 };
96 };
97 };
98
99 vbat: fixedregulator@0 {
100 compatible = "regulator-fixed";
101 regulator-name = "vbat";
102 regulator-min-microvolt = <5000000>;
103 regulator-max-microvolt = <5000000>;
104 regulator-boot-on;
105 };
106
107 lis3_reg: fixedregulator@1 {
108 compatible = "regulator-fixed";
109 regulator-name = "lis3_reg";
110 regulator-boot-on;
111 };
112
113 leds {
114 compatible = "gpio-leds";
115
116 led@1 {
117 label = "evmsk:green:usr0";
118 gpios = <&gpio2 4 0>;
119 default-state = "off";
120 };
121
122 led@2 {
123 label = "evmsk:green:usr1";
124 gpios = <&gpio2 5 0>;
125 default-state = "off";
126 };
127
128 led@3 {
129 label = "evmsk:green:mmc0";
130 gpios = <&gpio2 6 0>;
131 linux,default-trigger = "mmc0";
132 default-state = "off";
133 };
134
135 led@4 {
136 label = "evmsk:green:heartbeat";
137 gpios = <&gpio2 7 0>;
138 linux,default-trigger = "heartbeat";
139 default-state = "off";
140 };
141 };
142
143 gpio_buttons: gpio_buttons@0 {
144 compatible = "gpio-keys";
145 #address-cells = <1>;
146 #size-cells = <0>;
147
148 switch@1 {
149 label = "button0";
150 linux,code = <0x100>;
151 gpios = <&gpio3 3 0>;
152 };
153
154 switch@2 {
155 label = "button1";
156 linux,code = <0x101>;
157 gpios = <&gpio3 2 0>;
158 };
159
160 switch@3 {
161 label = "button2";
162 linux,code = <0x102>;
163 gpios = <&gpio1 30 0>;
164 gpio-key,wakeup;
165 };
166
167 switch@4 {
168 label = "button3";
169 linux,code = <0x103>;
170 gpios = <&gpio3 5 0>;
171 };
172 };
173};
174
175/include/ "tps65910.dtsi"
176
177&tps {
178 vcc1-supply = <&vbat>;
179 vcc2-supply = <&vbat>;
180 vcc3-supply = <&vbat>;
181 vcc4-supply = <&vbat>;
182 vcc5-supply = <&vbat>;
183 vcc6-supply = <&vbat>;
184 vcc7-supply = <&vbat>;
185 vccio-supply = <&vbat>;
186
187 regulators {
188 vrtc_reg: regulator@0 {
189 regulator-always-on;
190 };
191
192 vio_reg: regulator@1 {
193 regulator-always-on;
194 };
195
196 vdd1_reg: regulator@2 {
197 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
198 regulator-name = "vdd_mpu";
199 regulator-min-microvolt = <912500>;
200 regulator-max-microvolt = <1312500>;
201 regulator-boot-on;
202 regulator-always-on;
203 };
204
205 vdd2_reg: regulator@3 {
206 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
207 regulator-name = "vdd_core";
208 regulator-min-microvolt = <912500>;
209 regulator-max-microvolt = <1150000>;
210 regulator-boot-on;
211 regulator-always-on;
212 };
213
214 vdd3_reg: regulator@4 {
215 regulator-always-on;
216 };
217
218 vdig1_reg: regulator@5 {
219 regulator-always-on;
220 };
221
222 vdig2_reg: regulator@6 {
223 regulator-always-on;
224 };
225
226 vpll_reg: regulator@7 {
227 regulator-always-on;
228 };
229
230 vdac_reg: regulator@8 {
231 regulator-always-on;
232 };
233
234 vaux1_reg: regulator@9 {
235 regulator-always-on;
236 };
237
238 vaux2_reg: regulator@10 {
239 regulator-always-on;
240 };
241
242 vaux33_reg: regulator@11 {
243 regulator-always-on;
244 };
245
246 vmmc_reg: regulator@12 {
247 regulator-always-on;
248 };
249 };
250};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
deleted file mode 100644
index c2f14e875eb..00000000000
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ /dev/null
@@ -1,389 +0,0 @@
1/*
2 * Device Tree Source for AM33XX SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "skeleton.dtsi"
12
13/ {
14 compatible = "ti,am33xx";
15 interrupt-parent = <&intc>;
16
17 aliases {
18 serial0 = &uart1;
19 serial1 = &uart2;
20 serial2 = &uart3;
21 serial3 = &uart4;
22 serial4 = &uart5;
23 serial5 = &uart6;
24 };
25
26 cpus {
27 cpu@0 {
28 compatible = "arm,cortex-a8";
29
30 /*
31 * To consider voltage drop between PMIC and SoC,
32 * tolerance value is reduced to 2% from 4% and
33 * voltage value is increased as a precaution.
34 */
35 operating-points = <
36 /* kHz uV */
37 720000 1285000
38 600000 1225000
39 500000 1125000
40 275000 1125000
41 >;
42 voltage-tolerance = <2>; /* 2 percentage */
43 clock-latency = <300000>; /* From omap-cpufreq driver */
44 };
45 };
46
47 /*
48 * The soc node represents the soc top level view. It is uses for IPs
49 * that are not memory mapped in the MPU view or for the MPU itself.
50 */
51 soc {
52 compatible = "ti,omap-infra";
53 mpu {
54 compatible = "ti,omap3-mpu";
55 ti,hwmods = "mpu";
56 };
57 };
58
59 am33xx_pinmux: pinmux@44e10800 {
60 compatible = "pinctrl-single";
61 reg = <0x44e10800 0x0238>;
62 #address-cells = <1>;
63 #size-cells = <0>;
64 pinctrl-single,register-width = <32>;
65 pinctrl-single,function-mask = <0x7f>;
66 };
67
68 /*
69 * XXX: Use a flat representation of the AM33XX interconnect.
70 * The real AM33XX interconnect network is quite complex.Since
71 * that will not bring real advantage to represent that in DT
72 * for the moment, just use a fake OCP bus entry to represent
73 * the whole bus hierarchy.
74 */
75 ocp {
76 compatible = "simple-bus";
77 #address-cells = <1>;
78 #size-cells = <1>;
79 ranges;
80 ti,hwmods = "l3_main";
81
82 intc: interrupt-controller@48200000 {
83 compatible = "ti,omap2-intc";
84 interrupt-controller;
85 #interrupt-cells = <1>;
86 ti,intc-size = <128>;
87 reg = <0x48200000 0x1000>;
88 };
89
90 gpio1: gpio@44e07000 {
91 compatible = "ti,omap4-gpio";
92 ti,hwmods = "gpio1";
93 gpio-controller;
94 #gpio-cells = <2>;
95 interrupt-controller;
96 #interrupt-cells = <1>;
97 reg = <0x44e07000 0x1000>;
98 interrupts = <96>;
99 };
100
101 gpio2: gpio@4804c000 {
102 compatible = "ti,omap4-gpio";
103 ti,hwmods = "gpio2";
104 gpio-controller;
105 #gpio-cells = <2>;
106 interrupt-controller;
107 #interrupt-cells = <1>;
108 reg = <0x4804c000 0x1000>;
109 interrupts = <98>;
110 };
111
112 gpio3: gpio@481ac000 {
113 compatible = "ti,omap4-gpio";
114 ti,hwmods = "gpio3";
115 gpio-controller;
116 #gpio-cells = <2>;
117 interrupt-controller;
118 #interrupt-cells = <1>;
119 reg = <0x481ac000 0x1000>;
120 interrupts = <32>;
121 };
122
123 gpio4: gpio@481ae000 {
124 compatible = "ti,omap4-gpio";
125 ti,hwmods = "gpio4";
126 gpio-controller;
127 #gpio-cells = <2>;
128 interrupt-controller;
129 #interrupt-cells = <1>;
130 reg = <0x481ae000 0x1000>;
131 interrupts = <62>;
132 };
133
134 uart1: serial@44e09000 {
135 compatible = "ti,omap3-uart";
136 ti,hwmods = "uart1";
137 clock-frequency = <48000000>;
138 reg = <0x44e09000 0x2000>;
139 interrupts = <72>;
140 status = "disabled";
141 };
142
143 uart2: serial@48022000 {
144 compatible = "ti,omap3-uart";
145 ti,hwmods = "uart2";
146 clock-frequency = <48000000>;
147 reg = <0x48022000 0x2000>;
148 interrupts = <73>;
149 status = "disabled";
150 };
151
152 uart3: serial@48024000 {
153 compatible = "ti,omap3-uart";
154 ti,hwmods = "uart3";
155 clock-frequency = <48000000>;
156 reg = <0x48024000 0x2000>;
157 interrupts = <74>;
158 status = "disabled";
159 };
160
161 uart4: serial@481a6000 {
162 compatible = "ti,omap3-uart";
163 ti,hwmods = "uart4";
164 clock-frequency = <48000000>;
165 reg = <0x481a6000 0x2000>;
166 interrupts = <44>;
167 status = "disabled";
168 };
169
170 uart5: serial@481a8000 {
171 compatible = "ti,omap3-uart";
172 ti,hwmods = "uart5";
173 clock-frequency = <48000000>;
174 reg = <0x481a8000 0x2000>;
175 interrupts = <45>;
176 status = "disabled";
177 };
178
179 uart6: serial@481aa000 {
180 compatible = "ti,omap3-uart";
181 ti,hwmods = "uart6";
182 clock-frequency = <48000000>;
183 reg = <0x481aa000 0x2000>;
184 interrupts = <46>;
185 status = "disabled";
186 };
187
188 i2c1: i2c@44e0b000 {
189 compatible = "ti,omap4-i2c";
190 #address-cells = <1>;
191 #size-cells = <0>;
192 ti,hwmods = "i2c1";
193 reg = <0x44e0b000 0x1000>;
194 interrupts = <70>;
195 status = "disabled";
196 };
197
198 i2c2: i2c@4802a000 {
199 compatible = "ti,omap4-i2c";
200 #address-cells = <1>;
201 #size-cells = <0>;
202 ti,hwmods = "i2c2";
203 reg = <0x4802a000 0x1000>;
204 interrupts = <71>;
205 status = "disabled";
206 };
207
208 i2c3: i2c@4819c000 {
209 compatible = "ti,omap4-i2c";
210 #address-cells = <1>;
211 #size-cells = <0>;
212 ti,hwmods = "i2c3";
213 reg = <0x4819c000 0x1000>;
214 interrupts = <30>;
215 status = "disabled";
216 };
217
218 wdt2: wdt@44e35000 {
219 compatible = "ti,omap3-wdt";
220 ti,hwmods = "wd_timer2";
221 reg = <0x44e35000 0x1000>;
222 interrupts = <91>;
223 };
224
225 dcan0: d_can@481cc000 {
226 compatible = "bosch,d_can";
227 ti,hwmods = "d_can0";
228 reg = <0x481cc000 0x2000>;
229 interrupts = <52>;
230 status = "disabled";
231 };
232
233 dcan1: d_can@481d0000 {
234 compatible = "bosch,d_can";
235 ti,hwmods = "d_can1";
236 reg = <0x481d0000 0x2000>;
237 interrupts = <55>;
238 status = "disabled";
239 };
240
241 timer1: timer@44e31000 {
242 compatible = "ti,omap2-timer";
243 reg = <0x44e31000 0x400>;
244 interrupts = <67>;
245 ti,hwmods = "timer1";
246 ti,timer-alwon;
247 };
248
249 timer2: timer@48040000 {
250 compatible = "ti,omap2-timer";
251 reg = <0x48040000 0x400>;
252 interrupts = <68>;
253 ti,hwmods = "timer2";
254 };
255
256 timer3: timer@48042000 {
257 compatible = "ti,omap2-timer";
258 reg = <0x48042000 0x400>;
259 interrupts = <69>;
260 ti,hwmods = "timer3";
261 };
262
263 timer4: timer@48044000 {
264 compatible = "ti,omap2-timer";
265 reg = <0x48044000 0x400>;
266 interrupts = <92>;
267 ti,hwmods = "timer4";
268 ti,timer-pwm;
269 };
270
271 timer5: timer@48046000 {
272 compatible = "ti,omap2-timer";
273 reg = <0x48046000 0x400>;
274 interrupts = <93>;
275 ti,hwmods = "timer5";
276 ti,timer-pwm;
277 };
278
279 timer6: timer@48048000 {
280 compatible = "ti,omap2-timer";
281 reg = <0x48048000 0x400>;
282 interrupts = <94>;
283 ti,hwmods = "timer6";
284 ti,timer-pwm;
285 };
286
287 timer7: timer@4804a000 {
288 compatible = "ti,omap2-timer";
289 reg = <0x4804a000 0x400>;
290 interrupts = <95>;
291 ti,hwmods = "timer7";
292 ti,timer-pwm;
293 };
294
295 rtc@44e3e000 {
296 compatible = "ti,da830-rtc";
297 reg = <0x44e3e000 0x1000>;
298 interrupts = <75
299 76>;
300 ti,hwmods = "rtc";
301 };
302
303 spi0: spi@48030000 {
304 compatible = "ti,omap4-mcspi";
305 #address-cells = <1>;
306 #size-cells = <0>;
307 reg = <0x48030000 0x400>;
308 interrupt = <65>;
309 ti,spi-num-cs = <2>;
310 ti,hwmods = "spi0";
311 status = "disabled";
312 };
313
314 spi1: spi@481a0000 {
315 compatible = "ti,omap4-mcspi";
316 #address-cells = <1>;
317 #size-cells = <0>;
318 reg = <0x481a0000 0x400>;
319 interrupt = <125>;
320 ti,spi-num-cs = <2>;
321 ti,hwmods = "spi1";
322 status = "disabled";
323 };
324
325 usb@47400000 {
326 compatible = "ti,musb-am33xx";
327 reg = <0x47400000 0x1000 /* usbss */
328 0x47401000 0x800 /* musb instance 0 */
329 0x47401800 0x800>; /* musb instance 1 */
330 interrupts = <17 /* usbss */
331 18 /* musb instance 0 */
332 19>; /* musb instance 1 */
333 multipoint = <1>;
334 num-eps = <16>;
335 ram-bits = <12>;
336 port0-mode = <3>;
337 port1-mode = <3>;
338 power = <250>;
339 ti,hwmods = "usb_otg_hs";
340 };
341
342 mac: ethernet@4a100000 {
343 compatible = "ti,cpsw";
344 ti,hwmods = "cpgmac0";
345 cpdma_channels = <8>;
346 ale_entries = <1024>;
347 bd_ram_size = <0x2000>;
348 no_bd_ram = <0>;
349 rx_descs = <64>;
350 mac_control = <0x20>;
351 slaves = <2>;
352 cpts_active_slave = <0>;
353 cpts_clock_mult = <0x80000000>;
354 cpts_clock_shift = <29>;
355 reg = <0x4a100000 0x800
356 0x4a101200 0x100>;
357 #address-cells = <1>;
358 #size-cells = <1>;
359 interrupt-parent = <&intc>;
360 /*
361 * c0_rx_thresh_pend
362 * c0_rx_pend
363 * c0_tx_pend
364 * c0_misc_pend
365 */
366 interrupts = <40 41 42 43>;
367 ranges;
368
369 davinci_mdio: mdio@4a101000 {
370 compatible = "ti,davinci_mdio";
371 #address-cells = <1>;
372 #size-cells = <0>;
373 ti,hwmods = "davinci_mdio";
374 bus_freq = <1000000>;
375 reg = <0x4a101000 0x100>;
376 };
377
378 cpsw_emac0: slave@4a100200 {
379 /* Filled in by U-Boot */
380 mac-address = [ 00 00 00 00 00 00 ];
381 };
382
383 cpsw_emac1: slave@4a100300 {
384 /* Filled in by U-Boot */
385 mac-address = [ 00 00 00 00 00 00 ];
386 };
387 };
388 };
389};
diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/am3517-evm.dts
deleted file mode 100644
index 474f760ecad..00000000000
--- a/arch/arm/boot/dts/am3517-evm.dts
+++ /dev/null
@@ -1,32 +0,0 @@
1/*
2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10/include/ "omap3.dtsi"
11
12/ {
13 model = "TI AM3517 EVM (AM3517/05)";
14 compatible = "ti,am3517-evm", "ti,omap3";
15
16 memory {
17 device_type = "memory";
18 reg = <0x80000000 0x10000000>; /* 256 MB */
19 };
20};
21
22&i2c1 {
23 clock-frequency = <400000>;
24};
25
26&i2c2 {
27 clock-frequency = <400000>;
28};
29
30&i2c3 {
31 clock-frequency = <400000>;
32};
diff --git a/arch/arm/boot/dts/am3517_mt_ventoux.dts b/arch/arm/boot/dts/am3517_mt_ventoux.dts
deleted file mode 100644
index 5eb26d7d9b4..00000000000
--- a/arch/arm/boot/dts/am3517_mt_ventoux.dts
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * Copyright (C) 2011 Ilya Yanok, EmCraft Systems
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10/include/ "omap3.dtsi"
11
12/ {
13 model = "TeeJet Mt.Ventoux";
14 compatible = "teejet,mt_ventoux", "ti,omap3";
15
16 memory {
17 device_type = "memory";
18 reg = <0x80000000 0x10000000>; /* 256 MB */
19 };
20
21 /* AM35xx doesn't have IVA */
22 soc {
23 iva {
24 status = "disabled";
25 };
26 };
27};
diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/animeo_ip.dts
deleted file mode 100644
index 74d92cd29d8..00000000000
--- a/arch/arm/boot/dts/animeo_ip.dts
+++ /dev/null
@@ -1,178 +0,0 @@
1/*
2 * animeo_ip.dts - Device Tree file for Somfy Animeo IP Boards
3 *
4 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2 only.
7 */
8
9/dts-v1/;
10/include/ "at91sam9260.dtsi"
11
12/ {
13 model = "Somfy Animeo IP";
14 compatible = "somfy,animeo-ip", "atmel,at91sam9260", "atmel,at91sam9";
15
16 aliases {
17 serial0 = &usart1;
18 serial1 = &usart2;
19 serial2 = &usart0;
20 serial3 = &dbgu;
21 serial4 = &usart3;
22 serial5 = &uart0;
23 serial6 = &uart1;
24 };
25
26 chosen {
27 linux,stdout-path = &usart2;
28 };
29
30 memory {
31 reg = <0x20000000 0x4000000>;
32 };
33
34 clocks {
35 #address-cells = <1>;
36 #size-cells = <1>;
37 ranges;
38
39 main_clock: clock@0 {
40 compatible = "atmel,osc", "fixed-clock";
41 clock-frequency = <18432000>;
42 };
43 };
44
45 ahb {
46 apb {
47 usart0: serial@fffb0000 {
48 pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts>;
49 linux,rs485-enabled-at-boot-time;
50 status = "okay";
51 };
52
53 usart1: serial@fffb4000 {
54 pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts>;
55 linux,rs485-enabled-at-boot-time;
56 status = "okay";
57 };
58
59 usart2: serial@fffb8000 {
60 pinctrl-0 = <&pinctrl_usart2>;
61 status = "okay";
62 };
63
64 macb0: ethernet@fffc4000 {
65 pinctrl-0 = <&pinctrl_macb_rmii &pinctrl_macb_rmii_mii>;
66 phy-mode = "mii";
67 status = "okay";
68 };
69
70 mmc0: mmc@fffa8000 {
71 pinctrl-0 = <&pinctrl_mmc0_clk
72 &pinctrl_mmc0_slot1_cmd_dat0
73 &pinctrl_mmc0_slot1_dat1_3>;
74 status = "okay";
75
76 slot@1 {
77 reg = <1>;
78 bus-width = <4>;
79 };
80 };
81 };
82
83 nand0: nand@40000000 {
84 nand-bus-width = <8>;
85 nand-ecc-mode = "soft";
86 nand-on-flash-bbt;
87 status = "okay";
88
89 at91bootstrap@0 {
90 label = "at91bootstrap";
91 reg = <0x0 0x8000>;
92 };
93
94 barebox@8000 {
95 label = "barebox";
96 reg = <0x8000 0x40000>;
97 };
98
99 bareboxenv@48000 {
100 label = "bareboxenv";
101 reg = <0x48000 0x8000>;
102 };
103
104 user_block@0x50000 {
105 label = "user_block";
106 reg = <0x50000 0xb0000>;
107 };
108
109 kernel@100000 {
110 label = "kernel";
111 reg = <0x100000 0x1b0000>;
112 };
113
114 root@2b0000 {
115 label = "root";
116 reg = <0x2b0000 0x1D50000>;
117 };
118 };
119
120 usb0: ohci@00500000 {
121 num-ports = <2>;
122 atmel,vbus-gpio = <&pioB 15 1>;
123 status = "okay";
124 };
125 };
126
127 leds {
128 compatible = "gpio-leds";
129
130 power_green {
131 label = "power_green";
132 gpios = <&pioC 17 0>;
133 linux,default-trigger = "heartbeat";
134 };
135
136 power_red {
137 label = "power_red";
138 gpios = <&pioA 2 0>;
139 };
140
141 tx_green {
142 label = "tx_green";
143 gpios = <&pioC 19 0>;
144 };
145
146 tx_red {
147 label = "tx_red";
148 gpios = <&pioC 18 0>;
149 };
150 };
151
152 gpio_keys {
153 compatible = "gpio-keys";
154 #address-cells = <1>;
155 #size-cells = <0>;
156
157 keyswitch_in {
158 label = "keyswitch_in";
159 gpios = <&pioB 1 0>;
160 linux,code = <28>;
161 gpio-key,wakeup;
162 };
163
164 error_in {
165 label = "error_in";
166 gpios = <&pioB 2 0>;
167 linux,code = <29>;
168 gpio-key,wakeup;
169 };
170
171 btn {
172 label = "btn";
173 gpios = <&pioC 23 0>;
174 linux,code = <31>;
175 gpio-key,wakeup;
176 };
177 };
178};
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
deleted file mode 100644
index 00044026ef1..00000000000
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * Device Tree file for Marvell Armada 370 evaluation board
3 * (DB-88F6710-BP-DDR3)
4 *
5 * Copyright (C) 2012 Marvell
6 *
7 * Lior Amsalem <alior@marvell.com>
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
16/dts-v1/;
17/include/ "armada-370.dtsi"
18
19/ {
20 model = "Marvell Armada 370 Evaluation Board";
21 compatible = "marvell,a370-db", "marvell,armada370", "marvell,armada-370-xp";
22
23 chosen {
24 bootargs = "console=ttyS0,115200 earlyprintk";
25 };
26
27 memory {
28 device_type = "memory";
29 reg = <0x00000000 0x20000000>; /* 512 MB */
30 };
31
32 soc {
33 serial@d0012000 {
34 clock-frequency = <200000000>;
35 status = "okay";
36 };
37 sata@d00a0000 {
38 nr-ports = <2>;
39 status = "okay";
40 };
41
42 mdio {
43 phy0: ethernet-phy@0 {
44 reg = <0>;
45 };
46
47 phy1: ethernet-phy@1 {
48 reg = <1>;
49 };
50 };
51
52 ethernet@d0070000 {
53 status = "okay";
54 phy = <&phy0>;
55 phy-mode = "rgmii-id";
56 };
57 ethernet@d0074000 {
58 status = "okay";
59 phy = <&phy1>;
60 phy-mode = "rgmii-id";
61 };
62 };
63};
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
deleted file mode 100644
index 3b407133659..00000000000
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ /dev/null
@@ -1,56 +0,0 @@
1/*
2 * Device Tree file for Globalscale Mirabox
3 *
4 * Gregory CLEMENT <gregory.clement@free-electrons.com>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11/dts-v1/;
12/include/ "armada-370.dtsi"
13
14/ {
15 model = "Globalscale Mirabox";
16 compatible = "globalscale,mirabox", "marvell,armada370", "marvell,armada-370-xp";
17
18 chosen {
19 bootargs = "console=ttyS0,115200 earlyprintk";
20 };
21
22 memory {
23 device_type = "memory";
24 reg = <0x00000000 0x20000000>; /* 512 MB */
25 };
26
27 soc {
28 serial@d0012000 {
29 clock-frequency = <200000000>;
30 status = "okay";
31 };
32 timer@d0020300 {
33 clock-frequency = <600000000>;
34 status = "okay";
35 };
36 mdio {
37 phy0: ethernet-phy@0 {
38 reg = <0>;
39 };
40
41 phy1: ethernet-phy@1 {
42 reg = <1>;
43 };
44 };
45 ethernet@d0070000 {
46 status = "okay";
47 phy = <&phy0>;
48 phy-mode = "rgmii-id";
49 };
50 ethernet@d0074000 {
51 status = "okay";
52 phy = <&phy1>;
53 phy-mode = "rgmii-id";
54 };
55 };
56};
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
deleted file mode 100644
index 4c0abe85405..00000000000
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ /dev/null
@@ -1,136 +0,0 @@
1/*
2 * Device Tree Include file for Marvell Armada 370 and Armada XP SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 *
15 * This file contains the definitions that are common to the Armada
16 * 370 and Armada XP SoC.
17 */
18
19/include/ "skeleton.dtsi"
20
21/ {
22 model = "Marvell Armada 370 and XP SoC";
23 compatible = "marvell,armada-370-xp";
24
25 cpus {
26 cpu@0 {
27 compatible = "marvell,sheeva-v7";
28 };
29 };
30
31 mpic: interrupt-controller@d0020000 {
32 compatible = "marvell,mpic";
33 #interrupt-cells = <1>;
34 #address-cells = <1>;
35 #size-cells = <1>;
36 interrupt-controller;
37 };
38
39 coherency-fabric@d0020200 {
40 compatible = "marvell,coherency-fabric";
41 reg = <0xd0020200 0xb0>,
42 <0xd0021810 0x1c>;
43 };
44
45 soc {
46 #address-cells = <1>;
47 #size-cells = <1>;
48 compatible = "simple-bus";
49 interrupt-parent = <&mpic>;
50 ranges;
51
52 serial@d0012000 {
53 compatible = "snps,dw-apb-uart";
54 reg = <0xd0012000 0x100>;
55 reg-shift = <2>;
56 interrupts = <41>;
57 reg-io-width = <4>;
58 status = "disabled";
59 };
60 serial@d0012100 {
61 compatible = "snps,dw-apb-uart";
62 reg = <0xd0012100 0x100>;
63 reg-shift = <2>;
64 interrupts = <42>;
65 reg-io-width = <4>;
66 status = "disabled";
67 };
68
69 timer@d0020300 {
70 compatible = "marvell,armada-370-xp-timer";
71 reg = <0xd0020300 0x30>;
72 interrupts = <37>, <38>, <39>, <40>;
73 clocks = <&coreclk 2>;
74 };
75
76 addr-decoding@d0020000 {
77 compatible = "marvell,armada-addr-decoding-controller";
78 reg = <0xd0020000 0x258>;
79 };
80
81 sata@d00a0000 {
82 compatible = "marvell,orion-sata";
83 reg = <0xd00a0000 0x2400>;
84 interrupts = <55>;
85 clocks = <&gateclk 15>, <&gateclk 30>;
86 clock-names = "0", "1";
87 status = "disabled";
88 };
89
90 mdio {
91 #address-cells = <1>;
92 #size-cells = <0>;
93 compatible = "marvell,orion-mdio";
94 reg = <0xd0072004 0x4>;
95 };
96
97 ethernet@d0070000 {
98 compatible = "marvell,armada-370-neta";
99 reg = <0xd0070000 0x2500>;
100 interrupts = <8>;
101 clocks = <&gateclk 4>;
102 status = "disabled";
103 };
104
105 ethernet@d0074000 {
106 compatible = "marvell,armada-370-neta";
107 reg = <0xd0074000 0x2500>;
108 interrupts = <10>;
109 clocks = <&gateclk 3>;
110 status = "disabled";
111 };
112
113 i2c0: i2c@d0011000 {
114 compatible = "marvell,mv64xxx-i2c";
115 reg = <0xd0011000 0x20>;
116 #address-cells = <1>;
117 #size-cells = <0>;
118 interrupts = <31>;
119 timeout-ms = <1000>;
120 clocks = <&coreclk 0>;
121 status = "disabled";
122 };
123
124 i2c1: i2c@d0011100 {
125 compatible = "marvell,mv64xxx-i2c";
126 reg = <0xd0011100 0x20>;
127 #address-cells = <1>;
128 #size-cells = <0>;
129 interrupts = <32>;
130 timeout-ms = <1000>;
131 clocks = <&coreclk 0>;
132 status = "disabled";
133 };
134 };
135};
136
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
deleted file mode 100644
index 636cf7d4009..00000000000
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ /dev/null
@@ -1,136 +0,0 @@
1/*
2 * Device Tree Include file for Marvell Armada 370 family SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 *
14 * Contains definitions specific to the Armada 370 SoC that are not
15 * common to all Armada SoCs.
16 */
17
18/include/ "armada-370-xp.dtsi"
19
20/ {
21 model = "Marvell Armada 370 family SoC";
22 compatible = "marvell,armada370", "marvell,armada-370-xp";
23 L2: l2-cache {
24 compatible = "marvell,aurora-outer-cache";
25 reg = <0xd0008000 0x1000>;
26 cache-id-part = <0x100>;
27 wt-override;
28 };
29
30 aliases {
31 gpio0 = &gpio0;
32 gpio1 = &gpio1;
33 gpio2 = &gpio2;
34 };
35
36 mpic: interrupt-controller@d0020000 {
37 reg = <0xd0020a00 0x1d0>,
38 <0xd0021870 0x58>;
39 };
40
41 soc {
42 system-controller@d0018200 {
43 compatible = "marvell,armada-370-xp-system-controller";
44 reg = <0xd0018200 0x100>;
45 };
46
47 pinctrl {
48 compatible = "marvell,mv88f6710-pinctrl";
49 reg = <0xd0018000 0x38>;
50 };
51
52 gpio0: gpio@d0018100 {
53 compatible = "marvell,orion-gpio";
54 reg = <0xd0018100 0x40>;
55 ngpios = <32>;
56 gpio-controller;
57 #gpio-cells = <2>;
58 interrupt-controller;
59 #interrupts-cells = <2>;
60 interrupts = <82>, <83>, <84>, <85>;
61 };
62
63 gpio1: gpio@d0018140 {
64 compatible = "marvell,orion-gpio";
65 reg = <0xd0018140 0x40>;
66 ngpios = <32>;
67 gpio-controller;
68 #gpio-cells = <2>;
69 interrupt-controller;
70 #interrupts-cells = <2>;
71 interrupts = <87>, <88>, <89>, <90>;
72 };
73
74 gpio2: gpio@d0018180 {
75 compatible = "marvell,orion-gpio";
76 reg = <0xd0018180 0x40>;
77 ngpios = <2>;
78 gpio-controller;
79 #gpio-cells = <2>;
80 interrupt-controller;
81 #interrupts-cells = <2>;
82 interrupts = <91>;
83 };
84
85 coreclk: mvebu-sar@d0018230 {
86 compatible = "marvell,armada-370-core-clock";
87 reg = <0xd0018230 0x08>;
88 #clock-cells = <1>;
89 };
90
91 gateclk: clock-gating-control@d0018220 {
92 compatible = "marvell,armada-370-gating-clock";
93 reg = <0xd0018220 0x4>;
94 clocks = <&coreclk 0>;
95 #clock-cells = <1>;
96 };
97
98 xor@d0060800 {
99 compatible = "marvell,orion-xor";
100 reg = <0xd0060800 0x100
101 0xd0060A00 0x100>;
102 status = "okay";
103
104 xor00 {
105 interrupts = <51>;
106 dmacap,memcpy;
107 dmacap,xor;
108 };
109 xor01 {
110 interrupts = <52>;
111 dmacap,memcpy;
112 dmacap,xor;
113 dmacap,memset;
114 };
115 };
116
117 xor@d0060900 {
118 compatible = "marvell,orion-xor";
119 reg = <0xd0060900 0x100
120 0xd0060b00 0x100>;
121 status = "okay";
122
123 xor10 {
124 interrupts = <94>;
125 dmacap,memcpy;
126 dmacap,xor;
127 };
128 xor11 {
129 interrupts = <95>;
130 dmacap,memcpy;
131 dmacap,xor;
132 dmacap,memset;
133 };
134 };
135 };
136};
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
deleted file mode 100644
index 8e53b25b550..00000000000
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ /dev/null
@@ -1,94 +0,0 @@
1/*
2 * Device Tree file for Marvell Armada XP evaluation board
3 * (DB-78460-BP)
4 *
5 * Copyright (C) 2012 Marvell
6 *
7 * Lior Amsalem <alior@marvell.com>
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
16/dts-v1/;
17/include/ "armada-xp-mv78460.dtsi"
18
19/ {
20 model = "Marvell Armada XP Evaluation Board";
21 compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
22
23 chosen {
24 bootargs = "console=ttyS0,115200 earlyprintk";
25 };
26
27 memory {
28 device_type = "memory";
29 reg = <0x00000000 0x80000000>; /* 2 GB */
30 };
31
32 soc {
33 serial@d0012000 {
34 clock-frequency = <250000000>;
35 status = "okay";
36 };
37 serial@d0012100 {
38 clock-frequency = <250000000>;
39 status = "okay";
40 };
41 serial@d0012200 {
42 clock-frequency = <250000000>;
43 status = "okay";
44 };
45 serial@d0012300 {
46 clock-frequency = <250000000>;
47 status = "okay";
48 };
49
50 sata@d00a0000 {
51 nr-ports = <2>;
52 status = "okay";
53 };
54
55 mdio {
56 phy0: ethernet-phy@0 {
57 reg = <0>;
58 };
59
60 phy1: ethernet-phy@1 {
61 reg = <1>;
62 };
63
64 phy2: ethernet-phy@2 {
65 reg = <25>;
66 };
67
68 phy3: ethernet-phy@3 {
69 reg = <27>;
70 };
71 };
72
73 ethernet@d0070000 {
74 status = "okay";
75 phy = <&phy0>;
76 phy-mode = "rgmii-id";
77 };
78 ethernet@d0074000 {
79 status = "okay";
80 phy = <&phy1>;
81 phy-mode = "rgmii-id";
82 };
83 ethernet@d0030000 {
84 status = "okay";
85 phy = <&phy2>;
86 phy-mode = "sgmii";
87 };
88 ethernet@d0034000 {
89 status = "okay";
90 phy = <&phy3>;
91 phy-mode = "sgmii";
92 };
93 };
94};
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
deleted file mode 100644
index 271855a6e22..00000000000
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ /dev/null
@@ -1,76 +0,0 @@
1/*
2 * Device Tree Include file for Marvell Armada XP family SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 *
12 * Contains definitions specific to the Armada XP MV78230 SoC that are not
13 * common to all Armada XP SoCs.
14 */
15
16/include/ "armada-xp.dtsi"
17
18/ {
19 model = "Marvell Armada XP MV78230 SoC";
20 compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
21
22 aliases {
23 gpio0 = &gpio0;
24 gpio1 = &gpio1;
25 };
26
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 cpu@0 {
32 device_type = "cpu";
33 compatible = "marvell,sheeva-v7";
34 reg = <0>;
35 clocks = <&cpuclk 0>;
36 };
37
38 cpu@1 {
39 device_type = "cpu";
40 compatible = "marvell,sheeva-v7";
41 reg = <1>;
42 clocks = <&cpuclk 1>;
43 };
44 };
45
46 soc {
47 pinctrl {
48 compatible = "marvell,mv78230-pinctrl";
49 reg = <0xd0018000 0x38>;
50 };
51
52 gpio0: gpio@d0018100 {
53 compatible = "marvell,armadaxp-gpio";
54 reg = <0xd0018100 0x40>,
55 <0xd0018800 0x30>;
56 ngpios = <32>;
57 gpio-controller;
58 #gpio-cells = <2>;
59 interrupt-controller;
60 #interrupts-cells = <2>;
61 interrupts = <16>, <17>, <18>, <19>;
62 };
63
64 gpio1: gpio@d0018140 {
65 compatible = "marvell,armadaxp-gpio";
66 reg = <0xd0018140 0x40>,
67 <0xd0018840 0x30>;
68 ngpios = <17>;
69 gpio-controller;
70 #gpio-cells = <2>;
71 interrupt-controller;
72 #interrupts-cells = <2>;
73 interrupts = <20>, <21>, <22>;
74 };
75 };
76};
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
deleted file mode 100644
index 1c1937dbce7..00000000000
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ /dev/null
@@ -1,97 +0,0 @@
1/*
2 * Device Tree Include file for Marvell Armada XP family SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 *
12 * Contains definitions specific to the Armada XP MV78260 SoC that are not
13 * common to all Armada XP SoCs.
14 */
15
16/include/ "armada-xp.dtsi"
17
18/ {
19 model = "Marvell Armada XP MV78260 SoC";
20 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
21
22 aliases {
23 gpio0 = &gpio0;
24 gpio1 = &gpio1;
25 gpio2 = &gpio2;
26 };
27
28 cpus {
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 cpu@0 {
33 device_type = "cpu";
34 compatible = "marvell,sheeva-v7";
35 reg = <0>;
36 clocks = <&cpuclk 0>;
37 };
38
39 cpu@1 {
40 device_type = "cpu";
41 compatible = "marvell,sheeva-v7";
42 reg = <1>;
43 clocks = <&cpuclk 1>;
44 };
45 };
46
47 soc {
48 pinctrl {
49 compatible = "marvell,mv78260-pinctrl";
50 reg = <0xd0018000 0x38>;
51 };
52
53 gpio0: gpio@d0018100 {
54 compatible = "marvell,armadaxp-gpio";
55 reg = <0xd0018100 0x40>,
56 <0xd0018800 0x30>;
57 ngpios = <32>;
58 gpio-controller;
59 #gpio-cells = <2>;
60 interrupt-controller;
61 #interrupts-cells = <2>;
62 interrupts = <16>, <17>, <18>, <19>;
63 };
64
65 gpio1: gpio@d0018140 {
66 compatible = "marvell,armadaxp-gpio";
67 reg = <0xd0018140 0x40>,
68 <0xd0018840 0x30>;
69 ngpios = <32>;
70 gpio-controller;
71 #gpio-cells = <2>;
72 interrupt-controller;
73 #interrupts-cells = <2>;
74 interrupts = <20>, <21>, <22>, <23>;
75 };
76
77 gpio2: gpio@d0018180 {
78 compatible = "marvell,armadaxp-gpio";
79 reg = <0xd0018180 0x40>,
80 <0xd0018870 0x30>;
81 ngpios = <3>;
82 gpio-controller;
83 #gpio-cells = <2>;
84 interrupt-controller;
85 #interrupts-cells = <2>;
86 interrupts = <24>;
87 };
88
89 ethernet@d0034000 {
90 compatible = "marvell,armada-370-neta";
91 reg = <0xd0034000 0x2500>;
92 interrupts = <14>;
93 clocks = <&gateclk 1>;
94 status = "disabled";
95 };
96 };
97};
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
deleted file mode 100644
index 4905cf3a5ef..00000000000
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ /dev/null
@@ -1,112 +0,0 @@
1/*
2 * Device Tree Include file for Marvell Armada XP family SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 *
12 * Contains definitions specific to the Armada XP MV78460 SoC that are not
13 * common to all Armada XP SoCs.
14 */
15
16/include/ "armada-xp.dtsi"
17
18/ {
19 model = "Marvell Armada XP MV78460 SoC";
20 compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
21
22 aliases {
23 gpio0 = &gpio0;
24 gpio1 = &gpio1;
25 gpio2 = &gpio2;
26 };
27
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 cpu@0 {
34 device_type = "cpu";
35 compatible = "marvell,sheeva-v7";
36 reg = <0>;
37 clocks = <&cpuclk 0>;
38 };
39
40 cpu@1 {
41 device_type = "cpu";
42 compatible = "marvell,sheeva-v7";
43 reg = <1>;
44 clocks = <&cpuclk 1>;
45 };
46
47 cpu@2 {
48 device_type = "cpu";
49 compatible = "marvell,sheeva-v7";
50 reg = <2>;
51 clocks = <&cpuclk 2>;
52 };
53
54 cpu@3 {
55 device_type = "cpu";
56 compatible = "marvell,sheeva-v7";
57 reg = <3>;
58 clocks = <&cpuclk 3>;
59 };
60 };
61
62 soc {
63 pinctrl {
64 compatible = "marvell,mv78460-pinctrl";
65 reg = <0xd0018000 0x38>;
66 };
67
68 gpio0: gpio@d0018100 {
69 compatible = "marvell,armadaxp-gpio";
70 reg = <0xd0018100 0x40>,
71 <0xd0018800 0x30>;
72 ngpios = <32>;
73 gpio-controller;
74 #gpio-cells = <2>;
75 interrupt-controller;
76 #interrupts-cells = <2>;
77 interrupts = <16>, <17>, <18>, <19>;
78 };
79
80 gpio1: gpio@d0018140 {
81 compatible = "marvell,armadaxp-gpio";
82 reg = <0xd0018140 0x40>,
83 <0xd0018840 0x30>;
84 ngpios = <32>;
85 gpio-controller;
86 #gpio-cells = <2>;
87 interrupt-controller;
88 #interrupts-cells = <2>;
89 interrupts = <20>, <21>, <22>, <23>;
90 };
91
92 gpio2: gpio@d0018180 {
93 compatible = "marvell,armadaxp-gpio";
94 reg = <0xd0018180 0x40>,
95 <0xd0018870 0x30>;
96 ngpios = <3>;
97 gpio-controller;
98 #gpio-cells = <2>;
99 interrupt-controller;
100 #interrupts-cells = <2>;
101 interrupts = <24>;
102 };
103
104 ethernet@d0034000 {
105 compatible = "marvell,armada-370-neta";
106 reg = <0xd0034000 0x2500>;
107 interrupts = <14>;
108 clocks = <&gateclk 1>;
109 status = "disabled";
110 };
111 };
112 };
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
deleted file mode 100644
index b42652fd3d8..00000000000
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ /dev/null
@@ -1,125 +0,0 @@
1/*
2 * Device Tree file for OpenBlocks AX3-4 board
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13/dts-v1/;
14/include/ "armada-xp-mv78260.dtsi"
15
16/ {
17 model = "PlatHome OpenBlocks AX3-4 board";
18 compatible = "plathome,openblocks-ax3-4", "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
19
20 chosen {
21 bootargs = "console=ttyS0,115200 earlyprintk";
22 };
23
24 memory {
25 device_type = "memory";
26 reg = <0x00000000 0xC0000000>; /* 3 GB */
27 };
28
29 soc {
30 serial@d0012000 {
31 clock-frequency = <250000000>;
32 status = "okay";
33 };
34 serial@d0012100 {
35 clock-frequency = <250000000>;
36 status = "okay";
37 };
38 pinctrl {
39 led_pins: led-pins-0 {
40 marvell,pins = "mpp49", "mpp51", "mpp53";
41 marvell,function = "gpio";
42 };
43 };
44 leds {
45 compatible = "gpio-leds";
46 pinctrl-names = "default";
47 pinctrl-0 = <&led_pins>;
48
49 red_led {
50 label = "red_led";
51 gpios = <&gpio1 17 1>;
52 default-state = "off";
53 };
54
55 yellow_led {
56 label = "yellow_led";
57 gpios = <&gpio1 19 1>;
58 default-state = "off";
59 };
60
61 green_led {
62 label = "green_led";
63 gpios = <&gpio1 21 1>;
64 default-state = "off";
65 linux,default-trigger = "heartbeat";
66 };
67 };
68
69 mdio {
70 phy0: ethernet-phy@0 {
71 reg = <0>;
72 };
73
74 phy1: ethernet-phy@1 {
75 reg = <1>;
76 };
77
78 phy2: ethernet-phy@2 {
79 reg = <2>;
80 };
81
82 phy3: ethernet-phy@3 {
83 reg = <3>;
84 };
85 };
86
87 ethernet@d0070000 {
88 status = "okay";
89 phy = <&phy0>;
90 phy-mode = "sgmii";
91 };
92 ethernet@d0074000 {
93 status = "okay";
94 phy = <&phy1>;
95 phy-mode = "sgmii";
96 };
97 ethernet@d0030000 {
98 status = "okay";
99 phy = <&phy2>;
100 phy-mode = "sgmii";
101 };
102 ethernet@d0034000 {
103 status = "okay";
104 phy = <&phy3>;
105 phy-mode = "sgmii";
106 };
107 i2c@d0011000 {
108 status = "okay";
109 clock-frequency = <400000>;
110 };
111 i2c@d0011100 {
112 status = "okay";
113 clock-frequency = <400000>;
114
115 s35390a: s35390a@30 {
116 compatible = "s35390a";
117 reg = <0x30>;
118 };
119 };
120 sata@d00a0000 {
121 nr-ports = <2>;
122 status = "okay";
123 };
124 };
125};
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
deleted file mode 100644
index 2e37ef101c9..00000000000
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ /dev/null
@@ -1,138 +0,0 @@
1/*
2 * Device Tree Include file for Marvell Armada XP family SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 *
15 * Contains definitions specific to the Armada XP SoC that are not
16 * common to all Armada SoCs.
17 */
18
19/include/ "armada-370-xp.dtsi"
20
21/ {
22 model = "Marvell Armada XP family SoC";
23 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
24
25 L2: l2-cache {
26 compatible = "marvell,aurora-system-cache";
27 reg = <0xd0008000 0x1000>;
28 cache-id-part = <0x100>;
29 wt-override;
30 };
31
32 mpic: interrupt-controller@d0020000 {
33 reg = <0xd0020a00 0x1d0>,
34 <0xd0021070 0x58>;
35 };
36
37 armada-370-xp-pmsu@d0022000 {
38 compatible = "marvell,armada-370-xp-pmsu";
39 reg = <0xd0022100 0x430>,
40 <0xd0020800 0x20>;
41 };
42
43 soc {
44 serial@d0012200 {
45 compatible = "snps,dw-apb-uart";
46 reg = <0xd0012200 0x100>;
47 reg-shift = <2>;
48 interrupts = <43>;
49 reg-io-width = <4>;
50 status = "disabled";
51 };
52 serial@d0012300 {
53 compatible = "snps,dw-apb-uart";
54 reg = <0xd0012300 0x100>;
55 reg-shift = <2>;
56 interrupts = <44>;
57 reg-io-width = <4>;
58 status = "disabled";
59 };
60
61 timer@d0020300 {
62 marvell,timer-25Mhz;
63 };
64
65 coreclk: mvebu-sar@d0018230 {
66 compatible = "marvell,armada-xp-core-clock";
67 reg = <0xd0018230 0x08>;
68 #clock-cells = <1>;
69 };
70
71 cpuclk: clock-complex@d0018700 {
72 #clock-cells = <1>;
73 compatible = "marvell,armada-xp-cpu-clock";
74 reg = <0xd0018700 0xA0>;
75 clocks = <&coreclk 1>;
76 };
77
78 gateclk: clock-gating-control@d0018220 {
79 compatible = "marvell,armada-xp-gating-clock";
80 reg = <0xd0018220 0x4>;
81 clocks = <&coreclk 0>;
82 #clock-cells = <1>;
83 };
84
85 system-controller@d0018200 {
86 compatible = "marvell,armada-370-xp-system-controller";
87 reg = <0xd0018200 0x500>;
88 };
89
90 ethernet@d0030000 {
91 compatible = "marvell,armada-370-neta";
92 reg = <0xd0030000 0x2500>;
93 interrupts = <12>;
94 clocks = <&gateclk 2>;
95 status = "disabled";
96 };
97
98 xor@d0060900 {
99 compatible = "marvell,orion-xor";
100 reg = <0xd0060900 0x100
101 0xd0060b00 0x100>;
102 clocks = <&gateclk 22>;
103 status = "okay";
104
105 xor10 {
106 interrupts = <51>;
107 dmacap,memcpy;
108 dmacap,xor;
109 };
110 xor11 {
111 interrupts = <52>;
112 dmacap,memcpy;
113 dmacap,xor;
114 dmacap,memset;
115 };
116 };
117
118 xor@d00f0900 {
119 compatible = "marvell,orion-xor";
120 reg = <0xd00F0900 0x100
121 0xd00F0B00 0x100>;
122 clocks = <&gateclk 28>;
123 status = "okay";
124
125 xor00 {
126 interrupts = <94>;
127 dmacap,memcpy;
128 dmacap,xor;
129 };
130 xor01 {
131 interrupts = <95>;
132 dmacap,memcpy;
133 dmacap,xor;
134 dmacap,memset;
135 };
136 };
137 };
138};
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
deleted file mode 100644
index e154f242c68..00000000000
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ /dev/null
@@ -1,349 +0,0 @@
1/*
2 * at91rm9200.dtsi - Device Tree Include file for AT91RM9200 family SoC
3 *
4 * Copyright (C) 2011 Atmel,
5 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
6 * 2012 Joachim Eastwood <manabian@gmail.com>
7 *
8 * Based on at91sam9260.dtsi
9 *
10 * Licensed under GPLv2 or later.
11 */
12
13/include/ "skeleton.dtsi"
14
15/ {
16 model = "Atmel AT91RM9200 family SoC";
17 compatible = "atmel,at91rm9200";
18 interrupt-parent = <&aic>;
19
20 aliases {
21 serial0 = &dbgu;
22 serial1 = &usart0;
23 serial2 = &usart1;
24 serial3 = &usart2;
25 serial4 = &usart3;
26 gpio0 = &pioA;
27 gpio1 = &pioB;
28 gpio2 = &pioC;
29 gpio3 = &pioD;
30 tcb0 = &tcb0;
31 tcb1 = &tcb1;
32 };
33 cpus {
34 cpu@0 {
35 compatible = "arm,arm920t";
36 };
37 };
38
39 memory {
40 reg = <0x20000000 0x04000000>;
41 };
42
43 ahb {
44 compatible = "simple-bus";
45 #address-cells = <1>;
46 #size-cells = <1>;
47 ranges;
48
49 apb {
50 compatible = "simple-bus";
51 #address-cells = <1>;
52 #size-cells = <1>;
53 ranges;
54
55 aic: interrupt-controller@fffff000 {
56 #interrupt-cells = <3>;
57 compatible = "atmel,at91rm9200-aic";
58 interrupt-controller;
59 reg = <0xfffff000 0x200>;
60 atmel,external-irqs = <25 26 27 28 29 30 31>;
61 };
62
63 ramc0: ramc@ffffff00 {
64 compatible = "atmel,at91rm9200-sdramc";
65 reg = <0xffffff00 0x100>;
66 };
67
68 pmc: pmc@fffffc00 {
69 compatible = "atmel,at91rm9200-pmc";
70 reg = <0xfffffc00 0x100>;
71 };
72
73 st: timer@fffffd00 {
74 compatible = "atmel,at91rm9200-st";
75 reg = <0xfffffd00 0x100>;
76 interrupts = <1 4 7>;
77 };
78
79 tcb0: timer@fffa0000 {
80 compatible = "atmel,at91rm9200-tcb";
81 reg = <0xfffa0000 0x100>;
82 interrupts = <17 4 0 18 4 0 19 4 0>;
83 };
84
85 tcb1: timer@fffa4000 {
86 compatible = "atmel,at91rm9200-tcb";
87 reg = <0xfffa4000 0x100>;
88 interrupts = <20 4 0 21 4 0 22 4 0>;
89 };
90
91 pinctrl@fffff400 {
92 #address-cells = <1>;
93 #size-cells = <1>;
94 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
95 ranges = <0xfffff400 0xfffff400 0x800>;
96
97 atmel,mux-mask = <
98 /* A B */
99 0xffffffff 0xffffffff /* pioA */
100 0xffffffff 0x083fffff /* pioB */
101 0xffff3fff 0x00000000 /* pioC */
102 0x03ff87ff 0x0fffff80 /* pioD */
103 >;
104
105 /* shared pinctrl settings */
106 dbgu {
107 pinctrl_dbgu: dbgu-0 {
108 atmel,pins =
109 <0 30 0x1 0x0 /* PA30 periph A */
110 0 31 0x1 0x1>; /* PA31 periph with pullup */
111 };
112 };
113
114 uart0 {
115 pinctrl_uart0: uart0-0 {
116 atmel,pins =
117 <0 17 0x1 0x0 /* PA17 periph A */
118 0 18 0x1 0x0>; /* PA18 periph A */
119 };
120
121 pinctrl_uart0_rts: uart0_rts-0 {
122 atmel,pins =
123 <0 20 0x1 0x0>; /* PA20 periph A */
124 };
125
126 pinctrl_uart0_cts: uart0_cts-0 {
127 atmel,pins =
128 <0 21 0x1 0x0>; /* PA21 periph A */
129 };
130 };
131
132 uart1 {
133 pinctrl_uart1: uart1-0 {
134 atmel,pins =
135 <1 20 0x1 0x1 /* PB20 periph A with pullup */
136 1 21 0x1 0x0>; /* PB21 periph A */
137 };
138
139 pinctrl_uart1_rts: uart1_rts-0 {
140 atmel,pins =
141 <1 24 0x1 0x0>; /* PB24 periph A */
142 };
143
144 pinctrl_uart1_cts: uart1_cts-0 {
145 atmel,pins =
146 <1 26 0x1 0x0>; /* PB26 periph A */
147 };
148
149 pinctrl_uart1_dtr_dsr: uart1_dtr_dsr-0 {
150 atmel,pins =
151 <1 19 0x1 0x0 /* PB19 periph A */
152 1 25 0x1 0x0>; /* PB25 periph A */
153 };
154
155 pinctrl_uart1_dcd: uart1_dcd-0 {
156 atmel,pins =
157 <1 23 0x1 0x0>; /* PB23 periph A */
158 };
159
160 pinctrl_uart1_ri: uart1_ri-0 {
161 atmel,pins =
162 <1 18 0x1 0x0>; /* PB18 periph A */
163 };
164 };
165
166 uart2 {
167 pinctrl_uart2: uart2-0 {
168 atmel,pins =
169 <0 22 0x1 0x0 /* PA22 periph A */
170 0 23 0x1 0x1>; /* PA23 periph A with pullup */
171 };
172
173 pinctrl_uart2_rts: uart2_rts-0 {
174 atmel,pins =
175 <0 30 0x2 0x0>; /* PA30 periph B */
176 };
177
178 pinctrl_uart2_cts: uart2_cts-0 {
179 atmel,pins =
180 <0 31 0x2 0x0>; /* PA31 periph B */
181 };
182 };
183
184 uart3 {
185 pinctrl_uart3: uart3-0 {
186 atmel,pins =
187 <0 5 0x2 0x1 /* PA5 periph B with pullup */
188 0 6 0x2 0x0>; /* PA6 periph B */
189 };
190
191 pinctrl_uart3_rts: uart3_rts-0 {
192 atmel,pins =
193 <1 0 0x2 0x0>; /* PB0 periph B */
194 };
195
196 pinctrl_uart3_cts: uart3_cts-0 {
197 atmel,pins =
198 <1 1 0x2 0x0>; /* PB1 periph B */
199 };
200 };
201
202 nand {
203 pinctrl_nand: nand-0 {
204 atmel,pins =
205 <2 2 0x0 0x1 /* PC2 gpio RDY pin pull_up */
206 1 1 0x0 0x1>; /* PB1 gpio CD pin pull_up */
207 };
208 };
209
210 pioA: gpio@fffff400 {
211 compatible = "atmel,at91rm9200-gpio";
212 reg = <0xfffff400 0x200>;
213 interrupts = <2 4 1>;
214 #gpio-cells = <2>;
215 gpio-controller;
216 interrupt-controller;
217 #interrupt-cells = <2>;
218 };
219
220 pioB: gpio@fffff600 {
221 compatible = "atmel,at91rm9200-gpio";
222 reg = <0xfffff600 0x200>;
223 interrupts = <3 4 1>;
224 #gpio-cells = <2>;
225 gpio-controller;
226 interrupt-controller;
227 #interrupt-cells = <2>;
228 };
229
230 pioC: gpio@fffff800 {
231 compatible = "atmel,at91rm9200-gpio";
232 reg = <0xfffff800 0x200>;
233 interrupts = <4 4 1>;
234 #gpio-cells = <2>;
235 gpio-controller;
236 interrupt-controller;
237 #interrupt-cells = <2>;
238 };
239
240 pioD: gpio@fffffa00 {
241 compatible = "atmel,at91rm9200-gpio";
242 reg = <0xfffffa00 0x200>;
243 interrupts = <5 4 1>;
244 #gpio-cells = <2>;
245 gpio-controller;
246 interrupt-controller;
247 #interrupt-cells = <2>;
248 };
249 };
250
251 dbgu: serial@fffff200 {
252 compatible = "atmel,at91rm9200-usart";
253 reg = <0xfffff200 0x200>;
254 interrupts = <1 4 7>;
255 pinctrl-names = "default";
256 pinctrl-0 = <&pinctrl_dbgu>;
257 status = "disabled";
258 };
259
260 usart0: serial@fffc0000 {
261 compatible = "atmel,at91rm9200-usart";
262 reg = <0xfffc0000 0x200>;
263 interrupts = <6 4 5>;
264 atmel,use-dma-rx;
265 atmel,use-dma-tx;
266 pinctrl-names = "default";
267 pinctrl-0 = <&pinctrl_uart0>;
268 status = "disabled";
269 };
270
271 usart1: serial@fffc4000 {
272 compatible = "atmel,at91rm9200-usart";
273 reg = <0xfffc4000 0x200>;
274 interrupts = <7 4 5>;
275 atmel,use-dma-rx;
276 atmel,use-dma-tx;
277 pinctrl-names = "default";
278 pinctrl-0 = <&pinctrl_uart1>;
279 status = "disabled";
280 };
281
282 usart2: serial@fffc8000 {
283 compatible = "atmel,at91rm9200-usart";
284 reg = <0xfffc8000 0x200>;
285 interrupts = <8 4 5>;
286 atmel,use-dma-rx;
287 atmel,use-dma-tx;
288 pinctrl-names = "default";
289 pinctrl-0 = <&pinctrl_uart2>;
290 status = "disabled";
291 };
292
293 usart3: serial@fffcc000 {
294 compatible = "atmel,at91rm9200-usart";
295 reg = <0xfffcc000 0x200>;
296 interrupts = <23 4 5>;
297 atmel,use-dma-rx;
298 atmel,use-dma-tx;
299 pinctrl-names = "default";
300 pinctrl-0 = <&pinctrl_uart3>;
301 status = "disabled";
302 };
303
304 usb1: gadget@fffb0000 {
305 compatible = "atmel,at91rm9200-udc";
306 reg = <0xfffb0000 0x4000>;
307 interrupts = <11 4 2>;
308 status = "disabled";
309 };
310 };
311
312 nand0: nand@40000000 {
313 compatible = "atmel,at91rm9200-nand";
314 #address-cells = <1>;
315 #size-cells = <1>;
316 reg = <0x40000000 0x10000000>;
317 atmel,nand-addr-offset = <21>;
318 atmel,nand-cmd-offset = <22>;
319 pinctrl-names = "default";
320 pinctrl-0 = <&pinctrl_nand>;
321 nand-ecc-mode = "soft";
322 gpios = <&pioC 2 0
323 0
324 &pioB 1 0
325 >;
326 status = "disabled";
327 };
328
329 usb0: ohci@00300000 {
330 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
331 reg = <0x00300000 0x100000>;
332 interrupts = <23 4 2>;
333 status = "disabled";
334 };
335 };
336
337 i2c@0 {
338 compatible = "i2c-gpio";
339 gpios = <&pioA 23 0 /* sda */
340 &pioA 24 0 /* scl */
341 >;
342 i2c-gpio,sda-open-drain;
343 i2c-gpio,scl-open-drain;
344 i2c-gpio,delay-us = <2>; /* ~100 kHz */
345 #address-cells = <1>;
346 #size-cells = <0>;
347 status = "disabled";
348 };
349};
diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/at91rm9200ek.dts
deleted file mode 100644
index 8aa48931e0a..00000000000
--- a/arch/arm/boot/dts/at91rm9200ek.dts
+++ /dev/null
@@ -1,79 +0,0 @@
1/*
2 * at91rm9200ek.dts - Device Tree file for Atmel AT91RM9200 evaluation kit
3 *
4 * Copyright (C) 2012 Joachim Eastwood <manabian@gmail.com>
5 *
6 * Licensed under GPLv2 only
7 */
8/dts-v1/;
9/include/ "at91rm9200.dtsi"
10
11/ {
12 model = "Atmel AT91RM9200 evaluation kit";
13 compatible = "atmel,at91rm9200ek", "atmel,at91rm9200";
14
15 memory {
16 reg = <0x20000000 0x4000000>;
17 };
18
19 clocks {
20 #address-cells = <1>;
21 #size-cells = <1>;
22 ranges;
23
24 main_clock: clock@0 {
25 compatible = "atmel,osc", "fixed-clock";
26 clock-frequency = <18432000>;
27 };
28 };
29
30 ahb {
31 apb {
32 dbgu: serial@fffff200 {
33 status = "okay";
34 };
35
36 usart1: serial@fffc4000 {
37 pinctrl-0 =
38 <&pinctrl_uart1
39 &pinctrl_uart1_rts
40 &pinctrl_uart1_cts
41 &pinctrl_uart1_dtr_dsr
42 &pinctrl_uart1_dcd
43 &pinctrl_uart1_ri>;
44 status = "okay";
45 };
46
47 usb1: gadget@fffb0000 {
48 atmel,vbus-gpio = <&pioD 4 0>;
49 status = "okay";
50 };
51 };
52
53 usb0: ohci@00300000 {
54 num-ports = <2>;
55 status = "okay";
56 };
57 };
58
59 leds {
60 compatible = "gpio-leds";
61
62 ds2 {
63 label = "green";
64 gpios = <&pioB 0 0x1>;
65 linux,default-trigger = "mmc0";
66 };
67
68 ds4 {
69 label = "yellow";
70 gpios = <&pioB 1 0x1>;
71 linux,default-trigger = "heartbeat";
72 };
73
74 ds6 {
75 label = "red";
76 gpios = <&pioB 2 0x1>;
77 };
78 };
79};
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
deleted file mode 100644
index 68bccf41a2c..00000000000
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ /dev/null
@@ -1,536 +0,0 @@
1/*
2 * at91sam9260.dtsi - Device Tree Include file for AT91SAM9260 family SoC
3 *
4 * Copyright (C) 2011 Atmel,
5 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
6 * 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
7 *
8 * Licensed under GPLv2 or later.
9 */
10
11/include/ "skeleton.dtsi"
12
13/ {
14 model = "Atmel AT91SAM9260 family SoC";
15 compatible = "atmel,at91sam9260";
16 interrupt-parent = <&aic>;
17
18 aliases {
19 serial0 = &dbgu;
20 serial1 = &usart0;
21 serial2 = &usart1;
22 serial3 = &usart2;
23 serial4 = &usart3;
24 serial5 = &uart0;
25 serial6 = &uart1;
26 gpio0 = &pioA;
27 gpio1 = &pioB;
28 gpio2 = &pioC;
29 tcb0 = &tcb0;
30 tcb1 = &tcb1;
31 i2c0 = &i2c0;
32 ssc0 = &ssc0;
33 };
34 cpus {
35 cpu@0 {
36 compatible = "arm,arm926ejs";
37 };
38 };
39
40 memory {
41 reg = <0x20000000 0x04000000>;
42 };
43
44 ahb {
45 compatible = "simple-bus";
46 #address-cells = <1>;
47 #size-cells = <1>;
48 ranges;
49
50 apb {
51 compatible = "simple-bus";
52 #address-cells = <1>;
53 #size-cells = <1>;
54 ranges;
55
56 aic: interrupt-controller@fffff000 {
57 #interrupt-cells = <3>;
58 compatible = "atmel,at91rm9200-aic";
59 interrupt-controller;
60 reg = <0xfffff000 0x200>;
61 atmel,external-irqs = <29 30 31>;
62 };
63
64 ramc0: ramc@ffffea00 {
65 compatible = "atmel,at91sam9260-sdramc";
66 reg = <0xffffea00 0x200>;
67 };
68
69 pmc: pmc@fffffc00 {
70 compatible = "atmel,at91rm9200-pmc";
71 reg = <0xfffffc00 0x100>;
72 };
73
74 rstc@fffffd00 {
75 compatible = "atmel,at91sam9260-rstc";
76 reg = <0xfffffd00 0x10>;
77 };
78
79 shdwc@fffffd10 {
80 compatible = "atmel,at91sam9260-shdwc";
81 reg = <0xfffffd10 0x10>;
82 };
83
84 pit: timer@fffffd30 {
85 compatible = "atmel,at91sam9260-pit";
86 reg = <0xfffffd30 0xf>;
87 interrupts = <1 4 7>;
88 };
89
90 tcb0: timer@fffa0000 {
91 compatible = "atmel,at91rm9200-tcb";
92 reg = <0xfffa0000 0x100>;
93 interrupts = <17 4 0 18 4 0 19 4 0>;
94 };
95
96 tcb1: timer@fffdc000 {
97 compatible = "atmel,at91rm9200-tcb";
98 reg = <0xfffdc000 0x100>;
99 interrupts = <26 4 0 27 4 0 28 4 0>;
100 };
101
102 pinctrl@fffff400 {
103 #address-cells = <1>;
104 #size-cells = <1>;
105 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
106 ranges = <0xfffff400 0xfffff400 0x600>;
107
108 atmel,mux-mask = <
109 /* A B */
110 0xffffffff 0xffc00c3b /* pioA */
111 0xffffffff 0x7fff3ccf /* pioB */
112 0xffffffff 0x007fffff /* pioC */
113 >;
114
115 /* shared pinctrl settings */
116 dbgu {
117 pinctrl_dbgu: dbgu-0 {
118 atmel,pins =
119 <1 14 0x1 0x0 /* PB14 periph A */
120 1 15 0x1 0x1>; /* PB15 periph with pullup */
121 };
122 };
123
124 usart0 {
125 pinctrl_usart0: usart0-0 {
126 atmel,pins =
127 <1 4 0x1 0x0 /* PB4 periph A */
128 1 5 0x1 0x0>; /* PB5 periph A */
129 };
130
131 pinctrl_usart0_rts: usart0_rts-0 {
132 atmel,pins =
133 <1 26 0x1 0x0>; /* PB26 periph A */
134 };
135
136 pinctrl_usart0_cts: usart0_cts-0 {
137 atmel,pins =
138 <1 27 0x1 0x0>; /* PB27 periph A */
139 };
140
141 pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 {
142 atmel,pins =
143 <1 24 0x1 0x0 /* PB24 periph A */
144 1 22 0x1 0x0>; /* PB22 periph A */
145 };
146
147 pinctrl_usart0_dcd: usart0_dcd-0 {
148 atmel,pins =
149 <1 23 0x1 0x0>; /* PB23 periph A */
150 };
151
152 pinctrl_usart0_ri: usart0_ri-0 {
153 atmel,pins =
154 <1 25 0x1 0x0>; /* PB25 periph A */
155 };
156 };
157
158 usart1 {
159 pinctrl_usart1: usart1-0 {
160 atmel,pins =
161 <2 6 0x1 0x1 /* PB6 periph A with pullup */
162 2 7 0x1 0x0>; /* PB7 periph A */
163 };
164
165 pinctrl_usart1_rts: usart1_rts-0 {
166 atmel,pins =
167 <1 28 0x1 0x0>; /* PB28 periph A */
168 };
169
170 pinctrl_usart1_cts: usart1_cts-0 {
171 atmel,pins =
172 <1 29 0x1 0x0>; /* PB29 periph A */
173 };
174 };
175
176 usart2 {
177 pinctrl_usart2: usart2-0 {
178 atmel,pins =
179 <1 8 0x1 0x1 /* PB8 periph A with pullup */
180 1 9 0x1 0x0>; /* PB9 periph A */
181 };
182
183 pinctrl_usart2_rts: usart2_rts-0 {
184 atmel,pins =
185 <0 4 0x1 0x0>; /* PA4 periph A */
186 };
187
188 pinctrl_usart2_cts: usart2_cts-0 {
189 atmel,pins =
190 <0 5 0x1 0x0>; /* PA5 periph A */
191 };
192 };
193
194 usart3 {
195 pinctrl_usart3: usart3-0 {
196 atmel,pins =
197 <2 10 0x1 0x1 /* PB10 periph A with pullup */
198 2 11 0x1 0x0>; /* PB11 periph A */
199 };
200
201 pinctrl_usart3_rts: usart3_rts-0 {
202 atmel,pins =
203 <3 8 0x2 0x0>; /* PB8 periph B */
204 };
205
206 pinctrl_usart3_cts: usart3_cts-0 {
207 atmel,pins =
208 <3 10 0x2 0x0>; /* PB10 periph B */
209 };
210 };
211
212 uart0 {
213 pinctrl_uart0: uart0-0 {
214 atmel,pins =
215 <0 31 0x2 0x1 /* PA31 periph B with pullup */
216 0 30 0x2 0x0>; /* PA30 periph B */
217 };
218 };
219
220 uart1 {
221 pinctrl_uart1: uart1-0 {
222 atmel,pins =
223 <2 12 0x1 0x1 /* PB12 periph A with pullup */
224 2 13 0x1 0x0>; /* PB13 periph A */
225 };
226 };
227
228 nand {
229 pinctrl_nand: nand-0 {
230 atmel,pins =
231 <2 13 0x0 0x1 /* PC13 gpio RDY pin pull_up */
232 2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
233 };
234 };
235
236 macb {
237 pinctrl_macb_rmii: macb_rmii-0 {
238 atmel,pins =
239 <0 12 0x1 0x0 /* PA12 periph A */
240 0 13 0x1 0x0 /* PA13 periph A */
241 0 14 0x1 0x0 /* PA14 periph A */
242 0 15 0x1 0x0 /* PA15 periph A */
243 0 16 0x1 0x0 /* PA16 periph A */
244 0 17 0x1 0x0 /* PA17 periph A */
245 0 18 0x1 0x0 /* PA18 periph A */
246 0 19 0x1 0x0 /* PA19 periph A */
247 0 20 0x1 0x0 /* PA20 periph A */
248 0 21 0x1 0x0>; /* PA21 periph A */
249 };
250
251 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
252 atmel,pins =
253 <0 22 0x2 0x0 /* PA22 periph B */
254 0 23 0x2 0x0 /* PA23 periph B */
255 0 24 0x2 0x0 /* PA24 periph B */
256 0 25 0x2 0x0 /* PA25 periph B */
257 0 26 0x2 0x0 /* PA26 periph B */
258 0 27 0x2 0x0 /* PA27 periph B */
259 0 28 0x2 0x0 /* PA28 periph B */
260 0 29 0x2 0x0>; /* PA29 periph B */
261 };
262
263 pinctrl_macb_rmii_mii_alt: macb_rmii_mii-1 {
264 atmel,pins =
265 <0 10 0x2 0x0 /* PA10 periph B */
266 0 11 0x2 0x0 /* PA11 periph B */
267 0 24 0x2 0x0 /* PA24 periph B */
268 0 25 0x2 0x0 /* PA25 periph B */
269 0 26 0x2 0x0 /* PA26 periph B */
270 0 27 0x2 0x0 /* PA27 periph B */
271 0 28 0x2 0x0 /* PA28 periph B */
272 0 29 0x2 0x0>; /* PA29 periph B */
273 };
274 };
275
276 mmc0 {
277 pinctrl_mmc0_clk: mmc0_clk-0 {
278 atmel,pins =
279 <0 8 0x1 0x0>; /* PA8 periph A */
280 };
281
282 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
283 atmel,pins =
284 <0 7 0x1 0x1 /* PA7 periph A with pullup */
285 0 6 0x1 0x1>; /* PA6 periph A with pullup */
286 };
287
288 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
289 atmel,pins =
290 <0 9 0x1 0x1 /* PA9 periph A with pullup */
291 0 10 0x1 0x1 /* PA10 periph A with pullup */
292 0 11 0x1 0x1>; /* PA11 periph A with pullup */
293 };
294
295 pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
296 atmel,pins =
297 <0 1 0x2 0x1 /* PA1 periph B with pullup */
298 0 0 0x2 0x1>; /* PA0 periph B with pullup */
299 };
300
301 pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
302 atmel,pins =
303 <0 5 0x2 0x1 /* PA5 periph B with pullup */
304 0 4 0x2 0x1 /* PA4 periph B with pullup */
305 0 3 0x2 0x1>; /* PA3 periph B with pullup */
306 };
307 };
308
309 pioA: gpio@fffff400 {
310 compatible = "atmel,at91rm9200-gpio";
311 reg = <0xfffff400 0x200>;
312 interrupts = <2 4 1>;
313 #gpio-cells = <2>;
314 gpio-controller;
315 interrupt-controller;
316 #interrupt-cells = <2>;
317 };
318
319 pioB: gpio@fffff600 {
320 compatible = "atmel,at91rm9200-gpio";
321 reg = <0xfffff600 0x200>;
322 interrupts = <3 4 1>;
323 #gpio-cells = <2>;
324 gpio-controller;
325 interrupt-controller;
326 #interrupt-cells = <2>;
327 };
328
329 pioC: gpio@fffff800 {
330 compatible = "atmel,at91rm9200-gpio";
331 reg = <0xfffff800 0x200>;
332 interrupts = <4 4 1>;
333 #gpio-cells = <2>;
334 gpio-controller;
335 interrupt-controller;
336 #interrupt-cells = <2>;
337 };
338 };
339
340 dbgu: serial@fffff200 {
341 compatible = "atmel,at91sam9260-usart";
342 reg = <0xfffff200 0x200>;
343 interrupts = <1 4 7>;
344 pinctrl-names = "default";
345 pinctrl-0 = <&pinctrl_dbgu>;
346 status = "disabled";
347 };
348
349 usart0: serial@fffb0000 {
350 compatible = "atmel,at91sam9260-usart";
351 reg = <0xfffb0000 0x200>;
352 interrupts = <6 4 5>;
353 atmel,use-dma-rx;
354 atmel,use-dma-tx;
355 pinctrl-names = "default";
356 pinctrl-0 = <&pinctrl_usart0>;
357 status = "disabled";
358 };
359
360 usart1: serial@fffb4000 {
361 compatible = "atmel,at91sam9260-usart";
362 reg = <0xfffb4000 0x200>;
363 interrupts = <7 4 5>;
364 atmel,use-dma-rx;
365 atmel,use-dma-tx;
366 pinctrl-names = "default";
367 pinctrl-0 = <&pinctrl_usart1>;
368 status = "disabled";
369 };
370
371 usart2: serial@fffb8000 {
372 compatible = "atmel,at91sam9260-usart";
373 reg = <0xfffb8000 0x200>;
374 interrupts = <8 4 5>;
375 atmel,use-dma-rx;
376 atmel,use-dma-tx;
377 pinctrl-names = "default";
378 pinctrl-0 = <&pinctrl_usart2>;
379 status = "disabled";
380 };
381
382 usart3: serial@fffd0000 {
383 compatible = "atmel,at91sam9260-usart";
384 reg = <0xfffd0000 0x200>;
385 interrupts = <23 4 5>;
386 atmel,use-dma-rx;
387 atmel,use-dma-tx;
388 pinctrl-names = "default";
389 pinctrl-0 = <&pinctrl_usart3>;
390 status = "disabled";
391 };
392
393 uart0: serial@fffd4000 {
394 compatible = "atmel,at91sam9260-usart";
395 reg = <0xfffd4000 0x200>;
396 interrupts = <24 4 5>;
397 atmel,use-dma-rx;
398 atmel,use-dma-tx;
399 pinctrl-names = "default";
400 pinctrl-0 = <&pinctrl_uart0>;
401 status = "disabled";
402 };
403
404 uart1: serial@fffd8000 {
405 compatible = "atmel,at91sam9260-usart";
406 reg = <0xfffd8000 0x200>;
407 interrupts = <25 4 5>;
408 atmel,use-dma-rx;
409 atmel,use-dma-tx;
410 pinctrl-names = "default";
411 pinctrl-0 = <&pinctrl_uart1>;
412 status = "disabled";
413 };
414
415 macb0: ethernet@fffc4000 {
416 compatible = "cdns,at32ap7000-macb", "cdns,macb";
417 reg = <0xfffc4000 0x100>;
418 interrupts = <21 4 3>;
419 pinctrl-names = "default";
420 pinctrl-0 = <&pinctrl_macb_rmii>;
421 status = "disabled";
422 };
423
424 usb1: gadget@fffa4000 {
425 compatible = "atmel,at91rm9200-udc";
426 reg = <0xfffa4000 0x4000>;
427 interrupts = <10 4 2>;
428 status = "disabled";
429 };
430
431 i2c0: i2c@fffac000 {
432 compatible = "atmel,at91sam9260-i2c";
433 reg = <0xfffac000 0x100>;
434 interrupts = <11 4 6>;
435 #address-cells = <1>;
436 #size-cells = <0>;
437 status = "disabled";
438 };
439
440 mmc0: mmc@fffa8000 {
441 compatible = "atmel,hsmci";
442 reg = <0xfffa8000 0x600>;
443 interrupts = <9 4 0>;
444 #address-cells = <1>;
445 #size-cells = <0>;
446 status = "disabled";
447 };
448
449 ssc0: ssc@fffbc000 {
450 compatible = "atmel,at91rm9200-ssc";
451 reg = <0xfffbc000 0x4000>;
452 interrupts = <14 4 5>;
453 status = "disabled";
454 };
455
456 adc0: adc@fffe0000 {
457 compatible = "atmel,at91sam9260-adc";
458 reg = <0xfffe0000 0x100>;
459 interrupts = <5 4 0>;
460 atmel,adc-use-external-triggers;
461 atmel,adc-channels-used = <0xf>;
462 atmel,adc-vref = <3300>;
463 atmel,adc-num-channels = <4>;
464 atmel,adc-startup-time = <15>;
465 atmel,adc-channel-base = <0x30>;
466 atmel,adc-drdy-mask = <0x10000>;
467 atmel,adc-status-register = <0x1c>;
468 atmel,adc-trigger-register = <0x04>;
469
470 trigger@0 {
471 trigger-name = "timer-counter-0";
472 trigger-value = <0x1>;
473 };
474 trigger@1 {
475 trigger-name = "timer-counter-1";
476 trigger-value = <0x3>;
477 };
478
479 trigger@2 {
480 trigger-name = "timer-counter-2";
481 trigger-value = <0x5>;
482 };
483
484 trigger@3 {
485 trigger-name = "external";
486 trigger-value = <0x13>;
487 trigger-external;
488 };
489 };
490
491 watchdog@fffffd40 {
492 compatible = "atmel,at91sam9260-wdt";
493 reg = <0xfffffd40 0x10>;
494 status = "disabled";
495 };
496 };
497
498 nand0: nand@40000000 {
499 compatible = "atmel,at91rm9200-nand";
500 #address-cells = <1>;
501 #size-cells = <1>;
502 reg = <0x40000000 0x10000000
503 0xffffe800 0x200
504 >;
505 atmel,nand-addr-offset = <21>;
506 atmel,nand-cmd-offset = <22>;
507 pinctrl-names = "default";
508 pinctrl-0 = <&pinctrl_nand>;
509 gpios = <&pioC 13 0
510 &pioC 14 0
511 0
512 >;
513 status = "disabled";
514 };
515
516 usb0: ohci@00500000 {
517 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
518 reg = <0x00500000 0x100000>;
519 interrupts = <20 4 2>;
520 status = "disabled";
521 };
522 };
523
524 i2c@0 {
525 compatible = "i2c-gpio";
526 gpios = <&pioA 23 0 /* sda */
527 &pioA 24 0 /* scl */
528 >;
529 i2c-gpio,sda-open-drain;
530 i2c-gpio,scl-open-drain;
531 i2c-gpio,delay-us = <2>; /* ~100 kHz */
532 #address-cells = <1>;
533 #size-cells = <0>;
534 status = "disabled";
535 };
536};
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
deleted file mode 100644
index 32ec62cf538..00000000000
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ /dev/null
@@ -1,469 +0,0 @@
1/*
2 * at91sam9263.dtsi - Device Tree Include file for AT91SAM9263 family SoC
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2 only.
7 */
8
9/include/ "skeleton.dtsi"
10
11/ {
12 model = "Atmel AT91SAM9263 family SoC";
13 compatible = "atmel,at91sam9263";
14 interrupt-parent = <&aic>;
15
16 aliases {
17 serial0 = &dbgu;
18 serial1 = &usart0;
19 serial2 = &usart1;
20 serial3 = &usart2;
21 gpio0 = &pioA;
22 gpio1 = &pioB;
23 gpio2 = &pioC;
24 gpio3 = &pioD;
25 gpio4 = &pioE;
26 tcb0 = &tcb0;
27 i2c0 = &i2c0;
28 ssc0 = &ssc0;
29 ssc1 = &ssc1;
30 };
31 cpus {
32 cpu@0 {
33 compatible = "arm,arm926ejs";
34 };
35 };
36
37 memory {
38 reg = <0x20000000 0x08000000>;
39 };
40
41 ahb {
42 compatible = "simple-bus";
43 #address-cells = <1>;
44 #size-cells = <1>;
45 ranges;
46
47 apb {
48 compatible = "simple-bus";
49 #address-cells = <1>;
50 #size-cells = <1>;
51 ranges;
52
53 aic: interrupt-controller@fffff000 {
54 #interrupt-cells = <3>;
55 compatible = "atmel,at91rm9200-aic";
56 interrupt-controller;
57 reg = <0xfffff000 0x200>;
58 atmel,external-irqs = <30 31>;
59 };
60
61 pmc: pmc@fffffc00 {
62 compatible = "atmel,at91rm9200-pmc";
63 reg = <0xfffffc00 0x100>;
64 };
65
66 ramc: ramc@ffffe200 {
67 compatible = "atmel,at91sam9260-sdramc";
68 reg = <0xffffe200 0x200
69 0xffffe800 0x200>;
70 };
71
72 pit: timer@fffffd30 {
73 compatible = "atmel,at91sam9260-pit";
74 reg = <0xfffffd30 0xf>;
75 interrupts = <1 4 7>;
76 };
77
78 tcb0: timer@fff7c000 {
79 compatible = "atmel,at91rm9200-tcb";
80 reg = <0xfff7c000 0x100>;
81 interrupts = <19 4 0>;
82 };
83
84 rstc@fffffd00 {
85 compatible = "atmel,at91sam9260-rstc";
86 reg = <0xfffffd00 0x10>;
87 };
88
89 shdwc@fffffd10 {
90 compatible = "atmel,at91sam9260-shdwc";
91 reg = <0xfffffd10 0x10>;
92 };
93
94 pinctrl@fffff200 {
95 #address-cells = <1>;
96 #size-cells = <1>;
97 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
98 ranges = <0xfffff200 0xfffff200 0xa00>;
99
100 atmel,mux-mask = <
101 /* A B */
102 0xfffffffb 0xffffe07f /* pioA */
103 0x0007ffff 0x39072fff /* pioB */
104 0xffffffff 0x3ffffff8 /* pioC */
105 0xfffffbff 0xffffffff /* pioD */
106 0xffe00fff 0xfbfcff00 /* pioE */
107 >;
108
109 /* shared pinctrl settings */
110 dbgu {
111 pinctrl_dbgu: dbgu-0 {
112 atmel,pins =
113 <2 30 0x1 0x0 /* PC30 periph A */
114 2 31 0x1 0x1>; /* PC31 periph with pullup */
115 };
116 };
117
118 usart0 {
119 pinctrl_usart0: usart0-0 {
120 atmel,pins =
121 <0 26 0x1 0x1 /* PA26 periph A with pullup */
122 0 27 0x1 0x0>; /* PA27 periph A */
123 };
124
125 pinctrl_usart0_rts: usart0_rts-0 {
126 atmel,pins =
127 <0 28 0x1 0x0>; /* PA28 periph A */
128 };
129
130 pinctrl_usart0_cts: usart0_cts-0 {
131 atmel,pins =
132 <0 29 0x1 0x0>; /* PA29 periph A */
133 };
134 };
135
136 usart1 {
137 pinctrl_usart1: usart1-0 {
138 atmel,pins =
139 <3 0 0x1 0x1 /* PD0 periph A with pullup */
140 3 1 0x1 0x0>; /* PD1 periph A */
141 };
142
143 pinctrl_usart1_rts: usart1_rts-0 {
144 atmel,pins =
145 <3 7 0x2 0x0>; /* PD7 periph B */
146 };
147
148 pinctrl_usart1_cts: usart1_cts-0 {
149 atmel,pins =
150 <3 8 0x2 0x0>; /* PD8 periph B */
151 };
152 };
153
154 usart2 {
155 pinctrl_usart2: usart2-0 {
156 atmel,pins =
157 <3 2 0x1 0x1 /* PD2 periph A with pullup */
158 3 3 0x1 0x0>; /* PD3 periph A */
159 };
160
161 pinctrl_usart2_rts: usart2_rts-0 {
162 atmel,pins =
163 <3 5 0x2 0x0>; /* PD5 periph B */
164 };
165
166 pinctrl_usart2_cts: usart2_cts-0 {
167 atmel,pins =
168 <4 6 0x2 0x0>; /* PD6 periph B */
169 };
170 };
171
172 nand {
173 pinctrl_nand: nand-0 {
174 atmel,pins =
175 <0 22 0x0 0x1 /* PA22 gpio RDY pin pull_up*/
176 3 15 0x0 0x1>; /* PD15 gpio enable pin pull_up */
177 };
178 };
179
180 macb {
181 pinctrl_macb_rmii: macb_rmii-0 {
182 atmel,pins =
183 <2 25 0x2 0x0 /* PC25 periph B */
184 4 21 0x1 0x0 /* PE21 periph A */
185 4 23 0x1 0x0 /* PE23 periph A */
186 4 24 0x1 0x0 /* PE24 periph A */
187 4 25 0x1 0x0 /* PE25 periph A */
188 4 26 0x1 0x0 /* PE26 periph A */
189 4 27 0x1 0x0 /* PE27 periph A */
190 4 28 0x1 0x0 /* PE28 periph A */
191 4 29 0x1 0x0 /* PE29 periph A */
192 4 30 0x1 0x0>; /* PE30 periph A */
193 };
194
195 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
196 atmel,pins =
197 <2 20 0x2 0x0 /* PC20 periph B */
198 2 21 0x2 0x0 /* PC21 periph B */
199 2 22 0x2 0x0 /* PC22 periph B */
200 2 23 0x2 0x0 /* PC23 periph B */
201 2 24 0x2 0x0 /* PC24 periph B */
202 2 25 0x2 0x0 /* PC25 periph B */
203 2 27 0x2 0x0 /* PC27 periph B */
204 4 22 0x2 0x0>; /* PE22 periph B */
205 };
206 };
207
208 mmc0 {
209 pinctrl_mmc0_clk: mmc0_clk-0 {
210 atmel,pins =
211 <0 12 0x1 0x0>; /* PA12 periph A */
212 };
213
214 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
215 atmel,pins =
216 <0 1 0x1 0x1 /* PA1 periph A with pullup */
217 0 0 0x1 0x1>; /* PA0 periph A with pullup */
218 };
219
220 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
221 atmel,pins =
222 <0 3 0x1 0x1 /* PA3 periph A with pullup */
223 0 4 0x1 0x1 /* PA4 periph A with pullup */
224 0 5 0x1 0x1>; /* PA5 periph A with pullup */
225 };
226
227 pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
228 atmel,pins =
229 <0 16 0x1 0x1 /* PA16 periph A with pullup */
230 0 17 0x1 0x1>; /* PA17 periph A with pullup */
231 };
232
233 pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
234 atmel,pins =
235 <0 18 0x1 0x1 /* PA18 periph A with pullup */
236 0 19 0x1 0x1 /* PA19 periph A with pullup */
237 0 20 0x1 0x1>; /* PA20 periph A with pullup */
238 };
239 };
240
241 mmc1 {
242 pinctrl_mmc1_clk: mmc1_clk-0 {
243 atmel,pins =
244 <0 6 0x1 0x0>; /* PA6 periph A */
245 };
246
247 pinctrl_mmc1_slot0_cmd_dat0: mmc1_slot0_cmd_dat0-0 {
248 atmel,pins =
249 <0 7 0x1 0x1 /* PA7 periph A with pullup */
250 0 8 0x1 0x1>; /* PA8 periph A with pullup */
251 };
252
253 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
254 atmel,pins =
255 <0 9 0x1 0x1 /* PA9 periph A with pullup */
256 0 10 0x1 0x1 /* PA10 periph A with pullup */
257 0 11 0x1 0x1>; /* PA11 periph A with pullup */
258 };
259
260 pinctrl_mmc1_slot1_cmd_dat0: mmc1_slot1_cmd_dat0-0 {
261 atmel,pins =
262 <0 21 0x1 0x1 /* PA21 periph A with pullup */
263 0 22 0x1 0x1>; /* PA22 periph A with pullup */
264 };
265
266 pinctrl_mmc1_slot1_dat1_3: mmc1_slot1_dat1_3-0 {
267 atmel,pins =
268 <0 23 0x1 0x1 /* PA23 periph A with pullup */
269 0 24 0x1 0x1 /* PA24 periph A with pullup */
270 0 25 0x1 0x1>; /* PA25 periph A with pullup */
271 };
272 };
273
274 pioA: gpio@fffff200 {
275 compatible = "atmel,at91rm9200-gpio";
276 reg = <0xfffff200 0x200>;
277 interrupts = <2 4 1>;
278 #gpio-cells = <2>;
279 gpio-controller;
280 interrupt-controller;
281 #interrupt-cells = <2>;
282 };
283
284 pioB: gpio@fffff400 {
285 compatible = "atmel,at91rm9200-gpio";
286 reg = <0xfffff400 0x200>;
287 interrupts = <3 4 1>;
288 #gpio-cells = <2>;
289 gpio-controller;
290 interrupt-controller;
291 #interrupt-cells = <2>;
292 };
293
294 pioC: gpio@fffff600 {
295 compatible = "atmel,at91rm9200-gpio";
296 reg = <0xfffff600 0x200>;
297 interrupts = <4 4 1>;
298 #gpio-cells = <2>;
299 gpio-controller;
300 interrupt-controller;
301 #interrupt-cells = <2>;
302 };
303
304 pioD: gpio@fffff800 {
305 compatible = "atmel,at91rm9200-gpio";
306 reg = <0xfffff800 0x200>;
307 interrupts = <4 4 1>;
308 #gpio-cells = <2>;
309 gpio-controller;
310 interrupt-controller;
311 #interrupt-cells = <2>;
312 };
313
314 pioE: gpio@fffffa00 {
315 compatible = "atmel,at91rm9200-gpio";
316 reg = <0xfffffa00 0x200>;
317 interrupts = <4 4 1>;
318 #gpio-cells = <2>;
319 gpio-controller;
320 interrupt-controller;
321 #interrupt-cells = <2>;
322 };
323 };
324
325 dbgu: serial@ffffee00 {
326 compatible = "atmel,at91sam9260-usart";
327 reg = <0xffffee00 0x200>;
328 interrupts = <1 4 7>;
329 pinctrl-names = "default";
330 pinctrl-0 = <&pinctrl_dbgu>;
331 status = "disabled";
332 };
333
334 usart0: serial@fff8c000 {
335 compatible = "atmel,at91sam9260-usart";
336 reg = <0xfff8c000 0x200>;
337 interrupts = <7 4 5>;
338 atmel,use-dma-rx;
339 atmel,use-dma-tx;
340 pinctrl-names = "default";
341 pinctrl-0 = <&pinctrl_usart0>;
342 status = "disabled";
343 };
344
345 usart1: serial@fff90000 {
346 compatible = "atmel,at91sam9260-usart";
347 reg = <0xfff90000 0x200>;
348 interrupts = <8 4 5>;
349 atmel,use-dma-rx;
350 atmel,use-dma-tx;
351 pinctrl-names = "default";
352 pinctrl-0 = <&pinctrl_usart1>;
353 status = "disabled";
354 };
355
356 usart2: serial@fff94000 {
357 compatible = "atmel,at91sam9260-usart";
358 reg = <0xfff94000 0x200>;
359 interrupts = <9 4 5>;
360 atmel,use-dma-rx;
361 atmel,use-dma-tx;
362 pinctrl-names = "default";
363 pinctrl-0 = <&pinctrl_usart2>;
364 status = "disabled";
365 };
366
367 ssc0: ssc@fff98000 {
368 compatible = "atmel,at91rm9200-ssc";
369 reg = <0xfff98000 0x4000>;
370 interrupts = <16 4 5>;
371 status = "disabled";
372 };
373
374 ssc1: ssc@fff9c000 {
375 compatible = "atmel,at91rm9200-ssc";
376 reg = <0xfff9c000 0x4000>;
377 interrupts = <17 4 5>;
378 status = "disabled";
379 };
380
381 macb0: ethernet@fffbc000 {
382 compatible = "cdns,at32ap7000-macb", "cdns,macb";
383 reg = <0xfffbc000 0x100>;
384 interrupts = <21 4 3>;
385 pinctrl-names = "default";
386 pinctrl-0 = <&pinctrl_macb_rmii>;
387 status = "disabled";
388 };
389
390 usb1: gadget@fff78000 {
391 compatible = "atmel,at91rm9200-udc";
392 reg = <0xfff78000 0x4000>;
393 interrupts = <24 4 2>;
394 status = "disabled";
395 };
396
397 i2c0: i2c@fff88000 {
398 compatible = "atmel,at91sam9263-i2c";
399 reg = <0xfff88000 0x100>;
400 interrupts = <13 4 6>;
401 #address-cells = <1>;
402 #size-cells = <0>;
403 status = "disabled";
404 };
405
406 mmc0: mmc@fff80000 {
407 compatible = "atmel,hsmci";
408 reg = <0xfff80000 0x600>;
409 interrupts = <10 4 0>;
410 #address-cells = <1>;
411 #size-cells = <0>;
412 status = "disabled";
413 };
414
415 mmc1: mmc@fff84000 {
416 compatible = "atmel,hsmci";
417 reg = <0xfff84000 0x600>;
418 interrupts = <11 4 0>;
419 #address-cells = <1>;
420 #size-cells = <0>;
421 status = "disabled";
422 };
423
424 watchdog@fffffd40 {
425 compatible = "atmel,at91sam9260-wdt";
426 reg = <0xfffffd40 0x10>;
427 status = "disabled";
428 };
429 };
430
431 nand0: nand@40000000 {
432 compatible = "atmel,at91rm9200-nand";
433 #address-cells = <1>;
434 #size-cells = <1>;
435 reg = <0x40000000 0x10000000
436 0xffffe000 0x200
437 >;
438 atmel,nand-addr-offset = <21>;
439 atmel,nand-cmd-offset = <22>;
440 pinctrl-names = "default";
441 pinctrl-0 = <&pinctrl_nand>;
442 gpios = <&pioA 22 0
443 &pioD 15 0
444 0
445 >;
446 status = "disabled";
447 };
448
449 usb0: ohci@00a00000 {
450 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
451 reg = <0x00a00000 0x100000>;
452 interrupts = <29 4 2>;
453 status = "disabled";
454 };
455 };
456
457 i2c@0 {
458 compatible = "i2c-gpio";
459 gpios = <&pioB 4 0 /* sda */
460 &pioB 5 0 /* scl */
461 >;
462 i2c-gpio,sda-open-drain;
463 i2c-gpio,scl-open-drain;
464 i2c-gpio,delay-us = <2>; /* ~100 kHz */
465 #address-cells = <1>;
466 #size-cells = <0>;
467 status = "disabled";
468 };
469};
diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts
deleted file mode 100644
index 1eb08728f52..00000000000
--- a/arch/arm/boot/dts/at91sam9263ek.dts
+++ /dev/null
@@ -1,185 +0,0 @@
1/*
2 * at91sam9263ek.dts - Device Tree file for Atmel at91sam9263 reference board
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2 only
7 */
8/dts-v1/;
9/include/ "at91sam9263.dtsi"
10
11/ {
12 model = "Atmel at91sam9263ek";
13 compatible = "atmel,at91sam9263ek", "atmel,at91sam9263", "atmel,at91sam9";
14
15 chosen {
16 bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
17 };
18
19 memory {
20 reg = <0x20000000 0x4000000>;
21 };
22
23 clocks {
24 #address-cells = <1>;
25 #size-cells = <1>;
26 ranges;
27
28 main_clock: clock@0 {
29 compatible = "atmel,osc", "fixed-clock";
30 clock-frequency = <16367660>;
31 };
32 };
33
34 ahb {
35 apb {
36 dbgu: serial@ffffee00 {
37 status = "okay";
38 };
39
40 usart0: serial@fff8c000 {
41 pinctrl-0 = <
42 &pinctrl_usart0
43 &pinctrl_usart0_rts
44 &pinctrl_usart0_cts>;
45 status = "okay";
46 };
47
48 macb0: ethernet@fffbc000 {
49 phy-mode = "rmii";
50 status = "okay";
51 };
52
53 usb1: gadget@fff78000 {
54 atmel,vbus-gpio = <&pioA 25 0>;
55 status = "okay";
56 };
57
58 mmc0: mmc@fff80000 {
59 pinctrl-0 = <
60 &pinctrl_board_mmc0
61 &pinctrl_mmc0_clk
62 &pinctrl_mmc0_slot0_cmd_dat0
63 &pinctrl_mmc0_slot0_dat1_3>;
64 status = "okay";
65 slot@0 {
66 reg = <0>;
67 bus-width = <4>;
68 cd-gpios = <&pioE 18 0>;
69 wp-gpios = <&pioE 19 0>;
70 };
71 };
72
73 pinctrl@fffff200 {
74 mmc0 {
75 pinctrl_board_mmc0: mmc0-board {
76 atmel,pins =
77 <5 18 0x0 0x5 /* PE18 gpio CD pin pull up and deglitch */
78 5 19 0x0 0x1>; /* PE19 gpio WP pin pull up */
79 };
80 };
81 };
82 };
83
84 nand0: nand@40000000 {
85 nand-bus-width = <8>;
86 nand-ecc-mode = "soft";
87 nand-on-flash-bbt = <1>;
88 status = "okay";
89
90 at91bootstrap@0 {
91 label = "at91bootstrap";
92 reg = <0x0 0x20000>;
93 };
94
95 barebox@20000 {
96 label = "barebox";
97 reg = <0x20000 0x40000>;
98 };
99
100 bareboxenv@60000 {
101 label = "bareboxenv";
102 reg = <0x60000 0x20000>;
103 };
104
105 bareboxenv2@80000 {
106 label = "bareboxenv2";
107 reg = <0x80000 0x20000>;
108 };
109
110 oftree@80000 {
111 label = "oftree";
112 reg = <0xa0000 0x20000>;
113 };
114
115 kernel@a0000 {
116 label = "kernel";
117 reg = <0xc0000 0x400000>;
118 };
119
120 rootfs@4a0000 {
121 label = "rootfs";
122 reg = <0x4c0000 0x7800000>;
123 };
124
125 data@7ca0000 {
126 label = "data";
127 reg = <0x7cc0000 0x8340000>;
128 };
129 };
130
131 usb0: ohci@00a00000 {
132 num-ports = <2>;
133 status = "okay";
134 atmel,vbus-gpio = <&pioA 24 0
135 &pioA 21 0
136 >;
137 };
138 };
139
140 leds {
141 compatible = "gpio-leds";
142
143 d3 {
144 label = "d3";
145 gpios = <&pioB 7 0>;
146 linux,default-trigger = "heartbeat";
147 };
148
149 d2 {
150 label = "d2";
151 gpios = <&pioC 29 1>;
152 linux,default-trigger = "nand-disk";
153 };
154 };
155
156 gpio_keys {
157 compatible = "gpio-keys";
158 #address-cells = <1>;
159 #size-cells = <0>;
160
161 left_click {
162 label = "left_click";
163 gpios = <&pioC 5 1>;
164 linux,code = <272>;
165 gpio-key,wakeup;
166 };
167
168 right_click {
169 label = "right_click";
170 gpios = <&pioC 4 1>;
171 linux,code = <273>;
172 gpio-key,wakeup;
173 };
174 };
175
176 i2c@0 {
177 status = "okay";
178
179 24c512@50 {
180 compatible = "24c512";
181 reg = <0x50>;
182 pagesize = <128>;
183 };
184 };
185};
diff --git a/arch/arm/boot/dts/at91sam9g15.dtsi b/arch/arm/boot/dts/at91sam9g15.dtsi
deleted file mode 100644
index fbe7a7089c2..00000000000
--- a/arch/arm/boot/dts/at91sam9g15.dtsi
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * at91sam9g15.dtsi - Device Tree Include file for AT91SAM9G15 SoC
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8
9/include/ "at91sam9x5.dtsi"
10
11/ {
12 model = "Atmel AT91SAM9G15 SoC";
13 compatible = "atmel, at91sam9g15, atmel,at91sam9x5";
14
15 ahb {
16 apb {
17 pinctrl@fffff400 {
18 atmel,mux-mask = <
19 /* A B C */
20 0xffffffff 0xffe0399f 0x00000000 /* pioA */
21 0x00040000 0x00047e3f 0x00000000 /* pioB */
22 0xfdffffff 0x00000000 0xb83fffff /* pioC */
23 0x003fffff 0x003f8000 0x00000000 /* pioD */
24 >;
25 };
26 };
27 };
28};
diff --git a/arch/arm/boot/dts/at91sam9g15ek.dts b/arch/arm/boot/dts/at91sam9g15ek.dts
deleted file mode 100644
index 86dd3f6d938..00000000000
--- a/arch/arm/boot/dts/at91sam9g15ek.dts
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * at91sam9g15ek.dts - Device Tree file for AT91SAM9G15-EK board
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/dts-v1/;
10/include/ "at91sam9g15.dtsi"
11/include/ "at91sam9x5ek.dtsi"
12
13/ {
14 model = "Atmel AT91SAM9G25-EK";
15 compatible = "atmel,at91sam9g15ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
16};
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
deleted file mode 100644
index 75ce6e76001..00000000000
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * at91sam9g20.dtsi - Device Tree Include file for AT91SAM9G20 family SoC
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8
9/include/ "at91sam9260.dtsi"
10
11/ {
12 model = "Atmel AT91SAM9G20 family SoC";
13 compatible = "atmel,at91sam9g20";
14
15 memory {
16 reg = <0x20000000 0x08000000>;
17 };
18
19 ahb {
20 apb {
21 i2c0: i2c@fffac000 {
22 compatible = "atmel,at91sam9g20-i2c";
23 };
24
25 adc0: adc@fffe0000 {
26 atmel,adc-startup-time = <40>;
27 };
28 };
29 };
30};
diff --git a/arch/arm/boot/dts/at91sam9g20ek.dts b/arch/arm/boot/dts/at91sam9g20ek.dts
deleted file mode 100644
index e5324bf9d52..00000000000
--- a/arch/arm/boot/dts/at91sam9g20ek.dts
+++ /dev/null
@@ -1,29 +0,0 @@
1/*
2 * at91sam9g20ek.dts - Device Tree file for Atmel at91sam9g20ek board
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8/dts-v1/;
9/include/ "at91sam9g20ek_common.dtsi"
10
11/ {
12 model = "Atmel at91sam9g20ek";
13 compatible = "atmel,at91sam9g20ek", "atmel,at91sam9g20", "atmel,at91sam9";
14
15 leds {
16 compatible = "gpio-leds";
17
18 ds1 {
19 label = "ds1";
20 gpios = <&pioA 9 0>;
21 linux,default-trigger = "heartbeat";
22 };
23
24 ds5 {
25 label = "ds5";
26 gpios = <&pioA 6 1>;
27 };
28 };
29};
diff --git a/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts b/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts
deleted file mode 100644
index 66467b11312..00000000000
--- a/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts
+++ /dev/null
@@ -1,55 +0,0 @@
1/*
2 * at91sam9g20ek_2mmc.dts - Device Tree file for Atmel at91sam9g20ek 2 MMC board
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8/dts-v1/;
9/include/ "at91sam9g20ek_common.dtsi"
10
11/ {
12 model = "Atmel at91sam9g20ek 2 mmc";
13 compatible = "atmel,at91sam9g20ek_2mmc", "atmel,at91sam9g20", "atmel,at91sam9";
14
15 ahb {
16 apb{
17 mmc0: mmc@fffa8000 {
18 /* clk already mux wuth slot0 */
19 pinctrl-0 = <
20 &pinctrl_board_mmc0_slot0
21 &pinctrl_mmc0_slot0_cmd_dat0
22 &pinctrl_mmc0_slot0_dat1_3>;
23 slot@0 {
24 reg = <0>;
25 bus-width = <4>;
26 cd-gpios = <&pioC 2 0>;
27 };
28 };
29
30 pinctrl@fffff400 {
31 mmc0_slot0 {
32 pinctrl_board_mmc0_slot0: mmc0_slot0-board {
33 atmel,pins =
34 <2 2 0x0 0x5>; /* PC2 gpio CD pin pull up and deglitch */
35 };
36 };
37 };
38 };
39 };
40
41 leds {
42 compatible = "gpio-leds";
43
44 ds1 {
45 label = "ds1";
46 gpios = <&pioB 9 0>;
47 linux,default-trigger = "heartbeat";
48 };
49
50 ds5 {
51 label = "ds5";
52 gpios = <&pioB 8 1>;
53 };
54 };
55};
diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
deleted file mode 100644
index da15e83e7f1..00000000000
--- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
+++ /dev/null
@@ -1,202 +0,0 @@
1/*
2 * at91sam9g20ek_common.dtsi - Device Tree file for Atmel at91sam9g20ek board
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8/include/ "at91sam9g20.dtsi"
9
10/ {
11
12 chosen {
13 bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
14 };
15
16 memory {
17 reg = <0x20000000 0x4000000>;
18 };
19
20 clocks {
21 #address-cells = <1>;
22 #size-cells = <1>;
23 ranges;
24
25 main_clock: clock@0 {
26 compatible = "atmel,osc", "fixed-clock";
27 clock-frequency = <18432000>;
28 };
29 };
30
31 ahb {
32 apb {
33 pinctrl@fffff400 {
34 board {
35 pinctrl_pck0_as_mck: pck0_as_mck {
36 atmel,pins =
37 <2 1 0x2 0x0>; /* PC1 periph B */
38 };
39
40 };
41 };
42
43 dbgu: serial@fffff200 {
44 status = "okay";
45 };
46
47 usart0: serial@fffb0000 {
48 pinctrl-0 =
49 <&pinctrl_usart0
50 &pinctrl_usart0_rts
51 &pinctrl_usart0_cts
52 &pinctrl_usart0_dtr_dsr
53 &pinctrl_usart0_dcd
54 &pinctrl_usart0_ri>;
55 status = "okay";
56 };
57
58 usart1: serial@fffb4000 {
59 status = "okay";
60 };
61
62 macb0: ethernet@fffc4000 {
63 phy-mode = "rmii";
64 status = "okay";
65 };
66
67 usb1: gadget@fffa4000 {
68 atmel,vbus-gpio = <&pioC 5 0>;
69 status = "okay";
70 };
71
72 mmc0: mmc@fffa8000 {
73 pinctrl-0 = <
74 &pinctrl_board_mmc0_slot1
75 &pinctrl_mmc0_clk
76 &pinctrl_mmc0_slot1_cmd_dat0
77 &pinctrl_mmc0_slot1_dat1_3>;
78 status = "okay";
79 slot@1 {
80 reg = <1>;
81 bus-width = <4>;
82 cd-gpios = <&pioC 9 0>;
83 };
84 };
85
86 pinctrl@fffff400 {
87 mmc0_slot1 {
88 pinctrl_board_mmc0_slot1: mmc0_slot1-board {
89 atmel,pins =
90 <2 9 0x0 0x5>; /* PC9 gpio CD pin pull up and deglitch */
91 };
92 };
93 };
94
95 ssc0: ssc@fffbc000 {
96 status = "okay";
97 pinctrl-0 = <&pinctrl_ssc0_tx>;
98 };
99 };
100
101 nand0: nand@40000000 {
102 nand-bus-width = <8>;
103 nand-ecc-mode = "soft";
104 nand-on-flash-bbt;
105 status = "okay";
106
107 at91bootstrap@0 {
108 label = "at91bootstrap";
109 reg = <0x0 0x20000>;
110 };
111
112 barebox@20000 {
113 label = "barebox";
114 reg = <0x20000 0x40000>;
115 };
116
117 bareboxenv@60000 {
118 label = "bareboxenv";
119 reg = <0x60000 0x20000>;
120 };
121
122 bareboxenv2@80000 {
123 label = "bareboxenv2";
124 reg = <0x80000 0x20000>;
125 };
126
127 oftree@80000 {
128 label = "oftree";
129 reg = <0xa0000 0x20000>;
130 };
131
132 kernel@a0000 {
133 label = "kernel";
134 reg = <0xc0000 0x400000>;
135 };
136
137 rootfs@4a0000 {
138 label = "rootfs";
139 reg = <0x4c0000 0x7800000>;
140 };
141
142 data@7ca0000 {
143 label = "data";
144 reg = <0x7cc0000 0x8340000>;
145 };
146 };
147
148 usb0: ohci@00500000 {
149 num-ports = <2>;
150 status = "okay";
151 };
152 };
153
154 i2c@0 {
155 status = "okay";
156
157 24c512@50 {
158 compatible = "24c512";
159 reg = <0x50>;
160 };
161
162 wm8731: wm8731@1b {
163 compatible = "wm8731";
164 reg = <0x1b>;
165 };
166 };
167
168 gpio_keys {
169 compatible = "gpio-keys";
170 #address-cells = <1>;
171 #size-cells = <0>;
172
173 btn3 {
174 label = "Button 3";
175 gpios = <&pioA 30 1>;
176 linux,code = <0x103>;
177 gpio-key,wakeup;
178 };
179
180 btn4 {
181 label = "Button 4";
182 gpios = <&pioA 31 1>;
183 linux,code = <0x104>;
184 gpio-key,wakeup;
185 };
186 };
187
188 sound {
189 compatible = "atmel,at91sam9g20ek-wm8731-audio";
190 pinctrl-names = "default";
191 pinctrl-0 = <&pinctrl_pck0_as_mck>;
192
193 atmel,model = "wm8731 @ AT91SAMG20EK";
194
195 atmel,audio-routing =
196 "Ext Spk", "LHPOUT",
197 "Int Mic", "MICIN";
198
199 atmel,ssc-controller = <&ssc0>;
200 atmel,audio-codec = <&wm8731>;
201 };
202};
diff --git a/arch/arm/boot/dts/at91sam9g25.dtsi b/arch/arm/boot/dts/at91sam9g25.dtsi
deleted file mode 100644
index 05a718fb83c..00000000000
--- a/arch/arm/boot/dts/at91sam9g25.dtsi
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * at91sam9g25.dtsi - Device Tree Include file for AT91SAM9G25 SoC
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8
9/include/ "at91sam9x5.dtsi"
10
11/ {
12 model = "Atmel AT91SAM9G25 SoC";
13 compatible = "atmel, at91sam9g25, atmel,at91sam9x5";
14
15 ahb {
16 apb {
17 pinctrl@fffff400 {
18 atmel,mux-mask = <
19 /* A B C */
20 0xffffffff 0xffe0399f 0xc000001c /* pioA */
21 0x0007ffff 0x8000fe3f 0x00000000 /* pioB */
22 0x80000000 0x07c0ffff 0xb83fffff /* pioC */
23 0x003fffff 0x003f8000 0x00000000 /* pioD */
24 >;
25 };
26 };
27 };
28};
diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts
deleted file mode 100644
index c5ab16fba05..00000000000
--- a/arch/arm/boot/dts/at91sam9g25ek.dts
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * at91sam9g25ek.dts - Device Tree file for AT91SAM9G25-EK board
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/dts-v1/;
10/include/ "at91sam9g25.dtsi"
11/include/ "at91sam9x5ek.dtsi"
12
13/ {
14 model = "Atmel AT91SAM9G25-EK";
15 compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
16};
diff --git a/arch/arm/boot/dts/at91sam9g35.dtsi b/arch/arm/boot/dts/at91sam9g35.dtsi
deleted file mode 100644
index f9d14a72279..00000000000
--- a/arch/arm/boot/dts/at91sam9g35.dtsi
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * at91sam9g35.dtsi - Device Tree Include file for AT91SAM9G35 SoC
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8
9/include/ "at91sam9x5.dtsi"
10
11/ {
12 model = "Atmel AT91SAM9G35 SoC";
13 compatible = "atmel, at91sam9g35, atmel,at91sam9x5";
14
15 ahb {
16 apb {
17 pinctrl@fffff400 {
18 atmel,mux-mask = <
19 /* A B C */
20 0xffffffff 0xffe0399f 0xc000000c /* pioA */
21 0x000406ff 0x00047e3f 0x00000000 /* pioB */
22 0xfdffffff 0x00000000 0xb83fffff /* pioC */
23 0x003fffff 0x003f8000 0x00000000 /* pioD */
24 >;
25 };
26 };
27 };
28};
diff --git a/arch/arm/boot/dts/at91sam9g35ek.dts b/arch/arm/boot/dts/at91sam9g35ek.dts
deleted file mode 100644
index 95944bdd798..00000000000
--- a/arch/arm/boot/dts/at91sam9g35ek.dts
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * at91sam9g35ek.dts - Device Tree file for AT91SAM9G35-EK board
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/dts-v1/;
10/include/ "at91sam9g35.dtsi"
11/include/ "at91sam9x5ek.dtsi"
12
13/ {
14 model = "Atmel AT91SAM9G35-EK";
15 compatible = "atmel,at91sam9g35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
16};
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
deleted file mode 100644
index 231858ffd85..00000000000
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ /dev/null
@@ -1,545 +0,0 @@
1/*
2 * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
3 * applies to AT91SAM9G45, AT91SAM9M10,
4 * AT91SAM9G46, AT91SAM9M11 SoC
5 *
6 * Copyright (C) 2011 Atmel,
7 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
8 *
9 * Licensed under GPLv2 or later.
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 model = "Atmel AT91SAM9G45 family SoC";
16 compatible = "atmel,at91sam9g45";
17 interrupt-parent = <&aic>;
18
19 aliases {
20 serial0 = &dbgu;
21 serial1 = &usart0;
22 serial2 = &usart1;
23 serial3 = &usart2;
24 serial4 = &usart3;
25 gpio0 = &pioA;
26 gpio1 = &pioB;
27 gpio2 = &pioC;
28 gpio3 = &pioD;
29 gpio4 = &pioE;
30 tcb0 = &tcb0;
31 tcb1 = &tcb1;
32 i2c0 = &i2c0;
33 i2c1 = &i2c1;
34 ssc0 = &ssc0;
35 ssc1 = &ssc1;
36 };
37 cpus {
38 cpu@0 {
39 compatible = "arm,arm926ejs";
40 };
41 };
42
43 memory {
44 reg = <0x70000000 0x10000000>;
45 };
46
47 ahb {
48 compatible = "simple-bus";
49 #address-cells = <1>;
50 #size-cells = <1>;
51 ranges;
52
53 apb {
54 compatible = "simple-bus";
55 #address-cells = <1>;
56 #size-cells = <1>;
57 ranges;
58
59 aic: interrupt-controller@fffff000 {
60 #interrupt-cells = <3>;
61 compatible = "atmel,at91rm9200-aic";
62 interrupt-controller;
63 reg = <0xfffff000 0x200>;
64 atmel,external-irqs = <31>;
65 };
66
67 ramc0: ramc@ffffe400 {
68 compatible = "atmel,at91sam9g45-ddramc";
69 reg = <0xffffe400 0x200
70 0xffffe600 0x200>;
71 };
72
73 pmc: pmc@fffffc00 {
74 compatible = "atmel,at91rm9200-pmc";
75 reg = <0xfffffc00 0x100>;
76 };
77
78 rstc@fffffd00 {
79 compatible = "atmel,at91sam9g45-rstc";
80 reg = <0xfffffd00 0x10>;
81 };
82
83 pit: timer@fffffd30 {
84 compatible = "atmel,at91sam9260-pit";
85 reg = <0xfffffd30 0xf>;
86 interrupts = <1 4 7>;
87 };
88
89
90 shdwc@fffffd10 {
91 compatible = "atmel,at91sam9rl-shdwc";
92 reg = <0xfffffd10 0x10>;
93 };
94
95 tcb0: timer@fff7c000 {
96 compatible = "atmel,at91rm9200-tcb";
97 reg = <0xfff7c000 0x100>;
98 interrupts = <18 4 0>;
99 };
100
101 tcb1: timer@fffd4000 {
102 compatible = "atmel,at91rm9200-tcb";
103 reg = <0xfffd4000 0x100>;
104 interrupts = <18 4 0>;
105 };
106
107 dma: dma-controller@ffffec00 {
108 compatible = "atmel,at91sam9g45-dma";
109 reg = <0xffffec00 0x200>;
110 interrupts = <21 4 0>;
111 };
112
113 pinctrl@fffff200 {
114 #address-cells = <1>;
115 #size-cells = <1>;
116 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
117 ranges = <0xfffff200 0xfffff200 0xa00>;
118
119 atmel,mux-mask = <
120 /* A B */
121 0xffffffff 0xffc003ff /* pioA */
122 0xffffffff 0x800f8f00 /* pioB */
123 0xffffffff 0x00000e00 /* pioC */
124 0xffffffff 0xff0c1381 /* pioD */
125 0xffffffff 0x81ffff81 /* pioE */
126 >;
127
128 /* shared pinctrl settings */
129 dbgu {
130 pinctrl_dbgu: dbgu-0 {
131 atmel,pins =
132 <1 12 0x1 0x0 /* PB12 periph A */
133 1 13 0x1 0x0>; /* PB13 periph A */
134 };
135 };
136
137 usart0 {
138 pinctrl_usart0: usart0-0 {
139 atmel,pins =
140 <1 19 0x1 0x1 /* PB19 periph A with pullup */
141 1 18 0x1 0x0>; /* PB18 periph A */
142 };
143
144 pinctrl_usart0_rts: usart0_rts-0 {
145 atmel,pins =
146 <1 17 0x2 0x0>; /* PB17 periph B */
147 };
148
149 pinctrl_usart0_cts: usart0_cts-0 {
150 atmel,pins =
151 <1 15 0x2 0x0>; /* PB15 periph B */
152 };
153 };
154
155 uart1 {
156 pinctrl_usart1: usart1-0 {
157 atmel,pins =
158 <1 4 0x1 0x1 /* PB4 periph A with pullup */
159 1 5 0x1 0x0>; /* PB5 periph A */
160 };
161
162 pinctrl_usart1_rts: usart1_rts-0 {
163 atmel,pins =
164 <3 16 0x1 0x0>; /* PD16 periph A */
165 };
166
167 pinctrl_usart1_cts: usart1_cts-0 {
168 atmel,pins =
169 <3 17 0x1 0x0>; /* PD17 periph A */
170 };
171 };
172
173 usart2 {
174 pinctrl_usart2: usart2-0 {
175 atmel,pins =
176 <1 6 0x1 0x1 /* PB6 periph A with pullup */
177 1 7 0x1 0x0>; /* PB7 periph A */
178 };
179
180 pinctrl_usart2_rts: usart2_rts-0 {
181 atmel,pins =
182 <2 9 0x2 0x0>; /* PC9 periph B */
183 };
184
185 pinctrl_usart2_cts: usart2_cts-0 {
186 atmel,pins =
187 <2 11 0x2 0x0>; /* PC11 periph B */
188 };
189 };
190
191 usart3 {
192 pinctrl_usart3: usart3-0 {
193 atmel,pins =
194 <1 8 0x1 0x1 /* PB9 periph A with pullup */
195 1 9 0x1 0x0>; /* PB8 periph A */
196 };
197
198 pinctrl_usart3_rts: usart3_rts-0 {
199 atmel,pins =
200 <0 23 0x2 0x0>; /* PA23 periph B */
201 };
202
203 pinctrl_usart3_cts: usart3_cts-0 {
204 atmel,pins =
205 <0 24 0x2 0x0>; /* PA24 periph B */
206 };
207 };
208
209 nand {
210 pinctrl_nand: nand-0 {
211 atmel,pins =
212 <2 8 0x0 0x1 /* PC8 gpio RDY pin pull_up*/
213 2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
214 };
215 };
216
217 macb {
218 pinctrl_macb_rmii: macb_rmii-0 {
219 atmel,pins =
220 <0 10 0x1 0x0 /* PA10 periph A */
221 0 11 0x1 0x0 /* PA11 periph A */
222 0 12 0x1 0x0 /* PA12 periph A */
223 0 13 0x1 0x0 /* PA13 periph A */
224 0 14 0x1 0x0 /* PA14 periph A */
225 0 15 0x1 0x0 /* PA15 periph A */
226 0 16 0x1 0x0 /* PA16 periph A */
227 0 17 0x1 0x0 /* PA17 periph A */
228 0 18 0x1 0x0 /* PA18 periph A */
229 0 19 0x1 0x0>; /* PA19 periph A */
230 };
231
232 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
233 atmel,pins =
234 <0 6 0x2 0x0 /* PA6 periph B */
235 0 7 0x2 0x0 /* PA7 periph B */
236 0 8 0x2 0x0 /* PA8 periph B */
237 0 9 0x2 0x0 /* PA9 periph B */
238 0 27 0x2 0x0 /* PA27 periph B */
239 0 28 0x2 0x0 /* PA28 periph B */
240 0 29 0x2 0x0 /* PA29 periph B */
241 0 30 0x2 0x0>; /* PA30 periph B */
242 };
243 };
244
245 mmc0 {
246 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
247 atmel,pins =
248 <0 0 0x1 0x0 /* PA0 periph A */
249 0 1 0x1 0x1 /* PA1 periph A with pullup */
250 0 2 0x1 0x1>; /* PA2 periph A with pullup */
251 };
252
253 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
254 atmel,pins =
255 <0 3 0x1 0x1 /* PA3 periph A with pullup */
256 0 4 0x1 0x1 /* PA4 periph A with pullup */
257 0 5 0x1 0x1>; /* PA5 periph A with pullup */
258 };
259
260 pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
261 atmel,pins =
262 <0 6 0x1 0x1 /* PA6 periph A with pullup */
263 0 7 0x1 0x1 /* PA7 periph A with pullup */
264 0 8 0x1 0x1 /* PA8 periph A with pullup */
265 0 9 0x1 0x1>; /* PA9 periph A with pullup */
266 };
267 };
268
269 mmc1 {
270 pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
271 atmel,pins =
272 <0 31 0x1 0x0 /* PA31 periph A */
273 0 22 0x1 0x1 /* PA22 periph A with pullup */
274 0 23 0x1 0x1>; /* PA23 periph A with pullup */
275 };
276
277 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
278 atmel,pins =
279 <0 24 0x1 0x1 /* PA24 periph A with pullup */
280 0 25 0x1 0x1 /* PA25 periph A with pullup */
281 0 26 0x1 0x1>; /* PA26 periph A with pullup */
282 };
283
284 pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 {
285 atmel,pins =
286 <0 27 0x1 0x1 /* PA27 periph A with pullup */
287 0 28 0x1 0x1 /* PA28 periph A with pullup */
288 0 29 0x1 0x1 /* PA29 periph A with pullup */
289 0 20 0x1 0x1>; /* PA30 periph A with pullup */
290 };
291 };
292
293 pioA: gpio@fffff200 {
294 compatible = "atmel,at91rm9200-gpio";
295 reg = <0xfffff200 0x200>;
296 interrupts = <2 4 1>;
297 #gpio-cells = <2>;
298 gpio-controller;
299 interrupt-controller;
300 #interrupt-cells = <2>;
301 };
302
303 pioB: gpio@fffff400 {
304 compatible = "atmel,at91rm9200-gpio";
305 reg = <0xfffff400 0x200>;
306 interrupts = <3 4 1>;
307 #gpio-cells = <2>;
308 gpio-controller;
309 interrupt-controller;
310 #interrupt-cells = <2>;
311 };
312
313 pioC: gpio@fffff600 {
314 compatible = "atmel,at91rm9200-gpio";
315 reg = <0xfffff600 0x200>;
316 interrupts = <4 4 1>;
317 #gpio-cells = <2>;
318 gpio-controller;
319 interrupt-controller;
320 #interrupt-cells = <2>;
321 };
322
323 pioD: gpio@fffff800 {
324 compatible = "atmel,at91rm9200-gpio";
325 reg = <0xfffff800 0x200>;
326 interrupts = <5 4 1>;
327 #gpio-cells = <2>;
328 gpio-controller;
329 interrupt-controller;
330 #interrupt-cells = <2>;
331 };
332
333 pioE: gpio@fffffa00 {
334 compatible = "atmel,at91rm9200-gpio";
335 reg = <0xfffffa00 0x200>;
336 interrupts = <5 4 1>;
337 #gpio-cells = <2>;
338 gpio-controller;
339 interrupt-controller;
340 #interrupt-cells = <2>;
341 };
342 };
343
344 dbgu: serial@ffffee00 {
345 compatible = "atmel,at91sam9260-usart";
346 reg = <0xffffee00 0x200>;
347 interrupts = <1 4 7>;
348 pinctrl-names = "default";
349 pinctrl-0 = <&pinctrl_dbgu>;
350 status = "disabled";
351 };
352
353 usart0: serial@fff8c000 {
354 compatible = "atmel,at91sam9260-usart";
355 reg = <0xfff8c000 0x200>;
356 interrupts = <7 4 5>;
357 atmel,use-dma-rx;
358 atmel,use-dma-tx;
359 pinctrl-names = "default";
360 pinctrl-0 = <&pinctrl_usart0>;
361 status = "disabled";
362 };
363
364 usart1: serial@fff90000 {
365 compatible = "atmel,at91sam9260-usart";
366 reg = <0xfff90000 0x200>;
367 interrupts = <8 4 5>;
368 atmel,use-dma-rx;
369 atmel,use-dma-tx;
370 pinctrl-names = "default";
371 pinctrl-0 = <&pinctrl_usart1>;
372 status = "disabled";
373 };
374
375 usart2: serial@fff94000 {
376 compatible = "atmel,at91sam9260-usart";
377 reg = <0xfff94000 0x200>;
378 interrupts = <9 4 5>;
379 atmel,use-dma-rx;
380 atmel,use-dma-tx;
381 pinctrl-names = "default";
382 pinctrl-0 = <&pinctrl_usart2>;
383 status = "disabled";
384 };
385
386 usart3: serial@fff98000 {
387 compatible = "atmel,at91sam9260-usart";
388 reg = <0xfff98000 0x200>;
389 interrupts = <10 4 5>;
390 atmel,use-dma-rx;
391 atmel,use-dma-tx;
392 pinctrl-names = "default";
393 pinctrl-0 = <&pinctrl_usart3>;
394 status = "disabled";
395 };
396
397 macb0: ethernet@fffbc000 {
398 compatible = "cdns,at32ap7000-macb", "cdns,macb";
399 reg = <0xfffbc000 0x100>;
400 interrupts = <25 4 3>;
401 pinctrl-names = "default";
402 pinctrl-0 = <&pinctrl_macb_rmii>;
403 status = "disabled";
404 };
405
406 i2c0: i2c@fff84000 {
407 compatible = "atmel,at91sam9g10-i2c";
408 reg = <0xfff84000 0x100>;
409 interrupts = <12 4 6>;
410 #address-cells = <1>;
411 #size-cells = <0>;
412 status = "disabled";
413 };
414
415 i2c1: i2c@fff88000 {
416 compatible = "atmel,at91sam9g10-i2c";
417 reg = <0xfff88000 0x100>;
418 interrupts = <13 4 6>;
419 #address-cells = <1>;
420 #size-cells = <0>;
421 status = "disabled";
422 };
423
424 ssc0: ssc@fff9c000 {
425 compatible = "atmel,at91sam9g45-ssc";
426 reg = <0xfff9c000 0x4000>;
427 interrupts = <16 4 5>;
428 status = "disabled";
429 };
430
431 ssc1: ssc@fffa0000 {
432 compatible = "atmel,at91sam9g45-ssc";
433 reg = <0xfffa0000 0x4000>;
434 interrupts = <17 4 5>;
435 status = "disabled";
436 };
437
438 adc0: adc@fffb0000 {
439 compatible = "atmel,at91sam9260-adc";
440 reg = <0xfffb0000 0x100>;
441 interrupts = <20 4 0>;
442 atmel,adc-use-external-triggers;
443 atmel,adc-channels-used = <0xff>;
444 atmel,adc-vref = <3300>;
445 atmel,adc-num-channels = <8>;
446 atmel,adc-startup-time = <40>;
447 atmel,adc-channel-base = <0x30>;
448 atmel,adc-drdy-mask = <0x10000>;
449 atmel,adc-status-register = <0x1c>;
450 atmel,adc-trigger-register = <0x08>;
451
452 trigger@0 {
453 trigger-name = "external-rising";
454 trigger-value = <0x1>;
455 trigger-external;
456 };
457 trigger@1 {
458 trigger-name = "external-falling";
459 trigger-value = <0x2>;
460 trigger-external;
461 };
462
463 trigger@2 {
464 trigger-name = "external-any";
465 trigger-value = <0x3>;
466 trigger-external;
467 };
468
469 trigger@3 {
470 trigger-name = "continuous";
471 trigger-value = <0x6>;
472 };
473 };
474
475 mmc0: mmc@fff80000 {
476 compatible = "atmel,hsmci";
477 reg = <0xfff80000 0x600>;
478 interrupts = <11 4 0>;
479 #address-cells = <1>;
480 #size-cells = <0>;
481 status = "disabled";
482 };
483
484 mmc1: mmc@fffd0000 {
485 compatible = "atmel,hsmci";
486 reg = <0xfffd0000 0x600>;
487 interrupts = <29 4 0>;
488 #address-cells = <1>;
489 #size-cells = <0>;
490 status = "disabled";
491 };
492
493 watchdog@fffffd40 {
494 compatible = "atmel,at91sam9260-wdt";
495 reg = <0xfffffd40 0x10>;
496 status = "disabled";
497 };
498 };
499
500 nand0: nand@40000000 {
501 compatible = "atmel,at91rm9200-nand";
502 #address-cells = <1>;
503 #size-cells = <1>;
504 reg = <0x40000000 0x10000000
505 0xffffe200 0x200
506 >;
507 atmel,nand-addr-offset = <21>;
508 atmel,nand-cmd-offset = <22>;
509 pinctrl-names = "default";
510 pinctrl-0 = <&pinctrl_nand>;
511 gpios = <&pioC 8 0
512 &pioC 14 0
513 0
514 >;
515 status = "disabled";
516 };
517
518 usb0: ohci@00700000 {
519 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
520 reg = <0x00700000 0x100000>;
521 interrupts = <22 4 2>;
522 status = "disabled";
523 };
524
525 usb1: ehci@00800000 {
526 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
527 reg = <0x00800000 0x100000>;
528 interrupts = <22 4 2>;
529 status = "disabled";
530 };
531 };
532
533 i2c@0 {
534 compatible = "i2c-gpio";
535 gpios = <&pioA 20 0 /* sda */
536 &pioA 21 0 /* scl */
537 >;
538 i2c-gpio,sda-open-drain;
539 i2c-gpio,scl-open-drain;
540 i2c-gpio,delay-us = <5>; /* ~100 kHz */
541 #address-cells = <1>;
542 #size-cells = <0>;
543 status = "disabled";
544 };
545};
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
deleted file mode 100644
index 20c31913c27..00000000000
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ /dev/null
@@ -1,212 +0,0 @@
1/*
2 * at91sam9m10g45ek.dts - Device Tree file for AT91SAM9M10G45-EK board
3 *
4 * Copyright (C) 2011 Atmel,
5 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/dts-v1/;
10/include/ "at91sam9g45.dtsi"
11
12/ {
13 model = "Atmel AT91SAM9M10G45-EK";
14 compatible = "atmel,at91sam9m10g45ek", "atmel,at91sam9g45", "atmel,at91sam9";
15
16 chosen {
17 bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=jffs2";
18 };
19
20 memory {
21 reg = <0x70000000 0x4000000>;
22 };
23
24 clocks {
25 #address-cells = <1>;
26 #size-cells = <1>;
27 ranges;
28
29 main_clock: clock@0 {
30 compatible = "atmel,osc", "fixed-clock";
31 clock-frequency = <12000000>;
32 };
33 };
34
35 ahb {
36 apb {
37 dbgu: serial@ffffee00 {
38 status = "okay";
39 };
40
41 usart1: serial@fff90000 {
42 pinctrl-0 =
43 <&pinctrl_usart1
44 &pinctrl_usart1_rts
45 &pinctrl_usart1_cts>;
46 status = "okay";
47 };
48
49 macb0: ethernet@fffbc000 {
50 phy-mode = "rmii";
51 status = "okay";
52 };
53
54 i2c0: i2c@fff84000 {
55 status = "okay";
56 };
57
58 i2c1: i2c@fff88000 {
59 status = "okay";
60 };
61
62 mmc0: mmc@fff80000 {
63 pinctrl-0 = <
64 &pinctrl_board_mmc0
65 &pinctrl_mmc0_slot0_clk_cmd_dat0
66 &pinctrl_mmc0_slot0_dat1_3>;
67 status = "okay";
68 slot@0 {
69 reg = <0>;
70 bus-width = <4>;
71 cd-gpios = <&pioD 10 0>;
72 };
73 };
74
75 mmc1: mmc@fffd0000 {
76 pinctrl-0 = <
77 &pinctrl_board_mmc1
78 &pinctrl_mmc1_slot0_clk_cmd_dat0
79 &pinctrl_mmc1_slot0_dat1_3>;
80 status = "okay";
81 slot@0 {
82 reg = <0>;
83 bus-width = <4>;
84 cd-gpios = <&pioD 11 0>;
85 wp-gpios = <&pioD 29 0>;
86 };
87 };
88
89 pinctrl@fffff200 {
90 mmc0 {
91 pinctrl_board_mmc0: mmc0-board {
92 atmel,pins =
93 <3 10 0x0 0x5>; /* PD10 gpio CD pin pull up and deglitch */
94 };
95 };
96
97 mmc1 {
98 pinctrl_board_mmc1: mmc1-board {
99 atmel,pins =
100 <3 11 0x0 0x5 /* PD11 gpio CD pin pull up and deglitch */
101 3 29 0x0 0x1>; /* PD29 gpio WP pin pull up */
102 };
103 };
104 };
105 };
106
107 nand0: nand@40000000 {
108 nand-bus-width = <8>;
109 nand-ecc-mode = "soft";
110 nand-on-flash-bbt;
111 status = "okay";
112
113 boot@0 {
114 label = "bootstrap/uboot/kernel";
115 reg = <0x0 0x400000>;
116 };
117
118 rootfs@400000 {
119 label = "rootfs";
120 reg = <0x400000 0x3C00000>;
121 };
122
123 data@4000000 {
124 label = "data";
125 reg = <0x4000000 0xC000000>;
126 };
127 };
128
129 usb0: ohci@00700000 {
130 status = "okay";
131 num-ports = <2>;
132 atmel,vbus-gpio = <&pioD 1 1
133 &pioD 3 1>;
134 };
135
136 usb1: ehci@00800000 {
137 status = "okay";
138 };
139 };
140
141 leds {
142 compatible = "gpio-leds";
143
144 d8 {
145 label = "d8";
146 gpios = <&pioD 30 0>;
147 linux,default-trigger = "heartbeat";
148 };
149
150 d6 {
151 label = "d6";
152 gpios = <&pioD 0 1>;
153 linux,default-trigger = "nand-disk";
154 };
155
156 d7 {
157 label = "d7";
158 gpios = <&pioD 31 1>;
159 linux,default-trigger = "mmc0";
160 };
161 };
162
163 gpio_keys {
164 compatible = "gpio-keys";
165 #address-cells = <1>;
166 #size-cells = <0>;
167
168 left_click {
169 label = "left_click";
170 gpios = <&pioB 6 1>;
171 linux,code = <272>;
172 gpio-key,wakeup;
173 };
174
175 right_click {
176 label = "right_click";
177 gpios = <&pioB 7 1>;
178 linux,code = <273>;
179 gpio-key,wakeup;
180 };
181
182 left {
183 label = "Joystick Left";
184 gpios = <&pioB 14 1>;
185 linux,code = <105>;
186 };
187
188 right {
189 label = "Joystick Right";
190 gpios = <&pioB 15 1>;
191 linux,code = <106>;
192 };
193
194 up {
195 label = "Joystick Up";
196 gpios = <&pioB 16 1>;
197 linux,code = <103>;
198 };
199
200 down {
201 label = "Joystick Down";
202 gpios = <&pioB 17 1>;
203 linux,code = <108>;
204 };
205
206 enter {
207 label = "Joystick Press";
208 gpios = <&pioB 18 1>;
209 linux,code = <28>;
210 };
211 };
212};
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
deleted file mode 100644
index e9efb34f437..00000000000
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ /dev/null
@@ -1,400 +0,0 @@
1/*
2 * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Hong Xu <hong.xu@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9
10/include/ "skeleton.dtsi"
11
12/ {
13 model = "Atmel AT91SAM9N12 SoC";
14 compatible = "atmel,at91sam9n12";
15 interrupt-parent = <&aic>;
16
17 aliases {
18 serial0 = &dbgu;
19 serial1 = &usart0;
20 serial2 = &usart1;
21 serial3 = &usart2;
22 serial4 = &usart3;
23 gpio0 = &pioA;
24 gpio1 = &pioB;
25 gpio2 = &pioC;
26 gpio3 = &pioD;
27 tcb0 = &tcb0;
28 tcb1 = &tcb1;
29 i2c0 = &i2c0;
30 i2c1 = &i2c1;
31 };
32 cpus {
33 cpu@0 {
34 compatible = "arm,arm926ejs";
35 };
36 };
37
38 memory {
39 reg = <0x20000000 0x10000000>;
40 };
41
42 ahb {
43 compatible = "simple-bus";
44 #address-cells = <1>;
45 #size-cells = <1>;
46 ranges;
47
48 apb {
49 compatible = "simple-bus";
50 #address-cells = <1>;
51 #size-cells = <1>;
52 ranges;
53
54 aic: interrupt-controller@fffff000 {
55 #interrupt-cells = <3>;
56 compatible = "atmel,at91rm9200-aic";
57 interrupt-controller;
58 reg = <0xfffff000 0x200>;
59 };
60
61 ramc0: ramc@ffffe800 {
62 compatible = "atmel,at91sam9g45-ddramc";
63 reg = <0xffffe800 0x200>;
64 };
65
66 pmc: pmc@fffffc00 {
67 compatible = "atmel,at91rm9200-pmc";
68 reg = <0xfffffc00 0x100>;
69 };
70
71 rstc@fffffe00 {
72 compatible = "atmel,at91sam9g45-rstc";
73 reg = <0xfffffe00 0x10>;
74 };
75
76 pit: timer@fffffe30 {
77 compatible = "atmel,at91sam9260-pit";
78 reg = <0xfffffe30 0xf>;
79 interrupts = <1 4 7>;
80 };
81
82 shdwc@fffffe10 {
83 compatible = "atmel,at91sam9x5-shdwc";
84 reg = <0xfffffe10 0x10>;
85 };
86
87 mmc0: mmc@f0008000 {
88 compatible = "atmel,hsmci";
89 reg = <0xf0008000 0x600>;
90 interrupts = <12 4 0>;
91 #address-cells = <1>;
92 #size-cells = <0>;
93 status = "disabled";
94 };
95
96 tcb0: timer@f8008000 {
97 compatible = "atmel,at91sam9x5-tcb";
98 reg = <0xf8008000 0x100>;
99 interrupts = <17 4 0>;
100 };
101
102 tcb1: timer@f800c000 {
103 compatible = "atmel,at91sam9x5-tcb";
104 reg = <0xf800c000 0x100>;
105 interrupts = <17 4 0>;
106 };
107
108 dma: dma-controller@ffffec00 {
109 compatible = "atmel,at91sam9g45-dma";
110 reg = <0xffffec00 0x200>;
111 interrupts = <20 4 0>;
112 };
113
114 pinctrl@fffff400 {
115 #address-cells = <1>;
116 #size-cells = <1>;
117 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
118 ranges = <0xfffff400 0xfffff400 0x800>;
119
120 atmel,mux-mask = <
121 /* A B C */
122 0xffffffff 0xffe07983 0x00000000 /* pioA */
123 0x00040000 0x00047e0f 0x00000000 /* pioB */
124 0xfdffffff 0x07c00000 0xb83fffff /* pioC */
125 0x003fffff 0x003f8000 0x00000000 /* pioD */
126 >;
127
128 /* shared pinctrl settings */
129 dbgu {
130 pinctrl_dbgu: dbgu-0 {
131 atmel,pins =
132 <0 9 0x1 0x0 /* PA9 periph A */
133 0 10 0x1 0x1>; /* PA10 periph with pullup */
134 };
135 };
136
137 usart0 {
138 pinctrl_usart0: usart0-0 {
139 atmel,pins =
140 <0 1 0x1 0x1 /* PA1 periph A with pullup */
141 0 0 0x1 0x0>; /* PA0 periph A */
142 };
143
144 pinctrl_usart0_rts: usart0_rts-0 {
145 atmel,pins =
146 <0 2 0x1 0x0>; /* PA2 periph A */
147 };
148
149 pinctrl_usart0_cts: usart0_cts-0 {
150 atmel,pins =
151 <0 3 0x1 0x0>; /* PA3 periph A */
152 };
153 };
154
155 usart1 {
156 pinctrl_usart1: usart1-0 {
157 atmel,pins =
158 <0 6 0x1 0x1 /* PA6 periph A with pullup */
159 0 5 0x1 0x0>; /* PA5 periph A */
160 };
161 };
162
163 usart2 {
164 pinctrl_usart2: usart2-0 {
165 atmel,pins =
166 <0 8 0x1 0x1 /* PA8 periph A with pullup */
167 0 7 0x1 0x0>; /* PA7 periph A */
168 };
169
170 pinctrl_usart2_rts: usart2_rts-0 {
171 atmel,pins =
172 <1 0 0x2 0x0>; /* PB0 periph B */
173 };
174
175 pinctrl_usart2_cts: usart2_cts-0 {
176 atmel,pins =
177 <1 1 0x2 0x0>; /* PB1 periph B */
178 };
179 };
180
181 usart3 {
182 pinctrl_usart3: usart3-0 {
183 atmel,pins =
184 <2 23 0x2 0x1 /* PC23 periph B with pullup */
185 2 22 0x2 0x0>; /* PC22 periph B */
186 };
187
188 pinctrl_usart3_rts: usart3_rts-0 {
189 atmel,pins =
190 <2 24 0x2 0x0>; /* PC24 periph B */
191 };
192
193 pinctrl_usart3_cts: usart3_cts-0 {
194 atmel,pins =
195 <2 25 0x2 0x0>; /* PC25 periph B */
196 };
197 };
198
199 uart0 {
200 pinctrl_uart0: uart0-0 {
201 atmel,pins =
202 <2 9 0x3 0x1 /* PC9 periph C with pullup */
203 2 8 0x3 0x0>; /* PC8 periph C */
204 };
205 };
206
207 uart1 {
208 pinctrl_uart1: uart1-0 {
209 atmel,pins =
210 <2 16 0x3 0x1 /* PC17 periph C with pullup */
211 2 17 0x3 0x0>; /* PC16 periph C */
212 };
213 };
214
215 nand {
216 pinctrl_nand: nand-0 {
217 atmel,pins =
218 <3 5 0x0 0x1 /* PD5 gpio RDY pin pull_up*/
219 3 4 0x0 0x1>; /* PD4 gpio enable pin pull_up */
220 };
221 };
222
223 mmc0 {
224 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
225 atmel,pins =
226 <0 17 0x1 0x0 /* PA17 periph A */
227 0 16 0x1 0x1 /* PA16 periph A with pullup */
228 0 15 0x1 0x1>; /* PA15 periph A with pullup */
229 };
230
231 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
232 atmel,pins =
233 <0 18 0x1 0x1 /* PA18 periph A with pullup */
234 0 19 0x1 0x1 /* PA19 periph A with pullup */
235 0 20 0x1 0x1>; /* PA20 periph A with pullup */
236 };
237
238 pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
239 atmel,pins =
240 <0 11 0x2 0x1 /* PA11 periph B with pullup */
241 0 12 0x2 0x1 /* PA12 periph B with pullup */
242 0 13 0x2 0x1 /* PA13 periph B with pullup */
243 0 14 0x2 0x1>; /* PA14 periph B with pullup */
244 };
245 };
246
247 pioA: gpio@fffff400 {
248 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
249 reg = <0xfffff400 0x200>;
250 interrupts = <2 4 1>;
251 #gpio-cells = <2>;
252 gpio-controller;
253 interrupt-controller;
254 #interrupt-cells = <2>;
255 };
256
257 pioB: gpio@fffff600 {
258 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
259 reg = <0xfffff600 0x200>;
260 interrupts = <2 4 1>;
261 #gpio-cells = <2>;
262 gpio-controller;
263 interrupt-controller;
264 #interrupt-cells = <2>;
265 };
266
267 pioC: gpio@fffff800 {
268 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
269 reg = <0xfffff800 0x200>;
270 interrupts = <3 4 1>;
271 #gpio-cells = <2>;
272 gpio-controller;
273 interrupt-controller;
274 #interrupt-cells = <2>;
275 };
276
277 pioD: gpio@fffffa00 {
278 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
279 reg = <0xfffffa00 0x200>;
280 interrupts = <3 4 1>;
281 #gpio-cells = <2>;
282 gpio-controller;
283 interrupt-controller;
284 #interrupt-cells = <2>;
285 };
286 };
287
288 dbgu: serial@fffff200 {
289 compatible = "atmel,at91sam9260-usart";
290 reg = <0xfffff200 0x200>;
291 interrupts = <1 4 7>;
292 pinctrl-names = "default";
293 pinctrl-0 = <&pinctrl_dbgu>;
294 status = "disabled";
295 };
296
297 usart0: serial@f801c000 {
298 compatible = "atmel,at91sam9260-usart";
299 reg = <0xf801c000 0x4000>;
300 interrupts = <5 4 5>;
301 atmel,use-dma-rx;
302 atmel,use-dma-tx;
303 pinctrl-names = "default";
304 pinctrl-0 = <&pinctrl_usart0>;
305 status = "disabled";
306 };
307
308 usart1: serial@f8020000 {
309 compatible = "atmel,at91sam9260-usart";
310 reg = <0xf8020000 0x4000>;
311 interrupts = <6 4 5>;
312 atmel,use-dma-rx;
313 atmel,use-dma-tx;
314 pinctrl-names = "default";
315 pinctrl-0 = <&pinctrl_usart1>;
316 status = "disabled";
317 };
318
319 usart2: serial@f8024000 {
320 compatible = "atmel,at91sam9260-usart";
321 reg = <0xf8024000 0x4000>;
322 interrupts = <7 4 5>;
323 atmel,use-dma-rx;
324 atmel,use-dma-tx;
325 pinctrl-names = "default";
326 pinctrl-0 = <&pinctrl_usart2>;
327 status = "disabled";
328 };
329
330 usart3: serial@f8028000 {
331 compatible = "atmel,at91sam9260-usart";
332 reg = <0xf8028000 0x4000>;
333 interrupts = <8 4 5>;
334 atmel,use-dma-rx;
335 atmel,use-dma-tx;
336 pinctrl-names = "default";
337 pinctrl-0 = <&pinctrl_usart3>;
338 status = "disabled";
339 };
340
341 i2c0: i2c@f8010000 {
342 compatible = "atmel,at91sam9x5-i2c";
343 reg = <0xf8010000 0x100>;
344 interrupts = <9 4 6>;
345 #address-cells = <1>;
346 #size-cells = <0>;
347 status = "disabled";
348 };
349
350 i2c1: i2c@f8014000 {
351 compatible = "atmel,at91sam9x5-i2c";
352 reg = <0xf8014000 0x100>;
353 interrupts = <10 4 6>;
354 #address-cells = <1>;
355 #size-cells = <0>;
356 status = "disabled";
357 };
358 };
359
360 nand0: nand@40000000 {
361 compatible = "atmel,at91rm9200-nand";
362 #address-cells = <1>;
363 #size-cells = <1>;
364 reg = < 0x40000000 0x10000000
365 0xffffe000 0x00000600
366 0xffffe600 0x00000200
367 0x00100000 0x00100000
368 >;
369 atmel,nand-addr-offset = <21>;
370 atmel,nand-cmd-offset = <22>;
371 pinctrl-names = "default";
372 pinctrl-0 = <&pinctrl_nand>;
373 gpios = <&pioD 5 0
374 &pioD 4 0
375 0
376 >;
377 status = "disabled";
378 };
379
380 usb0: ohci@00500000 {
381 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
382 reg = <0x00500000 0x00100000>;
383 interrupts = <22 4 2>;
384 status = "disabled";
385 };
386 };
387
388 i2c@0 {
389 compatible = "i2c-gpio";
390 gpios = <&pioA 30 0 /* sda */
391 &pioA 31 0 /* scl */
392 >;
393 i2c-gpio,sda-open-drain;
394 i2c-gpio,scl-open-drain;
395 i2c-gpio,delay-us = <2>; /* ~100 kHz */
396 #address-cells = <1>;
397 #size-cells = <0>;
398 status = "disabled";
399 };
400};
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
deleted file mode 100644
index 0376bf4fd66..00000000000
--- a/arch/arm/boot/dts/at91sam9n12ek.dts
+++ /dev/null
@@ -1,114 +0,0 @@
1/*
2 * at91sam9n12ek.dts - Device Tree file for AT91SAM9N12-EK board
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Hong Xu <hong.xu@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/dts-v1/;
10/include/ "at91sam9n12.dtsi"
11
12/ {
13 model = "Atmel AT91SAM9N12-EK";
14 compatible = "atmel,at91sam9n12ek", "atmel,at91sam9n12", "atmel,at91sam9";
15
16 chosen {
17 bootargs = "mem=128M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=jffs2";
18 };
19
20 memory {
21 reg = <0x20000000 0x10000000>;
22 };
23
24 clocks {
25 #address-cells = <1>;
26 #size-cells = <1>;
27 ranges;
28
29 main_clock: clock@0 {
30 compatible = "atmel,osc", "fixed-clock";
31 clock-frequency = <16000000>;
32 };
33 };
34
35 ahb {
36 apb {
37 dbgu: serial@fffff200 {
38 status = "okay";
39 };
40
41 i2c0: i2c@f8010000 {
42 status = "okay";
43 };
44
45 i2c1: i2c@f8014000 {
46 status = "okay";
47 };
48
49 mmc0: mmc@f0008000 {
50 pinctrl-0 = <
51 &pinctrl_board_mmc0
52 &pinctrl_mmc0_slot0_clk_cmd_dat0
53 &pinctrl_mmc0_slot0_dat1_3>;
54 status = "okay";
55 slot@0 {
56 reg = <0>;
57 bus-width = <4>;
58 cd-gpios = <&pioA 7 0>;
59 };
60 };
61
62 pinctrl@fffff400 {
63 mmc0 {
64 pinctrl_board_mmc0: mmc0-board {
65 atmel,pins =
66 <0 7 0x0 0x5>; /* PA7 gpio CD pin pull up and deglitch */
67 };
68 };
69 };
70 };
71
72 nand0: nand@40000000 {
73 nand-bus-width = <8>;
74 nand-ecc-mode = "soft";
75 nand-on-flash-bbt;
76 status = "okay";
77 };
78 };
79
80 leds {
81 compatible = "gpio-leds";
82
83 d8 {
84 label = "d8";
85 gpios = <&pioB 4 1>;
86 linux,default-trigger = "mmc0";
87 };
88
89 d9 {
90 label = "d6";
91 gpios = <&pioB 5 1>;
92 linux,default-trigger = "nand-disk";
93 };
94
95 d10 {
96 label = "d7";
97 gpios = <&pioB 6 0>;
98 linux,default-trigger = "heartbeat";
99 };
100 };
101
102 gpio_keys {
103 compatible = "gpio-keys";
104 #address-cells = <1>;
105 #size-cells = <0>;
106
107 enter {
108 label = "Enter";
109 gpios = <&pioB 4 1>;
110 linux,code = <28>;
111 gpio-key,wakeup;
112 };
113 };
114};
diff --git a/arch/arm/boot/dts/at91sam9x25.dtsi b/arch/arm/boot/dts/at91sam9x25.dtsi
deleted file mode 100644
index 54eb33ba6d2..00000000000
--- a/arch/arm/boot/dts/at91sam9x25.dtsi
+++ /dev/null
@@ -1,49 +0,0 @@
1/*
2 * at91sam9x25.dtsi - Device Tree Include file for AT91SAM9X25 SoC
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8
9/include/ "at91sam9x5.dtsi"
10
11/ {
12 model = "Atmel AT91SAM9X25 SoC";
13 compatible = "atmel, at91sam9x25, atmel,at91sam9x5";
14
15 ahb {
16 apb {
17 pinctrl@fffff400 {
18 atmel,mux-mask = <
19 /* A B C */
20 0xffffffff 0xffe03fff 0xc000001c /* pioA */
21 0x0007ffff 0x00047e3f 0x00000000 /* pioB */
22 0x80000000 0xfffd0000 0xb83fffff /* pioC */
23 0x003fffff 0x003f8000 0x00000000 /* pioD */
24 >;
25
26 macb1 {
27 pinctrl_macb1_rmii: macb1_rmii-0 {
28 atmel,pins =
29 <2 16 0x2 0x0 /* PC16 periph B */
30 2 18 0x2 0x0 /* PC18 periph B */
31 2 19 0x2 0x0 /* PC19 periph B */
32 2 20 0x2 0x0 /* PC20 periph B */
33 2 21 0x2 0x0 /* PC21 periph B */
34 2 27 0x2 0x0 /* PC27 periph B */
35 2 28 0x2 0x0 /* PC28 periph B */
36 2 29 0x2 0x0 /* PC29 periph B */
37 2 30 0x2 0x0 /* PC30 periph B */
38 2 31 0x2 0x0>; /* PC31 periph B */
39 };
40 };
41 };
42
43 macb1: ethernet@f8030000 {
44 pinctrl-names = "default";
45 pinctrl-0 = <&pinctrl_macb1_rmii>;
46 };
47 };
48 };
49};
diff --git a/arch/arm/boot/dts/at91sam9x25ek.dts b/arch/arm/boot/dts/at91sam9x25ek.dts
deleted file mode 100644
index af907eaa1f2..00000000000
--- a/arch/arm/boot/dts/at91sam9x25ek.dts
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * at91sam9x25ek.dts - Device Tree file for AT91SAM9X25-EK board
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/dts-v1/;
10/include/ "at91sam9x25.dtsi"
11/include/ "at91sam9x5ek.dtsi"
12
13/ {
14 model = "Atmel AT91SAM9G25-EK";
15 compatible = "atmel,at91sam9x25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
16};
diff --git a/arch/arm/boot/dts/at91sam9x35.dtsi b/arch/arm/boot/dts/at91sam9x35.dtsi
deleted file mode 100644
index fb102d6126c..00000000000
--- a/arch/arm/boot/dts/at91sam9x35.dtsi
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * at91sam9x35.dtsi - Device Tree Include file for AT91SAM9X35 SoC
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8
9/include/ "at91sam9x5.dtsi"
10
11/ {
12 model = "Atmel AT91SAM9X35 SoC";
13 compatible = "atmel, at91sam9x35, atmel,at91sam9x5";
14
15 ahb {
16 apb {
17 pinctrl@fffff400 {
18 atmel,mux-mask = <
19 /* A B C */
20 0xffffffff 0xffe03fff 0xc000000c /* pioA */
21 0x000406ff 0x00047e3f 0x00000000 /* pioB */
22 0xfdffffff 0x00000000 0xb83fffff /* pioC */
23 0x003fffff 0x003f8000 0x00000000 /* pioD */
24 >;
25 };
26 };
27 };
28};
diff --git a/arch/arm/boot/dts/at91sam9x35ek.dts b/arch/arm/boot/dts/at91sam9x35ek.dts
deleted file mode 100644
index 5ccb607b541..00000000000
--- a/arch/arm/boot/dts/at91sam9x35ek.dts
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * at91sam9x35ek.dts - Device Tree file for AT91SAM9X35-EK board
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/dts-v1/;
10/include/ "at91sam9x35.dtsi"
11/include/ "at91sam9x5ek.dtsi"
12
13/ {
14 model = "Atmel AT91SAM9X35-EK";
15 compatible = "atmel,at91sam9x35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
16};
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
deleted file mode 100644
index 40ac3a4eb1a..00000000000
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ /dev/null
@@ -1,548 +0,0 @@
1/*
2 * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
3 * applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35,
4 * AT91SAM9X25, AT91SAM9X35 SoC
5 *
6 * Copyright (C) 2012 Atmel,
7 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
8 *
9 * Licensed under GPLv2 or later.
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 model = "Atmel AT91SAM9x5 family SoC";
16 compatible = "atmel,at91sam9x5";
17 interrupt-parent = <&aic>;
18
19 aliases {
20 serial0 = &dbgu;
21 serial1 = &usart0;
22 serial2 = &usart1;
23 serial3 = &usart2;
24 gpio0 = &pioA;
25 gpio1 = &pioB;
26 gpio2 = &pioC;
27 gpio3 = &pioD;
28 tcb0 = &tcb0;
29 tcb1 = &tcb1;
30 i2c0 = &i2c0;
31 i2c1 = &i2c1;
32 i2c2 = &i2c2;
33 ssc0 = &ssc0;
34 };
35 cpus {
36 cpu@0 {
37 compatible = "arm,arm926ejs";
38 };
39 };
40
41 memory {
42 reg = <0x20000000 0x10000000>;
43 };
44
45 ahb {
46 compatible = "simple-bus";
47 #address-cells = <1>;
48 #size-cells = <1>;
49 ranges;
50
51 apb {
52 compatible = "simple-bus";
53 #address-cells = <1>;
54 #size-cells = <1>;
55 ranges;
56
57 aic: interrupt-controller@fffff000 {
58 #interrupt-cells = <3>;
59 compatible = "atmel,at91rm9200-aic";
60 interrupt-controller;
61 reg = <0xfffff000 0x200>;
62 atmel,external-irqs = <31>;
63 };
64
65 ramc0: ramc@ffffe800 {
66 compatible = "atmel,at91sam9g45-ddramc";
67 reg = <0xffffe800 0x200>;
68 };
69
70 pmc: pmc@fffffc00 {
71 compatible = "atmel,at91rm9200-pmc";
72 reg = <0xfffffc00 0x100>;
73 };
74
75 rstc@fffffe00 {
76 compatible = "atmel,at91sam9g45-rstc";
77 reg = <0xfffffe00 0x10>;
78 };
79
80 shdwc@fffffe10 {
81 compatible = "atmel,at91sam9x5-shdwc";
82 reg = <0xfffffe10 0x10>;
83 };
84
85 pit: timer@fffffe30 {
86 compatible = "atmel,at91sam9260-pit";
87 reg = <0xfffffe30 0xf>;
88 interrupts = <1 4 7>;
89 };
90
91 ssc0: ssc@f0010000 {
92 compatible = "atmel,at91sam9g45-ssc";
93 reg = <0xf0010000 0x4000>;
94 interrupts = <28 4 5>;
95 status = "disabled";
96 };
97
98 tcb0: timer@f8008000 {
99 compatible = "atmel,at91sam9x5-tcb";
100 reg = <0xf8008000 0x100>;
101 interrupts = <17 4 0>;
102 };
103
104 tcb1: timer@f800c000 {
105 compatible = "atmel,at91sam9x5-tcb";
106 reg = <0xf800c000 0x100>;
107 interrupts = <17 4 0>;
108 };
109
110 dma0: dma-controller@ffffec00 {
111 compatible = "atmel,at91sam9g45-dma";
112 reg = <0xffffec00 0x200>;
113 interrupts = <20 4 0>;
114 };
115
116 dma1: dma-controller@ffffee00 {
117 compatible = "atmel,at91sam9g45-dma";
118 reg = <0xffffee00 0x200>;
119 interrupts = <21 4 0>;
120 };
121
122 pinctrl@fffff400 {
123 #address-cells = <1>;
124 #size-cells = <1>;
125 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
126 ranges = <0xfffff400 0xfffff400 0x800>;
127
128 /* shared pinctrl settings */
129 dbgu {
130 pinctrl_dbgu: dbgu-0 {
131 atmel,pins =
132 <0 9 0x1 0x0 /* PA9 periph A */
133 0 10 0x1 0x1>; /* PA10 periph A with pullup */
134 };
135 };
136
137 usart0 {
138 pinctrl_usart0: usart0-0 {
139 atmel,pins =
140 <0 0 0x1 0x1 /* PA0 periph A with pullup */
141 0 1 0x1 0x0>; /* PA1 periph A */
142 };
143
144 pinctrl_usart0_rts: usart0_rts-0 {
145 atmel,pins =
146 <0 2 0x1 0x0>; /* PA2 periph A */
147 };
148
149 pinctrl_usart0_cts: usart0_cts-0 {
150 atmel,pins =
151 <0 3 0x1 0x0>; /* PA3 periph A */
152 };
153 };
154
155 usart1 {
156 pinctrl_usart1: usart1-0 {
157 atmel,pins =
158 <0 5 0x1 0x1 /* PA5 periph A with pullup */
159 0 6 0x1 0x0>; /* PA6 periph A */
160 };
161
162 pinctrl_usart1_rts: usart1_rts-0 {
163 atmel,pins =
164 <3 27 0x3 0x0>; /* PC27 periph C */
165 };
166
167 pinctrl_usart1_cts: usart1_cts-0 {
168 atmel,pins =
169 <3 28 0x3 0x0>; /* PC28 periph C */
170 };
171 };
172
173 usart2 {
174 pinctrl_usart2: usart2-0 {
175 atmel,pins =
176 <0 7 0x1 0x1 /* PA7 periph A with pullup */
177 0 8 0x1 0x0>; /* PA8 periph A */
178 };
179
180 pinctrl_uart2_rts: uart2_rts-0 {
181 atmel,pins =
182 <0 0 0x2 0x0>; /* PB0 periph B */
183 };
184
185 pinctrl_uart2_cts: uart2_cts-0 {
186 atmel,pins =
187 <0 1 0x2 0x0>; /* PB1 periph B */
188 };
189 };
190
191 usart3 {
192 pinctrl_uart3: usart3-0 {
193 atmel,pins =
194 <3 23 0x2 0x1 /* PC22 periph B with pullup */
195 3 23 0x2 0x0>; /* PC23 periph B */
196 };
197
198 pinctrl_usart3_rts: usart3_rts-0 {
199 atmel,pins =
200 <3 24 0x2 0x0>; /* PC24 periph B */
201 };
202
203 pinctrl_usart3_cts: usart3_cts-0 {
204 atmel,pins =
205 <3 25 0x2 0x0>; /* PC25 periph B */
206 };
207 };
208
209 uart0 {
210 pinctrl_uart0: uart0-0 {
211 atmel,pins =
212 <3 8 0x3 0x0 /* PC8 periph C */
213 3 9 0x3 0x1>; /* PC9 periph C with pullup */
214 };
215 };
216
217 uart1 {
218 pinctrl_uart1: uart1-0 {
219 atmel,pins =
220 <3 16 0x3 0x0 /* PC16 periph C */
221 3 17 0x3 0x1>; /* PC17 periph C with pullup */
222 };
223 };
224
225 nand {
226 pinctrl_nand: nand-0 {
227 atmel,pins =
228 <3 4 0x0 0x1 /* PD5 gpio RDY pin pull_up */
229 3 5 0x0 0x1>; /* PD4 gpio enable pin pull_up */
230 };
231 };
232
233 macb0 {
234 pinctrl_macb0_rmii: macb0_rmii-0 {
235 atmel,pins =
236 <1 0 0x1 0x0 /* PB0 periph A */
237 1 1 0x1 0x0 /* PB1 periph A */
238 1 2 0x1 0x0 /* PB2 periph A */
239 1 3 0x1 0x0 /* PB3 periph A */
240 1 4 0x1 0x0 /* PB4 periph A */
241 1 5 0x1 0x0 /* PB5 periph A */
242 1 6 0x1 0x0 /* PB6 periph A */
243 1 7 0x1 0x0 /* PB7 periph A */
244 1 9 0x1 0x0 /* PB9 periph A */
245 1 10 0x1 0x0>; /* PB10 periph A */
246 };
247
248 pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
249 atmel,pins =
250 <1 8 0x1 0x0 /* PA8 periph A */
251 1 11 0x1 0x0 /* PA11 periph A */
252 1 12 0x1 0x0 /* PA12 periph A */
253 1 13 0x1 0x0 /* PA13 periph A */
254 1 14 0x1 0x0 /* PA14 periph A */
255 1 15 0x1 0x0 /* PA15 periph A */
256 1 16 0x1 0x0 /* PA16 periph A */
257 1 17 0x1 0x0>; /* PA17 periph A */
258 };
259 };
260
261 mmc0 {
262 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
263 atmel,pins =
264 <0 17 0x1 0x0 /* PA17 periph A */
265 0 16 0x1 0x1 /* PA16 periph A with pullup */
266 0 15 0x1 0x1>; /* PA15 periph A with pullup */
267 };
268
269 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
270 atmel,pins =
271 <0 18 0x1 0x1 /* PA18 periph A with pullup */
272 0 19 0x1 0x1 /* PA19 periph A with pullup */
273 0 20 0x1 0x1>; /* PA20 periph A with pullup */
274 };
275 };
276
277 mmc1 {
278 pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
279 atmel,pins =
280 <0 13 0x2 0x0 /* PA13 periph B */
281 0 12 0x2 0x1 /* PA12 periph B with pullup */
282 0 11 0x2 0x1>; /* PA11 periph B with pullup */
283 };
284
285 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
286 atmel,pins =
287 <0 2 0x2 0x1 /* PA2 periph B with pullup */
288 0 3 0x2 0x1 /* PA3 periph B with pullup */
289 0 4 0x2 0x1>; /* PA4 periph B with pullup */
290 };
291 };
292
293 pioA: gpio@fffff400 {
294 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
295 reg = <0xfffff400 0x200>;
296 interrupts = <2 4 1>;
297 #gpio-cells = <2>;
298 gpio-controller;
299 interrupt-controller;
300 #interrupt-cells = <2>;
301 };
302
303 pioB: gpio@fffff600 {
304 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
305 reg = <0xfffff600 0x200>;
306 interrupts = <2 4 1>;
307 #gpio-cells = <2>;
308 gpio-controller;
309 #gpio-lines = <19>;
310 interrupt-controller;
311 #interrupt-cells = <2>;
312 };
313
314 pioC: gpio@fffff800 {
315 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
316 reg = <0xfffff800 0x200>;
317 interrupts = <3 4 1>;
318 #gpio-cells = <2>;
319 gpio-controller;
320 interrupt-controller;
321 #interrupt-cells = <2>;
322 };
323
324 pioD: gpio@fffffa00 {
325 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
326 reg = <0xfffffa00 0x200>;
327 interrupts = <3 4 1>;
328 #gpio-cells = <2>;
329 gpio-controller;
330 #gpio-lines = <22>;
331 interrupt-controller;
332 #interrupt-cells = <2>;
333 };
334 };
335
336 mmc0: mmc@f0008000 {
337 compatible = "atmel,hsmci";
338 reg = <0xf0008000 0x600>;
339 interrupts = <12 4 0>;
340 #address-cells = <1>;
341 #size-cells = <0>;
342 status = "disabled";
343 };
344
345 mmc1: mmc@f000c000 {
346 compatible = "atmel,hsmci";
347 reg = <0xf000c000 0x600>;
348 interrupts = <26 4 0>;
349 #address-cells = <1>;
350 #size-cells = <0>;
351 status = "disabled";
352 };
353
354 dbgu: serial@fffff200 {
355 compatible = "atmel,at91sam9260-usart";
356 reg = <0xfffff200 0x200>;
357 interrupts = <1 4 7>;
358 pinctrl-names = "default";
359 pinctrl-0 = <&pinctrl_dbgu>;
360 status = "disabled";
361 };
362
363 usart0: serial@f801c000 {
364 compatible = "atmel,at91sam9260-usart";
365 reg = <0xf801c000 0x200>;
366 interrupts = <5 4 5>;
367 atmel,use-dma-rx;
368 atmel,use-dma-tx;
369 pinctrl-names = "default";
370 pinctrl-0 = <&pinctrl_usart0>;
371 status = "disabled";
372 };
373
374 usart1: serial@f8020000 {
375 compatible = "atmel,at91sam9260-usart";
376 reg = <0xf8020000 0x200>;
377 interrupts = <6 4 5>;
378 atmel,use-dma-rx;
379 atmel,use-dma-tx;
380 pinctrl-names = "default";
381 pinctrl-0 = <&pinctrl_usart1>;
382 status = "disabled";
383 };
384
385 usart2: serial@f8024000 {
386 compatible = "atmel,at91sam9260-usart";
387 reg = <0xf8024000 0x200>;
388 interrupts = <7 4 5>;
389 atmel,use-dma-rx;
390 atmel,use-dma-tx;
391 pinctrl-names = "default";
392 pinctrl-0 = <&pinctrl_usart2>;
393 status = "disabled";
394 };
395
396 macb0: ethernet@f802c000 {
397 compatible = "cdns,at32ap7000-macb", "cdns,macb";
398 reg = <0xf802c000 0x100>;
399 interrupts = <24 4 3>;
400 pinctrl-names = "default";
401 pinctrl-0 = <&pinctrl_macb0_rmii>;
402 status = "disabled";
403 };
404
405 macb1: ethernet@f8030000 {
406 compatible = "cdns,at32ap7000-macb", "cdns,macb";
407 reg = <0xf8030000 0x100>;
408 interrupts = <27 4 3>;
409 status = "disabled";
410 };
411
412 i2c0: i2c@f8010000 {
413 compatible = "atmel,at91sam9x5-i2c";
414 reg = <0xf8010000 0x100>;
415 interrupts = <9 4 6>;
416 #address-cells = <1>;
417 #size-cells = <0>;
418 status = "disabled";
419 };
420
421 i2c1: i2c@f8014000 {
422 compatible = "atmel,at91sam9x5-i2c";
423 reg = <0xf8014000 0x100>;
424 interrupts = <10 4 6>;
425 #address-cells = <1>;
426 #size-cells = <0>;
427 status = "disabled";
428 };
429
430 i2c2: i2c@f8018000 {
431 compatible = "atmel,at91sam9x5-i2c";
432 reg = <0xf8018000 0x100>;
433 interrupts = <11 4 6>;
434 #address-cells = <1>;
435 #size-cells = <0>;
436 status = "disabled";
437 };
438
439 adc0: adc@f804c000 {
440 compatible = "atmel,at91sam9260-adc";
441 reg = <0xf804c000 0x100>;
442 interrupts = <19 4 0>;
443 atmel,adc-use-external;
444 atmel,adc-channels-used = <0xffff>;
445 atmel,adc-vref = <3300>;
446 atmel,adc-num-channels = <12>;
447 atmel,adc-startup-time = <40>;
448 atmel,adc-channel-base = <0x50>;
449 atmel,adc-drdy-mask = <0x1000000>;
450 atmel,adc-status-register = <0x30>;
451 atmel,adc-trigger-register = <0xc0>;
452
453 trigger@0 {
454 trigger-name = "external-rising";
455 trigger-value = <0x1>;
456 trigger-external;
457 };
458
459 trigger@1 {
460 trigger-name = "external-falling";
461 trigger-value = <0x2>;
462 trigger-external;
463 };
464
465 trigger@2 {
466 trigger-name = "external-any";
467 trigger-value = <0x3>;
468 trigger-external;
469 };
470
471 trigger@3 {
472 trigger-name = "continuous";
473 trigger-value = <0x6>;
474 };
475 };
476 };
477
478 nand0: nand@40000000 {
479 compatible = "atmel,at91rm9200-nand";
480 #address-cells = <1>;
481 #size-cells = <1>;
482 reg = <0x40000000 0x10000000
483 >;
484 atmel,nand-addr-offset = <21>;
485 atmel,nand-cmd-offset = <22>;
486 pinctrl-names = "default";
487 pinctrl-0 = <&pinctrl_nand>;
488 gpios = <&pioD 5 0
489 &pioD 4 0
490 0
491 >;
492 status = "disabled";
493 };
494
495 usb0: ohci@00600000 {
496 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
497 reg = <0x00600000 0x100000>;
498 interrupts = <22 4 2>;
499 status = "disabled";
500 };
501
502 usb1: ehci@00700000 {
503 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
504 reg = <0x00700000 0x100000>;
505 interrupts = <22 4 2>;
506 status = "disabled";
507 };
508 };
509
510 i2c@0 {
511 compatible = "i2c-gpio";
512 gpios = <&pioA 30 0 /* sda */
513 &pioA 31 0 /* scl */
514 >;
515 i2c-gpio,sda-open-drain;
516 i2c-gpio,scl-open-drain;
517 i2c-gpio,delay-us = <2>; /* ~100 kHz */
518 #address-cells = <1>;
519 #size-cells = <0>;
520 status = "disabled";
521 };
522
523 i2c@1 {
524 compatible = "i2c-gpio";
525 gpios = <&pioC 0 0 /* sda */
526 &pioC 1 0 /* scl */
527 >;
528 i2c-gpio,sda-open-drain;
529 i2c-gpio,scl-open-drain;
530 i2c-gpio,delay-us = <2>; /* ~100 kHz */
531 #address-cells = <1>;
532 #size-cells = <0>;
533 status = "disabled";
534 };
535
536 i2c@2 {
537 compatible = "i2c-gpio";
538 gpios = <&pioB 4 0 /* sda */
539 &pioB 5 0 /* scl */
540 >;
541 i2c-gpio,sda-open-drain;
542 i2c-gpio,scl-open-drain;
543 i2c-gpio,delay-us = <2>; /* ~100 kHz */
544 #address-cells = <1>;
545 #size-cells = <0>;
546 status = "disabled";
547 };
548};
diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi b/arch/arm/boot/dts/at91sam9x5cm.dtsi
deleted file mode 100644
index 31e7be23703..00000000000
--- a/arch/arm/boot/dts/at91sam9x5cm.dtsi
+++ /dev/null
@@ -1,74 +0,0 @@
1/*
2 * at91sam9x5cm.dtsi - Device Tree Include file for AT91SAM9x5 CPU Module
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9
10/ {
11 memory {
12 reg = <0x20000000 0x8000000>;
13 };
14
15 clocks {
16 #address-cells = <1>;
17 #size-cells = <1>;
18 ranges;
19
20 main_clock: clock@0 {
21 compatible = "atmel,osc", "fixed-clock";
22 clock-frequency = <12000000>;
23 };
24 };
25
26 ahb {
27 nand0: nand@40000000 {
28 nand-bus-width = <8>;
29 nand-ecc-mode = "soft";
30 nand-on-flash-bbt;
31 status = "okay";
32
33 at91bootstrap@0 {
34 label = "at91bootstrap";
35 reg = <0x0 0x40000>;
36 };
37
38 uboot@40000 {
39 label = "u-boot";
40 reg = <0x40000 0x80000>;
41 };
42
43 ubootenv@c0000 {
44 label = "U-Boot Env";
45 reg = <0xc0000 0x140000>;
46 };
47
48 kernel@200000 {
49 label = "kernel";
50 reg = <0x200000 0x600000>;
51 };
52
53 rootfs@800000 {
54 label = "rootfs";
55 reg = <0x800000 0x1f800000>;
56 };
57 };
58 };
59
60 leds {
61 compatible = "gpio-leds";
62
63 pb18 {
64 label = "pb18";
65 gpios = <&pioB 18 1>;
66 linux,default-trigger = "heartbeat";
67 };
68
69 pd21 {
70 label = "pd21";
71 gpios = <&pioD 21 0>;
72 };
73 };
74};
diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi
deleted file mode 100644
index 8a7cf1d9cf5..00000000000
--- a/arch/arm/boot/dts/at91sam9x5ek.dtsi
+++ /dev/null
@@ -1,101 +0,0 @@
1/*
2 * at91sam9x5ek.dtsi - Device Tree file for AT91SAM9x5CM Base board
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/include/ "at91sam9x5cm.dtsi"
10
11/ {
12 model = "Atmel AT91SAM9X5-EK";
13 compatible = "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
14
15 chosen {
16 bootargs = "128M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
17 };
18
19 ahb {
20 apb {
21 mmc0: mmc@f0008000 {
22 pinctrl-0 = <
23 &pinctrl_board_mmc0
24 &pinctrl_mmc0_slot0_clk_cmd_dat0
25 &pinctrl_mmc0_slot0_dat1_3>;
26 status = "okay";
27 slot@0 {
28 reg = <0>;
29 bus-width = <4>;
30 cd-gpios = <&pioD 15 0>;
31 };
32 };
33
34 mmc1: mmc@f000c000 {
35 pinctrl-0 = <
36 &pinctrl_board_mmc1
37 &pinctrl_mmc1_slot0_clk_cmd_dat0
38 &pinctrl_mmc1_slot0_dat1_3>;
39 status = "okay";
40 slot@0 {
41 reg = <0>;
42 bus-width = <4>;
43 cd-gpios = <&pioD 14 0>;
44 };
45 };
46
47 dbgu: serial@fffff200 {
48 status = "okay";
49 };
50
51 usart0: serial@f801c000 {
52 status = "okay";
53 };
54
55 macb0: ethernet@f802c000 {
56 phy-mode = "rmii";
57 status = "okay";
58 };
59
60 i2c0: i2c@f8010000 {
61 status = "okay";
62 };
63
64 i2c1: i2c@f8014000 {
65 status = "okay";
66 };
67
68 i2c2: i2c@f8018000 {
69 status = "okay";
70 };
71
72 pinctrl@fffff400 {
73 mmc0 {
74 pinctrl_board_mmc0: mmc0-board {
75 atmel,pins =
76 <3 15 0x0 0x5>; /* PD15 gpio CD pin pull up and deglitch */
77 };
78 };
79
80 mmc1 {
81 pinctrl_board_mmc1: mmc1-board {
82 atmel,pins =
83 <3 14 0x0 0x5>; /* PD14 gpio CD pin pull up and deglitch */
84 };
85 };
86 };
87 };
88
89 usb0: ohci@00600000 {
90 status = "okay";
91 num-ports = <2>;
92 atmel,vbus-gpio = <&pioD 19 1
93 &pioD 20 1
94 >;
95 };
96
97 usb1: ehci@00700000 {
98 status = "okay";
99 };
100 };
101};
diff --git a/arch/arm/boot/dts/bcm11351-brt.dts b/arch/arm/boot/dts/bcm11351-brt.dts
deleted file mode 100644
index 248067cf706..00000000000
--- a/arch/arm/boot/dts/bcm11351-brt.dts
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * Copyright (C) 2012 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14/dts-v1/;
15
16/include/ "bcm11351.dtsi"
17
18/ {
19 model = "BCM11351 BRT board";
20 compatible = "bcm,bcm11351-brt", "bcm,bcm11351";
21
22 memory {
23 reg = <0x80000000 0x40000000>; /* 1 GB */
24 };
25
26 uart@3e000000 {
27 status = "okay";
28 };
29
30};
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi
deleted file mode 100644
index ad135885bd2..00000000000
--- a/arch/arm/boot/dts/bcm11351.dtsi
+++ /dev/null
@@ -1,50 +0,0 @@
1/*
2 * Copyright (C) 2012 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14/include/ "skeleton.dtsi"
15
16/ {
17 model = "BCM11351 SoC";
18 compatible = "bcm,bcm11351";
19 interrupt-parent = <&gic>;
20
21 chosen {
22 bootargs = "console=ttyS0,115200n8";
23 };
24
25 gic: interrupt-controller@3ff00100 {
26 compatible = "arm,cortex-a9-gic";
27 #interrupt-cells = <3>;
28 #address-cells = <0>;
29 interrupt-controller;
30 reg = <0x3ff01000 0x1000>,
31 <0x3ff00100 0x100>;
32 };
33
34 uart@3e000000 {
35 compatible = "bcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
36 status = "disabled";
37 reg = <0x3e000000 0x1000>;
38 clock-frequency = <13000000>;
39 interrupts = <0x0 67 0x4>;
40 reg-shift = <2>;
41 reg-io-width = <4>;
42 };
43
44 L2: l2-cache {
45 compatible = "arm,pl310-cache";
46 reg = <0x3ff20000 0x1000>;
47 cache-unified;
48 cache-level = <2>;
49 };
50};
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts
deleted file mode 100644
index 9b72054a0bc..00000000000
--- a/arch/arm/boot/dts/bcm2835-rpi-b.dts
+++ /dev/null
@@ -1,27 +0,0 @@
1/dts-v1/;
2/memreserve/ 0x0c000000 0x04000000;
3/include/ "bcm2835.dtsi"
4
5/ {
6 compatible = "raspberrypi,model-b", "brcm,bcm2835";
7 model = "Raspberry Pi Model B";
8
9 memory {
10 reg = <0 0x10000000>;
11 };
12};
13
14&gpio {
15 pinctrl-names = "default";
16 pinctrl-0 = <&alt0 &alt3>;
17
18 alt0: alt0 {
19 brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11 14 15 40 45>;
20 brcm,function = <4>; /* alt0 */
21 };
22
23 alt3: alt3 {
24 brcm,pins = <48 49 50 51 52 53>;
25 brcm,function = <7>; /* alt3 */
26 };
27};
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
deleted file mode 100644
index 8917550fd1b..00000000000
--- a/arch/arm/boot/dts/bcm2835.dtsi
+++ /dev/null
@@ -1,67 +0,0 @@
1/include/ "skeleton.dtsi"
2
3/ {
4 compatible = "brcm,bcm2835";
5 model = "BCM2835";
6 interrupt-parent = <&intc>;
7
8 chosen {
9 bootargs = "earlyprintk console=ttyAMA0";
10 };
11
12 soc {
13 compatible = "simple-bus";
14 #address-cells = <1>;
15 #size-cells = <1>;
16 ranges = <0x7e000000 0x20000000 0x02000000>;
17
18 timer {
19 compatible = "brcm,bcm2835-system-timer";
20 reg = <0x7e003000 0x1000>;
21 interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
22 clock-frequency = <1000000>;
23 };
24
25 intc: interrupt-controller {
26 compatible = "brcm,bcm2835-armctrl-ic";
27 reg = <0x7e00b200 0x200>;
28 interrupt-controller;
29 #interrupt-cells = <2>;
30 };
31
32 watchdog {
33 compatible = "brcm,bcm2835-pm-wdt";
34 reg = <0x7e100000 0x28>;
35 };
36
37 uart@20201000 {
38 compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
39 reg = <0x7e201000 0x1000>;
40 interrupts = <2 25>;
41 clock-frequency = <3000000>;
42 };
43
44 gpio: gpio {
45 compatible = "brcm,bcm2835-gpio";
46 reg = <0x7e200000 0xb4>;
47 /*
48 * The GPIO IP block is designed for 3 banks of GPIOs.
49 * Each bank has a GPIO interrupt for itself.
50 * There is an overall "any bank" interrupt.
51 * In order, these are GIC interrupts 17, 18, 19, 20.
52 * Since the BCM2835 only has 2 banks, the 2nd bank
53 * interrupt output appears to be mirrored onto the
54 * 3rd bank's interrupt signal.
55 * So, a bank0 interrupt shows up on 17, 20, and
56 * a bank1 interrupt shows up on 18, 19, 20!
57 */
58 interrupts = <2 17>, <2 18>, <2 19>, <2 20>;
59
60 gpio-controller;
61 #gpio-cells = <2>;
62
63 interrupt-controller;
64 #interrupt-cells = <2>;
65 };
66 };
67};
diff --git a/arch/arm/boot/dts/ccu9540.dts b/arch/arm/boot/dts/ccu9540.dts
deleted file mode 100644
index 04305463f00..00000000000
--- a/arch/arm/boot/dts/ccu9540.dts
+++ /dev/null
@@ -1,72 +0,0 @@
1/*
2 * Copyright 2012 ST-Ericsson AB
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "dbx5x0.dtsi"
14
15/ {
16 model = "ST-Ericsson CCU9540 platform with Device Tree";
17 compatible = "st-ericsson,ccu9540", "st-ericsson,u9540";
18
19 memory {
20 reg = <0x00000000 0x20000000>;
21 };
22
23 soc-u9500 {
24 uart@80120000 {
25 status = "okay";
26 };
27
28 uart@80121000 {
29 status = "okay";
30 };
31
32 uart@80007000 {
33 status = "okay";
34 };
35
36 // External Micro SD slot
37 sdi0_per1@80126000 {
38 arm,primecell-periphid = <0x10480180>;
39 max-frequency = <100000000>;
40 bus-width = <4>;
41 mmc-cap-sd-highspeed;
42 mmc-cap-mmc-highspeed;
43 vmmc-supply = <&ab8500_ldo_aux3_reg>;
44
45 cd-gpios = <&gpio7 6 0x4>; // 230
46 cd-inverted;
47
48 status = "okay";
49 };
50
51
52 // WLAN SDIO channel
53 sdi1_per2@80118000 {
54 arm,primecell-periphid = <0x10480180>;
55 max-frequency = <50000000>;
56 bus-width = <4>;
57
58 status = "okay";
59 };
60
61 // On-board eMMC
62 sdi4_per2@80114000 {
63 arm,primecell-periphid = <0x10480180>;
64 max-frequency = <100000000>;
65 bus-width = <8>;
66 mmc-cap-mmc-highspeed;
67 vmmc-supply = <&ab8500_ldo_aux2_reg>;
68
69 status = "okay";
70 };
71 };
72};
diff --git a/arch/arm/boot/dts/cros5250-common.dtsi b/arch/arm/boot/dts/cros5250-common.dtsi
deleted file mode 100644
index fddd1741743..00000000000
--- a/arch/arm/boot/dts/cros5250-common.dtsi
+++ /dev/null
@@ -1,184 +0,0 @@
1/*
2 * Common device tree include for all Exynos 5250 boards based off of Daisy.
3 *
4 * Copyright (c) 2012 Google, Inc
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11/ {
12 aliases {
13 };
14
15 memory {
16 reg = <0x40000000 0x80000000>;
17 };
18
19 chosen {
20 };
21
22 i2c@12C60000 {
23 samsung,i2c-sda-delay = <100>;
24 samsung,i2c-max-bus-freq = <378000>;
25 gpios = <&gpb3 0 2 3 0>,
26 <&gpb3 1 2 3 0>;
27 };
28
29 i2c@12C70000 {
30 samsung,i2c-sda-delay = <100>;
31 samsung,i2c-max-bus-freq = <378000>;
32 gpios = <&gpb3 2 2 3 0>,
33 <&gpb3 3 2 3 0>;
34 };
35
36 i2c@12C80000 {
37 samsung,i2c-sda-delay = <100>;
38 samsung,i2c-max-bus-freq = <66000>;
39
40 /*
41 * Disabled pullups since external part has its own pullups and
42 * double-pulling gets us out of spec in some cases.
43 */
44 gpios = <&gpa0 6 3 0 0>,
45 <&gpa0 7 3 0 0>;
46
47 hdmiddc@50 {
48 compatible = "samsung,exynos5-hdmiddc";
49 reg = <0x50>;
50 };
51 };
52
53 i2c@12C90000 {
54 samsung,i2c-sda-delay = <100>;
55 samsung,i2c-max-bus-freq = <66000>;
56 gpios = <&gpa1 2 3 3 0>,
57 <&gpa1 3 3 3 0>;
58 };
59
60 i2c@12CA0000 {
61 status = "disabled";
62 };
63
64 i2c@12CB0000 {
65 samsung,i2c-sda-delay = <100>;
66 samsung,i2c-max-bus-freq = <66000>;
67 gpios = <&gpa2 2 3 3 0>,
68 <&gpa2 3 3 3 0>;
69 };
70
71 i2c@12CC0000 {
72 status = "disabled";
73 };
74
75 i2c@12CD0000 {
76 samsung,i2c-sda-delay = <100>;
77 samsung,i2c-max-bus-freq = <66000>;
78 gpios = <&gpb2 2 3 3 0>,
79 <&gpb2 3 3 3 0>;
80 };
81
82 i2c@12CE0000 {
83 samsung,i2c-sda-delay = <100>;
84 samsung,i2c-max-bus-freq = <378000>;
85
86 hdmiphy@38 {
87 compatible = "samsung,exynos5-hdmiphy";
88 reg = <0x38>;
89 };
90 };
91
92 dwmmc0@12200000 {
93 num-slots = <1>;
94 supports-highspeed;
95 broken-cd;
96 fifo-depth = <0x80>;
97 card-detect-delay = <200>;
98 samsung,dw-mshc-ciu-div = <3>;
99 samsung,dw-mshc-sdr-timing = <2 3 3>;
100 samsung,dw-mshc-ddr-timing = <1 2 3>;
101
102 slot@0 {
103 reg = <0>;
104 bus-width = <8>;
105 gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>,
106 <&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>,
107 <&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>,
108 <&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>,
109 <&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>;
110 };
111 };
112
113 dwmmc1@12210000 {
114 status = "disabled";
115 };
116
117 dwmmc2@12220000 {
118 num-slots = <1>;
119 supports-highspeed;
120 fifo-depth = <0x80>;
121 card-detect-delay = <200>;
122 samsung,dw-mshc-ciu-div = <3>;
123 samsung,dw-mshc-sdr-timing = <2 3 3>;
124 samsung,dw-mshc-ddr-timing = <1 2 3>;
125
126 slot@0 {
127 reg = <0>;
128 bus-width = <4>;
129 samsung,cd-pinmux-gpio = <&gpc3 2 2 3 3>;
130 wp-gpios = <&gpc2 1 0 0 3>;
131 gpios = <&gpc3 0 2 0 3>, <&gpc3 1 2 0 3>,
132 <&gpc3 3 2 3 3>, <&gpc3 4 2 3 3>,
133 <&gpc3 5 2 3 3>, <&gpc3 6 2 3 3>;
134 };
135 };
136
137 dwmmc3@12230000 {
138 num-slots = <1>;
139 supports-highspeed;
140 broken-cd;
141 fifo-depth = <0x80>;
142 card-detect-delay = <200>;
143 samsung,dw-mshc-ciu-div = <3>;
144 samsung,dw-mshc-sdr-timing = <2 3 3>;
145 samsung,dw-mshc-ddr-timing = <1 2 3>;
146
147 slot@0 {
148 reg = <0>;
149 bus-width = <4>;
150 /* See board-specific dts files for GPIOs */
151 };
152 };
153
154 spi_0: spi@12d20000 {
155 status = "disabled";
156 };
157
158 spi_1: spi@12d30000 {
159 gpios = <&gpa2 4 2 3 0>,
160 <&gpa2 6 2 3 0>,
161 <&gpa2 7 2 3 0>;
162 samsung,spi-src-clk = <0>;
163 num-cs = <1>;
164 };
165
166 spi_2: spi@12d40000 {
167 status = "disabled";
168 };
169
170 hdmi {
171 hpd-gpio = <&gpx3 7 0xf 1 3>;
172 };
173
174 gpio-keys {
175 compatible = "gpio-keys";
176
177 power {
178 label = "Power";
179 gpios = <&gpx1 3 0 0x10000 0>;
180 linux,code = <116>; /* KEY_POWER */
181 gpio-key,wakeup;
182 };
183 };
184};
diff --git a/arch/arm/boot/dts/da850-enbw-cmc.dts b/arch/arm/boot/dts/da850-enbw-cmc.dts
deleted file mode 100644
index 422fdb3fcfc..00000000000
--- a/arch/arm/boot/dts/da850-enbw-cmc.dts
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * Device Tree for AM1808 EnBW CMC board
3 *
4 * Copyright 2012 DENX Software Engineering GmbH
5 * Heiko Schocher <hs@denx.de>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12/dts-v1/;
13/include/ "da850.dtsi"
14
15/ {
16 compatible = "enbw,cmc", "ti,da850";
17 model = "EnBW CMC";
18
19 soc {
20 serial0: serial@1c42000 {
21 status = "okay";
22 };
23 serial1: serial@1d0c000 {
24 status = "okay";
25 };
26 serial2: serial@1d0d000 {
27 status = "okay";
28 };
29 };
30};
diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
deleted file mode 100644
index 37dc5a3243b..00000000000
--- a/arch/arm/boot/dts/da850-evm.dts
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * Device Tree for DA850 EVM board
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation, version 2.
9 */
10/dts-v1/;
11/include/ "da850.dtsi"
12
13/ {
14 compatible = "ti,da850-evm", "ti,da850";
15 model = "DA850/AM1808/OMAP-L138 EVM";
16
17 soc {
18 serial0: serial@1c42000 {
19 status = "okay";
20 };
21 serial1: serial@1d0c000 {
22 status = "okay";
23 };
24 serial2: serial@1d0d000 {
25 status = "okay";
26 };
27 };
28};
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
deleted file mode 100644
index 640ab75c20d..00000000000
--- a/arch/arm/boot/dts/da850.dtsi
+++ /dev/null
@@ -1,60 +0,0 @@
1/*
2 * Copyright 2012 DENX Software Engineering GmbH
3 * Heiko Schocher <hs@denx.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10/include/ "skeleton.dtsi"
11
12/ {
13 arm {
14 #address-cells = <1>;
15 #size-cells = <1>;
16 ranges;
17 intc: interrupt-controller {
18 compatible = "ti,cp-intc";
19 interrupt-controller;
20 #interrupt-cells = <1>;
21 ti,intc-size = <100>;
22 reg = <0xfffee000 0x2000>;
23 };
24 };
25 soc {
26 compatible = "simple-bus";
27 model = "da850";
28 #address-cells = <1>;
29 #size-cells = <1>;
30 ranges = <0x0 0x01c00000 0x400000>;
31
32 serial0: serial@1c42000 {
33 compatible = "ns16550a";
34 reg = <0x42000 0x100>;
35 clock-frequency = <150000000>;
36 reg-shift = <2>;
37 interrupts = <25>;
38 interrupt-parent = <&intc>;
39 status = "disabled";
40 };
41 serial1: serial@1d0c000 {
42 compatible = "ns16550a";
43 reg = <0x10c000 0x100>;
44 clock-frequency = <150000000>;
45 reg-shift = <2>;
46 interrupts = <53>;
47 interrupt-parent = <&intc>;
48 status = "disabled";
49 };
50 serial2: serial@1d0d000 {
51 compatible = "ns16550a";
52 reg = <0x10d000 0x100>;
53 clock-frequency = <150000000>;
54 reg-shift = <2>;
55 interrupts = <61>;
56 interrupt-parent = <&intc>;
57 status = "disabled";
58 };
59 };
60};
diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
deleted file mode 100644
index 63f2fbcfe81..00000000000
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ /dev/null
@@ -1,688 +0,0 @@
1/*
2 * Copyright 2012 Linaro Ltd
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 soc-u9500 {
16 #address-cells = <1>;
17 #size-cells = <1>;
18 compatible = "stericsson,db8500";
19 interrupt-parent = <&intc>;
20 ranges;
21
22 intc: interrupt-controller@a0411000 {
23 compatible = "arm,cortex-a9-gic";
24 #interrupt-cells = <3>;
25 #address-cells = <1>;
26 interrupt-controller;
27 reg = <0xa0411000 0x1000>,
28 <0xa0410100 0x100>;
29 };
30
31 L2: l2-cache {
32 compatible = "arm,pl310-cache";
33 reg = <0xa0412000 0x1000>;
34 interrupts = <0 13 4>;
35 cache-unified;
36 cache-level = <2>;
37 };
38
39 pmu {
40 compatible = "arm,cortex-a9-pmu";
41 interrupts = <0 7 0x4>;
42 };
43
44 timer@a0410600 {
45 compatible = "arm,cortex-a9-twd-timer";
46 reg = <0xa0410600 0x20>;
47 interrupts = <1 13 0x304>;
48 };
49
50 rtc@80154000 {
51 compatible = "arm,rtc-pl031", "arm,primecell";
52 reg = <0x80154000 0x1000>;
53 interrupts = <0 18 0x4>;
54 };
55
56 gpio0: gpio@8012e000 {
57 compatible = "stericsson,db8500-gpio",
58 "st,nomadik-gpio";
59 reg = <0x8012e000 0x80>;
60 interrupts = <0 119 0x4>;
61 interrupt-controller;
62 #interrupt-cells = <2>;
63 st,supports-sleepmode;
64 gpio-controller;
65 #gpio-cells = <2>;
66 gpio-bank = <0>;
67 };
68
69 gpio1: gpio@8012e080 {
70 compatible = "stericsson,db8500-gpio",
71 "st,nomadik-gpio";
72 reg = <0x8012e080 0x80>;
73 interrupts = <0 120 0x4>;
74 interrupt-controller;
75 #interrupt-cells = <2>;
76 st,supports-sleepmode;
77 gpio-controller;
78 #gpio-cells = <2>;
79 gpio-bank = <1>;
80 };
81
82 gpio2: gpio@8000e000 {
83 compatible = "stericsson,db8500-gpio",
84 "st,nomadik-gpio";
85 reg = <0x8000e000 0x80>;
86 interrupts = <0 121 0x4>;
87 interrupt-controller;
88 #interrupt-cells = <2>;
89 st,supports-sleepmode;
90 gpio-controller;
91 #gpio-cells = <2>;
92 gpio-bank = <2>;
93 };
94
95 gpio3: gpio@8000e080 {
96 compatible = "stericsson,db8500-gpio",
97 "st,nomadik-gpio";
98 reg = <0x8000e080 0x80>;
99 interrupts = <0 122 0x4>;
100 interrupt-controller;
101 #interrupt-cells = <2>;
102 st,supports-sleepmode;
103 gpio-controller;
104 #gpio-cells = <2>;
105 gpio-bank = <3>;
106 };
107
108 gpio4: gpio@8000e100 {
109 compatible = "stericsson,db8500-gpio",
110 "st,nomadik-gpio";
111 reg = <0x8000e100 0x80>;
112 interrupts = <0 123 0x4>;
113 interrupt-controller;
114 #interrupt-cells = <2>;
115 st,supports-sleepmode;
116 gpio-controller;
117 #gpio-cells = <2>;
118 gpio-bank = <4>;
119 };
120
121 gpio5: gpio@8000e180 {
122 compatible = "stericsson,db8500-gpio",
123 "st,nomadik-gpio";
124 reg = <0x8000e180 0x80>;
125 interrupts = <0 124 0x4>;
126 interrupt-controller;
127 #interrupt-cells = <2>;
128 st,supports-sleepmode;
129 gpio-controller;
130 #gpio-cells = <2>;
131 gpio-bank = <5>;
132 };
133
134 gpio6: gpio@8011e000 {
135 compatible = "stericsson,db8500-gpio",
136 "st,nomadik-gpio";
137 reg = <0x8011e000 0x80>;
138 interrupts = <0 125 0x4>;
139 interrupt-controller;
140 #interrupt-cells = <2>;
141 st,supports-sleepmode;
142 gpio-controller;
143 #gpio-cells = <2>;
144 gpio-bank = <6>;
145 };
146
147 gpio7: gpio@8011e080 {
148 compatible = "stericsson,db8500-gpio",
149 "st,nomadik-gpio";
150 reg = <0x8011e080 0x80>;
151 interrupts = <0 126 0x4>;
152 interrupt-controller;
153 #interrupt-cells = <2>;
154 st,supports-sleepmode;
155 gpio-controller;
156 #gpio-cells = <2>;
157 gpio-bank = <7>;
158 };
159
160 gpio8: gpio@a03fe000 {
161 compatible = "stericsson,db8500-gpio",
162 "st,nomadik-gpio";
163 reg = <0xa03fe000 0x80>;
164 interrupts = <0 127 0x4>;
165 interrupt-controller;
166 #interrupt-cells = <2>;
167 st,supports-sleepmode;
168 gpio-controller;
169 #gpio-cells = <2>;
170 gpio-bank = <8>;
171 };
172
173 pinctrl@80157000 {
174 // This is actually the PRCMU base address
175 reg = <0x80157000 0x2000>;
176 compatible = "stericsson,nmk_pinctrl";
177 };
178
179 usb@a03e0000 {
180 compatible = "stericsson,db8500-musb",
181 "mentor,musb";
182 reg = <0xa03e0000 0x10000>;
183 interrupts = <0 23 0x4>;
184 };
185
186 dma-controller@801C0000 {
187 compatible = "stericsson,db8500-dma40",
188 "stericsson,dma40";
189 reg = <0x801C0000 0x1000 0x40010000 0x800>;
190 interrupts = <0 25 0x4>;
191 };
192
193 prcmu@80157000 {
194 compatible = "stericsson,db8500-prcmu";
195 reg = <0x80157000 0x1000>;
196 interrupts = <0 47 0x4>;
197 #address-cells = <1>;
198 #size-cells = <1>;
199 interrupt-controller;
200 #interrupt-cells = <2>;
201 ranges;
202
203 prcmu-timer-4@80157450 {
204 compatible = "stericsson,db8500-prcmu-timer-4";
205 reg = <0x80157450 0xC>;
206 };
207
208 thermal@801573c0 {
209 compatible = "stericsson,db8500-thermal";
210 reg = <0x801573c0 0x40>;
211 interrupts = <21 0x4>, <22 0x4>;
212 interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH";
213 status = "disabled";
214 };
215
216 db8500-prcmu-regulators {
217 compatible = "stericsson,db8500-prcmu-regulator";
218
219 // DB8500_REGULATOR_VAPE
220 db8500_vape_reg: db8500_vape {
221 regulator-compatible = "db8500_vape";
222 regulator-always-on;
223 };
224
225 // DB8500_REGULATOR_VARM
226 db8500_varm_reg: db8500_varm {
227 regulator-compatible = "db8500_varm";
228 };
229
230 // DB8500_REGULATOR_VMODEM
231 db8500_vmodem_reg: db8500_vmodem {
232 regulator-compatible = "db8500_vmodem";
233 };
234
235 // DB8500_REGULATOR_VPLL
236 db8500_vpll_reg: db8500_vpll {
237 regulator-compatible = "db8500_vpll";
238 };
239
240 // DB8500_REGULATOR_VSMPS1
241 db8500_vsmps1_reg: db8500_vsmps1 {
242 regulator-compatible = "db8500_vsmps1";
243 };
244
245 // DB8500_REGULATOR_VSMPS2
246 db8500_vsmps2_reg: db8500_vsmps2 {
247 regulator-compatible = "db8500_vsmps2";
248 };
249
250 // DB8500_REGULATOR_VSMPS3
251 db8500_vsmps3_reg: db8500_vsmps3 {
252 regulator-compatible = "db8500_vsmps3";
253 };
254
255 // DB8500_REGULATOR_VRF1
256 db8500_vrf1_reg: db8500_vrf1 {
257 regulator-compatible = "db8500_vrf1";
258 };
259
260 // DB8500_REGULATOR_SWITCH_SVAMMDSP
261 db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
262 regulator-compatible = "db8500_sva_mmdsp";
263 };
264
265 // DB8500_REGULATOR_SWITCH_SVAMMDSPRET
266 db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
267 regulator-compatible = "db8500_sva_mmdsp_ret";
268 };
269
270 // DB8500_REGULATOR_SWITCH_SVAPIPE
271 db8500_sva_pipe_reg: db8500_sva_pipe {
272 regulator-compatible = "db8500_sva_pipe";
273 };
274
275 // DB8500_REGULATOR_SWITCH_SIAMMDSP
276 db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
277 regulator-compatible = "db8500_sia_mmdsp";
278 };
279
280 // DB8500_REGULATOR_SWITCH_SIAMMDSPRET
281 db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
282 };
283
284 // DB8500_REGULATOR_SWITCH_SIAPIPE
285 db8500_sia_pipe_reg: db8500_sia_pipe {
286 regulator-compatible = "db8500_sia_pipe";
287 };
288
289 // DB8500_REGULATOR_SWITCH_SGA
290 db8500_sga_reg: db8500_sga {
291 regulator-compatible = "db8500_sga";
292 vin-supply = <&db8500_vape_reg>;
293 };
294
295 // DB8500_REGULATOR_SWITCH_B2R2_MCDE
296 db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
297 regulator-compatible = "db8500_b2r2_mcde";
298 vin-supply = <&db8500_vape_reg>;
299 };
300
301 // DB8500_REGULATOR_SWITCH_ESRAM12
302 db8500_esram12_reg: db8500_esram12 {
303 regulator-compatible = "db8500_esram12";
304 };
305
306 // DB8500_REGULATOR_SWITCH_ESRAM12RET
307 db8500_esram12_ret_reg: db8500_esram12_ret {
308 regulator-compatible = "db8500_esram12_ret";
309 };
310
311 // DB8500_REGULATOR_SWITCH_ESRAM34
312 db8500_esram34_reg: db8500_esram34 {
313 regulator-compatible = "db8500_esram34";
314 };
315
316 // DB8500_REGULATOR_SWITCH_ESRAM34RET
317 db8500_esram34_ret_reg: db8500_esram34_ret {
318 regulator-compatible = "db8500_esram34_ret";
319 };
320 };
321
322 ab8500@5 {
323 compatible = "stericsson,ab8500";
324 reg = <5>; /* mailbox 5 is i2c */
325 interrupt-parent = <&intc>;
326 interrupts = <0 40 0x4>;
327 interrupt-controller;
328 #interrupt-cells = <2>;
329
330 ab8500-rtc {
331 compatible = "stericsson,ab8500-rtc";
332 interrupts = <17 0x4
333 18 0x4>;
334 interrupt-names = "60S", "ALARM";
335 };
336
337 ab8500-gpadc {
338 compatible = "stericsson,ab8500-gpadc";
339 interrupts = <32 0x4
340 39 0x4>;
341 interrupt-names = "HW_CONV_END", "SW_CONV_END";
342 vddadc-supply = <&ab8500_ldo_tvout_reg>;
343 };
344
345 ab8500_battery: ab8500_battery {
346 stericsson,battery-type = "LIPO";
347 thermistor-on-batctrl;
348 };
349
350 ab8500_fg {
351 compatible = "stericsson,ab8500-fg";
352 battery = <&ab8500_battery>;
353 };
354
355 ab8500_btemp {
356 compatible = "stericsson,ab8500-btemp";
357 battery = <&ab8500_battery>;
358 };
359
360 ab8500_charger {
361 compatible = "stericsson,ab8500-charger";
362 battery = <&ab8500_battery>;
363 vddadc-supply = <&ab8500_ldo_tvout_reg>;
364 };
365
366 ab8500_chargalg {
367 compatible = "stericsson,ab8500-chargalg";
368 battery = <&ab8500_battery>;
369 };
370
371 ab8500_usb {
372 compatible = "stericsson,ab8500-usb";
373 interrupts = < 90 0x4
374 96 0x4
375 14 0x4
376 15 0x4
377 79 0x4
378 74 0x4
379 75 0x4>;
380 interrupt-names = "ID_WAKEUP_R",
381 "ID_WAKEUP_F",
382 "VBUS_DET_F",
383 "VBUS_DET_R",
384 "USB_LINK_STATUS",
385 "USB_ADP_PROBE_PLUG",
386 "USB_ADP_PROBE_UNPLUG";
387 vddulpivio18-supply = <&ab8500_ldo_initcore_reg>;
388 v-ape-supply = <&db8500_vape_reg>;
389 musb_1v8-supply = <&db8500_vsmps2_reg>;
390 };
391
392 ab8500-ponkey {
393 compatible = "stericsson,ab8500-poweron-key";
394 interrupts = <6 0x4
395 7 0x4>;
396 interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
397 };
398
399 ab8500-sysctrl {
400 compatible = "stericsson,ab8500-sysctrl";
401 };
402
403 ab8500-pwm {
404 compatible = "stericsson,ab8500-pwm";
405 };
406
407 ab8500-debugfs {
408 compatible = "stericsson,ab8500-debug";
409 };
410
411 codec: ab8500-codec {
412 compatible = "stericsson,ab8500-codec";
413
414 stericsson,earpeice-cmv = <950>; /* Units in mV. */
415 };
416
417 ab8500-regulators {
418 compatible = "stericsson,ab8500-regulator";
419
420 // supplies to the display/camera
421 ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
422 regulator-compatible = "ab8500_ldo_aux1";
423 regulator-min-microvolt = <2500000>;
424 regulator-max-microvolt = <2900000>;
425 regulator-boot-on;
426 /* BUG: If turned off MMC will be affected. */
427 regulator-always-on;
428 };
429
430 // supplies to the on-board eMMC
431 ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
432 regulator-compatible = "ab8500_ldo_aux2";
433 regulator-min-microvolt = <1100000>;
434 regulator-max-microvolt = <3300000>;
435 };
436
437 // supply for VAUX3; SDcard slots
438 ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
439 regulator-compatible = "ab8500_ldo_aux3";
440 regulator-min-microvolt = <1100000>;
441 regulator-max-microvolt = <3300000>;
442 };
443
444 // supply for v-intcore12; VINTCORE12 LDO
445 ab8500_ldo_initcore_reg: ab8500_ldo_initcore {
446 regulator-compatible = "ab8500_ldo_initcore";
447 };
448
449 // supply for tvout; gpadc; TVOUT LDO
450 ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
451 regulator-compatible = "ab8500_ldo_tvout";
452 };
453
454 // supply for ab8500-usb; USB LDO
455 ab8500_ldo_usb_reg: ab8500_ldo_usb {
456 regulator-compatible = "ab8500_ldo_usb";
457 };
458
459 // supply for ab8500-vaudio; VAUDIO LDO
460 ab8500_ldo_audio_reg: ab8500_ldo_audio {
461 regulator-compatible = "ab8500_ldo_audio";
462 };
463
464 // supply for v-anamic1 VAMic1-LDO
465 ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
466 regulator-compatible = "ab8500_ldo_anamic1";
467 };
468
469 // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1
470 ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
471 regulator-compatible = "ab8500_ldo_amamic2";
472 };
473
474 // supply for v-dmic; VDMIC LDO
475 ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
476 regulator-compatible = "ab8500_ldo_dmic";
477 };
478
479 // supply for U8500 CSI/DSI; VANA LDO
480 ab8500_ldo_ana_reg: ab8500_ldo_ana {
481 regulator-compatible = "ab8500_ldo_ana";
482 };
483 };
484 };
485 };
486
487 i2c@80004000 {
488 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
489 reg = <0x80004000 0x1000>;
490 interrupts = <0 21 0x4>;
491 arm,primecell-periphid = <0x180024>;
492
493 #address-cells = <1>;
494 #size-cells = <0>;
495 v-i2c-supply = <&db8500_vape_reg>;
496
497 clock-frequency = <400000>;
498 };
499
500 i2c@80122000 {
501 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
502 reg = <0x80122000 0x1000>;
503 interrupts = <0 22 0x4>;
504 arm,primecell-periphid = <0x180024>;
505
506 #address-cells = <1>;
507 #size-cells = <0>;
508 v-i2c-supply = <&db8500_vape_reg>;
509
510 clock-frequency = <400000>;
511 };
512
513 i2c@80128000 {
514 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
515 reg = <0x80128000 0x1000>;
516 interrupts = <0 55 0x4>;
517 arm,primecell-periphid = <0x180024>;
518
519 #address-cells = <1>;
520 #size-cells = <0>;
521 v-i2c-supply = <&db8500_vape_reg>;
522
523 clock-frequency = <400000>;
524 };
525
526 i2c@80110000 {
527 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
528 reg = <0x80110000 0x1000>;
529 interrupts = <0 12 0x4>;
530 arm,primecell-periphid = <0x180024>;
531
532 #address-cells = <1>;
533 #size-cells = <0>;
534 v-i2c-supply = <&db8500_vape_reg>;
535
536 clock-frequency = <400000>;
537 };
538
539 i2c@8012a000 {
540 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
541 reg = <0x8012a000 0x1000>;
542 interrupts = <0 51 0x4>;
543 arm,primecell-periphid = <0x180024>;
544
545 #address-cells = <1>;
546 #size-cells = <0>;
547 v-i2c-supply = <&db8500_vape_reg>;
548
549 clock-frequency = <400000>;
550 };
551
552 ssp@80002000 {
553 compatible = "arm,pl022", "arm,primecell";
554 reg = <0x80002000 0x1000>;
555 interrupts = <0 14 0x4>;
556 #address-cells = <1>;
557 #size-cells = <0>;
558 status = "disabled";
559
560 // Add one of these for each child device
561 cs-gpios = <&gpio0 31 0x4 &gpio4 14 0x4 &gpio4 16 0x4
562 &gpio6 22 0x4 &gpio7 0 0x4>;
563
564 };
565
566 uart@80120000 {
567 compatible = "arm,pl011", "arm,primecell";
568 reg = <0x80120000 0x1000>;
569 interrupts = <0 11 0x4>;
570 status = "disabled";
571 };
572 uart@80121000 {
573 compatible = "arm,pl011", "arm,primecell";
574 reg = <0x80121000 0x1000>;
575 interrupts = <0 19 0x4>;
576 status = "disabled";
577 };
578 uart@80007000 {
579 compatible = "arm,pl011", "arm,primecell";
580 reg = <0x80007000 0x1000>;
581 interrupts = <0 26 0x4>;
582 status = "disabled";
583 };
584
585 sdi0_per1@80126000 {
586 compatible = "arm,pl18x", "arm,primecell";
587 reg = <0x80126000 0x1000>;
588 interrupts = <0 60 0x4>;
589 status = "disabled";
590 };
591
592 sdi1_per2@80118000 {
593 compatible = "arm,pl18x", "arm,primecell";
594 reg = <0x80118000 0x1000>;
595 interrupts = <0 50 0x4>;
596 status = "disabled";
597 };
598
599 sdi2_per3@80005000 {
600 compatible = "arm,pl18x", "arm,primecell";
601 reg = <0x80005000 0x1000>;
602 interrupts = <0 41 0x4>;
603 status = "disabled";
604 };
605
606 sdi3_per2@80119000 {
607 compatible = "arm,pl18x", "arm,primecell";
608 reg = <0x80119000 0x1000>;
609 interrupts = <0 59 0x4>;
610 status = "disabled";
611 };
612
613 sdi4_per2@80114000 {
614 compatible = "arm,pl18x", "arm,primecell";
615 reg = <0x80114000 0x1000>;
616 interrupts = <0 99 0x4>;
617 status = "disabled";
618 };
619
620 sdi5_per3@80008000 {
621 compatible = "arm,pl18x", "arm,primecell";
622 reg = <0x80008000 0x1000>;
623 interrupts = <0 100 0x4>;
624 status = "disabled";
625 };
626
627 msp0: msp@80123000 {
628 compatible = "stericsson,ux500-msp-i2s";
629 reg = <0x80123000 0x1000>;
630 interrupts = <0 31 0x4>;
631 v-ape-supply = <&db8500_vape_reg>;
632 status = "disabled";
633 };
634
635 msp1: msp@80124000 {
636 compatible = "stericsson,ux500-msp-i2s";
637 reg = <0x80124000 0x1000>;
638 interrupts = <0 62 0x4>;
639 v-ape-supply = <&db8500_vape_reg>;
640 status = "disabled";
641 };
642
643 // HDMI sound
644 msp2: msp@80117000 {
645 compatible = "stericsson,ux500-msp-i2s";
646 reg = <0x80117000 0x1000>;
647 interrupts = <0 98 0x4>;
648 v-ape-supply = <&db8500_vape_reg>;
649 status = "disabled";
650 };
651
652 msp3: msp@80125000 {
653 compatible = "stericsson,ux500-msp-i2s";
654 reg = <0x80125000 0x1000>;
655 interrupts = <0 62 0x4>;
656 v-ape-supply = <&db8500_vape_reg>;
657 status = "disabled";
658 };
659
660 external-bus@50000000 {
661 compatible = "simple-bus";
662 reg = <0x50000000 0x4000000>;
663 #address-cells = <1>;
664 #size-cells = <1>;
665 ranges = <0 0x50000000 0x4000000>;
666 status = "disabled";
667 };
668
669 cpufreq-cooling {
670 compatible = "stericsson,db8500-cpufreq-cooling";
671 status = "disabled";
672 };
673
674 vmmci: regulator-gpio {
675 compatible = "regulator-gpio";
676
677 regulator-min-microvolt = <1800000>;
678 regulator-max-microvolt = <2600000>;
679 regulator-name = "mmci-reg";
680 regulator-type = "voltage";
681
682 states = <1800000 0x1
683 2900000 0x0>;
684
685 status = "disabled";
686 };
687 };
688};
diff --git a/arch/arm/boot/dts/dove-cm-a510.dts b/arch/arm/boot/dts/dove-cm-a510.dts
deleted file mode 100644
index 61a8062e56d..00000000000
--- a/arch/arm/boot/dts/dove-cm-a510.dts
+++ /dev/null
@@ -1,38 +0,0 @@
1/dts-v1/;
2
3/include/ "dove.dtsi"
4
5/ {
6 model = "Compulab CM-A510";
7 compatible = "compulab,cm-a510", "marvell,dove";
8
9 memory {
10 device_type = "memory";
11 reg = <0x00000000 0x40000000>;
12 };
13
14 chosen {
15 bootargs = "console=ttyS0,115200n8 earlyprintk";
16 };
17};
18
19&uart0 { status = "okay"; };
20&uart1 { status = "okay"; };
21&sdio0 { status = "okay"; };
22&sdio1 { status = "okay"; };
23&sata0 { status = "okay"; };
24
25&spi0 {
26 status = "okay";
27
28 /* spi0.0: 4M Flash Winbond W25Q32BV */
29 spi-flash@0 {
30 compatible = "st,w25q32";
31 spi-max-frequency = <20000000>;
32 reg = <0>;
33 };
34};
35
36&i2c0 {
37 status = "okay";
38};
diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts
deleted file mode 100644
index fed7d3f9f43..00000000000
--- a/arch/arm/boot/dts/dove-cubox.dts
+++ /dev/null
@@ -1,52 +0,0 @@
1/dts-v1/;
2
3/include/ "dove.dtsi"
4
5/ {
6 model = "SolidRun CuBox";
7 compatible = "solidrun,cubox", "marvell,dove";
8
9 memory {
10 device_type = "memory";
11 reg = <0x00000000 0x40000000>;
12 };
13
14 chosen {
15 bootargs = "console=ttyS0,115200n8 earlyprintk";
16 };
17
18 leds {
19 compatible = "gpio-leds";
20 power {
21 label = "Power";
22 gpios = <&gpio0 18 1>;
23 linux,default-trigger = "default-on";
24 };
25 };
26};
27
28&uart0 { status = "okay"; };
29&sdio0 { status = "okay"; };
30&sata0 { status = "okay"; };
31&i2c0 { status = "okay"; };
32
33&spi0 {
34 status = "okay";
35
36 /* spi0.0: 4M Flash Winbond W25Q32BV */
37 spi-flash@0 {
38 compatible = "st,w25q32";
39 spi-max-frequency = <20000000>;
40 reg = <0>;
41 };
42};
43
44&pinctrl {
45 pinctrl-0 = <&pmx_gpio_18>;
46 pinctrl-names = "default";
47
48 pmx_gpio_18: pmx-gpio-18 {
49 marvell,pins = "mpp18";
50 marvell,function = "gpio";
51 };
52};
diff --git a/arch/arm/boot/dts/dove-dove-db.dts b/arch/arm/boot/dts/dove-dove-db.dts
deleted file mode 100644
index e5a920beab4..00000000000
--- a/arch/arm/boot/dts/dove-dove-db.dts
+++ /dev/null
@@ -1,38 +0,0 @@
1/dts-v1/;
2
3/include/ "dove.dtsi"
4
5/ {
6 model = "Marvell DB-MV88AP510-BP Development Board";
7 compatible = "marvell,dove-db", "marvell,dove";
8
9 memory {
10 device_type = "memory";
11 reg = <0x00000000 0x40000000>;
12 };
13
14 chosen {
15 bootargs = "console=ttyS0,115200n8 earlyprintk";
16 };
17};
18
19&uart0 { status = "okay"; };
20&uart1 { status = "okay"; };
21&sdio0 { status = "okay"; };
22&sdio1 { status = "okay"; };
23&sata0 { status = "okay"; };
24
25&spi0 {
26 status = "okay";
27
28 /* spi0.0: 4M Flash ST-M25P32-VMF6P */
29 spi-flash@0 {
30 compatible = "st,m25p32";
31 spi-max-frequency = <20000000>;
32 reg = <0>;
33 };
34};
35
36&i2c0 {
37 status = "okay";
38};
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
deleted file mode 100644
index 42eac1ff3cc..00000000000
--- a/arch/arm/boot/dts/dove.dtsi
+++ /dev/null
@@ -1,234 +0,0 @@
1/include/ "skeleton.dtsi"
2
3/ {
4 compatible = "marvell,dove";
5 model = "Marvell Armada 88AP510 SoC";
6
7 aliases {
8 gpio0 = &gpio0;
9 gpio1 = &gpio1;
10 gpio2 = &gpio2;
11 };
12
13 soc@f1000000 {
14 compatible = "simple-bus";
15 #address-cells = <1>;
16 #size-cells = <1>;
17 interrupt-parent = <&intc>;
18
19 ranges = <0xc8000000 0xc8000000 0x0100000 /* CESA SRAM 1M */
20 0xe0000000 0xe0000000 0x8000000 /* PCIe0 Mem 128M */
21 0xe8000000 0xe8000000 0x8000000 /* PCIe1 Mem 128M */
22 0xf0000000 0xf0000000 0x0100000 /* ScratchPad 1M */
23 0x00000000 0xf1000000 0x1000000 /* SB/NB regs 16M */
24 0xf2000000 0xf2000000 0x0100000 /* PCIe0 I/O 1M */
25 0xf2100000 0xf2100000 0x0100000 /* PCIe0 I/O 1M */
26 0xf8000000 0xf8000000 0x8000000>; /* BootROM 128M */
27
28 l2: l2-cache {
29 compatible = "marvell,tauros2-cache";
30 marvell,tauros2-cache-features = <0>;
31 };
32
33 intc: interrupt-controller {
34 compatible = "marvell,orion-intc";
35 interrupt-controller;
36 #interrupt-cells = <1>;
37 reg = <0x20204 0x04>, <0x20214 0x04>;
38 };
39
40 core_clk: core-clocks@d0214 {
41 compatible = "marvell,dove-core-clock";
42 reg = <0xd0214 0x4>;
43 #clock-cells = <1>;
44 };
45
46 gate_clk: clock-gating-control@d0038 {
47 compatible = "marvell,dove-gating-clock";
48 reg = <0xd0038 0x4>;
49 clocks = <&core_clk 0>;
50 #clock-cells = <1>;
51 };
52
53 uart0: serial@12000 {
54 compatible = "ns16550a";
55 reg = <0x12000 0x100>;
56 reg-shift = <2>;
57 interrupts = <7>;
58 clock-frequency = <166666667>;
59 status = "disabled";
60 };
61
62 uart1: serial@12100 {
63 compatible = "ns16550a";
64 reg = <0x12100 0x100>;
65 reg-shift = <2>;
66 interrupts = <8>;
67 clock-frequency = <166666667>;
68 status = "disabled";
69 };
70
71 uart2: serial@12200 {
72 compatible = "ns16550a";
73 reg = <0x12000 0x100>;
74 reg-shift = <2>;
75 interrupts = <9>;
76 clock-frequency = <166666667>;
77 status = "disabled";
78 };
79
80 uart3: serial@12300 {
81 compatible = "ns16550a";
82 reg = <0x12100 0x100>;
83 reg-shift = <2>;
84 interrupts = <10>;
85 clock-frequency = <166666667>;
86 status = "disabled";
87 };
88
89 gpio0: gpio@d0400 {
90 compatible = "marvell,orion-gpio";
91 #gpio-cells = <2>;
92 gpio-controller;
93 reg = <0xd0400 0x20>;
94 ngpios = <32>;
95 interrupt-controller;
96 interrupts = <12>, <13>, <14>, <60>;
97 };
98
99 gpio1: gpio@d0420 {
100 compatible = "marvell,orion-gpio";
101 #gpio-cells = <2>;
102 gpio-controller;
103 reg = <0xd0420 0x20>;
104 ngpios = <32>;
105 interrupt-controller;
106 interrupts = <61>;
107 };
108
109 gpio2: gpio@e8400 {
110 compatible = "marvell,orion-gpio";
111 #gpio-cells = <2>;
112 gpio-controller;
113 reg = <0xe8400 0x0c>;
114 ngpios = <8>;
115 };
116
117 pinctrl: pinctrl@d0200 {
118 compatible = "marvell,dove-pinctrl";
119 reg = <0xd0200 0x10>;
120 clocks = <&gate_clk 22>;
121 };
122
123 spi0: spi@10600 {
124 compatible = "marvell,orion-spi";
125 #address-cells = <1>;
126 #size-cells = <0>;
127 cell-index = <0>;
128 interrupts = <6>;
129 reg = <0x10600 0x28>;
130 clocks = <&core_clk 0>;
131 status = "disabled";
132 };
133
134 spi1: spi@14600 {
135 compatible = "marvell,orion-spi";
136 #address-cells = <1>;
137 #size-cells = <0>;
138 cell-index = <1>;
139 interrupts = <5>;
140 reg = <0x14600 0x28>;
141 clocks = <&core_clk 0>;
142 status = "disabled";
143 };
144
145 i2c0: i2c@11000 {
146 compatible = "marvell,mv64xxx-i2c";
147 reg = <0x11000 0x20>;
148 #address-cells = <1>;
149 #size-cells = <0>;
150 interrupts = <11>;
151 clock-frequency = <400000>;
152 timeout-ms = <1000>;
153 clocks = <&core_clk 0>;
154 status = "disabled";
155 };
156
157 sdio0: sdio@92000 {
158 compatible = "marvell,dove-sdhci";
159 reg = <0x92000 0x100>;
160 interrupts = <35>, <37>;
161 clocks = <&gate_clk 8>;
162 status = "disabled";
163 };
164
165 sdio1: sdio@90000 {
166 compatible = "marvell,dove-sdhci";
167 reg = <0x90000 0x100>;
168 interrupts = <36>, <38>;
169 clocks = <&gate_clk 9>;
170 status = "disabled";
171 };
172
173 sata0: sata@a0000 {
174 compatible = "marvell,orion-sata";
175 reg = <0xa0000 0x2400>;
176 interrupts = <62>;
177 clocks = <&gate_clk 3>;
178 nr-ports = <1>;
179 status = "disabled";
180 };
181
182 crypto: crypto@30000 {
183 compatible = "marvell,orion-crypto";
184 reg = <0x30000 0x10000>,
185 <0xc8000000 0x800>;
186 reg-names = "regs", "sram";
187 interrupts = <31>;
188 clocks = <&gate_clk 15>;
189 status = "okay";
190 };
191
192 xor0: dma-engine@60800 {
193 compatible = "marvell,orion-xor";
194 reg = <0x60800 0x100
195 0x60a00 0x100>;
196 clocks = <&gate_clk 23>;
197 status = "okay";
198
199 channel0 {
200 interrupts = <39>;
201 dmacap,memcpy;
202 dmacap,xor;
203 };
204
205 channel1 {
206 interrupts = <40>;
207 dmacap,memset;
208 dmacap,memcpy;
209 dmacap,xor;
210 };
211 };
212
213 xor1: dma-engine@60900 {
214 compatible = "marvell,orion-xor";
215 reg = <0x60900 0x100
216 0x60b00 0x100>;
217 clocks = <&gate_clk 24>;
218 status = "okay";
219
220 channel0 {
221 interrupts = <42>;
222 dmacap,memcpy;
223 dmacap,xor;
224 };
225
226 channel1 {
227 interrupts = <43>;
228 dmacap,memset;
229 dmacap,memcpy;
230 dmacap,xor;
231 };
232 };
233 };
234};
diff --git a/arch/arm/boot/dts/ea3250.dts b/arch/arm/boot/dts/ea3250.dts
deleted file mode 100644
index a4ba31b23c8..00000000000
--- a/arch/arm/boot/dts/ea3250.dts
+++ /dev/null
@@ -1,281 +0,0 @@
1/*
2 * Embedded Artists LPC3250 board
3 *
4 * Copyright 2012 Roland Stigge <stigge@antcom.de>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "lpc32xx.dtsi"
16
17/ {
18 model = "Embedded Artists LPC3250 board based on NXP LPC3250";
19 compatible = "ea,ea3250", "nxp,lpc3250";
20 #address-cells = <1>;
21 #size-cells = <1>;
22
23 memory {
24 device_type = "memory";
25 reg = <0 0x4000000>;
26 };
27
28 ahb {
29 mac: ethernet@31060000 {
30 phy-mode = "rmii";
31 use-iram;
32 };
33
34 /* Here, choose exactly one from: ohci, usbd */
35 ohci@31020000 {
36 transceiver = <&isp1301>;
37 status = "okay";
38 };
39
40/*
41 usbd@31020000 {
42 transceiver = <&isp1301>;
43 status = "okay";
44 };
45*/
46
47 /* 128MB Flash via SLC NAND controller */
48 slc: flash@20020000 {
49 status = "okay";
50 #address-cells = <1>;
51 #size-cells = <1>;
52
53 nxp,wdr-clks = <14>;
54 nxp,wwidth = <260000000>;
55 nxp,whold = <104000000>;
56 nxp,wsetup = <200000000>;
57 nxp,rdr-clks = <14>;
58 nxp,rwidth = <34666666>;
59 nxp,rhold = <104000000>;
60 nxp,rsetup = <200000000>;
61 nand-on-flash-bbt;
62 gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
63
64 mtd0@00000000 {
65 label = "ea3250-boot";
66 reg = <0x00000000 0x00080000>;
67 read-only;
68 };
69
70 mtd1@00080000 {
71 label = "ea3250-uboot";
72 reg = <0x00080000 0x000c0000>;
73 read-only;
74 };
75
76 mtd2@00140000 {
77 label = "ea3250-kernel";
78 reg = <0x00140000 0x00400000>;
79 };
80
81 mtd3@00540000 {
82 label = "ea3250-rootfs";
83 reg = <0x00540000 0x07ac0000>;
84 };
85 };
86
87 apb {
88 uart5: serial@40090000 {
89 status = "okay";
90 };
91
92 uart3: serial@40080000 {
93 status = "okay";
94 };
95
96 uart6: serial@40098000 {
97 status = "okay";
98 };
99
100 i2c1: i2c@400A0000 {
101 clock-frequency = <100000>;
102
103 eeprom@50 {
104 compatible = "at,24c256";
105 reg = <0x50>;
106 };
107
108 eeprom@57 {
109 compatible = "at,24c64";
110 reg = <0x57>;
111 };
112
113 uda1380: uda1380@18 {
114 compatible = "nxp,uda1380";
115 reg = <0x18>;
116 power-gpio = <&gpio 0x59 0>;
117 reset-gpio = <&gpio 0x51 0>;
118 dac-clk = "wspll";
119 };
120
121 pca9532: pca9532@60 {
122 compatible = "nxp,pca9532";
123 gpio-controller;
124 #gpio-cells = <2>;
125 reg = <0x60>;
126 };
127 };
128
129 i2c2: i2c@400A8000 {
130 clock-frequency = <100000>;
131 };
132
133 i2cusb: i2c@31020300 {
134 clock-frequency = <100000>;
135
136 isp1301: usb-transceiver@2d {
137 compatible = "nxp,isp1301";
138 reg = <0x2d>;
139 };
140 };
141
142 sd@20098000 {
143 wp-gpios = <&pca9532 5 0>;
144 cd-gpios = <&pca9532 4 0>;
145 cd-inverted;
146 bus-width = <4>;
147 status = "okay";
148 };
149 };
150
151 fab {
152 uart1: serial@40014000 {
153 status = "okay";
154 };
155
156 /* 3-axis accelerometer X,Y,Z (or AD-IN instead of Z) */
157 adc@40048000 {
158 status = "okay";
159 };
160 };
161 };
162
163 gpio_keys {
164 compatible = "gpio-keys";
165 #address-cells = <1>;
166 #size-cells = <0>;
167 autorepeat;
168 button@21 {
169 label = "Interrupt Key";
170 linux,code = <103>;
171 gpios = <&gpio 4 1 0>; /* GPI_P3 1 */
172 };
173 key1 {
174 label = "KEY1";
175 linux,code = <1>;
176 gpios = <&pca9532 0 0>;
177 };
178 key2 {
179 label = "KEY2";
180 linux,code = <2>;
181 gpios = <&pca9532 1 0>;
182 };
183 key3 {
184 label = "KEY3";
185 linux,code = <3>;
186 gpios = <&pca9532 2 0>;
187 };
188 key4 {
189 label = "KEY4";
190 linux,code = <4>;
191 gpios = <&pca9532 3 0>;
192 };
193 joy0 {
194 label = "Joystick Key 0";
195 linux,code = <10>;
196 gpios = <&gpio 2 0 0>; /* P2.0 */
197 };
198 joy1 {
199 label = "Joystick Key 1";
200 linux,code = <11>;
201 gpios = <&gpio 2 1 0>; /* P2.1 */
202 };
203 joy2 {
204 label = "Joystick Key 2";
205 linux,code = <12>;
206 gpios = <&gpio 2 2 0>; /* P2.2 */
207 };
208 joy3 {
209 label = "Joystick Key 3";
210 linux,code = <13>;
211 gpios = <&gpio 2 3 0>; /* P2.3 */
212 };
213 joy4 {
214 label = "Joystick Key 4";
215 linux,code = <14>;
216 gpios = <&gpio 2 4 0>; /* P2.4 */
217 };
218 };
219
220 leds {
221 compatible = "gpio-leds";
222
223 /* LEDs on OEM Board */
224
225 led1 {
226 gpios = <&gpio 5 14 1>; /* GPO_P3 14, GPIO 93, active low */
227 linux,default-trigger = "timer";
228 default-state = "off";
229 };
230
231 led2 {
232 gpios = <&gpio 2 10 1>; /* P2.10, active low */
233 default-state = "off";
234 };
235
236 led3 {
237 gpios = <&gpio 2 11 1>; /* P2.11, active low */
238 default-state = "off";
239 };
240
241 led4 {
242 gpios = <&gpio 2 12 1>; /* P2.12, active low */
243 default-state = "off";
244 };
245
246 /* LEDs on Base Board */
247
248 lede1 {
249 gpios = <&pca9532 8 0>;
250 default-state = "off";
251 };
252 lede2 {
253 gpios = <&pca9532 9 0>;
254 default-state = "off";
255 };
256 lede3 {
257 gpios = <&pca9532 10 0>;
258 default-state = "off";
259 };
260 lede4 {
261 gpios = <&pca9532 11 0>;
262 default-state = "off";
263 };
264 lede5 {
265 gpios = <&pca9532 12 0>;
266 default-state = "off";
267 };
268 lede6 {
269 gpios = <&pca9532 13 0>;
270 default-state = "off";
271 };
272 lede7 {
273 gpios = <&pca9532 14 0>;
274 default-state = "off";
275 };
276 lede8 {
277 gpios = <&pca9532 15 0>;
278 default-state = "off";
279 };
280 };
281};
diff --git a/arch/arm/boot/dts/ecx-2000.dts b/arch/arm/boot/dts/ecx-2000.dts
deleted file mode 100644
index 139b40cc3a2..00000000000
--- a/arch/arm/boot/dts/ecx-2000.dts
+++ /dev/null
@@ -1,108 +0,0 @@
1/*
2 * Copyright 2011-2012 Calxeda, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17/dts-v1/;
18
19/* First 4KB has pen for secondary cores. */
20/memreserve/ 0x00000000 0x0001000;
21
22/ {
23 model = "Calxeda ECX-2000";
24 compatible = "calxeda,ecx-2000";
25 #address-cells = <2>;
26 #size-cells = <2>;
27 clock-ranges;
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 cpu@0 {
34 compatible = "arm,cortex-a15";
35 device_type = "cpu";
36 reg = <0>;
37 clocks = <&a9pll>;
38 clock-names = "cpu";
39 };
40
41 cpu@1 {
42 compatible = "arm,cortex-a15";
43 device_type = "cpu";
44 reg = <1>;
45 clocks = <&a9pll>;
46 clock-names = "cpu";
47 };
48
49 cpu@2 {
50 compatible = "arm,cortex-a15";
51 device_type = "cpu";
52 reg = <2>;
53 clocks = <&a9pll>;
54 clock-names = "cpu";
55 };
56
57 cpu@3 {
58 compatible = "arm,cortex-a15";
59 device_type = "cpu";
60 reg = <3>;
61 clocks = <&a9pll>;
62 clock-names = "cpu";
63 };
64 };
65
66 memory@0 {
67 name = "memory";
68 device_type = "memory";
69 reg = <0x00000000 0x00000000 0x00000000 0xff800000>;
70 };
71
72 memory@200000000 {
73 name = "memory";
74 device_type = "memory";
75 reg = <0x00000002 0x00000000 0x00000003 0x00000000>;
76 };
77
78 soc {
79 ranges = <0x00000000 0x00000000 0x00000000 0xffffffff>;
80
81 timer {
82 compatible = "arm,cortex-a15-timer", "arm,armv7-timer"; interrupts = <1 13 0xf08>,
83 <1 14 0xf08>,
84 <1 11 0xf08>,
85 <1 10 0xf08>;
86 };
87
88 intc: interrupt-controller@fff11000 {
89 compatible = "arm,cortex-a15-gic";
90 #interrupt-cells = <3>;
91 #size-cells = <0>;
92 #address-cells = <1>;
93 interrupt-controller;
94 interrupts = <1 9 0xf04>;
95 reg = <0xfff11000 0x1000>,
96 <0xfff12000 0x1000>,
97 <0xfff14000 0x2000>,
98 <0xfff16000 0x2000>;
99 };
100
101 pmu {
102 compatible = "arm,cortex-a9-pmu";
103 interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>;
104 };
105 };
106};
107
108/include/ "ecx-common.dtsi"
diff --git a/arch/arm/boot/dts/ecx-common.dtsi b/arch/arm/boot/dts/ecx-common.dtsi
deleted file mode 100644
index d61b535f682..00000000000
--- a/arch/arm/boot/dts/ecx-common.dtsi
+++ /dev/null
@@ -1,237 +0,0 @@
1/*
2 * Copyright 2011-2012 Calxeda, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17/ {
18 chosen {
19 bootargs = "console=ttyAMA0";
20 };
21
22 soc {
23 #address-cells = <1>;
24 #size-cells = <1>;
25 compatible = "simple-bus";
26 interrupt-parent = <&intc>;
27
28 sata@ffe08000 {
29 compatible = "calxeda,hb-ahci";
30 reg = <0xffe08000 0x10000>;
31 interrupts = <0 83 4>;
32 dma-coherent;
33 calxeda,port-phys = <&combophy5 0 &combophy0 0
34 &combophy0 1 &combophy0 2
35 &combophy0 3>;
36 };
37
38 sdhci@ffe0e000 {
39 compatible = "calxeda,hb-sdhci";
40 reg = <0xffe0e000 0x1000>;
41 interrupts = <0 90 4>;
42 clocks = <&eclk>;
43 status = "disabled";
44 };
45
46 memory-controller@fff00000 {
47 compatible = "calxeda,hb-ddr-ctrl";
48 reg = <0xfff00000 0x1000>;
49 interrupts = <0 91 4>;
50 };
51
52 ipc@fff20000 {
53 compatible = "arm,pl320", "arm,primecell";
54 reg = <0xfff20000 0x1000>;
55 interrupts = <0 7 4>;
56 clocks = <&pclk>;
57 clock-names = "apb_pclk";
58 };
59
60 gpioe: gpio@fff30000 {
61 #gpio-cells = <2>;
62 compatible = "arm,pl061", "arm,primecell";
63 gpio-controller;
64 reg = <0xfff30000 0x1000>;
65 interrupts = <0 14 4>;
66 clocks = <&pclk>;
67 clock-names = "apb_pclk";
68 status = "disabled";
69 };
70
71 gpiof: gpio@fff31000 {
72 #gpio-cells = <2>;
73 compatible = "arm,pl061", "arm,primecell";
74 gpio-controller;
75 reg = <0xfff31000 0x1000>;
76 interrupts = <0 15 4>;
77 clocks = <&pclk>;
78 clock-names = "apb_pclk";
79 status = "disabled";
80 };
81
82 gpiog: gpio@fff32000 {
83 #gpio-cells = <2>;
84 compatible = "arm,pl061", "arm,primecell";
85 gpio-controller;
86 reg = <0xfff32000 0x1000>;
87 interrupts = <0 16 4>;
88 clocks = <&pclk>;
89 clock-names = "apb_pclk";
90 status = "disabled";
91 };
92
93 gpioh: gpio@fff33000 {
94 #gpio-cells = <2>;
95 compatible = "arm,pl061", "arm,primecell";
96 gpio-controller;
97 reg = <0xfff33000 0x1000>;
98 interrupts = <0 17 4>;
99 clocks = <&pclk>;
100 clock-names = "apb_pclk";
101 status = "disabled";
102 };
103
104 timer@fff34000 {
105 compatible = "arm,sp804", "arm,primecell";
106 reg = <0xfff34000 0x1000>;
107 interrupts = <0 18 4>;
108 clocks = <&pclk>;
109 clock-names = "apb_pclk";
110 };
111
112 rtc@fff35000 {
113 compatible = "arm,pl031", "arm,primecell";
114 reg = <0xfff35000 0x1000>;
115 interrupts = <0 19 4>;
116 clocks = <&pclk>;
117 clock-names = "apb_pclk";
118 };
119
120 serial@fff36000 {
121 compatible = "arm,pl011", "arm,primecell";
122 reg = <0xfff36000 0x1000>;
123 interrupts = <0 20 4>;
124 clocks = <&pclk>;
125 clock-names = "apb_pclk";
126 };
127
128 smic@fff3a000 {
129 compatible = "ipmi-smic";
130 device_type = "ipmi";
131 reg = <0xfff3a000 0x1000>;
132 interrupts = <0 24 4>;
133 reg-size = <4>;
134 reg-spacing = <4>;
135 };
136
137 sregs@fff3c000 {
138 compatible = "calxeda,hb-sregs";
139 reg = <0xfff3c000 0x1000>;
140
141 clocks {
142 #address-cells = <1>;
143 #size-cells = <0>;
144
145 osc: oscillator {
146 #clock-cells = <0>;
147 compatible = "fixed-clock";
148 clock-frequency = <33333000>;
149 };
150
151 ddrpll: ddrpll {
152 #clock-cells = <0>;
153 compatible = "calxeda,hb-pll-clock";
154 clocks = <&osc>;
155 reg = <0x108>;
156 };
157
158 a9pll: a9pll {
159 #clock-cells = <0>;
160 compatible = "calxeda,hb-pll-clock";
161 clocks = <&osc>;
162 reg = <0x100>;
163 };
164
165 a9periphclk: a9periphclk {
166 #clock-cells = <0>;
167 compatible = "calxeda,hb-a9periph-clock";
168 clocks = <&a9pll>;
169 reg = <0x104>;
170 };
171
172 a9bclk: a9bclk {
173 #clock-cells = <0>;
174 compatible = "calxeda,hb-a9bus-clock";
175 clocks = <&a9pll>;
176 reg = <0x104>;
177 };
178
179 emmcpll: emmcpll {
180 #clock-cells = <0>;
181 compatible = "calxeda,hb-pll-clock";
182 clocks = <&osc>;
183 reg = <0x10C>;
184 };
185
186 eclk: eclk {
187 #clock-cells = <0>;
188 compatible = "calxeda,hb-emmc-clock";
189 clocks = <&emmcpll>;
190 reg = <0x114>;
191 };
192
193 pclk: pclk {
194 #clock-cells = <0>;
195 compatible = "fixed-clock";
196 clock-frequency = <150000000>;
197 };
198 };
199 };
200
201 dma@fff3d000 {
202 compatible = "arm,pl330", "arm,primecell";
203 reg = <0xfff3d000 0x1000>;
204 interrupts = <0 92 4>;
205 clocks = <&pclk>;
206 clock-names = "apb_pclk";
207 };
208
209 ethernet@fff50000 {
210 compatible = "calxeda,hb-xgmac";
211 reg = <0xfff50000 0x1000>;
212 interrupts = <0 77 4 0 78 4 0 79 4>;
213 dma-coherent;
214 };
215
216 ethernet@fff51000 {
217 compatible = "calxeda,hb-xgmac";
218 reg = <0xfff51000 0x1000>;
219 interrupts = <0 80 4 0 81 4 0 82 4>;
220 dma-coherent;
221 };
222
223 combophy0: combo-phy@fff58000 {
224 compatible = "calxeda,hb-combophy";
225 #phy-cells = <1>;
226 reg = <0xfff58000 0x1000>;
227 phydev = <5>;
228 };
229
230 combophy5: combo-phy@fff5d000 {
231 compatible = "calxeda,hb-combophy";
232 #phy-cells = <1>;
233 reg = <0xfff5d000 0x1000>;
234 phydev = <31>;
235 };
236 };
237};
diff --git a/arch/arm/boot/dts/elpida_ecb240abacn.dtsi b/arch/arm/boot/dts/elpida_ecb240abacn.dtsi
deleted file mode 100644
index f97f70f8337..00000000000
--- a/arch/arm/boot/dts/elpida_ecb240abacn.dtsi
+++ /dev/null
@@ -1,67 +0,0 @@
1/*
2 * Common devices used in different OMAP boards
3 */
4
5/ {
6 elpida_ECB240ABACN: lpddr2 {
7 compatible = "Elpida,ECB240ABACN","jedec,lpddr2-s4";
8 density = <2048>;
9 io-width = <32>;
10
11 tRPab-min-tck = <3>;
12 tRCD-min-tck = <3>;
13 tWR-min-tck = <3>;
14 tRASmin-min-tck = <3>;
15 tRRD-min-tck = <2>;
16 tWTR-min-tck = <2>;
17 tXP-min-tck = <2>;
18 tRTP-min-tck = <2>;
19 tCKE-min-tck = <3>;
20 tCKESR-min-tck = <3>;
21 tFAW-min-tck = <8>;
22
23 timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
24 compatible = "jedec,lpddr2-timings";
25 min-freq = <10000000>;
26 max-freq = <400000000>;
27 tRPab = <21000>;
28 tRCD = <18000>;
29 tWR = <15000>;
30 tRAS-min = <42000>;
31 tRRD = <10000>;
32 tWTR = <7500>;
33 tXP = <7500>;
34 tRTP = <7500>;
35 tCKESR = <15000>;
36 tDQSCK-max = <5500>;
37 tFAW = <50000>;
38 tZQCS = <90000>;
39 tZQCL = <360000>;
40 tZQinit = <1000000>;
41 tRAS-max-ns = <70000>;
42 tDQSCK-max-derated = <6000>;
43 };
44
45 timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 {
46 compatible = "jedec,lpddr2-timings";
47 min-freq = <10000000>;
48 max-freq = <200000000>;
49 tRPab = <21000>;
50 tRCD = <18000>;
51 tWR = <15000>;
52 tRAS-min = <42000>;
53 tRRD = <10000>;
54 tWTR = <10000>;
55 tXP = <7500>;
56 tRTP = <7500>;
57 tCKESR = <15000>;
58 tDQSCK-max = <5500>;
59 tFAW = <50000>;
60 tZQCS = <90000>;
61 tZQCL = <360000>;
62 tZQinit = <1000000>;
63 tRAS-max-ns = <70000>;
64 tDQSCK-max-derated = <6000>;
65 };
66 };
67};
diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts
deleted file mode 100644
index 297e3baba71..00000000000
--- a/arch/arm/boot/dts/emev2-kzm9d.dts
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * Device Tree Source for the KZM9D board
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10/dts-v1/;
11
12/include/ "emev2.dtsi"
13
14/ {
15 model = "EMEV2 KZM9D Board";
16 compatible = "renesas,kzm9d", "renesas,emev2";
17
18 memory {
19 device_type = "memory";
20 reg = <0x40000000 0x8000000>;
21 };
22
23 chosen {
24 bootargs = "console=ttyS1,115200n81";
25 };
26};
diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi
deleted file mode 100644
index eb504a6c0f4..00000000000
--- a/arch/arm/boot/dts/emev2.dtsi
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * Device Tree Source for the EMEV2 SoC
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "skeleton.dtsi"
12
13/ {
14 compatible = "renesas,emev2";
15 interrupt-parent = <&gic>;
16
17 cpus {
18 cpu@0 {
19 compatible = "arm,cortex-a9";
20 };
21 cpu@1 {
22 compatible = "arm,cortex-a9";
23 };
24 };
25
26 gic: interrupt-controller@e0020000 {
27 compatible = "arm,cortex-a9-gic";
28 interrupt-controller;
29 #interrupt-cells = <3>;
30 reg = <0xe0028000 0x1000>,
31 <0xe0020000 0x0100>;
32 };
33
34 sti@e0180000 {
35 compatible = "renesas,em-sti";
36 reg = <0xe0180000 0x54>;
37 interrupts = <0 125 0>;
38 };
39
40 uart@e1020000 {
41 compatible = "renesas,em-uart";
42 reg = <0xe1020000 0x38>;
43 interrupts = <0 8 0>;
44 };
45
46 uart@e1030000 {
47 compatible = "renesas,em-uart";
48 reg = <0xe1030000 0x38>;
49 interrupts = <0 9 0>;
50 };
51
52 uart@e1040000 {
53 compatible = "renesas,em-uart";
54 reg = <0xe1040000 0x38>;
55 interrupts = <0 10 0>;
56 };
57
58 uart@e1050000 {
59 compatible = "renesas,em-uart";
60 reg = <0xe1050000 0x38>;
61 interrupts = <0 11 0>;
62 };
63};
diff --git a/arch/arm/boot/dts/ethernut5.dts b/arch/arm/boot/dts/ethernut5.dts
deleted file mode 100644
index 1ea9d34460a..00000000000
--- a/arch/arm/boot/dts/ethernut5.dts
+++ /dev/null
@@ -1,84 +0,0 @@
1/*
2 * ethernut5.dts - Device Tree file for Ethernut 5 board
3 *
4 * Copyright (C) 2012 egnite GmbH <info@egnite.de>
5 *
6 * Licensed under GPLv2.
7 */
8/dts-v1/;
9/include/ "at91sam9260.dtsi"
10
11/ {
12 model = "Ethernut 5";
13 compatible = "egnite,ethernut5", "atmel,at91sam9260", "atmel,at91sam9";
14
15 chosen {
16 bootargs = "console=ttyS0,115200 root=/dev/mtdblock0 rw rootfstype=jffs2";
17 };
18
19 memory {
20 reg = <0x20000000 0x08000000>;
21 };
22
23 ahb {
24 apb {
25 dbgu: serial@fffff200 {
26 status = "okay";
27 };
28
29 usart0: serial@fffb0000 {
30 status = "okay";
31 };
32
33 usart1: serial@fffb4000 {
34 status = "okay";
35 };
36
37 macb0: ethernet@fffc4000 {
38 phy-mode = "rmii";
39 status = "okay";
40 };
41
42 usb1: gadget@fffa4000 {
43 atmel,vbus-gpio = <&pioC 5 0>;
44 status = "okay";
45 };
46 };
47
48 nand0: nand@40000000 {
49 nand-bus-width = <8>;
50 nand-ecc-mode = "soft";
51 nand-on-flash-bbt;
52 status = "okay";
53
54 gpios = <0
55 &pioC 14 0
56 0
57 >;
58
59 root@0 {
60 label = "root";
61 reg = <0x0 0x08000000>;
62 };
63
64 data@20000 {
65 label = "data";
66 reg = <0x08000000 0x38000000>;
67 };
68 };
69
70 usb0: ohci@00500000 {
71 num-ports = <2>;
72 status = "okay";
73 };
74 };
75
76 i2c@0 {
77 status = "okay";
78
79 pcf8563@50 {
80 compatible = "nxp,pcf8563";
81 reg = <0x51>;
82 };
83 };
84};
diff --git a/arch/arm/boot/dts/evk-pro3.dts b/arch/arm/boot/dts/evk-pro3.dts
deleted file mode 100644
index 96e50f56943..00000000000
--- a/arch/arm/boot/dts/evk-pro3.dts
+++ /dev/null
@@ -1,53 +0,0 @@
1/*
2 * evk-pro3.dts - Device Tree file for Telit EVK-PRO3 with Telit GE863-PRO3
3 *
4 * Copyright (C) 2012 Telit,
5 * 2012 Fabio Porcedda <fabio.porcedda@gmail.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9
10/dts-v1/;
11
12/include/ "ge863-pro3.dtsi"
13
14/ {
15 model = "Telit EVK-PRO3 for Telit GE863-PRO3";
16 compatible = "telit,evk-pro3", "atmel,at91sam9260", "atmel,at91sam9";
17
18 ahb {
19 apb {
20 macb0: ethernet@fffc4000 {
21 phy-mode = "rmii";
22 status = "okay";
23 };
24
25 usart0: serial@fffb0000 {
26 status = "okay";
27 };
28
29 usart2: serial@fffb8000 {
30 status = "okay";
31 };
32
33 usb1: gadget@fffa4000 {
34 atmel,vbus-gpio = <&pioC 5 0>;
35 status = "okay";
36 };
37
38 watchdog@fffffd40 {
39 status = "okay";
40 };
41 };
42
43 usb0: ohci@00500000 {
44 num-ports = <2>;
45 status = "okay";
46 };
47 };
48
49 i2c@0 {
50 status = "okay";
51 };
52
53}; \ No newline at end of file
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
deleted file mode 100644
index e1347fceb5b..00000000000
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ /dev/null
@@ -1,292 +0,0 @@
1/*
2 * Samsung's Exynos4 SoC series common device tree source
3 *
4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2010-2011 Linaro Ltd.
7 * www.linaro.org
8 *
9 * Samsung's Exynos4 SoC series device nodes are listed in this file. Particular
10 * SoCs from Exynos4 series can include this file and provide values for SoCs
11 * specfic bindings.
12 *
13 * Note: This file does not include device nodes for all the controllers in
14 * Exynos4 SoCs. As device tree coverage for Exynos4 increases, additional
15 * nodes can be added to this file.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 */
21
22/include/ "skeleton.dtsi"
23
24/ {
25 interrupt-parent = <&gic>;
26
27 aliases {
28 spi0 = &spi_0;
29 spi1 = &spi_1;
30 spi2 = &spi_2;
31 i2c0 = &i2c_0;
32 i2c1 = &i2c_1;
33 i2c2 = &i2c_2;
34 i2c3 = &i2c_3;
35 i2c4 = &i2c_4;
36 i2c5 = &i2c_5;
37 i2c6 = &i2c_6;
38 i2c7 = &i2c_7;
39 };
40
41 pd_mfc: mfc-power-domain@10023C40 {
42 compatible = "samsung,exynos4210-pd";
43 reg = <0x10023C40 0x20>;
44 };
45
46 pd_g3d: g3d-power-domain@10023C60 {
47 compatible = "samsung,exynos4210-pd";
48 reg = <0x10023C60 0x20>;
49 };
50
51 pd_lcd0: lcd0-power-domain@10023C80 {
52 compatible = "samsung,exynos4210-pd";
53 reg = <0x10023C80 0x20>;
54 };
55
56 pd_tv: tv-power-domain@10023C20 {
57 compatible = "samsung,exynos4210-pd";
58 reg = <0x10023C20 0x20>;
59 };
60
61 pd_cam: cam-power-domain@10023C00 {
62 compatible = "samsung,exynos4210-pd";
63 reg = <0x10023C00 0x20>;
64 };
65
66 pd_gps: gps-power-domain@10023CE0 {
67 compatible = "samsung,exynos4210-pd";
68 reg = <0x10023CE0 0x20>;
69 };
70
71 gic:interrupt-controller@10490000 {
72 compatible = "arm,cortex-a9-gic";
73 #interrupt-cells = <3>;
74 interrupt-controller;
75 reg = <0x10490000 0x1000>, <0x10480000 0x100>;
76 };
77
78 combiner:interrupt-controller@10440000 {
79 compatible = "samsung,exynos4210-combiner";
80 #interrupt-cells = <2>;
81 interrupt-controller;
82 reg = <0x10440000 0x1000>;
83 };
84
85 watchdog@10060000 {
86 compatible = "samsung,s3c2410-wdt";
87 reg = <0x10060000 0x100>;
88 interrupts = <0 43 0>;
89 status = "disabled";
90 };
91
92 rtc@10070000 {
93 compatible = "samsung,s3c6410-rtc";
94 reg = <0x10070000 0x100>;
95 interrupts = <0 44 0>, <0 45 0>;
96 status = "disabled";
97 };
98
99 keypad@100A0000 {
100 compatible = "samsung,s5pv210-keypad";
101 reg = <0x100A0000 0x100>;
102 interrupts = <0 109 0>;
103 status = "disabled";
104 };
105
106 sdhci@12510000 {
107 compatible = "samsung,exynos4210-sdhci";
108 reg = <0x12510000 0x100>;
109 interrupts = <0 73 0>;
110 status = "disabled";
111 };
112
113 sdhci@12520000 {
114 compatible = "samsung,exynos4210-sdhci";
115 reg = <0x12520000 0x100>;
116 interrupts = <0 74 0>;
117 status = "disabled";
118 };
119
120 sdhci@12530000 {
121 compatible = "samsung,exynos4210-sdhci";
122 reg = <0x12530000 0x100>;
123 interrupts = <0 75 0>;
124 status = "disabled";
125 };
126
127 sdhci@12540000 {
128 compatible = "samsung,exynos4210-sdhci";
129 reg = <0x12540000 0x100>;
130 interrupts = <0 76 0>;
131 status = "disabled";
132 };
133
134 serial@13800000 {
135 compatible = "samsung,exynos4210-uart";
136 reg = <0x13800000 0x100>;
137 interrupts = <0 52 0>;
138 status = "disabled";
139 };
140
141 serial@13810000 {
142 compatible = "samsung,exynos4210-uart";
143 reg = <0x13810000 0x100>;
144 interrupts = <0 53 0>;
145 status = "disabled";
146 };
147
148 serial@13820000 {
149 compatible = "samsung,exynos4210-uart";
150 reg = <0x13820000 0x100>;
151 interrupts = <0 54 0>;
152 status = "disabled";
153 };
154
155 serial@13830000 {
156 compatible = "samsung,exynos4210-uart";
157 reg = <0x13830000 0x100>;
158 interrupts = <0 55 0>;
159 status = "disabled";
160 };
161
162 i2c_0: i2c@13860000 {
163 #address-cells = <1>;
164 #size-cells = <0>;
165 compatible = "samsung,s3c2440-i2c";
166 reg = <0x13860000 0x100>;
167 interrupts = <0 58 0>;
168 status = "disabled";
169 };
170
171 i2c_1: i2c@13870000 {
172 #address-cells = <1>;
173 #size-cells = <0>;
174 compatible = "samsung,s3c2440-i2c";
175 reg = <0x13870000 0x100>;
176 interrupts = <0 59 0>;
177 status = "disabled";
178 };
179
180 i2c_2: i2c@13880000 {
181 #address-cells = <1>;
182 #size-cells = <0>;
183 compatible = "samsung,s3c2440-i2c";
184 reg = <0x13880000 0x100>;
185 interrupts = <0 60 0>;
186 status = "disabled";
187 };
188
189 i2c_3: i2c@13890000 {
190 #address-cells = <1>;
191 #size-cells = <0>;
192 compatible = "samsung,s3c2440-i2c";
193 reg = <0x13890000 0x100>;
194 interrupts = <0 61 0>;
195 status = "disabled";
196 };
197
198 i2c_4: i2c@138A0000 {
199 #address-cells = <1>;
200 #size-cells = <0>;
201 compatible = "samsung,s3c2440-i2c";
202 reg = <0x138A0000 0x100>;
203 interrupts = <0 62 0>;
204 status = "disabled";
205 };
206
207 i2c_5: i2c@138B0000 {
208 #address-cells = <1>;
209 #size-cells = <0>;
210 compatible = "samsung,s3c2440-i2c";
211 reg = <0x138B0000 0x100>;
212 interrupts = <0 63 0>;
213 status = "disabled";
214 };
215
216 i2c_6: i2c@138C0000 {
217 #address-cells = <1>;
218 #size-cells = <0>;
219 compatible = "samsung,s3c2440-i2c";
220 reg = <0x138C0000 0x100>;
221 interrupts = <0 64 0>;
222 status = "disabled";
223 };
224
225 i2c_7: i2c@138D0000 {
226 #address-cells = <1>;
227 #size-cells = <0>;
228 compatible = "samsung,s3c2440-i2c";
229 reg = <0x138D0000 0x100>;
230 interrupts = <0 65 0>;
231 status = "disabled";
232 };
233
234 spi_0: spi@13920000 {
235 compatible = "samsung,exynos4210-spi";
236 reg = <0x13920000 0x100>;
237 interrupts = <0 66 0>;
238 tx-dma-channel = <&pdma0 7>; /* preliminary */
239 rx-dma-channel = <&pdma0 6>; /* preliminary */
240 #address-cells = <1>;
241 #size-cells = <0>;
242 status = "disabled";
243 };
244
245 spi_1: spi@13930000 {
246 compatible = "samsung,exynos4210-spi";
247 reg = <0x13930000 0x100>;
248 interrupts = <0 67 0>;
249 tx-dma-channel = <&pdma1 7>; /* preliminary */
250 rx-dma-channel = <&pdma1 6>; /* preliminary */
251 #address-cells = <1>;
252 #size-cells = <0>;
253 status = "disabled";
254 };
255
256 spi_2: spi@13940000 {
257 compatible = "samsung,exynos4210-spi";
258 reg = <0x13940000 0x100>;
259 interrupts = <0 68 0>;
260 tx-dma-channel = <&pdma0 9>; /* preliminary */
261 rx-dma-channel = <&pdma0 8>; /* preliminary */
262 #address-cells = <1>;
263 #size-cells = <0>;
264 status = "disabled";
265 };
266
267 amba {
268 #address-cells = <1>;
269 #size-cells = <1>;
270 compatible = "arm,amba-bus";
271 interrupt-parent = <&gic>;
272 ranges;
273
274 pdma0: pdma@12680000 {
275 compatible = "arm,pl330", "arm,primecell";
276 reg = <0x12680000 0x1000>;
277 interrupts = <0 35 0>;
278 };
279
280 pdma1: pdma@12690000 {
281 compatible = "arm,pl330", "arm,primecell";
282 reg = <0x12690000 0x1000>;
283 interrupts = <0 36 0>;
284 };
285
286 mdma1: mdma@12850000 {
287 compatible = "arm,pl330", "arm,primecell";
288 reg = <0x12850000 0x1000>;
289 interrupts = <0 34 0>;
290 };
291 };
292};
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
deleted file mode 100644
index f2710018e84..00000000000
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ /dev/null
@@ -1,124 +0,0 @@
1/*
2 * Samsung's Exynos4210 based Origen board device tree source
3 *
4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2010-2011 Linaro Ltd.
7 * www.linaro.org
8 *
9 * Device tree source file for Insignal's Origen board which is based on
10 * Samsung's Exynos4210 SoC.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15*/
16
17/dts-v1/;
18/include/ "exynos4210.dtsi"
19
20/ {
21 model = "Insignal Origen evaluation board based on Exynos4210";
22 compatible = "insignal,origen", "samsung,exynos4210";
23
24 memory {
25 reg = <0x40000000 0x10000000
26 0x50000000 0x10000000
27 0x60000000 0x10000000
28 0x70000000 0x10000000>;
29 };
30
31 chosen {
32 bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
33 };
34
35 mmc_reg: voltage-regulator {
36 compatible = "regulator-fixed";
37 regulator-name = "VMEM_VDD_2.8V";
38 regulator-min-microvolt = <2800000>;
39 regulator-max-microvolt = <2800000>;
40 gpio = <&gpx1 1 0>;
41 enable-active-high;
42 };
43
44 sdhci@12530000 {
45 bus-width = <4>;
46 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
47 pinctrl-names = "default";
48 vmmc-supply = <&mmc_reg>;
49 status = "okay";
50 };
51
52 sdhci@12510000 {
53 bus-width = <4>;
54 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_cd>;
55 pinctrl-names = "default";
56 vmmc-supply = <&mmc_reg>;
57 status = "okay";
58 };
59
60 serial@13800000 {
61 status = "okay";
62 };
63
64 serial@13810000 {
65 status = "okay";
66 };
67
68 serial@13820000 {
69 status = "okay";
70 };
71
72 serial@13830000 {
73 status = "okay";
74 };
75
76 gpio_keys {
77 compatible = "gpio-keys";
78 #address-cells = <1>;
79 #size-cells = <0>;
80
81 up {
82 label = "Up";
83 gpios = <&gpx2 0 1>;
84 linux,code = <103>;
85 gpio-key,wakeup;
86 };
87
88 down {
89 label = "Down";
90 gpios = <&gpx2 1 1>;
91 linux,code = <108>;
92 gpio-key,wakeup;
93 };
94
95 back {
96 label = "Back";
97 gpios = <&gpx1 7 1>;
98 linux,code = <158>;
99 gpio-key,wakeup;
100 };
101
102 home {
103 label = "Home";
104 gpios = <&gpx1 6 1>;
105 linux,code = <102>;
106 gpio-key,wakeup;
107 };
108
109 menu {
110 label = "Menu";
111 gpios = <&gpx1 5 1>;
112 linux,code = <139>;
113 gpio-key,wakeup;
114 };
115 };
116
117 leds {
118 compatible = "gpio-leds";
119 status {
120 gpios = <&gpx1 3 1>;
121 linux,default-trigger = "heartbeat";
122 };
123 };
124};
diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
deleted file mode 100644
index 55a2efb763d..00000000000
--- a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
+++ /dev/null
@@ -1,735 +0,0 @@
1/*
2 * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source
3 *
4 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2011-2012 Linaro Ltd.
7 * www.linaro.org
8 *
9 * Samsung's Exynos4210 SoC pin-mux and pin-config optiosn are listed as device
10 * tree nodes are listed in this file.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15*/
16
17/ {
18 pinctrl@11400000 {
19 gpa0: gpa0 {
20 gpio-controller;
21 #gpio-cells = <2>;
22
23 interrupt-controller;
24 #interrupt-cells = <2>;
25 };
26
27 gpa1: gpa1 {
28 gpio-controller;
29 #gpio-cells = <2>;
30
31 interrupt-controller;
32 #interrupt-cells = <2>;
33 };
34
35 gpb: gpb {
36 gpio-controller;
37 #gpio-cells = <2>;
38
39 interrupt-controller;
40 #interrupt-cells = <2>;
41 };
42
43 gpc0: gpc0 {
44 gpio-controller;
45 #gpio-cells = <2>;
46
47 interrupt-controller;
48 #interrupt-cells = <2>;
49 };
50
51 gpc1: gpc1 {
52 gpio-controller;
53 #gpio-cells = <2>;
54
55 interrupt-controller;
56 #interrupt-cells = <2>;
57 };
58
59 gpd0: gpd0 {
60 gpio-controller;
61 #gpio-cells = <2>;
62
63 interrupt-controller;
64 #interrupt-cells = <2>;
65 };
66
67 gpd1: gpd1 {
68 gpio-controller;
69 #gpio-cells = <2>;
70
71 interrupt-controller;
72 #interrupt-cells = <2>;
73 };
74
75 gpe0: gpe0 {
76 gpio-controller;
77 #gpio-cells = <2>;
78
79 interrupt-controller;
80 #interrupt-cells = <2>;
81 };
82
83 gpe1: gpe1 {
84 gpio-controller;
85 #gpio-cells = <2>;
86
87 interrupt-controller;
88 #interrupt-cells = <2>;
89 };
90
91 gpe2: gpe2 {
92 gpio-controller;
93 #gpio-cells = <2>;
94
95 interrupt-controller;
96 #interrupt-cells = <2>;
97 };
98
99 gpe3: gpe3 {
100 gpio-controller;
101 #gpio-cells = <2>;
102
103 interrupt-controller;
104 #interrupt-cells = <2>;
105 };
106
107 gpe4: gpe4 {
108 gpio-controller;
109 #gpio-cells = <2>;
110
111 interrupt-controller;
112 #interrupt-cells = <2>;
113 };
114
115 gpf0: gpf0 {
116 gpio-controller;
117 #gpio-cells = <2>;
118
119 interrupt-controller;
120 #interrupt-cells = <2>;
121 };
122
123 gpf1: gpf1 {
124 gpio-controller;
125 #gpio-cells = <2>;
126
127 interrupt-controller;
128 #interrupt-cells = <2>;
129 };
130
131 gpf2: gpf2 {
132 gpio-controller;
133 #gpio-cells = <2>;
134
135 interrupt-controller;
136 #interrupt-cells = <2>;
137 };
138
139 gpf3: gpf3 {
140 gpio-controller;
141 #gpio-cells = <2>;
142
143 interrupt-controller;
144 #interrupt-cells = <2>;
145 };
146
147 uart0_data: uart0-data {
148 samsung,pins = "gpa0-0", "gpa0-1";
149 samsung,pin-function = <0x2>;
150 samsung,pin-pud = <0>;
151 samsung,pin-drv = <0>;
152 };
153
154 uart0_fctl: uart0-fctl {
155 samsung,pins = "gpa0-2", "gpa0-3";
156 samsung,pin-function = <2>;
157 samsung,pin-pud = <0>;
158 samsung,pin-drv = <0>;
159 };
160
161 uart1_data: uart1-data {
162 samsung,pins = "gpa0-4", "gpa0-5";
163 samsung,pin-function = <2>;
164 samsung,pin-pud = <0>;
165 samsung,pin-drv = <0>;
166 };
167
168 uart1_fctl: uart1-fctl {
169 samsung,pins = "gpa0-6", "gpa0-7";
170 samsung,pin-function = <2>;
171 samsung,pin-pud = <0>;
172 samsung,pin-drv = <0>;
173 };
174
175 i2c2_bus: i2c2-bus {
176 samsung,pins = "gpa0-6", "gpa0-7";
177 samsung,pin-function = <3>;
178 samsung,pin-pud = <3>;
179 samsung,pin-drv = <0>;
180 };
181
182 uart2_data: uart2-data {
183 samsung,pins = "gpa1-0", "gpa1-1";
184 samsung,pin-function = <2>;
185 samsung,pin-pud = <0>;
186 samsung,pin-drv = <0>;
187 };
188
189 uart2_fctl: uart2-fctl {
190 samsung,pins = "gpa1-2", "gpa1-3";
191 samsung,pin-function = <2>;
192 samsung,pin-pud = <0>;
193 samsung,pin-drv = <0>;
194 };
195
196 uart_audio_a: uart-audio-a {
197 samsung,pins = "gpa1-0", "gpa1-1";
198 samsung,pin-function = <4>;
199 samsung,pin-pud = <0>;
200 samsung,pin-drv = <0>;
201 };
202
203 i2c3_bus: i2c3-bus {
204 samsung,pins = "gpa1-2", "gpa1-3";
205 samsung,pin-function = <3>;
206 samsung,pin-pud = <3>;
207 samsung,pin-drv = <0>;
208 };
209
210 uart3_data: uart3-data {
211 samsung,pins = "gpa1-4", "gpa1-5";
212 samsung,pin-function = <2>;
213 samsung,pin-pud = <0>;
214 samsung,pin-drv = <0>;
215 };
216
217 uart_audio_b: uart-audio-b {
218 samsung,pins = "gpa1-4", "gpa1-5";
219 samsung,pin-function = <4>;
220 samsung,pin-pud = <0>;
221 samsung,pin-drv = <0>;
222 };
223
224 spi0_bus: spi0-bus {
225 samsung,pins = "gpb-0", "gpb-2", "gpb-3";
226 samsung,pin-function = <2>;
227 samsung,pin-pud = <3>;
228 samsung,pin-drv = <0>;
229 };
230
231 i2c4_bus: i2c4-bus {
232 samsung,pins = "gpb-2", "gpb-3";
233 samsung,pin-function = <3>;
234 samsung,pin-pud = <3>;
235 samsung,pin-drv = <0>;
236 };
237
238 spi1_bus: spi1-bus {
239 samsung,pins = "gpb-4", "gpb-6", "gpb-7";
240 samsung,pin-function = <2>;
241 samsung,pin-pud = <3>;
242 samsung,pin-drv = <0>;
243 };
244
245 i2c5_bus: i2c5-bus {
246 samsung,pins = "gpb-6", "gpb-7";
247 samsung,pin-function = <3>;
248 samsung,pin-pud = <3>;
249 samsung,pin-drv = <0>;
250 };
251
252 i2s1_bus: i2s1-bus {
253 samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
254 "gpc0-4";
255 samsung,pin-function = <2>;
256 samsung,pin-pud = <0>;
257 samsung,pin-drv = <0>;
258 };
259
260 pcm1_bus: pcm1-bus {
261 samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
262 "gpc0-4";
263 samsung,pin-function = <3>;
264 samsung,pin-pud = <0>;
265 samsung,pin-drv = <0>;
266 };
267
268 ac97_bus: ac97-bus {
269 samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
270 "gpc0-4";
271 samsung,pin-function = <4>;
272 samsung,pin-pud = <0>;
273 samsung,pin-drv = <0>;
274 };
275
276 i2s2_bus: i2s2-bus {
277 samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
278 "gpc1-4";
279 samsung,pin-function = <2>;
280 samsung,pin-pud = <0>;
281 samsung,pin-drv = <0>;
282 };
283
284 pcm2_bus: pcm2-bus {
285 samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
286 "gpc1-4";
287 samsung,pin-function = <3>;
288 samsung,pin-pud = <0>;
289 samsung,pin-drv = <0>;
290 };
291
292 spdif_bus: spdif-bus {
293 samsung,pins = "gpc1-0", "gpc1-1";
294 samsung,pin-function = <4>;
295 samsung,pin-pud = <0>;
296 samsung,pin-drv = <0>;
297 };
298
299 i2c6_bus: i2c6-bus {
300 samsung,pins = "gpc1-3", "gpc1-4";
301 samsung,pin-function = <4>;
302 samsung,pin-pud = <3>;
303 samsung,pin-drv = <0>;
304 };
305
306 spi2_bus: spi2-bus {
307 samsung,pins = "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4";
308 samsung,pin-function = <5>;
309 samsung,pin-pud = <3>;
310 samsung,pin-drv = <0>;
311 };
312
313 i2c7_bus: i2c7-bus {
314 samsung,pins = "gpd0-2", "gpd0-3";
315 samsung,pin-function = <3>;
316 samsung,pin-pud = <3>;
317 samsung,pin-drv = <0>;
318 };
319
320 i2c0_bus: i2c0-bus {
321 samsung,pins = "gpd1-0", "gpd1-1";
322 samsung,pin-function = <2>;
323 samsung,pin-pud = <3>;
324 samsung,pin-drv = <0>;
325 };
326
327 i2c1_bus: i2c1-bus {
328 samsung,pins = "gpd1-2", "gpd1-3";
329 samsung,pin-function = <2>;
330 samsung,pin-pud = <3>;
331 samsung,pin-drv = <0>;
332 };
333 };
334
335 pinctrl@11000000 {
336 gpj0: gpj0 {
337 gpio-controller;
338 #gpio-cells = <2>;
339
340 interrupt-controller;
341 #interrupt-cells = <2>;
342 };
343
344 gpj1: gpj1 {
345 gpio-controller;
346 #gpio-cells = <2>;
347
348 interrupt-controller;
349 #interrupt-cells = <2>;
350 };
351
352 gpk0: gpk0 {
353 gpio-controller;
354 #gpio-cells = <2>;
355
356 interrupt-controller;
357 #interrupt-cells = <2>;
358 };
359
360 gpk1: gpk1 {
361 gpio-controller;
362 #gpio-cells = <2>;
363
364 interrupt-controller;
365 #interrupt-cells = <2>;
366 };
367
368 gpk2: gpk2 {
369 gpio-controller;
370 #gpio-cells = <2>;
371
372 interrupt-controller;
373 #interrupt-cells = <2>;
374 };
375
376 gpk3: gpk3 {
377 gpio-controller;
378 #gpio-cells = <2>;
379
380 interrupt-controller;
381 #interrupt-cells = <2>;
382 };
383
384 gpl0: gpl0 {
385 gpio-controller;
386 #gpio-cells = <2>;
387
388 interrupt-controller;
389 #interrupt-cells = <2>;
390 };
391
392 gpl1: gpl1 {
393 gpio-controller;
394 #gpio-cells = <2>;
395
396 interrupt-controller;
397 #interrupt-cells = <2>;
398 };
399
400 gpl2: gpl2 {
401 gpio-controller;
402 #gpio-cells = <2>;
403
404 interrupt-controller;
405 #interrupt-cells = <2>;
406 };
407
408 gpy0: gpy0 {
409 gpio-controller;
410 #gpio-cells = <2>;
411 };
412
413 gpy1: gpy1 {
414 gpio-controller;
415 #gpio-cells = <2>;
416 };
417
418 gpy2: gpy2 {
419 gpio-controller;
420 #gpio-cells = <2>;
421 };
422
423 gpy3: gpy3 {
424 gpio-controller;
425 #gpio-cells = <2>;
426 };
427
428 gpy4: gpy4 {
429 gpio-controller;
430 #gpio-cells = <2>;
431 };
432
433 gpy5: gpy5 {
434 gpio-controller;
435 #gpio-cells = <2>;
436 };
437
438 gpy6: gpy6 {
439 gpio-controller;
440 #gpio-cells = <2>;
441 };
442
443 gpx0: gpx0 {
444 gpio-controller;
445 #gpio-cells = <2>;
446
447 interrupt-controller;
448 interrupt-parent = <&gic>;
449 interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
450 <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>;
451 #interrupt-cells = <2>;
452 };
453
454 gpx1: gpx1 {
455 gpio-controller;
456 #gpio-cells = <2>;
457
458 interrupt-controller;
459 interrupt-parent = <&gic>;
460 interrupts = <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
461 <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
462 #interrupt-cells = <2>;
463 };
464
465 gpx2: gpx2 {
466 gpio-controller;
467 #gpio-cells = <2>;
468
469 interrupt-controller;
470 #interrupt-cells = <2>;
471 };
472
473 gpx3: gpx3 {
474 gpio-controller;
475 #gpio-cells = <2>;
476
477 interrupt-controller;
478 #interrupt-cells = <2>;
479 };
480
481 sd0_clk: sd0-clk {
482 samsung,pins = "gpk0-0";
483 samsung,pin-function = <2>;
484 samsung,pin-pud = <0>;
485 samsung,pin-drv = <3>;
486 };
487
488 sd0_cmd: sd0-cmd {
489 samsung,pins = "gpk0-1";
490 samsung,pin-function = <2>;
491 samsung,pin-pud = <0>;
492 samsung,pin-drv = <3>;
493 };
494
495 sd0_cd: sd0-cd {
496 samsung,pins = "gpk0-2";
497 samsung,pin-function = <2>;
498 samsung,pin-pud = <3>;
499 samsung,pin-drv = <3>;
500 };
501
502 sd0_bus1: sd0-bus-width1 {
503 samsung,pins = "gpk0-3";
504 samsung,pin-function = <2>;
505 samsung,pin-pud = <3>;
506 samsung,pin-drv = <3>;
507 };
508
509 sd0_bus4: sd0-bus-width4 {
510 samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
511 samsung,pin-function = <2>;
512 samsung,pin-pud = <3>;
513 samsung,pin-drv = <3>;
514 };
515
516 sd0_bus8: sd0-bus-width8 {
517 samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
518 samsung,pin-function = <3>;
519 samsung,pin-pud = <3>;
520 samsung,pin-drv = <3>;
521 };
522
523 sd4_clk: sd4-clk {
524 samsung,pins = "gpk0-0";
525 samsung,pin-function = <3>;
526 samsung,pin-pud = <0>;
527 samsung,pin-drv = <3>;
528 };
529
530 sd4_cmd: sd4-cmd {
531 samsung,pins = "gpk0-1";
532 samsung,pin-function = <3>;
533 samsung,pin-pud = <0>;
534 samsung,pin-drv = <3>;
535 };
536
537 sd4_cd: sd4-cd {
538 samsung,pins = "gpk0-2";
539 samsung,pin-function = <3>;
540 samsung,pin-pud = <3>;
541 samsung,pin-drv = <3>;
542 };
543
544 sd4_bus1: sd4-bus-width1 {
545 samsung,pins = "gpk0-3";
546 samsung,pin-function = <3>;
547 samsung,pin-pud = <3>;
548 samsung,pin-drv = <3>;
549 };
550
551 sd4_bus4: sd4-bus-width4 {
552 samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
553 samsung,pin-function = <3>;
554 samsung,pin-pud = <3>;
555 samsung,pin-drv = <3>;
556 };
557
558 sd4_bus8: sd4-bus-width8 {
559 samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
560 samsung,pin-function = <3>;
561 samsung,pin-pud = <4>;
562 samsung,pin-drv = <3>;
563 };
564
565 sd1_clk: sd1-clk {
566 samsung,pins = "gpk1-0";
567 samsung,pin-function = <2>;
568 samsung,pin-pud = <0>;
569 samsung,pin-drv = <3>;
570 };
571
572 sd1_cmd: sd1-cmd {
573 samsung,pins = "gpk1-1";
574 samsung,pin-function = <2>;
575 samsung,pin-pud = <0>;
576 samsung,pin-drv = <3>;
577 };
578
579 sd1_cd: sd1-cd {
580 samsung,pins = "gpk1-2";
581 samsung,pin-function = <2>;
582 samsung,pin-pud = <3>;
583 samsung,pin-drv = <3>;
584 };
585
586 sd1_bus1: sd1-bus-width1 {
587 samsung,pins = "gpk1-3";
588 samsung,pin-function = <2>;
589 samsung,pin-pud = <3>;
590 samsung,pin-drv = <3>;
591 };
592
593 sd1_bus4: sd1-bus-width4 {
594 samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
595 samsung,pin-function = <2>;
596 samsung,pin-pud = <3>;
597 samsung,pin-drv = <3>;
598 };
599
600 sd2_clk: sd2-clk {
601 samsung,pins = "gpk2-0";
602 samsung,pin-function = <2>;
603 samsung,pin-pud = <0>;
604 samsung,pin-drv = <3>;
605 };
606
607 sd2_cmd: sd2-cmd {
608 samsung,pins = "gpk2-1";
609 samsung,pin-function = <2>;
610 samsung,pin-pud = <0>;
611 samsung,pin-drv = <3>;
612 };
613
614 sd2_cd: sd2-cd {
615 samsung,pins = "gpk2-2";
616 samsung,pin-function = <2>;
617 samsung,pin-pud = <3>;
618 samsung,pin-drv = <3>;
619 };
620
621 sd2_bus1: sd2-bus-width1 {
622 samsung,pins = "gpk2-3";
623 samsung,pin-function = <2>;
624 samsung,pin-pud = <3>;
625 samsung,pin-drv = <3>;
626 };
627
628 sd2_bus4: sd2-bus-width4 {
629 samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6";
630 samsung,pin-function = <2>;
631 samsung,pin-pud = <3>;
632 samsung,pin-drv = <3>;
633 };
634
635 sd2_bus8: sd2-bus-width8 {
636 samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
637 samsung,pin-function = <3>;
638 samsung,pin-pud = <3>;
639 samsung,pin-drv = <3>;
640 };
641
642 sd3_clk: sd3-clk {
643 samsung,pins = "gpk3-0";
644 samsung,pin-function = <2>;
645 samsung,pin-pud = <0>;
646 samsung,pin-drv = <3>;
647 };
648
649 sd3_cmd: sd3-cmd {
650 samsung,pins = "gpk3-1";
651 samsung,pin-function = <2>;
652 samsung,pin-pud = <0>;
653 samsung,pin-drv = <3>;
654 };
655
656 sd3_cd: sd3-cd {
657 samsung,pins = "gpk3-2";
658 samsung,pin-function = <2>;
659 samsung,pin-pud = <3>;
660 samsung,pin-drv = <3>;
661 };
662
663 sd3_bus1: sd3-bus-width1 {
664 samsung,pins = "gpk3-3";
665 samsung,pin-function = <2>;
666 samsung,pin-pud = <3>;
667 samsung,pin-drv = <3>;
668 };
669
670 sd3_bus4: sd3-bus-width4 {
671 samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
672 samsung,pin-function = <2>;
673 samsung,pin-pud = <3>;
674 samsung,pin-drv = <3>;
675 };
676
677 eint0: ext-int0 {
678 samsung,pins = "gpx0-0";
679 samsung,pin-function = <0xf>;
680 samsung,pin-pud = <0>;
681 samsung,pin-drv = <0>;
682 };
683
684 eint8: ext-int8 {
685 samsung,pins = "gpx1-0";
686 samsung,pin-function = <0xf>;
687 samsung,pin-pud = <0>;
688 samsung,pin-drv = <0>;
689 };
690
691 eint15: ext-int15 {
692 samsung,pins = "gpx1-7";
693 samsung,pin-function = <0xf>;
694 samsung,pin-pud = <0>;
695 samsung,pin-drv = <0>;
696 };
697
698 eint16: ext-int16 {
699 samsung,pins = "gpx2-0";
700 samsung,pin-function = <0xf>;
701 samsung,pin-pud = <0>;
702 samsung,pin-drv = <0>;
703 };
704
705 eint31: ext-int31 {
706 samsung,pins = "gpx3-7";
707 samsung,pin-function = <0xf>;
708 samsung,pin-pud = <0>;
709 samsung,pin-drv = <0>;
710 };
711 };
712
713 pinctrl@03860000 {
714 gpz: gpz {
715 gpio-controller;
716 #gpio-cells = <2>;
717 };
718
719 i2s0_bus: i2s0-bus {
720 samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
721 "gpz-4", "gpz-5", "gpz-6";
722 samsung,pin-function = <0x2>;
723 samsung,pin-pud = <0>;
724 samsung,pin-drv = <0>;
725 };
726
727 pcm0_bus: pcm0-bus {
728 samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
729 "gpz-4";
730 samsung,pin-function = <0x3>;
731 samsung,pin-pud = <0>;
732 samsung,pin-drv = <0>;
733 };
734 };
735};
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts
deleted file mode 100644
index f63490707f3..00000000000
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ /dev/null
@@ -1,192 +0,0 @@
1/*
2 * Samsung's Exynos4210 based SMDKV310 board device tree source
3 *
4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2010-2011 Linaro Ltd.
7 * www.linaro.org
8 *
9 * Device tree source file for Samsung's SMDKV310 board which is based on
10 * Samsung's Exynos4210 SoC.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15*/
16
17/dts-v1/;
18/include/ "exynos4210.dtsi"
19
20/ {
21 model = "Samsung smdkv310 evaluation board based on Exynos4210";
22 compatible = "samsung,smdkv310", "samsung,exynos4210";
23
24 memory {
25 reg = <0x40000000 0x80000000>;
26 };
27
28 chosen {
29 bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc";
30 };
31
32 sdhci@12530000 {
33 samsung,sdhci-bus-width = <4>;
34 linux,mmc_cap_4_bit_data;
35 samsung,sdhci-cd-internal;
36 gpio-cd = <&gpk2 2 2 3 3>;
37 gpios = <&gpk2 0 2 0 3>,
38 <&gpk2 1 2 0 3>,
39 <&gpk2 3 2 3 3>,
40 <&gpk2 4 2 3 3>,
41 <&gpk2 5 2 3 3>,
42 <&gpk2 6 2 3 3>;
43 status = "okay";
44 };
45
46 serial@13800000 {
47 status = "okay";
48 };
49
50 serial@13810000 {
51 status = "okay";
52 };
53
54 serial@13820000 {
55 status = "okay";
56 };
57
58 serial@13830000 {
59 status = "okay";
60 };
61
62 keypad@100A0000 {
63 samsung,keypad-num-rows = <2>;
64 samsung,keypad-num-columns = <8>;
65 linux,keypad-no-autorepeat;
66 linux,keypad-wakeup;
67 status = "okay";
68
69 row-gpios = <&gpx2 0 3 3 0>,
70 <&gpx2 1 3 3 0>;
71
72 col-gpios = <&gpx1 0 3 0 0>,
73 <&gpx1 1 3 0 0>,
74 <&gpx1 2 3 0 0>,
75 <&gpx1 3 3 0 0>,
76 <&gpx1 4 3 0 0>,
77 <&gpx1 5 3 0 0>,
78 <&gpx1 6 3 0 0>,
79 <&gpx1 7 3 0 0>;
80
81 key_1 {
82 keypad,row = <0>;
83 keypad,column = <3>;
84 linux,code = <2>;
85 };
86
87 key_2 {
88 keypad,row = <0>;
89 keypad,column = <4>;
90 linux,code = <3>;
91 };
92
93 key_3 {
94 keypad,row = <0>;
95 keypad,column = <5>;
96 linux,code = <4>;
97 };
98
99 key_4 {
100 keypad,row = <0>;
101 keypad,column = <6>;
102 linux,code = <5>;
103 };
104
105 key_5 {
106 keypad,row = <0>;
107 keypad,column = <7>;
108 linux,code = <6>;
109 };
110
111 key_a {
112 keypad,row = <1>;
113 keypad,column = <3>;
114 linux,code = <30>;
115 };
116
117 key_b {
118 keypad,row = <1>;
119 keypad,column = <4>;
120 linux,code = <48>;
121 };
122
123 key_c {
124 keypad,row = <1>;
125 keypad,column = <5>;
126 linux,code = <46>;
127 };
128
129 key_d {
130 keypad,row = <1>;
131 keypad,column = <6>;
132 linux,code = <32>;
133 };
134
135 key_e {
136 keypad,row = <1>;
137 keypad,column = <7>;
138 linux,code = <18>;
139 };
140 };
141
142 i2c@13860000 {
143 #address-cells = <1>;
144 #size-cells = <0>;
145 samsung,i2c-sda-delay = <100>;
146 samsung,i2c-max-bus-freq = <20000>;
147 gpios = <&gpd1 0 2 3 0>,
148 <&gpd1 1 2 3 0>;
149 status = "okay";
150
151 eeprom@50 {
152 compatible = "samsung,24ad0xd1";
153 reg = <0x50>;
154 };
155
156 eeprom@52 {
157 compatible = "samsung,24ad0xd1";
158 reg = <0x52>;
159 };
160 };
161
162 spi_2: spi@13940000 {
163 gpios = <&gpc1 1 5 3 0>,
164 <&gpc1 3 5 3 0>,
165 <&gpc1 4 5 3 0>;
166 status = "okay";
167
168 w25x80@0 {
169 #address-cells = <1>;
170 #size-cells = <1>;
171 compatible = "w25x80";
172 reg = <0>;
173 spi-max-frequency = <1000000>;
174
175 controller-data {
176 cs-gpio = <&gpc1 2 1 0 3>;
177 samsung,spi-feedback-delay = <0>;
178 };
179
180 partition@0 {
181 label = "U-Boot";
182 reg = <0x0 0x40000>;
183 read-only;
184 };
185
186 partition@40000 {
187 label = "Kernel";
188 reg = <0x40000 0xc0000>;
189 };
190 };
191 };
192};
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
deleted file mode 100644
index c346b64dff5..00000000000
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ /dev/null
@@ -1,292 +0,0 @@
1/*
2 * Samsung's Exynos4210 based Trats board device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Device tree source file for Samsung's Trats board which is based on
8 * Samsung's Exynos4210 SoC.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15/dts-v1/;
16/include/ "exynos4210.dtsi"
17
18/ {
19 model = "Samsung Trats based on Exynos4210";
20 compatible = "samsung,trats", "samsung,exynos4210";
21
22 memory {
23 reg = <0x40000000 0x10000000
24 0x50000000 0x10000000
25 0x60000000 0x10000000
26 0x70000000 0x10000000>;
27 };
28
29 chosen {
30 bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rootwait earlyprintk panic=5";
31 };
32
33 vemmc_reg: voltage-regulator@0 {
34 compatible = "regulator-fixed";
35 regulator-name = "VMEM_VDD_2.8V";
36 regulator-min-microvolt = <2800000>;
37 regulator-max-microvolt = <2800000>;
38 gpio = <&gpk0 2 0>;
39 enable-active-high;
40 };
41
42 sdhci_emmc: sdhci@12510000 {
43 bus-width = <8>;
44 non-removable;
45 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus8>;
46 pinctrl-names = "default";
47 vmmc-supply = <&vemmc_reg>;
48 status = "okay";
49 };
50
51 serial@13800000 {
52 status = "okay";
53 };
54
55 serial@13810000 {
56 status = "okay";
57 };
58
59 serial@13820000 {
60 status = "okay";
61 };
62
63 serial@13830000 {
64 status = "okay";
65 };
66
67 gpio-keys {
68 compatible = "gpio-keys";
69
70 vol-down-key {
71 gpios = <&gpx2 1 1>;
72 linux,code = <114>;
73 label = "volume down";
74 debounce-interval = <10>;
75 };
76
77 vol-up-key {
78 gpios = <&gpx2 0 1>;
79 linux,code = <115>;
80 label = "volume up";
81 debounce-interval = <10>;
82 };
83
84 power-key {
85 gpios = <&gpx2 7 1>;
86 linux,code = <116>;
87 label = "power";
88 debounce-interval = <10>;
89 gpio-key,wakeup;
90 };
91
92 ok-key {
93 gpios = <&gpx3 5 1>;
94 linux,code = <352>;
95 label = "ok";
96 debounce-interval = <10>;
97 };
98 };
99
100 tsp_reg: voltage-regulator {
101 compatible = "regulator-fixed";
102 regulator-name = "TSP_FIXED_VOLTAGES";
103 regulator-min-microvolt = <2800000>;
104 regulator-max-microvolt = <2800000>;
105 gpio = <&gpl0 3 0>;
106 enable-active-high;
107 };
108
109 i2c@13890000 {
110 samsung,i2c-sda-delay = <100>;
111 samsung,i2c-slave-addr = <0x10>;
112 samsung,i2c-max-bus-freq = <400000>;
113 pinctrl-0 = <&i2c3_bus>;
114 pinctrl-names = "default";
115 status = "okay";
116
117 mms114-touchscreen@48 {
118 compatible = "melfas,mms114";
119 reg = <0x48>;
120 interrupt-parent = <&gpx0>;
121 interrupts = <4 2>;
122 x-size = <720>;
123 y-size = <1280>;
124 avdd-supply = <&tsp_reg>;
125 vdd-supply = <&tsp_reg>;
126 };
127 };
128
129 i2c@138B0000 {
130 samsung,i2c-sda-delay = <100>;
131 samsung,i2c-slave-addr = <0x10>;
132 samsung,i2c-max-bus-freq = <100000>;
133 pinctrl-0 = <&i2c5_bus>;
134 pinctrl-names = "default";
135 status = "okay";
136
137 max8997_pmic@66 {
138 compatible = "maxim,max8997-pmic";
139
140 reg = <0x66>;
141
142 max8997,pmic-buck1-uses-gpio-dvs;
143 max8997,pmic-buck2-uses-gpio-dvs;
144 max8997,pmic-buck5-uses-gpio-dvs;
145
146 max8997,pmic-ignore-gpiodvs-side-effect;
147 max8997,pmic-buck125-default-dvs-idx = <0>;
148
149 max8997,pmic-buck125-dvs-gpios = <&gpx0 5 0>,
150 <&gpx0 6 0>,
151 <&gpl0 0 0>;
152
153 max8997,pmic-buck1-dvs-voltage = <1350000>, <1300000>,
154 <1250000>, <1200000>,
155 <1150000>, <1100000>,
156 <1000000>, <950000>;
157
158 max8997,pmic-buck2-dvs-voltage = <1100000>, <1000000>,
159 <950000>, <900000>,
160 <1100000>, <1000000>,
161 <950000>, <900000>;
162
163 max8997,pmic-buck5-dvs-voltage = <1200000>, <1200000>,
164 <1200000>, <1200000>,
165 <1200000>, <1200000>,
166 <1200000>, <1200000>;
167
168 regulators {
169 valive_reg: LDO2 {
170 regulator-name = "VALIVE_1.1V_C210";
171 regulator-min-microvolt = <1100000>;
172 regulator-max-microvolt = <1100000>;
173 regulator-always-on;
174 };
175
176 vusb_reg: LDO3 {
177 regulator-name = "VUSB_1.1V_C210";
178 regulator-min-microvolt = <1100000>;
179 regulator-max-microvolt = <1100000>;
180 };
181
182 vmipi_reg: LDO4 {
183 regulator-name = "VMIPI_1.8V";
184 regulator-min-microvolt = <1800000>;
185 regulator-max-microvolt = <1800000>;
186 };
187
188 vpda_reg: LDO6 {
189 regulator-name = "VCC_1.8V_PDA";
190 regulator-min-microvolt = <1800000>;
191 regulator-max-microvolt = <1800000>;
192 regulator-always-on;
193 };
194
195 vcam_reg: LDO7 {
196 regulator-name = "CAM_ISP_1.8V";
197 regulator-min-microvolt = <1800000>;
198 regulator-max-microvolt = <1800000>;
199 };
200
201 vusbdac_reg: LDO8 {
202 regulator-name = "VUSB/VDAC_3.3V_C210";
203 regulator-min-microvolt = <3300000>;
204 regulator-max-microvolt = <3300000>;
205 };
206
207 vccpda_reg: LDO9 {
208 regulator-name = "VCC_2.8V_PDA";
209 regulator-min-microvolt = <2800000>;
210 regulator-max-microvolt = <2800000>;
211 regulator-always-on;
212 };
213
214 vpll_reg: LDO10 {
215 regulator-name = "VPLL_1.1V_C210";
216 regulator-min-microvolt = <1100000>;
217 regulator-max-microvolt = <1100000>;
218 regulator-always-on;
219 };
220
221 vcclcd_reg: LDO13 {
222 regulator-name = "VCC_3.3V_LCD";
223 regulator-min-microvolt = <3300000>;
224 regulator-max-microvolt = <3300000>;
225 };
226
227 vlcd_reg: LDO15 {
228 regulator-name = "VLCD_2.2V";
229 regulator-min-microvolt = <2200000>;
230 regulator-max-microvolt = <2200000>;
231 };
232
233 camsensor_reg: LDO16 {
234 regulator-name = "CAM_SENSOR_IO_1.8V";
235 regulator-min-microvolt = <1800000>;
236 regulator-max-microvolt = <1800000>;
237 };
238
239 vddq_reg: LDO21 {
240 regulator-name = "VDDQ_M1M2_1.2V";
241 regulator-min-microvolt = <1200000>;
242 regulator-max-microvolt = <1200000>;
243 regulator-always-on;
244 };
245
246 varm_breg: BUCK1 {
247 regulator-name = "VARM_1.2V_C210";
248 regulator-min-microvolt = <900000>;
249 regulator-max-microvolt = <1350000>;
250 regulator-always-on;
251 };
252
253 vint_breg: BUCK2 {
254 regulator-name = "VINT_1.1V_C210";
255 regulator-min-microvolt = <900000>;
256 regulator-max-microvolt = <1100000>;
257 regulator-always-on;
258 };
259
260 camisp_breg: BUCK4 {
261 regulator-name = "CAM_ISP_CORE_1.2V";
262 regulator-min-microvolt = <1200000>;
263 regulator-max-microvolt = <1200000>;
264 };
265
266 vmem_breg: BUCK5 {
267 regulator-name = "VMEM_1.2V_C210";
268 regulator-min-microvolt = <1200000>;
269 regulator-max-microvolt = <1200000>;
270 regulator-always-on;
271 };
272
273 vccsub_breg: BUCK7 {
274 regulator-name = "VCC_SUB_2.0V";
275 regulator-min-microvolt = <2000000>;
276 regulator-max-microvolt = <2000000>;
277 regulator-always-on;
278 };
279
280 safe1_sreg: ESAFEOUT1 {
281 regulator-name = "SAFEOUT1";
282 regulator-always-on;
283 };
284
285 safe2_sreg: ESAFEOUT2 {
286 regulator-name = "SAFEOUT2";
287 regulator-boot-on;
288 };
289 };
290 };
291 };
292};
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
deleted file mode 100644
index e31bfc4a6f0..00000000000
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ /dev/null
@@ -1,79 +0,0 @@
1/*
2 * Samsung's Exynos4210 SoC device tree source
3 *
4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2010-2011 Linaro Ltd.
7 * www.linaro.org
8 *
9 * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
10 * based board files can include this file and provide values for board specfic
11 * bindings.
12 *
13 * Note: This file does not include device nodes for all the controllers in
14 * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
15 * nodes can be added to this file.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20*/
21
22/include/ "exynos4.dtsi"
23/include/ "exynos4210-pinctrl.dtsi"
24
25/ {
26 compatible = "samsung,exynos4210";
27
28 aliases {
29 pinctrl0 = &pinctrl_0;
30 pinctrl1 = &pinctrl_1;
31 pinctrl2 = &pinctrl_2;
32 };
33
34 pd_lcd1: lcd1-power-domain@10023CA0 {
35 compatible = "samsung,exynos4210-pd";
36 reg = <0x10023CA0 0x20>;
37 };
38
39 gic:interrupt-controller@10490000 {
40 cpu-offset = <0x8000>;
41 };
42
43 combiner:interrupt-controller@10440000 {
44 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
45 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
46 <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
47 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
48 };
49
50 pinctrl_0: pinctrl@11400000 {
51 compatible = "samsung,pinctrl-exynos4210";
52 reg = <0x11400000 0x1000>;
53 interrupts = <0 47 0>;
54 };
55
56 pinctrl_1: pinctrl@11000000 {
57 compatible = "samsung,pinctrl-exynos4210";
58 reg = <0x11000000 0x1000>;
59 interrupts = <0 46 0>;
60
61 wakup_eint: wakeup-interrupt-controller {
62 compatible = "samsung,exynos4210-wakeup-eint";
63 interrupt-parent = <&gic>;
64 interrupts = <0 32 0>;
65 };
66 };
67
68 pinctrl_2: pinctrl@03860000 {
69 compatible = "samsung,pinctrl-exynos4210";
70 reg = <0x03860000 0x1000>;
71 };
72
73 tmu@100C0000 {
74 compatible = "samsung,exynos4210-tmu";
75 interrupt-parent = <&combiner>;
76 reg = <0x100C0000 0x100>;
77 interrupts = <2 4>;
78 };
79};
diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi
deleted file mode 100644
index c6ae2005961..00000000000
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * Samsung's Exynos4212 SoC device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Samsung's Exynos4212 SoC device nodes are listed in this file. Exynos4212
8 * based board files can include this file and provide values for board specfic
9 * bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * Exynos4212 SoC. As device tree coverage for Exynos4212 increases, additional
13 * nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18*/
19
20/include/ "exynos4x12.dtsi"
21
22/ {
23 compatible = "samsung,exynos4212";
24
25 gic:interrupt-controller@10490000 {
26 cpu-offset = <0x8000>;
27 };
28};
diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts
deleted file mode 100644
index f05bf575cc4..00000000000
--- a/arch/arm/boot/dts/exynos4412-smdk4412.dts
+++ /dev/null
@@ -1,45 +0,0 @@
1/*
2 * Samsung's Exynos4412 based SMDK board device tree source
3 *
4 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Device tree source file for Samsung's SMDK4412 board which is based on
8 * Samsung's Exynos4412 SoC.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15/dts-v1/;
16/include/ "exynos4412.dtsi"
17
18/ {
19 model = "Samsung SMDK evaluation board based on Exynos4412";
20 compatible = "samsung,smdk4412", "samsung,exynos4412";
21
22 memory {
23 reg = <0x40000000 0x40000000>;
24 };
25
26 chosen {
27 bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc";
28 };
29
30 serial@13800000 {
31 status = "okay";
32 };
33
34 serial@13810000 {
35 status = "okay";
36 };
37
38 serial@13820000 {
39 status = "okay";
40 };
41
42 serial@13830000 {
43 status = "okay";
44 };
45};
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
deleted file mode 100644
index d7dfe312772..00000000000
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * Samsung's Exynos4412 SoC device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412
8 * based board files can include this file and provide values for board specfic
9 * bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional
13 * nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18*/
19
20/include/ "exynos4x12.dtsi"
21
22/ {
23 compatible = "samsung,exynos4412";
24
25 gic:interrupt-controller@10490000 {
26 cpu-offset = <0x4000>;
27 };
28};
diff --git a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
deleted file mode 100644
index 8e6115adcd9..00000000000
--- a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
+++ /dev/null
@@ -1,965 +0,0 @@
1/*
2 * Samsung's Exynos4x12 SoCs pin-mux and pin-config device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Samsung's Exynos4x12 SoCs pin-mux and pin-config optiosn are listed as device
8 * tree nodes are listed in this file.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15/ {
16 pinctrl@11400000 {
17 gpa0: gpa0 {
18 gpio-controller;
19 #gpio-cells = <2>;
20
21 interrupt-controller;
22 #interrupt-cells = <2>;
23 };
24
25 gpa1: gpa1 {
26 gpio-controller;
27 #gpio-cells = <2>;
28
29 interrupt-controller;
30 #interrupt-cells = <2>;
31 };
32
33 gpb: gpb {
34 gpio-controller;
35 #gpio-cells = <2>;
36
37 interrupt-controller;
38 #interrupt-cells = <2>;
39 };
40
41 gpc0: gpc0 {
42 gpio-controller;
43 #gpio-cells = <2>;
44
45 interrupt-controller;
46 #interrupt-cells = <2>;
47 };
48
49 gpc1: gpc1 {
50 gpio-controller;
51 #gpio-cells = <2>;
52
53 interrupt-controller;
54 #interrupt-cells = <2>;
55 };
56
57 gpd0: gpd0 {
58 gpio-controller;
59 #gpio-cells = <2>;
60
61 interrupt-controller;
62 #interrupt-cells = <2>;
63 };
64
65 gpd1: gpd1 {
66 gpio-controller;
67 #gpio-cells = <2>;
68
69 interrupt-controller;
70 #interrupt-cells = <2>;
71 };
72
73 gpf0: gpf0 {
74 gpio-controller;
75 #gpio-cells = <2>;
76
77 interrupt-controller;
78 #interrupt-cells = <2>;
79 };
80
81 gpf1: gpf1 {
82 gpio-controller;
83 #gpio-cells = <2>;
84
85 interrupt-controller;
86 #interrupt-cells = <2>;
87 };
88
89 gpf2: gpf2 {
90 gpio-controller;
91 #gpio-cells = <2>;
92
93 interrupt-controller;
94 #interrupt-cells = <2>;
95 };
96
97 gpf3: gpf3 {
98 gpio-controller;
99 #gpio-cells = <2>;
100
101 interrupt-controller;
102 #interrupt-cells = <2>;
103 };
104
105 gpj0: gpj0 {
106 gpio-controller;
107 #gpio-cells = <2>;
108
109 interrupt-controller;
110 #interrupt-cells = <2>;
111 };
112
113 gpj1: gpj1 {
114 gpio-controller;
115 #gpio-cells = <2>;
116
117 interrupt-controller;
118 #interrupt-cells = <2>;
119 };
120
121 uart0_data: uart0-data {
122 samsung,pins = "gpa0-0", "gpa0-1";
123 samsung,pin-function = <0x2>;
124 samsung,pin-pud = <0>;
125 samsung,pin-drv = <0>;
126 };
127
128 uart0_fctl: uart0-fctl {
129 samsung,pins = "gpa0-2", "gpa0-3";
130 samsung,pin-function = <2>;
131 samsung,pin-pud = <0>;
132 samsung,pin-drv = <0>;
133 };
134
135 uart1_data: uart1-data {
136 samsung,pins = "gpa0-4", "gpa0-5";
137 samsung,pin-function = <2>;
138 samsung,pin-pud = <0>;
139 samsung,pin-drv = <0>;
140 };
141
142 uart1_fctl: uart1-fctl {
143 samsung,pins = "gpa0-6", "gpa0-7";
144 samsung,pin-function = <2>;
145 samsung,pin-pud = <0>;
146 samsung,pin-drv = <0>;
147 };
148
149 i2c2_bus: i2c2-bus {
150 samsung,pins = "gpa0-6", "gpa0-7";
151 samsung,pin-function = <3>;
152 samsung,pin-pud = <3>;
153 samsung,pin-drv = <0>;
154 };
155
156 uart2_data: uart2-data {
157 samsung,pins = "gpa1-0", "gpa1-1";
158 samsung,pin-function = <2>;
159 samsung,pin-pud = <0>;
160 samsung,pin-drv = <0>;
161 };
162
163 uart2_fctl: uart2-fctl {
164 samsung,pins = "gpa1-2", "gpa1-3";
165 samsung,pin-function = <2>;
166 samsung,pin-pud = <0>;
167 samsung,pin-drv = <0>;
168 };
169
170 uart_audio_a: uart-audio-a {
171 samsung,pins = "gpa1-0", "gpa1-1";
172 samsung,pin-function = <4>;
173 samsung,pin-pud = <0>;
174 samsung,pin-drv = <0>;
175 };
176
177 i2c3_bus: i2c3-bus {
178 samsung,pins = "gpa1-2", "gpa1-3";
179 samsung,pin-function = <3>;
180 samsung,pin-pud = <3>;
181 samsung,pin-drv = <0>;
182 };
183
184 uart3_data: uart3-data {
185 samsung,pins = "gpa1-4", "gpa1-5";
186 samsung,pin-function = <2>;
187 samsung,pin-pud = <0>;
188 samsung,pin-drv = <0>;
189 };
190
191 uart_audio_b: uart-audio-b {
192 samsung,pins = "gpa1-4", "gpa1-5";
193 samsung,pin-function = <4>;
194 samsung,pin-pud = <0>;
195 samsung,pin-drv = <0>;
196 };
197
198 spi0_bus: spi0-bus {
199 samsung,pins = "gpb-0", "gpb-2", "gpb-3";
200 samsung,pin-function = <2>;
201 samsung,pin-pud = <3>;
202 samsung,pin-drv = <0>;
203 };
204
205 i2c4_bus: i2c4-bus {
206 samsung,pins = "gpb-0", "gpb-1";
207 samsung,pin-function = <3>;
208 samsung,pin-pud = <3>;
209 samsung,pin-drv = <0>;
210 };
211
212 spi1_bus: spi1-bus {
213 samsung,pins = "gpb-4", "gpb-6", "gpb-7";
214 samsung,pin-function = <2>;
215 samsung,pin-pud = <3>;
216 samsung,pin-drv = <0>;
217 };
218
219 i2c5_bus: i2c5-bus {
220 samsung,pins = "gpb-2", "gpb-3";
221 samsung,pin-function = <3>;
222 samsung,pin-pud = <3>;
223 samsung,pin-drv = <0>;
224 };
225
226 i2s1_bus: i2s1-bus {
227 samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
228 "gpc0-4";
229 samsung,pin-function = <2>;
230 samsung,pin-pud = <0>;
231 samsung,pin-drv = <0>;
232 };
233
234 pcm1_bus: pcm1-bus {
235 samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
236 "gpc0-4";
237 samsung,pin-function = <3>;
238 samsung,pin-pud = <0>;
239 samsung,pin-drv = <0>;
240 };
241
242 ac97_bus: ac97-bus {
243 samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
244 "gpc0-4";
245 samsung,pin-function = <4>;
246 samsung,pin-pud = <0>;
247 samsung,pin-drv = <0>;
248 };
249
250 i2s2_bus: i2s2-bus {
251 samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
252 "gpc1-4";
253 samsung,pin-function = <2>;
254 samsung,pin-pud = <0>;
255 samsung,pin-drv = <0>;
256 };
257
258 pcm2_bus: pcm2-bus {
259 samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
260 "gpc1-4";
261 samsung,pin-function = <3>;
262 samsung,pin-pud = <0>;
263 samsung,pin-drv = <0>;
264 };
265
266 spdif_bus: spdif-bus {
267 samsung,pins = "gpc1-0", "gpc1-1";
268 samsung,pin-function = <4>;
269 samsung,pin-pud = <0>;
270 samsung,pin-drv = <0>;
271 };
272
273 i2c6_bus: i2c6-bus {
274 samsung,pins = "gpc1-3", "gpc1-4";
275 samsung,pin-function = <4>;
276 samsung,pin-pud = <3>;
277 samsung,pin-drv = <0>;
278 };
279
280 spi2_bus: spi2-bus {
281 samsung,pins = "gpc1-1", "gpc1-3", "gpc1-4";
282 samsung,pin-function = <5>;
283 samsung,pin-pud = <3>;
284 samsung,pin-drv = <0>;
285 };
286
287 pwm0_out: pwm0-out {
288 samsung,pins = "gpd0-0";
289 samsung,pin-function = <2>;
290 samsung,pin-pud = <0>;
291 samsung,pin-drv = <0>;
292 };
293
294 pwm1_out: pwm1-out {
295 samsung,pins = "gpd0-1";
296 samsung,pin-function = <2>;
297 samsung,pin-pud = <0>;
298 samsung,pin-drv = <0>;
299 };
300
301 lcd_ctrl: lcd-ctrl {
302 samsung,pins = "gpd0-0", "gpd0-1";
303 samsung,pin-function = <3>;
304 samsung,pin-pud = <0>;
305 samsung,pin-drv = <0>;
306 };
307
308 i2c7_bus: i2c7-bus {
309 samsung,pins = "gpd0-2", "gpd0-3";
310 samsung,pin-function = <3>;
311 samsung,pin-pud = <3>;
312 samsung,pin-drv = <0>;
313 };
314
315 pwm2_out: pwm2-out {
316 samsung,pins = "gpd0-2";
317 samsung,pin-function = <2>;
318 samsung,pin-pud = <0>;
319 samsung,pin-drv = <0>;
320 };
321
322 pwm3_out: pwm3-out {
323 samsung,pins = "gpd0-3";
324 samsung,pin-function = <2>;
325 samsung,pin-pud = <0>;
326 samsung,pin-drv = <0>;
327 };
328
329 i2c0_bus: i2c0-bus {
330 samsung,pins = "gpd1-0", "gpd1-1";
331 samsung,pin-function = <2>;
332 samsung,pin-pud = <3>;
333 samsung,pin-drv = <0>;
334 };
335
336 mipi0_clk: mipi0-clk {
337 samsung,pins = "gpd1-0", "gpd1-1";
338 samsung,pin-function = <3>;
339 samsung,pin-pud = <0>;
340 samsung,pin-drv = <0>;
341 };
342
343 i2c1_bus: i2c1-bus {
344 samsung,pins = "gpd1-2", "gpd1-3";
345 samsung,pin-function = <2>;
346 samsung,pin-pud = <3>;
347 samsung,pin-drv = <0>;
348 };
349
350 mipi1_clk: mipi1-clk {
351 samsung,pins = "gpd1-2", "gpd1-3";
352 samsung,pin-function = <3>;
353 samsung,pin-pud = <0>;
354 samsung,pin-drv = <0>;
355 };
356
357 lcd_clk: lcd-clk {
358 samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3";
359 samsung,pin-function = <2>;
360 samsung,pin-pud = <0>;
361 samsung,pin-drv = <0>;
362 };
363
364 lcd_data16: lcd-data-width16 {
365 samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2",
366 "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0",
367 "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7",
368 "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3";
369 samsung,pin-function = <2>;
370 samsung,pin-pud = <0>;
371 samsung,pin-drv = <0>;
372 };
373
374 lcd_data18: lcd-data-width18 {
375 samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1",
376 "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7",
377 "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
378 "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1",
379 "gpf3-2", "gpf3-3";
380 samsung,pin-function = <2>;
381 samsung,pin-pud = <0>;
382 samsung,pin-drv = <0>;
383 };
384
385 lcd_data24: lcd-data-width24 {
386 samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7",
387 "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3",
388 "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7",
389 "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
390 "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7",
391 "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3";
392 samsung,pin-function = <2>;
393 samsung,pin-pud = <0>;
394 samsung,pin-drv = <0>;
395 };
396
397 lcd_ldi: lcd-ldi {
398 samsung,pins = "gpf3-4";
399 samsung,pin-function = <2>;
400 samsung,pin-pud = <0>;
401 samsung,pin-drv = <0>;
402 };
403
404 cam_port_a: cam-port-a {
405 samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3",
406 "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7",
407 "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-3",
408 "gpj1-4";
409 samsung,pin-function = <2>;
410 samsung,pin-pud = <3>;
411 samsung,pin-drv = <0>;
412 };
413 };
414
415 pinctrl@11000000 {
416 gpk0: gpk0 {
417 gpio-controller;
418 #gpio-cells = <2>;
419
420 interrupt-controller;
421 #interrupt-cells = <2>;
422 };
423
424 gpk1: gpk1 {
425 gpio-controller;
426 #gpio-cells = <2>;
427
428 interrupt-controller;
429 #interrupt-cells = <2>;
430 };
431
432 gpk2: gpk2 {
433 gpio-controller;
434 #gpio-cells = <2>;
435
436 interrupt-controller;
437 #interrupt-cells = <2>;
438 };
439
440 gpk3: gpk3 {
441 gpio-controller;
442 #gpio-cells = <2>;
443
444 interrupt-controller;
445 #interrupt-cells = <2>;
446 };
447
448 gpl0: gpl0 {
449 gpio-controller;
450 #gpio-cells = <2>;
451
452 interrupt-controller;
453 #interrupt-cells = <2>;
454 };
455
456 gpl1: gpl1 {
457 gpio-controller;
458 #gpio-cells = <2>;
459
460 interrupt-controller;
461 #interrupt-cells = <2>;
462 };
463
464 gpl2: gpl2 {
465 gpio-controller;
466 #gpio-cells = <2>;
467
468 interrupt-controller;
469 #interrupt-cells = <2>;
470 };
471
472 gpm0: gpm0 {
473 gpio-controller;
474 #gpio-cells = <2>;
475
476 interrupt-controller;
477 #interrupt-cells = <2>;
478 };
479
480 gpm1: gpm1 {
481 gpio-controller;
482 #gpio-cells = <2>;
483
484 interrupt-controller;
485 #interrupt-cells = <2>;
486 };
487
488 gpm2: gpm2 {
489 gpio-controller;
490 #gpio-cells = <2>;
491
492 interrupt-controller;
493 #interrupt-cells = <2>;
494 };
495
496 gpm3: gpm3 {
497 gpio-controller;
498 #gpio-cells = <2>;
499
500 interrupt-controller;
501 #interrupt-cells = <2>;
502 };
503
504 gpm4: gpm4 {
505 gpio-controller;
506 #gpio-cells = <2>;
507
508 interrupt-controller;
509 #interrupt-cells = <2>;
510 };
511
512 gpy0: gpy0 {
513 gpio-controller;
514 #gpio-cells = <2>;
515 };
516
517 gpy1: gpy1 {
518 gpio-controller;
519 #gpio-cells = <2>;
520 };
521
522 gpy2: gpy2 {
523 gpio-controller;
524 #gpio-cells = <2>;
525 };
526
527 gpy3: gpy3 {
528 gpio-controller;
529 #gpio-cells = <2>;
530 };
531
532 gpy4: gpy4 {
533 gpio-controller;
534 #gpio-cells = <2>;
535 };
536
537 gpy5: gpy5 {
538 gpio-controller;
539 #gpio-cells = <2>;
540 };
541
542 gpy6: gpy6 {
543 gpio-controller;
544 #gpio-cells = <2>;
545 };
546
547 gpx0: gpx0 {
548 gpio-controller;
549 #gpio-cells = <2>;
550
551 interrupt-controller;
552 interrupt-parent = <&gic>;
553 interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
554 <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>;
555 #interrupt-cells = <2>;
556 };
557
558 gpx1: gpx1 {
559 gpio-controller;
560 #gpio-cells = <2>;
561
562 interrupt-controller;
563 interrupt-parent = <&gic>;
564 interrupts = <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
565 <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
566 #interrupt-cells = <2>;
567 };
568
569 gpx2: gpx2 {
570 gpio-controller;
571 #gpio-cells = <2>;
572
573 interrupt-controller;
574 #interrupt-cells = <2>;
575 };
576
577 gpx3: gpx3 {
578 gpio-controller;
579 #gpio-cells = <2>;
580
581 interrupt-controller;
582 #interrupt-cells = <2>;
583 };
584
585 sd0_clk: sd0-clk {
586 samsung,pins = "gpk0-0";
587 samsung,pin-function = <2>;
588 samsung,pin-pud = <0>;
589 samsung,pin-drv = <3>;
590 };
591
592 sd0_cmd: sd0-cmd {
593 samsung,pins = "gpk0-1";
594 samsung,pin-function = <2>;
595 samsung,pin-pud = <0>;
596 samsung,pin-drv = <3>;
597 };
598
599 sd0_cd: sd0-cd {
600 samsung,pins = "gpk0-2";
601 samsung,pin-function = <2>;
602 samsung,pin-pud = <3>;
603 samsung,pin-drv = <3>;
604 };
605
606 sd0_bus1: sd0-bus-width1 {
607 samsung,pins = "gpk0-3";
608 samsung,pin-function = <2>;
609 samsung,pin-pud = <3>;
610 samsung,pin-drv = <3>;
611 };
612
613 sd0_bus4: sd0-bus-width4 {
614 samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
615 samsung,pin-function = <2>;
616 samsung,pin-pud = <3>;
617 samsung,pin-drv = <3>;
618 };
619
620 sd0_bus8: sd0-bus-width8 {
621 samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
622 samsung,pin-function = <3>;
623 samsung,pin-pud = <3>;
624 samsung,pin-drv = <3>;
625 };
626
627 sd4_clk: sd4-clk {
628 samsung,pins = "gpk0-0";
629 samsung,pin-function = <3>;
630 samsung,pin-pud = <0>;
631 samsung,pin-drv = <3>;
632 };
633
634 sd4_cmd: sd4-cmd {
635 samsung,pins = "gpk0-1";
636 samsung,pin-function = <3>;
637 samsung,pin-pud = <0>;
638 samsung,pin-drv = <3>;
639 };
640
641 sd4_cd: sd4-cd {
642 samsung,pins = "gpk0-2";
643 samsung,pin-function = <3>;
644 samsung,pin-pud = <3>;
645 samsung,pin-drv = <3>;
646 };
647
648 sd4_bus1: sd4-bus-width1 {
649 samsung,pins = "gpk0-3";
650 samsung,pin-function = <3>;
651 samsung,pin-pud = <3>;
652 samsung,pin-drv = <3>;
653 };
654
655 sd4_bus4: sd4-bus-width4 {
656 samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
657 samsung,pin-function = <3>;
658 samsung,pin-pud = <3>;
659 samsung,pin-drv = <3>;
660 };
661
662 sd4_bus8: sd4-bus-width8 {
663 samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
664 samsung,pin-function = <3>;
665 samsung,pin-pud = <4>;
666 samsung,pin-drv = <3>;
667 };
668
669 sd1_clk: sd1-clk {
670 samsung,pins = "gpk1-0";
671 samsung,pin-function = <2>;
672 samsung,pin-pud = <0>;
673 samsung,pin-drv = <3>;
674 };
675
676 sd1_cmd: sd1-cmd {
677 samsung,pins = "gpk1-1";
678 samsung,pin-function = <2>;
679 samsung,pin-pud = <0>;
680 samsung,pin-drv = <3>;
681 };
682
683 sd1_cd: sd1-cd {
684 samsung,pins = "gpk1-2";
685 samsung,pin-function = <2>;
686 samsung,pin-pud = <3>;
687 samsung,pin-drv = <3>;
688 };
689
690 sd1_bus1: sd1-bus-width1 {
691 samsung,pins = "gpk1-3";
692 samsung,pin-function = <2>;
693 samsung,pin-pud = <3>;
694 samsung,pin-drv = <3>;
695 };
696
697 sd1_bus4: sd1-bus-width4 {
698 samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
699 samsung,pin-function = <2>;
700 samsung,pin-pud = <3>;
701 samsung,pin-drv = <3>;
702 };
703
704 sd2_clk: sd2-clk {
705 samsung,pins = "gpk2-0";
706 samsung,pin-function = <2>;
707 samsung,pin-pud = <0>;
708 samsung,pin-drv = <3>;
709 };
710
711 sd2_cmd: sd2-cmd {
712 samsung,pins = "gpk2-1";
713 samsung,pin-function = <2>;
714 samsung,pin-pud = <0>;
715 samsung,pin-drv = <3>;
716 };
717
718 sd2_cd: sd2-cd {
719 samsung,pins = "gpk2-2";
720 samsung,pin-function = <2>;
721 samsung,pin-pud = <3>;
722 samsung,pin-drv = <3>;
723 };
724
725 sd2_bus1: sd2-bus-width1 {
726 samsung,pins = "gpk2-3";
727 samsung,pin-function = <2>;
728 samsung,pin-pud = <3>;
729 samsung,pin-drv = <3>;
730 };
731
732 sd2_bus4: sd2-bus-width4 {
733 samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6";
734 samsung,pin-function = <2>;
735 samsung,pin-pud = <3>;
736 samsung,pin-drv = <3>;
737 };
738
739 sd2_bus8: sd2-bus-width8 {
740 samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
741 samsung,pin-function = <3>;
742 samsung,pin-pud = <3>;
743 samsung,pin-drv = <3>;
744 };
745
746 sd3_clk: sd3-clk {
747 samsung,pins = "gpk3-0";
748 samsung,pin-function = <2>;
749 samsung,pin-pud = <0>;
750 samsung,pin-drv = <3>;
751 };
752
753 sd3_cmd: sd3-cmd {
754 samsung,pins = "gpk3-1";
755 samsung,pin-function = <2>;
756 samsung,pin-pud = <0>;
757 samsung,pin-drv = <3>;
758 };
759
760 sd3_cd: sd3-cd {
761 samsung,pins = "gpk3-2";
762 samsung,pin-function = <2>;
763 samsung,pin-pud = <3>;
764 samsung,pin-drv = <3>;
765 };
766
767 sd3_bus1: sd3-bus-width1 {
768 samsung,pins = "gpk3-3";
769 samsung,pin-function = <2>;
770 samsung,pin-pud = <3>;
771 samsung,pin-drv = <3>;
772 };
773
774 sd3_bus4: sd3-bus-width4 {
775 samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
776 samsung,pin-function = <2>;
777 samsung,pin-pud = <3>;
778 samsung,pin-drv = <3>;
779 };
780
781 keypad_col0: keypad-col0 {
782 samsung,pins = "gpl2-0";
783 samsung,pin-function = <3>;
784 samsung,pin-pud = <0>;
785 samsung,pin-drv = <0>;
786 };
787
788 keypad_col1: keypad-col1 {
789 samsung,pins = "gpl2-1";
790 samsung,pin-function = <3>;
791 samsung,pin-pud = <0>;
792 samsung,pin-drv = <0>;
793 };
794
795 keypad_col2: keypad-col2 {
796 samsung,pins = "gpl2-2";
797 samsung,pin-function = <3>;
798 samsung,pin-pud = <0>;
799 samsung,pin-drv = <0>;
800 };
801
802 keypad_col3: keypad-col3 {
803 samsung,pins = "gpl2-3";
804 samsung,pin-function = <3>;
805 samsung,pin-pud = <0>;
806 samsung,pin-drv = <0>;
807 };
808
809 keypad_col4: keypad-col4 {
810 samsung,pins = "gpl2-4";
811 samsung,pin-function = <3>;
812 samsung,pin-pud = <0>;
813 samsung,pin-drv = <0>;
814 };
815
816 keypad_col5: keypad-col5 {
817 samsung,pins = "gpl2-5";
818 samsung,pin-function = <3>;
819 samsung,pin-pud = <0>;
820 samsung,pin-drv = <0>;
821 };
822
823 keypad_col6: keypad-col6 {
824 samsung,pins = "gpl2-6";
825 samsung,pin-function = <3>;
826 samsung,pin-pud = <0>;
827 samsung,pin-drv = <0>;
828 };
829
830 keypad_col7: keypad-col7 {
831 samsung,pins = "gpl2-7";
832 samsung,pin-function = <3>;
833 samsung,pin-pud = <0>;
834 samsung,pin-drv = <0>;
835 };
836
837 cam_port_b: cam-port-b {
838 samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3",
839 "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7",
840 "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1",
841 "gpm2-2";
842 samsung,pin-function = <3>;
843 samsung,pin-pud = <3>;
844 samsung,pin-drv = <0>;
845 };
846
847 eint0: ext-int0 {
848 samsung,pins = "gpx0-0";
849 samsung,pin-function = <0xf>;
850 samsung,pin-pud = <0>;
851 samsung,pin-drv = <0>;
852 };
853
854 eint8: ext-int8 {
855 samsung,pins = "gpx1-0";
856 samsung,pin-function = <0xf>;
857 samsung,pin-pud = <0>;
858 samsung,pin-drv = <0>;
859 };
860
861 eint15: ext-int15 {
862 samsung,pins = "gpx1-7";
863 samsung,pin-function = <0xf>;
864 samsung,pin-pud = <0>;
865 samsung,pin-drv = <0>;
866 };
867
868 eint16: ext-int16 {
869 samsung,pins = "gpx2-0";
870 samsung,pin-function = <0xf>;
871 samsung,pin-pud = <0>;
872 samsung,pin-drv = <0>;
873 };
874
875 eint31: ext-int31 {
876 samsung,pins = "gpx3-7";
877 samsung,pin-function = <0xf>;
878 samsung,pin-pud = <0>;
879 samsung,pin-drv = <0>;
880 };
881 };
882
883 pinctrl@03860000 {
884 gpz: gpz {
885 gpio-controller;
886 #gpio-cells = <2>;
887
888 interrupt-controller;
889 #interrupt-cells = <2>;
890 };
891
892 i2s0_bus: i2s0-bus {
893 samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
894 "gpz-4", "gpz-5", "gpz-6";
895 samsung,pin-function = <0x2>;
896 samsung,pin-pud = <0>;
897 samsung,pin-drv = <0>;
898 };
899
900 pcm0_bus: pcm0-bus {
901 samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
902 "gpz-4";
903 samsung,pin-function = <0x3>;
904 samsung,pin-pud = <0>;
905 samsung,pin-drv = <0>;
906 };
907 };
908
909 pinctrl@106E0000 {
910 gpv0: gpv0 {
911 gpio-controller;
912 #gpio-cells = <2>;
913
914 interrupt-controller;
915 #interrupt-cells = <2>;
916 };
917
918 gpv1: gpv1 {
919 gpio-controller;
920 #gpio-cells = <2>;
921
922 interrupt-controller;
923 #interrupt-cells = <2>;
924 };
925
926 gpv2: gpv2 {
927 gpio-controller;
928 #gpio-cells = <2>;
929
930 interrupt-controller;
931 #interrupt-cells = <2>;
932 };
933
934 gpv3: gpv3 {
935 gpio-controller;
936 #gpio-cells = <2>;
937
938 interrupt-controller;
939 #interrupt-cells = <2>;
940 };
941
942 gpv4: gpv4 {
943 gpio-controller;
944 #gpio-cells = <2>;
945
946 interrupt-controller;
947 #interrupt-cells = <2>;
948 };
949
950 c2c_bus: c2c-bus {
951 samsung,pins = "gpv0-0", "gpv0-1", "gpv0-2", "gpv0-3",
952 "gpv0-4", "gpv0-5", "gpv0-6", "gpv0-7",
953 "gpv1-0", "gpv1-1", "gpv1-2", "gpv1-3",
954 "gpv1-4", "gpv1-5", "gpv1-6", "gpv1-7",
955 "gpv2-0", "gpv2-1", "gpv2-2", "gpv2-3",
956 "gpv2-4", "gpv2-5", "gpv2-6", "gpv2-7",
957 "gpv3-0", "gpv3-1", "gpv3-2", "gpv3-3",
958 "gpv3-4", "gpv3-5", "gpv3-6", "gpv3-7",
959 "gpv4-0", "gpv4-1";
960 samsung,pin-function = <0x2>;
961 samsung,pin-pud = <0>;
962 samsung,pin-drv = <0>;
963 };
964 };
965};
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
deleted file mode 100644
index 179a62e46c9..00000000000
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ /dev/null
@@ -1,69 +0,0 @@
1/*
2 * Samsung's Exynos4x12 SoCs device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12
8 * based board files can include this file and provide values for board specfic
9 * bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional
13 * nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18*/
19
20/include/ "exynos4.dtsi"
21/include/ "exynos4x12-pinctrl.dtsi"
22
23/ {
24 aliases {
25 pinctrl0 = &pinctrl_0;
26 pinctrl1 = &pinctrl_1;
27 pinctrl2 = &pinctrl_2;
28 pinctrl3 = &pinctrl_3;
29 };
30
31 combiner:interrupt-controller@10440000 {
32 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
33 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
34 <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
35 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
36 <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>;
37 };
38
39 pinctrl_0: pinctrl@11400000 {
40 compatible = "samsung,pinctrl-exynos4x12";
41 reg = <0x11400000 0x1000>;
42 interrupts = <0 47 0>;
43 };
44
45 pinctrl_1: pinctrl@11000000 {
46 compatible = "samsung,pinctrl-exynos4x12";
47 reg = <0x11000000 0x1000>;
48 interrupts = <0 46 0>;
49
50 wakup_eint: wakeup-interrupt-controller {
51 compatible = "samsung,exynos4210-wakeup-eint";
52 interrupt-parent = <&gic>;
53 interrupts = <0 32 0>;
54 };
55 };
56
57 pinctrl_2: pinctrl@03860000 {
58 compatible = "samsung,pinctrl-exynos4x12";
59 reg = <0x03860000 0x1000>;
60 interrupt-parent = <&combiner>;
61 interrupts = <10 0>;
62 };
63
64 pinctrl_3: pinctrl@106E0000 {
65 compatible = "samsung,pinctrl-exynos4x12";
66 reg = <0x106E0000 0x1000>;
67 interrupts = <0 72 0>;
68 };
69};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
deleted file mode 100644
index 942d5761ca9..00000000000
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ /dev/null
@@ -1,207 +0,0 @@
1/*
2 * SAMSUNG SMDK5250 board device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12/dts-v1/;
13/include/ "exynos5250.dtsi"
14
15/ {
16 model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
17 compatible = "samsung,smdk5250", "samsung,exynos5250";
18
19 aliases {
20 };
21
22 memory {
23 reg = <0x40000000 0x80000000>;
24 };
25
26 chosen {
27 bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
28 };
29
30 i2c@12C60000 {
31 samsung,i2c-sda-delay = <100>;
32 samsung,i2c-max-bus-freq = <20000>;
33 gpios = <&gpb3 0 2 3 0>,
34 <&gpb3 1 2 3 0>;
35
36 eeprom@50 {
37 compatible = "samsung,s524ad0xd1";
38 reg = <0x50>;
39 };
40 };
41
42 i2c@12C70000 {
43 samsung,i2c-sda-delay = <100>;
44 samsung,i2c-max-bus-freq = <20000>;
45 gpios = <&gpb3 2 2 3 0>,
46 <&gpb3 3 2 3 0>;
47
48 eeprom@51 {
49 compatible = "samsung,s524ad0xd1";
50 reg = <0x51>;
51 };
52 };
53
54 i2c@121D0000 {
55 samsung,i2c-sda-delay = <100>;
56 samsung,i2c-max-bus-freq = <40000>;
57 samsung,i2c-slave-addr = <0x38>;
58
59 sata-phy {
60 compatible = "samsung,sata-phy";
61 reg = <0x38>;
62 };
63 };
64
65 sata@122F0000 {
66 samsung,sata-freq = <66>;
67 };
68
69 i2c@12C80000 {
70 samsung,i2c-sda-delay = <100>;
71 samsung,i2c-max-bus-freq = <66000>;
72 gpios = <&gpa0 6 3 3 0>,
73 <&gpa0 7 3 3 0>;
74
75 hdmiddc@50 {
76 compatible = "samsung,exynos5-hdmiddc";
77 reg = <0x50>;
78 };
79 };
80
81 i2c@12C90000 {
82 status = "disabled";
83 };
84
85 i2c@12CA0000 {
86 status = "disabled";
87 };
88
89 i2c@12CB0000 {
90 status = "disabled";
91 };
92
93 i2c@12CC0000 {
94 status = "disabled";
95 };
96
97 i2c@12CD0000 {
98 status = "disabled";
99 };
100
101 i2c@12CE0000 {
102 samsung,i2c-sda-delay = <100>;
103 samsung,i2c-max-bus-freq = <66000>;
104
105 hdmiphy@38 {
106 compatible = "samsung,exynos5-hdmiphy";
107 reg = <0x38>;
108 };
109 };
110
111 dwmmc0@12200000 {
112 num-slots = <1>;
113 supports-highspeed;
114 broken-cd;
115 fifo-depth = <0x80>;
116 card-detect-delay = <200>;
117 samsung,dw-mshc-ciu-div = <3>;
118 samsung,dw-mshc-sdr-timing = <2 3 3>;
119 samsung,dw-mshc-ddr-timing = <1 2 3>;
120
121 slot@0 {
122 reg = <0>;
123 bus-width = <8>;
124 gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>,
125 <&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>,
126 <&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>,
127 <&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>,
128 <&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>;
129 };
130 };
131
132 dwmmc1@12210000 {
133 status = "disabled";
134 };
135
136 dwmmc2@12220000 {
137 num-slots = <1>;
138 supports-highspeed;
139 fifo-depth = <0x80>;
140 card-detect-delay = <200>;
141 samsung,dw-mshc-ciu-div = <3>;
142 samsung,dw-mshc-sdr-timing = <2 3 3>;
143 samsung,dw-mshc-ddr-timing = <1 2 3>;
144
145 slot@0 {
146 reg = <0>;
147 bus-width = <4>;
148 samsung,cd-pinmux-gpio = <&gpc3 2 2 3 3>;
149 gpios = <&gpc3 0 2 0 3>, <&gpc3 1 2 0 3>,
150 <&gpc3 3 2 3 3>, <&gpc3 4 2 3 3>,
151 <&gpc3 5 2 3 3>, <&gpc3 6 2 3 3>,
152 <&gpc4 3 3 3 3>, <&gpc4 3 3 3 3>,
153 <&gpc4 5 3 3 3>, <&gpc4 6 3 3 3>;
154 };
155 };
156
157 dwmmc3@12230000 {
158 status = "disabled";
159 };
160
161 spi_0: spi@12d20000 {
162 status = "disabled";
163 };
164
165 spi_1: spi@12d30000 {
166 gpios = <&gpa2 4 2 3 0>,
167 <&gpa2 6 2 3 0>,
168 <&gpa2 7 2 3 0>;
169
170 w25q80bw@0 {
171 #address-cells = <1>;
172 #size-cells = <1>;
173 compatible = "w25x80";
174 reg = <0>;
175 spi-max-frequency = <1000000>;
176
177 controller-data {
178 cs-gpio = <&gpa2 5 1 0 3>;
179 samsung,spi-feedback-delay = <0>;
180 };
181
182 partition@0 {
183 label = "U-Boot";
184 reg = <0x0 0x40000>;
185 read-only;
186 };
187
188 partition@40000 {
189 label = "Kernel";
190 reg = <0x40000 0xc0000>;
191 };
192 };
193 };
194
195 spi_2: spi@12d40000 {
196 status = "disabled";
197 };
198
199 hdmi {
200 hpd-gpio = <&gpx3 7 0xf 1 3>;
201 };
202
203 codec@11000000 {
204 samsung,mfc-r = <0x43000000 0x800000>;
205 samsung,mfc-l = <0x51000000 0x800000>;
206 };
207};
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
deleted file mode 100644
index 17dd951c1cd..00000000000
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ /dev/null
@@ -1,43 +0,0 @@
1/*
2 * Google Snow board device tree source
3 *
4 * Copyright (c) 2012 Google, Inc
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11/dts-v1/;
12/include/ "exynos5250.dtsi"
13/include/ "cros5250-common.dtsi"
14
15/ {
16 model = "Google Snow";
17 compatible = "google,snow", "samsung,exynos5250";
18
19 gpio-keys {
20 compatible = "gpio-keys";
21
22 lid-switch {
23 label = "Lid";
24 gpios = <&gpx3 5 0 0x10000 0>;
25 linux,input-type = <5>; /* EV_SW */
26 linux,code = <0>; /* SW_LID */
27 debounce-interval = <1>;
28 gpio-key,wakeup;
29 };
30 };
31
32 /*
33 * On Snow we've got SIP WiFi and so can keep drive strengths low to
34 * reduce EMI.
35 */
36 dwmmc3@12230000 {
37 slot@0 {
38 gpios = <&gpc4 0 2 0 0>, <&gpc4 1 2 3 0>,
39 <&gpc4 3 2 3 0>, <&gpc4 4 2 3 0>,
40 <&gpc4 5 2 3 0>, <&gpc4 6 2 3 0>;
41 };
42 };
43};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
deleted file mode 100644
index 3acf594ea60..00000000000
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ /dev/null
@@ -1,586 +0,0 @@
1/*
2 * SAMSUNG EXYNOS5250 SoC device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
8 * EXYNOS5250 based board files can include this file and provide
9 * values for board specfic bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
13 * additional nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18*/
19
20/include/ "skeleton.dtsi"
21
22/ {
23 compatible = "samsung,exynos5250";
24 interrupt-parent = <&gic>;
25
26 aliases {
27 spi0 = &spi_0;
28 spi1 = &spi_1;
29 spi2 = &spi_2;
30 gsc0 = &gsc_0;
31 gsc1 = &gsc_1;
32 gsc2 = &gsc_2;
33 gsc3 = &gsc_3;
34 mshc0 = &dwmmc_0;
35 mshc1 = &dwmmc_1;
36 mshc2 = &dwmmc_2;
37 mshc3 = &dwmmc_3;
38 i2c0 = &i2c_0;
39 i2c1 = &i2c_1;
40 i2c2 = &i2c_2;
41 i2c3 = &i2c_3;
42 i2c4 = &i2c_4;
43 i2c5 = &i2c_5;
44 i2c6 = &i2c_6;
45 i2c7 = &i2c_7;
46 i2c8 = &i2c_8;
47 };
48
49 gic:interrupt-controller@10481000 {
50 compatible = "arm,cortex-a9-gic";
51 #interrupt-cells = <3>;
52 interrupt-controller;
53 reg = <0x10481000 0x1000>, <0x10482000 0x2000>;
54 };
55
56 combiner:interrupt-controller@10440000 {
57 compatible = "samsung,exynos4210-combiner";
58 #interrupt-cells = <2>;
59 interrupt-controller;
60 samsung,combiner-nr = <32>;
61 reg = <0x10440000 0x1000>;
62 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
63 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
64 <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
65 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
66 <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
67 <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
68 <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
69 <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
70 };
71
72 watchdog {
73 compatible = "samsung,s3c2410-wdt";
74 reg = <0x101D0000 0x100>;
75 interrupts = <0 42 0>;
76 };
77
78 codec@11000000 {
79 compatible = "samsung,mfc-v6";
80 reg = <0x11000000 0x10000>;
81 interrupts = <0 96 0>;
82 };
83
84 rtc {
85 compatible = "samsung,s3c6410-rtc";
86 reg = <0x101E0000 0x100>;
87 interrupts = <0 43 0>, <0 44 0>;
88 };
89
90 tmu@10060000 {
91 compatible = "samsung,exynos5250-tmu";
92 reg = <0x10060000 0x100>;
93 interrupts = <0 65 0>;
94 };
95
96 serial@12C00000 {
97 compatible = "samsung,exynos4210-uart";
98 reg = <0x12C00000 0x100>;
99 interrupts = <0 51 0>;
100 };
101
102 serial@12C10000 {
103 compatible = "samsung,exynos4210-uart";
104 reg = <0x12C10000 0x100>;
105 interrupts = <0 52 0>;
106 };
107
108 serial@12C20000 {
109 compatible = "samsung,exynos4210-uart";
110 reg = <0x12C20000 0x100>;
111 interrupts = <0 53 0>;
112 };
113
114 serial@12C30000 {
115 compatible = "samsung,exynos4210-uart";
116 reg = <0x12C30000 0x100>;
117 interrupts = <0 54 0>;
118 };
119
120 sata@122F0000 {
121 compatible = "samsung,exynos5-sata-ahci";
122 reg = <0x122F0000 0x1ff>;
123 interrupts = <0 115 0>;
124 };
125
126 sata-phy@12170000 {
127 compatible = "samsung,exynos5-sata-phy";
128 reg = <0x12170000 0x1ff>;
129 };
130
131 i2c_0: i2c@12C60000 {
132 compatible = "samsung,s3c2440-i2c";
133 reg = <0x12C60000 0x100>;
134 interrupts = <0 56 0>;
135 #address-cells = <1>;
136 #size-cells = <0>;
137 };
138
139 i2c_1: i2c@12C70000 {
140 compatible = "samsung,s3c2440-i2c";
141 reg = <0x12C70000 0x100>;
142 interrupts = <0 57 0>;
143 #address-cells = <1>;
144 #size-cells = <0>;
145 };
146
147 i2c_2: i2c@12C80000 {
148 compatible = "samsung,s3c2440-i2c";
149 reg = <0x12C80000 0x100>;
150 interrupts = <0 58 0>;
151 #address-cells = <1>;
152 #size-cells = <0>;
153 };
154
155 i2c_3: i2c@12C90000 {
156 compatible = "samsung,s3c2440-i2c";
157 reg = <0x12C90000 0x100>;
158 interrupts = <0 59 0>;
159 #address-cells = <1>;
160 #size-cells = <0>;
161 };
162
163 i2c_4: i2c@12CA0000 {
164 compatible = "samsung,s3c2440-i2c";
165 reg = <0x12CA0000 0x100>;
166 interrupts = <0 60 0>;
167 #address-cells = <1>;
168 #size-cells = <0>;
169 };
170
171 i2c_5: i2c@12CB0000 {
172 compatible = "samsung,s3c2440-i2c";
173 reg = <0x12CB0000 0x100>;
174 interrupts = <0 61 0>;
175 #address-cells = <1>;
176 #size-cells = <0>;
177 };
178
179 i2c_6: i2c@12CC0000 {
180 compatible = "samsung,s3c2440-i2c";
181 reg = <0x12CC0000 0x100>;
182 interrupts = <0 62 0>;
183 #address-cells = <1>;
184 #size-cells = <0>;
185 };
186
187 i2c_7: i2c@12CD0000 {
188 compatible = "samsung,s3c2440-i2c";
189 reg = <0x12CD0000 0x100>;
190 interrupts = <0 63 0>;
191 #address-cells = <1>;
192 #size-cells = <0>;
193 };
194
195 i2c_8: i2c@12CE0000 {
196 compatible = "samsung,s3c2440-hdmiphy-i2c";
197 reg = <0x12CE0000 0x1000>;
198 interrupts = <0 64 0>;
199 #address-cells = <1>;
200 #size-cells = <0>;
201 };
202
203 i2c@121D0000 {
204 compatible = "samsung,exynos5-sata-phy-i2c";
205 reg = <0x121D0000 0x100>;
206 #address-cells = <1>;
207 #size-cells = <0>;
208 };
209
210 spi_0: spi@12d20000 {
211 compatible = "samsung,exynos4210-spi";
212 reg = <0x12d20000 0x100>;
213 interrupts = <0 66 0>;
214 tx-dma-channel = <&pdma0 5>; /* preliminary */
215 rx-dma-channel = <&pdma0 4>; /* preliminary */
216 #address-cells = <1>;
217 #size-cells = <0>;
218 };
219
220 spi_1: spi@12d30000 {
221 compatible = "samsung,exynos4210-spi";
222 reg = <0x12d30000 0x100>;
223 interrupts = <0 67 0>;
224 tx-dma-channel = <&pdma1 5>; /* preliminary */
225 rx-dma-channel = <&pdma1 4>; /* preliminary */
226 #address-cells = <1>;
227 #size-cells = <0>;
228 };
229
230 spi_2: spi@12d40000 {
231 compatible = "samsung,exynos4210-spi";
232 reg = <0x12d40000 0x100>;
233 interrupts = <0 68 0>;
234 tx-dma-channel = <&pdma0 7>; /* preliminary */
235 rx-dma-channel = <&pdma0 6>; /* preliminary */
236 #address-cells = <1>;
237 #size-cells = <0>;
238 };
239
240 dwmmc_0: dwmmc0@12200000 {
241 compatible = "samsung,exynos5250-dw-mshc";
242 reg = <0x12200000 0x1000>;
243 interrupts = <0 75 0>;
244 #address-cells = <1>;
245 #size-cells = <0>;
246 };
247
248 dwmmc_1: dwmmc1@12210000 {
249 compatible = "samsung,exynos5250-dw-mshc";
250 reg = <0x12210000 0x1000>;
251 interrupts = <0 76 0>;
252 #address-cells = <1>;
253 #size-cells = <0>;
254 };
255
256 dwmmc_2: dwmmc2@12220000 {
257 compatible = "samsung,exynos5250-dw-mshc";
258 reg = <0x12220000 0x1000>;
259 interrupts = <0 77 0>;
260 #address-cells = <1>;
261 #size-cells = <0>;
262 };
263
264 dwmmc_3: dwmmc3@12230000 {
265 compatible = "samsung,exynos5250-dw-mshc";
266 reg = <0x12230000 0x1000>;
267 interrupts = <0 78 0>;
268 #address-cells = <1>;
269 #size-cells = <0>;
270 };
271
272 amba {
273 #address-cells = <1>;
274 #size-cells = <1>;
275 compatible = "arm,amba-bus";
276 interrupt-parent = <&gic>;
277 ranges;
278
279 pdma0: pdma@121A0000 {
280 compatible = "arm,pl330", "arm,primecell";
281 reg = <0x121A0000 0x1000>;
282 interrupts = <0 34 0>;
283 };
284
285 pdma1: pdma@121B0000 {
286 compatible = "arm,pl330", "arm,primecell";
287 reg = <0x121B0000 0x1000>;
288 interrupts = <0 35 0>;
289 };
290
291 mdma0: mdma@10800000 {
292 compatible = "arm,pl330", "arm,primecell";
293 reg = <0x10800000 0x1000>;
294 interrupts = <0 33 0>;
295 };
296
297 mdma1: mdma@11C10000 {
298 compatible = "arm,pl330", "arm,primecell";
299 reg = <0x11C10000 0x1000>;
300 interrupts = <0 124 0>;
301 };
302 };
303
304 gpio-controllers {
305 #address-cells = <1>;
306 #size-cells = <1>;
307 gpio-controller;
308 ranges;
309
310 gpa0: gpio-controller@11400000 {
311 compatible = "samsung,exynos4-gpio";
312 reg = <0x11400000 0x20>;
313 #gpio-cells = <4>;
314 };
315
316 gpa1: gpio-controller@11400020 {
317 compatible = "samsung,exynos4-gpio";
318 reg = <0x11400020 0x20>;
319 #gpio-cells = <4>;
320 };
321
322 gpa2: gpio-controller@11400040 {
323 compatible = "samsung,exynos4-gpio";
324 reg = <0x11400040 0x20>;
325 #gpio-cells = <4>;
326 };
327
328 gpb0: gpio-controller@11400060 {
329 compatible = "samsung,exynos4-gpio";
330 reg = <0x11400060 0x20>;
331 #gpio-cells = <4>;
332 };
333
334 gpb1: gpio-controller@11400080 {
335 compatible = "samsung,exynos4-gpio";
336 reg = <0x11400080 0x20>;
337 #gpio-cells = <4>;
338 };
339
340 gpb2: gpio-controller@114000A0 {
341 compatible = "samsung,exynos4-gpio";
342 reg = <0x114000A0 0x20>;
343 #gpio-cells = <4>;
344 };
345
346 gpb3: gpio-controller@114000C0 {
347 compatible = "samsung,exynos4-gpio";
348 reg = <0x114000C0 0x20>;
349 #gpio-cells = <4>;
350 };
351
352 gpc0: gpio-controller@114000E0 {
353 compatible = "samsung,exynos4-gpio";
354 reg = <0x114000E0 0x20>;
355 #gpio-cells = <4>;
356 };
357
358 gpc1: gpio-controller@11400100 {
359 compatible = "samsung,exynos4-gpio";
360 reg = <0x11400100 0x20>;
361 #gpio-cells = <4>;
362 };
363
364 gpc2: gpio-controller@11400120 {
365 compatible = "samsung,exynos4-gpio";
366 reg = <0x11400120 0x20>;
367 #gpio-cells = <4>;
368 };
369
370 gpc3: gpio-controller@11400140 {
371 compatible = "samsung,exynos4-gpio";
372 reg = <0x11400140 0x20>;
373 #gpio-cells = <4>;
374 };
375
376 gpc4: gpio-controller@114002E0 {
377 compatible = "samsung,exynos4-gpio";
378 reg = <0x114002E0 0x20>;
379 #gpio-cells = <4>;
380 };
381
382 gpd0: gpio-controller@11400160 {
383 compatible = "samsung,exynos4-gpio";
384 reg = <0x11400160 0x20>;
385 #gpio-cells = <4>;
386 };
387
388 gpd1: gpio-controller@11400180 {
389 compatible = "samsung,exynos4-gpio";
390 reg = <0x11400180 0x20>;
391 #gpio-cells = <4>;
392 };
393
394 gpy0: gpio-controller@114001A0 {
395 compatible = "samsung,exynos4-gpio";
396 reg = <0x114001A0 0x20>;
397 #gpio-cells = <4>;
398 };
399
400 gpy1: gpio-controller@114001C0 {
401 compatible = "samsung,exynos4-gpio";
402 reg = <0x114001C0 0x20>;
403 #gpio-cells = <4>;
404 };
405
406 gpy2: gpio-controller@114001E0 {
407 compatible = "samsung,exynos4-gpio";
408 reg = <0x114001E0 0x20>;
409 #gpio-cells = <4>;
410 };
411
412 gpy3: gpio-controller@11400200 {
413 compatible = "samsung,exynos4-gpio";
414 reg = <0x11400200 0x20>;
415 #gpio-cells = <4>;
416 };
417
418 gpy4: gpio-controller@11400220 {
419 compatible = "samsung,exynos4-gpio";
420 reg = <0x11400220 0x20>;
421 #gpio-cells = <4>;
422 };
423
424 gpy5: gpio-controller@11400240 {
425 compatible = "samsung,exynos4-gpio";
426 reg = <0x11400240 0x20>;
427 #gpio-cells = <4>;
428 };
429
430 gpy6: gpio-controller@11400260 {
431 compatible = "samsung,exynos4-gpio";
432 reg = <0x11400260 0x20>;
433 #gpio-cells = <4>;
434 };
435
436 gpx0: gpio-controller@11400C00 {
437 compatible = "samsung,exynos4-gpio";
438 reg = <0x11400C00 0x20>;
439 #gpio-cells = <4>;
440 };
441
442 gpx1: gpio-controller@11400C20 {
443 compatible = "samsung,exynos4-gpio";
444 reg = <0x11400C20 0x20>;
445 #gpio-cells = <4>;
446 };
447
448 gpx2: gpio-controller@11400C40 {
449 compatible = "samsung,exynos4-gpio";
450 reg = <0x11400C40 0x20>;
451 #gpio-cells = <4>;
452 };
453
454 gpx3: gpio-controller@11400C60 {
455 compatible = "samsung,exynos4-gpio";
456 reg = <0x11400C60 0x20>;
457 #gpio-cells = <4>;
458 };
459
460 gpe0: gpio-controller@13400000 {
461 compatible = "samsung,exynos4-gpio";
462 reg = <0x13400000 0x20>;
463 #gpio-cells = <4>;
464 };
465
466 gpe1: gpio-controller@13400020 {
467 compatible = "samsung,exynos4-gpio";
468 reg = <0x13400020 0x20>;
469 #gpio-cells = <4>;
470 };
471
472 gpf0: gpio-controller@13400040 {
473 compatible = "samsung,exynos4-gpio";
474 reg = <0x13400040 0x20>;
475 #gpio-cells = <4>;
476 };
477
478 gpf1: gpio-controller@13400060 {
479 compatible = "samsung,exynos4-gpio";
480 reg = <0x13400060 0x20>;
481 #gpio-cells = <4>;
482 };
483
484 gpg0: gpio-controller@13400080 {
485 compatible = "samsung,exynos4-gpio";
486 reg = <0x13400080 0x20>;
487 #gpio-cells = <4>;
488 };
489
490 gpg1: gpio-controller@134000A0 {
491 compatible = "samsung,exynos4-gpio";
492 reg = <0x134000A0 0x20>;
493 #gpio-cells = <4>;
494 };
495
496 gpg2: gpio-controller@134000C0 {
497 compatible = "samsung,exynos4-gpio";
498 reg = <0x134000C0 0x20>;
499 #gpio-cells = <4>;
500 };
501
502 gph0: gpio-controller@134000E0 {
503 compatible = "samsung,exynos4-gpio";
504 reg = <0x134000E0 0x20>;
505 #gpio-cells = <4>;
506 };
507
508 gph1: gpio-controller@13400100 {
509 compatible = "samsung,exynos4-gpio";
510 reg = <0x13400100 0x20>;
511 #gpio-cells = <4>;
512 };
513
514 gpv0: gpio-controller@10D10000 {
515 compatible = "samsung,exynos4-gpio";
516 reg = <0x10D10000 0x20>;
517 #gpio-cells = <4>;
518 };
519
520 gpv1: gpio-controller@10D10020 {
521 compatible = "samsung,exynos4-gpio";
522 reg = <0x10D10020 0x20>;
523 #gpio-cells = <4>;
524 };
525
526 gpv2: gpio-controller@10D10040 {
527 compatible = "samsung,exynos4-gpio";
528 reg = <0x10D10060 0x20>;
529 #gpio-cells = <4>;
530 };
531
532 gpv3: gpio-controller@10D10060 {
533 compatible = "samsung,exynos4-gpio";
534 reg = <0x10D10080 0x20>;
535 #gpio-cells = <4>;
536 };
537
538 gpv4: gpio-controller@10D10080 {
539 compatible = "samsung,exynos4-gpio";
540 reg = <0x10D100C0 0x20>;
541 #gpio-cells = <4>;
542 };
543
544 gpz: gpio-controller@03860000 {
545 compatible = "samsung,exynos4-gpio";
546 reg = <0x03860000 0x20>;
547 #gpio-cells = <4>;
548 };
549 };
550
551 gsc_0: gsc@0x13e00000 {
552 compatible = "samsung,exynos5-gsc";
553 reg = <0x13e00000 0x1000>;
554 interrupts = <0 85 0>;
555 };
556
557 gsc_1: gsc@0x13e10000 {
558 compatible = "samsung,exynos5-gsc";
559 reg = <0x13e10000 0x1000>;
560 interrupts = <0 86 0>;
561 };
562
563 gsc_2: gsc@0x13e20000 {
564 compatible = "samsung,exynos5-gsc";
565 reg = <0x13e20000 0x1000>;
566 interrupts = <0 87 0>;
567 };
568
569 gsc_3: gsc@0x13e30000 {
570 compatible = "samsung,exynos5-gsc";
571 reg = <0x13e30000 0x1000>;
572 interrupts = <0 88 0>;
573 };
574
575 hdmi {
576 compatible = "samsung,exynos5-hdmi";
577 reg = <0x14530000 0x70000>;
578 interrupts = <0 95 0>;
579 };
580
581 mixer {
582 compatible = "samsung,exynos5-mixer";
583 reg = <0x14450000 0x10000>;
584 interrupts = <0 94 0>;
585 };
586};
diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
deleted file mode 100644
index 81e2c964a90..00000000000
--- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts
+++ /dev/null
@@ -1,46 +0,0 @@
1/*
2 * SAMSUNG SSDK5440 board device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12/dts-v1/;
13/include/ "exynos5440.dtsi"
14
15/ {
16 model = "SAMSUNG SSDK5440 board based on EXYNOS5440";
17 compatible = "samsung,ssdk5440", "samsung,exynos5440";
18
19 memory {
20 reg = <0x80000000 0x80000000>;
21 };
22
23 chosen {
24 bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x81000000,8M console=ttySAC0,115200 init=/linuxrc";
25 };
26
27 spi {
28 status = "disabled";
29 };
30
31 i2c@F0000 {
32 status = "disabled";
33 };
34
35 i2c@100000 {
36 status = "disabled";
37 };
38
39 watchdog {
40 status = "disabled";
41 };
42
43 rtc {
44 status = "disabled";
45 };
46};
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
deleted file mode 100644
index 024269de8ee..00000000000
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ /dev/null
@@ -1,159 +0,0 @@
1/*
2 * SAMSUNG EXYNOS5440 SoC device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12/include/ "skeleton.dtsi"
13
14/ {
15 compatible = "samsung,exynos5440";
16
17 interrupt-parent = <&gic>;
18
19 gic:interrupt-controller@2E0000 {
20 compatible = "arm,cortex-a15-gic";
21 #interrupt-cells = <3>;
22 interrupt-controller;
23 reg = <0x2E1000 0x1000>, <0x2E2000 0x1000>;
24 };
25
26 cpus {
27 cpu@0 {
28 compatible = "arm,cortex-a15";
29 timer {
30 compatible = "arm,armv7-timer";
31 interrupts = <1 13 0xf08>;
32 clock-frequency = <1000000>;
33 };
34 };
35 cpu@1 {
36 compatible = "arm,cortex-a15";
37 timer {
38 compatible = "arm,armv7-timer";
39 interrupts = <1 14 0xf08>;
40 clock-frequency = <1000000>;
41 };
42 };
43 cpu@2 {
44 compatible = "arm,cortex-a15";
45 timer {
46 compatible = "arm,armv7-timer";
47 interrupts = <1 14 0xf08>;
48 clock-frequency = <1000000>;
49 };
50 };
51 cpu@3 {
52 compatible = "arm,cortex-a15";
53 timer {
54 compatible = "arm,armv7-timer";
55 interrupts = <1 14 0xf08>;
56 clock-frequency = <1000000>;
57 };
58 };
59 };
60
61 common {
62 compatible = "samsung,exynos5440";
63
64 };
65
66 serial@B0000 {
67 compatible = "samsung,exynos4210-uart";
68 reg = <0xB0000 0x1000>;
69 interrupts = <0 2 0>;
70 };
71
72 serial@C0000 {
73 compatible = "samsung,exynos4210-uart";
74 reg = <0xC0000 0x1000>;
75 interrupts = <0 3 0>;
76 };
77
78 spi {
79 compatible = "samsung,exynos4210-spi";
80 reg = <0xD0000 0x1000>;
81 interrupts = <0 4 0>;
82 tx-dma-channel = <&pdma0 5>; /* preliminary */
83 rx-dma-channel = <&pdma0 4>; /* preliminary */
84 #address-cells = <1>;
85 #size-cells = <0>;
86 };
87
88 pinctrl {
89 compatible = "samsung,pinctrl-exynos5440";
90 reg = <0xE0000 0x1000>;
91 interrupt-controller;
92 #interrupt-cells = <2>;
93 #gpio-cells = <2>;
94
95 fan: fan {
96 samsung,exynos5440-pin-function = <1>;
97 };
98
99 hdd_led0: hdd_led0 {
100 samsung,exynos5440-pin-function = <2>;
101 };
102
103 hdd_led1: hdd_led1 {
104 samsung,exynos5440-pin-function = <3>;
105 };
106
107 uart1: uart1 {
108 samsung,exynos5440-pin-function = <4>;
109 };
110 };
111
112 i2c@F0000 {
113 compatible = "samsung,s3c2440-i2c";
114 reg = <0xF0000 0x1000>;
115 interrupts = <0 5 0>;
116 #address-cells = <1>;
117 #size-cells = <0>;
118 };
119
120 i2c@100000 {
121 compatible = "samsung,s3c2440-i2c";
122 reg = <0x100000 0x1000>;
123 interrupts = <0 6 0>;
124 #address-cells = <1>;
125 #size-cells = <0>;
126 };
127
128 watchdog {
129 compatible = "samsung,s3c2410-wdt";
130 reg = <0x110000 0x1000>;
131 interrupts = <0 1 0>;
132 };
133
134 amba {
135 #address-cells = <1>;
136 #size-cells = <1>;
137 compatible = "arm,amba-bus";
138 interrupt-parent = <&gic>;
139 ranges;
140
141 pdma0: pdma@121A0000 {
142 compatible = "arm,pl330", "arm,primecell";
143 reg = <0x120000 0x1000>;
144 interrupts = <0 34 0>;
145 };
146
147 pdma1: pdma@121B0000 {
148 compatible = "arm,pl330", "arm,primecell";
149 reg = <0x121000 0x1000>;
150 interrupts = <0 35 0>;
151 };
152 };
153
154 rtc {
155 compatible = "samsung,s3c6410-rtc";
156 reg = <0x130000 0x1000>;
157 interrupts = <0 16 0>, <0 17 0>;
158 };
159};
diff --git a/arch/arm/boot/dts/ge863-pro3.dtsi b/arch/arm/boot/dts/ge863-pro3.dtsi
deleted file mode 100644
index 17136fc7a51..00000000000
--- a/arch/arm/boot/dts/ge863-pro3.dtsi
+++ /dev/null
@@ -1,52 +0,0 @@
1/*
2 * ge863_pro3.dtsi - Device Tree file for Telit GE863-PRO3
3 *
4 * Copyright (C) 2012 Telit,
5 * 2012 Fabio Porcedda <fabio.porcedda@gmail.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9
10/include/ "at91sam9260.dtsi"
11
12/ {
13 clocks {
14 #address-cells = <1>;
15 #size-cells = <1>;
16 ranges;
17
18 main_clock: clock@0 {
19 compatible = "atmel,osc", "fixed-clock";
20 clock-frequency = <6000000>;
21 };
22 };
23
24 ahb {
25 apb {
26 dbgu: serial@fffff200 {
27 status = "okay";
28 };
29 };
30
31 nand0: nand@40000000 {
32 nand-bus-width = <8>;
33 nand-ecc-mode = "soft";
34 nand-on-flash-bbt;
35 status = "okay";
36
37 boot@0 {
38 label = "boot";
39 reg = <0x0 0x7c0000>;
40 };
41
42 root@07c0000 {
43 label = "root";
44 reg = <0x7c0000 0x7840000>;
45 };
46 };
47 };
48
49 chosen {
50 bootargs = "console=ttyS0,115200 root=ubi0:rootfs ubi.mtd=1 rootfstype=ubifs";
51 };
52};
diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts
deleted file mode 100644
index 5927a8df562..00000000000
--- a/arch/arm/boot/dts/highbank.dts
+++ /dev/null
@@ -1,126 +0,0 @@
1/*
2 * Copyright 2011-2012 Calxeda, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17/dts-v1/;
18
19/* First 4KB has pen for secondary cores. */
20/memreserve/ 0x00000000 0x0001000;
21
22/ {
23 model = "Calxeda Highbank";
24 compatible = "calxeda,highbank";
25 #address-cells = <1>;
26 #size-cells = <1>;
27 clock-ranges;
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 cpu@900 {
34 compatible = "arm,cortex-a9";
35 device_type = "cpu";
36 reg = <0x900>;
37 next-level-cache = <&L2>;
38 clocks = <&a9pll>;
39 clock-names = "cpu";
40 };
41
42 cpu@901 {
43 compatible = "arm,cortex-a9";
44 device_type = "cpu";
45 reg = <0x901>;
46 next-level-cache = <&L2>;
47 clocks = <&a9pll>;
48 clock-names = "cpu";
49 };
50
51 cpu@902 {
52 compatible = "arm,cortex-a9";
53 device_type = "cpu";
54 reg = <0x902>;
55 next-level-cache = <&L2>;
56 clocks = <&a9pll>;
57 clock-names = "cpu";
58 };
59
60 cpu@903 {
61 compatible = "arm,cortex-a9";
62 device_type = "cpu";
63 reg = <0x903>;
64 next-level-cache = <&L2>;
65 clocks = <&a9pll>;
66 clock-names = "cpu";
67 };
68 };
69
70 memory {
71 name = "memory";
72 device_type = "memory";
73 reg = <0x00000000 0xff900000>;
74 };
75
76 soc {
77 ranges = <0x00000000 0x00000000 0xffffffff>;
78
79 timer@fff10600 {
80 compatible = "arm,cortex-a9-twd-timer";
81 reg = <0xfff10600 0x20>;
82 interrupts = <1 13 0xf01>;
83 clocks = <&a9periphclk>;
84 };
85
86 watchdog@fff10620 {
87 compatible = "arm,cortex-a9-twd-wdt";
88 reg = <0xfff10620 0x20>;
89 interrupts = <1 14 0xf01>;
90 clocks = <&a9periphclk>;
91 };
92
93 intc: interrupt-controller@fff11000 {
94 compatible = "arm,cortex-a9-gic";
95 #interrupt-cells = <3>;
96 #size-cells = <0>;
97 #address-cells = <1>;
98 interrupt-controller;
99 reg = <0xfff11000 0x1000>,
100 <0xfff10100 0x100>;
101 };
102
103 L2: l2-cache {
104 compatible = "arm,pl310-cache";
105 reg = <0xfff12000 0x1000>;
106 interrupts = <0 70 4>;
107 cache-unified;
108 cache-level = <2>;
109 };
110
111 pmu {
112 compatible = "arm,cortex-a9-pmu";
113 interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>;
114 };
115
116
117 sregs@fff3c200 {
118 compatible = "calxeda,hb-sregs-l2-ecc";
119 reg = <0xfff3c200 0x100>;
120 interrupts = <0 71 4 0 72 4>;
121 };
122
123 };
124};
125
126/include/ "ecx-common.dtsi"
diff --git a/arch/arm/boot/dts/href.dtsi b/arch/arm/boot/dts/href.dtsi
deleted file mode 100644
index 592fb9dc35b..00000000000
--- a/arch/arm/boot/dts/href.dtsi
+++ /dev/null
@@ -1,273 +0,0 @@
1/*
2 * Copyright 2012 ST-Ericsson AB
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/include/ "dbx5x0.dtsi"
13
14/ {
15 memory {
16 reg = <0x00000000 0x20000000>;
17 };
18
19 gpio_keys {
20 compatible = "gpio-keys";
21 #address-cells = <1>;
22 #size-cells = <0>;
23
24 button@1 {
25 linux,code = <11>;
26 label = "SFH7741 Proximity Sensor";
27 };
28 };
29
30 soc-u9500 {
31 uart@80120000 {
32 status = "okay";
33 };
34
35 uart@80121000 {
36 status = "okay";
37 };
38
39 uart@80007000 {
40 status = "okay";
41 };
42
43 i2c@80004000 {
44 tc3589x@42 {
45 compatible = "tc3589x";
46 reg = <0x42>;
47 interrupt-parent = <&gpio6>;
48 interrupts = <25 0x1>;
49
50 interrupt-controller;
51 #interrupt-cells = <2>;
52
53 tc3589x_gpio: tc3589x_gpio {
54 compatible = "tc3589x-gpio";
55 interrupts = <0 0x1>;
56
57 interrupt-controller;
58 #interrupt-cells = <2>;
59 gpio-controller;
60 #gpio-cells = <2>;
61 };
62 };
63 };
64
65 i2c@80128000 {
66 lp5521@0x33 {
67 compatible = "lp5521";
68 reg = <0x33>;
69 };
70
71 lp5521@0x34 {
72 compatible = "lp5521";
73 reg = <0x34>;
74 };
75
76 bh1780@0x29 {
77 compatible = "rohm,bh1780gli";
78 reg = <0x33>;
79 };
80 };
81
82 // External Micro SD slot
83 sdi0_per1@80126000 {
84 arm,primecell-periphid = <0x10480180>;
85 max-frequency = <50000000>;
86 bus-width = <4>;
87 mmc-cap-sd-highspeed;
88 mmc-cap-mmc-highspeed;
89 vmmc-supply = <&ab8500_ldo_aux3_reg>;
90
91 cd-gpios = <&tc3589x_gpio 3 0x4>;
92
93 status = "okay";
94 };
95
96 // WLAN SDIO channel
97 sdi1_per2@80118000 {
98 arm,primecell-periphid = <0x10480180>;
99 max-frequency = <50000000>;
100 bus-width = <4>;
101
102 status = "okay";
103 };
104
105 // PoP:ed eMMC
106 sdi2_per3@80005000 {
107 arm,primecell-periphid = <0x10480180>;
108 max-frequency = <50000000>;
109 bus-width = <8>;
110 mmc-cap-mmc-highspeed;
111
112 status = "okay";
113 };
114
115 // On-board eMMC
116 sdi4_per2@80114000 {
117 arm,primecell-periphid = <0x10480180>;
118 max-frequency = <50000000>;
119 bus-width = <8>;
120 mmc-cap-mmc-highspeed;
121 vmmc-supply = <&ab8500_ldo_aux2_reg>;
122
123 status = "okay";
124 };
125
126 sound {
127 compatible = "stericsson,snd-soc-mop500";
128
129 stericsson,cpu-dai = <&msp1 &msp3>;
130 stericsson,audio-codec = <&codec>;
131 };
132
133 msp1: msp@80124000 {
134 status = "okay";
135 };
136
137 msp3: msp@80125000 {
138 status = "okay";
139 };
140
141 prcmu@80157000 {
142 db8500-prcmu-regulators {
143 db8500_vape_reg: db8500_vape {
144 regulator-name = "db8500-vape";
145 };
146
147 db8500_varm_reg: db8500_varm {
148 regulator-name = "db8500-varm";
149 };
150
151 db8500_vmodem_reg: db8500_vmodem {
152 regulator-name = "db8500-vmodem";
153 };
154
155 db8500_vpll_reg: db8500_vpll {
156 regulator-name = "db8500-vpll";
157 };
158
159 db8500_vsmps1_reg: db8500_vsmps1 {
160 regulator-name = "db8500-vsmps1";
161 };
162
163 db8500_vsmps2_reg: db8500_vsmps2 {
164 regulator-name = "db8500-vsmps2";
165 };
166
167 db8500_vsmps3_reg: db8500_vsmps3 {
168 regulator-name = "db8500-vsmps3";
169 };
170
171 db8500_vrf1_reg: db8500_vrf1 {
172 regulator-name = "db8500-vrf1";
173 };
174
175 db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
176 regulator-name = "db8500-sva-mmdsp";
177 };
178
179 db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
180 regulator-name = "db8500-sva-mmdsp-ret";
181 };
182
183 db8500_sva_pipe_reg: db8500_sva_pipe {
184 regulator-name = "db8500_sva_pipe";
185 };
186
187 db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
188 regulator-name = "db8500_sia_mmdsp";
189 };
190
191 db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
192 regulator-name = "db8500-sia-mmdsp-ret";
193 };
194
195 db8500_sia_pipe_reg: db8500_sia_pipe {
196 regulator-name = "db8500-sia-pipe";
197 };
198
199 db8500_sga_reg: db8500_sga {
200 regulator-name = "db8500-sga";
201 };
202
203 db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
204 regulator-name = "db8500-b2r2-mcde";
205 };
206
207 db8500_esram12_reg: db8500_esram12 {
208 regulator-name = "db8500-esram12";
209 };
210
211 db8500_esram12_ret_reg: db8500_esram12_ret {
212 regulator-name = "db8500-esram12-ret";
213 };
214
215 db8500_esram34_reg: db8500_esram34 {
216 regulator-name = "db8500-esram34";
217 };
218
219 db8500_esram34_ret_reg: db8500_esram34_ret {
220 regulator-name = "db8500-esram34-ret";
221 };
222 };
223
224 ab8500@5 {
225 ab8500-regulators {
226 ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
227 regulator-name = "V-DISPLAY";
228 };
229
230 ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
231 regulator-name = "V-eMMC1";
232 };
233
234 ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
235 regulator-name = "V-MMC-SD";
236 };
237
238 ab8500_ldo_initcore_reg: ab8500_ldo_initcore {
239 regulator-name = "V-INTCORE";
240 };
241
242 ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
243 regulator-name = "V-TVOUT";
244 };
245
246 ab8500_ldo_usb_reg: ab8500_ldo_usb {
247 regulator-name = "dummy";
248 };
249
250 ab8500_ldo_audio_reg: ab8500_ldo_audio {
251 regulator-name = "V-AUD";
252 };
253
254 ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
255 regulator-name = "V-AMIC1";
256 };
257
258 ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
259 regulator-name = "V-AMIC2";
260 };
261
262 ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
263 regulator-name = "V-DMIC";
264 };
265
266 ab8500_ldo_ana_reg: ab8500_ldo_ana {
267 regulator-name = "V-CSI/DSI";
268 };
269 };
270 };
271 };
272 };
273};
diff --git a/arch/arm/boot/dts/hrefprev60.dts b/arch/arm/boot/dts/hrefprev60.dts
deleted file mode 100644
index eec29c4a86d..00000000000
--- a/arch/arm/boot/dts/hrefprev60.dts
+++ /dev/null
@@ -1,48 +0,0 @@
1/*
2 * Copyright 2012 ST-Ericsson AB
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "dbx5x0.dtsi"
14/include/ "href.dtsi"
15/include/ "stuib.dtsi"
16
17/ {
18 model = "ST-Ericsson HREF (pre-v60) platform with Device Tree";
19 compatible = "st-ericsson,mop500", "st-ericsson,u8500";
20
21 gpio_keys {
22 button@1 {
23 gpios = <&tc3589x_gpio 7 0x4>;
24 };
25 };
26
27 soc-u9500 {
28 i2c@80004000 {
29 tps61052@33 {
30 compatible = "tps61052";
31 reg = <0x33>;
32 };
33 };
34
35 i2c@80110000 {
36 bu21013_tp@0x5c {
37 reset-gpio = <&tc3589x_gpio 13 0x4>;
38 };
39 };
40
41 vmmci: regulator-gpio {
42 gpios = <&tc3589x_gpio 18 0x4>;
43 gpio-enable = <&tc3589x_gpio 17 0x4>;
44
45 status = "okay";
46 };
47 };
48};
diff --git a/arch/arm/boot/dts/hrefv60plus.dts b/arch/arm/boot/dts/hrefv60plus.dts
deleted file mode 100644
index 55f4191a626..00000000000
--- a/arch/arm/boot/dts/hrefv60plus.dts
+++ /dev/null
@@ -1,210 +0,0 @@
1/*
2 * Copyright 2012 ST-Ericsson AB
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "dbx5x0.dtsi"
14/include/ "href.dtsi"
15/include/ "stuib.dtsi"
16
17/ {
18 model = "ST-Ericsson HREF (v60+) platform with Device Tree";
19 compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500";
20
21 gpio_keys {
22 button@1 {
23 gpios = <&gpio6 25 0x4>;
24 };
25 };
26
27 soc-u9500 {
28 i2c@80110000 {
29 bu21013_tp@0x5c {
30 reset-gpio = <&gpio4 15 0x4>;
31 };
32 };
33
34 // External Micro SD slot
35 sdi0_per1@80126000 {
36 arm,primecell-periphid = <0x10480180>;
37 max-frequency = <50000000>;
38 bus-width = <4>;
39 mmc-cap-sd-highspeed;
40 mmc-cap-mmc-highspeed;
41 vmmc-supply = <&ab8500_ldo_aux3_reg>;
42
43 cd-gpios = <&tc3589x_gpio 3 0x4>;
44
45 status = "okay";
46 };
47
48 // WLAN SDIO channel
49 sdi1_per2@80118000 {
50 arm,primecell-periphid = <0x10480180>;
51 max-frequency = <50000000>;
52 bus-width = <4>;
53
54 status = "okay";
55 };
56
57 // PoP:ed eMMC
58 sdi2_per3@80005000 {
59 arm,primecell-periphid = <0x10480180>;
60 max-frequency = <50000000>;
61 bus-width = <8>;
62 mmc-cap-mmc-highspeed;
63
64 status = "okay";
65 };
66
67 // On-board eMMC
68 sdi4_per2@80114000 {
69 arm,primecell-periphid = <0x10480180>;
70 max-frequency = <50000000>;
71 bus-width = <8>;
72 mmc-cap-mmc-highspeed;
73 vmmc-supply = <&ab8500_ldo_aux2_reg>;
74
75 status = "okay";
76 };
77
78 prcmu@80157000 {
79 db8500-prcmu-regulators {
80 db8500_vape_reg: db8500_vape {
81 regulator-name = "db8500-vape";
82 };
83
84 db8500_varm_reg: db8500_varm {
85 regulator-name = "db8500-varm";
86 };
87
88 db8500_vmodem_reg: db8500_vmodem {
89 regulator-name = "db8500-vmodem";
90 };
91
92 db8500_vpll_reg: db8500_vpll {
93 regulator-name = "db8500-vpll";
94 };
95
96 db8500_vsmps1_reg: db8500_vsmps1 {
97 regulator-name = "db8500-vsmps1";
98 };
99
100 db8500_vsmps2_reg: db8500_vsmps2 {
101 regulator-name = "db8500-vsmps2";
102 };
103
104 db8500_vsmps3_reg: db8500_vsmps3 {
105 regulator-name = "db8500-vsmps3";
106 };
107
108 db8500_vrf1_reg: db8500_vrf1 {
109 regulator-name = "db8500-vrf1";
110 };
111
112 db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
113 regulator-name = "db8500-sva-mmdsp";
114 };
115
116 db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
117 regulator-name = "db8500-sva-mmdsp-ret";
118 };
119
120 db8500_sva_pipe_reg: db8500_sva_pipe {
121 regulator-name = "db8500_sva_pipe";
122 };
123
124 db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
125 regulator-name = "db8500_sia_mmdsp";
126 };
127
128 db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
129 regulator-name = "db8500-sia-mmdsp-ret";
130 };
131
132 db8500_sia_pipe_reg: db8500_sia_pipe {
133 regulator-name = "db8500-sia-pipe";
134 };
135
136 db8500_sga_reg: db8500_sga {
137 regulator-name = "db8500-sga";
138 };
139
140 db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
141 regulator-name = "db8500-b2r2-mcde";
142 };
143
144 db8500_esram12_reg: db8500_esram12 {
145 regulator-name = "db8500-esram12";
146 };
147
148 db8500_esram12_ret_reg: db8500_esram12_ret {
149 regulator-name = "db8500-esram12-ret";
150 };
151
152 db8500_esram34_reg: db8500_esram34 {
153 regulator-name = "db8500-esram34";
154 };
155
156 db8500_esram34_ret_reg: db8500_esram34_ret {
157 regulator-name = "db8500-esram34-ret";
158 };
159 };
160
161 ab8500@5 {
162 ab8500-regulators {
163 ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
164 regulator-name = "V-DISPLAY";
165 };
166
167 ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
168 regulator-name = "V-eMMC1";
169 };
170
171 ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
172 regulator-name = "V-MMC-SD";
173 };
174
175 ab8500_ldo_initcore_reg: ab8500_ldo_initcore {
176 regulator-name = "V-INTCORE";
177 };
178
179 ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
180 regulator-name = "V-TVOUT";
181 };
182
183 ab8500_ldo_usb_reg: ab8500_ldo_usb {
184 regulator-name = "dummy";
185 };
186
187 ab8500_ldo_audio_reg: ab8500_ldo_audio {
188 regulator-name = "V-AUD";
189 };
190
191 ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
192 regulator-name = "V-AMIC1";
193 };
194
195 ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
196 regulator-name = "V-AMIC2";
197 };
198
199 ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
200 regulator-name = "V-DMIC";
201 };
202
203 ab8500_ldo_ana_reg: ab8500_ldo_ana {
204 regulator-name = "V-CSI/DSI";
205 };
206 };
207 };
208 };
209 };
210};
diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts
deleted file mode 100644
index 035c13f9d3c..00000000000
--- a/arch/arm/boot/dts/imx23-evk.dts
+++ /dev/null
@@ -1,106 +0,0 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "imx23.dtsi"
14
15/ {
16 model = "Freescale i.MX23 Evaluation Kit";
17 compatible = "fsl,imx23-evk", "fsl,imx23";
18
19 memory {
20 reg = <0x40000000 0x08000000>;
21 };
22
23 apb@80000000 {
24 apbh@80000000 {
25 gpmi-nand@8000c000 {
26 pinctrl-names = "default";
27 pinctrl-0 = <&gpmi_pins_a &gpmi_pins_fixup>;
28 status = "okay";
29 };
30
31 ssp0: ssp@80010000 {
32 compatible = "fsl,imx23-mmc";
33 pinctrl-names = "default";
34 pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
35 bus-width = <4>;
36 wp-gpios = <&gpio1 30 0>;
37 vmmc-supply = <&reg_vddio_sd0>;
38 status = "okay";
39 };
40
41 pinctrl@80018000 {
42 pinctrl-names = "default";
43 pinctrl-0 = <&hog_pins_a>;
44
45 hog_pins_a: hog@0 {
46 reg = <0>;
47 fsl,pinmux-ids = <
48 0x1123 /* MX23_PAD_LCD_RESET__GPIO_1_18 */
49 0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */
50 0x11e3 /* MX23_PAD_PWM4__GPIO_1_30 */
51 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
52 >;
53 fsl,drive-strength = <0>;
54 fsl,voltage = <1>;
55 fsl,pull-up = <0>;
56 };
57 };
58
59 lcdif@80030000 {
60 pinctrl-names = "default";
61 pinctrl-0 = <&lcdif_24bit_pins_a>;
62 panel-enable-gpios = <&gpio1 18 0>;
63 status = "okay";
64 };
65 };
66
67 apbx@80040000 {
68 pwm: pwm@80064000 {
69 pinctrl-names = "default";
70 pinctrl-0 = <&pwm2_pins_a>;
71 status = "okay";
72 };
73
74 auart0: serial@8006c000 {
75 pinctrl-names = "default";
76 pinctrl-0 = <&auart0_pins_a>;
77 status = "okay";
78 };
79
80 duart: serial@80070000 {
81 pinctrl-names = "default";
82 pinctrl-0 = <&duart_pins_a>;
83 status = "okay";
84 };
85 };
86 };
87
88 regulators {
89 compatible = "simple-bus";
90
91 reg_vddio_sd0: vddio-sd0 {
92 compatible = "regulator-fixed";
93 regulator-name = "vddio-sd0";
94 regulator-min-microvolt = <3300000>;
95 regulator-max-microvolt = <3300000>;
96 gpio = <&gpio1 29 0>;
97 };
98 };
99
100 backlight {
101 compatible = "pwm-backlight";
102 pwms = <&pwm 2 5000000>;
103 brightness-levels = <0 4 8 16 32 64 128 255>;
104 default-brightness-level = <6>;
105 };
106};
diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts
deleted file mode 100644
index e7484e4ea65..00000000000
--- a/arch/arm/boot/dts/imx23-olinuxino.dts
+++ /dev/null
@@ -1,120 +0,0 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "imx23.dtsi"
16
17/ {
18 model = "i.MX23 Olinuxino Low Cost Board";
19 compatible = "olimex,imx23-olinuxino", "fsl,imx23";
20
21 memory {
22 reg = <0x40000000 0x04000000>;
23 };
24
25 apb@80000000 {
26 apbh@80000000 {
27 ssp0: ssp@80010000 {
28 compatible = "fsl,imx23-mmc";
29 pinctrl-names = "default";
30 pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
31 bus-width = <4>;
32 status = "okay";
33 };
34
35 pinctrl@80018000 {
36 pinctrl-names = "default";
37 pinctrl-0 = <&hog_pins_a>;
38
39 hog_pins_a: hog@0 {
40 reg = <0>;
41 fsl,pinmux-ids = <
42 0x0113 /* MX23_PAD_GPMI_ALE__GPIO_0_17 */
43 >;
44 fsl,drive-strength = <0>;
45 fsl,voltage = <1>;
46 fsl,pull-up = <0>;
47 };
48
49 led_pin_gpio2_1: led_gpio2_1@0 {
50 reg = <0>;
51 fsl,pinmux-ids = <
52 0x2013 /* MX23_PAD_SSP1_DETECT__GPIO_2_1 */
53 >;
54 fsl,drive-strength = <0>;
55 fsl,voltage = <1>;
56 fsl,pull-up = <0>;
57 };
58 };
59
60 ssp1: ssp@80034000 {
61 #address-cells = <1>;
62 #size-cells = <0>;
63 compatible = "fsl,imx23-spi";
64 pinctrl-names = "default";
65 pinctrl-0 = <&spi2_pins_a>;
66 status = "okay";
67 };
68 };
69
70 apbx@80040000 {
71 duart: serial@80070000 {
72 pinctrl-names = "default";
73 pinctrl-0 = <&duart_pins_a>;
74 status = "okay";
75 };
76
77 auart0: serial@8006c000 {
78 pinctrl-names = "default";
79 pinctrl-0 = <&auart0_2pins_a>;
80 status = "okay";
81 };
82
83 usbphy0: usbphy@8007c000 {
84 status = "okay";
85 };
86 };
87 };
88
89 ahb@80080000 {
90 usb0: usb@80080000 {
91 vbus-supply = <&reg_usb0_vbus>;
92 status = "okay";
93 };
94 };
95
96 regulators {
97 compatible = "simple-bus";
98
99 reg_usb0_vbus: usb0_vbus {
100 compatible = "regulator-fixed";
101 regulator-name = "usb0_vbus";
102 regulator-min-microvolt = <5000000>;
103 regulator-max-microvolt = <5000000>;
104 enable-active-high;
105 startup-delay-us = <300>; /* LAN9215 requires a POR of 200us minimum */
106 gpio = <&gpio0 17 0>;
107 };
108 };
109
110 leds {
111 compatible = "gpio-leds";
112 pinctrl-names = "default";
113 pinctrl-0 = <&led_pin_gpio2_1>;
114
115 user {
116 label = "green";
117 gpios = <&gpio2 1 1>;
118 };
119 };
120};
diff --git a/arch/arm/boot/dts/imx23-stmp378x_devb.dts b/arch/arm/boot/dts/imx23-stmp378x_devb.dts
deleted file mode 100644
index 85c3864b6a5..00000000000
--- a/arch/arm/boot/dts/imx23-stmp378x_devb.dts
+++ /dev/null
@@ -1,78 +0,0 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "imx23.dtsi"
14
15/ {
16 model = "Freescale STMP378x Development Board";
17 compatible = "fsl,stmp378x-devb", "fsl,imx23";
18
19 memory {
20 reg = <0x40000000 0x04000000>;
21 };
22
23 apb@80000000 {
24 apbh@80000000 {
25 ssp0: ssp@80010000 {
26 compatible = "fsl,imx23-mmc";
27 pinctrl-names = "default";
28 pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
29 bus-width = <4>;
30 wp-gpios = <&gpio1 30 0>;
31 vmmc-supply = <&reg_vddio_sd0>;
32 status = "okay";
33 };
34
35 pinctrl@80018000 {
36 pinctrl-names = "default";
37 pinctrl-0 = <&hog_pins_a>;
38
39 hog_pins_a: hog@0 {
40 reg = <0>;
41 fsl,pinmux-ids = <
42 0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */
43 0x11e3 /* MX23_PAD_PWM4__GPIO_1_30 */
44 >;
45 fsl,drive-strength = <0>;
46 fsl,voltage = <1>;
47 fsl,pull-up = <0>;
48 };
49 };
50 };
51
52 apbx@80040000 {
53 auart0: serial@8006c000 {
54 pinctrl-names = "default";
55 pinctrl-0 = <&auart0_pins_a>;
56 status = "okay";
57 };
58
59 duart: serial@80070000 {
60 pinctrl-names = "default";
61 pinctrl-0 = <&duart_pins_a>;
62 status = "okay";
63 };
64 };
65 };
66
67 regulators {
68 compatible = "simple-bus";
69
70 reg_vddio_sd0: vddio-sd0 {
71 compatible = "regulator-fixed";
72 regulator-name = "vddio-sd0";
73 regulator-min-microvolt = <3300000>;
74 regulator-max-microvolt = <3300000>;
75 gpio = <&gpio1 29 0>;
76 };
77 };
78};
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
deleted file mode 100644
index 65415c598a5..00000000000
--- a/arch/arm/boot/dts/imx23.dtsi
+++ /dev/null
@@ -1,479 +0,0 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 interrupt-parent = <&icoll>;
16
17 aliases {
18 gpio0 = &gpio0;
19 gpio1 = &gpio1;
20 gpio2 = &gpio2;
21 serial0 = &auart0;
22 serial1 = &auart1;
23 };
24
25 cpus {
26 cpu@0 {
27 compatible = "arm,arm926ejs";
28 };
29 };
30
31 apb@80000000 {
32 compatible = "simple-bus";
33 #address-cells = <1>;
34 #size-cells = <1>;
35 reg = <0x80000000 0x80000>;
36 ranges;
37
38 apbh@80000000 {
39 compatible = "simple-bus";
40 #address-cells = <1>;
41 #size-cells = <1>;
42 reg = <0x80000000 0x40000>;
43 ranges;
44
45 icoll: interrupt-controller@80000000 {
46 compatible = "fsl,imx23-icoll", "fsl,icoll";
47 interrupt-controller;
48 #interrupt-cells = <1>;
49 reg = <0x80000000 0x2000>;
50 };
51
52 dma-apbh@80004000 {
53 compatible = "fsl,imx23-dma-apbh";
54 reg = <0x80004000 0x2000>;
55 clocks = <&clks 15>;
56 };
57
58 ecc@80008000 {
59 reg = <0x80008000 0x2000>;
60 status = "disabled";
61 };
62
63 gpmi-nand@8000c000 {
64 compatible = "fsl,imx23-gpmi-nand";
65 #address-cells = <1>;
66 #size-cells = <1>;
67 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
68 reg-names = "gpmi-nand", "bch";
69 interrupts = <13>, <56>;
70 interrupt-names = "gpmi-dma", "bch";
71 clocks = <&clks 34>;
72 clock-names = "gpmi_io";
73 fsl,gpmi-dma-channel = <4>;
74 status = "disabled";
75 };
76
77 ssp0: ssp@80010000 {
78 reg = <0x80010000 0x2000>;
79 interrupts = <15 14>;
80 clocks = <&clks 33>;
81 fsl,ssp-dma-channel = <1>;
82 status = "disabled";
83 };
84
85 etm@80014000 {
86 reg = <0x80014000 0x2000>;
87 status = "disabled";
88 };
89
90 pinctrl@80018000 {
91 #address-cells = <1>;
92 #size-cells = <0>;
93 compatible = "fsl,imx23-pinctrl", "simple-bus";
94 reg = <0x80018000 0x2000>;
95
96 gpio0: gpio@0 {
97 compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
98 interrupts = <16>;
99 gpio-controller;
100 #gpio-cells = <2>;
101 interrupt-controller;
102 #interrupt-cells = <2>;
103 };
104
105 gpio1: gpio@1 {
106 compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
107 interrupts = <17>;
108 gpio-controller;
109 #gpio-cells = <2>;
110 interrupt-controller;
111 #interrupt-cells = <2>;
112 };
113
114 gpio2: gpio@2 {
115 compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
116 interrupts = <18>;
117 gpio-controller;
118 #gpio-cells = <2>;
119 interrupt-controller;
120 #interrupt-cells = <2>;
121 };
122
123 duart_pins_a: duart@0 {
124 reg = <0>;
125 fsl,pinmux-ids = <
126 0x11a2 /* MX23_PAD_PWM0__DUART_RX */
127 0x11b2 /* MX23_PAD_PWM1__DUART_TX */
128 >;
129 fsl,drive-strength = <0>;
130 fsl,voltage = <1>;
131 fsl,pull-up = <0>;
132 };
133
134 auart0_pins_a: auart0@0 {
135 reg = <0>;
136 fsl,pinmux-ids = <
137 0x01c0 /* MX23_PAD_AUART1_RX__AUART1_RX */
138 0x01d0 /* MX23_PAD_AUART1_TX__AUART1_TX */
139 0x01a0 /* MX23_PAD_AUART1_CTS__AUART1_CTS */
140 0x01b0 /* MX23_PAD_AUART1_RTS__AUART1_RTS */
141 >;
142 fsl,drive-strength = <0>;
143 fsl,voltage = <1>;
144 fsl,pull-up = <0>;
145 };
146
147 auart0_2pins_a: auart0-2pins@0 {
148 reg = <0>;
149 fsl,pinmux-ids = <
150 0x01e2 /* MX23_PAD_I2C_SCL__AUART1_TX */
151 0x01f2 /* MX23_PAD_I2C_SDA__AUART1_RX */
152 >;
153 fsl,drive-strength = <0>;
154 fsl,voltage = <1>;
155 fsl,pull-up = <0>;
156 };
157
158 gpmi_pins_a: gpmi-nand@0 {
159 reg = <0>;
160 fsl,pinmux-ids = <
161 0x0000 /* MX23_PAD_GPMI_D00__GPMI_D00 */
162 0x0010 /* MX23_PAD_GPMI_D01__GPMI_D01 */
163 0x0020 /* MX23_PAD_GPMI_D02__GPMI_D02 */
164 0x0030 /* MX23_PAD_GPMI_D03__GPMI_D03 */
165 0x0040 /* MX23_PAD_GPMI_D04__GPMI_D04 */
166 0x0050 /* MX23_PAD_GPMI_D05__GPMI_D05 */
167 0x0060 /* MX23_PAD_GPMI_D06__GPMI_D06 */
168 0x0070 /* MX23_PAD_GPMI_D07__GPMI_D07 */
169 0x0100 /* MX23_PAD_GPMI_CLE__GPMI_CLE */
170 0x0110 /* MX23_PAD_GPMI_ALE__GPMI_ALE */
171 0x0130 /* MX23_PAD_GPMI_RDY0__GPMI_RDY0 */
172 0x0140 /* MX23_PAD_GPMI_RDY1__GPMI_RDY1 */
173 0x0170 /* MX23_PAD_GPMI_WPN__GPMI_WPN */
174 0x0180 /* MX23_PAD_GPMI_WRN__GPMI_WRN */
175 0x0190 /* MX23_PAD_GPMI_RDN__GPMI_RDN */
176 0x21b0 /* MX23_PAD_GPMI_CE1N__GPMI_CE1N */
177 0x21c0 /* MX23_PAD_GPMI_CE0N__GPMI_CE0N */
178 >;
179 fsl,drive-strength = <0>;
180 fsl,voltage = <1>;
181 fsl,pull-up = <0>;
182 };
183
184 gpmi_pins_fixup: gpmi-pins-fixup {
185 fsl,pinmux-ids = <
186 0x0170 /* MX23_PAD_GPMI_WPN__GPMI_WPN */
187 0x0180 /* MX23_PAD_GPMI_WRN__GPMI_WRN */
188 0x0190 /* MX23_PAD_GPMI_RDN__GPMI_RDN */
189 >;
190 fsl,drive-strength = <2>;
191 };
192
193 mmc0_4bit_pins_a: mmc0-4bit@0 {
194 reg = <0>;
195 fsl,pinmux-ids = <
196 0x2020 /* MX23_PAD_SSP1_DATA0__SSP1_DATA0 */
197 0x2030 /* MX23_PAD_SSP1_DATA1__SSP1_DATA1 */
198 0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */
199 0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */
200 0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */
201 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
202 >;
203 fsl,drive-strength = <1>;
204 fsl,voltage = <1>;
205 fsl,pull-up = <1>;
206 };
207
208 mmc0_8bit_pins_a: mmc0-8bit@0 {
209 reg = <0>;
210 fsl,pinmux-ids = <
211 0x2020 /* MX23_PAD_SSP1_DATA0__SSP1_DATA0 */
212 0x2030 /* MX23_PAD_SSP1_DATA1__SSP1_DATA1 */
213 0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */
214 0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */
215 0x0082 /* MX23_PAD_GPMI_D08__SSP1_DATA4 */
216 0x0092 /* MX23_PAD_GPMI_D09__SSP1_DATA5 */
217 0x00a2 /* MX23_PAD_GPMI_D10__SSP1_DATA6 */
218 0x00b2 /* MX23_PAD_GPMI_D11__SSP1_DATA7 */
219 0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */
220 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
221 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
222 >;
223 fsl,drive-strength = <1>;
224 fsl,voltage = <1>;
225 fsl,pull-up = <1>;
226 };
227
228 mmc0_pins_fixup: mmc0-pins-fixup {
229 fsl,pinmux-ids = <
230 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
231 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
232 >;
233 fsl,pull-up = <0>;
234 };
235
236 pwm2_pins_a: pwm2@0 {
237 reg = <0>;
238 fsl,pinmux-ids = <
239 0x11c0 /* MX23_PAD_PWM2__PWM2 */
240 >;
241 fsl,drive-strength = <0>;
242 fsl,voltage = <1>;
243 fsl,pull-up = <0>;
244 };
245
246 lcdif_24bit_pins_a: lcdif-24bit@0 {
247 reg = <0>;
248 fsl,pinmux-ids = <
249 0x1000 /* MX23_PAD_LCD_D00__LCD_D0 */
250 0x1010 /* MX23_PAD_LCD_D01__LCD_D1 */
251 0x1020 /* MX23_PAD_LCD_D02__LCD_D2 */
252 0x1030 /* MX23_PAD_LCD_D03__LCD_D3 */
253 0x1040 /* MX23_PAD_LCD_D04__LCD_D4 */
254 0x1050 /* MX23_PAD_LCD_D05__LCD_D5 */
255 0x1060 /* MX23_PAD_LCD_D06__LCD_D6 */
256 0x1070 /* MX23_PAD_LCD_D07__LCD_D7 */
257 0x1080 /* MX23_PAD_LCD_D08__LCD_D8 */
258 0x1090 /* MX23_PAD_LCD_D09__LCD_D9 */
259 0x10a0 /* MX23_PAD_LCD_D10__LCD_D10 */
260 0x10b0 /* MX23_PAD_LCD_D11__LCD_D11 */
261 0x10c0 /* MX23_PAD_LCD_D12__LCD_D12 */
262 0x10d0 /* MX23_PAD_LCD_D13__LCD_D13 */
263 0x10e0 /* MX23_PAD_LCD_D14__LCD_D14 */
264 0x10f0 /* MX23_PAD_LCD_D15__LCD_D15 */
265 0x1100 /* MX23_PAD_LCD_D16__LCD_D16 */
266 0x1110 /* MX23_PAD_LCD_D17__LCD_D17 */
267 0x0081 /* MX23_PAD_GPMI_D08__LCD_D18 */
268 0x0091 /* MX23_PAD_GPMI_D09__LCD_D19 */
269 0x00a1 /* MX23_PAD_GPMI_D10__LCD_D20 */
270 0x00b1 /* MX23_PAD_GPMI_D11__LCD_D21 */
271 0x00c1 /* MX23_PAD_GPMI_D12__LCD_D22 */
272 0x00d1 /* MX23_PAD_GPMI_D13__LCD_D23 */
273 0x1160 /* MX23_PAD_LCD_DOTCK__LCD_DOTCK */
274 0x1170 /* MX23_PAD_LCD_ENABLE__LCD_ENABLE */
275 0x1180 /* MX23_PAD_LCD_HSYNC__LCD_HSYNC */
276 0x1190 /* MX23_PAD_LCD_VSYNC__LCD_VSYNC */
277 >;
278 fsl,drive-strength = <0>;
279 fsl,voltage = <1>;
280 fsl,pull-up = <0>;
281 };
282
283 spi2_pins_a: spi2@0 {
284 reg = <0>;
285 fsl,pinmux-ids = <
286 0x0182 /* MX23_PAD_GPMI_WRN__SSP2_SCK */
287 0x0142 /* MX23_PAD_GPMI_RDY1__SSP2_CMD */
288 0x0002 /* MX23_PAD_GPMI_D00__SSP2_DATA0 */
289 0x0032 /* MX23_PAD_GPMI_D03__SSP2_DATA3 */
290 >;
291 fsl,drive-strength = <1>;
292 fsl,voltage = <1>;
293 fsl,pull-up = <1>;
294 };
295 };
296
297 digctl@8001c000 {
298 reg = <0x8001c000 2000>;
299 status = "disabled";
300 };
301
302 emi@80020000 {
303 reg = <0x80020000 0x2000>;
304 status = "disabled";
305 };
306
307 dma-apbx@80024000 {
308 compatible = "fsl,imx23-dma-apbx";
309 reg = <0x80024000 0x2000>;
310 clocks = <&clks 16>;
311 };
312
313 dcp@80028000 {
314 reg = <0x80028000 0x2000>;
315 status = "disabled";
316 };
317
318 pxp@8002a000 {
319 reg = <0x8002a000 0x2000>;
320 status = "disabled";
321 };
322
323 ocotp@8002c000 {
324 reg = <0x8002c000 0x2000>;
325 status = "disabled";
326 };
327
328 axi-ahb@8002e000 {
329 reg = <0x8002e000 0x2000>;
330 status = "disabled";
331 };
332
333 lcdif@80030000 {
334 compatible = "fsl,imx23-lcdif";
335 reg = <0x80030000 2000>;
336 interrupts = <46 45>;
337 clocks = <&clks 38>;
338 status = "disabled";
339 };
340
341 ssp1: ssp@80034000 {
342 reg = <0x80034000 0x2000>;
343 interrupts = <2 20>;
344 clocks = <&clks 33>;
345 fsl,ssp-dma-channel = <2>;
346 status = "disabled";
347 };
348
349 tvenc@80038000 {
350 reg = <0x80038000 0x2000>;
351 status = "disabled";
352 };
353 };
354
355 apbx@80040000 {
356 compatible = "simple-bus";
357 #address-cells = <1>;
358 #size-cells = <1>;
359 reg = <0x80040000 0x40000>;
360 ranges;
361
362 clks: clkctrl@80040000 {
363 compatible = "fsl,imx23-clkctrl";
364 reg = <0x80040000 0x2000>;
365 #clock-cells = <1>;
366 };
367
368 saif0: saif@80042000 {
369 reg = <0x80042000 0x2000>;
370 status = "disabled";
371 };
372
373 power@80044000 {
374 reg = <0x80044000 0x2000>;
375 status = "disabled";
376 };
377
378 saif1: saif@80046000 {
379 reg = <0x80046000 0x2000>;
380 status = "disabled";
381 };
382
383 audio-out@80048000 {
384 reg = <0x80048000 0x2000>;
385 status = "disabled";
386 };
387
388 audio-in@8004c000 {
389 reg = <0x8004c000 0x2000>;
390 status = "disabled";
391 };
392
393 lradc@80050000 {
394 reg = <0x80050000 0x2000>;
395 status = "disabled";
396 };
397
398 spdif@80054000 {
399 reg = <0x80054000 2000>;
400 status = "disabled";
401 };
402
403 i2c@80058000 {
404 reg = <0x80058000 0x2000>;
405 status = "disabled";
406 };
407
408 rtc@8005c000 {
409 compatible = "fsl,imx23-rtc", "fsl,stmp3xxx-rtc";
410 reg = <0x8005c000 0x2000>;
411 interrupts = <22>;
412 };
413
414 pwm: pwm@80064000 {
415 compatible = "fsl,imx23-pwm";
416 reg = <0x80064000 0x2000>;
417 clocks = <&clks 30>;
418 #pwm-cells = <2>;
419 fsl,pwm-number = <5>;
420 status = "disabled";
421 };
422
423 timrot@80068000 {
424 compatible = "fsl,imx23-timrot", "fsl,timrot";
425 reg = <0x80068000 0x2000>;
426 interrupts = <28 29 30 31>;
427 };
428
429 auart0: serial@8006c000 {
430 compatible = "fsl,imx23-auart";
431 reg = <0x8006c000 0x2000>;
432 interrupts = <24 25 23>;
433 clocks = <&clks 32>;
434 status = "disabled";
435 };
436
437 auart1: serial@8006e000 {
438 compatible = "fsl,imx23-auart";
439 reg = <0x8006e000 0x2000>;
440 interrupts = <59 60 58>;
441 clocks = <&clks 32>;
442 status = "disabled";
443 };
444
445 duart: serial@80070000 {
446 compatible = "arm,pl011", "arm,primecell";
447 reg = <0x80070000 0x2000>;
448 interrupts = <0>;
449 clocks = <&clks 32>, <&clks 16>;
450 clock-names = "uart", "apb_pclk";
451 status = "disabled";
452 };
453
454 usbphy0: usbphy@8007c000 {
455 compatible = "fsl,imx23-usbphy";
456 reg = <0x8007c000 0x2000>;
457 clocks = <&clks 41>;
458 status = "disabled";
459 };
460 };
461 };
462
463 ahb@80080000 {
464 compatible = "simple-bus";
465 #address-cells = <1>;
466 #size-cells = <1>;
467 reg = <0x80080000 0x80000>;
468 ranges;
469
470 usb0: usb@80080000 {
471 compatible = "fsl,imx23-usb", "fsl,imx27-usb";
472 reg = <0x80080000 0x40000>;
473 interrupts = <11>;
474 fsl,usbphy = <&usbphy0>;
475 clocks = <&clks 40>;
476 status = "disabled";
477 };
478 };
479};
diff --git a/arch/arm/boot/dts/imx25-karo-tx25.dts b/arch/arm/boot/dts/imx25-karo-tx25.dts
deleted file mode 100644
index d81f8a0b979..00000000000
--- a/arch/arm/boot/dts/imx25-karo-tx25.dts
+++ /dev/null
@@ -1,44 +0,0 @@
1/*
2 * Copyright 2012 Sascha Hauer, Pengutronix
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "imx25.dtsi"
14
15/ {
16 model = "Ka-Ro TX25";
17 compatible = "karo,imx25-tx25", "fsl,imx25";
18
19 memory {
20 reg = <0x80000000 0x02000000 0x90000000 0x02000000>;
21 };
22
23 soc {
24 aips@43f00000 {
25 uart1: serial@43f90000 {
26 status = "okay";
27 };
28 };
29
30 spba@50000000 {
31 fec: ethernet@50038000 {
32 status = "okay";
33 phy-mode = "rmii";
34 };
35 };
36
37 emi@80000000 {
38 nand@bb000000 {
39 nand-on-flash-bbt;
40 status = "okay";
41 };
42 };
43 };
44};
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
deleted file mode 100644
index e1b13ebc96d..00000000000
--- a/arch/arm/boot/dts/imx25.dtsi
+++ /dev/null
@@ -1,515 +0,0 @@
1/*
2 * Copyright 2012 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 aliases {
16 serial0 = &uart1;
17 serial1 = &uart2;
18 serial2 = &uart3;
19 serial3 = &uart4;
20 serial4 = &uart5;
21 gpio0 = &gpio1;
22 gpio1 = &gpio2;
23 gpio2 = &gpio3;
24 gpio3 = &gpio4;
25 usb0 = &usbotg;
26 usb1 = &usbhost1;
27 };
28
29 asic: asic-interrupt-controller@68000000 {
30 compatible = "fsl,imx25-asic", "fsl,avic";
31 interrupt-controller;
32 #interrupt-cells = <1>;
33 reg = <0x68000000 0x8000000>;
34 };
35
36 clocks {
37 #address-cells = <1>;
38 #size-cells = <0>;
39
40 osc {
41 compatible = "fsl,imx-osc", "fixed-clock";
42 clock-frequency = <24000000>;
43 };
44 };
45
46 soc {
47 #address-cells = <1>;
48 #size-cells = <1>;
49 compatible = "simple-bus";
50 interrupt-parent = <&asic>;
51 ranges;
52
53 aips@43f00000 { /* AIPS1 */
54 compatible = "fsl,aips-bus", "simple-bus";
55 #address-cells = <1>;
56 #size-cells = <1>;
57 reg = <0x43f00000 0x100000>;
58 ranges;
59
60 i2c1: i2c@43f80000 {
61 #address-cells = <1>;
62 #size-cells = <0>;
63 compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
64 reg = <0x43f80000 0x4000>;
65 clocks = <&clks 48>;
66 clock-names = "";
67 interrupts = <3>;
68 status = "disabled";
69 };
70
71 i2c3: i2c@43f84000 {
72 #address-cells = <1>;
73 #size-cells = <0>;
74 compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
75 reg = <0x43f84000 0x4000>;
76 clocks = <&clks 48>;
77 clock-names = "";
78 interrupts = <10>;
79 status = "disabled";
80 };
81
82 can1: can@43f88000 {
83 compatible = "fsl,imx25-flexcan", "fsl,p1010-flexcan";
84 reg = <0x43f88000 0x4000>;
85 interrupts = <43>;
86 clocks = <&clks 75>, <&clks 75>;
87 clock-names = "ipg", "per";
88 status = "disabled";
89 };
90
91 can2: can@43f8c000 {
92 compatible = "fsl,imx25-flexcan", "fsl,p1010-flexcan";
93 reg = <0x43f8c000 0x4000>;
94 interrupts = <44>;
95 clocks = <&clks 76>, <&clks 76>;
96 clock-names = "ipg", "per";
97 status = "disabled";
98 };
99
100 uart1: serial@43f90000 {
101 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
102 reg = <0x43f90000 0x4000>;
103 interrupts = <45>;
104 clocks = <&clks 120>, <&clks 57>;
105 clock-names = "ipg", "per";
106 status = "disabled";
107 };
108
109 uart2: serial@43f94000 {
110 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
111 reg = <0x43f94000 0x4000>;
112 interrupts = <32>;
113 clocks = <&clks 121>, <&clks 57>;
114 clock-names = "ipg", "per";
115 status = "disabled";
116 };
117
118 i2c2: i2c@43f98000 {
119 #address-cells = <1>;
120 #size-cells = <0>;
121 compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
122 reg = <0x43f98000 0x4000>;
123 clocks = <&clks 48>;
124 clock-names = "";
125 interrupts = <4>;
126 status = "disabled";
127 };
128
129 owire@43f9c000 {
130 #address-cells = <1>;
131 #size-cells = <0>;
132 reg = <0x43f9c000 0x4000>;
133 clocks = <&clks 51>;
134 clock-names = "";
135 interrupts = <2>;
136 status = "disabled";
137 };
138
139 spi1: cspi@43fa4000 {
140 #address-cells = <1>;
141 #size-cells = <0>;
142 compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
143 reg = <0x43fa4000 0x4000>;
144 clocks = <&clks 62>;
145 clock-names = "ipg";
146 interrupts = <14>;
147 status = "disabled";
148 };
149
150 kpp@43fa8000 {
151 #address-cells = <1>;
152 #size-cells = <0>;
153 reg = <0x43fa8000 0x4000>;
154 clocks = <&clks 102>;
155 clock-names = "";
156 interrupts = <24>;
157 status = "disabled";
158 };
159
160 iomuxc@43fac000{
161 compatible = "fsl,imx25-iomuxc";
162 reg = <0x43fac000 0x4000>;
163 };
164
165 audmux@43fb0000 {
166 compatible = "fsl,imx25-audmux", "fsl,imx31-audmux";
167 reg = <0x43fb0000 0x4000>;
168 status = "disabled";
169 };
170 };
171
172 spba@50000000 {
173 compatible = "fsl,spba-bus", "simple-bus";
174 #address-cells = <1>;
175 #size-cells = <1>;
176 reg = <0x50000000 0x40000>;
177 ranges;
178
179 spi3: cspi@50004000 {
180 #address-cells = <1>;
181 #size-cells = <0>;
182 compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
183 reg = <0x50004000 0x4000>;
184 interrupts = <0>;
185 clocks = <&clks 80>;
186 clock-names = "ipg";
187 status = "disabled";
188 };
189
190 uart4: serial@50008000 {
191 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
192 reg = <0x50008000 0x4000>;
193 interrupts = <5>;
194 clocks = <&clks 123>, <&clks 57>;
195 clock-names = "ipg", "per";
196 status = "disabled";
197 };
198
199 uart3: serial@5000c000 {
200 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
201 reg = <0x5000c000 0x4000>;
202 interrupts = <18>;
203 clocks = <&clks 122>, <&clks 57>;
204 clock-names = "ipg", "per";
205 status = "disabled";
206 };
207
208 spi2: cspi@50010000 {
209 #address-cells = <1>;
210 #size-cells = <0>;
211 compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
212 reg = <0x50010000 0x4000>;
213 clocks = <&clks 79>;
214 clock-names = "ipg";
215 interrupts = <13>;
216 status = "disabled";
217 };
218
219 ssi2: ssi@50014000 {
220 compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
221 reg = <0x50014000 0x4000>;
222 interrupts = <11>;
223 status = "disabled";
224 };
225
226 esai@50018000 {
227 reg = <0x50018000 0x4000>;
228 interrupts = <7>;
229 };
230
231 uart5: serial@5002c000 {
232 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
233 reg = <0x5002c000 0x4000>;
234 interrupts = <40>;
235 clocks = <&clks 124>, <&clks 57>;
236 clock-names = "ipg", "per";
237 status = "disabled";
238 };
239
240 tsc: tsc@50030000 {
241 compatible = "fsl,imx25-adc", "fsl,imx21-tsc";
242 reg = <0x50030000 0x4000>;
243 interrupts = <46>;
244 clocks = <&clks 119>;
245 clock-names = "ipg";
246 status = "disabled";
247 };
248
249 ssi1: ssi@50034000 {
250 compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
251 reg = <0x50034000 0x4000>;
252 interrupts = <12>;
253 status = "disabled";
254 };
255
256 fec: ethernet@50038000 {
257 compatible = "fsl,imx25-fec";
258 reg = <0x50038000 0x4000>;
259 interrupts = <57>;
260 clocks = <&clks 88>, <&clks 65>;
261 clock-names = "ipg", "ahb";
262 status = "disabled";
263 };
264 };
265
266 aips@53f00000 { /* AIPS2 */
267 compatible = "fsl,aips-bus", "simple-bus";
268 #address-cells = <1>;
269 #size-cells = <1>;
270 reg = <0x53f00000 0x100000>;
271 ranges;
272
273 clks: ccm@53f80000 {
274 compatible = "fsl,imx25-ccm";
275 reg = <0x53f80000 0x4000>;
276 interrupts = <31>;
277 #clock-cells = <1>;
278 };
279
280 gpt4: timer@53f84000 {
281 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
282 reg = <0x53f84000 0x4000>;
283 clocks = <&clks 9>, <&clks 45>;
284 clock-names = "ipg", "per";
285 interrupts = <1>;
286 };
287
288 gpt3: timer@53f88000 {
289 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
290 reg = <0x53f88000 0x4000>;
291 clocks = <&clks 9>, <&clks 47>;
292 clock-names = "ipg", "per";
293 interrupts = <29>;
294 };
295
296 gpt2: timer@53f8c000 {
297 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
298 reg = <0x53f8c000 0x4000>;
299 clocks = <&clks 9>, <&clks 47>;
300 clock-names = "ipg", "per";
301 interrupts = <53>;
302 };
303
304 gpt1: timer@53f90000 {
305 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
306 reg = <0x53f90000 0x4000>;
307 clocks = <&clks 9>, <&clks 47>;
308 clock-names = "ipg", "per";
309 interrupts = <54>;
310 };
311
312 epit1: timer@53f94000 {
313 compatible = "fsl,imx25-epit";
314 reg = <0x53f94000 0x4000>;
315 interrupts = <28>;
316 };
317
318 epit2: timer@53f98000 {
319 compatible = "fsl,imx25-epit";
320 reg = <0x53f98000 0x4000>;
321 interrupts = <27>;
322 };
323
324 gpio4: gpio@53f9c000 {
325 compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
326 reg = <0x53f9c000 0x4000>;
327 interrupts = <23>;
328 gpio-controller;
329 #gpio-cells = <2>;
330 interrupt-controller;
331 #interrupt-cells = <2>;
332 };
333
334 pwm2: pwm@53fa0000 {
335 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
336 #pwm-cells = <2>;
337 reg = <0x53fa0000 0x4000>;
338 clocks = <&clks 106>, <&clks 36>;
339 clock-names = "ipg", "per";
340 interrupts = <36>;
341 };
342
343 gpio3: gpio@53fa4000 {
344 compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
345 reg = <0x53fa4000 0x4000>;
346 interrupts = <16>;
347 gpio-controller;
348 #gpio-cells = <2>;
349 interrupt-controller;
350 #interrupt-cells = <2>;
351 };
352
353 pwm3: pwm@53fa8000 {
354 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
355 #pwm-cells = <2>;
356 reg = <0x53fa8000 0x4000>;
357 clocks = <&clks 107>, <&clks 36>;
358 clock-names = "ipg", "per";
359 interrupts = <41>;
360 };
361
362 esdhc1: esdhc@53fb4000 {
363 compatible = "fsl,imx25-esdhc";
364 reg = <0x53fb4000 0x4000>;
365 interrupts = <9>;
366 clocks = <&clks 86>, <&clks 63>, <&clks 45>;
367 clock-names = "ipg", "ahb", "per";
368 status = "disabled";
369 };
370
371 esdhc2: esdhc@53fb8000 {
372 compatible = "fsl,imx25-esdhc";
373 reg = <0x53fb8000 0x4000>;
374 interrupts = <8>;
375 clocks = <&clks 87>, <&clks 64>, <&clks 46>;
376 clock-names = "ipg", "ahb", "per";
377 status = "disabled";
378 };
379
380 lcdc@53fbc000 {
381 reg = <0x53fbc000 0x4000>;
382 interrupts = <39>;
383 clocks = <&clks 103>, <&clks 66>, <&clks 49>;
384 clock-names = "ipg", "ahb", "per";
385 status = "disabled";
386 };
387
388 slcdc@53fc0000 {
389 reg = <0x53fc0000 0x4000>;
390 interrupts = <38>;
391 status = "disabled";
392 };
393
394 pwm4: pwm@53fc8000 {
395 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
396 reg = <0x53fc8000 0x4000>;
397 clocks = <&clks 108>, <&clks 36>;
398 clock-names = "ipg", "per";
399 interrupts = <42>;
400 };
401
402 gpio1: gpio@53fcc000 {
403 compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
404 reg = <0x53fcc000 0x4000>;
405 interrupts = <52>;
406 gpio-controller;
407 #gpio-cells = <2>;
408 interrupt-controller;
409 #interrupt-cells = <2>;
410 };
411
412 gpio2: gpio@53fd0000 {
413 compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
414 reg = <0x53fd0000 0x4000>;
415 interrupts = <51>;
416 gpio-controller;
417 #gpio-cells = <2>;
418 interrupt-controller;
419 #interrupt-cells = <2>;
420 };
421
422 sdma@53fd4000 {
423 compatible = "fsl,imx25-sdma", "fsl,imx35-sdma";
424 reg = <0x53fd4000 0x4000>;
425 clocks = <&clks 112>, <&clks 68>;
426 clock-names = "ipg", "ahb";
427 interrupts = <34>;
428 };
429
430 wdog@53fdc000 {
431 compatible = "fsl,imx25-wdt", "fsl,imx21-wdt";
432 reg = <0x53fdc000 0x4000>;
433 clocks = <&clks 126>;
434 clock-names = "";
435 interrupts = <55>;
436 };
437
438 pwm1: pwm@53fe0000 {
439 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
440 #pwm-cells = <2>;
441 reg = <0x53fe0000 0x4000>;
442 clocks = <&clks 105>, <&clks 36>;
443 clock-names = "ipg", "per";
444 interrupts = <26>;
445 };
446
447 usbphy1: usbphy@1 {
448 compatible = "nop-usbphy";
449 status = "disabled";
450 };
451
452 usbphy2: usbphy@2 {
453 compatible = "nop-usbphy";
454 status = "disabled";
455 };
456
457 usbotg: usb@53ff4000 {
458 compatible = "fsl,imx25-usb", "fsl,imx27-usb";
459 reg = <0x53ff4000 0x0200>;
460 interrupts = <37>;
461 clocks = <&clks 9>, <&clks 70>, <&clks 8>;
462 clock-names = "ipg", "ahb", "per";
463 fsl,usbmisc = <&usbmisc 0>;
464 status = "disabled";
465 };
466
467 usbhost1: usb@53ff4400 {
468 compatible = "fsl,imx25-usb", "fsl,imx27-usb";
469 reg = <0x53ff4400 0x0200>;
470 interrupts = <35>;
471 clocks = <&clks 9>, <&clks 70>, <&clks 8>;
472 clock-names = "ipg", "ahb", "per";
473 fsl,usbmisc = <&usbmisc 1>;
474 status = "disabled";
475 };
476
477 usbmisc: usbmisc@53ff4600 {
478 #index-cells = <1>;
479 compatible = "fsl,imx25-usbmisc";
480 clocks = <&clks 9>, <&clks 70>, <&clks 8>;
481 clock-names = "ipg", "ahb", "per";
482 reg = <0x53ff4600 0x00f>;
483 status = "disabled";
484 };
485
486 dryice@53ffc000 {
487 compatible = "fsl,imx25-dryice", "fsl,imx25-rtc";
488 reg = <0x53ffc000 0x4000>;
489 clocks = <&clks 81>;
490 clock-names = "ipg";
491 interrupts = <25>;
492 };
493 };
494
495 emi@80000000 {
496 compatible = "fsl,emi-bus", "simple-bus";
497 #address-cells = <1>;
498 #size-cells = <1>;
499 reg = <0x80000000 0x3b002000>;
500 ranges;
501
502 nand@bb000000 {
503 #address-cells = <1>;
504 #size-cells = <1>;
505
506 compatible = "fsl,imx25-nand";
507 reg = <0xbb000000 0x2000>;
508 clocks = <&clks 50>;
509 clock-names = "";
510 interrupts = <33>;
511 status = "disabled";
512 };
513 };
514 };
515};
diff --git a/arch/arm/boot/dts/imx27-3ds.dts b/arch/arm/boot/dts/imx27-3ds.dts
deleted file mode 100644
index fa04c7b18bc..00000000000
--- a/arch/arm/boot/dts/imx27-3ds.dts
+++ /dev/null
@@ -1,37 +0,0 @@
1/*
2 * Copyright 2012 Sascha Hauer, Pengutronix
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "imx27.dtsi"
14
15/ {
16 model = "mx27_3ds";
17 compatible = "freescale,imx27-3ds", "fsl,imx27";
18
19 memory {
20 reg = <0x0 0x0>;
21 };
22
23 soc {
24 aipi@10000000 { /* aipi1 */
25 uart1: serial@1000a000 {
26 fsl,uart-has-rtscts;
27 status = "okay";
28 };
29 };
30
31 aipi@10020000 { /* aipi2 */
32 ethernet@1002b000 {
33 status = "okay";
34 };
35 };
36 };
37};
diff --git a/arch/arm/boot/dts/imx27-apf27.dts b/arch/arm/boot/dts/imx27-apf27.dts
deleted file mode 100644
index c0327c054de..00000000000
--- a/arch/arm/boot/dts/imx27-apf27.dts
+++ /dev/null
@@ -1,89 +0,0 @@
1/*
2 * Copyright 2012 Philippe Reynes <tremyfr@yahoo.fr>
3 * Copyright 2012 Armadeus Systems <support@armadeus.com>
4 *
5 * Based on code which is: Copyright 2012 Sascha Hauer, Pengutronix
6 *
7 * The code contained herein is licensed under the GNU General Public
8 * License. You may obtain a copy of the GNU General Public License
9 * Version 2 or later at the following locations:
10 *
11 * http://www.opensource.org/licenses/gpl-license.html
12 * http://www.gnu.org/copyleft/gpl.html
13 */
14
15/dts-v1/;
16/include/ "imx27.dtsi"
17
18/ {
19 model = "Armadeus Systems APF27 module";
20 compatible = "armadeus,imx27-apf27", "fsl,imx27";
21
22 memory {
23 reg = <0xa0000000 0x04000000>;
24 };
25
26 clocks {
27 #address-cells = <1>;
28 #size-cells = <0>;
29
30 osc26m {
31 compatible = "fsl,imx-osc26m", "fixed-clock";
32 clock-frequency = <0>;
33 };
34 };
35
36 soc {
37 aipi@10000000 {
38 serial@1000a000 {
39 status = "okay";
40 };
41
42 ethernet@1002b000 {
43 status = "okay";
44 };
45 };
46
47 nand@d8000000 {
48 status = "okay";
49 nand-bus-width = <16>;
50 nand-ecc-mode = "hw";
51 nand-on-flash-bbt;
52
53 partition@0 {
54 label = "u-boot";
55 reg = <0x0 0x100000>;
56 };
57
58 partition@100000 {
59 label = "env";
60 reg = <0x100000 0x80000>;
61 };
62
63 partition@180000 {
64 label = "env2";
65 reg = <0x180000 0x80000>;
66 };
67
68 partition@200000 {
69 label = "firmware";
70 reg = <0x200000 0x80000>;
71 };
72
73 partition@280000 {
74 label = "dtb";
75 reg = <0x280000 0x80000>;
76 };
77
78 partition@300000 {
79 label = "kernel";
80 reg = <0x300000 0x500000>;
81 };
82
83 partition@800000 {
84 label = "rootfs";
85 reg = <0x800000 0xf800000>;
86 };
87 };
88 };
89};
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore.dts b/arch/arm/boot/dts/imx27-phytec-phycore.dts
deleted file mode 100644
index 53b0ec0c228..00000000000
--- a/arch/arm/boot/dts/imx27-phytec-phycore.dts
+++ /dev/null
@@ -1,73 +0,0 @@
1/*
2 * Copyright 2012 Sascha Hauer, Pengutronix
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "imx27.dtsi"
14
15/ {
16 model = "Phytec pcm038";
17 compatible = "phytec,imx27-pcm038", "fsl,imx27";
18
19 memory {
20 reg = <0x0 0x0>;
21 };
22
23 soc {
24 aipi@10000000 { /* aipi1 */
25 serial@1000a000 {
26 fsl,uart-has-rtscts;
27 status = "okay";
28 };
29
30 serial@1000b000 {
31 fsl,uart-has-rtscts;
32 status = "okay";
33 };
34
35 serial@1000c000 {
36 fsl,uart-has-rtscts;
37 status = "okay";
38 };
39
40 i2c@1001d000 {
41 clock-frequency = <400000>;
42 status = "okay";
43 at24@52 {
44 compatible = "at,24c32";
45 pagesize = <32>;
46 reg = <0x52>;
47 };
48 pcf8563@51 {
49 compatible = "nxp,pcf8563";
50 reg = <0x51>;
51 };
52 lm75@4a {
53 compatible = "national,lm75";
54 reg = <0x4a>;
55 };
56 };
57 };
58
59 aipi@10020000 { /* aipi2 */
60 ethernet@1002b000 {
61 status = "okay";
62 };
63 };
64 };
65
66 nor_flash@c0000000 {
67 compatible = "cfi-flash";
68 bank-width = <2>;
69 reg = <0xc0000000 0x02000000>;
70 #address-cells = <1>;
71 #size-cells = <1>;
72 };
73};
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
deleted file mode 100644
index 5a82cb5707a..00000000000
--- a/arch/arm/boot/dts/imx27.dtsi
+++ /dev/null
@@ -1,241 +0,0 @@
1/*
2 * Copyright 2012 Sascha Hauer, Pengutronix
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 aliases {
16 serial0 = &uart1;
17 serial1 = &uart2;
18 serial2 = &uart3;
19 serial3 = &uart4;
20 serial4 = &uart5;
21 serial5 = &uart6;
22 gpio0 = &gpio1;
23 gpio1 = &gpio2;
24 gpio2 = &gpio3;
25 gpio3 = &gpio4;
26 gpio4 = &gpio5;
27 gpio5 = &gpio6;
28 };
29
30 avic: avic-interrupt-controller@e0000000 {
31 compatible = "fsl,imx27-avic", "fsl,avic";
32 interrupt-controller;
33 #interrupt-cells = <1>;
34 reg = <0x10040000 0x1000>;
35 };
36
37 clocks {
38 #address-cells = <1>;
39 #size-cells = <0>;
40
41 osc26m {
42 compatible = "fsl,imx-osc26m", "fixed-clock";
43 clock-frequency = <26000000>;
44 };
45 };
46
47 soc {
48 #address-cells = <1>;
49 #size-cells = <1>;
50 compatible = "simple-bus";
51 interrupt-parent = <&avic>;
52 ranges;
53
54 aipi@10000000 { /* AIPI1 */
55 compatible = "fsl,aipi-bus", "simple-bus";
56 #address-cells = <1>;
57 #size-cells = <1>;
58 reg = <0x10000000 0x20000>;
59 ranges;
60
61 wdog: wdog@10002000 {
62 compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
63 reg = <0x10002000 0x4000>;
64 interrupts = <27>;
65 };
66
67 uart1: serial@1000a000 {
68 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
69 reg = <0x1000a000 0x1000>;
70 interrupts = <20>;
71 status = "disabled";
72 };
73
74 uart2: serial@1000b000 {
75 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
76 reg = <0x1000b000 0x1000>;
77 interrupts = <19>;
78 status = "disabled";
79 };
80
81 uart3: serial@1000c000 {
82 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
83 reg = <0x1000c000 0x1000>;
84 interrupts = <18>;
85 status = "disabled";
86 };
87
88 uart4: serial@1000d000 {
89 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
90 reg = <0x1000d000 0x1000>;
91 interrupts = <17>;
92 status = "disabled";
93 };
94
95 cspi1: cspi@1000e000 {
96 #address-cells = <1>;
97 #size-cells = <0>;
98 compatible = "fsl,imx27-cspi";
99 reg = <0x1000e000 0x1000>;
100 interrupts = <16>;
101 status = "disabled";
102 };
103
104 cspi2: cspi@1000f000 {
105 #address-cells = <1>;
106 #size-cells = <0>;
107 compatible = "fsl,imx27-cspi";
108 reg = <0x1000f000 0x1000>;
109 interrupts = <15>;
110 status = "disabled";
111 };
112
113 i2c1: i2c@10012000 {
114 #address-cells = <1>;
115 #size-cells = <0>;
116 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
117 reg = <0x10012000 0x1000>;
118 interrupts = <12>;
119 status = "disabled";
120 };
121
122 gpio1: gpio@10015000 {
123 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
124 reg = <0x10015000 0x100>;
125 interrupts = <8>;
126 gpio-controller;
127 #gpio-cells = <2>;
128 interrupt-controller;
129 #interrupt-cells = <2>;
130 };
131
132 gpio2: gpio@10015100 {
133 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
134 reg = <0x10015100 0x100>;
135 interrupts = <8>;
136 gpio-controller;
137 #gpio-cells = <2>;
138 interrupt-controller;
139 #interrupt-cells = <2>;
140 };
141
142 gpio3: gpio@10015200 {
143 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
144 reg = <0x10015200 0x100>;
145 interrupts = <8>;
146 gpio-controller;
147 #gpio-cells = <2>;
148 interrupt-controller;
149 #interrupt-cells = <2>;
150 };
151
152 gpio4: gpio@10015300 {
153 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
154 reg = <0x10015300 0x100>;
155 interrupts = <8>;
156 gpio-controller;
157 #gpio-cells = <2>;
158 interrupt-controller;
159 #interrupt-cells = <2>;
160 };
161
162 gpio5: gpio@10015400 {
163 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
164 reg = <0x10015400 0x100>;
165 interrupts = <8>;
166 gpio-controller;
167 #gpio-cells = <2>;
168 interrupt-controller;
169 #interrupt-cells = <2>;
170 };
171
172 gpio6: gpio@10015500 {
173 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
174 reg = <0x10015500 0x100>;
175 interrupts = <8>;
176 gpio-controller;
177 #gpio-cells = <2>;
178 interrupt-controller;
179 #interrupt-cells = <2>;
180 };
181
182 cspi3: cspi@10017000 {
183 #address-cells = <1>;
184 #size-cells = <0>;
185 compatible = "fsl,imx27-cspi";
186 reg = <0x10017000 0x1000>;
187 interrupts = <6>;
188 status = "disabled";
189 };
190
191 uart5: serial@1001b000 {
192 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
193 reg = <0x1001b000 0x1000>;
194 interrupts = <49>;
195 status = "disabled";
196 };
197
198 uart6: serial@1001c000 {
199 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
200 reg = <0x1001c000 0x1000>;
201 interrupts = <48>;
202 status = "disabled";
203 };
204
205 i2c2: i2c@1001d000 {
206 #address-cells = <1>;
207 #size-cells = <0>;
208 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
209 reg = <0x1001d000 0x1000>;
210 interrupts = <1>;
211 status = "disabled";
212 };
213
214 };
215
216 aipi@10020000 { /* AIPI2 */
217 compatible = "fsl,aipi-bus", "simple-bus";
218 #address-cells = <1>;
219 #size-cells = <1>;
220 reg = <0x10020000 0x20000>;
221 ranges;
222
223 fec: ethernet@1002b000 {
224 compatible = "fsl,imx27-fec";
225 reg = <0x1002b000 0x4000>;
226 interrupts = <50>;
227 status = "disabled";
228 };
229 };
230
231 nfc: nand@d8000000 {
232 #address-cells = <1>;
233 #size-cells = <1>;
234
235 compatible = "fsl,imx27-nand";
236 reg = <0xd8000000 0x1000>;
237 interrupts = <29>;
238 status = "disabled";
239 };
240 };
241};
diff --git a/arch/arm/boot/dts/imx28-apf28.dts b/arch/arm/boot/dts/imx28-apf28.dts
deleted file mode 100644
index 7eb075876c4..00000000000
--- a/arch/arm/boot/dts/imx28-apf28.dts
+++ /dev/null
@@ -1,85 +0,0 @@
1/*
2 * Copyright 2012 Armadeus Systems - <support@armadeus.com>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "imx28.dtsi"
14
15/ {
16 model = "Armadeus Systems APF28 module";
17 compatible = "armadeus,imx28-apf28", "fsl,imx28";
18
19 memory {
20 reg = <0x40000000 0x08000000>;
21 };
22
23 apb@80000000 {
24 apbh@80000000 {
25 gpmi-nand@8000c000 {
26 pinctrl-names = "default";
27 pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
28 status = "okay";
29
30 partition@0 {
31 label = "u-boot";
32 reg = <0x0 0x300000>;
33 };
34
35 partition@300000 {
36 label = "env";
37 reg = <0x300000 0x80000>;
38 };
39
40 partition@380000 {
41 label = "env2";
42 reg = <0x380000 0x80000>;
43 };
44
45 partition@400000 {
46 label = "dtb";
47 reg = <0x400000 0x80000>;
48 };
49
50 partition@480000 {
51 label = "splash";
52 reg = <0x480000 0x80000>;
53 };
54
55 partition@500000 {
56 label = "kernel";
57 reg = <0x500000 0x800000>;
58 };
59
60 partition@d00000 {
61 label = "rootfs";
62 reg = <0xd00000 0xf300000>;
63 };
64 };
65 };
66
67 apbx@80040000 {
68 duart: serial@80074000 {
69 pinctrl-names = "default";
70 pinctrl-0 = <&duart_pins_a>;
71 status = "okay";
72 };
73 };
74 };
75
76 ahb@80080000 {
77 mac0: ethernet@800f0000 {
78 phy-mode = "rmii";
79 pinctrl-names = "default";
80 pinctrl-0 = <&mac0_pins_a>;
81 phy-reset-gpios = <&gpio4 13 0>;
82 status = "okay";
83 };
84 };
85};
diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts
deleted file mode 100644
index 6d8865bfb4b..00000000000
--- a/arch/arm/boot/dts/imx28-apf28dev.dts
+++ /dev/null
@@ -1,154 +0,0 @@
1/*
2 * Copyright 2012 Armadeus Systems - <support@armadeus.com>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/* APF28Dev is a docking board for the APF28 SOM */
13/include/ "imx28-apf28.dts"
14
15/ {
16 model = "Armadeus Systems APF28Dev docking/development board";
17 compatible = "armadeus,imx28-apf28dev", "armadeus,imx28-apf28", "fsl,imx28";
18
19 apb@80000000 {
20 apbh@80000000 {
21 ssp0: ssp@80010000 {
22 compatible = "fsl,imx28-mmc";
23 pinctrl-names = "default";
24 pinctrl-0 = <&mmc0_4bit_pins_a
25 &mmc0_cd_cfg &mmc0_sck_cfg>;
26 bus-width = <4>;
27 status = "okay";
28 };
29
30 ssp2: ssp@80014000 {
31 compatible = "fsl,imx28-spi";
32 pinctrl-names = "default";
33 pinctrl-0 = <&spi2_pins_a>;
34 status = "okay";
35 };
36
37 pinctrl@80018000 {
38 pinctrl-names = "default";
39 pinctrl-0 = <&hog_pins_apf28dev>;
40
41 hog_pins_apf28dev: hog@0 {
42 reg = <0>;
43 fsl,pinmux-ids = <
44 0x1103 /* MX28_PAD_LCD_D16__GPIO_1_16 */
45 0x1113 /* MX28_PAD_LCD_D17__GPIO_1_17 */
46 0x1123 /* MX28_PAD_LCD_D18__GPIO_1_18 */
47 0x1133 /* MX28_PAD_LCD_D19__GPIO_1_19 */
48 0x1143 /* MX28_PAD_LCD_D20__GPIO_1_20 */
49 0x1153 /* MX28_PAD_LCD_D21__GPIO_1_21 */
50 0x1163 /* MX28_PAD_LCD_D22__GPIO_1_22 */
51 >;
52 fsl,drive-strength = <0>;
53 fsl,voltage = <1>;
54 fsl,pull-up = <0>;
55 };
56
57 lcdif_pins_apf28dev: lcdif-apf28dev@0 {
58 reg = <0>;
59 fsl,pinmux-ids = <
60 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */
61 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */
62 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */
63 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */
64 >;
65 fsl,drive-strength = <0>;
66 fsl,voltage = <1>;
67 fsl,pull-up = <0>;
68 };
69 };
70
71 lcdif@80030000 {
72 pinctrl-names = "default";
73 pinctrl-0 = <&lcdif_16bit_pins_a
74 &lcdif_pins_apf28dev>;
75 status = "okay";
76 };
77 };
78
79 apbx@80040000 {
80 lradc@80050000 {
81 status = "okay";
82 };
83
84 i2c0: i2c@80058000 {
85 pinctrl-names = "default";
86 pinctrl-0 = <&i2c0_pins_a>;
87 status = "okay";
88 };
89
90 pwm: pwm@80064000 {
91 pinctrl-names = "default";
92 pinctrl-0 = <&pwm3_pins_a &pwm4_pins_a>;
93 status = "okay";
94 };
95
96 usbphy0: usbphy@8007c000 {
97 status = "okay";
98 };
99
100 usbphy1: usbphy@8007e000 {
101 status = "okay";
102 };
103 };
104 };
105
106 ahb@80080000 {
107 usb0: usb@80080000 {
108 vbus-supply = <&reg_usb0_vbus>;
109 status = "okay";
110 };
111
112 usb1: usb@80090000 {
113 status = "okay";
114 };
115
116 mac1: ethernet@800f4000 {
117 phy-mode = "rmii";
118 pinctrl-names = "default";
119 pinctrl-0 = <&mac1_pins_a>;
120 phy-reset-gpios = <&gpio0 23 0>;
121 status = "okay";
122 };
123 };
124
125 regulators {
126 compatible = "simple-bus";
127
128 reg_usb0_vbus: usb0_vbus {
129 compatible = "regulator-fixed";
130 regulator-name = "usb0_vbus";
131 regulator-min-microvolt = <5000000>;
132 regulator-max-microvolt = <5000000>;
133 gpio = <&gpio1 23 1>;
134 };
135 };
136
137 leds {
138 compatible = "gpio-leds";
139
140 user {
141 label = "Heartbeat";
142 gpios = <&gpio0 21 0>;
143 linux,default-trigger = "heartbeat";
144 };
145 };
146
147 backlight {
148 compatible = "pwm-backlight";
149
150 pwms = <&pwm 3 191000>;
151 brightness-levels = <0 4 8 16 32 64 128 255>;
152 default-brightness-level = <6>;
153 };
154};
diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts
deleted file mode 100644
index 5171667a776..00000000000
--- a/arch/arm/boot/dts/imx28-apx4devkit.dts
+++ /dev/null
@@ -1,198 +0,0 @@
1/dts-v1/;
2/include/ "imx28.dtsi"
3
4/ {
5 model = "Bluegiga APX4 Development Kit";
6 compatible = "bluegiga,apx4devkit", "fsl,imx28";
7
8 memory {
9 reg = <0x40000000 0x04000000>;
10 };
11
12 apb@80000000 {
13 apbh@80000000 {
14 gpmi-nand@8000c000 {
15 pinctrl-names = "default";
16 pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
17 status = "okay";
18 };
19
20 ssp0: ssp@80010000 {
21 compatible = "fsl,imx28-mmc";
22 pinctrl-names = "default";
23 pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_sck_cfg>;
24 bus-width = <4>;
25 status = "okay";
26 };
27
28 ssp2: ssp@80014000 {
29 compatible = "fsl,imx28-mmc";
30 pinctrl-names = "default";
31 pinctrl-0 = <&mmc2_4bit_pins_apx4 &mmc2_sck_cfg_apx4>;
32 bus-width = <4>;
33 status = "okay";
34 };
35
36 pinctrl@80018000 {
37 pinctrl-names = "default";
38 pinctrl-0 = <&hog_pins_a>;
39
40 hog_pins_a: hog@0 {
41 reg = <0>;
42 fsl,pinmux-ids = <
43 0x0113 /* MX28_PAD_GPMI_CE1N__GPIO_0_17 */
44 0x0153 /* MX28_PAD_GPMI_RDY1__GPIO_0_21 */
45 0x2123 /* MX28_PAD_SSP2_MISO__GPIO_2_18 */
46 0x2131 /* MX28_PAD_SSP2_SS0__GPIO_2_19 */
47 0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */
48 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */
49 0x4143 /* MX28_PAD_JTAG_RTCK__GPIO_4_20 */
50 >;
51 fsl,drive-strength = <0>;
52 fsl,voltage = <1>;
53 fsl,pull-up = <0>;
54 };
55
56 lcdif_pins_apx4: lcdif-apx4@0 {
57 reg = <0>;
58 fsl,pinmux-ids = <
59 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */
60 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */
61 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */
62 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */
63 >;
64 fsl,drive-strength = <0>;
65 fsl,voltage = <1>;
66 fsl,pull-up = <0>;
67 };
68
69 mmc2_4bit_pins_apx4: mmc2-4bit-apx4@0 {
70 reg = <0>;
71 fsl,pinmux-ids = <
72 0x2041 /* MX28_PAD_SSP0_DATA4__SSP2_D0 */
73 0x2051 /* MX28_PAD_SSP0_DATA5__SSP2_D3 */
74 0x2061 /* MX28_PAD_SSP0_DATA6__SSP2_CMD */
75 0x2071 /* MX28_PAD_SSP0_DATA7__SSP2_SCK */
76 0x2141 /* MX28_PAD_SSP2_SS1__SSP2_D1 */
77 0x2151 /* MX28_PAD_SSP2_SS2__SSP2_D2 */
78 >;
79 fsl,drive-strength = <1>;
80 fsl,voltage = <1>;
81 fsl,pull-up = <1>;
82 };
83
84 mmc2_sck_cfg_apx4: mmc2-sck-cfg-apx4 {
85 fsl,pinmux-ids = <
86 0x2071 /* MX28_PAD_SSP0_DATA7__SSP2_SCK */
87 >;
88 fsl,drive-strength = <2>;
89 fsl,pull-up = <0>;
90 };
91 };
92
93 lcdif@80030000 {
94 pinctrl-names = "default";
95 pinctrl-0 = <&lcdif_24bit_pins_a
96 &lcdif_pins_apx4>;
97 status = "okay";
98 };
99 };
100
101 apbx@80040000 {
102 saif0: saif@80042000 {
103 pinctrl-names = "default";
104 pinctrl-0 = <&saif0_pins_a>;
105 status = "okay";
106 };
107
108 saif1: saif@80046000 {
109 pinctrl-names = "default";
110 pinctrl-0 = <&saif1_pins_a>;
111 fsl,saif-master = <&saif0>;
112 status = "okay";
113 };
114
115 i2c0: i2c@80058000 {
116 pinctrl-names = "default";
117 pinctrl-0 = <&i2c0_pins_a>;
118 status = "okay";
119
120 sgtl5000: codec@0a {
121 compatible = "fsl,sgtl5000";
122 reg = <0x0a>;
123 VDDA-supply = <&reg_3p3v>;
124 VDDIO-supply = <&reg_3p3v>;
125
126 };
127
128 pcf8563: rtc@51 {
129 compatible = "phg,pcf8563";
130 reg = <0x51>;
131 };
132 };
133
134 duart: serial@80074000 {
135 pinctrl-names = "default";
136 pinctrl-0 = <&duart_pins_a>;
137 status = "okay";
138 };
139
140 auart0: serial@8006a000 {
141 pinctrl-names = "default";
142 pinctrl-0 = <&auart0_pins_a>;
143 status = "okay";
144 };
145
146 auart1: serial@8006c000 {
147 pinctrl-names = "default";
148 pinctrl-0 = <&auart1_2pins_a>;
149 status = "okay";
150 };
151
152 auart2: serial@8006e000 {
153 pinctrl-names = "default";
154 pinctrl-0 = <&auart2_2pins_a>;
155 status = "okay";
156 };
157 };
158 };
159
160 ahb@80080000 {
161 mac0: ethernet@800f0000 {
162 phy-mode = "rmii";
163 pinctrl-names = "default";
164 pinctrl-0 = <&mac0_pins_a>;
165 status = "okay";
166 };
167 };
168
169 regulators {
170 compatible = "simple-bus";
171
172 reg_3p3v: 3p3v {
173 compatible = "regulator-fixed";
174 regulator-name = "3P3V";
175 regulator-min-microvolt = <3300000>;
176 regulator-max-microvolt = <3300000>;
177 regulator-always-on;
178 };
179 };
180
181 sound {
182 compatible = "bluegiga,apx4devkit-sgtl5000",
183 "fsl,mxs-audio-sgtl5000";
184 model = "apx4devkit-sgtl5000";
185 saif-controllers = <&saif0 &saif1>;
186 audio-codec = <&sgtl5000>;
187 };
188
189 leds {
190 compatible = "gpio-leds";
191
192 user {
193 label = "Heartbeat";
194 gpios = <&gpio3 28 0>;
195 linux,default-trigger = "heartbeat";
196 };
197 };
198};
diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts
deleted file mode 100644
index 1594694532b..00000000000
--- a/arch/arm/boot/dts/imx28-cfa10036.dts
+++ /dev/null
@@ -1,98 +0,0 @@
1/*
2 * Copyright 2012 Free Electrons
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "imx28.dtsi"
14
15/ {
16 model = "Crystalfontz CFA-10036 Board";
17 compatible = "crystalfontz,cfa10036", "fsl,imx28";
18
19 memory {
20 reg = <0x40000000 0x08000000>;
21 };
22
23 apb@80000000 {
24 apbh@80000000 {
25 pinctrl@80018000 {
26 pinctrl-names = "default";
27 pinctrl-0 = <&hog_pins_cfa10036>;
28
29 hog_pins_cfa10036: hog-10036@0 {
30 reg = <0>;
31 fsl,pinmux-ids = <
32 0x2073 /* MX28_PAD_SSP0_D7__GPIO_2_7 */
33 >;
34 fsl,drive-strength = <0>;
35 fsl,voltage = <1>;
36 fsl,pull-up = <0>;
37 };
38
39 led_pins_cfa10036: leds-10036@0 {
40 reg = <0>;
41 fsl,pinmux-ids = <
42 0x3043 /* MX28_PAD_AUART1_RX__GPIO_3_4 */
43 >;
44 fsl,drive-strength = <0>;
45 fsl,voltage = <1>;
46 fsl,pull-up = <0>;
47 };
48 };
49
50 ssp0: ssp@80010000 {
51 compatible = "fsl,imx28-mmc";
52 pinctrl-names = "default";
53 pinctrl-0 = <&mmc0_4bit_pins_a
54 &mmc0_cd_cfg &mmc0_sck_cfg>;
55 bus-width = <4>;
56 status = "okay";
57 };
58 };
59
60 apbx@80040000 {
61 pwm: pwm@80064000 {
62 pinctrl-names = "default";
63 pinctrl-0 = <&pwm4_pins_a>;
64 status = "okay";
65 };
66
67 duart: serial@80074000 {
68 pinctrl-names = "default";
69 pinctrl-0 = <&duart_pins_b>;
70 status = "okay";
71 };
72
73 i2c0: i2c@80058000 {
74 pinctrl-names = "default";
75 pinctrl-0 = <&i2c0_pins_b>;
76 status = "okay";
77
78 ssd1307: oled@3c {
79 compatible = "solomon,ssd1307fb-i2c";
80 reg = <0x3c>;
81 pwms = <&pwm 4 3000>;
82 reset-gpios = <&gpio2 7 0>;
83 };
84 };
85 };
86 };
87
88 leds {
89 compatible = "gpio-leds";
90 pinctrl-names = "default";
91 pinctrl-0 = <&led_pins_cfa10036>;
92
93 power {
94 gpios = <&gpio3 4 1>;
95 default-state = "on";
96 };
97 };
98};
diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts
deleted file mode 100644
index bdc80a4453d..00000000000
--- a/arch/arm/boot/dts/imx28-cfa10049.dts
+++ /dev/null
@@ -1,156 +0,0 @@
1/*
2 * Copyright 2012 Free Electrons
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/*
13 * The CFA-10049 is an expansion board for the CFA-10036 module, thus we
14 * need to include the CFA-10036 DTS.
15 */
16/include/ "imx28-cfa10036.dts"
17
18/ {
19 model = "Crystalfontz CFA-10049 Board";
20 compatible = "crystalfontz,cfa10049", "crystalfontz,cfa10036", "fsl,imx28";
21
22 apb@80000000 {
23 apbh@80000000 {
24 pinctrl@80018000 {
25 pinctrl-names = "default", "default";
26 pinctrl-1 = <&hog_pins_cfa10049>;
27
28 hog_pins_cfa10049: hog-10049@0 {
29 reg = <0>;
30 fsl,pinmux-ids = <
31 0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */
32 0x1163 /* MX28_PAD_LCD_D22__GPIO_1_22 */
33 0x1173 /* MX28_PAD_LCD_D22__GPIO_1_23 */
34 0x2153 /* MX28_PAD_SSP2_D5__GPIO_2_21 */
35 >;
36 fsl,drive-strength = <0>;
37 fsl,voltage = <1>;
38 fsl,pull-up = <0>;
39 };
40
41 spi3_pins_cfa10049: spi3-cfa10049@0 {
42 reg = <0>;
43 fsl,pinmux-ids = <
44 0x0181 /* MX28_PAD_GPMI_RDN__SSP3_SCK */
45 0x01c1 /* MX28_PAD_GPMI_RESETN__SSP3_CMD */
46 0x0111 /* MX28_PAD_GPMI_CE1N__SSP3_D3 */
47 0x01a2 /* MX28_PAD_GPMI_ALE__SSP3_D4 */
48 0x01b2 /* MX28_PAD_GPMI_CLE__SSP3_D5 */
49 >;
50 fsl,drive-strength = <1>;
51 fsl,voltage = <1>;
52 fsl,pull-up = <1>;
53 };
54 };
55
56 ssp3: ssp@80016000 {
57 compatible = "fsl,imx28-spi";
58 pinctrl-names = "default";
59 pinctrl-0 = <&spi3_pins_cfa10049>;
60 status = "okay";
61
62 gpio5: gpio5@0 {
63 compatible = "fairchild,74hc595";
64 gpio-controller;
65 #gpio-cells = <2>;
66 reg = <0>;
67 registers-number = <2>;
68 spi-max-frequency = <100000>;
69 };
70
71 gpio6: gpio6@1 {
72 compatible = "fairchild,74hc595";
73 gpio-controller;
74 #gpio-cells = <2>;
75 reg = <1>;
76 registers-number = <4>;
77 spi-max-frequency = <100000>;
78 };
79
80 dac0: dh2228@2 {
81 compatible = "rohm,dh2228fv";
82 reg = <2>;
83 spi-max-frequency = <100000>;
84 };
85 };
86 };
87
88 apbx@80040000 {
89 i2c1: i2c@8005a000 {
90 pinctrl-names = "default";
91 pinctrl-0 = <&i2c1_pins_a>;
92 status = "okay";
93 };
94
95 i2cmux {
96 compatible = "i2c-mux-gpio";
97 #address-cells = <1>;
98 #size-cells = <0>;
99 mux-gpios = <&gpio1 22 0 &gpio1 23 0>;
100 i2c-parent = <&i2c1>;
101
102 i2c@0 {
103 reg = <0>;
104 };
105
106 i2c@1 {
107 reg = <1>;
108 };
109
110 i2c@2 {
111 reg = <2>;
112 };
113
114 i2c@3 {
115 reg = <3>;
116 };
117 };
118
119 usbphy1: usbphy@8007e000 {
120 status = "okay";
121 };
122 };
123 };
124
125 ahb@80080000 {
126 usb1: usb@80090000 {
127 vbus-supply = <&reg_usb1_vbus>;
128 pinctrl-0 = <&usbphy1_pins_a>;
129 pinctrl-names = "default";
130 status = "okay";
131 };
132 };
133
134 regulators {
135 compatible = "simple-bus";
136
137 reg_usb1_vbus: usb1_vbus {
138 compatible = "regulator-fixed";
139 regulator-name = "usb1_vbus";
140 regulator-min-microvolt = <5000000>;
141 regulator-max-microvolt = <5000000>;
142 gpio = <&gpio0 7 1>;
143 };
144 };
145
146 ahb@80080000 {
147 mac0: ethernet@800f0000 {
148 phy-mode = "rmii";
149 pinctrl-names = "default";
150 pinctrl-0 = <&mac0_pins_a>;
151 phy-reset-gpios = <&gpio2 21 0>;
152 phy-reset-duration = <100>;
153 status = "okay";
154 };
155 };
156};
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
deleted file mode 100644
index 2da316e0440..00000000000
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ /dev/null
@@ -1,316 +0,0 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "imx28.dtsi"
14
15/ {
16 model = "Freescale i.MX28 Evaluation Kit";
17 compatible = "fsl,imx28-evk", "fsl,imx28";
18
19 memory {
20 reg = <0x40000000 0x08000000>;
21 };
22
23 apb@80000000 {
24 apbh@80000000 {
25 gpmi-nand@8000c000 {
26 pinctrl-names = "default";
27 pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg
28 &gpmi_pins_evk>;
29 status = "okay";
30 };
31
32 ssp0: ssp@80010000 {
33 compatible = "fsl,imx28-mmc";
34 pinctrl-names = "default";
35 pinctrl-0 = <&mmc0_8bit_pins_a
36 &mmc0_cd_cfg &mmc0_sck_cfg>;
37 bus-width = <8>;
38 wp-gpios = <&gpio2 12 0>;
39 vmmc-supply = <&reg_vddio_sd0>;
40 status = "okay";
41 };
42
43 ssp1: ssp@80012000 {
44 compatible = "fsl,imx28-mmc";
45 bus-width = <8>;
46 wp-gpios = <&gpio0 28 0>;
47 };
48
49 ssp2: ssp@80014000 {
50 #address-cells = <1>;
51 #size-cells = <0>;
52 compatible = "fsl,imx28-spi";
53 pinctrl-names = "default";
54 pinctrl-0 = <&spi2_pins_a>;
55 status = "okay";
56
57 flash: m25p80@0 {
58 #address-cells = <1>;
59 #size-cells = <1>;
60 compatible = "sst,sst25vf016b";
61 spi-max-frequency = <40000000>;
62 reg = <0>;
63 };
64 };
65
66 pinctrl@80018000 {
67 pinctrl-names = "default";
68 pinctrl-0 = <&hog_pins_a>;
69
70 hog_pins_a: hog@0 {
71 reg = <0>;
72 fsl,pinmux-ids = <
73 0x20d3 /* MX28_PAD_SSP1_CMD__GPIO_2_13 */
74 0x20f3 /* MX28_PAD_SSP1_DATA3__GPIO_2_15 */
75 0x40d3 /* MX28_PAD_ENET0_RX_CLK__GPIO_4_13 */
76 0x20c3 /* MX28_PAD_SSP1_SCK__GPIO_2_12 */
77 0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */
78 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */
79 0x3083 /* MX28_PAD_AUART2_RX__GPIO_3_8 */
80 0x3093 /* MX28_PAD_AUART2_TX__GPIO_3_9 */
81 >;
82 fsl,drive-strength = <0>;
83 fsl,voltage = <1>;
84 fsl,pull-up = <0>;
85 };
86
87 led_pin_gpio3_5: led_gpio3_5@0 {
88 reg = <0>;
89 fsl,pinmux-ids = <
90 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */
91 >;
92 fsl,drive-strength = <0>;
93 fsl,voltage = <1>;
94 fsl,pull-up = <0>;
95 };
96
97 gpmi_pins_evk: gpmi-nand-evk@0 {
98 reg = <0>;
99 fsl,pinmux-ids = <
100 0x0110 /* MX28_PAD_GPMI_CE1N__GPMI_CE1N */
101 0x0150 /* MX28_PAD_GPMI_RDY1__GPMI_READY1 */
102 >;
103 fsl,drive-strength = <0>;
104 fsl,voltage = <1>;
105 fsl,pull-up = <0>;
106 };
107
108 lcdif_pins_evk: lcdif-evk@0 {
109 reg = <0>;
110 fsl,pinmux-ids = <
111 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */
112 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */
113 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */
114 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */
115 >;
116 fsl,drive-strength = <0>;
117 fsl,voltage = <1>;
118 fsl,pull-up = <0>;
119 };
120 };
121
122 lcdif@80030000 {
123 pinctrl-names = "default";
124 pinctrl-0 = <&lcdif_24bit_pins_a
125 &lcdif_pins_evk>;
126 panel-enable-gpios = <&gpio3 30 0>;
127 status = "okay";
128 };
129
130 can0: can@80032000 {
131 pinctrl-names = "default";
132 pinctrl-0 = <&can0_pins_a>;
133 status = "okay";
134 };
135
136 can1: can@80034000 {
137 pinctrl-names = "default";
138 pinctrl-0 = <&can1_pins_a>;
139 status = "okay";
140 };
141 };
142
143 apbx@80040000 {
144 saif0: saif@80042000 {
145 pinctrl-names = "default";
146 pinctrl-0 = <&saif0_pins_a>;
147 status = "okay";
148 };
149
150 saif1: saif@80046000 {
151 pinctrl-names = "default";
152 pinctrl-0 = <&saif1_pins_a>;
153 fsl,saif-master = <&saif0>;
154 status = "okay";
155 };
156
157 lradc@80050000 {
158 status = "okay";
159 };
160
161 i2c0: i2c@80058000 {
162 pinctrl-names = "default";
163 pinctrl-0 = <&i2c0_pins_a>;
164 status = "okay";
165
166 sgtl5000: codec@0a {
167 compatible = "fsl,sgtl5000";
168 reg = <0x0a>;
169 VDDA-supply = <&reg_3p3v>;
170 VDDIO-supply = <&reg_3p3v>;
171
172 };
173
174 at24@51 {
175 compatible = "at24,24c32";
176 pagesize = <32>;
177 reg = <0x51>;
178 };
179 };
180
181 pwm: pwm@80064000 {
182 pinctrl-names = "default";
183 pinctrl-0 = <&pwm2_pins_a>;
184 status = "okay";
185 };
186
187 duart: serial@80074000 {
188 pinctrl-names = "default";
189 pinctrl-0 = <&duart_pins_a>;
190 status = "okay";
191 };
192
193 auart0: serial@8006a000 {
194 pinctrl-names = "default";
195 pinctrl-0 = <&auart0_pins_a>;
196 status = "okay";
197 };
198
199 auart3: serial@80070000 {
200 pinctrl-names = "default";
201 pinctrl-0 = <&auart3_pins_a>;
202 status = "okay";
203 };
204
205 usbphy0: usbphy@8007c000 {
206 status = "okay";
207 };
208
209 usbphy1: usbphy@8007e000 {
210 status = "okay";
211 };
212 };
213 };
214
215 ahb@80080000 {
216 usb0: usb@80080000 {
217 vbus-supply = <&reg_usb0_vbus>;
218 status = "okay";
219 };
220
221 usb1: usb@80090000 {
222 vbus-supply = <&reg_usb1_vbus>;
223 status = "okay";
224 };
225
226 mac0: ethernet@800f0000 {
227 phy-mode = "rmii";
228 pinctrl-names = "default";
229 pinctrl-0 = <&mac0_pins_a>;
230 phy-supply = <&reg_fec_3v3>;
231 phy-reset-gpios = <&gpio4 13 0>;
232 phy-reset-duration = <100>;
233 status = "okay";
234 };
235
236 mac1: ethernet@800f4000 {
237 phy-mode = "rmii";
238 pinctrl-names = "default";
239 pinctrl-0 = <&mac1_pins_a>;
240 status = "okay";
241 };
242 };
243
244 regulators {
245 compatible = "simple-bus";
246
247 reg_3p3v: 3p3v {
248 compatible = "regulator-fixed";
249 regulator-name = "3P3V";
250 regulator-min-microvolt = <3300000>;
251 regulator-max-microvolt = <3300000>;
252 regulator-always-on;
253 };
254
255 reg_vddio_sd0: vddio-sd0 {
256 compatible = "regulator-fixed";
257 regulator-name = "vddio-sd0";
258 regulator-min-microvolt = <3300000>;
259 regulator-max-microvolt = <3300000>;
260 gpio = <&gpio3 28 0>;
261 };
262
263 reg_fec_3v3: fec-3v3 {
264 compatible = "regulator-fixed";
265 regulator-name = "fec-3v3";
266 regulator-min-microvolt = <3300000>;
267 regulator-max-microvolt = <3300000>;
268 gpio = <&gpio2 15 0>;
269 };
270
271 reg_usb0_vbus: usb0_vbus {
272 compatible = "regulator-fixed";
273 regulator-name = "usb0_vbus";
274 regulator-min-microvolt = <5000000>;
275 regulator-max-microvolt = <5000000>;
276 gpio = <&gpio3 9 0>;
277 enable-active-high;
278 };
279
280 reg_usb1_vbus: usb1_vbus {
281 compatible = "regulator-fixed";
282 regulator-name = "usb1_vbus";
283 regulator-min-microvolt = <5000000>;
284 regulator-max-microvolt = <5000000>;
285 gpio = <&gpio3 8 0>;
286 enable-active-high;
287 };
288 };
289
290 sound {
291 compatible = "fsl,imx28-evk-sgtl5000",
292 "fsl,mxs-audio-sgtl5000";
293 model = "imx28-evk-sgtl5000";
294 saif-controllers = <&saif0 &saif1>;
295 audio-codec = <&sgtl5000>;
296 };
297
298 leds {
299 compatible = "gpio-leds";
300 pinctrl-names = "default";
301 pinctrl-0 = <&led_pin_gpio3_5>;
302
303 user {
304 label = "Heartbeat";
305 gpios = <&gpio3 5 0>;
306 linux,default-trigger = "heartbeat";
307 };
308 };
309
310 backlight {
311 compatible = "pwm-backlight";
312 pwms = <&pwm 2 5000000>;
313 brightness-levels = <0 4 8 16 32 64 128 255>;
314 default-brightness-level = <6>;
315 };
316};
diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts
deleted file mode 100644
index 3bab6b00c52..00000000000
--- a/arch/arm/boot/dts/imx28-m28evk.dts
+++ /dev/null
@@ -1,277 +0,0 @@
1/*
2 * Copyright (C) 2012 Marek Vasut <marex@denx.de>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "imx28.dtsi"
14
15/ {
16 model = "DENX M28EVK";
17 compatible = "denx,m28evk", "fsl,imx28";
18
19 memory {
20 reg = <0x40000000 0x08000000>;
21 };
22
23 apb@80000000 {
24 apbh@80000000 {
25 gpmi-nand@8000c000 {
26 #address-cells = <1>;
27 #size-cells = <1>;
28 pinctrl-names = "default";
29 pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
30 status = "okay";
31
32 partition@0 {
33 label = "bootloader";
34 reg = <0x00000000 0x00300000>;
35 read-only;
36 };
37
38 partition@1 {
39 label = "environment";
40 reg = <0x00300000 0x00080000>;
41 };
42
43 partition@2 {
44 label = "redundant-environment";
45 reg = <0x00380000 0x00080000>;
46 };
47
48 partition@3 {
49 label = "kernel";
50 reg = <0x00400000 0x00400000>;
51 };
52
53 partition@4 {
54 label = "filesystem";
55 reg = <0x00800000 0x0f800000>;
56 };
57 };
58
59 ssp0: ssp@80010000 {
60 compatible = "fsl,imx28-mmc";
61 pinctrl-names = "default";
62 pinctrl-0 = <&mmc0_8bit_pins_a
63 &mmc0_cd_cfg
64 &mmc0_sck_cfg>;
65 bus-width = <8>;
66 wp-gpios = <&gpio3 10 0>;
67 vmmc-supply = <&reg_vddio_sd0>;
68 status = "okay";
69 };
70
71 ssp2: ssp@80014000 {
72 #address-cells = <1>;
73 #size-cells = <0>;
74 compatible = "fsl,imx28-spi";
75 pinctrl-names = "default";
76 pinctrl-0 = <&spi2_pins_a>;
77 status = "okay";
78
79 flash: m25p80@0 {
80 #address-cells = <1>;
81 #size-cells = <1>;
82 compatible = "m25p80";
83 spi-max-frequency = <40000000>;
84 reg = <0>;
85 };
86 };
87
88 pinctrl@80018000 {
89 pinctrl-names = "default";
90 pinctrl-0 = <&hog_pins_a>;
91
92 hog_pins_a: hog@0 {
93 reg = <0>;
94 fsl,pinmux-ids = <
95 0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */
96 0x30a3 /* MX28_PAD_AUART2_CTS__GPIO_3_10 */
97 0x30b3 /* MX28_PAD_AUART2_RTS__GPIO_3_11 */
98 0x30c3 /* MX28_PAD_AUART3_RX__GPIO_3_12 */
99 0x30d3 /* MX28_PAD_AUART3_TX__GPIO_3_13 */
100 >;
101 fsl,drive-strength = <0>;
102 fsl,voltage = <1>;
103 fsl,pull-up = <0>;
104 };
105
106 lcdif_pins_m28: lcdif-m28@0 {
107 reg = <0>;
108 fsl,pinmux-ids = <
109 0x11e0 /* MX28_PAD_LCD_DOTCLK__LCD_DOTCLK */
110 0x11f0 /* MX28_PAD_LCD_ENABLE__LCD_ENABLE */
111 >;
112 fsl,drive-strength = <0>;
113 fsl,voltage = <1>;
114 fsl,pull-up = <0>;
115 };
116 };
117
118 lcdif@80030000 {
119 pinctrl-names = "default";
120 pinctrl-0 = <&lcdif_24bit_pins_a
121 &lcdif_pins_m28>;
122 status = "okay";
123 };
124
125 can0: can@80032000 {
126 pinctrl-names = "default";
127 pinctrl-0 = <&can0_pins_a>;
128 status = "okay";
129 };
130
131 can1: can@80034000 {
132 pinctrl-names = "default";
133 pinctrl-0 = <&can1_pins_a>;
134 status = "okay";
135 };
136 };
137
138 apbx@80040000 {
139 saif0: saif@80042000 {
140 pinctrl-names = "default";
141 pinctrl-0 = <&saif0_pins_a>;
142 status = "okay";
143 };
144
145 saif1: saif@80046000 {
146 pinctrl-names = "default";
147 pinctrl-0 = <&saif1_pins_a>;
148 fsl,saif-master = <&saif0>;
149 status = "okay";
150 };
151
152 i2c0: i2c@80058000 {
153 pinctrl-names = "default";
154 pinctrl-0 = <&i2c0_pins_a>;
155 clock-frequency = <400000>;
156 status = "okay";
157
158 sgtl5000: codec@0a {
159 compatible = "fsl,sgtl5000";
160 reg = <0x0a>;
161 VDDA-supply = <&reg_3p3v>;
162 VDDIO-supply = <&reg_3p3v>;
163
164 };
165
166 eeprom: eeprom@51 {
167 compatible = "atmel,24c128";
168 reg = <0x51>;
169 pagesize = <32>;
170 };
171
172 rtc: rtc@68 {
173 compatible = "stm,mt41t62";
174 reg = <0x68>;
175 };
176 };
177
178 lradc@80050000 {
179 status = "okay";
180 };
181
182 duart: serial@80074000 {
183 pinctrl-names = "default";
184 pinctrl-0 = <&duart_pins_a>;
185 status = "okay";
186 };
187
188 usbphy0: usbphy@8007c000 {
189 status = "okay";
190 };
191
192 usbphy1: usbphy@8007e000 {
193 status = "okay";
194 };
195
196 auart0: serial@8006a000 {
197 pinctrl-names = "default";
198 pinctrl-0 = <&auart0_2pins_a>;
199 status = "okay";
200 };
201 };
202 };
203
204 ahb@80080000 {
205 usb0: usb@80080000 {
206 vbus-supply = <&reg_usb0_vbus>;
207 pinctrl-names = "default";
208 pinctrl-0 = <&usbphy0_pins_a>;
209 status = "okay";
210 };
211
212 usb1: usb@80090000 {
213 vbus-supply = <&reg_usb1_vbus>;
214 pinctrl-names = "default";
215 pinctrl-0 = <&usbphy1_pins_a>;
216 status = "okay";
217 };
218
219 mac0: ethernet@800f0000 {
220 phy-mode = "rmii";
221 pinctrl-names = "default";
222 pinctrl-0 = <&mac0_pins_a>;
223 status = "okay";
224 };
225
226 mac1: ethernet@800f4000 {
227 phy-mode = "rmii";
228 pinctrl-names = "default";
229 pinctrl-0 = <&mac1_pins_a>;
230 status = "okay";
231 };
232 };
233
234 regulators {
235 compatible = "simple-bus";
236
237 reg_3p3v: 3p3v {
238 compatible = "regulator-fixed";
239 regulator-name = "3P3V";
240 regulator-min-microvolt = <3300000>;
241 regulator-max-microvolt = <3300000>;
242 regulator-always-on;
243 };
244
245 reg_vddio_sd0: vddio-sd0 {
246 compatible = "regulator-fixed";
247 regulator-name = "vddio-sd0";
248 regulator-min-microvolt = <3300000>;
249 regulator-max-microvolt = <3300000>;
250 gpio = <&gpio3 28 0>;
251 };
252
253 reg_usb0_vbus: usb0_vbus {
254 compatible = "regulator-fixed";
255 regulator-name = "usb0_vbus";
256 regulator-min-microvolt = <5000000>;
257 regulator-max-microvolt = <5000000>;
258 gpio = <&gpio3 12 0>;
259 };
260
261 reg_usb1_vbus: usb1_vbus {
262 compatible = "regulator-fixed";
263 regulator-name = "usb1_vbus";
264 regulator-min-microvolt = <5000000>;
265 regulator-max-microvolt = <5000000>;
266 gpio = <&gpio3 13 0>;
267 };
268 };
269
270 sound {
271 compatible = "denx,m28evk-sgtl5000",
272 "fsl,mxs-audio-sgtl5000";
273 model = "m28evk-sgtl5000";
274 saif-controllers = <&saif0 &saif1>;
275 audio-codec = <&sgtl5000>;
276 };
277};
diff --git a/arch/arm/boot/dts/imx28-sps1.dts b/arch/arm/boot/dts/imx28-sps1.dts
deleted file mode 100644
index e6cde8aa7ff..00000000000
--- a/arch/arm/boot/dts/imx28-sps1.dts
+++ /dev/null
@@ -1,169 +0,0 @@
1/*
2 * Copyright (C) 2012 Marek Vasut <marex@denx.de>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "imx28.dtsi"
14
15/ {
16 model = "SchulerControl GmbH, SC SPS 1";
17 compatible = "schulercontrol,imx28-sps1", "fsl,imx28";
18
19 memory {
20 reg = <0x40000000 0x08000000>;
21 };
22
23 apb@80000000 {
24 apbh@80000000 {
25 pinctrl@80018000 {
26 pinctrl-names = "default";
27 pinctrl-0 = <&hog_pins_a>;
28
29 hog_pins_a: hog-gpios@0 {
30 reg = <0>;
31 fsl,pinmux-ids = <
32 0x0003 /* MX28_PAD_GPMI_D00__GPIO_0_0 */
33 0x0033 /* MX28_PAD_GPMI_D03__GPIO_0_3 */
34 0x0063 /* MX28_PAD_GPMI_D06__GPIO_0_6 */
35 >;
36 fsl,drive-strength = <0>;
37 fsl,voltage = <1>;
38 fsl,pull-up = <0>;
39 };
40
41 };
42
43 ssp0: ssp@80010000 {
44 compatible = "fsl,imx28-mmc";
45 pinctrl-names = "default";
46 pinctrl-0 = <&mmc0_4bit_pins_a>;
47 bus-width = <4>;
48 status = "okay";
49 };
50
51 ssp2: ssp@80014000 {
52 #address-cells = <1>;
53 #size-cells = <0>;
54 compatible = "fsl,imx28-spi";
55 pinctrl-names = "default";
56 pinctrl-0 = <&spi2_pins_a>;
57 status = "okay";
58
59 flash: m25p80@0 {
60 #address-cells = <1>;
61 #size-cells = <1>;
62 compatible = "everspin,mr25h256", "mr25h256";
63 spi-max-frequency = <40000000>;
64 reg = <0>;
65 };
66 };
67 };
68
69 apbx@80040000 {
70 i2c0: i2c@80058000 {
71 pinctrl-names = "default";
72 pinctrl-0 = <&i2c0_pins_a>;
73 clock-frequency = <400000>;
74 status = "okay";
75
76 rtc: rtc@51 {
77 compatible = "nxp,pcf8563";
78 reg = <0x51>;
79 };
80
81 eeprom: eeprom@52 {
82 compatible = "atmel,24c64";
83 reg = <0x52>;
84 pagesize = <32>;
85 };
86 };
87
88 duart: serial@80074000 {
89 pinctrl-names = "default";
90 pinctrl-0 = <&duart_pins_a>;
91 status = "okay";
92 };
93
94 usbphy0: usbphy@8007c000 {
95 status = "okay";
96 };
97
98 auart0: serial@8006a000 {
99 pinctrl-names = "default";
100 pinctrl-0 = <&auart0_pins_a>;
101 status = "okay";
102 };
103 };
104 };
105
106 ahb@80080000 {
107 usb0: usb@80080000 {
108 vbus-supply = <&reg_usb0_vbus>;
109 pinctrl-names = "default";
110 pinctrl-0 = <&usbphy0_pins_b>;
111 status = "okay";
112 };
113
114 mac0: ethernet@800f0000 {
115 phy-mode = "rmii";
116 pinctrl-names = "default";
117 pinctrl-0 = <&mac0_pins_a>;
118 status = "okay";
119 };
120
121 mac1: ethernet@800f4000 {
122 phy-mode = "rmii";
123 pinctrl-names = "default";
124 pinctrl-0 = <&mac1_pins_a>;
125 status = "okay";
126 };
127 };
128
129 regulators {
130 compatible = "simple-bus";
131
132 reg_usb0_vbus: usb0_vbus {
133 compatible = "regulator-fixed";
134 regulator-name = "usb0_vbus";
135 regulator-min-microvolt = <5000000>;
136 regulator-max-microvolt = <5000000>;
137 gpio = <&gpio3 9 0>;
138 };
139 };
140
141 leds {
142 #address-cells = <1>;
143 #size-cells = <0>;
144 compatible = "gpio-leds";
145 status = "okay";
146
147 led@1 {
148 label = "sps1-1:yellow:user";
149 gpios = <&gpio0 6 0>;
150 linux,default-trigger = "heartbeat";
151 reg = <0>;
152 };
153
154 led@2 {
155 label = "sps1-2:red:user";
156 gpios = <&gpio0 3 0>;
157 linux,default-trigger = "heartbeat";
158 reg = <1>;
159 };
160
161 led@3 {
162 label = "sps1-3:red:user";
163 gpios = <&gpio0 0 0>;
164 default-trigger = "heartbeat";
165 reg = <2>;
166 };
167
168 };
169};
diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts
deleted file mode 100644
index 37be532f005..00000000000
--- a/arch/arm/boot/dts/imx28-tx28.dts
+++ /dev/null
@@ -1,116 +0,0 @@
1/dts-v1/;
2/include/ "imx28.dtsi"
3
4/ {
5 model = "Ka-Ro electronics TX28 module";
6 compatible = "karo,tx28", "fsl,imx28";
7
8 memory {
9 reg = <0x40000000 0x08000000>;
10 };
11
12 apb@80000000 {
13 apbh@80000000 {
14 ssp0: ssp@80010000 {
15 compatible = "fsl,imx28-mmc";
16 pinctrl-names = "default";
17 pinctrl-0 = <&mmc0_4bit_pins_a
18 &mmc0_cd_cfg
19 &mmc0_sck_cfg>;
20 bus-width = <4>;
21 status = "okay";
22 };
23
24 pinctrl@80018000 {
25 pinctrl-names = "default";
26 pinctrl-0 = <&hog_pins_a>;
27
28 hog_pins_a: hog@0 {
29 reg = <0>;
30 fsl,pinmux-ids = <
31 0x40a3 /* MX28_PAD_ENET0_RXD3__GPIO_4_10 */
32 >;
33 fsl,drive-strength = <0>;
34 fsl,voltage = <1>;
35 fsl,pull-up = <0>;
36 };
37
38 mac0_pins_gpio: mac0-gpio-mode@0 {
39 reg = <0>;
40 fsl,pinmux-ids = <
41 0x4003 /* MX28_PAD_ENET0_MDC__GPIO_4_0 */
42 0x4013 /* MX28_PAD_ENET0_MDIO__GPIO_4_1 */
43 0x4023 /* MX28_PAD_ENET0_RX_EN__GPIO_4_2 */
44 0x4033 /* MX28_PAD_ENET0_RXD0__GPIO_4_3 */
45 0x4043 /* MX28_PAD_ENET0_RXD1__GPIO_4_4 */
46 0x4063 /* MX28_PAD_ENET0_TX_EN__GPIO_4_6 */
47 0x4073 /* MX28_PAD_ENET0_TXD0__GPIO_4_7 */
48 0x4083 /* MX28_PAD_ENET0_TXD1__GPIO_4_8 */
49 0x4103 /* MX28_PAD_ENET_CLK__GPIO_4_16 */
50 >;
51 fsl,drive-strength = <0>;
52 fsl,voltage = <1>;
53 fsl,pull-up = <0>;
54 };
55 };
56 };
57
58 apbx@80040000 {
59 i2c0: i2c@80058000 {
60 pinctrl-names = "default";
61 pinctrl-0 = <&i2c0_pins_a>;
62 status = "okay";
63
64 ds1339: rtc@68 {
65 compatible = "mxim,ds1339";
66 reg = <0x68>;
67 };
68 };
69
70 pwm: pwm@80064000 {
71 pinctrl-names = "default";
72 pinctrl-0 = <&pwm0_pins_a>;
73 status = "okay";
74 };
75
76 duart: serial@80074000 {
77 pinctrl-names = "default";
78 pinctrl-0 = <&duart_4pins_a>;
79 status = "okay";
80 };
81
82 auart1: serial@8006c000 {
83 pinctrl-names = "default";
84 pinctrl-0 = <&auart1_pins_a>;
85 status = "okay";
86 };
87 };
88 };
89
90 ahb@80080000 {
91 mac0: ethernet@800f0000 {
92 phy-mode = "rmii";
93 pinctrl-names = "default", "gpio_mode";
94 pinctrl-0 = <&mac0_pins_a>;
95 pinctrl-1 = <&mac0_pins_gpio>;
96 status = "okay";
97 };
98 };
99
100 leds {
101 compatible = "gpio-leds";
102
103 user {
104 label = "Heartbeat";
105 gpios = <&gpio4 10 0>;
106 linux,default-trigger = "heartbeat";
107 };
108 };
109
110 backlight {
111 compatible = "pwm-backlight";
112 pwms = <&pwm 0 5000000>;
113 brightness-levels = <0 4 8 16 32 64 128 255>;
114 default-brightness-level = <6>;
115 };
116};
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
deleted file mode 100644
index 13b7053d799..00000000000
--- a/arch/arm/boot/dts/imx28.dtsi
+++ /dev/null
@@ -1,953 +0,0 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 interrupt-parent = <&icoll>;
16
17 aliases {
18 gpio0 = &gpio0;
19 gpio1 = &gpio1;
20 gpio2 = &gpio2;
21 gpio3 = &gpio3;
22 gpio4 = &gpio4;
23 saif0 = &saif0;
24 saif1 = &saif1;
25 serial0 = &auart0;
26 serial1 = &auart1;
27 serial2 = &auart2;
28 serial3 = &auart3;
29 serial4 = &auart4;
30 ethernet0 = &mac0;
31 ethernet1 = &mac1;
32 };
33
34 cpus {
35 cpu@0 {
36 compatible = "arm,arm926ejs";
37 };
38 };
39
40 apb@80000000 {
41 compatible = "simple-bus";
42 #address-cells = <1>;
43 #size-cells = <1>;
44 reg = <0x80000000 0x80000>;
45 ranges;
46
47 apbh@80000000 {
48 compatible = "simple-bus";
49 #address-cells = <1>;
50 #size-cells = <1>;
51 reg = <0x80000000 0x3c900>;
52 ranges;
53
54 icoll: interrupt-controller@80000000 {
55 compatible = "fsl,imx28-icoll", "fsl,icoll";
56 interrupt-controller;
57 #interrupt-cells = <1>;
58 reg = <0x80000000 0x2000>;
59 };
60
61 hsadc@80002000 {
62 reg = <0x80002000 0x2000>;
63 interrupts = <13 87>;
64 status = "disabled";
65 };
66
67 dma-apbh@80004000 {
68 compatible = "fsl,imx28-dma-apbh";
69 reg = <0x80004000 0x2000>;
70 clocks = <&clks 25>;
71 };
72
73 perfmon@80006000 {
74 reg = <0x80006000 0x800>;
75 interrupts = <27>;
76 status = "disabled";
77 };
78
79 gpmi-nand@8000c000 {
80 compatible = "fsl,imx28-gpmi-nand";
81 #address-cells = <1>;
82 #size-cells = <1>;
83 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
84 reg-names = "gpmi-nand", "bch";
85 interrupts = <88>, <41>;
86 interrupt-names = "gpmi-dma", "bch";
87 clocks = <&clks 50>;
88 clock-names = "gpmi_io";
89 fsl,gpmi-dma-channel = <4>;
90 status = "disabled";
91 };
92
93 ssp0: ssp@80010000 {
94 #address-cells = <1>;
95 #size-cells = <0>;
96 reg = <0x80010000 0x2000>;
97 interrupts = <96 82>;
98 clocks = <&clks 46>;
99 fsl,ssp-dma-channel = <0>;
100 status = "disabled";
101 };
102
103 ssp1: ssp@80012000 {
104 #address-cells = <1>;
105 #size-cells = <0>;
106 reg = <0x80012000 0x2000>;
107 interrupts = <97 83>;
108 clocks = <&clks 47>;
109 fsl,ssp-dma-channel = <1>;
110 status = "disabled";
111 };
112
113 ssp2: ssp@80014000 {
114 #address-cells = <1>;
115 #size-cells = <0>;
116 reg = <0x80014000 0x2000>;
117 interrupts = <98 84>;
118 clocks = <&clks 48>;
119 fsl,ssp-dma-channel = <2>;
120 status = "disabled";
121 };
122
123 ssp3: ssp@80016000 {
124 #address-cells = <1>;
125 #size-cells = <0>;
126 reg = <0x80016000 0x2000>;
127 interrupts = <99 85>;
128 clocks = <&clks 49>;
129 fsl,ssp-dma-channel = <3>;
130 status = "disabled";
131 };
132
133 pinctrl@80018000 {
134 #address-cells = <1>;
135 #size-cells = <0>;
136 compatible = "fsl,imx28-pinctrl", "simple-bus";
137 reg = <0x80018000 0x2000>;
138
139 gpio0: gpio@0 {
140 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
141 interrupts = <127>;
142 gpio-controller;
143 #gpio-cells = <2>;
144 interrupt-controller;
145 #interrupt-cells = <2>;
146 };
147
148 gpio1: gpio@1 {
149 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
150 interrupts = <126>;
151 gpio-controller;
152 #gpio-cells = <2>;
153 interrupt-controller;
154 #interrupt-cells = <2>;
155 };
156
157 gpio2: gpio@2 {
158 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
159 interrupts = <125>;
160 gpio-controller;
161 #gpio-cells = <2>;
162 interrupt-controller;
163 #interrupt-cells = <2>;
164 };
165
166 gpio3: gpio@3 {
167 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
168 interrupts = <124>;
169 gpio-controller;
170 #gpio-cells = <2>;
171 interrupt-controller;
172 #interrupt-cells = <2>;
173 };
174
175 gpio4: gpio@4 {
176 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
177 interrupts = <123>;
178 gpio-controller;
179 #gpio-cells = <2>;
180 interrupt-controller;
181 #interrupt-cells = <2>;
182 };
183
184 duart_pins_a: duart@0 {
185 reg = <0>;
186 fsl,pinmux-ids = <
187 0x3102 /* MX28_PAD_PWM0__DUART_RX */
188 0x3112 /* MX28_PAD_PWM1__DUART_TX */
189 >;
190 fsl,drive-strength = <0>;
191 fsl,voltage = <1>;
192 fsl,pull-up = <0>;
193 };
194
195 duart_pins_b: duart@1 {
196 reg = <1>;
197 fsl,pinmux-ids = <
198 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
199 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
200 >;
201 fsl,drive-strength = <0>;
202 fsl,voltage = <1>;
203 fsl,pull-up = <0>;
204 };
205
206 duart_4pins_a: duart-4pins@0 {
207 reg = <0>;
208 fsl,pinmux-ids = <
209 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
210 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
211 0x3002 /* MX28_PAD_AUART0_RX__DUART_CTS */
212 0x3012 /* MX28_PAD_AUART0_TX__DUART_RTS */
213 >;
214 fsl,drive-strength = <0>;
215 fsl,voltage = <1>;
216 fsl,pull-up = <0>;
217 };
218
219 gpmi_pins_a: gpmi-nand@0 {
220 reg = <0>;
221 fsl,pinmux-ids = <
222 0x0000 /* MX28_PAD_GPMI_D00__GPMI_D0 */
223 0x0010 /* MX28_PAD_GPMI_D01__GPMI_D1 */
224 0x0020 /* MX28_PAD_GPMI_D02__GPMI_D2 */
225 0x0030 /* MX28_PAD_GPMI_D03__GPMI_D3 */
226 0x0040 /* MX28_PAD_GPMI_D04__GPMI_D4 */
227 0x0050 /* MX28_PAD_GPMI_D05__GPMI_D5 */
228 0x0060 /* MX28_PAD_GPMI_D06__GPMI_D6 */
229 0x0070 /* MX28_PAD_GPMI_D07__GPMI_D7 */
230 0x0100 /* MX28_PAD_GPMI_CE0N__GPMI_CE0N */
231 0x0140 /* MX28_PAD_GPMI_RDY0__GPMI_READY0 */
232 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
233 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
234 0x01a0 /* MX28_PAD_GPMI_ALE__GPMI_ALE */
235 0x01b0 /* MX28_PAD_GPMI_CLE__GPMI_CLE */
236 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
237 >;
238 fsl,drive-strength = <0>;
239 fsl,voltage = <1>;
240 fsl,pull-up = <0>;
241 };
242
243 gpmi_status_cfg: gpmi-status-cfg {
244 fsl,pinmux-ids = <
245 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
246 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
247 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
248 >;
249 fsl,drive-strength = <2>;
250 };
251
252 auart0_pins_a: auart0@0 {
253 reg = <0>;
254 fsl,pinmux-ids = <
255 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
256 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
257 0x3020 /* MX28_PAD_AUART0_CTS__AUART0_CTS */
258 0x3030 /* MX28_PAD_AUART0_RTS__AUART0_RTS */
259 >;
260 fsl,drive-strength = <0>;
261 fsl,voltage = <1>;
262 fsl,pull-up = <0>;
263 };
264
265 auart0_2pins_a: auart0-2pins@0 {
266 reg = <0>;
267 fsl,pinmux-ids = <
268 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
269 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
270 >;
271 fsl,drive-strength = <0>;
272 fsl,voltage = <1>;
273 fsl,pull-up = <0>;
274 };
275
276 auart1_pins_a: auart1@0 {
277 reg = <0>;
278 fsl,pinmux-ids = <
279 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
280 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
281 0x3060 /* MX28_PAD_AUART1_CTS__AUART1_CTS */
282 0x3070 /* MX28_PAD_AUART1_RTS__AUART1_RTS */
283 >;
284 fsl,drive-strength = <0>;
285 fsl,voltage = <1>;
286 fsl,pull-up = <0>;
287 };
288
289 auart1_2pins_a: auart1-2pins@0 {
290 reg = <0>;
291 fsl,pinmux-ids = <
292 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
293 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
294 >;
295 fsl,drive-strength = <0>;
296 fsl,voltage = <1>;
297 fsl,pull-up = <0>;
298 };
299
300 auart2_2pins_a: auart2-2pins@0 {
301 reg = <0>;
302 fsl,pinmux-ids = <
303 0x2101 /* MX28_PAD_SSP2_SCK__AUART2_RX */
304 0x2111 /* MX28_PAD_SSP2_MOSI__AUART2_TX */
305 >;
306 fsl,drive-strength = <0>;
307 fsl,voltage = <1>;
308 fsl,pull-up = <0>;
309 };
310
311 auart3_pins_a: auart3@0 {
312 reg = <0>;
313 fsl,pinmux-ids = <
314 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */
315 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */
316 0x30e0 /* MX28_PAD_AUART3_CTS__AUART3_CTS */
317 0x30f0 /* MX28_PAD_AUART3_RTS__AUART3_RTS */
318 >;
319 fsl,drive-strength = <0>;
320 fsl,voltage = <1>;
321 fsl,pull-up = <0>;
322 };
323
324 auart3_2pins_a: auart3-2pins@0 {
325 reg = <0>;
326 fsl,pinmux-ids = <
327 0x2121 /* MX28_PAD_SSP2_MISO__AUART3_RX */
328 0x2131 /* MX28_PAD_SSP2_SS0__AUART3_TX */
329 >;
330 fsl,drive-strength = <0>;
331 fsl,voltage = <1>;
332 fsl,pull-up = <0>;
333 };
334
335 mac0_pins_a: mac0@0 {
336 reg = <0>;
337 fsl,pinmux-ids = <
338 0x4000 /* MX28_PAD_ENET0_MDC__ENET0_MDC */
339 0x4010 /* MX28_PAD_ENET0_MDIO__ENET0_MDIO */
340 0x4020 /* MX28_PAD_ENET0_RX_EN__ENET0_RX_EN */
341 0x4030 /* MX28_PAD_ENET0_RXD0__ENET0_RXD0 */
342 0x4040 /* MX28_PAD_ENET0_RXD1__ENET0_RXD1 */
343 0x4060 /* MX28_PAD_ENET0_TX_EN__ENET0_TX_EN */
344 0x4070 /* MX28_PAD_ENET0_TXD0__ENET0_TXD0 */
345 0x4080 /* MX28_PAD_ENET0_TXD1__ENET0_TXD1 */
346 0x4100 /* MX28_PAD_ENET_CLK__CLKCTRL_ENET */
347 >;
348 fsl,drive-strength = <1>;
349 fsl,voltage = <1>;
350 fsl,pull-up = <1>;
351 };
352
353 mac1_pins_a: mac1@0 {
354 reg = <0>;
355 fsl,pinmux-ids = <
356 0x40f1 /* MX28_PAD_ENET0_CRS__ENET1_RX_EN */
357 0x4091 /* MX28_PAD_ENET0_RXD2__ENET1_RXD0 */
358 0x40a1 /* MX28_PAD_ENET0_RXD3__ENET1_RXD1 */
359 0x40e1 /* MX28_PAD_ENET0_COL__ENET1_TX_EN */
360 0x40b1 /* MX28_PAD_ENET0_TXD2__ENET1_TXD0 */
361 0x40c1 /* MX28_PAD_ENET0_TXD3__ENET1_TXD1 */
362 >;
363 fsl,drive-strength = <1>;
364 fsl,voltage = <1>;
365 fsl,pull-up = <1>;
366 };
367
368 mmc0_8bit_pins_a: mmc0-8bit@0 {
369 reg = <0>;
370 fsl,pinmux-ids = <
371 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
372 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
373 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
374 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
375 0x2040 /* MX28_PAD_SSP0_DATA4__SSP0_D4 */
376 0x2050 /* MX28_PAD_SSP0_DATA5__SSP0_D5 */
377 0x2060 /* MX28_PAD_SSP0_DATA6__SSP0_D6 */
378 0x2070 /* MX28_PAD_SSP0_DATA7__SSP0_D7 */
379 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
380 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
381 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
382 >;
383 fsl,drive-strength = <1>;
384 fsl,voltage = <1>;
385 fsl,pull-up = <1>;
386 };
387
388 mmc0_4bit_pins_a: mmc0-4bit@0 {
389 reg = <0>;
390 fsl,pinmux-ids = <
391 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
392 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
393 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
394 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
395 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
396 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
397 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
398 >;
399 fsl,drive-strength = <1>;
400 fsl,voltage = <1>;
401 fsl,pull-up = <1>;
402 };
403
404 mmc0_cd_cfg: mmc0-cd-cfg {
405 fsl,pinmux-ids = <
406 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
407 >;
408 fsl,pull-up = <0>;
409 };
410
411 mmc0_sck_cfg: mmc0-sck-cfg {
412 fsl,pinmux-ids = <
413 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
414 >;
415 fsl,drive-strength = <2>;
416 fsl,pull-up = <0>;
417 };
418
419 i2c0_pins_a: i2c0@0 {
420 reg = <0>;
421 fsl,pinmux-ids = <
422 0x3180 /* MX28_PAD_I2C0_SCL__I2C0_SCL */
423 0x3190 /* MX28_PAD_I2C0_SDA__I2C0_SDA */
424 >;
425 fsl,drive-strength = <1>;
426 fsl,voltage = <1>;
427 fsl,pull-up = <1>;
428 };
429
430 i2c0_pins_b: i2c0@1 {
431 reg = <1>;
432 fsl,pinmux-ids = <
433 0x3001 /* MX28_PAD_AUART0_RX__I2C0_SCL */
434 0x3011 /* MX28_PAD_AUART0_TX__I2C0_SDA */
435 >;
436 fsl,drive-strength = <1>;
437 fsl,voltage = <1>;
438 fsl,pull-up = <1>;
439 };
440
441 i2c1_pins_a: i2c1@0 {
442 reg = <0>;
443 fsl,pinmux-ids = <
444 0x3101 /* MX28_PAD_PWM0__I2C1_SCL */
445 0x3111 /* MX28_PAD_PWM1__I2C1_SDA */
446 >;
447 fsl,drive-strength = <1>;
448 fsl,voltage = <1>;
449 fsl,pull-up = <1>;
450 };
451
452 saif0_pins_a: saif0@0 {
453 reg = <0>;
454 fsl,pinmux-ids = <
455 0x3140 /* MX28_PAD_SAIF0_MCLK__SAIF0_MCLK */
456 0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */
457 0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */
458 0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */
459 >;
460 fsl,drive-strength = <2>;
461 fsl,voltage = <1>;
462 fsl,pull-up = <1>;
463 };
464
465 saif1_pins_a: saif1@0 {
466 reg = <0>;
467 fsl,pinmux-ids = <
468 0x31a0 /* MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 */
469 >;
470 fsl,drive-strength = <2>;
471 fsl,voltage = <1>;
472 fsl,pull-up = <1>;
473 };
474
475 pwm0_pins_a: pwm0@0 {
476 reg = <0>;
477 fsl,pinmux-ids = <
478 0x3100 /* MX28_PAD_PWM0__PWM_0 */
479 >;
480 fsl,drive-strength = <0>;
481 fsl,voltage = <1>;
482 fsl,pull-up = <0>;
483 };
484
485 pwm2_pins_a: pwm2@0 {
486 reg = <0>;
487 fsl,pinmux-ids = <
488 0x3120 /* MX28_PAD_PWM2__PWM_2 */
489 >;
490 fsl,drive-strength = <0>;
491 fsl,voltage = <1>;
492 fsl,pull-up = <0>;
493 };
494
495 pwm3_pins_a: pwm3@0 {
496 reg = <0>;
497 fsl,pinmux-ids = <
498 0x31c0 /* MX28_PAD_PWM3__PWM_3 */
499 >;
500 fsl,drive-strength = <0>;
501 fsl,voltage = <1>;
502 fsl,pull-up = <0>;
503 };
504
505 pwm4_pins_a: pwm4@0 {
506 reg = <0>;
507 fsl,pinmux-ids = <
508 0x31d0 /* MX28_PAD_PWM4__PWM_4 */
509 >;
510 fsl,drive-strength = <0>;
511 fsl,voltage = <1>;
512 fsl,pull-up = <0>;
513 };
514
515 lcdif_24bit_pins_a: lcdif-24bit@0 {
516 reg = <0>;
517 fsl,pinmux-ids = <
518 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
519 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
520 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
521 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
522 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
523 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
524 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
525 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
526 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
527 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
528 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
529 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
530 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
531 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
532 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
533 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
534 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */
535 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */
536 0x1120 /* MX28_PAD_LCD_D18__LCD_D18 */
537 0x1130 /* MX28_PAD_LCD_D19__LCD_D19 */
538 0x1140 /* MX28_PAD_LCD_D20__LCD_D20 */
539 0x1150 /* MX28_PAD_LCD_D21__LCD_D21 */
540 0x1160 /* MX28_PAD_LCD_D22__LCD_D22 */
541 0x1170 /* MX28_PAD_LCD_D23__LCD_D23 */
542 >;
543 fsl,drive-strength = <0>;
544 fsl,voltage = <1>;
545 fsl,pull-up = <0>;
546 };
547
548 lcdif_16bit_pins_a: lcdif-16bit@0 {
549 reg = <0>;
550 fsl,pinmux-ids = <
551 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
552 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
553 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
554 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
555 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
556 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
557 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
558 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
559 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
560 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
561 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
562 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
563 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
564 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
565 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
566 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
567 >;
568 fsl,drive-strength = <0>;
569 fsl,voltage = <1>;
570 fsl,pull-up = <0>;
571 };
572
573 can0_pins_a: can0@0 {
574 reg = <0>;
575 fsl,pinmux-ids = <
576 0x0161 /* MX28_PAD_GPMI_RDY2__CAN0_TX */
577 0x0171 /* MX28_PAD_GPMI_RDY3__CAN0_RX */
578 >;
579 fsl,drive-strength = <0>;
580 fsl,voltage = <1>;
581 fsl,pull-up = <0>;
582 };
583
584 can1_pins_a: can1@0 {
585 reg = <0>;
586 fsl,pinmux-ids = <
587 0x0121 /* MX28_PAD_GPMI_CE2N__CAN1_TX */
588 0x0131 /* MX28_PAD_GPMI_CE3N__CAN1_RX */
589 >;
590 fsl,drive-strength = <0>;
591 fsl,voltage = <1>;
592 fsl,pull-up = <0>;
593 };
594
595 spi2_pins_a: spi2@0 {
596 reg = <0>;
597 fsl,pinmux-ids = <
598 0x2100 /* MX28_PAD_SSP2_SCK__SSP2_SCK */
599 0x2110 /* MX28_PAD_SSP2_MOSI__SSP2_CMD */
600 0x2120 /* MX28_PAD_SSP2_MISO__SSP2_D0 */
601 0x2130 /* MX28_PAD_SSP2_SS0__SSP2_D3 */
602 >;
603 fsl,drive-strength = <1>;
604 fsl,voltage = <1>;
605 fsl,pull-up = <1>;
606 };
607
608 usbphy0_pins_a: usbphy0@0 {
609 reg = <0>;
610 fsl,pinmux-ids = <
611 0x2152 /* MX28_PAD_SSP2_SS2__USB0_OVERCURRENT */
612 >;
613 fsl,drive-strength = <2>;
614 fsl,voltage = <1>;
615 fsl,pull-up = <0>;
616 };
617
618 usbphy0_pins_b: usbphy0@1 {
619 reg = <1>;
620 fsl,pinmux-ids = <
621 0x3061 /* MX28_PAD_AUART1_CTS__USB0_OVERCURRENT */
622 >;
623 fsl,drive-strength = <2>;
624 fsl,voltage = <1>;
625 fsl,pull-up = <0>;
626 };
627
628 usbphy1_pins_a: usbphy1@0 {
629 reg = <0>;
630 fsl,pinmux-ids = <
631 0x2142 /* MX28_PAD_SSP2_SS1__USB1_OVERCURRENT */
632 >;
633 fsl,drive-strength = <2>;
634 fsl,voltage = <1>;
635 fsl,pull-up = <0>;
636 };
637 };
638
639 digctl@8001c000 {
640 reg = <0x8001c000 0x2000>;
641 interrupts = <89>;
642 status = "disabled";
643 };
644
645 etm@80022000 {
646 reg = <0x80022000 0x2000>;
647 status = "disabled";
648 };
649
650 dma-apbx@80024000 {
651 compatible = "fsl,imx28-dma-apbx";
652 reg = <0x80024000 0x2000>;
653 clocks = <&clks 26>;
654 };
655
656 dcp@80028000 {
657 reg = <0x80028000 0x2000>;
658 interrupts = <52 53 54>;
659 status = "disabled";
660 };
661
662 pxp@8002a000 {
663 reg = <0x8002a000 0x2000>;
664 interrupts = <39>;
665 status = "disabled";
666 };
667
668 ocotp@8002c000 {
669 reg = <0x8002c000 0x2000>;
670 status = "disabled";
671 };
672
673 axi-ahb@8002e000 {
674 reg = <0x8002e000 0x2000>;
675 status = "disabled";
676 };
677
678 lcdif@80030000 {
679 compatible = "fsl,imx28-lcdif";
680 reg = <0x80030000 0x2000>;
681 interrupts = <38 86>;
682 clocks = <&clks 55>;
683 status = "disabled";
684 };
685
686 can0: can@80032000 {
687 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
688 reg = <0x80032000 0x2000>;
689 interrupts = <8>;
690 clocks = <&clks 58>, <&clks 58>;
691 clock-names = "ipg", "per";
692 status = "disabled";
693 };
694
695 can1: can@80034000 {
696 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
697 reg = <0x80034000 0x2000>;
698 interrupts = <9>;
699 clocks = <&clks 59>, <&clks 59>;
700 clock-names = "ipg", "per";
701 status = "disabled";
702 };
703
704 simdbg@8003c000 {
705 reg = <0x8003c000 0x200>;
706 status = "disabled";
707 };
708
709 simgpmisel@8003c200 {
710 reg = <0x8003c200 0x100>;
711 status = "disabled";
712 };
713
714 simsspsel@8003c300 {
715 reg = <0x8003c300 0x100>;
716 status = "disabled";
717 };
718
719 simmemsel@8003c400 {
720 reg = <0x8003c400 0x100>;
721 status = "disabled";
722 };
723
724 gpiomon@8003c500 {
725 reg = <0x8003c500 0x100>;
726 status = "disabled";
727 };
728
729 simenet@8003c700 {
730 reg = <0x8003c700 0x100>;
731 status = "disabled";
732 };
733
734 armjtag@8003c800 {
735 reg = <0x8003c800 0x100>;
736 status = "disabled";
737 };
738 };
739
740 apbx@80040000 {
741 compatible = "simple-bus";
742 #address-cells = <1>;
743 #size-cells = <1>;
744 reg = <0x80040000 0x40000>;
745 ranges;
746
747 clks: clkctrl@80040000 {
748 compatible = "fsl,imx28-clkctrl";
749 reg = <0x80040000 0x2000>;
750 #clock-cells = <1>;
751 };
752
753 saif0: saif@80042000 {
754 compatible = "fsl,imx28-saif";
755 reg = <0x80042000 0x2000>;
756 interrupts = <59 80>;
757 clocks = <&clks 53>;
758 fsl,saif-dma-channel = <4>;
759 status = "disabled";
760 };
761
762 power@80044000 {
763 reg = <0x80044000 0x2000>;
764 status = "disabled";
765 };
766
767 saif1: saif@80046000 {
768 compatible = "fsl,imx28-saif";
769 reg = <0x80046000 0x2000>;
770 interrupts = <58 81>;
771 clocks = <&clks 54>;
772 fsl,saif-dma-channel = <5>;
773 status = "disabled";
774 };
775
776 lradc@80050000 {
777 compatible = "fsl,imx28-lradc";
778 reg = <0x80050000 0x2000>;
779 interrupts = <10 14 15 16 17 18 19
780 20 21 22 23 24 25>;
781 status = "disabled";
782 };
783
784 spdif@80054000 {
785 reg = <0x80054000 0x2000>;
786 interrupts = <45 66>;
787 status = "disabled";
788 };
789
790 rtc@80056000 {
791 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
792 reg = <0x80056000 0x2000>;
793 interrupts = <29>;
794 };
795
796 i2c0: i2c@80058000 {
797 #address-cells = <1>;
798 #size-cells = <0>;
799 compatible = "fsl,imx28-i2c";
800 reg = <0x80058000 0x2000>;
801 interrupts = <111 68>;
802 clock-frequency = <100000>;
803 fsl,i2c-dma-channel = <6>;
804 status = "disabled";
805 };
806
807 i2c1: i2c@8005a000 {
808 #address-cells = <1>;
809 #size-cells = <0>;
810 compatible = "fsl,imx28-i2c";
811 reg = <0x8005a000 0x2000>;
812 interrupts = <110 69>;
813 clock-frequency = <100000>;
814 fsl,i2c-dma-channel = <7>;
815 status = "disabled";
816 };
817
818 pwm: pwm@80064000 {
819 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
820 reg = <0x80064000 0x2000>;
821 clocks = <&clks 44>;
822 #pwm-cells = <2>;
823 fsl,pwm-number = <8>;
824 status = "disabled";
825 };
826
827 timrot@80068000 {
828 compatible = "fsl,imx28-timrot", "fsl,timrot";
829 reg = <0x80068000 0x2000>;
830 interrupts = <48 49 50 51>;
831 };
832
833 auart0: serial@8006a000 {
834 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
835 reg = <0x8006a000 0x2000>;
836 interrupts = <112 70 71>;
837 fsl,auart-dma-channel = <8 9>;
838 clocks = <&clks 45>;
839 status = "disabled";
840 };
841
842 auart1: serial@8006c000 {
843 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
844 reg = <0x8006c000 0x2000>;
845 interrupts = <113 72 73>;
846 clocks = <&clks 45>;
847 status = "disabled";
848 };
849
850 auart2: serial@8006e000 {
851 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
852 reg = <0x8006e000 0x2000>;
853 interrupts = <114 74 75>;
854 clocks = <&clks 45>;
855 status = "disabled";
856 };
857
858 auart3: serial@80070000 {
859 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
860 reg = <0x80070000 0x2000>;
861 interrupts = <115 76 77>;
862 clocks = <&clks 45>;
863 status = "disabled";
864 };
865
866 auart4: serial@80072000 {
867 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
868 reg = <0x80072000 0x2000>;
869 interrupts = <116 78 79>;
870 clocks = <&clks 45>;
871 status = "disabled";
872 };
873
874 duart: serial@80074000 {
875 compatible = "arm,pl011", "arm,primecell";
876 reg = <0x80074000 0x1000>;
877 interrupts = <47>;
878 clocks = <&clks 45>, <&clks 26>;
879 clock-names = "uart", "apb_pclk";
880 status = "disabled";
881 };
882
883 usbphy0: usbphy@8007c000 {
884 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
885 reg = <0x8007c000 0x2000>;
886 clocks = <&clks 62>;
887 status = "disabled";
888 };
889
890 usbphy1: usbphy@8007e000 {
891 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
892 reg = <0x8007e000 0x2000>;
893 clocks = <&clks 63>;
894 status = "disabled";
895 };
896 };
897 };
898
899 ahb@80080000 {
900 compatible = "simple-bus";
901 #address-cells = <1>;
902 #size-cells = <1>;
903 reg = <0x80080000 0x80000>;
904 ranges;
905
906 usb0: usb@80080000 {
907 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
908 reg = <0x80080000 0x10000>;
909 interrupts = <93>;
910 clocks = <&clks 60>;
911 fsl,usbphy = <&usbphy0>;
912 status = "disabled";
913 };
914
915 usb1: usb@80090000 {
916 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
917 reg = <0x80090000 0x10000>;
918 interrupts = <92>;
919 clocks = <&clks 61>;
920 fsl,usbphy = <&usbphy1>;
921 status = "disabled";
922 };
923
924 dflpt@800c0000 {
925 reg = <0x800c0000 0x10000>;
926 status = "disabled";
927 };
928
929 mac0: ethernet@800f0000 {
930 compatible = "fsl,imx28-fec";
931 reg = <0x800f0000 0x4000>;
932 interrupts = <101>;
933 clocks = <&clks 57>, <&clks 57>;
934 clock-names = "ipg", "ahb";
935 status = "disabled";
936 };
937
938 mac1: ethernet@800f4000 {
939 compatible = "fsl,imx28-fec";
940 reg = <0x800f4000 0x4000>;
941 interrupts = <102>;
942 clocks = <&clks 57>, <&clks 57>;
943 clock-names = "ipg", "ahb";
944 status = "disabled";
945 };
946
947 switch@800f8000 {
948 reg = <0x800f8000 0x8000>;
949 status = "disabled";
950 };
951
952 };
953};
diff --git a/arch/arm/boot/dts/imx31-bug.dts b/arch/arm/boot/dts/imx31-bug.dts
deleted file mode 100644
index 7f67402328d..00000000000
--- a/arch/arm/boot/dts/imx31-bug.dts
+++ /dev/null
@@ -1,31 +0,0 @@
1/*
2 * Copyright 2012 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "imx31.dtsi"
14
15/ {
16 model = "Buglabs i.MX31 Bug 1.x";
17 compatible = "buglabs,imx31-bug", "fsl,imx31";
18
19 memory {
20 reg = <0x80000000 0x8000000>; /* 128M */
21 };
22
23 soc {
24 aips@43f00000 { /* AIPS1 */
25 uart5: serial@43fb4000 {
26 fsl,uart-has-rtscts;
27 status = "okay";
28 };
29 };
30 };
31};
diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi
deleted file mode 100644
index eef7099f3e3..00000000000
--- a/arch/arm/boot/dts/imx31.dtsi
+++ /dev/null
@@ -1,88 +0,0 @@
1/*
2 * Copyright 2012 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 aliases {
16 serial0 = &uart1;
17 serial1 = &uart2;
18 serial2 = &uart3;
19 serial3 = &uart4;
20 serial4 = &uart5;
21 };
22
23 avic: avic-interrupt-controller@60000000 {
24 compatible = "fsl,imx31-avic", "fsl,avic";
25 interrupt-controller;
26 #interrupt-cells = <1>;
27 reg = <0x60000000 0x100000>;
28 };
29
30 soc {
31 #address-cells = <1>;
32 #size-cells = <1>;
33 compatible = "simple-bus";
34 interrupt-parent = <&avic>;
35 ranges;
36
37 aips@43f00000 { /* AIPS1 */
38 compatible = "fsl,aips-bus", "simple-bus";
39 #address-cells = <1>;
40 #size-cells = <1>;
41 reg = <0x43f00000 0x100000>;
42 ranges;
43
44 uart1: serial@43f90000 {
45 compatible = "fsl,imx31-uart", "fsl,imx21-uart";
46 reg = <0x43f90000 0x4000>;
47 interrupts = <45>;
48 status = "disabled";
49 };
50
51 uart2: serial@43f94000 {
52 compatible = "fsl,imx31-uart", "fsl,imx21-uart";
53 reg = <0x43f94000 0x4000>;
54 interrupts = <32>;
55 status = "disabled";
56 };
57
58 uart4: serial@43fb0000 {
59 compatible = "fsl,imx31-uart", "fsl,imx21-uart";
60 reg = <0x43fb0000 0x4000>;
61 interrupts = <46>;
62 status = "disabled";
63 };
64
65 uart5: serial@43fb4000 {
66 compatible = "fsl,imx31-uart", "fsl,imx21-uart";
67 reg = <0x43fb4000 0x4000>;
68 interrupts = <47>;
69 status = "disabled";
70 };
71 };
72
73 spba@50000000 {
74 compatible = "fsl,spba-bus", "simple-bus";
75 #address-cells = <1>;
76 #size-cells = <1>;
77 reg = <0x50000000 0x100000>;
78 ranges;
79
80 uart3: serial@5000c000 {
81 compatible = "fsl,imx31-uart", "fsl,imx21-uart";
82 reg = <0x5000c000 0x4000>;
83 interrupts = <18>;
84 status = "disabled";
85 };
86 };
87 };
88};
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
deleted file mode 100644
index 567e7ee72f9..00000000000
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ /dev/null
@@ -1,283 +0,0 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
14/include/ "imx51.dtsi"
15
16/ {
17 model = "Freescale i.MX51 Babbage Board";
18 compatible = "fsl,imx51-babbage", "fsl,imx51";
19
20 memory {
21 reg = <0x90000000 0x20000000>;
22 };
23
24 soc {
25 display@di0 {
26 compatible = "fsl,imx-parallel-display";
27 crtcs = <&ipu 0>;
28 interface-pix-fmt = "rgb24";
29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_ipu_disp1_1>;
31 };
32
33 display@di1 {
34 compatible = "fsl,imx-parallel-display";
35 crtcs = <&ipu 1>;
36 interface-pix-fmt = "rgb565";
37 pinctrl-names = "default";
38 pinctrl-0 = <&pinctrl_ipu_disp2_1>;
39 };
40
41 aips@70000000 { /* aips-1 */
42 spba@70000000 {
43 esdhc@70004000 { /* ESDHC1 */
44 pinctrl-names = "default";
45 pinctrl-0 = <&pinctrl_esdhc1_1>;
46 fsl,cd-controller;
47 fsl,wp-controller;
48 status = "okay";
49 };
50
51 esdhc@70008000 { /* ESDHC2 */
52 pinctrl-names = "default";
53 pinctrl-0 = <&pinctrl_esdhc2_1>;
54 cd-gpios = <&gpio1 6 0>;
55 wp-gpios = <&gpio1 5 0>;
56 status = "okay";
57 };
58
59 uart3: serial@7000c000 {
60 pinctrl-names = "default";
61 pinctrl-0 = <&pinctrl_uart3_1>;
62 fsl,uart-has-rtscts;
63 status = "okay";
64 };
65
66 ecspi@70010000 { /* ECSPI1 */
67 pinctrl-names = "default";
68 pinctrl-0 = <&pinctrl_ecspi1_1>;
69 fsl,spi-num-chipselects = <2>;
70 cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
71 status = "okay";
72
73 pmic: mc13892@0 {
74 #address-cells = <1>;
75 #size-cells = <0>;
76 compatible = "fsl,mc13892";
77 spi-max-frequency = <6000000>;
78 reg = <0>;
79 interrupt-parent = <&gpio1>;
80 interrupts = <8 0x4>;
81
82 regulators {
83 sw1_reg: sw1 {
84 regulator-min-microvolt = <600000>;
85 regulator-max-microvolt = <1375000>;
86 regulator-boot-on;
87 regulator-always-on;
88 };
89
90 sw2_reg: sw2 {
91 regulator-min-microvolt = <900000>;
92 regulator-max-microvolt = <1850000>;
93 regulator-boot-on;
94 regulator-always-on;
95 };
96
97 sw3_reg: sw3 {
98 regulator-min-microvolt = <1100000>;
99 regulator-max-microvolt = <1850000>;
100 regulator-boot-on;
101 regulator-always-on;
102 };
103
104 sw4_reg: sw4 {
105 regulator-min-microvolt = <1100000>;
106 regulator-max-microvolt = <1850000>;
107 regulator-boot-on;
108 regulator-always-on;
109 };
110
111 vpll_reg: vpll {
112 regulator-min-microvolt = <1050000>;
113 regulator-max-microvolt = <1800000>;
114 regulator-boot-on;
115 regulator-always-on;
116 };
117
118 vdig_reg: vdig {
119 regulator-min-microvolt = <1650000>;
120 regulator-max-microvolt = <1650000>;
121 regulator-boot-on;
122 };
123
124 vsd_reg: vsd {
125 regulator-min-microvolt = <1800000>;
126 regulator-max-microvolt = <3150000>;
127 };
128
129 vusb2_reg: vusb2 {
130 regulator-min-microvolt = <2400000>;
131 regulator-max-microvolt = <2775000>;
132 regulator-boot-on;
133 regulator-always-on;
134 };
135
136 vvideo_reg: vvideo {
137 regulator-min-microvolt = <2775000>;
138 regulator-max-microvolt = <2775000>;
139 };
140
141 vaudio_reg: vaudio {
142 regulator-min-microvolt = <2300000>;
143 regulator-max-microvolt = <3000000>;
144 };
145
146 vcam_reg: vcam {
147 regulator-min-microvolt = <2500000>;
148 regulator-max-microvolt = <3000000>;
149 };
150
151 vgen1_reg: vgen1 {
152 regulator-min-microvolt = <1200000>;
153 regulator-max-microvolt = <1200000>;
154 };
155
156 vgen2_reg: vgen2 {
157 regulator-min-microvolt = <1200000>;
158 regulator-max-microvolt = <3150000>;
159 regulator-always-on;
160 };
161
162 vgen3_reg: vgen3 {
163 regulator-min-microvolt = <1800000>;
164 regulator-max-microvolt = <2900000>;
165 regulator-always-on;
166 };
167 };
168 };
169
170 flash: at45db321d@1 {
171 #address-cells = <1>;
172 #size-cells = <1>;
173 compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
174 spi-max-frequency = <25000000>;
175 reg = <1>;
176
177 partition@0 {
178 label = "U-Boot";
179 reg = <0x0 0x40000>;
180 read-only;
181 };
182
183 partition@40000 {
184 label = "Kernel";
185 reg = <0x40000 0x3c0000>;
186 };
187 };
188 };
189
190 ssi2: ssi@70014000 {
191 fsl,mode = "i2s-slave";
192 status = "okay";
193 };
194 };
195
196 iomuxc@73fa8000 {
197 pinctrl-names = "default";
198 pinctrl-0 = <&pinctrl_hog>;
199
200 hog {
201 pinctrl_hog: hoggrp {
202 fsl,pins = <
203 694 0x20d5 /* MX51_PAD_GPIO1_0__SD1_CD */
204 697 0x20d5 /* MX51_PAD_GPIO1_1__SD1_WP */
205 737 0x100 /* MX51_PAD_GPIO1_5__GPIO1_5 */
206 740 0x100 /* MX51_PAD_GPIO1_6__GPIO1_6 */
207 121 0x5 /* MX51_PAD_EIM_A27__GPIO2_21 */
208 402 0x85 /* MX51_PAD_CSPI1_SS0__GPIO4_24 */
209 405 0x85 /* MX51_PAD_CSPI1_SS1__GPIO4_25 */
210 >;
211 };
212 };
213 };
214
215 uart1: serial@73fbc000 {
216 pinctrl-names = "default";
217 pinctrl-0 = <&pinctrl_uart1_1>;
218 fsl,uart-has-rtscts;
219 status = "okay";
220 };
221
222 uart2: serial@73fc0000 {
223 pinctrl-names = "default";
224 pinctrl-0 = <&pinctrl_uart2_1>;
225 status = "okay";
226 };
227 };
228
229 aips@80000000 { /* aips-2 */
230 i2c@83fc4000 { /* I2C2 */
231 pinctrl-names = "default";
232 pinctrl-0 = <&pinctrl_i2c2_1>;
233 status = "okay";
234
235 sgtl5000: codec@0a {
236 compatible = "fsl,sgtl5000";
237 reg = <0x0a>;
238 clock-frequency = <26000000>;
239 VDDA-supply = <&vdig_reg>;
240 VDDIO-supply = <&vvideo_reg>;
241 };
242 };
243
244 audmux@83fd0000 {
245 pinctrl-names = "default";
246 pinctrl-0 = <&pinctrl_audmux_1>;
247 status = "okay";
248 };
249
250 ethernet@83fec000 {
251 pinctrl-names = "default";
252 pinctrl-0 = <&pinctrl_fec_1>;
253 phy-mode = "mii";
254 status = "okay";
255 };
256 };
257 };
258
259 gpio-keys {
260 compatible = "gpio-keys";
261
262 power {
263 label = "Power Button";
264 gpios = <&gpio2 21 0>;
265 linux,code = <116>; /* KEY_POWER */
266 gpio-key,wakeup;
267 };
268 };
269
270 sound {
271 compatible = "fsl,imx51-babbage-sgtl5000",
272 "fsl,imx-audio-sgtl5000";
273 model = "imx51-babbage-sgtl5000";
274 ssi-controller = <&ssi2>;
275 audio-codec = <&sgtl5000>;
276 audio-routing =
277 "MIC_IN", "Mic Jack",
278 "Mic Jack", "Mic Bias",
279 "Headphone Jack", "HP_OUT";
280 mux-int-port = <2>;
281 mux-ext-port = <3>;
282 };
283};
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
deleted file mode 100644
index 1f5d45eff45..00000000000
--- a/arch/arm/boot/dts/imx51.dtsi
+++ /dev/null
@@ -1,561 +0,0 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/include/ "skeleton.dtsi"
14
15/ {
16 aliases {
17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 gpio0 = &gpio1;
21 gpio1 = &gpio2;
22 gpio2 = &gpio3;
23 gpio3 = &gpio4;
24 };
25
26 tzic: tz-interrupt-controller@e0000000 {
27 compatible = "fsl,imx51-tzic", "fsl,tzic";
28 interrupt-controller;
29 #interrupt-cells = <1>;
30 reg = <0xe0000000 0x4000>;
31 };
32
33 clocks {
34 #address-cells = <1>;
35 #size-cells = <0>;
36
37 ckil {
38 compatible = "fsl,imx-ckil", "fixed-clock";
39 clock-frequency = <32768>;
40 };
41
42 ckih1 {
43 compatible = "fsl,imx-ckih1", "fixed-clock";
44 clock-frequency = <22579200>;
45 };
46
47 ckih2 {
48 compatible = "fsl,imx-ckih2", "fixed-clock";
49 clock-frequency = <0>;
50 };
51
52 osc {
53 compatible = "fsl,imx-osc", "fixed-clock";
54 clock-frequency = <24000000>;
55 };
56 };
57
58 soc {
59 #address-cells = <1>;
60 #size-cells = <1>;
61 compatible = "simple-bus";
62 interrupt-parent = <&tzic>;
63 ranges;
64
65 ipu: ipu@40000000 {
66 #crtc-cells = <1>;
67 compatible = "fsl,imx51-ipu";
68 reg = <0x40000000 0x20000000>;
69 interrupts = <11 10>;
70 };
71
72 aips@70000000 { /* AIPS1 */
73 compatible = "fsl,aips-bus", "simple-bus";
74 #address-cells = <1>;
75 #size-cells = <1>;
76 reg = <0x70000000 0x10000000>;
77 ranges;
78
79 spba@70000000 {
80 compatible = "fsl,spba-bus", "simple-bus";
81 #address-cells = <1>;
82 #size-cells = <1>;
83 reg = <0x70000000 0x40000>;
84 ranges;
85
86 esdhc1: esdhc@70004000 {
87 compatible = "fsl,imx51-esdhc";
88 reg = <0x70004000 0x4000>;
89 interrupts = <1>;
90 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
91 clock-names = "ipg", "ahb", "per";
92 status = "disabled";
93 };
94
95 esdhc2: esdhc@70008000 {
96 compatible = "fsl,imx51-esdhc";
97 reg = <0x70008000 0x4000>;
98 interrupts = <2>;
99 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
100 clock-names = "ipg", "ahb", "per";
101 bus-width = <4>;
102 status = "disabled";
103 };
104
105 uart3: serial@7000c000 {
106 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
107 reg = <0x7000c000 0x4000>;
108 interrupts = <33>;
109 clocks = <&clks 32>, <&clks 33>;
110 clock-names = "ipg", "per";
111 status = "disabled";
112 };
113
114 ecspi1: ecspi@70010000 {
115 #address-cells = <1>;
116 #size-cells = <0>;
117 compatible = "fsl,imx51-ecspi";
118 reg = <0x70010000 0x4000>;
119 interrupts = <36>;
120 clocks = <&clks 51>, <&clks 52>;
121 clock-names = "ipg", "per";
122 status = "disabled";
123 };
124
125 ssi2: ssi@70014000 {
126 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
127 reg = <0x70014000 0x4000>;
128 interrupts = <30>;
129 clocks = <&clks 49>;
130 fsl,fifo-depth = <15>;
131 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
132 status = "disabled";
133 };
134
135 esdhc3: esdhc@70020000 {
136 compatible = "fsl,imx51-esdhc";
137 reg = <0x70020000 0x4000>;
138 interrupts = <3>;
139 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
140 clock-names = "ipg", "ahb", "per";
141 bus-width = <4>;
142 status = "disabled";
143 };
144
145 esdhc4: esdhc@70024000 {
146 compatible = "fsl,imx51-esdhc";
147 reg = <0x70024000 0x4000>;
148 interrupts = <4>;
149 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
150 clock-names = "ipg", "ahb", "per";
151 bus-width = <4>;
152 status = "disabled";
153 };
154 };
155
156 usbotg: usb@73f80000 {
157 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
158 reg = <0x73f80000 0x0200>;
159 interrupts = <18>;
160 status = "disabled";
161 };
162
163 usbh1: usb@73f80200 {
164 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
165 reg = <0x73f80200 0x0200>;
166 interrupts = <14>;
167 status = "disabled";
168 };
169
170 usbh2: usb@73f80400 {
171 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
172 reg = <0x73f80400 0x0200>;
173 interrupts = <16>;
174 status = "disabled";
175 };
176
177 usbh3: usb@73f80600 {
178 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
179 reg = <0x73f80600 0x0200>;
180 interrupts = <17>;
181 status = "disabled";
182 };
183
184 gpio1: gpio@73f84000 {
185 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
186 reg = <0x73f84000 0x4000>;
187 interrupts = <50 51>;
188 gpio-controller;
189 #gpio-cells = <2>;
190 interrupt-controller;
191 #interrupt-cells = <2>;
192 };
193
194 gpio2: gpio@73f88000 {
195 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
196 reg = <0x73f88000 0x4000>;
197 interrupts = <52 53>;
198 gpio-controller;
199 #gpio-cells = <2>;
200 interrupt-controller;
201 #interrupt-cells = <2>;
202 };
203
204 gpio3: gpio@73f8c000 {
205 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
206 reg = <0x73f8c000 0x4000>;
207 interrupts = <54 55>;
208 gpio-controller;
209 #gpio-cells = <2>;
210 interrupt-controller;
211 #interrupt-cells = <2>;
212 };
213
214 gpio4: gpio@73f90000 {
215 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
216 reg = <0x73f90000 0x4000>;
217 interrupts = <56 57>;
218 gpio-controller;
219 #gpio-cells = <2>;
220 interrupt-controller;
221 #interrupt-cells = <2>;
222 };
223
224 wdog1: wdog@73f98000 {
225 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
226 reg = <0x73f98000 0x4000>;
227 interrupts = <58>;
228 clocks = <&clks 0>;
229 };
230
231 wdog2: wdog@73f9c000 {
232 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
233 reg = <0x73f9c000 0x4000>;
234 interrupts = <59>;
235 clocks = <&clks 0>;
236 status = "disabled";
237 };
238
239 iomuxc: iomuxc@73fa8000 {
240 compatible = "fsl,imx51-iomuxc";
241 reg = <0x73fa8000 0x4000>;
242
243 audmux {
244 pinctrl_audmux_1: audmuxgrp-1 {
245 fsl,pins = <
246 384 0x80000000 /* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */
247 386 0x80000000 /* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */
248 389 0x80000000 /* MX51_PAD_AUD3_BB_CK__AUD3_TXC */
249 391 0x80000000 /* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */
250 >;
251 };
252 };
253
254 fec {
255 pinctrl_fec_1: fecgrp-1 {
256 fsl,pins = <
257 128 0x80000000 /* MX51_PAD_EIM_EB2__FEC_MDIO */
258 134 0x80000000 /* MX51_PAD_EIM_EB3__FEC_RDATA1 */
259 146 0x80000000 /* MX51_PAD_EIM_CS2__FEC_RDATA2 */
260 152 0x80000000 /* MX51_PAD_EIM_CS3__FEC_RDATA3 */
261 158 0x80000000 /* MX51_PAD_EIM_CS4__FEC_RX_ER */
262 165 0x80000000 /* MX51_PAD_EIM_CS5__FEC_CRS */
263 206 0x80000000 /* MX51_PAD_NANDF_RB2__FEC_COL */
264 213 0x80000000 /* MX51_PAD_NANDF_RB3__FEC_RX_CLK */
265 293 0x80000000 /* MX51_PAD_NANDF_D9__FEC_RDATA0 */
266 298 0x80000000 /* MX51_PAD_NANDF_D8__FEC_TDATA0 */
267 225 0x80000000 /* MX51_PAD_NANDF_CS2__FEC_TX_ER */
268 231 0x80000000 /* MX51_PAD_NANDF_CS3__FEC_MDC */
269 237 0x80000000 /* MX51_PAD_NANDF_CS4__FEC_TDATA1 */
270 243 0x80000000 /* MX51_PAD_NANDF_CS5__FEC_TDATA2 */
271 250 0x80000000 /* MX51_PAD_NANDF_CS6__FEC_TDATA3 */
272 255 0x80000000 /* MX51_PAD_NANDF_CS7__FEC_TX_EN */
273 260 0x80000000 /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */
274 >;
275 };
276 };
277
278 ecspi1 {
279 pinctrl_ecspi1_1: ecspi1grp-1 {
280 fsl,pins = <
281 398 0x185 /* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */
282 394 0x185 /* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */
283 409 0x185 /* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */
284 >;
285 };
286 };
287
288 esdhc1 {
289 pinctrl_esdhc1_1: esdhc1grp-1 {
290 fsl,pins = <
291 666 0x400020d5 /* MX51_PAD_SD1_CMD__SD1_CMD */
292 669 0x20d5 /* MX51_PAD_SD1_CLK__SD1_CLK */
293 672 0x20d5 /* MX51_PAD_SD1_DATA0__SD1_DATA0 */
294 678 0x20d5 /* MX51_PAD_SD1_DATA1__SD1_DATA1 */
295 684 0x20d5 /* MX51_PAD_SD1_DATA2__SD1_DATA2 */
296 691 0x20d5 /* MX51_PAD_SD1_DATA3__SD1_DATA3 */
297 >;
298 };
299 };
300
301 esdhc2 {
302 pinctrl_esdhc2_1: esdhc2grp-1 {
303 fsl,pins = <
304 704 0x400020d5 /* MX51_PAD_SD2_CMD__SD2_CMD */
305 707 0x20d5 /* MX51_PAD_SD2_CLK__SD2_CLK */
306 710 0x20d5 /* MX51_PAD_SD2_DATA0__SD2_DATA0 */
307 712 0x20d5 /* MX51_PAD_SD2_DATA1__SD2_DATA1 */
308 715 0x20d5 /* MX51_PAD_SD2_DATA2__SD2_DATA2 */
309 719 0x20d5 /* MX51_PAD_SD2_DATA3__SD2_DATA3 */
310 >;
311 };
312 };
313
314 i2c2 {
315 pinctrl_i2c2_1: i2c2grp-1 {
316 fsl,pins = <
317 449 0x400001ed /* MX51_PAD_KEY_COL4__I2C2_SCL */
318 454 0x400001ed /* MX51_PAD_KEY_COL5__I2C2_SDA */
319 >;
320 };
321 };
322
323 ipu_disp1 {
324 pinctrl_ipu_disp1_1: ipudisp1grp-1 {
325 fsl,pins = <
326 528 0x5 /* MX51_PAD_DISP1_DAT0__DISP1_DAT0 */
327 529 0x5 /* MX51_PAD_DISP1_DAT1__DISP1_DAT1 */
328 530 0x5 /* MX51_PAD_DISP1_DAT2__DISP1_DAT2 */
329 531 0x5 /* MX51_PAD_DISP1_DAT3__DISP1_DAT3 */
330 532 0x5 /* MX51_PAD_DISP1_DAT4__DISP1_DAT4 */
331 533 0x5 /* MX51_PAD_DISP1_DAT5__DISP1_DAT5 */
332 535 0x5 /* MX51_PAD_DISP1_DAT6__DISP1_DAT6 */
333 537 0x5 /* MX51_PAD_DISP1_DAT7__DISP1_DAT7 */
334 539 0x5 /* MX51_PAD_DISP1_DAT8__DISP1_DAT8 */
335 541 0x5 /* MX51_PAD_DISP1_DAT9__DISP1_DAT9 */
336 543 0x5 /* MX51_PAD_DISP1_DAT10__DISP1_DAT10 */
337 545 0x5 /* MX51_PAD_DISP1_DAT11__DISP1_DAT11 */
338 547 0x5 /* MX51_PAD_DISP1_DAT12__DISP1_DAT12 */
339 549 0x5 /* MX51_PAD_DISP1_DAT13__DISP1_DAT13 */
340 551 0x5 /* MX51_PAD_DISP1_DAT14__DISP1_DAT14 */
341 553 0x5 /* MX51_PAD_DISP1_DAT15__DISP1_DAT15 */
342 555 0x5 /* MX51_PAD_DISP1_DAT16__DISP1_DAT16 */
343 557 0x5 /* MX51_PAD_DISP1_DAT17__DISP1_DAT17 */
344 559 0x5 /* MX51_PAD_DISP1_DAT18__DISP1_DAT18 */
345 563 0x5 /* MX51_PAD_DISP1_DAT19__DISP1_DAT19 */
346 567 0x5 /* MX51_PAD_DISP1_DAT20__DISP1_DAT20 */
347 571 0x5 /* MX51_PAD_DISP1_DAT21__DISP1_DAT21 */
348 575 0x5 /* MX51_PAD_DISP1_DAT22__DISP1_DAT22 */
349 579 0x5 /* MX51_PAD_DISP1_DAT23__DISP1_DAT23 */
350 584 0x5 /* MX51_PAD_DI1_PIN2__DI1_PIN2 (hsync) */
351 583 0x5 /* MX51_PAD_DI1_PIN3__DI1_PIN3 (vsync) */
352 >;
353 };
354 };
355
356 ipu_disp2 {
357 pinctrl_ipu_disp2_1: ipudisp2grp-1 {
358 fsl,pins = <
359 603 0x5 /* MX51_PAD_DISP2_DAT0__DISP2_DAT0 */
360 608 0x5 /* MX51_PAD_DISP2_DAT1__DISP2_DAT1 */
361 613 0x5 /* MX51_PAD_DISP2_DAT2__DISP2_DAT2 */
362 614 0x5 /* MX51_PAD_DISP2_DAT3__DISP2_DAT3 */
363 615 0x5 /* MX51_PAD_DISP2_DAT4__DISP2_DAT4 */
364 616 0x5 /* MX51_PAD_DISP2_DAT5__DISP2_DAT5 */
365 617 0x5 /* MX51_PAD_DISP2_DAT6__DISP2_DAT6 */
366 622 0x5 /* MX51_PAD_DISP2_DAT7__DISP2_DAT7 */
367 627 0x5 /* MX51_PAD_DISP2_DAT8__DISP2_DAT8 */
368 633 0x5 /* MX51_PAD_DISP2_DAT9__DISP2_DAT9 */
369 637 0x5 /* MX51_PAD_DISP2_DAT10__DISP2_DAT10 */
370 643 0x5 /* MX51_PAD_DISP2_DAT11__DISP2_DAT11 */
371 648 0x5 /* MX51_PAD_DISP2_DAT12__DISP2_DAT12 */
372 652 0x5 /* MX51_PAD_DISP2_DAT13__DISP2_DAT13 */
373 656 0x5 /* MX51_PAD_DISP2_DAT14__DISP2_DAT14 */
374 661 0x5 /* MX51_PAD_DISP2_DAT15__DISP2_DAT15 */
375 593 0x5 /* MX51_PAD_DI2_PIN2__DI2_PIN2 (hsync) */
376 595 0x5 /* MX51_PAD_DI2_PIN3__DI2_PIN3 (vsync) */
377 597 0x5 /* MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK */
378 599 0x5 /* MX51_PAD_DI_GP4__DI2_PIN15 */
379 >;
380 };
381 };
382
383 uart1 {
384 pinctrl_uart1_1: uart1grp-1 {
385 fsl,pins = <
386 413 0x1c5 /* MX51_PAD_UART1_RXD__UART1_RXD */
387 416 0x1c5 /* MX51_PAD_UART1_TXD__UART1_TXD */
388 418 0x1c5 /* MX51_PAD_UART1_RTS__UART1_RTS */
389 420 0x1c5 /* MX51_PAD_UART1_CTS__UART1_CTS */
390 >;
391 };
392 };
393
394 uart2 {
395 pinctrl_uart2_1: uart2grp-1 {
396 fsl,pins = <
397 423 0x1c5 /* MX51_PAD_UART2_RXD__UART2_RXD */
398 426 0x1c5 /* MX51_PAD_UART2_TXD__UART2_TXD */
399 >;
400 };
401 };
402
403 uart3 {
404 pinctrl_uart3_1: uart3grp-1 {
405 fsl,pins = <
406 54 0x1c5 /* MX51_PAD_EIM_D25__UART3_RXD */
407 59 0x1c5 /* MX51_PAD_EIM_D26__UART3_TXD */
408 65 0x1c5 /* MX51_PAD_EIM_D27__UART3_RTS */
409 49 0x1c5 /* MX51_PAD_EIM_D24__UART3_CTS */
410 >;
411 };
412 };
413 };
414
415 pwm1: pwm@73fb4000 {
416 #pwm-cells = <2>;
417 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
418 reg = <0x73fb4000 0x4000>;
419 clocks = <&clks 37>, <&clks 38>;
420 clock-names = "ipg", "per";
421 interrupts = <61>;
422 };
423
424 pwm2: pwm@73fb8000 {
425 #pwm-cells = <2>;
426 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
427 reg = <0x73fb8000 0x4000>;
428 clocks = <&clks 39>, <&clks 40>;
429 clock-names = "ipg", "per";
430 interrupts = <94>;
431 };
432
433 uart1: serial@73fbc000 {
434 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
435 reg = <0x73fbc000 0x4000>;
436 interrupts = <31>;
437 clocks = <&clks 28>, <&clks 29>;
438 clock-names = "ipg", "per";
439 status = "disabled";
440 };
441
442 uart2: serial@73fc0000 {
443 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
444 reg = <0x73fc0000 0x4000>;
445 interrupts = <32>;
446 clocks = <&clks 30>, <&clks 31>;
447 clock-names = "ipg", "per";
448 status = "disabled";
449 };
450
451 clks: ccm@73fd4000{
452 compatible = "fsl,imx51-ccm";
453 reg = <0x73fd4000 0x4000>;
454 interrupts = <0 71 0x04 0 72 0x04>;
455 #clock-cells = <1>;
456 };
457 };
458
459 aips@80000000 { /* AIPS2 */
460 compatible = "fsl,aips-bus", "simple-bus";
461 #address-cells = <1>;
462 #size-cells = <1>;
463 reg = <0x80000000 0x10000000>;
464 ranges;
465
466 ecspi2: ecspi@83fac000 {
467 #address-cells = <1>;
468 #size-cells = <0>;
469 compatible = "fsl,imx51-ecspi";
470 reg = <0x83fac000 0x4000>;
471 interrupts = <37>;
472 clocks = <&clks 53>, <&clks 54>;
473 clock-names = "ipg", "per";
474 status = "disabled";
475 };
476
477 sdma: sdma@83fb0000 {
478 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
479 reg = <0x83fb0000 0x4000>;
480 interrupts = <6>;
481 clocks = <&clks 56>, <&clks 56>;
482 clock-names = "ipg", "ahb";
483 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
484 };
485
486 cspi: cspi@83fc0000 {
487 #address-cells = <1>;
488 #size-cells = <0>;
489 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
490 reg = <0x83fc0000 0x4000>;
491 interrupts = <38>;
492 clocks = <&clks 55>, <&clks 0>;
493 clock-names = "ipg", "per";
494 status = "disabled";
495 };
496
497 i2c2: i2c@83fc4000 {
498 #address-cells = <1>;
499 #size-cells = <0>;
500 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
501 reg = <0x83fc4000 0x4000>;
502 interrupts = <63>;
503 clocks = <&clks 35>;
504 status = "disabled";
505 };
506
507 i2c1: i2c@83fc8000 {
508 #address-cells = <1>;
509 #size-cells = <0>;
510 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
511 reg = <0x83fc8000 0x4000>;
512 interrupts = <62>;
513 clocks = <&clks 34>;
514 status = "disabled";
515 };
516
517 ssi1: ssi@83fcc000 {
518 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
519 reg = <0x83fcc000 0x4000>;
520 interrupts = <29>;
521 clocks = <&clks 48>;
522 fsl,fifo-depth = <15>;
523 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
524 status = "disabled";
525 };
526
527 audmux: audmux@83fd0000 {
528 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
529 reg = <0x83fd0000 0x4000>;
530 status = "disabled";
531 };
532
533 nfc: nand@83fdb000 {
534 compatible = "fsl,imx51-nand";
535 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
536 interrupts = <8>;
537 clocks = <&clks 60>;
538 status = "disabled";
539 };
540
541 ssi3: ssi@83fe8000 {
542 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
543 reg = <0x83fe8000 0x4000>;
544 interrupts = <96>;
545 clocks = <&clks 50>;
546 fsl,fifo-depth = <15>;
547 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
548 status = "disabled";
549 };
550
551 fec: ethernet@83fec000 {
552 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
553 reg = <0x83fec000 0x4000>;
554 interrupts = <87>;
555 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
556 clock-names = "ipg", "ahb", "ptp";
557 status = "disabled";
558 };
559 };
560 };
561};
diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts
deleted file mode 100644
index 4be76f22352..00000000000
--- a/arch/arm/boot/dts/imx53-ard.dts
+++ /dev/null
@@ -1,164 +0,0 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
14/include/ "imx53.dtsi"
15
16/ {
17 model = "Freescale i.MX53 Automotive Reference Design Board";
18 compatible = "fsl,imx53-ard", "fsl,imx53";
19
20 memory {
21 reg = <0x70000000 0x40000000>;
22 };
23
24 soc {
25 aips@50000000 { /* AIPS1 */
26 spba@50000000 {
27 esdhc@50004000 { /* ESDHC1 */
28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_esdhc1_2>;
30 cd-gpios = <&gpio1 1 0>;
31 wp-gpios = <&gpio1 9 0>;
32 status = "okay";
33 };
34 };
35
36 iomuxc@53fa8000 {
37 pinctrl-names = "default";
38 pinctrl-0 = <&pinctrl_hog>;
39
40 hog {
41 pinctrl_hog: hoggrp {
42 fsl,pins = <
43 1077 0x80000000 /* MX53_PAD_GPIO_1__GPIO1_1 */
44 1085 0x80000000 /* MX53_PAD_GPIO_9__GPIO1_9 */
45 486 0x80000000 /* MX53_PAD_EIM_EB3__GPIO2_31 */
46 739 0x80000000 /* MX53_PAD_GPIO_10__GPIO4_0 */
47 218 0x80000000 /* MX53_PAD_DISP0_DAT16__GPIO5_10 */
48 226 0x80000000 /* MX53_PAD_DISP0_DAT17__GPIO5_11 */
49 233 0x80000000 /* MX53_PAD_DISP0_DAT18__GPIO5_12 */
50 241 0x80000000 /* MX53_PAD_DISP0_DAT19__GPIO5_13 */
51 429 0x80000000 /* MX53_PAD_EIM_D16__EMI_WEIM_D_16 */
52 435 0x80000000 /* MX53_PAD_EIM_D17__EMI_WEIM_D_17 */
53 441 0x80000000 /* MX53_PAD_EIM_D18__EMI_WEIM_D_18 */
54 448 0x80000000 /* MX53_PAD_EIM_D19__EMI_WEIM_D_19 */
55 456 0x80000000 /* MX53_PAD_EIM_D20__EMI_WEIM_D_20 */
56 464 0x80000000 /* MX53_PAD_EIM_D21__EMI_WEIM_D_21 */
57 471 0x80000000 /* MX53_PAD_EIM_D22__EMI_WEIM_D_22 */
58 477 0x80000000 /* MX53_PAD_EIM_D23__EMI_WEIM_D_23 */
59 492 0x80000000 /* MX53_PAD_EIM_D24__EMI_WEIM_D_24 */
60 500 0x80000000 /* MX53_PAD_EIM_D25__EMI_WEIM_D_25 */
61 508 0x80000000 /* MX53_PAD_EIM_D26__EMI_WEIM_D_26 */
62 516 0x80000000 /* MX53_PAD_EIM_D27__EMI_WEIM_D_27 */
63 524 0x80000000 /* MX53_PAD_EIM_D28__EMI_WEIM_D_28 */
64 532 0x80000000 /* MX53_PAD_EIM_D29__EMI_WEIM_D_29 */
65 540 0x80000000 /* MX53_PAD_EIM_D30__EMI_WEIM_D_30 */
66 548 0x80000000 /* MX53_PAD_EIM_D31__EMI_WEIM_D_31 */
67 637 0x80000000 /* MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 */
68 642 0x80000000 /* MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 */
69 647 0x80000000 /* MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 */
70 652 0x80000000 /* MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 */
71 657 0x80000000 /* MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 */
72 662 0x80000000 /* MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 */
73 667 0x80000000 /* MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 */
74 611 0x80000000 /* MX53_PAD_EIM_OE__EMI_WEIM_OE */
75 616 0x80000000 /* MX53_PAD_EIM_RW__EMI_WEIM_RW */
76 607 0x80000000 /* MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 */
77 >;
78 };
79 };
80 };
81
82 uart1: serial@53fbc000 {
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_uart1_2>;
85 status = "okay";
86 };
87 };
88 };
89
90 eim-cs1@f4000000 {
91 #address-cells = <1>;
92 #size-cells = <1>;
93 compatible = "fsl,eim-bus", "simple-bus";
94 reg = <0xf4000000 0x3ff0000>;
95 ranges;
96
97 lan9220@f4000000 {
98 compatible = "smsc,lan9220", "smsc,lan9115";
99 reg = <0xf4000000 0x2000000>;
100 phy-mode = "mii";
101 interrupt-parent = <&gpio2>;
102 interrupts = <31 0x8>;
103 reg-io-width = <4>;
104 /*
105 * VDD33A and VDDVARIO of LAN9220 are supplied by
106 * SW4_3V3 of LTC3589. Before the regulator driver
107 * for this PMIC is available, we use a fixed dummy
108 * 3V3 regulator to get LAN9220 driver probing work.
109 */
110 vdd33a-supply = <&reg_3p3v>;
111 vddvario-supply = <&reg_3p3v>;
112 smsc,irq-push-pull;
113 };
114 };
115
116 regulators {
117 compatible = "simple-bus";
118
119 reg_3p3v: 3p3v {
120 compatible = "regulator-fixed";
121 regulator-name = "3P3V";
122 regulator-min-microvolt = <3300000>;
123 regulator-max-microvolt = <3300000>;
124 regulator-always-on;
125 };
126 };
127
128 gpio-keys {
129 compatible = "gpio-keys";
130
131 home {
132 label = "Home";
133 gpios = <&gpio5 10 0>;
134 linux,code = <102>; /* KEY_HOME */
135 gpio-key,wakeup;
136 };
137
138 back {
139 label = "Back";
140 gpios = <&gpio5 11 0>;
141 linux,code = <158>; /* KEY_BACK */
142 gpio-key,wakeup;
143 };
144
145 program {
146 label = "Program";
147 gpios = <&gpio5 12 0>;
148 linux,code = <362>; /* KEY_PROGRAM */
149 gpio-key,wakeup;
150 };
151
152 volume-up {
153 label = "Volume Up";
154 gpios = <&gpio5 13 0>;
155 linux,code = <115>; /* KEY_VOLUMEUP */
156 };
157
158 volume-down {
159 label = "Volume Down";
160 gpios = <&gpio4 0 0>;
161 linux,code = <114>; /* KEY_VOLUMEDOWN */
162 };
163 };
164};
diff --git a/arch/arm/boot/dts/imx53-evk.dts b/arch/arm/boot/dts/imx53-evk.dts
deleted file mode 100644
index a124d1e2525..00000000000
--- a/arch/arm/boot/dts/imx53-evk.dts
+++ /dev/null
@@ -1,134 +0,0 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
14/include/ "imx53.dtsi"
15
16/ {
17 model = "Freescale i.MX53 Evaluation Kit";
18 compatible = "fsl,imx53-evk", "fsl,imx53";
19
20 memory {
21 reg = <0x70000000 0x80000000>;
22 };
23
24 soc {
25 aips@50000000 { /* AIPS1 */
26 spba@50000000 {
27 esdhc@50004000 { /* ESDHC1 */
28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_esdhc1_1>;
30 cd-gpios = <&gpio3 13 0>;
31 wp-gpios = <&gpio3 14 0>;
32 status = "okay";
33 };
34
35 ecspi@50010000 { /* ECSPI1 */
36 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_ecspi1_1>;
38 fsl,spi-num-chipselects = <2>;
39 cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
40 status = "okay";
41
42 flash: at45db321d@1 {
43 #address-cells = <1>;
44 #size-cells = <1>;
45 compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
46 spi-max-frequency = <25000000>;
47 reg = <1>;
48
49 partition@0 {
50 label = "U-Boot";
51 reg = <0x0 0x40000>;
52 read-only;
53 };
54
55 partition@40000 {
56 label = "Kernel";
57 reg = <0x40000 0x3c0000>;
58 };
59 };
60 };
61
62 esdhc@50020000 { /* ESDHC3 */
63 pinctrl-names = "default";
64 pinctrl-0 = <&pinctrl_esdhc3_1>;
65 cd-gpios = <&gpio3 11 0>;
66 wp-gpios = <&gpio3 12 0>;
67 status = "okay";
68 };
69 };
70
71 iomuxc@53fa8000 {
72 pinctrl-names = "default";
73 pinctrl-0 = <&pinctrl_hog>;
74
75 hog {
76 pinctrl_hog: hoggrp {
77 fsl,pins = <
78 424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
79 449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
80 693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
81 697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
82 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
83 705 0x80000000 /* MX53_PAD_EIM_DA14__GPIO3_14 */
84 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
85 873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
86 >;
87 };
88 };
89 };
90
91 uart1: serial@53fbc000 {
92 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_uart1_1>;
94 status = "okay";
95 };
96 };
97
98 aips@60000000 { /* AIPS2 */
99 i2c@63fc4000 { /* I2C2 */
100 pinctrl-names = "default";
101 pinctrl-0 = <&pinctrl_i2c2_1>;
102 status = "okay";
103
104 pmic: mc13892@08 {
105 compatible = "fsl,mc13892", "fsl,mc13xxx";
106 reg = <0x08>;
107 };
108
109 codec: sgtl5000@0a {
110 compatible = "fsl,sgtl5000";
111 reg = <0x0a>;
112 };
113 };
114
115 ethernet@63fec000 {
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_fec_1>;
118 phy-mode = "rmii";
119 phy-reset-gpios = <&gpio7 6 0>;
120 status = "okay";
121 };
122 };
123 };
124
125 leds {
126 compatible = "gpio-leds";
127
128 green {
129 label = "Heartbeat";
130 gpios = <&gpio7 7 0>;
131 linux,default-trigger = "heartbeat";
132 };
133 };
134};
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts
deleted file mode 100644
index b0075537195..00000000000
--- a/arch/arm/boot/dts/imx53-qsb.dts
+++ /dev/null
@@ -1,278 +0,0 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
14/include/ "imx53.dtsi"
15
16/ {
17 model = "Freescale i.MX53 Quick Start Board";
18 compatible = "fsl,imx53-qsb", "fsl,imx53";
19
20 memory {
21 reg = <0x70000000 0x40000000>;
22 };
23
24 soc {
25 aips@50000000 { /* AIPS1 */
26 spba@50000000 {
27 esdhc@50004000 { /* ESDHC1 */
28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_esdhc1_1>;
30 cd-gpios = <&gpio3 13 0>;
31 status = "okay";
32 };
33
34 ssi2: ssi@50014000 {
35 fsl,mode = "i2s-slave";
36 status = "okay";
37 };
38
39 esdhc@50020000 { /* ESDHC3 */
40 pinctrl-names = "default";
41 pinctrl-0 = <&pinctrl_esdhc3_1>;
42 cd-gpios = <&gpio3 11 0>;
43 wp-gpios = <&gpio3 12 0>;
44 status = "okay";
45 };
46 };
47
48 iomuxc@53fa8000 {
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_hog>;
51
52 hog {
53 pinctrl_hog: hoggrp {
54 fsl,pins = <
55 1071 0x80000000 /* MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK */
56 1141 0x80000000 /* MX53_PAD_GPIO_8__GPIO1_8 */
57 982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
58 989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
59 693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
60 697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
61 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
62 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
63 1149 0x80000000 /* MX53_PAD_GPIO_16__GPIO7_11 */
64 >;
65 };
66
67 led_pin_gpio7_7: led_gpio7_7@0 {
68 fsl,pins = <
69 873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
70 >;
71 };
72 };
73
74 };
75
76 uart1: serial@53fbc000 {
77 pinctrl-names = "default";
78 pinctrl-0 = <&pinctrl_uart1_1>;
79 status = "okay";
80 };
81 };
82
83 aips@60000000 { /* AIPS2 */
84 i2c@63fc4000 { /* I2C2 */
85 pinctrl-names = "default";
86 pinctrl-0 = <&pinctrl_i2c2_1>;
87 status = "okay";
88
89 sgtl5000: codec@0a {
90 compatible = "fsl,sgtl5000";
91 reg = <0x0a>;
92 VDDA-supply = <&reg_3p2v>;
93 VDDIO-supply = <&reg_3p2v>;
94 };
95 };
96
97 i2c@63fc8000 { /* I2C1 */
98 pinctrl-names = "default";
99 pinctrl-0 = <&pinctrl_i2c1_1>;
100 status = "okay";
101
102 accelerometer: mma8450@1c {
103 compatible = "fsl,mma8450";
104 reg = <0x1c>;
105 };
106
107 pmic: dialog@48 {
108 compatible = "dlg,da9053-aa", "dlg,da9052";
109 reg = <0x48>;
110 interrupt-parent = <&gpio7>;
111 interrupts = <11 0x8>; /* low-level active IRQ at GPIO7_11 */
112
113 regulators {
114 buck1_reg: buck1 {
115 regulator-min-microvolt = <500000>;
116 regulator-max-microvolt = <2075000>;
117 regulator-always-on;
118 };
119
120 buck2_reg: buck2 {
121 regulator-min-microvolt = <500000>;
122 regulator-max-microvolt = <2075000>;
123 regulator-always-on;
124 };
125
126 buck3_reg: buck3 {
127 regulator-min-microvolt = <925000>;
128 regulator-max-microvolt = <2500000>;
129 regulator-always-on;
130 };
131
132 buck4_reg: buck4 {
133 regulator-min-microvolt = <925000>;
134 regulator-max-microvolt = <2500000>;
135 regulator-always-on;
136 };
137
138 ldo1_reg: ldo1 {
139 regulator-min-microvolt = <600000>;
140 regulator-max-microvolt = <1800000>;
141 regulator-boot-on;
142 regulator-always-on;
143 };
144
145 ldo2_reg: ldo2 {
146 regulator-min-microvolt = <600000>;
147 regulator-max-microvolt = <1800000>;
148 regulator-always-on;
149 };
150
151 ldo3_reg: ldo3 {
152 regulator-min-microvolt = <600000>;
153 regulator-max-microvolt = <1800000>;
154 regulator-always-on;
155 };
156
157 ldo4_reg: ldo4 {
158 regulator-min-microvolt = <1725000>;
159 regulator-max-microvolt = <3300000>;
160 regulator-always-on;
161 };
162
163 ldo5_reg: ldo5 {
164 regulator-min-microvolt = <1725000>;
165 regulator-max-microvolt = <3300000>;
166 regulator-always-on;
167 };
168
169 ldo6_reg: ldo6 {
170 regulator-min-microvolt = <1200000>;
171 regulator-max-microvolt = <3600000>;
172 regulator-always-on;
173 };
174
175 ldo7_reg: ldo7 {
176 regulator-min-microvolt = <1200000>;
177 regulator-max-microvolt = <3600000>;
178 regulator-always-on;
179 };
180
181 ldo8_reg: ldo8 {
182 regulator-min-microvolt = <1200000>;
183 regulator-max-microvolt = <3600000>;
184 regulator-always-on;
185 };
186
187 ldo9_reg: ldo9 {
188 regulator-min-microvolt = <1200000>;
189 regulator-max-microvolt = <3600000>;
190 regulator-always-on;
191 };
192
193 ldo10_reg: ldo10 {
194 regulator-min-microvolt = <1250000>;
195 regulator-max-microvolt = <3650000>;
196 regulator-always-on;
197 };
198 };
199 };
200 };
201
202 audmux@63fd0000 {
203 pinctrl-names = "default";
204 pinctrl-0 = <&pinctrl_audmux_1>;
205 status = "okay";
206 };
207
208 ethernet@63fec000 {
209 pinctrl-names = "default";
210 pinctrl-0 = <&pinctrl_fec_1>;
211 phy-mode = "rmii";
212 phy-reset-gpios = <&gpio7 6 0>;
213 status = "okay";
214 };
215 };
216 };
217
218 gpio-keys {
219 compatible = "gpio-keys";
220
221 power {
222 label = "Power Button";
223 gpios = <&gpio1 8 0>;
224 linux,code = <116>; /* KEY_POWER */
225 gpio-key,wakeup;
226 };
227
228 volume-up {
229 label = "Volume Up";
230 gpios = <&gpio2 14 0>;
231 linux,code = <115>; /* KEY_VOLUMEUP */
232 };
233
234 volume-down {
235 label = "Volume Down";
236 gpios = <&gpio2 15 0>;
237 linux,code = <114>; /* KEY_VOLUMEDOWN */
238 };
239 };
240
241 leds {
242 compatible = "gpio-leds";
243 pinctrl-names = "default";
244 pinctrl-0 = <&led_pin_gpio7_7>;
245
246 user {
247 label = "Heartbeat";
248 gpios = <&gpio7 7 0>;
249 linux,default-trigger = "heartbeat";
250 };
251 };
252
253 regulators {
254 compatible = "simple-bus";
255
256 reg_3p2v: 3p2v {
257 compatible = "regulator-fixed";
258 regulator-name = "3P2V";
259 regulator-min-microvolt = <3200000>;
260 regulator-max-microvolt = <3200000>;
261 regulator-always-on;
262 };
263 };
264
265 sound {
266 compatible = "fsl,imx53-qsb-sgtl5000",
267 "fsl,imx-audio-sgtl5000";
268 model = "imx53-qsb-sgtl5000";
269 ssi-controller = <&ssi2>;
270 audio-codec = <&sgtl5000>;
271 audio-routing =
272 "MIC_IN", "Mic Jack",
273 "Mic Jack", "Mic Bias",
274 "Headphone Jack", "HP_OUT";
275 mux-int-port = <2>;
276 mux-ext-port = <5>;
277 };
278};
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
deleted file mode 100644
index 06c68580c84..00000000000
--- a/arch/arm/boot/dts/imx53-smd.dts
+++ /dev/null
@@ -1,190 +0,0 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
14/include/ "imx53.dtsi"
15
16/ {
17 model = "Freescale i.MX53 Smart Mobile Reference Design Board";
18 compatible = "fsl,imx53-smd", "fsl,imx53";
19
20 memory {
21 reg = <0x70000000 0x40000000>;
22 };
23
24 soc {
25 aips@50000000 { /* AIPS1 */
26 spba@50000000 {
27 esdhc@50004000 { /* ESDHC1 */
28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_esdhc1_1>;
30 cd-gpios = <&gpio3 13 0>;
31 wp-gpios = <&gpio4 11 0>;
32 status = "okay";
33 };
34
35 esdhc@50008000 { /* ESDHC2 */
36 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_esdhc2_1>;
38 non-removable;
39 status = "okay";
40 };
41
42 uart3: serial@5000c000 {
43 pinctrl-names = "default";
44 pinctrl-0 = <&pinctrl_uart3_1>;
45 fsl,uart-has-rtscts;
46 status = "okay";
47 };
48
49 ecspi@50010000 { /* ECSPI1 */
50 pinctrl-names = "default";
51 pinctrl-0 = <&pinctrl_ecspi1_1>;
52 fsl,spi-num-chipselects = <2>;
53 cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
54 status = "okay";
55
56 zigbee: mc1323@0 {
57 compatible = "fsl,mc1323";
58 spi-max-frequency = <8000000>;
59 reg = <0>;
60 };
61
62 flash: m25p32@1 {
63 #address-cells = <1>;
64 #size-cells = <1>;
65 compatible = "st,m25p32", "st,m25p";
66 spi-max-frequency = <20000000>;
67 reg = <1>;
68
69 partition@0 {
70 label = "U-Boot";
71 reg = <0x0 0x40000>;
72 read-only;
73 };
74
75 partition@40000 {
76 label = "Kernel";
77 reg = <0x40000 0x3c0000>;
78 };
79 };
80 };
81
82 esdhc@50020000 { /* ESDHC3 */
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_esdhc3_1>;
85 non-removable;
86 status = "okay";
87 };
88 };
89
90 iomuxc@53fa8000 {
91 pinctrl-names = "default";
92 pinctrl-0 = <&pinctrl_hog>;
93
94 hog {
95 pinctrl_hog: hoggrp {
96 fsl,pins = <
97 982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
98 989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
99 424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
100 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
101 449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
102 43 0x80000000 /* MX53_PAD_KEY_ROW2__GPIO4_11 */
103 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
104 >;
105 };
106 };
107 };
108
109 uart1: serial@53fbc000 {
110 pinctrl-names = "default";
111 pinctrl-0 = <&pinctrl_uart1_1>;
112 status = "okay";
113 };
114
115 uart2: serial@53fc0000 {
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_uart2_1>;
118 status = "okay";
119 };
120 };
121
122 aips@60000000 { /* AIPS2 */
123 i2c@63fc4000 { /* I2C2 */
124 pinctrl-names = "default";
125 pinctrl-0 = <&pinctrl_i2c2_1>;
126 status = "okay";
127
128 codec: sgtl5000@0a {
129 compatible = "fsl,sgtl5000";
130 reg = <0x0a>;
131 };
132
133 magnetometer: mag3110@0e {
134 compatible = "fsl,mag3110";
135 reg = <0x0e>;
136 };
137
138 touchkey: mpr121@5a {
139 compatible = "fsl,mpr121";
140 reg = <0x5a>;
141 };
142 };
143
144 i2c@63fc8000 { /* I2C1 */
145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_i2c1_1>;
147 status = "okay";
148
149 accelerometer: mma8450@1c {
150 compatible = "fsl,mma8450";
151 reg = <0x1c>;
152 };
153
154 camera: ov5642@3c {
155 compatible = "ovti,ov5642";
156 reg = <0x3c>;
157 };
158
159 pmic: dialog@48 {
160 compatible = "dialog,da9053", "dialog,da9052";
161 reg = <0x48>;
162 };
163 };
164
165 ethernet@63fec000 {
166 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_fec_1>;
168 phy-mode = "rmii";
169 phy-reset-gpios = <&gpio7 6 0>;
170 status = "okay";
171 };
172 };
173 };
174
175 gpio-keys {
176 compatible = "gpio-keys";
177
178 volume-up {
179 label = "Volume Up";
180 gpios = <&gpio2 14 0>;
181 linux,code = <115>; /* KEY_VOLUMEUP */
182 };
183
184 volume-down {
185 label = "Volume Down";
186 gpios = <&gpio2 15 0>;
187 linux,code = <114>; /* KEY_VOLUMEDOWN */
188 };
189 };
190};
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
deleted file mode 100644
index edc3f1eb669..00000000000
--- a/arch/arm/boot/dts/imx53.dtsi
+++ /dev/null
@@ -1,668 +0,0 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/include/ "skeleton.dtsi"
14
15/ {
16 aliases {
17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 serial3 = &uart4;
21 serial4 = &uart5;
22 gpio0 = &gpio1;
23 gpio1 = &gpio2;
24 gpio2 = &gpio3;
25 gpio3 = &gpio4;
26 gpio4 = &gpio5;
27 gpio5 = &gpio6;
28 gpio6 = &gpio7;
29 };
30
31 tzic: tz-interrupt-controller@0fffc000 {
32 compatible = "fsl,imx53-tzic", "fsl,tzic";
33 interrupt-controller;
34 #interrupt-cells = <1>;
35 reg = <0x0fffc000 0x4000>;
36 };
37
38 clocks {
39 #address-cells = <1>;
40 #size-cells = <0>;
41
42 ckil {
43 compatible = "fsl,imx-ckil", "fixed-clock";
44 clock-frequency = <32768>;
45 };
46
47 ckih1 {
48 compatible = "fsl,imx-ckih1", "fixed-clock";
49 clock-frequency = <22579200>;
50 };
51
52 ckih2 {
53 compatible = "fsl,imx-ckih2", "fixed-clock";
54 clock-frequency = <0>;
55 };
56
57 osc {
58 compatible = "fsl,imx-osc", "fixed-clock";
59 clock-frequency = <24000000>;
60 };
61 };
62
63 soc {
64 #address-cells = <1>;
65 #size-cells = <1>;
66 compatible = "simple-bus";
67 interrupt-parent = <&tzic>;
68 ranges;
69
70 ipu: ipu@18000000 {
71 #crtc-cells = <1>;
72 compatible = "fsl,imx53-ipu";
73 reg = <0x18000000 0x080000000>;
74 interrupts = <11 10>;
75 };
76
77 aips@50000000 { /* AIPS1 */
78 compatible = "fsl,aips-bus", "simple-bus";
79 #address-cells = <1>;
80 #size-cells = <1>;
81 reg = <0x50000000 0x10000000>;
82 ranges;
83
84 spba@50000000 {
85 compatible = "fsl,spba-bus", "simple-bus";
86 #address-cells = <1>;
87 #size-cells = <1>;
88 reg = <0x50000000 0x40000>;
89 ranges;
90
91 esdhc1: esdhc@50004000 {
92 compatible = "fsl,imx53-esdhc";
93 reg = <0x50004000 0x4000>;
94 interrupts = <1>;
95 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
96 clock-names = "ipg", "ahb", "per";
97 bus-width = <4>;
98 status = "disabled";
99 };
100
101 esdhc2: esdhc@50008000 {
102 compatible = "fsl,imx53-esdhc";
103 reg = <0x50008000 0x4000>;
104 interrupts = <2>;
105 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
106 clock-names = "ipg", "ahb", "per";
107 bus-width = <4>;
108 status = "disabled";
109 };
110
111 uart3: serial@5000c000 {
112 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
113 reg = <0x5000c000 0x4000>;
114 interrupts = <33>;
115 clocks = <&clks 32>, <&clks 33>;
116 clock-names = "ipg", "per";
117 status = "disabled";
118 };
119
120 ecspi1: ecspi@50010000 {
121 #address-cells = <1>;
122 #size-cells = <0>;
123 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
124 reg = <0x50010000 0x4000>;
125 interrupts = <36>;
126 clocks = <&clks 51>, <&clks 52>;
127 clock-names = "ipg", "per";
128 status = "disabled";
129 };
130
131 ssi2: ssi@50014000 {
132 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
133 reg = <0x50014000 0x4000>;
134 interrupts = <30>;
135 clocks = <&clks 49>;
136 fsl,fifo-depth = <15>;
137 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
138 status = "disabled";
139 };
140
141 esdhc3: esdhc@50020000 {
142 compatible = "fsl,imx53-esdhc";
143 reg = <0x50020000 0x4000>;
144 interrupts = <3>;
145 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
146 clock-names = "ipg", "ahb", "per";
147 bus-width = <4>;
148 status = "disabled";
149 };
150
151 esdhc4: esdhc@50024000 {
152 compatible = "fsl,imx53-esdhc";
153 reg = <0x50024000 0x4000>;
154 interrupts = <4>;
155 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
156 clock-names = "ipg", "ahb", "per";
157 bus-width = <4>;
158 status = "disabled";
159 };
160 };
161
162 usbotg: usb@53f80000 {
163 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
164 reg = <0x53f80000 0x0200>;
165 interrupts = <18>;
166 status = "disabled";
167 };
168
169 usbh1: usb@53f80200 {
170 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
171 reg = <0x53f80200 0x0200>;
172 interrupts = <14>;
173 status = "disabled";
174 };
175
176 usbh2: usb@53f80400 {
177 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
178 reg = <0x53f80400 0x0200>;
179 interrupts = <16>;
180 status = "disabled";
181 };
182
183 usbh3: usb@53f80600 {
184 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
185 reg = <0x53f80600 0x0200>;
186 interrupts = <17>;
187 status = "disabled";
188 };
189
190 gpio1: gpio@53f84000 {
191 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
192 reg = <0x53f84000 0x4000>;
193 interrupts = <50 51>;
194 gpio-controller;
195 #gpio-cells = <2>;
196 interrupt-controller;
197 #interrupt-cells = <2>;
198 };
199
200 gpio2: gpio@53f88000 {
201 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
202 reg = <0x53f88000 0x4000>;
203 interrupts = <52 53>;
204 gpio-controller;
205 #gpio-cells = <2>;
206 interrupt-controller;
207 #interrupt-cells = <2>;
208 };
209
210 gpio3: gpio@53f8c000 {
211 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
212 reg = <0x53f8c000 0x4000>;
213 interrupts = <54 55>;
214 gpio-controller;
215 #gpio-cells = <2>;
216 interrupt-controller;
217 #interrupt-cells = <2>;
218 };
219
220 gpio4: gpio@53f90000 {
221 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
222 reg = <0x53f90000 0x4000>;
223 interrupts = <56 57>;
224 gpio-controller;
225 #gpio-cells = <2>;
226 interrupt-controller;
227 #interrupt-cells = <2>;
228 };
229
230 wdog1: wdog@53f98000 {
231 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
232 reg = <0x53f98000 0x4000>;
233 interrupts = <58>;
234 clocks = <&clks 0>;
235 };
236
237 wdog2: wdog@53f9c000 {
238 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
239 reg = <0x53f9c000 0x4000>;
240 interrupts = <59>;
241 clocks = <&clks 0>;
242 status = "disabled";
243 };
244
245 iomuxc: iomuxc@53fa8000 {
246 compatible = "fsl,imx53-iomuxc";
247 reg = <0x53fa8000 0x4000>;
248
249 audmux {
250 pinctrl_audmux_1: audmuxgrp-1 {
251 fsl,pins = <
252 10 0x80000000 /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */
253 17 0x80000000 /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */
254 23 0x80000000 /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */
255 30 0x80000000 /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */
256 >;
257 };
258 };
259
260 fec {
261 pinctrl_fec_1: fecgrp-1 {
262 fsl,pins = <
263 820 0x80000000 /* MX53_PAD_FEC_MDC__FEC_MDC */
264 779 0x80000000 /* MX53_PAD_FEC_MDIO__FEC_MDIO */
265 786 0x80000000 /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */
266 791 0x80000000 /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */
267 796 0x80000000 /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */
268 799 0x80000000 /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */
269 804 0x80000000 /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */
270 808 0x80000000 /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */
271 811 0x80000000 /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */
272 816 0x80000000 /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */
273 >;
274 };
275 };
276
277 ecspi1 {
278 pinctrl_ecspi1_1: ecspi1grp-1 {
279 fsl,pins = <
280 433 0x80000000 /* MX53_PAD_EIM_D16__ECSPI1_SCLK */
281 439 0x80000000 /* MX53_PAD_EIM_D17__ECSPI1_MISO */
282 445 0x80000000 /* MX53_PAD_EIM_D18__ECSPI1_MOSI */
283 >;
284 };
285 };
286
287 esdhc1 {
288 pinctrl_esdhc1_1: esdhc1grp-1 {
289 fsl,pins = <
290 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
291 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
292 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
293 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
294 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
295 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
296 >;
297 };
298
299 pinctrl_esdhc1_2: esdhc1grp-2 {
300 fsl,pins = <
301 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
302 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
303 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
304 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
305 941 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */
306 948 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */
307 955 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */
308 962 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */
309 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
310 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
311 >;
312 };
313 };
314
315 esdhc2 {
316 pinctrl_esdhc2_1: esdhc2grp-1 {
317 fsl,pins = <
318 1038 0x1d5 /* MX53_PAD_SD2_CMD__ESDHC2_CMD */
319 1032 0x1d5 /* MX53_PAD_SD2_CLK__ESDHC2_CLK */
320 1062 0x1d5 /* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */
321 1056 0x1d5 /* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */
322 1050 0x1d5 /* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */
323 1044 0x1d5 /* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */
324 >;
325 };
326 };
327
328 esdhc3 {
329 pinctrl_esdhc3_1: esdhc3grp-1 {
330 fsl,pins = <
331 943 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */
332 950 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */
333 957 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */
334 964 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */
335 893 0x1d5 /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */
336 900 0x1d5 /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */
337 906 0x1d5 /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */
338 912 0x1d5 /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */
339 857 0x1d5 /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */
340 863 0x1d5 /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */
341 >;
342 };
343 };
344
345 can1 {
346 pinctrl_can1_1: can1grp-1 {
347 fsl,pins = <
348 847 0x80000000 /* MX53_PAD_PATA_INTRQ__CAN1_TXCAN */
349 853 0x80000000 /* MX53_PAD_PATA_DIOR__CAN1_RXCAN */
350 >;
351 };
352 };
353
354 can2 {
355 pinctrl_can2_1: can2grp-1 {
356 fsl,pins = <
357 67 0x80000000 /* MX53_PAD_KEY_COL4__CAN2_TXCAN */
358 74 0x80000000 /* MX53_PAD_KEY_ROW4__CAN2_RXCAN */
359 >;
360 };
361 };
362
363 i2c1 {
364 pinctrl_i2c1_1: i2c1grp-1 {
365 fsl,pins = <
366 333 0xc0000000 /* MX53_PAD_CSI0_DAT8__I2C1_SDA */
367 341 0xc0000000 /* MX53_PAD_CSI0_DAT9__I2C1_SCL */
368 >;
369 };
370 };
371
372 i2c2 {
373 pinctrl_i2c2_1: i2c2grp-1 {
374 fsl,pins = <
375 61 0xc0000000 /* MX53_PAD_KEY_ROW3__I2C2_SDA */
376 53 0xc0000000 /* MX53_PAD_KEY_COL3__I2C2_SCL */
377 >;
378 };
379 };
380
381 i2c3 {
382 pinctrl_i2c3_1: i2c3grp-1 {
383 fsl,pins = <
384 1102 0xc0000000 /* MX53_PAD_GPIO_6__I2C3_SDA */
385 1130 0xc0000000 /* MX53_PAD_GPIO_5__I2C3_SCL */
386 >;
387 };
388 };
389
390 uart1 {
391 pinctrl_uart1_1: uart1grp-1 {
392 fsl,pins = <
393 346 0x1c5 /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */
394 354 0x1c5 /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */
395 >;
396 };
397
398 pinctrl_uart1_2: uart1grp-2 {
399 fsl,pins = <
400 828 0x1c5 /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */
401 832 0x1c5 /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */
402 >;
403 };
404 };
405
406 uart2 {
407 pinctrl_uart2_1: uart2grp-1 {
408 fsl,pins = <
409 841 0x1c5 /* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */
410 836 0x1c5 /* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */
411 >;
412 };
413 };
414
415 uart3 {
416 pinctrl_uart3_1: uart3grp-1 {
417 fsl,pins = <
418 884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */
419 888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */
420 875 0x1c5 /* MX53_PAD_PATA_DA_1__UART3_CTS */
421 880 0x1c5 /* MX53_PAD_PATA_DA_2__UART3_RTS */
422 >;
423 };
424 };
425
426 uart4 {
427 pinctrl_uart4_1: uart4grp-1 {
428 fsl,pins = <
429 11 0x1c5 /* MX53_PAD_KEY_COL0__UART4_TXD_MUX */
430 18 0x1c5 /* MX53_PAD_KEY_ROW0__UART4_RXD_MUX */
431 >;
432 };
433 };
434
435 uart5 {
436 pinctrl_uart5_1: uart5grp-1 {
437 fsl,pins = <
438 24 0x1c5 /* MX53_PAD_KEY_COL1__UART5_TXD_MUX */
439 31 0x1c5 /* MX53_PAD_KEY_ROW1__UART5_RXD_MUX */
440 >;
441 };
442 };
443
444 };
445
446 pwm1: pwm@53fb4000 {
447 #pwm-cells = <2>;
448 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
449 reg = <0x53fb4000 0x4000>;
450 clocks = <&clks 37>, <&clks 38>;
451 clock-names = "ipg", "per";
452 interrupts = <61>;
453 };
454
455 pwm2: pwm@53fb8000 {
456 #pwm-cells = <2>;
457 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
458 reg = <0x53fb8000 0x4000>;
459 clocks = <&clks 39>, <&clks 40>;
460 clock-names = "ipg", "per";
461 interrupts = <94>;
462 };
463
464 uart1: serial@53fbc000 {
465 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
466 reg = <0x53fbc000 0x4000>;
467 interrupts = <31>;
468 clocks = <&clks 28>, <&clks 29>;
469 clock-names = "ipg", "per";
470 status = "disabled";
471 };
472
473 uart2: serial@53fc0000 {
474 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
475 reg = <0x53fc0000 0x4000>;
476 interrupts = <32>;
477 clocks = <&clks 30>, <&clks 31>;
478 clock-names = "ipg", "per";
479 status = "disabled";
480 };
481
482 can1: can@53fc8000 {
483 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
484 reg = <0x53fc8000 0x4000>;
485 interrupts = <82>;
486 clocks = <&clks 158>, <&clks 157>;
487 clock-names = "ipg", "per";
488 status = "disabled";
489 };
490
491 can2: can@53fcc000 {
492 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
493 reg = <0x53fcc000 0x4000>;
494 interrupts = <83>;
495 clocks = <&clks 87>, <&clks 86>;
496 clock-names = "ipg", "per";
497 status = "disabled";
498 };
499
500 clks: ccm@53fd4000{
501 compatible = "fsl,imx53-ccm";
502 reg = <0x53fd4000 0x4000>;
503 interrupts = <0 71 0x04 0 72 0x04>;
504 #clock-cells = <1>;
505 };
506
507 gpio5: gpio@53fdc000 {
508 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
509 reg = <0x53fdc000 0x4000>;
510 interrupts = <103 104>;
511 gpio-controller;
512 #gpio-cells = <2>;
513 interrupt-controller;
514 #interrupt-cells = <2>;
515 };
516
517 gpio6: gpio@53fe0000 {
518 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
519 reg = <0x53fe0000 0x4000>;
520 interrupts = <105 106>;
521 gpio-controller;
522 #gpio-cells = <2>;
523 interrupt-controller;
524 #interrupt-cells = <2>;
525 };
526
527 gpio7: gpio@53fe4000 {
528 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
529 reg = <0x53fe4000 0x4000>;
530 interrupts = <107 108>;
531 gpio-controller;
532 #gpio-cells = <2>;
533 interrupt-controller;
534 #interrupt-cells = <2>;
535 };
536
537 i2c3: i2c@53fec000 {
538 #address-cells = <1>;
539 #size-cells = <0>;
540 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
541 reg = <0x53fec000 0x4000>;
542 interrupts = <64>;
543 clocks = <&clks 88>;
544 status = "disabled";
545 };
546
547 uart4: serial@53ff0000 {
548 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
549 reg = <0x53ff0000 0x4000>;
550 interrupts = <13>;
551 clocks = <&clks 65>, <&clks 66>;
552 clock-names = "ipg", "per";
553 status = "disabled";
554 };
555 };
556
557 aips@60000000 { /* AIPS2 */
558 compatible = "fsl,aips-bus", "simple-bus";
559 #address-cells = <1>;
560 #size-cells = <1>;
561 reg = <0x60000000 0x10000000>;
562 ranges;
563
564 uart5: serial@63f90000 {
565 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
566 reg = <0x63f90000 0x4000>;
567 interrupts = <86>;
568 clocks = <&clks 67>, <&clks 68>;
569 clock-names = "ipg", "per";
570 status = "disabled";
571 };
572
573 ecspi2: ecspi@63fac000 {
574 #address-cells = <1>;
575 #size-cells = <0>;
576 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
577 reg = <0x63fac000 0x4000>;
578 interrupts = <37>;
579 clocks = <&clks 53>, <&clks 54>;
580 clock-names = "ipg", "per";
581 status = "disabled";
582 };
583
584 sdma: sdma@63fb0000 {
585 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
586 reg = <0x63fb0000 0x4000>;
587 interrupts = <6>;
588 clocks = <&clks 56>, <&clks 56>;
589 clock-names = "ipg", "ahb";
590 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
591 };
592
593 cspi: cspi@63fc0000 {
594 #address-cells = <1>;
595 #size-cells = <0>;
596 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
597 reg = <0x63fc0000 0x4000>;
598 interrupts = <38>;
599 clocks = <&clks 55>, <&clks 0>;
600 clock-names = "ipg", "per";
601 status = "disabled";
602 };
603
604 i2c2: i2c@63fc4000 {
605 #address-cells = <1>;
606 #size-cells = <0>;
607 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
608 reg = <0x63fc4000 0x4000>;
609 interrupts = <63>;
610 clocks = <&clks 35>;
611 status = "disabled";
612 };
613
614 i2c1: i2c@63fc8000 {
615 #address-cells = <1>;
616 #size-cells = <0>;
617 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
618 reg = <0x63fc8000 0x4000>;
619 interrupts = <62>;
620 clocks = <&clks 34>;
621 status = "disabled";
622 };
623
624 ssi1: ssi@63fcc000 {
625 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
626 reg = <0x63fcc000 0x4000>;
627 interrupts = <29>;
628 clocks = <&clks 48>;
629 fsl,fifo-depth = <15>;
630 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
631 status = "disabled";
632 };
633
634 audmux: audmux@63fd0000 {
635 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
636 reg = <0x63fd0000 0x4000>;
637 status = "disabled";
638 };
639
640 nfc: nand@63fdb000 {
641 compatible = "fsl,imx53-nand";
642 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
643 interrupts = <8>;
644 clocks = <&clks 60>;
645 status = "disabled";
646 };
647
648 ssi3: ssi@63fe8000 {
649 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
650 reg = <0x63fe8000 0x4000>;
651 interrupts = <96>;
652 clocks = <&clks 50>;
653 fsl,fifo-depth = <15>;
654 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
655 status = "disabled";
656 };
657
658 fec: ethernet@63fec000 {
659 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
660 reg = <0x63fec000 0x4000>;
661 interrupts = <87>;
662 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
663 clock-names = "ipg", "ahb", "ptp";
664 status = "disabled";
665 };
666 };
667 };
668};
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
deleted file mode 100644
index 5bfa02a3f85..00000000000
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ /dev/null
@@ -1,110 +0,0 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
14/include/ "imx6q.dtsi"
15
16/ {
17 model = "Freescale i.MX6 Quad Armadillo2 Board";
18 compatible = "fsl,imx6q-arm2", "fsl,imx6q";
19
20 memory {
21 reg = <0x10000000 0x80000000>;
22 };
23
24 soc {
25 gpmi-nand@00112000 {
26 pinctrl-names = "default";
27 pinctrl-0 = <&pinctrl_gpmi_nand_1>;
28 status = "disabled"; /* gpmi nand conflicts with SD */
29 };
30
31 aips-bus@02000000 { /* AIPS1 */
32 iomuxc@020e0000 {
33 pinctrl-names = "default";
34 pinctrl-0 = <&pinctrl_hog>;
35
36 hog {
37 pinctrl_hog: hoggrp {
38 fsl,pins = <
39 176 0x80000000 /* MX6Q_PAD_EIM_D25__GPIO_3_25 */
40 >;
41 };
42 };
43
44 arm2 {
45 pinctrl_usdhc3_arm2: usdhc3grp-arm2 {
46 fsl,pins = <
47 1363 0x80000000 /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */
48 1369 0x80000000 /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */
49 >;
50 };
51 };
52 };
53 };
54
55 aips-bus@02100000 { /* AIPS2 */
56 ethernet@02188000 {
57 pinctrl-names = "default";
58 pinctrl-0 = <&pinctrl_enet_2>;
59 phy-mode = "rgmii";
60 status = "okay";
61 };
62
63 usdhc@02198000 { /* uSDHC3 */
64 cd-gpios = <&gpio6 11 0>;
65 wp-gpios = <&gpio6 14 0>;
66 vmmc-supply = <&reg_3p3v>;
67 pinctrl-names = "default";
68 pinctrl-0 = <&pinctrl_usdhc3_1
69 &pinctrl_usdhc3_arm2>;
70 status = "okay";
71 };
72
73 usdhc@0219c000 { /* uSDHC4 */
74 non-removable;
75 vmmc-supply = <&reg_3p3v>;
76 pinctrl-names = "default";
77 pinctrl-0 = <&pinctrl_usdhc4_1>;
78 status = "okay";
79 };
80
81 uart4: serial@021f0000 {
82 pinctrl-names = "default";
83 pinctrl-0 = <&pinctrl_uart4_1>;
84 status = "okay";
85 };
86 };
87 };
88
89 regulators {
90 compatible = "simple-bus";
91
92 reg_3p3v: 3p3v {
93 compatible = "regulator-fixed";
94 regulator-name = "3P3V";
95 regulator-min-microvolt = <3300000>;
96 regulator-max-microvolt = <3300000>;
97 regulator-always-on;
98 };
99 };
100
101 leds {
102 compatible = "gpio-leds";
103
104 debug-led {
105 label = "Heartbeat";
106 gpios = <&gpio3 25 0>;
107 linux,default-trigger = "heartbeat";
108 };
109 };
110};
diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-sabreauto.dts
deleted file mode 100644
index 826e4ad1477..00000000000
--- a/arch/arm/boot/dts/imx6q-sabreauto.dts
+++ /dev/null
@@ -1,64 +0,0 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
14/include/ "imx6q.dtsi"
15
16/ {
17 model = "Freescale i.MX6 Quad SABRE Automotive Board";
18 compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
19
20 memory {
21 reg = <0x10000000 0x80000000>;
22 };
23
24 soc {
25 aips-bus@02000000 { /* AIPS1 */
26 iomuxc@020e0000 {
27 pinctrl-names = "default";
28 pinctrl-0 = <&pinctrl_hog>;
29
30 hog {
31 pinctrl_hog: hoggrp {
32 fsl,pins = <
33 1376 0x80000000 /* MX6Q_PAD_NANDF_CS2__GPIO_6_15 */
34 13 0x80000000 /* MX6Q_PAD_SD2_DAT2__GPIO_1_13 */
35 >;
36 };
37 };
38 };
39 };
40
41 aips-bus@02100000 { /* AIPS2 */
42 uart4: serial@021f0000 {
43 pinctrl-names = "default";
44 pinctrl-0 = <&pinctrl_uart4_1>;
45 status = "okay";
46 };
47
48 ethernet@02188000 {
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_enet_2>;
51 phy-mode = "rgmii";
52 status = "okay";
53 };
54
55 usdhc@02198000 { /* uSDHC3 */
56 pinctrl-names = "default";
57 pinctrl-0 = <&pinctrl_usdhc3_1>;
58 cd-gpios = <&gpio6 15 0>;
59 wp-gpios = <&gpio1 13 0>;
60 status = "okay";
61 };
62 };
63 };
64};
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
deleted file mode 100644
index d152328285a..00000000000
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ /dev/null
@@ -1,178 +0,0 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
14/include/ "imx6q.dtsi"
15
16/ {
17 model = "Freescale i.MX6 Quad SABRE Lite Board";
18 compatible = "fsl,imx6q-sabrelite", "fsl,imx6q";
19
20 memory {
21 reg = <0x10000000 0x40000000>;
22 };
23
24 soc {
25 aips-bus@02000000 { /* AIPS1 */
26 spba-bus@02000000 {
27 ecspi@02008000 { /* eCSPI1 */
28 fsl,spi-num-chipselects = <1>;
29 cs-gpios = <&gpio3 19 0>;
30 pinctrl-names = "default";
31 pinctrl-0 = <&pinctrl_ecspi1_1>;
32 status = "okay";
33
34 flash: m25p80@0 {
35 compatible = "sst,sst25vf016b";
36 spi-max-frequency = <20000000>;
37 reg = <0>;
38 };
39 };
40
41 ssi1: ssi@02028000 {
42 fsl,mode = "i2s-slave";
43 status = "okay";
44 };
45 };
46
47 iomuxc@020e0000 {
48 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_hog>;
50
51 hog {
52 pinctrl_hog: hoggrp {
53 fsl,pins = <
54 1450 0x80000000 /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */
55 1458 0x80000000 /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */
56 121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
57 144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
58 152 0x80000000 /* MX6Q_PAD_EIM_D23__GPIO_3_23 */
59 1262 0x80000000 /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */
60 1270 0x1f0b0 /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */
61 953 0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */
62 >;
63 };
64 };
65 };
66 };
67
68 aips-bus@02100000 { /* AIPS2 */
69 usb@02184000 { /* USB OTG */
70 vbus-supply = <&reg_usb_otg_vbus>;
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_usbotg_1>;
73 disable-over-current;
74 status = "okay";
75 };
76
77 usb@02184200 { /* USB1 */
78 status = "okay";
79 };
80
81 ethernet@02188000 {
82 pinctrl-names = "default";
83 pinctrl-0 = <&pinctrl_enet_1>;
84 phy-mode = "rgmii";
85 phy-reset-gpios = <&gpio3 23 0>;
86 status = "okay";
87 };
88
89 usdhc@02198000 { /* uSDHC3 */
90 pinctrl-names = "default";
91 pinctrl-0 = <&pinctrl_usdhc3_2>;
92 cd-gpios = <&gpio7 0 0>;
93 wp-gpios = <&gpio7 1 0>;
94 vmmc-supply = <&reg_3p3v>;
95 status = "okay";
96 };
97
98 usdhc@0219c000 { /* uSDHC4 */
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_usdhc4_2>;
101 cd-gpios = <&gpio2 6 0>;
102 wp-gpios = <&gpio2 7 0>;
103 vmmc-supply = <&reg_3p3v>;
104 status = "okay";
105 };
106
107 audmux@021d8000 {
108 status = "okay";
109 pinctrl-names = "default";
110 pinctrl-0 = <&pinctrl_audmux_1>;
111 };
112
113 uart2: serial@021e8000 {
114 status = "okay";
115 pinctrl-names = "default";
116 pinctrl-0 = <&pinctrl_uart2_1>;
117 };
118
119 i2c@021a0000 { /* I2C1 */
120 status = "okay";
121 clock-frequency = <100000>;
122 pinctrl-names = "default";
123 pinctrl-0 = <&pinctrl_i2c1_1>;
124
125 codec: sgtl5000@0a {
126 compatible = "fsl,sgtl5000";
127 reg = <0x0a>;
128 clocks = <&clks 169>;
129 VDDA-supply = <&reg_2p5v>;
130 VDDIO-supply = <&reg_3p3v>;
131 };
132 };
133 };
134 };
135
136 regulators {
137 compatible = "simple-bus";
138
139 reg_2p5v: 2p5v {
140 compatible = "regulator-fixed";
141 regulator-name = "2P5V";
142 regulator-min-microvolt = <2500000>;
143 regulator-max-microvolt = <2500000>;
144 regulator-always-on;
145 };
146
147 reg_3p3v: 3p3v {
148 compatible = "regulator-fixed";
149 regulator-name = "3P3V";
150 regulator-min-microvolt = <3300000>;
151 regulator-max-microvolt = <3300000>;
152 regulator-always-on;
153 };
154
155 reg_usb_otg_vbus: usb_otg_vbus {
156 compatible = "regulator-fixed";
157 regulator-name = "usb_otg_vbus";
158 regulator-min-microvolt = <5000000>;
159 regulator-max-microvolt = <5000000>;
160 gpio = <&gpio3 22 0>;
161 enable-active-high;
162 };
163 };
164
165 sound {
166 compatible = "fsl,imx6q-sabrelite-sgtl5000",
167 "fsl,imx-audio-sgtl5000";
168 model = "imx6q-sabrelite-sgtl5000";
169 ssi-controller = <&ssi1>;
170 audio-codec = <&codec>;
171 audio-routing =
172 "MIC_IN", "Mic Jack",
173 "Mic Jack", "Mic Bias",
174 "Headphone Jack", "HP_OUT";
175 mux-int-port = <1>;
176 mux-ext-port = <4>;
177 };
178};
diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts
deleted file mode 100644
index a42402562b7..00000000000
--- a/arch/arm/boot/dts/imx6q-sabresd.dts
+++ /dev/null
@@ -1,94 +0,0 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
14/include/ "imx6q.dtsi"
15
16/ {
17 model = "Freescale i.MX6Q SABRE Smart Device Board";
18 compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
19
20 memory {
21 reg = <0x10000000 0x40000000>;
22 };
23
24 soc {
25 aips-bus@02000000 { /* AIPS1 */
26 spba-bus@02000000 {
27 uart1: serial@02020000 {
28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_uart1_1>;
30 status = "okay";
31 };
32 };
33
34 iomuxc@020e0000 {
35 pinctrl-names = "default";
36 pinctrl-0 = <&pinctrl_hog>;
37
38 hog {
39 pinctrl_hog: hoggrp {
40 fsl,pins = <
41 1004 0x80000000 /* MX6Q_PAD_GPIO_4__GPIO_1_4 */
42 1012 0x80000000 /* MX6Q_PAD_GPIO_5__GPIO_1_5 */
43 1402 0x80000000 /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */
44 1410 0x80000000 /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */
45 1418 0x80000000 /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */
46 1426 0x80000000 /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */
47 >;
48 };
49 };
50 };
51 };
52
53 aips-bus@02100000 { /* AIPS2 */
54 ethernet@02188000 {
55 pinctrl-names = "default";
56 pinctrl-0 = <&pinctrl_enet_1>;
57 phy-mode = "rgmii";
58 status = "okay";
59 };
60
61 usdhc@02194000 { /* uSDHC2 */
62 pinctrl-names = "default";
63 pinctrl-0 = <&pinctrl_usdhc2_1>;
64 cd-gpios = <&gpio2 2 0>;
65 wp-gpios = <&gpio2 3 0>;
66 status = "okay";
67 };
68
69 usdhc@02198000 { /* uSDHC3 */
70 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_usdhc3_1>;
72 cd-gpios = <&gpio2 0 0>;
73 wp-gpios = <&gpio2 1 0>;
74 status = "okay";
75 };
76 };
77 };
78
79 gpio-keys {
80 compatible = "gpio-keys";
81
82 volume-up {
83 label = "Volume Up";
84 gpios = <&gpio1 4 0>;
85 linux,code = <115>; /* KEY_VOLUMEUP */
86 };
87
88 volume-down {
89 label = "Volume Down";
90 gpios = <&gpio1 5 0>;
91 linux,code = <114>; /* KEY_VOLUMEDOWN */
92 };
93 };
94};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
deleted file mode 100644
index d6265ca9711..00000000000
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ /dev/null
@@ -1,1060 +0,0 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/include/ "skeleton.dtsi"
14
15/ {
16 aliases {
17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 serial3 = &uart4;
21 serial4 = &uart5;
22 gpio0 = &gpio1;
23 gpio1 = &gpio2;
24 gpio2 = &gpio3;
25 gpio3 = &gpio4;
26 gpio4 = &gpio5;
27 gpio5 = &gpio6;
28 gpio6 = &gpio7;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 cpu@0 {
36 compatible = "arm,cortex-a9";
37 reg = <0>;
38 next-level-cache = <&L2>;
39 operating-points = <
40 /* kHz uV */
41 792000 1100000
42 396000 950000
43 198000 850000
44 >;
45 clock-latency = <61036>; /* two CLK32 periods */
46 cpu0-supply = <&reg_cpu>;
47 };
48
49 cpu@1 {
50 compatible = "arm,cortex-a9";
51 reg = <1>;
52 next-level-cache = <&L2>;
53 };
54
55 cpu@2 {
56 compatible = "arm,cortex-a9";
57 reg = <2>;
58 next-level-cache = <&L2>;
59 };
60
61 cpu@3 {
62 compatible = "arm,cortex-a9";
63 reg = <3>;
64 next-level-cache = <&L2>;
65 };
66 };
67
68 intc: interrupt-controller@00a01000 {
69 compatible = "arm,cortex-a9-gic";
70 #interrupt-cells = <3>;
71 #address-cells = <1>;
72 #size-cells = <1>;
73 interrupt-controller;
74 reg = <0x00a01000 0x1000>,
75 <0x00a00100 0x100>;
76 };
77
78 clocks {
79 #address-cells = <1>;
80 #size-cells = <0>;
81
82 ckil {
83 compatible = "fsl,imx-ckil", "fixed-clock";
84 clock-frequency = <32768>;
85 };
86
87 ckih1 {
88 compatible = "fsl,imx-ckih1", "fixed-clock";
89 clock-frequency = <0>;
90 };
91
92 osc {
93 compatible = "fsl,imx-osc", "fixed-clock";
94 clock-frequency = <24000000>;
95 };
96 };
97
98 soc {
99 #address-cells = <1>;
100 #size-cells = <1>;
101 compatible = "simple-bus";
102 interrupt-parent = <&intc>;
103 ranges;
104
105 dma-apbh@00110000 {
106 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
107 reg = <0x00110000 0x2000>;
108 clocks = <&clks 106>;
109 };
110
111 nfc: gpmi-nand@00112000 {
112 compatible = "fsl,imx6q-gpmi-nand";
113 #address-cells = <1>;
114 #size-cells = <1>;
115 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
116 reg-names = "gpmi-nand", "bch";
117 interrupts = <0 13 0x04>, <0 15 0x04>;
118 interrupt-names = "gpmi-dma", "bch";
119 clocks = <&clks 152>, <&clks 153>, <&clks 151>,
120 <&clks 150>, <&clks 149>;
121 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
122 "gpmi_bch_apb", "per1_bch";
123 fsl,gpmi-dma-channel = <0>;
124 status = "disabled";
125 };
126
127 timer@00a00600 {
128 compatible = "arm,cortex-a9-twd-timer";
129 reg = <0x00a00600 0x20>;
130 interrupts = <1 13 0xf01>;
131 };
132
133 L2: l2-cache@00a02000 {
134 compatible = "arm,pl310-cache";
135 reg = <0x00a02000 0x1000>;
136 interrupts = <0 92 0x04>;
137 cache-unified;
138 cache-level = <2>;
139 };
140
141 aips-bus@02000000 { /* AIPS1 */
142 compatible = "fsl,aips-bus", "simple-bus";
143 #address-cells = <1>;
144 #size-cells = <1>;
145 reg = <0x02000000 0x100000>;
146 ranges;
147
148 spba-bus@02000000 {
149 compatible = "fsl,spba-bus", "simple-bus";
150 #address-cells = <1>;
151 #size-cells = <1>;
152 reg = <0x02000000 0x40000>;
153 ranges;
154
155 spdif: spdif@02004000 {
156 reg = <0x02004000 0x4000>;
157 interrupts = <0 52 0x04>;
158 };
159
160 ecspi1: ecspi@02008000 {
161 #address-cells = <1>;
162 #size-cells = <0>;
163 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
164 reg = <0x02008000 0x4000>;
165 interrupts = <0 31 0x04>;
166 clocks = <&clks 112>, <&clks 112>;
167 clock-names = "ipg", "per";
168 status = "disabled";
169 };
170
171 ecspi2: ecspi@0200c000 {
172 #address-cells = <1>;
173 #size-cells = <0>;
174 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
175 reg = <0x0200c000 0x4000>;
176 interrupts = <0 32 0x04>;
177 clocks = <&clks 113>, <&clks 113>;
178 clock-names = "ipg", "per";
179 status = "disabled";
180 };
181
182 ecspi3: ecspi@02010000 {
183 #address-cells = <1>;
184 #size-cells = <0>;
185 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
186 reg = <0x02010000 0x4000>;
187 interrupts = <0 33 0x04>;
188 clocks = <&clks 114>, <&clks 114>;
189 clock-names = "ipg", "per";
190 status = "disabled";
191 };
192
193 ecspi4: ecspi@02014000 {
194 #address-cells = <1>;
195 #size-cells = <0>;
196 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
197 reg = <0x02014000 0x4000>;
198 interrupts = <0 34 0x04>;
199 clocks = <&clks 115>, <&clks 115>;
200 clock-names = "ipg", "per";
201 status = "disabled";
202 };
203
204 ecspi5: ecspi@02018000 {
205 #address-cells = <1>;
206 #size-cells = <0>;
207 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
208 reg = <0x02018000 0x4000>;
209 interrupts = <0 35 0x04>;
210 clocks = <&clks 116>, <&clks 116>;
211 clock-names = "ipg", "per";
212 status = "disabled";
213 };
214
215 uart1: serial@02020000 {
216 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
217 reg = <0x02020000 0x4000>;
218 interrupts = <0 26 0x04>;
219 clocks = <&clks 160>, <&clks 161>;
220 clock-names = "ipg", "per";
221 status = "disabled";
222 };
223
224 esai: esai@02024000 {
225 reg = <0x02024000 0x4000>;
226 interrupts = <0 51 0x04>;
227 };
228
229 ssi1: ssi@02028000 {
230 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
231 reg = <0x02028000 0x4000>;
232 interrupts = <0 46 0x04>;
233 clocks = <&clks 178>;
234 fsl,fifo-depth = <15>;
235 fsl,ssi-dma-events = <38 37>;
236 status = "disabled";
237 };
238
239 ssi2: ssi@0202c000 {
240 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
241 reg = <0x0202c000 0x4000>;
242 interrupts = <0 47 0x04>;
243 clocks = <&clks 179>;
244 fsl,fifo-depth = <15>;
245 fsl,ssi-dma-events = <42 41>;
246 status = "disabled";
247 };
248
249 ssi3: ssi@02030000 {
250 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
251 reg = <0x02030000 0x4000>;
252 interrupts = <0 48 0x04>;
253 clocks = <&clks 180>;
254 fsl,fifo-depth = <15>;
255 fsl,ssi-dma-events = <46 45>;
256 status = "disabled";
257 };
258
259 asrc: asrc@02034000 {
260 reg = <0x02034000 0x4000>;
261 interrupts = <0 50 0x04>;
262 };
263
264 spba@0203c000 {
265 reg = <0x0203c000 0x4000>;
266 };
267 };
268
269 vpu: vpu@02040000 {
270 reg = <0x02040000 0x3c000>;
271 interrupts = <0 3 0x04 0 12 0x04>;
272 };
273
274 aipstz@0207c000 { /* AIPSTZ1 */
275 reg = <0x0207c000 0x4000>;
276 };
277
278 pwm1: pwm@02080000 {
279 #pwm-cells = <2>;
280 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
281 reg = <0x02080000 0x4000>;
282 interrupts = <0 83 0x04>;
283 clocks = <&clks 62>, <&clks 145>;
284 clock-names = "ipg", "per";
285 };
286
287 pwm2: pwm@02084000 {
288 #pwm-cells = <2>;
289 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
290 reg = <0x02084000 0x4000>;
291 interrupts = <0 84 0x04>;
292 clocks = <&clks 62>, <&clks 146>;
293 clock-names = "ipg", "per";
294 };
295
296 pwm3: pwm@02088000 {
297 #pwm-cells = <2>;
298 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
299 reg = <0x02088000 0x4000>;
300 interrupts = <0 85 0x04>;
301 clocks = <&clks 62>, <&clks 147>;
302 clock-names = "ipg", "per";
303 };
304
305 pwm4: pwm@0208c000 {
306 #pwm-cells = <2>;
307 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
308 reg = <0x0208c000 0x4000>;
309 interrupts = <0 86 0x04>;
310 clocks = <&clks 62>, <&clks 148>;
311 clock-names = "ipg", "per";
312 };
313
314 can1: flexcan@02090000 {
315 reg = <0x02090000 0x4000>;
316 interrupts = <0 110 0x04>;
317 };
318
319 can2: flexcan@02094000 {
320 reg = <0x02094000 0x4000>;
321 interrupts = <0 111 0x04>;
322 };
323
324 gpt: gpt@02098000 {
325 compatible = "fsl,imx6q-gpt";
326 reg = <0x02098000 0x4000>;
327 interrupts = <0 55 0x04>;
328 };
329
330 gpio1: gpio@0209c000 {
331 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
332 reg = <0x0209c000 0x4000>;
333 interrupts = <0 66 0x04 0 67 0x04>;
334 gpio-controller;
335 #gpio-cells = <2>;
336 interrupt-controller;
337 #interrupt-cells = <2>;
338 };
339
340 gpio2: gpio@020a0000 {
341 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
342 reg = <0x020a0000 0x4000>;
343 interrupts = <0 68 0x04 0 69 0x04>;
344 gpio-controller;
345 #gpio-cells = <2>;
346 interrupt-controller;
347 #interrupt-cells = <2>;
348 };
349
350 gpio3: gpio@020a4000 {
351 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
352 reg = <0x020a4000 0x4000>;
353 interrupts = <0 70 0x04 0 71 0x04>;
354 gpio-controller;
355 #gpio-cells = <2>;
356 interrupt-controller;
357 #interrupt-cells = <2>;
358 };
359
360 gpio4: gpio@020a8000 {
361 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
362 reg = <0x020a8000 0x4000>;
363 interrupts = <0 72 0x04 0 73 0x04>;
364 gpio-controller;
365 #gpio-cells = <2>;
366 interrupt-controller;
367 #interrupt-cells = <2>;
368 };
369
370 gpio5: gpio@020ac000 {
371 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
372 reg = <0x020ac000 0x4000>;
373 interrupts = <0 74 0x04 0 75 0x04>;
374 gpio-controller;
375 #gpio-cells = <2>;
376 interrupt-controller;
377 #interrupt-cells = <2>;
378 };
379
380 gpio6: gpio@020b0000 {
381 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
382 reg = <0x020b0000 0x4000>;
383 interrupts = <0 76 0x04 0 77 0x04>;
384 gpio-controller;
385 #gpio-cells = <2>;
386 interrupt-controller;
387 #interrupt-cells = <2>;
388 };
389
390 gpio7: gpio@020b4000 {
391 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
392 reg = <0x020b4000 0x4000>;
393 interrupts = <0 78 0x04 0 79 0x04>;
394 gpio-controller;
395 #gpio-cells = <2>;
396 interrupt-controller;
397 #interrupt-cells = <2>;
398 };
399
400 kpp: kpp@020b8000 {
401 reg = <0x020b8000 0x4000>;
402 interrupts = <0 82 0x04>;
403 };
404
405 wdog1: wdog@020bc000 {
406 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
407 reg = <0x020bc000 0x4000>;
408 interrupts = <0 80 0x04>;
409 clocks = <&clks 0>;
410 };
411
412 wdog2: wdog@020c0000 {
413 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
414 reg = <0x020c0000 0x4000>;
415 interrupts = <0 81 0x04>;
416 clocks = <&clks 0>;
417 status = "disabled";
418 };
419
420 clks: ccm@020c4000 {
421 compatible = "fsl,imx6q-ccm";
422 reg = <0x020c4000 0x4000>;
423 interrupts = <0 87 0x04 0 88 0x04>;
424 #clock-cells = <1>;
425 };
426
427 anatop: anatop@020c8000 {
428 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
429 reg = <0x020c8000 0x1000>;
430 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
431
432 regulator-1p1@110 {
433 compatible = "fsl,anatop-regulator";
434 regulator-name = "vdd1p1";
435 regulator-min-microvolt = <800000>;
436 regulator-max-microvolt = <1375000>;
437 regulator-always-on;
438 anatop-reg-offset = <0x110>;
439 anatop-vol-bit-shift = <8>;
440 anatop-vol-bit-width = <5>;
441 anatop-min-bit-val = <4>;
442 anatop-min-voltage = <800000>;
443 anatop-max-voltage = <1375000>;
444 };
445
446 regulator-3p0@120 {
447 compatible = "fsl,anatop-regulator";
448 regulator-name = "vdd3p0";
449 regulator-min-microvolt = <2800000>;
450 regulator-max-microvolt = <3150000>;
451 regulator-always-on;
452 anatop-reg-offset = <0x120>;
453 anatop-vol-bit-shift = <8>;
454 anatop-vol-bit-width = <5>;
455 anatop-min-bit-val = <0>;
456 anatop-min-voltage = <2625000>;
457 anatop-max-voltage = <3400000>;
458 };
459
460 regulator-2p5@130 {
461 compatible = "fsl,anatop-regulator";
462 regulator-name = "vdd2p5";
463 regulator-min-microvolt = <2000000>;
464 regulator-max-microvolt = <2750000>;
465 regulator-always-on;
466 anatop-reg-offset = <0x130>;
467 anatop-vol-bit-shift = <8>;
468 anatop-vol-bit-width = <5>;
469 anatop-min-bit-val = <0>;
470 anatop-min-voltage = <2000000>;
471 anatop-max-voltage = <2750000>;
472 };
473
474 reg_cpu: regulator-vddcore@140 {
475 compatible = "fsl,anatop-regulator";
476 regulator-name = "cpu";
477 regulator-min-microvolt = <725000>;
478 regulator-max-microvolt = <1450000>;
479 regulator-always-on;
480 anatop-reg-offset = <0x140>;
481 anatop-vol-bit-shift = <0>;
482 anatop-vol-bit-width = <5>;
483 anatop-min-bit-val = <1>;
484 anatop-min-voltage = <725000>;
485 anatop-max-voltage = <1450000>;
486 };
487
488 regulator-vddpu@140 {
489 compatible = "fsl,anatop-regulator";
490 regulator-name = "vddpu";
491 regulator-min-microvolt = <725000>;
492 regulator-max-microvolt = <1450000>;
493 regulator-always-on;
494 anatop-reg-offset = <0x140>;
495 anatop-vol-bit-shift = <9>;
496 anatop-vol-bit-width = <5>;
497 anatop-min-bit-val = <1>;
498 anatop-min-voltage = <725000>;
499 anatop-max-voltage = <1450000>;
500 };
501
502 regulator-vddsoc@140 {
503 compatible = "fsl,anatop-regulator";
504 regulator-name = "vddsoc";
505 regulator-min-microvolt = <725000>;
506 regulator-max-microvolt = <1450000>;
507 regulator-always-on;
508 anatop-reg-offset = <0x140>;
509 anatop-vol-bit-shift = <18>;
510 anatop-vol-bit-width = <5>;
511 anatop-min-bit-val = <1>;
512 anatop-min-voltage = <725000>;
513 anatop-max-voltage = <1450000>;
514 };
515 };
516
517 usbphy1: usbphy@020c9000 {
518 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
519 reg = <0x020c9000 0x1000>;
520 interrupts = <0 44 0x04>;
521 clocks = <&clks 182>;
522 };
523
524 usbphy2: usbphy@020ca000 {
525 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
526 reg = <0x020ca000 0x1000>;
527 interrupts = <0 45 0x04>;
528 clocks = <&clks 183>;
529 };
530
531 snvs@020cc000 {
532 compatible = "fsl,sec-v4.0-mon", "simple-bus";
533 #address-cells = <1>;
534 #size-cells = <1>;
535 ranges = <0 0x020cc000 0x4000>;
536
537 snvs-rtc-lp@34 {
538 compatible = "fsl,sec-v4.0-mon-rtc-lp";
539 reg = <0x34 0x58>;
540 interrupts = <0 19 0x04 0 20 0x04>;
541 };
542 };
543
544 epit1: epit@020d0000 { /* EPIT1 */
545 reg = <0x020d0000 0x4000>;
546 interrupts = <0 56 0x04>;
547 };
548
549 epit2: epit@020d4000 { /* EPIT2 */
550 reg = <0x020d4000 0x4000>;
551 interrupts = <0 57 0x04>;
552 };
553
554 src: src@020d8000 {
555 compatible = "fsl,imx6q-src";
556 reg = <0x020d8000 0x4000>;
557 interrupts = <0 91 0x04 0 96 0x04>;
558 };
559
560 gpc: gpc@020dc000 {
561 compatible = "fsl,imx6q-gpc";
562 reg = <0x020dc000 0x4000>;
563 interrupts = <0 89 0x04 0 90 0x04>;
564 };
565
566 gpr: iomuxc-gpr@020e0000 {
567 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
568 reg = <0x020e0000 0x38>;
569 };
570
571 iomuxc: iomuxc@020e0000 {
572 compatible = "fsl,imx6q-iomuxc";
573 reg = <0x020e0000 0x4000>;
574
575 /* shared pinctrl settings */
576 audmux {
577 pinctrl_audmux_1: audmux-1 {
578 fsl,pins = <
579 18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
580 1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
581 11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
582 3 0x80000000 /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
583 >;
584 };
585 };
586
587 ecspi1 {
588 pinctrl_ecspi1_1: ecspi1grp-1 {
589 fsl,pins = <
590 101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
591 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
592 94 0x100b1 /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
593 >;
594 };
595 };
596
597 enet {
598 pinctrl_enet_1: enetgrp-1 {
599 fsl,pins = <
600 695 0x1b0b0 /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */
601 756 0x1b0b0 /* MX6Q_PAD_ENET_MDC__ENET_MDC */
602 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
603 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
604 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
605 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
606 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
607 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
608 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
609 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
610 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
611 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
612 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
613 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
614 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
615 1033 0x4001b0a8 /* MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT*/
616 >;
617 };
618
619 pinctrl_enet_2: enetgrp-2 {
620 fsl,pins = <
621 890 0x1b0b0 /* MX6Q_PAD_KEY_COL1__ENET_MDIO */
622 909 0x1b0b0 /* MX6Q_PAD_KEY_COL2__ENET_MDC */
623 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
624 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
625 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
626 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
627 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
628 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
629 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
630 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
631 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
632 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
633 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
634 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
635 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
636 >;
637 };
638 };
639
640 gpmi-nand {
641 pinctrl_gpmi_nand_1: gpmi-nand-1 {
642 fsl,pins = <
643 1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
644 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
645 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
646 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
647 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
648 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
649 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
650 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
651 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
652 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
653 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
654 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
655 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
656 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
657 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
658 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
659 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
660 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
661 1463 0x00b1 /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
662 >;
663 };
664 };
665
666 i2c1 {
667 pinctrl_i2c1_1: i2c1grp-1 {
668 fsl,pins = <
669 137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */
670 196 0x4001b8b1 /* MX6Q_PAD_EIM_D28__I2C1_SDA */
671 >;
672 };
673 };
674
675 uart1 {
676 pinctrl_uart1_1: uart1grp-1 {
677 fsl,pins = <
678 1140 0x1b0b1 /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */
679 1148 0x1b0b1 /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */
680 >;
681 };
682 };
683
684 uart2 {
685 pinctrl_uart2_1: uart2grp-1 {
686 fsl,pins = <
687 183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */
688 191 0x1b0b1 /* MX6Q_PAD_EIM_D27__UART2_RXD */
689 >;
690 };
691 };
692
693 uart4 {
694 pinctrl_uart4_1: uart4grp-1 {
695 fsl,pins = <
696 877 0x1b0b1 /* MX6Q_PAD_KEY_COL0__UART4_TXD */
697 885 0x1b0b1 /* MX6Q_PAD_KEY_ROW0__UART4_RXD */
698 >;
699 };
700 };
701
702 usbotg {
703 pinctrl_usbotg_1: usbotggrp-1 {
704 fsl,pins = <
705 1592 0x17059 /* MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID */
706 >;
707 };
708 };
709
710 usdhc2 {
711 pinctrl_usdhc2_1: usdhc2grp-1 {
712 fsl,pins = <
713 1577 0x17059 /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */
714 1569 0x10059 /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */
715 16 0x17059 /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */
716 0 0x17059 /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */
717 8 0x17059 /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */
718 1583 0x17059 /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */
719 1430 0x17059 /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */
720 1438 0x17059 /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */
721 1446 0x17059 /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */
722 1454 0x17059 /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */
723 >;
724 };
725 };
726
727 usdhc3 {
728 pinctrl_usdhc3_1: usdhc3grp-1 {
729 fsl,pins = <
730 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
731 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
732 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
733 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
734 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
735 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
736 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
737 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
738 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
739 1241 0x17059 /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
740 >;
741 };
742
743 pinctrl_usdhc3_2: usdhc3grp-2 {
744 fsl,pins = <
745 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
746 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
747 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
748 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
749 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
750 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
751 >;
752 };
753 };
754
755 usdhc4 {
756 pinctrl_usdhc4_1: usdhc4grp-1 {
757 fsl,pins = <
758 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
759 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
760 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
761 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
762 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
763 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
764 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
765 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
766 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
767 1517 0x17059 /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
768 >;
769 };
770
771 pinctrl_usdhc4_2: usdhc4grp-2 {
772 fsl,pins = <
773 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
774 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
775 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
776 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
777 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
778 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
779 >;
780 };
781 };
782 };
783
784 dcic1: dcic@020e4000 {
785 reg = <0x020e4000 0x4000>;
786 interrupts = <0 124 0x04>;
787 };
788
789 dcic2: dcic@020e8000 {
790 reg = <0x020e8000 0x4000>;
791 interrupts = <0 125 0x04>;
792 };
793
794 sdma: sdma@020ec000 {
795 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
796 reg = <0x020ec000 0x4000>;
797 interrupts = <0 2 0x04>;
798 clocks = <&clks 155>, <&clks 155>;
799 clock-names = "ipg", "ahb";
800 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q-to1.bin";
801 };
802 };
803
804 aips-bus@02100000 { /* AIPS2 */
805 compatible = "fsl,aips-bus", "simple-bus";
806 #address-cells = <1>;
807 #size-cells = <1>;
808 reg = <0x02100000 0x100000>;
809 ranges;
810
811 caam@02100000 {
812 reg = <0x02100000 0x40000>;
813 interrupts = <0 105 0x04 0 106 0x04>;
814 };
815
816 aipstz@0217c000 { /* AIPSTZ2 */
817 reg = <0x0217c000 0x4000>;
818 };
819
820 usbotg: usb@02184000 {
821 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
822 reg = <0x02184000 0x200>;
823 interrupts = <0 43 0x04>;
824 clocks = <&clks 162>;
825 fsl,usbphy = <&usbphy1>;
826 fsl,usbmisc = <&usbmisc 0>;
827 status = "disabled";
828 };
829
830 usbh1: usb@02184200 {
831 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
832 reg = <0x02184200 0x200>;
833 interrupts = <0 40 0x04>;
834 clocks = <&clks 162>;
835 fsl,usbphy = <&usbphy2>;
836 fsl,usbmisc = <&usbmisc 1>;
837 status = "disabled";
838 };
839
840 usbh2: usb@02184400 {
841 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
842 reg = <0x02184400 0x200>;
843 interrupts = <0 41 0x04>;
844 clocks = <&clks 162>;
845 fsl,usbmisc = <&usbmisc 2>;
846 status = "disabled";
847 };
848
849 usbh3: usb@02184600 {
850 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
851 reg = <0x02184600 0x200>;
852 interrupts = <0 42 0x04>;
853 clocks = <&clks 162>;
854 fsl,usbmisc = <&usbmisc 3>;
855 status = "disabled";
856 };
857
858 usbmisc: usbmisc: usbmisc@02184800 {
859 #index-cells = <1>;
860 compatible = "fsl,imx6q-usbmisc";
861 reg = <0x02184800 0x200>;
862 clocks = <&clks 162>;
863 };
864
865 fec: ethernet@02188000 {
866 compatible = "fsl,imx6q-fec";
867 reg = <0x02188000 0x4000>;
868 interrupts = <0 118 0x04 0 119 0x04>;
869 clocks = <&clks 117>, <&clks 117>, <&clks 177>;
870 clock-names = "ipg", "ahb", "ptp";
871 status = "disabled";
872 };
873
874 mlb@0218c000 {
875 reg = <0x0218c000 0x4000>;
876 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
877 };
878
879 usdhc1: usdhc@02190000 {
880 compatible = "fsl,imx6q-usdhc";
881 reg = <0x02190000 0x4000>;
882 interrupts = <0 22 0x04>;
883 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
884 clock-names = "ipg", "ahb", "per";
885 bus-width = <4>;
886 status = "disabled";
887 };
888
889 usdhc2: usdhc@02194000 {
890 compatible = "fsl,imx6q-usdhc";
891 reg = <0x02194000 0x4000>;
892 interrupts = <0 23 0x04>;
893 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
894 clock-names = "ipg", "ahb", "per";
895 bus-width = <4>;
896 status = "disabled";
897 };
898
899 usdhc3: usdhc@02198000 {
900 compatible = "fsl,imx6q-usdhc";
901 reg = <0x02198000 0x4000>;
902 interrupts = <0 24 0x04>;
903 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
904 clock-names = "ipg", "ahb", "per";
905 bus-width = <4>;
906 status = "disabled";
907 };
908
909 usdhc4: usdhc@0219c000 {
910 compatible = "fsl,imx6q-usdhc";
911 reg = <0x0219c000 0x4000>;
912 interrupts = <0 25 0x04>;
913 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
914 clock-names = "ipg", "ahb", "per";
915 bus-width = <4>;
916 status = "disabled";
917 };
918
919 i2c1: i2c@021a0000 {
920 #address-cells = <1>;
921 #size-cells = <0>;
922 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
923 reg = <0x021a0000 0x4000>;
924 interrupts = <0 36 0x04>;
925 clocks = <&clks 125>;
926 status = "disabled";
927 };
928
929 i2c2: i2c@021a4000 {
930 #address-cells = <1>;
931 #size-cells = <0>;
932 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
933 reg = <0x021a4000 0x4000>;
934 interrupts = <0 37 0x04>;
935 clocks = <&clks 126>;
936 status = "disabled";
937 };
938
939 i2c3: i2c@021a8000 {
940 #address-cells = <1>;
941 #size-cells = <0>;
942 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
943 reg = <0x021a8000 0x4000>;
944 interrupts = <0 38 0x04>;
945 clocks = <&clks 127>;
946 status = "disabled";
947 };
948
949 romcp@021ac000 {
950 reg = <0x021ac000 0x4000>;
951 };
952
953 mmdc0: mmdc@021b0000 { /* MMDC0 */
954 compatible = "fsl,imx6q-mmdc";
955 reg = <0x021b0000 0x4000>;
956 };
957
958 mmdc1: mmdc@021b4000 { /* MMDC1 */
959 reg = <0x021b4000 0x4000>;
960 };
961
962 weim@021b8000 {
963 reg = <0x021b8000 0x4000>;
964 interrupts = <0 14 0x04>;
965 };
966
967 ocotp@021bc000 {
968 reg = <0x021bc000 0x4000>;
969 };
970
971 ocotp@021c0000 {
972 reg = <0x021c0000 0x4000>;
973 interrupts = <0 21 0x04>;
974 };
975
976 tzasc@021d0000 { /* TZASC1 */
977 reg = <0x021d0000 0x4000>;
978 interrupts = <0 108 0x04>;
979 };
980
981 tzasc@021d4000 { /* TZASC2 */
982 reg = <0x021d4000 0x4000>;
983 interrupts = <0 109 0x04>;
984 };
985
986 audmux: audmux@021d8000 {
987 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
988 reg = <0x021d8000 0x4000>;
989 status = "disabled";
990 };
991
992 mipi@021dc000 { /* MIPI-CSI */
993 reg = <0x021dc000 0x4000>;
994 };
995
996 mipi@021e0000 { /* MIPI-DSI */
997 reg = <0x021e0000 0x4000>;
998 };
999
1000 vdoa@021e4000 {
1001 reg = <0x021e4000 0x4000>;
1002 interrupts = <0 18 0x04>;
1003 };
1004
1005 uart2: serial@021e8000 {
1006 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1007 reg = <0x021e8000 0x4000>;
1008 interrupts = <0 27 0x04>;
1009 clocks = <&clks 160>, <&clks 161>;
1010 clock-names = "ipg", "per";
1011 status = "disabled";
1012 };
1013
1014 uart3: serial@021ec000 {
1015 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1016 reg = <0x021ec000 0x4000>;
1017 interrupts = <0 28 0x04>;
1018 clocks = <&clks 160>, <&clks 161>;
1019 clock-names = "ipg", "per";
1020 status = "disabled";
1021 };
1022
1023 uart4: serial@021f0000 {
1024 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1025 reg = <0x021f0000 0x4000>;
1026 interrupts = <0 29 0x04>;
1027 clocks = <&clks 160>, <&clks 161>;
1028 clock-names = "ipg", "per";
1029 status = "disabled";
1030 };
1031
1032 uart5: serial@021f4000 {
1033 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1034 reg = <0x021f4000 0x4000>;
1035 interrupts = <0 30 0x04>;
1036 clocks = <&clks 160>, <&clks 161>;
1037 clock-names = "ipg", "per";
1038 status = "disabled";
1039 };
1040 };
1041
1042 ipu1: ipu@02400000 {
1043 #crtc-cells = <1>;
1044 compatible = "fsl,imx6q-ipu";
1045 reg = <0x02400000 0x400000>;
1046 interrupts = <0 6 0x4 0 5 0x4>;
1047 clocks = <&clks 130>, <&clks 131>, <&clks 132>;
1048 clock-names = "bus", "di0", "di1";
1049 };
1050
1051 ipu2: ipu@02800000 {
1052 #crtc-cells = <1>;
1053 compatible = "fsl,imx6q-ipu";
1054 reg = <0x02800000 0x400000>;
1055 interrupts = <0 8 0x4 0 7 0x4>;
1056 clocks = <&clks 133>, <&clks 134>, <&clks 137>;
1057 clock-names = "bus", "di0", "di1";
1058 };
1059 };
1060};
diff --git a/arch/arm/boot/dts/integrator.dtsi b/arch/arm/boot/dts/integrator.dtsi
deleted file mode 100644
index 813b91d7bea..00000000000
--- a/arch/arm/boot/dts/integrator.dtsi
+++ /dev/null
@@ -1,76 +0,0 @@
1/*
2 * SoC core Device Tree for the ARM Integrator platforms
3 */
4
5/include/ "skeleton.dtsi"
6
7/ {
8 timer@13000000 {
9 reg = <0x13000000 0x100>;
10 interrupt-parent = <&pic>;
11 interrupts = <5>;
12 };
13
14 timer@13000100 {
15 reg = <0x13000100 0x100>;
16 interrupt-parent = <&pic>;
17 interrupts = <6>;
18 };
19
20 timer@13000200 {
21 reg = <0x13000200 0x100>;
22 interrupt-parent = <&pic>;
23 interrupts = <7>;
24 };
25
26 pic@14000000 {
27 compatible = "arm,versatile-fpga-irq";
28 #interrupt-cells = <1>;
29 interrupt-controller;
30 reg = <0x14000000 0x100>;
31 clear-mask = <0xffffffff>;
32 };
33
34 flash@24000000 {
35 compatible = "cfi-flash";
36 reg = <0x24000000 0x02000000>;
37 };
38
39 fpga {
40 compatible = "arm,amba-bus", "simple-bus";
41 #address-cells = <1>;
42 #size-cells = <1>;
43 ranges;
44 interrupt-parent = <&pic>;
45
46 /*
47 * These PrimeCells are in the same locations and using the
48 * same interrupts in all Integrators, however the silicon
49 * version deployed is different.
50 */
51 rtc@15000000 {
52 reg = <0x15000000 0x1000>;
53 interrupts = <8>;
54 };
55
56 uart@16000000 {
57 reg = <0x16000000 0x1000>;
58 interrupts = <1>;
59 };
60
61 uart@17000000 {
62 reg = <0x17000000 0x1000>;
63 interrupts = <2>;
64 };
65
66 kmi@18000000 {
67 reg = <0x18000000 0x1000>;
68 interrupts = <3>;
69 };
70
71 kmi@19000000 {
72 reg = <0x19000000 0x1000>;
73 interrupts = <4>;
74 };
75 };
76};
diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts
deleted file mode 100644
index c9c3fa34464..00000000000
--- a/arch/arm/boot/dts/integratorap.dts
+++ /dev/null
@@ -1,73 +0,0 @@
1/*
2 * Device Tree for the ARM Integrator/AP platform
3 */
4
5/dts-v1/;
6/include/ "integrator.dtsi"
7
8/ {
9 model = "ARM Integrator/AP";
10 compatible = "arm,integrator-ap";
11
12 aliases {
13 arm,timer-primary = &timer2;
14 arm,timer-secondary = &timer1;
15 };
16
17 chosen {
18 bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk";
19 };
20
21 syscon {
22 /* AP system controller registers */
23 reg = <0x11000000 0x100>;
24 };
25
26 timer0: timer@13000000 {
27 compatible = "arm,integrator-timer";
28 };
29
30 timer1: timer@13000100 {
31 compatible = "arm,integrator-timer";
32 };
33
34 timer2: timer@13000200 {
35 compatible = "arm,integrator-timer";
36 };
37
38 pic: pic@14000000 {
39 valid-mask = <0x003fffff>;
40 };
41
42 fpga {
43 /*
44 * The Integator/AP predates the idea to have magic numbers
45 * identifying the PrimeCell in hardware, thus we have to
46 * supply these from the device tree.
47 */
48 rtc: rtc@15000000 {
49 compatible = "arm,pl030", "arm,primecell";
50 arm,primecell-periphid = <0x00041030>;
51 };
52
53 uart0: uart@16000000 {
54 compatible = "arm,pl010", "arm,primecell";
55 arm,primecell-periphid = <0x00041010>;
56 };
57
58 uart1: uart@17000000 {
59 compatible = "arm,pl010", "arm,primecell";
60 arm,primecell-periphid = <0x00041010>;
61 };
62
63 kmi0: kmi@18000000 {
64 compatible = "arm,pl050", "arm,primecell";
65 arm,primecell-periphid = <0x00041050>;
66 };
67
68 kmi1: kmi@19000000 {
69 compatible = "arm,pl050", "arm,primecell";
70 arm,primecell-periphid = <0x00041050>;
71 };
72 };
73};
diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts
deleted file mode 100644
index 8b119399025..00000000000
--- a/arch/arm/boot/dts/integratorcp.dts
+++ /dev/null
@@ -1,115 +0,0 @@
1/*
2 * Device Tree for the ARM Integrator/CP platform
3 */
4
5/dts-v1/;
6/include/ "integrator.dtsi"
7
8/ {
9 model = "ARM Integrator/CP";
10 compatible = "arm,integrator-cp";
11
12 aliases {
13 arm,timer-primary = &timer2;
14 arm,timer-secondary = &timer1;
15 };
16
17 chosen {
18 bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk";
19 };
20
21 cpcon {
22 /* CP controller registers */
23 reg = <0xcb000000 0x100>;
24 };
25
26 timer0: timer@13000000 {
27 compatible = "arm,sp804", "arm,primecell";
28 };
29
30 timer1: timer@13000100 {
31 compatible = "arm,sp804", "arm,primecell";
32 };
33
34 timer2: timer@13000200 {
35 compatible = "arm,sp804", "arm,primecell";
36 };
37
38 pic: pic@14000000 {
39 valid-mask = <0x1fc003ff>;
40 };
41
42 cic: cic@10000040 {
43 compatible = "arm,versatile-fpga-irq";
44 #interrupt-cells = <1>;
45 interrupt-controller;
46 reg = <0x10000040 0x100>;
47 clear-mask = <0xffffffff>;
48 valid-mask = <0x00000007>;
49 };
50
51 sic: sic@ca000000 {
52 compatible = "arm,versatile-fpga-irq";
53 #interrupt-cells = <1>;
54 interrupt-controller;
55 reg = <0xca000000 0x100>;
56 clear-mask = <0x00000fff>;
57 valid-mask = <0x00000fff>;
58 };
59
60 ethernet@c8000000 {
61 compatible = "smsc,lan91c111";
62 reg = <0xc8000000 0x10>;
63 interrupt-parent = <&pic>;
64 interrupts = <27>;
65 };
66
67 fpga {
68 /*
69 * These PrimeCells are at the same location and using
70 * the same interrupts in all Integrators, but in the CP
71 * slightly newer versions are deployed.
72 */
73 rtc@15000000 {
74 compatible = "arm,pl031", "arm,primecell";
75 };
76
77 uart@16000000 {
78 compatible = "arm,pl011", "arm,primecell";
79 };
80
81 uart@17000000 {
82 compatible = "arm,pl011", "arm,primecell";
83 };
84
85 kmi@18000000 {
86 compatible = "arm,pl050", "arm,primecell";
87 };
88
89 kmi@19000000 {
90 compatible = "arm,pl050", "arm,primecell";
91 };
92
93 /*
94 * These PrimeCells are only available on the Integrator/CP
95 */
96 mmc@1c000000 {
97 compatible = "arm,pl180", "arm,primecell";
98 reg = <0x1c000000 0x1000>;
99 interrupts = <23 24>;
100 max-frequency = <515633>;
101 };
102
103 aaci@1d000000 {
104 compatible = "arm,pl041", "arm,primecell";
105 reg = <0x1d000000 0x1000>;
106 interrupts = <25>;
107 };
108
109 clcd@c0000000 {
110 compatible = "arm,pl110", "arm,primecell";
111 reg = <0xC0000000 0x1000>;
112 interrupts = <22>;
113 };
114 };
115};
diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi
deleted file mode 100644
index d6c9d65cbae..00000000000
--- a/arch/arm/boot/dts/kirkwood-6281.dtsi
+++ /dev/null
@@ -1,44 +0,0 @@
1/ {
2 ocp@f1000000 {
3 pinctrl: pinctrl@10000 {
4 compatible = "marvell,88f6281-pinctrl";
5 reg = <0x10000 0x20>;
6
7 pmx_nand: pmx-nand {
8 marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
9 "mpp4", "mpp5", "mpp18",
10 "mpp19";
11 marvell,function = "nand";
12 };
13 pmx_sata0: pmx-sata0 {
14 marvell,pins = "mpp5", "mpp21", "mpp23";
15 marvell,function = "sata0";
16 };
17 pmx_sata1: pmx-sata1 {
18 marvell,pins = "mpp4", "mpp20", "mpp22";
19 marvell,function = "sata1";
20 };
21 pmx_spi: pmx-spi {
22 marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3";
23 marvell,function = "spi";
24 };
25 pmx_twsi0: pmx-twsi0 {
26 marvell,pins = "mpp8", "mpp9";
27 marvell,function = "twsi0";
28 };
29 pmx_uart0: pmx-uart0 {
30 marvell,pins = "mpp10", "mpp11";
31 marvell,function = "uart0";
32 };
33 pmx_uart1: pmx-uart1 {
34 marvell,pins = "mpp13", "mpp14";
35 marvell,function = "uart1";
36 };
37 pmx_sdio: pmx-sdio {
38 marvell,pins = "mpp12", "mpp13", "mpp14",
39 "mpp15", "mpp16", "mpp17";
40 marvell,function = "sdio";
41 };
42 };
43 };
44};
diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi
deleted file mode 100644
index 4ccea2130a6..00000000000
--- a/arch/arm/boot/dts/kirkwood-6282.dtsi
+++ /dev/null
@@ -1,46 +0,0 @@
1/ {
2 ocp@f1000000 {
3
4 pinctrl: pinctrl@10000 {
5 compatible = "marvell,88f6282-pinctrl";
6 reg = <0x10000 0x20>;
7
8 pmx_sata0: pmx-sata0 {
9 marvell,pins = "mpp5", "mpp21", "mpp23";
10 marvell,function = "sata0";
11 };
12 pmx_sata1: pmx-sata1 {
13 marvell,pins = "mpp4", "mpp20", "mpp22";
14 marvell,function = "sata1";
15 };
16 pmx_spi: pmx-spi {
17 marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3";
18 marvell,function = "spi";
19 };
20 pmx_twsi0: pmx-twsi0 {
21 marvell,pins = "mpp8", "mpp9";
22 marvell,function = "twsi0";
23 };
24 pmx_uart0: pmx-uart0 {
25 marvell,pins = "mpp10", "mpp11";
26 marvell,function = "uart0";
27 };
28
29 pmx_uart1: pmx-uart1 {
30 marvell,pins = "mpp13", "mpp14";
31 marvell,function = "uart1";
32 };
33 };
34
35 i2c@11100 {
36 compatible = "marvell,mv64xxx-i2c";
37 reg = <0x11100 0x20>;
38 #address-cells = <1>;
39 #size-cells = <0>;
40 interrupts = <32>;
41 clock-frequency = <100000>;
42 clocks = <&gate_clk 7>;
43 status = "disabled";
44 };
45 };
46};
diff --git a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi b/arch/arm/boot/dts/kirkwood-98dx4122.dtsi
deleted file mode 100644
index 3271e4c8ea0..00000000000
--- a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi
+++ /dev/null
@@ -1,31 +0,0 @@
1/ {
2 ocp@f1000000 {
3 pinctrl: pinctrl@10000 {
4 compatible = "marvell,98dx4122-pinctrl";
5 reg = <0x10000 0x20>;
6
7 pmx_nand: pmx-nand {
8 marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
9 "mpp4", "mpp5", "mpp18",
10 "mpp19";
11 marvell,function = "nand";
12 };
13 pmx_spi: pmx-spi {
14 marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3";
15 marvell,function = "spi";
16 };
17 pmx_twsi0: pmx-twsi0 {
18 marvell,pins = "mpp8", "mpp9";
19 marvell,function = "twsi0";
20 };
21 pmx_uart0: pmx-uart0 {
22 marvell,pins = "mpp10", "mpp11";
23 marvell,function = "uart0";
24 };
25 pmx_uart1: pmx-uart1 {
26 marvell,pins = "mpp13", "mpp14";
27 marvell,function = "uart1";
28 };
29 };
30 };
31};
diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/kirkwood-dns320.dts
deleted file mode 100644
index 5bb0bf39d3b..00000000000
--- a/arch/arm/boot/dts/kirkwood-dns320.dts
+++ /dev/null
@@ -1,54 +0,0 @@
1/dts-v1/;
2
3/include/ "kirkwood-dnskw.dtsi"
4
5/ {
6 model = "D-Link DNS-320 NAS (Rev A1)";
7 compatible = "dlink,dns-320-a1", "dlink,dns-320", "dlink,dns-kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood";
8
9 memory {
10 device_type = "memory";
11 reg = <0x00000000 0x8000000>;
12 };
13
14 chosen {
15 bootargs = "console=ttyS0,115200n8 earlyprintk";
16 };
17
18 gpio-leds {
19 compatible = "gpio-leds";
20 blue-power {
21 label = "dns320:blue:power";
22 gpios = <&gpio0 26 1>; /* GPIO 26 Active Low */
23 linux,default-trigger = "default-on";
24 };
25 blue-usb {
26 label = "dns320:blue:usb";
27 gpios = <&gpio1 11 1>; /* GPIO 43 Active Low */
28 };
29 orange-l_hdd {
30 label = "dns320:orange:l_hdd";
31 gpios = <&gpio0 28 1>; /* GPIO 28 Active Low */
32 };
33 orange-r_hdd {
34 label = "dns320:orange:r_hdd";
35 gpios = <&gpio0 27 1>; /* GPIO 27 Active Low */
36 };
37 orange-usb {
38 label = "dns320:orange:usb";
39 gpios = <&gpio1 3 1>; /* GPIO 35 Active Low */
40 };
41 };
42
43 ocp@f1000000 {
44 serial@12000 {
45 clock-frequency = <166666667>;
46 status = "okay";
47 };
48
49 serial@12100 {
50 clock-frequency = <166666667>;
51 status = "okay";
52 };
53 };
54};
diff --git a/arch/arm/boot/dts/kirkwood-dns325.dts b/arch/arm/boot/dts/kirkwood-dns325.dts
deleted file mode 100644
index d430713ea9b..00000000000
--- a/arch/arm/boot/dts/kirkwood-dns325.dts
+++ /dev/null
@@ -1,57 +0,0 @@
1/dts-v1/;
2
3/include/ "kirkwood-dnskw.dtsi"
4
5/ {
6 model = "D-Link DNS-325 NAS (Rev A1)";
7 compatible = "dlink,dns-325-a1", "dlink,dns-325", "dlink,dns-kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood";
8
9 memory {
10 device_type = "memory";
11 reg = <0x00000000 0x10000000>;
12 };
13
14 chosen {
15 bootargs = "console=ttyS0,115200n8 earlyprintk";
16 };
17
18 gpio-leds {
19 compatible = "gpio-leds";
20 white-power {
21 label = "dns325:white:power";
22 gpios = <&gpio0 26 1>; /* GPIO 26 Active Low */
23 linux,default-trigger = "default-on";
24 };
25 white-usb {
26 label = "dns325:white:usb";
27 gpios = <&gpio1 11 1>; /* GPIO 43 Active Low */
28 };
29 red-l_hdd {
30 label = "dns325:red:l_hdd";
31 gpios = <&gpio0 28 1>; /* GPIO 28 Active Low */
32 };
33 red-r_hdd {
34 label = "dns325:red:r_hdd";
35 gpios = <&gpio0 27 1>; /* GPIO 27 Active Low */
36 };
37 red-usb {
38 label = "dns325:red:usb";
39 gpios = <&gpio0 29 1>; /* GPIO 29 Active Low */
40 };
41 };
42
43 ocp@f1000000 {
44 i2c@11000 {
45 status = "okay";
46
47 lm75: lm75@48 {
48 compatible = "national,lm75";
49 reg = <0x48>;
50 };
51 };
52 serial@12000 {
53 clock-frequency = <200000000>;
54 status = "okay";
55 };
56 };
57};
diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
deleted file mode 100644
index 6875ac00c17..00000000000
--- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi
+++ /dev/null
@@ -1,219 +0,0 @@
1/include/ "kirkwood.dtsi"
2/include/ "kirkwood-6281.dtsi"
3
4/ {
5 model = "D-Link DNS NASes (kirkwood-based)";
6 compatible = "dlink,dns-kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood";
7
8 gpio_keys {
9 compatible = "gpio-keys";
10 #address-cells = <1>;
11 #size-cells = <0>;
12 button@1 {
13 label = "Power button";
14 linux,code = <116>;
15 gpios = <&gpio1 2 1>;
16 };
17 button@2 {
18 label = "USB unmount button";
19 linux,code = <161>;
20 gpios = <&gpio1 15 1>;
21 };
22 button@3 {
23 label = "Reset button";
24 linux,code = <0x198>;
25 gpios = <&gpio1 16 1>;
26 };
27 };
28
29 gpio_fan {
30 /* Fan: ADDA AD045HB-G73 40mm 6000rpm@5v */
31 compatible = "gpio-fan";
32 gpios = <&gpio1 14 1
33 &gpio1 13 1>;
34 gpio-fan,speed-map = <0 0
35 3000 1
36 6000 2>;
37 };
38
39 gpio_poweroff {
40 compatible = "gpio-poweroff";
41 gpios = <&gpio1 4 0>;
42 };
43
44 ocp@f1000000 {
45 pinctrl: pinctrl@10000 {
46
47 pinctrl-0 = < &pmx_nand &pmx_uart1
48 &pmx_sata0 &pmx_sata1
49 &pmx_led_power
50 &pmx_led_red_right_hdd
51 &pmx_led_red_left_hdd
52 &pmx_led_red_usb_325
53 &pmx_button_power
54 &pmx_led_red_usb_320
55 &pmx_power_off &pmx_power_back_on
56 &pmx_power_sata0 &pmx_power_sata1
57 &pmx_present_sata0 &pmx_present_sata1
58 &pmx_led_white_usb &pmx_fan_tacho
59 &pmx_fan_high_speed &pmx_fan_low_speed
60 &pmx_button_unmount &pmx_button_reset
61 &pmx_temp_alarm >;
62 pinctrl-names = "default";
63
64 pmx_sata0: pmx-sata0 {
65 marvell,pins = "mpp20";
66 marvell,function = "sata1";
67 };
68 pmx_sata1: pmx-sata1 {
69 marvell,pins = "mpp21";
70 marvell,function = "sata0";
71 };
72 pmx_led_power: pmx-led-power {
73 marvell,pins = "mpp26";
74 marvell,function = "gpio";
75 };
76 pmx_led_red_right_hdd: pmx-led-red-right-hdd {
77 marvell,pins = "mpp27";
78 marvell,function = "gpio";
79 };
80 pmx_led_red_left_hdd: pmx-led-red-left-hdd {
81 marvell,pins = "mpp28";
82 marvell,function = "gpio";
83 };
84 pmx_led_red_usb_325: pmx-led-red-usb-325 {
85 marvell,pins = "mpp29";
86 marvell,function = "gpio";
87 };
88 pmx_button_power: pmx-button-power {
89 marvell,pins = "mpp34";
90 marvell,function = "gpio";
91 };
92 pmx_led_red_usb_320: pmx-led-red-usb-320 {
93 marvell,pins = "mpp35";
94 marvell,function = "gpio";
95 };
96 pmx_power_off: pmx-power-off {
97 marvell,pins = "mpp36";
98 marvell,function = "gpio";
99 };
100 pmx_power_back_on: pmx-power-back-on {
101 marvell,pins = "mpp37";
102 marvell,function = "gpio";
103 };
104 pmx_power_sata0: pmx-power-sata0 {
105 marvell,pins = "mpp39";
106 marvell,function = "gpio";
107 };
108 pmx_power_sata1: pmx-power-sata1 {
109 marvell,pins = "mpp40";
110 marvell,function = "gpio";
111 };
112 pmx_present_sata0: pmx-present-sata0 {
113 marvell,pins = "mpp41";
114 marvell,function = "gpio";
115 };
116 pmx_present_sata1: pmx-present-sata1 {
117 marvell,pins = "mpp42";
118 marvell,function = "gpio";
119 };
120 pmx_led_white_usb: pmx-led-white-usb {
121 marvell,pins = "mpp43";
122 marvell,function = "gpio";
123 };
124 pmx_fan_tacho: pmx-fan-tacho {
125 marvell,pins = "mpp44";
126 marvell,function = "gpio";
127 };
128 pmx_fan_high_speed: pmx-fan-high-speed {
129 marvell,pins = "mpp45";
130 marvell,function = "gpio";
131 };
132 pmx_fan_low_speed: pmx-fan-low-speed {
133 marvell,pins = "mpp46";
134 marvell,function = "gpio";
135 };
136 pmx_button_unmount: pmx-button-unmount {
137 marvell,pins = "mpp47";
138 marvell,function = "gpio";
139 };
140 pmx_button_reset: pmx-button-reset {
141 marvell,pins = "mpp48";
142 marvell,function = "gpio";
143 };
144 pmx_temp_alarm: pmx-temp-alarm {
145 marvell,pins = "mpp49";
146 marvell,function = "gpio";
147 };
148 };
149 sata@80000 {
150 status = "okay";
151 nr-ports = <2>;
152 };
153
154 nand@3000000 {
155 status = "okay";
156 chip-delay = <35>;
157
158 partition@0 {
159 label = "u-boot";
160 reg = <0x0000000 0x100000>;
161 read-only;
162 };
163
164 partition@100000 {
165 label = "uImage";
166 reg = <0x0100000 0x500000>;
167 };
168
169 partition@600000 {
170 label = "ramdisk";
171 reg = <0x0600000 0x500000>;
172 };
173
174 partition@b00000 {
175 label = "image";
176 reg = <0x0b00000 0x6600000>;
177 };
178
179 partition@7100000 {
180 label = "mini firmware";
181 reg = <0x7100000 0xa00000>;
182 };
183
184 partition@7b00000 {
185 label = "config";
186 reg = <0x7b00000 0x500000>;
187 };
188 };
189 };
190
191 regulators {
192 compatible = "simple-bus";
193 #address-cells = <1>;
194 #size-cells = <0>;
195
196 sata0_power: regulator@1 {
197 compatible = "regulator-fixed";
198 reg = <1>;
199 regulator-name = "SATA0 Power";
200 regulator-min-microvolt = <5000000>;
201 regulator-max-microvolt = <5000000>;
202 enable-active-high;
203 regulator-always-on;
204 regulator-boot-on;
205 gpio = <&gpio1 7 0>;
206 };
207 sata1_power: regulator@2 {
208 compatible = "regulator-fixed";
209 reg = <2>;
210 regulator-name = "SATA1 Power";
211 regulator-min-microvolt = <5000000>;
212 regulator-max-microvolt = <5000000>;
213 enable-active-high;
214 regulator-always-on;
215 regulator-boot-on;
216 gpio = <&gpio1 8 0>;
217 };
218 };
219};
diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts
deleted file mode 100644
index 2e3dd34e21a..00000000000
--- a/arch/arm/boot/dts/kirkwood-dockstar.dts
+++ /dev/null
@@ -1,94 +0,0 @@
1/dts-v1/;
2
3/include/ "kirkwood.dtsi"
4/include/ "kirkwood-6281.dtsi"
5
6/ {
7 model = "Seagate FreeAgent Dockstar";
8 compatible = "seagate,dockstar", "marvell,kirkwood-88f6281", "marvell,kirkwood";
9
10 memory {
11 device_type = "memory";
12 reg = <0x00000000 0x8000000>;
13 };
14
15 chosen {
16 bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10";
17 };
18
19 ocp@f1000000 {
20 pinctrl: pinctrl@10000 {
21
22 pinctrl-0 = < &pmx_usb_power_enable
23 &pmx_led_green &pmx_led_orange >;
24 pinctrl-names = "default";
25
26 pmx_usb_power_enable: pmx-usb-power-enable {
27 marvell,pins = "mpp29";
28 marvell,function = "gpio";
29 };
30 pmx_led_green: pmx-led-green {
31 marvell,pins = "mpp46";
32 marvell,function = "gpio";
33 };
34 pmx_led_orange: pmx-led-orange {
35 marvell,pins = "mpp47";
36 marvell,function = "gpio";
37 };
38 };
39 serial@12000 {
40 clock-frequency = <200000000>;
41 status = "ok";
42 };
43
44 nand@3000000 {
45 status = "okay";
46
47 partition@0 {
48 label = "u-boot";
49 reg = <0x0000000 0x100000>;
50 read-only;
51 };
52
53 partition@100000 {
54 label = "uImage";
55 reg = <0x0100000 0x400000>;
56 };
57
58 partition@500000 {
59 label = "data";
60 reg = <0x0500000 0xfb00000>;
61 };
62 };
63 };
64 gpio-leds {
65 compatible = "gpio-leds";
66
67 health {
68 label = "status:green:health";
69 gpios = <&gpio1 14 1>;
70 linux,default-trigger = "default-on";
71 };
72 fault {
73 label = "status:orange:fault";
74 gpios = <&gpio1 15 1>;
75 };
76 };
77 regulators {
78 compatible = "simple-bus";
79 #address-cells = <1>;
80 #size-cells = <0>;
81
82 usb_power: regulator@1 {
83 compatible = "regulator-fixed";
84 reg = <1>;
85 regulator-name = "USB Power";
86 regulator-min-microvolt = <5000000>;
87 regulator-max-microvolt = <5000000>;
88 enable-active-high;
89 regulator-always-on;
90 regulator-boot-on;
91 gpio = <&gpio0 29 0>;
92 };
93 };
94};
diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts
deleted file mode 100644
index f2d386c95b0..00000000000
--- a/arch/arm/boot/dts/kirkwood-dreamplug.dts
+++ /dev/null
@@ -1,95 +0,0 @@
1/dts-v1/;
2
3/include/ "kirkwood.dtsi"
4/include/ "kirkwood-6281.dtsi"
5
6/ {
7 model = "Globalscale Technologies Dreamplug";
8 compatible = "globalscale,dreamplug-003-ds2001", "globalscale,dreamplug", "marvell,kirkwood-88f6281", "marvell,kirkwood";
9
10 memory {
11 device_type = "memory";
12 reg = <0x00000000 0x20000000>;
13 };
14
15 chosen {
16 bootargs = "console=ttyS0,115200n8 earlyprintk";
17 };
18
19 ocp@f1000000 {
20 pinctrl: pinctrl@10000 {
21
22 pinctrl-0 = < &pmx_spi
23 &pmx_led_bluetooth &pmx_led_wifi
24 &pmx_led_wifi_ap >;
25 pinctrl-names = "default";
26
27 pmx_led_bluetooth: pmx-led-bluetooth {
28 marvell,pins = "mpp47";
29 marvell,function = "gpio";
30 };
31 pmx_led_wifi: pmx-led-wifi {
32 marvell,pins = "mpp48";
33 marvell,function = "gpio";
34 };
35 pmx_led_wifi_ap: pmx-led-wifi-ap {
36 marvell,pins = "mpp49";
37 marvell,function = "gpio";
38 };
39 };
40 serial@12000 {
41 clock-frequency = <200000000>;
42 status = "ok";
43 };
44
45 spi@10600 {
46 status = "okay";
47
48 m25p40@0 {
49 #address-cells = <1>;
50 #size-cells = <1>;
51 compatible = "mx25l1606e";
52 reg = <0>;
53 spi-max-frequency = <50000000>;
54 mode = <0>;
55
56 partition@0 {
57 reg = <0x0 0x80000>;
58 label = "u-boot";
59 };
60
61 partition@100000 {
62 reg = <0x100000 0x10000>;
63 label = "u-boot env";
64 };
65
66 partition@180000 {
67 reg = <0x180000 0x10000>;
68 label = "dtb";
69 };
70 };
71 };
72
73 sata@80000 {
74 status = "okay";
75 nr-ports = <1>;
76 };
77 };
78
79 gpio-leds {
80 compatible = "gpio-leds";
81
82 bluetooth {
83 label = "dreamplug:blue:bluetooth";
84 gpios = <&gpio1 15 1>;
85 };
86 wifi {
87 label = "dreamplug:green:wifi";
88 gpios = <&gpio1 16 1>;
89 };
90 wifi-ap {
91 label = "dreamplug:green:wifi_ap";
92 gpios = <&gpio1 17 1>;
93 };
94 };
95};
diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts
deleted file mode 100644
index 1b133e0c566..00000000000
--- a/arch/arm/boot/dts/kirkwood-goflexnet.dts
+++ /dev/null
@@ -1,172 +0,0 @@
1/dts-v1/;
2
3/include/ "kirkwood.dtsi"
4/include/ "kirkwood-6281.dtsi"
5
6/ {
7 model = "Seagate GoFlex Net";
8 compatible = "seagate,goflexnet", "marvell,kirkwood-88f6281", "marvell,kirkwood";
9
10 memory {
11 device_type = "memory";
12 reg = <0x00000000 0x8000000>;
13 };
14
15 chosen {
16 bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10";
17 };
18
19 ocp@f1000000 {
20 pinctrl: pinctrl@10000 {
21
22 pinctrl-0 = < &pmx_usb_power_enable &pmx_led_orange
23 &pmx_led_left_cap_0 &pmx_led_left_cap_1
24 &pmx_led_left_cap_2 &pmx_led_left_cap_3
25 &pmx_led_right_cap_0 &pmx_led_right_cap_1
26 &pmx_led_right_cap_2 &pmx_led_right_cap_3
27 >;
28 pinctrl-names = "default";
29
30 pmx_usb_power_enable: pmx-usb-power-enable {
31 marvell,pins = "mpp29";
32 marvell,function = "gpio";
33 };
34 pmx_led_right_cap_0: pmx-led_right_cap_0 {
35 marvell,pins = "mpp38";
36 marvell,function = "gpio";
37 };
38 pmx_led_right_cap_1: pmx-led_right_cap_1 {
39 marvell,pins = "mpp39";
40 marvell,function = "gpio";
41 };
42 pmx_led_right_cap_2: pmx-led_right_cap_2 {
43 marvell,pins = "mpp40";
44 marvell,function = "gpio";
45 };
46 pmx_led_right_cap_3: pmx-led_right_cap_3 {
47 marvell,pins = "mpp41";
48 marvell,function = "gpio";
49 };
50 pmx_led_left_cap_0: pmx-led_left_cap_0 {
51 marvell,pins = "mpp42";
52 marvell,function = "gpio";
53 };
54 pmx_led_left_cap_1: pmx-led_left_cap_1 {
55 marvell,pins = "mpp43";
56 marvell,function = "gpio";
57 };
58 pmx_led_left_cap_2: pmx-led_left_cap_2 {
59 marvell,pins = "mpp44";
60 marvell,function = "gpio";
61 };
62 pmx_led_left_cap_3: pmx-led_left_cap_3 {
63 marvell,pins = "mpp45";
64 marvell,function = "gpio";
65 };
66 pmx_led_green: pmx-led_green {
67 marvell,pins = "mpp46";
68 marvell,function = "gpio";
69 };
70 pmx_led_orange: pmx-led_orange {
71 marvell,pins = "mpp47";
72 marvell,function = "gpio";
73 };
74 };
75 serial@12000 {
76 clock-frequency = <200000000>;
77 status = "ok";
78 };
79
80 nand@3000000 {
81 status = "okay";
82
83 partition@0 {
84 label = "u-boot";
85 reg = <0x0000000 0x100000>;
86 read-only;
87 };
88
89 partition@100000 {
90 label = "uImage";
91 reg = <0x0100000 0x400000>;
92 };
93
94 partition@500000 {
95 label = "pogoplug";
96 reg = <0x0500000 0x2000000>;
97 };
98
99 partition@2500000 {
100 label = "root";
101 reg = <0x02500000 0xd800000>;
102 };
103 };
104 sata@80000 {
105 status = "okay";
106 nr-ports = <2>;
107 };
108
109 };
110 gpio-leds {
111 compatible = "gpio-leds";
112
113 health {
114 label = "status:green:health";
115 gpios = <&gpio1 14 1>;
116 linux,default-trigger = "default-on";
117 };
118 fault {
119 label = "status:orange:fault";
120 gpios = <&gpio1 15 1>;
121 };
122 left0 {
123 label = "status:white:left0";
124 gpios = <&gpio1 10 0>;
125 };
126 left1 {
127 label = "status:white:left1";
128 gpios = <&gpio1 11 0>;
129 };
130 left2 {
131 label = "status:white:left2";
132 gpios = <&gpio1 12 0>;
133 };
134 left3 {
135 label = "status:white:left3";
136 gpios = <&gpio1 13 0>;
137 };
138 right0 {
139 label = "status:white:right0";
140 gpios = <&gpio1 6 0>;
141 };
142 right1 {
143 label = "status:white:right1";
144 gpios = <&gpio1 7 0>;
145 };
146 right2 {
147 label = "status:white:right2";
148 gpios = <&gpio1 8 0>;
149 };
150 right3 {
151 label = "status:white:right3";
152 gpios = <&gpio1 9 0>;
153 };
154 };
155 regulators {
156 compatible = "simple-bus";
157 #address-cells = <1>;
158 #size-cells = <0>;
159
160 usb_power: regulator@1 {
161 compatible = "regulator-fixed";
162 reg = <1>;
163 regulator-name = "USB Power";
164 regulator-min-microvolt = <5000000>;
165 regulator-max-microvolt = <5000000>;
166 enable-active-high;
167 regulator-always-on;
168 regulator-boot-on;
169 gpio = <&gpio0 29 0>;
170 };
171 };
172};
diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts
deleted file mode 100644
index 71902da33d6..00000000000
--- a/arch/arm/boot/dts/kirkwood-ib62x0.dts
+++ /dev/null
@@ -1,122 +0,0 @@
1/dts-v1/;
2
3/include/ "kirkwood.dtsi"
4/include/ "kirkwood-6281.dtsi"
5
6/ {
7 model = "RaidSonic ICY BOX IB-NAS62x0 (Rev B)";
8 compatible = "raidsonic,ib-nas6210-b", "raidsonic,ib-nas6220-b", "raidsonic,ib-nas6210", "raidsonic,ib-nas6220", "raidsonic,ib-nas62x0", "marvell,kirkwood-88f6281", "marvell,kirkwood";
9
10 memory {
11 device_type = "memory";
12 reg = <0x00000000 0x10000000>;
13 };
14
15 chosen {
16 bootargs = "console=ttyS0,115200n8 earlyprintk";
17 };
18
19 ocp@f1000000 {
20 pinctrl: pinctrl@10000 {
21
22 pinctrl-0 = < &pmx_nand
23 &pmx_led_os_red &pmx_power_off
24 &pmx_led_os_green &pmx_led_usb_transfer
25 &pmx_button_reset &pmx_button_usb_copy >;
26 pinctrl-names = "default";
27
28 pmx_led_os_red: pmx-led-os-red {
29 marvell,pins = "mpp22";
30 marvell,function = "gpio";
31 };
32 pmx_power_off: pmx-power-off {
33 marvell,pins = "mpp24";
34 marvell,function = "gpio";
35 };
36 pmx_led_os_green: pmx-led-os-green {
37 marvell,pins = "mpp25";
38 marvell,function = "gpio";
39 };
40 pmx_led_usb_transfer: pmx-led-usb-transfer {
41 marvell,pins = "mpp27";
42 marvell,function = "gpio";
43 };
44 pmx_button_reset: pmx-button-reset {
45 marvell,pins = "mpp28";
46 marvell,function = "gpio";
47 };
48 pmx_button_usb_copy: pmx-button-usb-copy {
49 marvell,pins = "mpp29";
50 marvell,function = "gpio";
51 };
52 };
53 serial@12000 {
54 clock-frequency = <200000000>;
55 status = "okay";
56 };
57
58 sata@80000 {
59 status = "okay";
60 nr-ports = <2>;
61 };
62
63 nand@3000000 {
64 status = "okay";
65
66 partition@0 {
67 label = "u-boot";
68 reg = <0x0000000 0x100000>;
69 };
70
71 partition@100000 {
72 label = "uImage";
73 reg = <0x0100000 0x600000>;
74 };
75
76 partition@700000 {
77 label = "root";
78 reg = <0x0700000 0xf900000>;
79 };
80
81 };
82 };
83
84 gpio_keys {
85 compatible = "gpio-keys";
86 #address-cells = <1>;
87 #size-cells = <0>;
88 button@1 {
89 label = "USB Copy";
90 linux,code = <133>;
91 gpios = <&gpio0 29 1>;
92 };
93 button@2 {
94 label = "Reset";
95 linux,code = <0x198>;
96 gpios = <&gpio0 28 1>;
97 };
98 };
99 gpio-leds {
100 compatible = "gpio-leds";
101
102 green-os {
103 label = "ib62x0:green:os";
104 gpios = <&gpio0 25 0>;
105 linux,default-trigger = "default-on";
106 };
107 red-os {
108 label = "ib62x0:red:os";
109 gpios = <&gpio0 22 0>;
110 };
111 usb-copy {
112 label = "ib62x0:red:usb_copy";
113 gpios = <&gpio0 27 0>;
114 };
115 };
116 gpio_poweroff {
117 compatible = "gpio-poweroff";
118 gpios = <&gpio0 24 0>;
119 };
120
121
122};
diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts
deleted file mode 100644
index 504f16be8b5..00000000000
--- a/arch/arm/boot/dts/kirkwood-iconnect.dts
+++ /dev/null
@@ -1,171 +0,0 @@
1/dts-v1/;
2
3/include/ "kirkwood.dtsi"
4/include/ "kirkwood-6281.dtsi"
5
6/ {
7 model = "Iomega Iconnect";
8 compatible = "iom,iconnect-1.1", "iom,iconnect", "marvell,kirkwood-88f6281", "marvell,kirkwood";
9
10 memory {
11 device_type = "memory";
12 reg = <0x00000000 0x10000000>;
13 };
14
15 chosen {
16 bootargs = "console=ttyS0,115200n8 earlyprintk";
17 linux,initrd-start = <0x4500040>;
18 linux,initrd-end = <0x4800000>;
19 };
20
21 ocp@f1000000 {
22 pinctrl: pinctrl@10000 {
23
24 pinctrl-0 = < &pmx_gpio_12 &pmx_gpio_35
25 &pmx_gpio_41 &pmx_gpio_42
26 &pmx_gpio_43 &pmx_gpio_44
27 &pmx_gpio_45 &pmx_gpio_46
28 &pmx_gpio_47 &pmx_gpio_48 >;
29 pinctrl-names = "default";
30
31 pmx_gpio_12: pmx-gpio-12 {
32 marvell,pins = "mpp12";
33 marvell,function = "gpio";
34 };
35 pmx_gpio_35: pmx-gpio-35 {
36 marvell,pins = "mpp35";
37 marvell,function = "gpio";
38 };
39 pmx_gpio_41: pmx-gpio-41 {
40 marvell,pins = "mpp41";
41 marvell,function = "gpio";
42 };
43 pmx_gpio_42: pmx-gpio-42 {
44 marvell,pins = "mpp42";
45 marvell,function = "gpio";
46 };
47 pmx_gpio_43: pmx-gpio-43 {
48 marvell,pins = "mpp43";
49 marvell,function = "gpio";
50 };
51 pmx_gpio_44: pmx-gpio-44 {
52 marvell,pins = "mpp44";
53 marvell,function = "gpio";
54 };
55 pmx_gpio_45: pmx-gpio-45 {
56 marvell,pins = "mpp45";
57 marvell,function = "gpio";
58 };
59 pmx_gpio_46: pmx-gpio-46 {
60 marvell,pins = "mpp46";
61 marvell,function = "gpio";
62 };
63 pmx_gpio_47: pmx-gpio-47 {
64 marvell,pins = "mpp47";
65 marvell,function = "gpio";
66 };
67 pmx_gpio_48: pmx-gpio-48 {
68 marvell,pins = "mpp48";
69 marvell,function = "gpio";
70 };
71 };
72 i2c@11000 {
73 status = "okay";
74
75 lm63: lm63@4c {
76 compatible = "national,lm63";
77 reg = <0x4c>;
78 };
79 };
80 serial@12000 {
81 clock-frequency = <200000000>;
82 status = "ok";
83 };
84
85 nand@3000000 {
86 status = "okay";
87
88 partition@0 {
89 label = "uboot";
90 reg = <0x0000000 0xc0000>;
91 };
92
93 partition@a0000 {
94 label = "env";
95 reg = <0xa0000 0x20000>;
96 };
97
98 partition@100000 {
99 label = "zImage";
100 reg = <0x100000 0x300000>;
101 };
102
103 partition@540000 {
104 label = "initrd";
105 reg = <0x540000 0x300000>;
106 };
107
108 partition@980000 {
109 label = "boot";
110 reg = <0x980000 0x1f400000>;
111 };
112 };
113 };
114
115 gpio-leds {
116 compatible = "gpio-leds";
117
118 led-level {
119 label = "led_level";
120 gpios = <&gpio1 9 0>;
121 linux,default-trigger = "default-on";
122 };
123 power-blue {
124 label = "power:blue";
125 gpios = <&gpio1 10 0>;
126 linux,default-trigger = "timer";
127 };
128 power-red {
129 label = "power:red";
130 gpios = <&gpio1 11 0>;
131 };
132 usb1 {
133 label = "usb1:blue";
134 gpios = <&gpio1 12 0>;
135 };
136 usb2 {
137 label = "usb2:blue";
138 gpios = <&gpio1 13 0>;
139 };
140 usb3 {
141 label = "usb3:blue";
142 gpios = <&gpio1 14 0>;
143 };
144 usb4 {
145 label = "usb4:blue";
146 gpios = <&gpio1 15 0>;
147 };
148 otb {
149 label = "otb:blue";
150 gpios = <&gpio1 16 0>;
151 };
152 };
153
154 gpio_keys {
155 compatible = "gpio-keys";
156 #address-cells = <1>;
157 #size-cells = <0>;
158 button@1 {
159 label = "OTB Button";
160 linux,code = <133>;
161 gpios = <&gpio1 3 1>;
162 debounce-interval = <100>;
163 };
164 button@2 {
165 label = "Reset";
166 linux,code = <0x198>;
167 gpios = <&gpio0 12 1>;
168 debounce-interval = <100>;
169 };
170 };
171};
diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
deleted file mode 100644
index 6cae4599c4b..00000000000
--- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
+++ /dev/null
@@ -1,194 +0,0 @@
1/dts-v1/;
2
3/include/ "kirkwood.dtsi"
4/include/ "kirkwood-6281.dtsi"
5
6/ {
7 model = "Iomega StorCenter ix2-200";
8 compatible = "iom,ix2-200", "marvell,kirkwood-88f6281", "marvell,kirkwood";
9
10 memory {
11 device_type = "memory";
12 reg = <0x00000000 0x10000000>;
13 };
14
15 chosen {
16 bootargs = "console=ttyS0,115200n8 earlyprintk";
17 };
18
19 ocp@f1000000 {
20 pinctrl: pinctrl@10000 {
21
22 pinctrl-0 = < &pmx_button_reset &pmx_button_power
23 &pmx_led_backup &pmx_led_power
24 &pmx_button_otb &pmx_led_rebuild
25 &pmx_led_health
26 &pmx_led_sata_brt_ctrl_1
27 &pmx_led_sata_brt_ctrl_2
28 &pmx_led_backup_brt_ctrl_1
29 &pmx_led_backup_brt_ctrl_2
30 &pmx_led_power_brt_ctrl_1
31 &pmx_led_power_brt_ctrl_2
32 &pmx_led_health_brt_ctrl_1
33 &pmx_led_health_brt_ctrl_2
34 &pmx_led_rebuild_brt_ctrl_1
35 &pmx_led_rebuild_brt_ctrl_2 >;
36 pinctrl-names = "default";
37
38 pmx_button_reset: pmx-button-reset {
39 marvell,pins = "mpp12";
40 marvell,function = "gpio";
41 };
42 pmx_button_power: pmx-button-power {
43 marvell,pins = "mpp14";
44 marvell,function = "gpio";
45 };
46 pmx_led_backup: pmx-led-backup {
47 marvell,pins = "mpp15";
48 marvell,function = "gpio";
49 };
50 pmx_led_power: pmx-led-power {
51 marvell,pins = "mpp16";
52 marvell,function = "gpio";
53 };
54 pmx_button_otb: pmx-button-otb {
55 marvell,pins = "mpp35";
56 marvell,function = "gpio";
57 };
58 pmx_led_rebuild: pmx-led-rebuild {
59 marvell,pins = "mpp36";
60 marvell,function = "gpio";
61 };
62 pmx_led_health: pmx-led_health {
63 marvell,pins = "mpp37";
64 marvell,function = "gpio";
65 };
66 pmx_led_sata_brt_ctrl_1: pmx-led-sata-brt-ctrl-1 {
67 marvell,pins = "mpp38";
68 marvell,function = "gpio";
69 };
70 pmx_led_sata_brt_ctrl_2: pmx-led-sata-brt-ctrl-2 {
71 marvell,pins = "mpp39";
72 marvell,function = "gpio";
73 };
74 pmx_led_backup_brt_ctrl_1: pmx-led-backup-brt-ctrl-1 {
75 marvell,pins = "mpp40";
76 marvell,function = "gpio";
77 };
78 pmx_led_backup_brt_ctrl_2: pmx-led-backup-brt-ctrl-2 {
79 marvell,pins = "mpp41";
80 marvell,function = "gpio";
81 };
82 pmx_led_power_brt_ctrl_1: pmx-led-power-brt-ctrl-1 {
83 marvell,pins = "mpp42";
84 marvell,function = "gpio";
85 };
86 pmx_led_power_brt_ctrl_2: pmx-led-power-brt-ctrl-2 {
87 marvell,pins = "mpp43";
88 marvell,function = "gpio";
89 };
90 pmx_led_health_brt_ctrl_1: pmx-led-health-brt-ctrl-1 {
91 marvell,pins = "mpp44";
92 marvell,function = "gpio";
93 };
94 pmx_led_health_brt_ctrl_2: pmx-led-health-brt-ctrl-2 {
95 marvell,pins = "mpp45";
96 marvell,function = "gpio";
97 };
98 pmx_led_rebuild_brt_ctrl_1: pmx-led-rebuild-brt-ctrl-1 {
99 marvell,pins = "mpp44";
100 marvell,function = "gpio";
101 };
102 pmx_led_rebuild_brt_ctrl_2: pmx-led-rebuild-brt-ctrl-2 {
103 marvell,pins = "mpp45";
104 marvell,function = "gpio";
105 };
106
107 };
108 i2c@11000 {
109 status = "okay";
110
111 lm63: lm63@4c {
112 compatible = "national,lm63";
113 reg = <0x4c>;
114 };
115 };
116
117 serial@12000 {
118 clock-frequency = <200000000>;
119 status = "ok";
120 };
121
122 nand@3000000 {
123 status = "okay";
124
125 partition@0 {
126 label = "u-boot";
127 reg = <0x0000000 0x100000>;
128 read-only;
129 };
130
131 partition@a0000 {
132 label = "env";
133 reg = <0xa0000 0x20000>;
134 read-only;
135 };
136
137 partition@100000 {
138 label = "uImage";
139 reg = <0x100000 0x300000>;
140 };
141
142 partition@400000 {
143 label = "uInitrd";
144 reg = <0x540000 0x1000000>;
145 };
146 };
147 sata@80000 {
148 status = "okay";
149 nr-ports = <2>;
150 };
151
152 };
153 gpio-leds {
154 compatible = "gpio-leds";
155
156 power_led {
157 label = "status:white:power_led";
158 gpios = <&gpio0 16 0>;
159 linux,default-trigger = "default-on";
160 };
161 health_led1 {
162 label = "status:red:health_led";
163 gpios = <&gpio1 5 0>;
164 };
165 health_led2 {
166 label = "status:white:health_led";
167 gpios = <&gpio1 4 0>;
168 };
169 backup_led {
170 label = "status:blue:backup_led";
171 gpios = <&gpio0 15 0>;
172 };
173 };
174 gpio-keys {
175 compatible = "gpio-keys";
176 #address-cells = <1>;
177 #size-cells = <0>;
178 Power {
179 label = "Power Button";
180 linux,code = <116>;
181 gpios = <&gpio0 14 1>;
182 };
183 Reset {
184 label = "Reset Button";
185 linux,code = <0x198>;
186 gpios = <&gpio0 12 1>;
187 };
188 OTB {
189 label = "OTB Button";
190 linux,code = <133>;
191 gpios = <&gpio1 3 1>;
192 };
193 };
194};
diff --git a/arch/arm/boot/dts/kirkwood-is2.dts b/arch/arm/boot/dts/kirkwood-is2.dts
deleted file mode 100644
index 0bdce0ad727..00000000000
--- a/arch/arm/boot/dts/kirkwood-is2.dts
+++ /dev/null
@@ -1,30 +0,0 @@
1/dts-v1/;
2
3/include/ "kirkwood-ns2-common.dtsi"
4
5/ {
6 model = "LaCie Internet Space v2";
7 compatible = "lacie,inetspace_v2", "marvell,kirkwood-88f6281", "marvell,kirkwood";
8
9 memory {
10 device_type = "memory";
11 reg = <0x00000000 0x8000000>;
12 };
13
14 ocp@f1000000 {
15 sata@80000 {
16 status = "okay";
17 nr-ports = <1>;
18 };
19 };
20
21 ns2-leds {
22 compatible = "lacie,ns2-leds";
23
24 blue-sata {
25 label = "ns2:blue:sata";
26 slow-gpio = <&gpio0 29 0>;
27 cmd-gpio = <&gpio0 30 0>;
28 };
29 };
30};
diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
deleted file mode 100644
index 8db3123ac80..00000000000
--- a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
+++ /dev/null
@@ -1,46 +0,0 @@
1/dts-v1/;
2
3/include/ "kirkwood.dtsi"
4/include/ "kirkwood-98dx4122.dtsi"
5
6/ {
7 model = "Keymile Kirkwood Reference Design";
8 compatible = "keymile,km_kirkwood", "marvell,kirkwood-98DX4122", "marvell,kirkwood";
9
10 memory {
11 device_type = "memory";
12 reg = <0x00000000 0x08000000>;
13 };
14
15 chosen {
16 bootargs = "console=ttyS0,115200n8 earlyprintk";
17 };
18
19 ocp@f1000000 {
20 pinctrl: pinctrl@10000 {
21
22 pinctrl-0 = < &pmx_nand &pmx_i2c_gpio_sda
23 &pmx_i2c_gpio_scl >;
24 pinctrl-names = "default";
25
26 pmx_i2c_gpio_sda: pmx-gpio-sda {
27 marvell,pins = "mpp8";
28 marvell,function = "gpio";
29 };
30 pmx_i2c_gpio_scl: pmx-gpio-scl {
31 marvell,pins = "mpp9";
32 marvell,function = "gpio";
33 };
34 };
35
36 serial@12000 {
37 clock-frequency = <200000000>;
38 status = "ok";
39 };
40
41 nand@3000000 {
42 status = "ok";
43 chip-delay = <25>;
44 };
45 };
46};
diff --git a/arch/arm/boot/dts/kirkwood-lschlv2.dts b/arch/arm/boot/dts/kirkwood-lschlv2.dts
deleted file mode 100644
index 9510c9ea666..00000000000
--- a/arch/arm/boot/dts/kirkwood-lschlv2.dts
+++ /dev/null
@@ -1,20 +0,0 @@
1/dts-v1/;
2
3/include/ "kirkwood-lsxl.dtsi"
4
5/ {
6 model = "Buffalo Linkstation LS-CHLv2";
7 compatible = "buffalo,lschlv2", "buffalo,lsxl", "marvell,kirkwood-88f6281", "marvell,kirkwood";
8
9 memory {
10 device_type = "memory";
11 reg = <0x00000000 0x4000000>;
12 };
13
14 ocp@f1000000 {
15 serial@12000 {
16 clock-frequency = <166666667>;
17 status = "okay";
18 };
19 };
20};
diff --git a/arch/arm/boot/dts/kirkwood-lsxhl.dts b/arch/arm/boot/dts/kirkwood-lsxhl.dts
deleted file mode 100644
index 739019c4cba..00000000000
--- a/arch/arm/boot/dts/kirkwood-lsxhl.dts
+++ /dev/null
@@ -1,20 +0,0 @@
1/dts-v1/;
2
3/include/ "kirkwood-lsxl.dtsi"
4
5/ {
6 model = "Buffalo Linkstation LS-XHL";
7 compatible = "buffalo,lsxhl", "buffalo,lsxl", "marvell,kirkwood-88f6281", "marvell,kirkwood";
8
9 memory {
10 device_type = "memory";
11 reg = <0x00000000 0x10000000>;
12 };
13
14 ocp@f1000000 {
15 serial@12000 {
16 clock-frequency = <200000000>;
17 status = "okay";
18 };
19 };
20};
diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
deleted file mode 100644
index 37d45c4f88f..00000000000
--- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi
+++ /dev/null
@@ -1,203 +0,0 @@
1/include/ "kirkwood.dtsi"
2/include/ "kirkwood-6281.dtsi"
3
4/ {
5 chosen {
6 bootargs = "console=ttyS0,115200n8 earlyprintk";
7 };
8
9 ocp@f1000000 {
10 pinctrl: pinctrl@10000 {
11
12 pinctrl-0 = < &pmx_power_hdd &pmx_usb_vbus
13 &pmx_fan_low &pmx_fan_high
14 &pmx_led_function_red &pmx_led_alarm
15 &pmx_led_info &pmx_led_power
16 &pmx_fan_lock &pmx_button_function
17 &pmx_power_switch &pmx_power_auto_switch
18 &pmx_led_function_blue >;
19 pinctrl-names = "default";
20
21 pmx_power_hdd: pmx-power-hdd {
22 marvell,pins = "mpp10";
23 marvell,function = "gpo";
24 };
25 pmx_usb_vbus: pmx-usb-vbus {
26 marvell,pins = "mpp11";
27 marvell,function = "gpio";
28 };
29 pmx_fan_high: pmx-fan-high {
30 marvell,pins = "mpp18";
31 marvell,function = "gpo";
32 };
33 pmx_fan_low: pmx-fan-low {
34 marvell,pins = "mpp19";
35 marvell,function = "gpo";
36 };
37 pmx_led_function_blue: pmx-led-function-blue {
38 marvell,pins = "mpp36";
39 marvell,function = "gpio";
40 };
41 pmx_led_alarm: pmx-led-alarm {
42 marvell,pins = "mpp37";
43 marvell,function = "gpio";
44 };
45 pmx_led_info: pmx-led-info {
46 marvell,pins = "mpp38";
47 marvell,function = "gpio";
48 };
49 pmx_led_power: pmx-led-power {
50 marvell,pins = "mpp39";
51 marvell,function = "gpio";
52 };
53 pmx_fan_lock: pmx-fan-lock {
54 marvell,pins = "mpp40";
55 marvell,function = "gpio";
56 };
57 pmx_button_function: pmx-button-function {
58 marvell,pins = "mpp41";
59 marvell,function = "gpio";
60 };
61 pmx_power_switch: pmx-power-switch {
62 marvell,pins = "mpp42";
63 marvell,function = "gpio";
64 };
65 pmx_power_auto_switch: pmx-power-auto-switch {
66 marvell,pins = "mpp43";
67 marvell,function = "gpio";
68 };
69 pmx_led_function_red: pmx-led-function_red {
70 marvell,pins = "mpp48";
71 marvell,function = "gpio";
72 };
73
74 };
75 sata@80000 {
76 status = "okay";
77 nr-ports = <1>;
78 };
79
80 spi@10600 {
81 status = "okay";
82
83 m25p40@0 {
84 #address-cells = <1>;
85 #size-cells = <1>;
86 compatible = "m25p40";
87 reg = <0>;
88 spi-max-frequency = <25000000>;
89 mode = <0>;
90
91 partition@0 {
92 reg = <0x0 0x60000>;
93 label = "uboot";
94 read-only;
95 };
96
97 partition@60000 {
98 reg = <0x60000 0x10000>;
99 label = "dtb";
100 read-only;
101 };
102
103 partition@70000 {
104 reg = <0x70000 0x10000>;
105 label = "uboot_env";
106 };
107 };
108 };
109 };
110
111 gpio_keys {
112 compatible = "gpio-keys";
113 #address-cells = <1>;
114 #size-cells = <0>;
115 button@1 {
116 label = "Function Button";
117 linux,code = <357>;
118 gpios = <&gpio1 9 1>;
119 };
120 button@2 {
121 label = "Power-on Switch";
122 linux,code = <0>;
123 linux,input-type = <5>;
124 gpios = <&gpio1 10 1>;
125 };
126 button@3 {
127 label = "Power-auto Switch";
128 linux,code = <1>;
129 linux,input-type = <5>;
130 gpios = <&gpio1 11 1>;
131 };
132 };
133
134 gpio_leds {
135 compatible = "gpio-leds";
136
137 led@1 {
138 label = "lsxl:blue:func";
139 gpios = <&gpio1 4 1>;
140 };
141
142 led@2 {
143 label = "lsxl:red:alarm";
144 gpios = <&gpio1 5 1>;
145 };
146
147 led@3 {
148 label = "lsxl:amber:info";
149 gpios = <&gpio1 6 1>;
150 };
151
152 led@4 {
153 label = "lsxl:blue:power";
154 gpios = <&gpio1 7 1>;
155 linux,default-trigger = "default-on";
156 };
157
158 led@5 {
159 label = "lsxl:red:func";
160 gpios = <&gpio1 16 1>;
161 };
162 };
163
164 gpio_fan {
165 compatible = "gpio-fan";
166 gpios = <&gpio0 19 1
167 &gpio0 18 1>;
168 gpio-fan,speed-map = <0 3
169 1500 2
170 3250 1
171 5000 0>;
172 alarm-gpios = <&gpio1 8 0>;
173 };
174
175 regulators {
176 compatible = "simple-bus";
177 #address-cells = <1>;
178 #size-cells = <0>;
179
180 usb_power: regulator@1 {
181 compatible = "regulator-fixed";
182 reg = <1>;
183 regulator-name = "USB Power";
184 regulator-min-microvolt = <5000000>;
185 regulator-max-microvolt = <5000000>;
186 enable-active-high;
187 regulator-always-on;
188 regulator-boot-on;
189 gpio = <&gpio0 11 0>;
190 };
191 hdd_power: regulator@2 {
192 compatible = "regulator-fixed";
193 reg = <2>;
194 regulator-name = "HDD Power";
195 regulator-min-microvolt = <5000000>;
196 regulator-max-microvolt = <5000000>;
197 enable-active-high;
198 regulator-always-on;
199 regulator-boot-on;
200 gpio = <&gpio0 10 0>;
201 };
202 };
203};
diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts
deleted file mode 100644
index 262c6540376..00000000000
--- a/arch/arm/boot/dts/kirkwood-mplcec4.dts
+++ /dev/null
@@ -1,178 +0,0 @@
1/dts-v1/;
2
3/include/ "kirkwood.dtsi"
4/include/ "kirkwood-6281.dtsi"
5
6/ {
7 model = "MPL CEC4";
8 compatible = "mpl,cec4-10", "mpl,cec4", "marvell,kirkwood-88f6281", "marvell,kirkwood";
9
10 memory {
11 device_type = "memory";
12 reg = <0x00000000 0x20000000>;
13 };
14
15 chosen {
16 bootargs = "console=ttyS0,115200n8 earlyprintk";
17 };
18
19 ocp@f1000000 {
20 pinctrl: pinctrl@10000 {
21
22 pinctrl-0 = < &pmx_nand &pmx_uart0
23 &pmx_led_health &pmx_sdio
24 &pmx_sata0 &pmx_sata1
25 &pmx_led_user1o
26 &pmx_led_user1g &pmx_led_user0o
27 &pmx_led_user0g &pmx_led_misc
28 &pmx_sdio_cd
29 >;
30 pinctrl-names = "default";
31
32 pmx_led_health: pmx-led-health {
33 marvell,pins = "mpp7";
34 marvell,function = "gpo";
35 };
36
37 pmx_sata1: pmx-sata1 {
38 marvell,pins = "mpp34";
39 marvell,function = "sata1";
40 };
41
42 pmx_sata0: pmx-sata0 {
43 marvell,pins = "mpp35";
44 marvell,function = "sata0";
45 };
46
47 pmx_led_user1o: pmx-led-user1o {
48 marvell,pins = "mpp40";
49 marvell,function = "gpio";
50 };
51
52 pmx_led_user1g: pmx-led-user1g {
53 marvell,pins = "mpp41";
54 marvell,function = "gpio";
55 };
56
57 pmx_led_user0o: pmx-led-user0o {
58 marvell,pins = "mpp44";
59 marvell,function = "gpio";
60 };
61
62 pmx_led_user0g: pmx-led-user0g {
63 marvell,pins = "mpp45";
64 marvell,function = "gpio";
65 };
66
67 pmx_led_misc: pmx-led-misc {
68 marvell,pins = "mpp46";
69 marvell,function = "gpio";
70 };
71
72 pmx_sdio_cd: pmx-sdio-cd {
73 marvell,pins = "mpp47";
74 marvell,function = "gpio";
75 };
76 };
77
78 i2c@11000 {
79 status = "okay";
80
81 rtc@51 {
82 compatible = "nxp,pcf8563";
83 reg = <0x51>;
84 };
85
86 eeprom@57 {
87 compatible = "atmel,24c02";
88 reg = <0x57>;
89 };
90
91 };
92
93 serial@12000 {
94 clock-frequency = <200000000>;
95 status = "ok";
96 };
97
98 nand@3000000 {
99 status = "okay";
100
101 partition@0 {
102 label = "uboot";
103 reg = <0x0000000 0x100000>;
104 };
105
106 partition@100000 {
107 label = "env";
108 reg = <0x100000 0x80000>;
109 };
110
111 partition@180000 {
112 label = "fdt";
113 reg = <0x180000 0x80000>;
114 };
115
116 partition@200000 {
117 label = "kernel";
118 reg = <0x200000 0x400000>;
119 };
120
121 partition@600000 {
122 label = "rootfs";
123 reg = <0x600000 0x1fa00000>;
124 };
125 };
126
127 rtc@10300 {
128 status = "disabled";
129 };
130
131 sata@80000 {
132 nr-ports = <2>;
133 status = "okay";
134
135 };
136 };
137
138 gpio-leds {
139 compatible = "gpio-leds";
140
141 health {
142 label = "status:green:health";
143 gpios = <&gpio0 7 1>;
144 };
145
146 user1o {
147 label = "user1:orange";
148 gpios = <&gpio1 8 1>;
149 default-state = "on";
150 };
151
152 user1g {
153 label = "user1:green";
154 gpios = <&gpio1 9 1>;
155 default-state = "on";
156 };
157
158 user0o {
159 label = "user0:orange";
160 gpios = <&gpio1 12 1>;
161 default-state = "on";
162 };
163
164 user0g {
165 label = "user0:green";
166 gpios = <&gpio1 13 1>;
167 default-state = "on";
168 };
169
170 misc {
171 label = "status:orange:misc";
172 gpios = <&gpio1 14 1>;
173 default-state = "on";
174 };
175
176 };
177};
178
diff --git a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
deleted file mode 100644
index 9bc6785ad22..00000000000
--- a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
+++ /dev/null
@@ -1,63 +0,0 @@
1/include/ "kirkwood.dtsi"
2
3/ {
4 chosen {
5 bootargs = "console=ttyS0,115200n8";
6 };
7
8 ocp@f1000000 {
9 serial@12000 {
10 clock-frequency = <166666667>;
11 status = "okay";
12 };
13
14 spi@10600 {
15 status = "okay";
16
17 flash@0 {
18 #address-cells = <1>;
19 #size-cells = <1>;
20 compatible = "mx25l4005a";
21 reg = <0>;
22 spi-max-frequency = <20000000>;
23 mode = <0>;
24
25 partition@0 {
26 reg = <0x0 0x80000>;
27 label = "u-boot";
28 };
29 };
30 };
31
32 i2c@11000 {
33 status = "okay";
34
35 eeprom@50 {
36 compatible = "at,24c04";
37 pagesize = <16>;
38 reg = <0x50>;
39 };
40 };
41 };
42
43 gpio_keys {
44 compatible = "gpio-keys";
45 #address-cells = <1>;
46 #size-cells = <0>;
47
48 button@1 {
49 label = "Power push button";
50 linux,code = <116>;
51 gpios = <&gpio1 0 0>;
52 };
53 };
54
55 gpio-leds {
56 compatible = "gpio-leds";
57
58 red-fail {
59 label = "ns2:red:fail";
60 gpios = <&gpio0 12 0>;
61 };
62 };
63};
diff --git a/arch/arm/boot/dts/kirkwood-ns2.dts b/arch/arm/boot/dts/kirkwood-ns2.dts
deleted file mode 100644
index f2d36ecf36d..00000000000
--- a/arch/arm/boot/dts/kirkwood-ns2.dts
+++ /dev/null
@@ -1,30 +0,0 @@
1/dts-v1/;
2
3/include/ "kirkwood-ns2-common.dtsi"
4
5/ {
6 model = "LaCie Network Space v2";
7 compatible = "lacie,netspace_v2", "marvell,kirkwood-88f6281", "marvell,kirkwood";
8
9 memory {
10 device_type = "memory";
11 reg = <0x00000000 0x10000000>;
12 };
13
14 ocp@f1000000 {
15 sata@80000 {
16 status = "okay";
17 nr-ports = <1>;
18 };
19 };
20
21 ns2-leds {
22 compatible = "lacie,ns2-leds";
23
24 blue-sata {
25 label = "ns2:blue:sata";
26 slow-gpio = <&gpio0 29 0>;
27 cmd-gpio = <&gpio0 30 0>;
28 };
29 };
30};
diff --git a/arch/arm/boot/dts/kirkwood-ns2lite.dts b/arch/arm/boot/dts/kirkwood-ns2lite.dts
deleted file mode 100644
index b02eb4ea1bb..00000000000
--- a/arch/arm/boot/dts/kirkwood-ns2lite.dts
+++ /dev/null
@@ -1,30 +0,0 @@
1/dts-v1/;
2
3/include/ "kirkwood-ns2-common.dtsi"
4
5/ {
6 model = "LaCie Network Space Lite v2";
7 compatible = "lacie,netspace_lite_v2", "marvell,kirkwood-88f6192", "marvell,kirkwood";
8
9 memory {
10 device_type = "memory";
11 reg = <0x00000000 0x8000000>;
12 };
13
14 ocp@f1000000 {
15 sata@80000 {
16 status = "okay";
17 nr-ports = <1>;
18 };
19 };
20
21 gpio-leds {
22 compatible = "gpio-leds";
23
24 blue-sata {
25 label = "ns2:blue:sata";
26 gpios = <&gpio0 30 1>;
27 linux,default-trigger = "default-on";
28 };
29 };
30};
diff --git a/arch/arm/boot/dts/kirkwood-ns2max.dts b/arch/arm/boot/dts/kirkwood-ns2max.dts
deleted file mode 100644
index bcec4d6cada..00000000000
--- a/arch/arm/boot/dts/kirkwood-ns2max.dts
+++ /dev/null
@@ -1,49 +0,0 @@
1/dts-v1/;
2
3/include/ "kirkwood-ns2-common.dtsi"
4
5/ {
6 model = "LaCie Network Space Max v2";
7 compatible = "lacie,netspace_max_v2", "marvell,kirkwood-88f6281", "marvell,kirkwood";
8
9 memory {
10 device_type = "memory";
11 reg = <0x00000000 0x10000000>;
12 };
13
14 ocp@f1000000 {
15 sata@80000 {
16 status = "okay";
17 nr-ports = <2>;
18 };
19 };
20
21 gpio_fan {
22 compatible = "gpio-fan";
23 gpios = <&gpio0 22 1
24 &gpio0 7 1
25 &gpio1 1 1
26 &gpio0 23 1>;
27 gpio-fan,speed-map =
28 < 0 0
29 1500 15
30 1700 14
31 1800 13
32 2100 12
33 3100 11
34 3300 10
35 4300 9
36 5500 8>;
37 alarm-gpios = <&gpio0 25 1>;
38 };
39
40 ns2-leds {
41 compatible = "lacie,ns2-leds";
42
43 blue-sata {
44 label = "ns2:blue:sata";
45 slow-gpio = <&gpio0 29 0>;
46 cmd-gpio = <&gpio0 30 0>;
47 };
48 };
49};
diff --git a/arch/arm/boot/dts/kirkwood-ns2mini.dts b/arch/arm/boot/dts/kirkwood-ns2mini.dts
deleted file mode 100644
index b79f5eb2558..00000000000
--- a/arch/arm/boot/dts/kirkwood-ns2mini.dts
+++ /dev/null
@@ -1,49 +0,0 @@
1/dts-v1/;
2
3/include/ "kirkwood-ns2-common.dtsi"
4
5/ {
6 model = "LaCie Network Space Mini v2";
7 compatible = "lacie,netspace_mini_v2", "marvell,kirkwood-88f6192", "marvell,kirkwood";
8
9 memory {
10 device_type = "memory";
11 reg = <0x00000000 0x8000000>;
12 };
13
14 ocp@f1000000 {
15 sata@80000 {
16 status = "okay";
17 nr-ports = <1>;
18 };
19 };
20
21 gpio_fan {
22 compatible = "gpio-fan";
23 gpios = <&gpio0 22 1
24 &gpio0 7 1
25 &gpio1 1 1
26 &gpio0 23 1>;
27 gpio-fan,speed-map =
28 < 0 0
29 3000 15
30 3180 14
31 4140 13
32 4570 12
33 6760 11
34 7140 10
35 7980 9
36 9200 8>;
37 alarm-gpios = <&gpio0 25 1>;
38 };
39
40 ns2-leds {
41 compatible = "lacie,ns2-leds";
42
43 blue-sata {
44 label = "ns2:blue:sata";
45 slow-gpio = <&gpio0 29 0>;
46 cmd-gpio = <&gpio0 30 0>;
47 };
48 };
49};
diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/kirkwood-nsa310.dts
deleted file mode 100644
index 5509f965954..00000000000
--- a/arch/arm/boot/dts/kirkwood-nsa310.dts
+++ /dev/null
@@ -1,144 +0,0 @@
1/dts-v1/;
2
3/include/ "kirkwood.dtsi"
4
5/ {
6 model = "ZyXEL NSA310";
7 compatible = "zyxel,nsa310", "marvell,kirkwood-88f6281", "marvell,kirkwood";
8
9 memory {
10 device_type = "memory";
11 reg = <0x00000000 0x10000000>;
12 };
13
14 chosen {
15 bootargs = "console=ttyS0,115200";
16 };
17
18 ocp@f1000000 {
19
20 serial@12000 {
21 clock-frequency = <200000000>;
22 status = "ok";
23 };
24
25 sata@80000 {
26 status = "okay";
27 nr-ports = <2>;
28 };
29
30 i2c@11000 {
31 status = "okay";
32 };
33
34 nand@3000000 {
35 status = "okay";
36 chip-delay = <35>;
37
38 partition@0 {
39 label = "uboot";
40 reg = <0x0000000 0x0100000>;
41 read-only;
42 };
43 partition@100000 {
44 label = "uboot_env";
45 reg = <0x0100000 0x0080000>;
46 };
47 partition@180000 {
48 label = "key_store";
49 reg = <0x0180000 0x0080000>;
50 };
51 partition@200000 {
52 label = "info";
53 reg = <0x0200000 0x0080000>;
54 };
55 partition@280000 {
56 label = "etc";
57 reg = <0x0280000 0x0a00000>;
58 };
59 partition@c80000 {
60 label = "kernel_1";
61 reg = <0x0c80000 0x0a00000>;
62 };
63 partition@1680000 {
64 label = "rootfs1";
65 reg = <0x1680000 0x2fc0000>;
66 };
67 partition@4640000 {
68 label = "kernel_2";
69 reg = <0x4640000 0x0a00000>;
70 };
71 partition@5040000 {
72 label = "rootfs2";
73 reg = <0x5040000 0x2fc0000>;
74 };
75 };
76 };
77
78 gpio_keys {
79 compatible = "gpio-keys";
80 #address-cells = <1>;
81 #size-cells = <0>;
82
83 button@1 {
84 label = "Power Button";
85 linux,code = <116>;
86 gpios = <&gpio1 14 0>;
87 };
88 button@2 {
89 label = "Copy Button";
90 linux,code = <133>;
91 gpios = <&gpio1 5 1>;
92 };
93 button@3 {
94 label = "Reset Button";
95 linux,code = <0x198>;
96 gpios = <&gpio1 4 1>;
97 };
98 };
99
100 gpio-leds {
101 compatible = "gpio-leds";
102
103 green-sys {
104 label = "nsa310:green:sys";
105 gpios = <&gpio0 28 0>;
106 };
107 red-sys {
108 label = "nsa310:red:sys";
109 gpios = <&gpio0 29 0>;
110 };
111 green-hdd {
112 label = "nsa310:green:hdd";
113 gpios = <&gpio1 9 0>;
114 };
115 red-hdd {
116 label = "nsa310:red:hdd";
117 gpios = <&gpio1 10 0>;
118 };
119 green-esata {
120 label = "nsa310:green:esata";
121 gpios = <&gpio0 12 0>;
122 };
123 red-esata {
124 label = "nsa310:red:esata";
125 gpios = <&gpio0 13 0>;
126 };
127 green-usb {
128 label = "nsa310:green:usb";
129 gpios = <&gpio0 15 0>;
130 };
131 red-usb {
132 label = "nsa310:red:usb";
133 gpios = <&gpio0 16 0>;
134 };
135 green-copy {
136 label = "nsa310:green:copy";
137 gpios = <&gpio1 7 0>;
138 };
139 red-copy {
140 label = "nsa310:red:copy";
141 gpios = <&gpio1 8 0>;
142 };
143 };
144};
diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
deleted file mode 100644
index 49d3d74d4d3..00000000000
--- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
+++ /dev/null
@@ -1,98 +0,0 @@
1/dts-v1/;
2
3/include/ "kirkwood.dtsi"
4/include/ "kirkwood-6282.dtsi"
5
6/ {
7 model = "Plat'Home OpenBlocksA6";
8 compatible = "plathome,openblocks-a6", "marvell,kirkwood-88f6283", "marvell,kirkwood";
9
10 memory {
11 device_type = "memory";
12 reg = <0x00000000 0x20000000>;
13 };
14
15 chosen {
16 bootargs = "console=ttyS0,115200n8 earlyprintk";
17 };
18
19 ocp@f1000000 {
20 serial@12000 {
21 clock-frequency = <200000000>;
22 status = "ok";
23 };
24
25 serial@12100 {
26 clock-frequency = <200000000>;
27 status = "ok";
28 };
29
30 nand@3000000 {
31 chip-delay = <25>;
32 status = "okay";
33
34 partition@0 {
35 label = "uboot";
36 reg = <0x0 0x90000>;
37 };
38
39 partition@90000 {
40 label = "env";
41 reg = <0x90000 0x44000>;
42 };
43
44 partition@d4000 {
45 label = "test";
46 reg = <0xd4000 0x24000>;
47 };
48
49 partition@f4000 {
50 label = "conf";
51 reg = <0xf4000 0x400000>;
52 };
53
54 partition@4f4000 {
55 label = "linux";
56 reg = <0x4f4000 0x1d20000>;
57 };
58
59 partition@2214000 {
60 label = "user";
61 reg = <0x2214000 0x1dec000>;
62 };
63 };
64
65 sata@80000 {
66 nr-ports = <1>;
67 status = "okay";
68 };
69
70 i2c@11100 {
71 status = "okay";
72
73 s35390a: s35390a@30 {
74 compatible = "s35390a";
75 reg = <0x30>;
76 };
77 };
78 };
79
80 gpio-leds {
81 compatible = "gpio-leds";
82
83 led-red {
84 label = "obsa6:red:stat";
85 gpios = <&gpio1 9 1>;
86 };
87
88 led-green {
89 label = "obsa6:green:stat";
90 gpios = <&gpio1 10 1>;
91 };
92
93 led-yellow {
94 label = "obsa6:yellow:stat";
95 gpios = <&gpio1 11 1>;
96 };
97 };
98};
diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts
deleted file mode 100644
index cd15452a52a..00000000000
--- a/arch/arm/boot/dts/kirkwood-topkick.dts
+++ /dev/null
@@ -1,102 +0,0 @@
1/dts-v1/;
2
3/include/ "kirkwood.dtsi"
4
5/ {
6 model = "Univeral Scientific Industrial Co. Topkick-1281P2";
7 compatible = "usi,topkick-1281P2", "usi,topkick", "marvell,kirkwood-88f6282", "marvell,kirkwood";
8
9 memory {
10 device_type = "memory";
11 reg = <0x00000000 0x10000000>;
12 };
13
14 chosen {
15 bootargs = "console=ttyS0,115200n8 earlyprintk";
16 };
17
18 ocp@f1000000 {
19 serial@12000 {
20 clock-frequency = <200000000>;
21 status = "ok";
22 };
23
24 nand@3000000 {
25 status = "okay";
26
27 partition@0 {
28 label = "u-boot";
29 reg = <0x0000000 0x180000>;
30 };
31
32 partition@180000 {
33 label = "u-boot env";
34 reg = <0x0180000 0x20000>;
35 };
36
37 partition@200000 {
38 label = "uImage";
39 reg = <0x0200000 0x600000>;
40 };
41
42 partition@800000 {
43 label = "uInitrd";
44 reg = <0x0800000 0x1000000>;
45 };
46
47 partition@1800000 {
48 label = "rootfs";
49 reg = <0x1800000 0xe800000>;
50 };
51 };
52
53 sata@80000 {
54 status = "okay";
55 nr-ports = <1>;
56 };
57 };
58
59 gpio-leds {
60 compatible = "gpio-leds";
61
62 disk {
63 label = "topkick:yellow:disk";
64 gpios = <&gpio0 21 1>;
65 linux,default-trigger = "ide-disk";
66 };
67 system2 {
68 label = "topkick:red:system";
69 gpios = <&gpio1 5 1>;
70 };
71 system {
72 label = "topkick:blue:system";
73 gpios = <&gpio1 6 1>;
74 default-state = "on";
75 };
76 wifi {
77 label = "topkick:green:wifi";
78 gpios = <&gpio1 7 1>;
79 };
80 wifi2 {
81 label = "topkick:yellow:wifi";
82 gpios = <&gpio1 16 1>;
83 };
84 };
85 regulators {
86 compatible = "simple-bus";
87 #address-cells = <1>;
88 #size-cells = <0>;
89
90 sata0_power: regulator@1 {
91 compatible = "regulator-fixed";
92 reg = <1>;
93 regulator-name = "SATA0 Power";
94 regulator-min-microvolt = <5000000>;
95 regulator-max-microvolt = <5000000>;
96 enable-active-high;
97 regulator-always-on;
98 regulator-boot-on;
99 gpio = <&gpio1 4 0>;
100 };
101 };
102};
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
deleted file mode 100644
index 8295c833887..00000000000
--- a/arch/arm/boot/dts/kirkwood-ts219-6281.dts
+++ /dev/null
@@ -1,52 +0,0 @@
1/dts-v1/;
2
3/include/ "kirkwood-ts219.dtsi"
4/include/ "kirkwood-6281.dtsi"
5
6/ {
7 ocp@f1000000 {
8 pinctrl: pinctrl@10000 {
9
10 pinctrl-0 = < &pmx_uart0 &pmx_uart1 &pmx_spi
11 &pmx_twsi0 &pmx_sata0 &pmx_sata1
12 &pmx_ram_size &pmx_reset_button
13 &pmx_USB_copy_button &pmx_board_id>;
14 pinctrl-names = "default";
15
16 pmx_ram_size: pmx-ram-size {
17 /* RAM: 0: 256 MB, 1: 512 MB */
18 marvell,pins = "mpp36";
19 marvell,function = "gpio";
20 };
21 pmx_USB_copy_button: pmx-USB-copy-button {
22 marvell,pins = "mpp15";
23 marvell,function = "gpio";
24 };
25 pmx_reset_button: pmx-reset-button {
26 marvell,pins = "mpp16";
27 marvell,function = "gpio";
28 };
29 pmx_board_id: pmx-board-id {
30 /* 0: TS-11x, 1: TS-21x */
31 marvell,pins = "mpp44";
32 marvell,function = "gpio";
33 };
34 };
35 };
36
37 gpio_keys {
38 compatible = "gpio-keys";
39 #address-cells = <1>;
40 #size-cells = <0>;
41 button@1 {
42 label = "USB Copy";
43 linux,code = <133>;
44 gpios = <&gpio0 15 1>;
45 };
46 button@2 {
47 label = "Reset";
48 linux,code = <0x198>;
49 gpios = <&gpio0 16 1>;
50 };
51 };
52}; \ No newline at end of file
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
deleted file mode 100644
index df3f95dfba3..00000000000
--- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts
+++ /dev/null
@@ -1,52 +0,0 @@
1/dts-v1/;
2
3/include/ "kirkwood-ts219.dtsi"
4/include/ "kirkwood-6282.dtsi"
5
6/ {
7 ocp@f1000000 {
8 pinctrl: pinctrl@10000 {
9
10 pinctrl-0 = < &pmx_uart0 &pmx_uart1 &pmx_spi
11 &pmx_twsi0 &pmx_sata0 &pmx_sata1
12 &pmx_ram_size &pmx_reset_button
13 &pmx_USB_copy_button &pmx_board_id>;
14 pinctrl-names = "default";
15
16 pmx_ram_size: pmx-ram-size {
17 /* RAM: 0: 256 MB, 1: 512 MB */
18 marvell,pins = "mpp36";
19 marvell,function = "gpio";
20 };
21 pmx_reset_button: pmx-reset-button {
22 marvell,pins = "mpp37";
23 marvell,function = "gpio";
24 };
25 pmx_USB_copy_button: pmx-USB-copy-button {
26 marvell,pins = "mpp43";
27 marvell,function = "gpio";
28 };
29 pmx_board_id: pmx-board-id {
30 /* 0: TS-11x, 1: TS-21x */
31 marvell,pins = "mpp44";
32 marvell,function = "gpio";
33 };
34 };
35 };
36
37 gpio_keys {
38 compatible = "gpio-keys";
39 #address-cells = <1>;
40 #size-cells = <0>;
41 button@1 {
42 label = "USB Copy";
43 linux,code = <133>;
44 gpios = <&gpio1 11 1>;
45 };
46 button@2 {
47 label = "Reset";
48 linux,code = <0x198>;
49 gpios = <&gpio1 5 1>;
50 };
51 };
52}; \ No newline at end of file
diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/kirkwood-ts219.dtsi
deleted file mode 100644
index 64ea27cb329..00000000000
--- a/arch/arm/boot/dts/kirkwood-ts219.dtsi
+++ /dev/null
@@ -1,78 +0,0 @@
1/include/ "kirkwood.dtsi"
2
3/ {
4 model = "QNAP TS219 family";
5 compatible = "qnap,ts219", "marvell,kirkwood";
6
7 memory {
8 device_type = "memory";
9 reg = <0x00000000 0x20000000>;
10 };
11
12 chosen {
13 bootargs = "console=ttyS0,115200n8";
14 };
15
16 ocp@f1000000 {
17 i2c@11000 {
18 status = "okay";
19 clock-frequency = <400000>;
20
21 s35390a: s35390a@30 {
22 compatible = "s35390a";
23 reg = <0x30>;
24 };
25 };
26 serial@12000 {
27 clock-frequency = <200000000>;
28 status = "okay";
29 };
30 serial@12100 {
31 clock-frequency = <200000000>;
32 status = "okay";
33 };
34 spi@10600 {
35 status = "okay";
36
37 m25p128@0 {
38 #address-cells = <1>;
39 #size-cells = <1>;
40 compatible = "m25p128";
41 reg = <0>;
42 spi-max-frequency = <20000000>;
43 mode = <0>;
44
45 partition@0000000 {
46 reg = <0x00000000 0x00080000>;
47 label = "U-Boot";
48 };
49
50 partition@00200000 {
51 reg = <0x00200000 0x00200000>;
52 label = "Kernel";
53 };
54
55 partition@00400000 {
56 reg = <0x00400000 0x00900000>;
57 label = "RootFS1";
58 };
59 partition@00d00000 {
60 reg = <0x00d00000 0x00300000>;
61 label = "RootFS2";
62 };
63 partition@00040000 {
64 reg = <0x00080000 0x00040000>;
65 label = "U-Boot Config";
66 };
67 partition@000c0000 {
68 reg = <0x000c0000 0x00140000>;
69 label = "NAS Config";
70 };
71 };
72 };
73 sata@80000 {
74 status = "okay";
75 nr-ports = <2>;
76 };
77 };
78};
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
deleted file mode 100644
index 110d6cbb795..00000000000
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ /dev/null
@@ -1,195 +0,0 @@
1/include/ "skeleton.dtsi"
2
3/ {
4 compatible = "marvell,kirkwood";
5 interrupt-parent = <&intc>;
6
7 aliases {
8 gpio0 = &gpio0;
9 gpio1 = &gpio1;
10 };
11 intc: interrupt-controller {
12 compatible = "marvell,orion-intc", "marvell,intc";
13 interrupt-controller;
14 #interrupt-cells = <1>;
15 reg = <0xf1020204 0x04>,
16 <0xf1020214 0x04>;
17 };
18
19 ocp@f1000000 {
20 compatible = "simple-bus";
21 ranges = <0x00000000 0xf1000000 0x4000000
22 0xf5000000 0xf5000000 0x0000400>;
23 #address-cells = <1>;
24 #size-cells = <1>;
25
26 core_clk: core-clocks@10030 {
27 compatible = "marvell,kirkwood-core-clock";
28 reg = <0x10030 0x4>;
29 #clock-cells = <1>;
30 };
31
32 gpio0: gpio@10100 {
33 compatible = "marvell,orion-gpio";
34 #gpio-cells = <2>;
35 gpio-controller;
36 reg = <0x10100 0x40>;
37 ngpios = <32>;
38 interrupt-controller;
39 interrupts = <35>, <36>, <37>, <38>;
40 };
41
42 gpio1: gpio@10140 {
43 compatible = "marvell,orion-gpio";
44 #gpio-cells = <2>;
45 gpio-controller;
46 reg = <0x10140 0x40>;
47 ngpios = <18>;
48 interrupt-controller;
49 interrupts = <39>, <40>, <41>;
50 };
51
52 serial@12000 {
53 compatible = "ns16550a";
54 reg = <0x12000 0x100>;
55 reg-shift = <2>;
56 interrupts = <33>;
57 clocks = <&gate_clk 7>;
58 /* set clock-frequency in board dts */
59 status = "disabled";
60 };
61
62 serial@12100 {
63 compatible = "ns16550a";
64 reg = <0x12100 0x100>;
65 reg-shift = <2>;
66 interrupts = <34>;
67 clocks = <&gate_clk 7>;
68 /* set clock-frequency in board dts */
69 status = "disabled";
70 };
71
72 rtc@10300 {
73 compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
74 reg = <0x10300 0x20>;
75 interrupts = <53>;
76 };
77
78 spi@10600 {
79 compatible = "marvell,orion-spi";
80 #address-cells = <1>;
81 #size-cells = <0>;
82 cell-index = <0>;
83 interrupts = <23>;
84 reg = <0x10600 0x28>;
85 clocks = <&gate_clk 7>;
86 status = "disabled";
87 };
88
89 gate_clk: clock-gating-control@2011c {
90 compatible = "marvell,kirkwood-gating-clock";
91 reg = <0x2011c 0x4>;
92 clocks = <&core_clk 0>;
93 #clock-cells = <1>;
94 };
95
96 wdt@20300 {
97 compatible = "marvell,orion-wdt";
98 reg = <0x20300 0x28>;
99 clocks = <&gate_clk 7>;
100 status = "okay";
101 };
102
103 xor@60800 {
104 compatible = "marvell,orion-xor";
105 reg = <0x60800 0x100
106 0x60A00 0x100>;
107 status = "okay";
108 clocks = <&gate_clk 8>;
109
110 xor00 {
111 interrupts = <5>;
112 dmacap,memcpy;
113 dmacap,xor;
114 };
115 xor01 {
116 interrupts = <6>;
117 dmacap,memcpy;
118 dmacap,xor;
119 dmacap,memset;
120 };
121 };
122
123 xor@60900 {
124 compatible = "marvell,orion-xor";
125 reg = <0x60900 0x100
126 0xd0B00 0x100>;
127 status = "okay";
128 clocks = <&gate_clk 16>;
129
130 xor00 {
131 interrupts = <7>;
132 dmacap,memcpy;
133 dmacap,xor;
134 };
135 xor01 {
136 interrupts = <8>;
137 dmacap,memcpy;
138 dmacap,xor;
139 dmacap,memset;
140 };
141 };
142
143 ehci@50000 {
144 compatible = "marvell,orion-ehci";
145 reg = <0x50000 0x1000>;
146 interrupts = <19>;
147 clocks = <&gate_clk 3>;
148 status = "okay";
149 };
150
151 sata@80000 {
152 compatible = "marvell,orion-sata";
153 reg = <0x80000 0x5000>;
154 interrupts = <21>;
155 clocks = <&gate_clk 14>, <&gate_clk 15>;
156 clock-names = "0", "1";
157 status = "disabled";
158 };
159
160 nand@3000000 {
161 #address-cells = <1>;
162 #size-cells = <1>;
163 cle = <0>;
164 ale = <1>;
165 bank-width = <1>;
166 compatible = "marvell,orion-nand";
167 reg = <0x3000000 0x400>;
168 chip-delay = <25>;
169 /* set partition map and/or chip-delay in board dts */
170 clocks = <&gate_clk 7>;
171 status = "disabled";
172 };
173
174 i2c@11000 {
175 compatible = "marvell,mv64xxx-i2c";
176 reg = <0x11000 0x20>;
177 #address-cells = <1>;
178 #size-cells = <0>;
179 interrupts = <29>;
180 clock-frequency = <100000>;
181 clocks = <&gate_clk 7>;
182 status = "disabled";
183 };
184
185 crypto@30000 {
186 compatible = "marvell,orion-crypto";
187 reg = <0x30000 0x10000>,
188 <0xf5000000 0x800>;
189 reg-names = "regs", "sram";
190 interrupts = <22>;
191 clocks = <&gate_clk 17>;
192 status = "okay";
193 };
194 };
195};
diff --git a/arch/arm/boot/dts/kizbox.dts b/arch/arm/boot/dts/kizbox.dts
deleted file mode 100644
index e8814fe0e27..00000000000
--- a/arch/arm/boot/dts/kizbox.dts
+++ /dev/null
@@ -1,138 +0,0 @@
1/*
2 * kizbox.dts - Device Tree file for Overkiz Kizbox board
3 *
4 * Copyright (C) 2012 Boris BREZILLON <linux-arm@overkiz.com>
5 *
6 * Licensed under GPLv2.
7 */
8/dts-v1/;
9/include/ "at91sam9g20.dtsi"
10
11/ {
12
13 model = "Overkiz kizbox";
14 compatible = "overkiz,kizbox", "atmel,at91sam9g20", "atmel,at91sam9";
15
16 chosen {
17 bootargs = "panic=5 ubi.mtd=1 rootfstype=ubifs root=ubi0:root";
18 };
19
20 memory {
21 reg = <0x20000000 0x2000000>;
22 };
23
24 clocks {
25 #address-cells = <1>;
26 #size-cells = <1>;
27 ranges;
28
29 main_clock: clock@0 {
30 compatible = "atmel,osc", "fixed-clock";
31 clock-frequency = <18432000>;
32 };
33 };
34
35 ahb {
36 apb {
37 dbgu: serial@fffff200 {
38 status = "okay";
39 };
40
41 usart0: serial@fffb0000 {
42 status = "okay";
43 };
44
45 usart1: serial@fffb4000 {
46 status = "okay";
47 };
48
49 macb0: ethernet@fffc4000 {
50 phy-mode = "mii";
51 status = "okay";
52 };
53
54 };
55
56 nand0: nand@40000000 {
57 nand-bus-width = <8>;
58 nand-ecc-mode = "soft";
59 status = "okay";
60
61 bootloaderkernel@0 {
62 label = "bootloader-kernel";
63 reg = <0x0 0xc0000>;
64 };
65
66 ubi@c0000 {
67 label = "ubi";
68 reg = <0xc0000 0x7f40000>;
69 };
70
71 };
72
73 usb0: ohci@00500000 {
74 num-ports = <1>;
75 status = "okay";
76 };
77 };
78
79 i2c@0 {
80 status = "okay";
81
82 pcf8563@51 {
83 /* nxp pcf8563 rtc */
84 compatible = "nxp,pcf8563";
85 reg = <0x51>;
86 };
87
88 };
89
90 leds {
91 compatible = "gpio-leds";
92
93 led1g {
94 label = "led1:green";
95 gpios = <&pioB 0 1>;
96 linux,default-trigger = "none";
97 };
98
99 led1r {
100 label = "led1:red";
101 gpios = <&pioB 1 1>;
102 linux,default-trigger = "none";
103 };
104
105 led2g {
106 label = "led2:green";
107 gpios = <&pioB 2 1>;
108 linux,default-trigger = "none";
109 default-state = "on";
110 };
111
112 led2r {
113 label = "led2:red";
114 gpios = <&pioB 3 1>;
115 linux,default-trigger = "none";
116 };
117 };
118
119 gpio_keys {
120 compatible = "gpio-keys";
121 #address-cells = <1>;
122 #size-cells = <0>;
123
124 reset {
125 label = "reset";
126 gpios = <&pioB 30 1>;
127 linux,code = <0x100>;
128 gpio-key,wakeup;
129 };
130
131 mode {
132 label = "mode";
133 gpios = <&pioB 31 1>;
134 linux,code = <0x101>;
135 gpio-key,wakeup;
136 };
137 };
138}; \ No newline at end of file
diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
deleted file mode 100644
index 1582f484a86..00000000000
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ /dev/null
@@ -1,295 +0,0 @@
1/*
2 * NXP LPC32xx SoC
3 *
4 * Copyright 2012 Roland Stigge <stigge@antcom.de>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "skeleton.dtsi"
15
16/ {
17 compatible = "nxp,lpc3220";
18 interrupt-parent = <&mic>;
19
20 cpus {
21 cpu@0 {
22 compatible = "arm,arm926ejs";
23 };
24 };
25
26 ahb {
27 #address-cells = <1>;
28 #size-cells = <1>;
29 compatible = "simple-bus";
30 ranges = <0x20000000 0x20000000 0x30000000>;
31
32 /*
33 * Enable either SLC or MLC
34 */
35 slc: flash@20020000 {
36 compatible = "nxp,lpc3220-slc";
37 reg = <0x20020000 0x1000>;
38 status = "disabled";
39 };
40
41 mlc: flash@200a8000 {
42 compatible = "nxp,lpc3220-mlc";
43 reg = <0x200a8000 0x11000>;
44 interrupts = <11 0>;
45 status = "disabled";
46 };
47
48 dma@31000000 {
49 compatible = "arm,pl080", "arm,primecell";
50 reg = <0x31000000 0x1000>;
51 interrupts = <0x1c 0>;
52 };
53
54 /*
55 * Enable either ohci or usbd (gadget)!
56 */
57 ohci@31020000 {
58 compatible = "nxp,ohci-nxp", "usb-ohci";
59 reg = <0x31020000 0x300>;
60 interrupts = <0x3b 0>;
61 status = "disabled";
62 };
63
64 usbd@31020000 {
65 compatible = "nxp,lpc3220-udc";
66 reg = <0x31020000 0x300>;
67 interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>;
68 status = "disabled";
69 };
70
71 clcd@31040000 {
72 compatible = "arm,pl110", "arm,primecell";
73 reg = <0x31040000 0x1000>;
74 interrupts = <0x0e 0>;
75 status = "disabled";
76 };
77
78 mac: ethernet@31060000 {
79 compatible = "nxp,lpc-eth";
80 reg = <0x31060000 0x1000>;
81 interrupts = <0x1d 0>;
82 };
83
84 apb {
85 #address-cells = <1>;
86 #size-cells = <1>;
87 compatible = "simple-bus";
88 ranges = <0x20000000 0x20000000 0x30000000>;
89
90 ssp0: ssp@20084000 {
91 compatible = "arm,pl022", "arm,primecell";
92 reg = <0x20084000 0x1000>;
93 interrupts = <0x14 0>;
94 };
95
96 spi1: spi@20088000 {
97 compatible = "nxp,lpc3220-spi";
98 reg = <0x20088000 0x1000>;
99 };
100
101 ssp1: ssp@2008c000 {
102 compatible = "arm,pl022", "arm,primecell";
103 reg = <0x2008c000 0x1000>;
104 interrupts = <0x15 0>;
105 };
106
107 spi2: spi@20090000 {
108 compatible = "nxp,lpc3220-spi";
109 reg = <0x20090000 0x1000>;
110 };
111
112 i2s0: i2s@20094000 {
113 compatible = "nxp,lpc3220-i2s";
114 reg = <0x20094000 0x1000>;
115 };
116
117 sd@20098000 {
118 compatible = "arm,pl18x", "arm,primecell";
119 reg = <0x20098000 0x1000>;
120 interrupts = <0x0f 0>, <0x0d 0>;
121 status = "disabled";
122 };
123
124 i2s1: i2s@2009C000 {
125 compatible = "nxp,lpc3220-i2s";
126 reg = <0x2009C000 0x1000>;
127 };
128
129 /* UART5 first since it is the default console, ttyS0 */
130 uart5: serial@40090000 {
131 /* actually, ns16550a w/ 64 byte fifos! */
132 compatible = "nxp,lpc3220-uart";
133 reg = <0x40090000 0x1000>;
134 interrupts = <9 0>;
135 clock-frequency = <13000000>;
136 reg-shift = <2>;
137 status = "disabled";
138 };
139
140 uart3: serial@40080000 {
141 compatible = "nxp,lpc3220-uart";
142 reg = <0x40080000 0x1000>;
143 interrupts = <7 0>;
144 clock-frequency = <13000000>;
145 reg-shift = <2>;
146 status = "disabled";
147 };
148
149 uart4: serial@40088000 {
150 compatible = "nxp,lpc3220-uart";
151 reg = <0x40088000 0x1000>;
152 interrupts = <8 0>;
153 clock-frequency = <13000000>;
154 reg-shift = <2>;
155 status = "disabled";
156 };
157
158 uart6: serial@40098000 {
159 compatible = "nxp,lpc3220-uart";
160 reg = <0x40098000 0x1000>;
161 interrupts = <10 0>;
162 clock-frequency = <13000000>;
163 reg-shift = <2>;
164 status = "disabled";
165 };
166
167 i2c1: i2c@400A0000 {
168 compatible = "nxp,pnx-i2c";
169 reg = <0x400A0000 0x100>;
170 interrupts = <0x33 0>;
171 #address-cells = <1>;
172 #size-cells = <0>;
173 pnx,timeout = <0x64>;
174 };
175
176 i2c2: i2c@400A8000 {
177 compatible = "nxp,pnx-i2c";
178 reg = <0x400A8000 0x100>;
179 interrupts = <0x32 0>;
180 #address-cells = <1>;
181 #size-cells = <0>;
182 pnx,timeout = <0x64>;
183 };
184
185 mpwm: mpwm@400E8000 {
186 compatible = "nxp,lpc3220-motor-pwm";
187 reg = <0x400E8000 0x78>;
188 status = "disabled";
189 #pwm-cells = <2>;
190 };
191
192 i2cusb: i2c@31020300 {
193 compatible = "nxp,pnx-i2c";
194 reg = <0x31020300 0x100>;
195 interrupts = <0x3f 0>;
196 #address-cells = <1>;
197 #size-cells = <0>;
198 pnx,timeout = <0x64>;
199 };
200 };
201
202 fab {
203 #address-cells = <1>;
204 #size-cells = <1>;
205 compatible = "simple-bus";
206 ranges = <0x20000000 0x20000000 0x30000000>;
207
208 /*
209 * MIC Interrupt controller includes:
210 * MIC @40008000
211 * SIC1 @4000C000
212 * SIC2 @40010000
213 */
214 mic: interrupt-controller@40008000 {
215 compatible = "nxp,lpc3220-mic";
216 interrupt-controller;
217 reg = <0x40008000 0xC000>;
218 #interrupt-cells = <2>;
219 };
220
221 uart1: serial@40014000 {
222 compatible = "nxp,lpc3220-hsuart";
223 reg = <0x40014000 0x1000>;
224 interrupts = <26 0>;
225 status = "disabled";
226 };
227
228 uart2: serial@40018000 {
229 compatible = "nxp,lpc3220-hsuart";
230 reg = <0x40018000 0x1000>;
231 interrupts = <25 0>;
232 status = "disabled";
233 };
234
235 uart7: serial@4001c000 {
236 compatible = "nxp,lpc3220-hsuart";
237 reg = <0x4001c000 0x1000>;
238 interrupts = <24 0>;
239 status = "disabled";
240 };
241
242 rtc@40024000 {
243 compatible = "nxp,lpc3220-rtc";
244 reg = <0x40024000 0x1000>;
245 interrupts = <0x34 0>;
246 };
247
248 gpio: gpio@40028000 {
249 compatible = "nxp,lpc3220-gpio";
250 reg = <0x40028000 0x1000>;
251 gpio-controller;
252 #gpio-cells = <3>; /* bank, pin, flags */
253 };
254
255 watchdog@4003C000 {
256 compatible = "nxp,pnx4008-wdt";
257 reg = <0x4003C000 0x1000>;
258 };
259
260 /*
261 * TSC vs. ADC: Since those two share the same
262 * hardware, you need to choose from one of the
263 * following two and do 'status = "okay";' for one of
264 * them
265 */
266
267 adc@40048000 {
268 compatible = "nxp,lpc3220-adc";
269 reg = <0x40048000 0x1000>;
270 interrupts = <0x27 0>;
271 status = "disabled";
272 };
273
274 tsc@40048000 {
275 compatible = "nxp,lpc3220-tsc";
276 reg = <0x40048000 0x1000>;
277 interrupts = <0x27 0>;
278 status = "disabled";
279 };
280
281 key@40050000 {
282 compatible = "nxp,lpc3220-key";
283 reg = <0x40050000 0x1000>;
284 interrupts = <54 0>;
285 status = "disabled";
286 };
287
288 pwm: pwm@4005C000 {
289 compatible = "nxp,lpc3220-pwm";
290 reg = <0x4005C000 0x8>;
291 status = "disabled";
292 };
293 };
294 };
295};
diff --git a/arch/arm/boot/dts/mmp2-brownstone.dts b/arch/arm/boot/dts/mmp2-brownstone.dts
deleted file mode 100644
index c9b4f27d191..00000000000
--- a/arch/arm/boot/dts/mmp2-brownstone.dts
+++ /dev/null
@@ -1,38 +0,0 @@
1/*
2 * Copyright (C) 2012 Marvell Technology Group Ltd.
3 * Author: Haojian Zhuang <haojian.zhuang@marvell.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9
10/dts-v1/;
11/include/ "mmp2.dtsi"
12
13/ {
14 model = "Marvell MMP2 Brownstone Development Board";
15 compatible = "mrvl,mmp2-brownstone", "mrvl,mmp2";
16
17 chosen {
18 bootargs = "console=ttyS2,38400 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on";
19 };
20
21 memory {
22 reg = <0x00000000 0x08000000>;
23 };
24
25 soc {
26 apb@d4000000 {
27 uart3: uart@d4018000 {
28 status = "okay";
29 };
30 twsi1: i2c@d4011000 {
31 status = "okay";
32 };
33 rtc: rtc@d4010000 {
34 status = "okay";
35 };
36 };
37 };
38};
diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi
deleted file mode 100644
index 0514fb41627..00000000000
--- a/arch/arm/boot/dts/mmp2.dtsi
+++ /dev/null
@@ -1,225 +0,0 @@
1/*
2 * Copyright (C) 2012 Marvell Technology Group Ltd.
3 * Author: Haojian Zhuang <haojian.zhuang@marvell.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9
10/include/ "skeleton.dtsi"
11
12/ {
13 aliases {
14 serial0 = &uart1;
15 serial1 = &uart2;
16 serial2 = &uart3;
17 serial3 = &uart4;
18 i2c0 = &twsi1;
19 i2c1 = &twsi2;
20 };
21
22 soc {
23 #address-cells = <1>;
24 #size-cells = <1>;
25 compatible = "simple-bus";
26 interrupt-parent = <&intc>;
27 ranges;
28
29 L2: l2-cache {
30 compatible = "marvell,tauros2-cache";
31 marvell,tauros2-cache-features = <0x3>;
32 };
33
34 axi@d4200000 { /* AXI */
35 compatible = "mrvl,axi-bus", "simple-bus";
36 #address-cells = <1>;
37 #size-cells = <1>;
38 reg = <0xd4200000 0x00200000>;
39 ranges;
40
41 intc: interrupt-controller@d4282000 {
42 compatible = "mrvl,mmp2-intc";
43 interrupt-controller;
44 #interrupt-cells = <1>;
45 reg = <0xd4282000 0x1000>;
46 mrvl,intc-nr-irqs = <64>;
47 };
48
49 intcmux4@d4282150 {
50 compatible = "mrvl,mmp2-mux-intc";
51 interrupts = <4>;
52 interrupt-controller;
53 #interrupt-cells = <1>;
54 reg = <0x150 0x4>, <0x168 0x4>;
55 reg-names = "mux status", "mux mask";
56 mrvl,intc-nr-irqs = <2>;
57 };
58
59 intcmux5: interrupt-controller@d4282154 {
60 compatible = "mrvl,mmp2-mux-intc";
61 interrupts = <5>;
62 interrupt-controller;
63 #interrupt-cells = <1>;
64 reg = <0x154 0x4>, <0x16c 0x4>;
65 reg-names = "mux status", "mux mask";
66 mrvl,intc-nr-irqs = <2>;
67 mrvl,clr-mfp-irq = <1>;
68 };
69
70 intcmux9: interrupt-controller@d4282180 {
71 compatible = "mrvl,mmp2-mux-intc";
72 interrupts = <9>;
73 interrupt-controller;
74 #interrupt-cells = <1>;
75 reg = <0x180 0x4>, <0x17c 0x4>;
76 reg-names = "mux status", "mux mask";
77 mrvl,intc-nr-irqs = <3>;
78 };
79
80 intcmux17: interrupt-controller@d4282158 {
81 compatible = "mrvl,mmp2-mux-intc";
82 interrupts = <17>;
83 interrupt-controller;
84 #interrupt-cells = <1>;
85 reg = <0x158 0x4>, <0x170 0x4>;
86 reg-names = "mux status", "mux mask";
87 mrvl,intc-nr-irqs = <5>;
88 };
89
90 intcmux35: interrupt-controller@d428215c {
91 compatible = "mrvl,mmp2-mux-intc";
92 interrupts = <35>;
93 interrupt-controller;
94 #interrupt-cells = <1>;
95 reg = <0x15c 0x4>, <0x174 0x4>;
96 reg-names = "mux status", "mux mask";
97 mrvl,intc-nr-irqs = <15>;
98 };
99
100 intcmux51: interrupt-controller@d4282160 {
101 compatible = "mrvl,mmp2-mux-intc";
102 interrupts = <51>;
103 interrupt-controller;
104 #interrupt-cells = <1>;
105 reg = <0x160 0x4>, <0x178 0x4>;
106 reg-names = "mux status", "mux mask";
107 mrvl,intc-nr-irqs = <2>;
108 };
109
110 intcmux55: interrupt-controller@d4282188 {
111 compatible = "mrvl,mmp2-mux-intc";
112 interrupts = <55>;
113 interrupt-controller;
114 #interrupt-cells = <1>;
115 reg = <0x188 0x4>, <0x184 0x4>;
116 reg-names = "mux status", "mux mask";
117 mrvl,intc-nr-irqs = <2>;
118 };
119 };
120
121 apb@d4000000 { /* APB */
122 compatible = "mrvl,apb-bus", "simple-bus";
123 #address-cells = <1>;
124 #size-cells = <1>;
125 reg = <0xd4000000 0x00200000>;
126 ranges;
127
128 timer0: timer@d4014000 {
129 compatible = "mrvl,mmp-timer";
130 reg = <0xd4014000 0x100>;
131 interrupts = <13>;
132 };
133
134 uart1: uart@d4030000 {
135 compatible = "mrvl,mmp-uart";
136 reg = <0xd4030000 0x1000>;
137 interrupts = <27>;
138 status = "disabled";
139 };
140
141 uart2: uart@d4017000 {
142 compatible = "mrvl,mmp-uart";
143 reg = <0xd4017000 0x1000>;
144 interrupts = <28>;
145 status = "disabled";
146 };
147
148 uart3: uart@d4018000 {
149 compatible = "mrvl,mmp-uart";
150 reg = <0xd4018000 0x1000>;
151 interrupts = <24>;
152 status = "disabled";
153 };
154
155 uart4: uart@d4016000 {
156 compatible = "mrvl,mmp-uart";
157 reg = <0xd4016000 0x1000>;
158 interrupts = <46>;
159 status = "disabled";
160 };
161
162 gpio@d4019000 {
163 compatible = "mrvl,mmp-gpio";
164 #address-cells = <1>;
165 #size-cells = <1>;
166 reg = <0xd4019000 0x1000>;
167 gpio-controller;
168 #gpio-cells = <2>;
169 interrupts = <49>;
170 interrupt-names = "gpio_mux";
171 interrupt-controller;
172 #interrupt-cells = <1>;
173 ranges;
174
175 gcb0: gpio@d4019000 {
176 reg = <0xd4019000 0x4>;
177 };
178
179 gcb1: gpio@d4019004 {
180 reg = <0xd4019004 0x4>;
181 };
182
183 gcb2: gpio@d4019008 {
184 reg = <0xd4019008 0x4>;
185 };
186
187 gcb3: gpio@d4019100 {
188 reg = <0xd4019100 0x4>;
189 };
190
191 gcb4: gpio@d4019104 {
192 reg = <0xd4019104 0x4>;
193 };
194
195 gcb5: gpio@d4019108 {
196 reg = <0xd4019108 0x4>;
197 };
198 };
199
200 twsi1: i2c@d4011000 {
201 compatible = "mrvl,mmp-twsi";
202 reg = <0xd4011000 0x1000>;
203 interrupts = <7>;
204 mrvl,i2c-fast-mode;
205 status = "disabled";
206 };
207
208 twsi2: i2c@d4025000 {
209 compatible = "mrvl,mmp-twsi";
210 reg = <0xd4025000 0x1000>;
211 interrupts = <58>;
212 status = "disabled";
213 };
214
215 rtc: rtc@d4010000 {
216 compatible = "mrvl,mmp-rtc";
217 reg = <0xd4010000 0x1000>;
218 interrupts = <1 0>;
219 interrupt-names = "rtc 1Hz", "rtc alarm";
220 interrupt-parent = <&intcmux5>;
221 status = "disabled";
222 };
223 };
224 };
225};
diff --git a/arch/arm/boot/dts/msm8660-surf.dts b/arch/arm/boot/dts/msm8660-surf.dts
deleted file mode 100644
index 31f2157cd7d..00000000000
--- a/arch/arm/boot/dts/msm8660-surf.dts
+++ /dev/null
@@ -1,41 +0,0 @@
1/dts-v1/;
2
3/include/ "skeleton.dtsi"
4
5/ {
6 model = "Qualcomm MSM8660 SURF";
7 compatible = "qcom,msm8660-surf", "qcom,msm8660";
8 interrupt-parent = <&intc>;
9
10 intc: interrupt-controller@2080000 {
11 compatible = "qcom,msm-8660-qgic";
12 interrupt-controller;
13 #interrupt-cells = <3>;
14 reg = < 0x02080000 0x1000 >,
15 < 0x02081000 0x1000 >;
16 };
17
18 timer@2000004 {
19 compatible = "qcom,msm-gpt", "qcom,msm-timer";
20 interrupts = <1 1 0x301>;
21 reg = <0x02000004 0x10>;
22 clock-frequency = <32768>;
23 cpu-offset = <0x40000>;
24 };
25
26 timer@2000024 {
27 compatible = "qcom,msm-dgt", "qcom,msm-timer";
28 interrupts = <1 0 0x301>;
29 reg = <0x02000024 0x10>,
30 <0x02000034 0x4>;
31 clock-frequency = <6750000>;
32 cpu-offset = <0x40000>;
33 };
34
35 serial@19c400000 {
36 compatible = "qcom,msm-hsuart", "qcom,msm-uart";
37 reg = <0x19c40000 0x1000>,
38 <0x19c00000 0x1000>;
39 interrupts = <0 195 0x0>;
40 };
41};
diff --git a/arch/arm/boot/dts/msm8960-cdp.dts b/arch/arm/boot/dts/msm8960-cdp.dts
deleted file mode 100644
index 9e621b5ad3d..00000000000
--- a/arch/arm/boot/dts/msm8960-cdp.dts
+++ /dev/null
@@ -1,41 +0,0 @@
1/dts-v1/;
2
3/include/ "skeleton.dtsi"
4
5/ {
6 model = "Qualcomm MSM8960 CDP";
7 compatible = "qcom,msm8960-cdp", "qcom,msm8960";
8 interrupt-parent = <&intc>;
9
10 intc: interrupt-controller@2000000 {
11 compatible = "qcom,msm-qgic2";
12 interrupt-controller;
13 #interrupt-cells = <3>;
14 reg = < 0x02000000 0x1000 >,
15 < 0x02002000 0x1000 >;
16 };
17
18 timer@200a004 {
19 compatible = "qcom,msm-gpt", "qcom,msm-timer";
20 interrupts = <1 2 0x301>;
21 reg = <0x0200a004 0x10>;
22 clock-frequency = <32768>;
23 cpu-offset = <0x80000>;
24 };
25
26 timer@200a024 {
27 compatible = "qcom,msm-dgt", "qcom,msm-timer";
28 interrupts = <1 1 0x301>;
29 reg = <0x0200a024 0x10>,
30 <0x0200a034 0x4>;
31 clock-frequency = <6750000>;
32 cpu-offset = <0x80000>;
33 };
34
35 serial@19c400000 {
36 compatible = "qcom,msm-hsuart", "qcom,msm-uart";
37 reg = <0x16440000 0x1000>,
38 <0x16400000 0x1000>;
39 interrupts = <0 154 0x0>;
40 };
41};
diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
deleted file mode 100644
index 761c4b69b25..00000000000
--- a/arch/arm/boot/dts/omap2.dtsi
+++ /dev/null
@@ -1,155 +0,0 @@
1/*
2 * Device Tree Source for OMAP2 SoC
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "skeleton.dtsi"
12
13/ {
14 compatible = "ti,omap2430", "ti,omap2420", "ti,omap2";
15 interrupt-parent = <&intc>;
16
17 aliases {
18 serial0 = &uart1;
19 serial1 = &uart2;
20 serial2 = &uart3;
21 };
22
23 cpus {
24 cpu@0 {
25 compatible = "arm,arm1136jf-s";
26 };
27 };
28
29 soc {
30 compatible = "ti,omap-infra";
31 mpu {
32 compatible = "ti,omap2-mpu";
33 ti,hwmods = "mpu";
34 };
35 };
36
37 ocp {
38 compatible = "simple-bus";
39 #address-cells = <1>;
40 #size-cells = <1>;
41 ranges;
42 ti,hwmods = "l3_main";
43
44 intc: interrupt-controller@1 {
45 compatible = "ti,omap2-intc";
46 interrupt-controller;
47 #interrupt-cells = <1>;
48 ti,intc-size = <96>;
49 reg = <0x480FE000 0x1000>;
50 };
51
52 uart1: serial@4806a000 {
53 compatible = "ti,omap2-uart";
54 ti,hwmods = "uart1";
55 clock-frequency = <48000000>;
56 };
57
58 uart2: serial@4806c000 {
59 compatible = "ti,omap2-uart";
60 ti,hwmods = "uart2";
61 clock-frequency = <48000000>;
62 };
63
64 uart3: serial@4806e000 {
65 compatible = "ti,omap2-uart";
66 ti,hwmods = "uart3";
67 clock-frequency = <48000000>;
68 };
69
70 timer2: timer@4802a000 {
71 compatible = "ti,omap2-timer";
72 reg = <0x4802a000 0x400>;
73 interrupts = <38>;
74 ti,hwmods = "timer2";
75 };
76
77 timer3: timer@48078000 {
78 compatible = "ti,omap2-timer";
79 reg = <0x48078000 0x400>;
80 interrupts = <39>;
81 ti,hwmods = "timer3";
82 };
83
84 timer4: timer@4807a000 {
85 compatible = "ti,omap2-timer";
86 reg = <0x4807a000 0x400>;
87 interrupts = <40>;
88 ti,hwmods = "timer4";
89 };
90
91 timer5: timer@4807c000 {
92 compatible = "ti,omap2-timer";
93 reg = <0x4807c000 0x400>;
94 interrupts = <41>;
95 ti,hwmods = "timer5";
96 ti,timer-dsp;
97 };
98
99 timer6: timer@4807e000 {
100 compatible = "ti,omap2-timer";
101 reg = <0x4807e000 0x400>;
102 interrupts = <42>;
103 ti,hwmods = "timer6";
104 ti,timer-dsp;
105 };
106
107 timer7: timer@48080000 {
108 compatible = "ti,omap2-timer";
109 reg = <0x48080000 0x400>;
110 interrupts = <43>;
111 ti,hwmods = "timer7";
112 ti,timer-dsp;
113 };
114
115 timer8: timer@48082000 {
116 compatible = "ti,omap2-timer";
117 reg = <0x48082000 0x400>;
118 interrupts = <44>;
119 ti,hwmods = "timer8";
120 ti,timer-dsp;
121 };
122
123 timer9: timer@48084000 {
124 compatible = "ti,omap2-timer";
125 reg = <0x48084000 0x400>;
126 interrupts = <45>;
127 ti,hwmods = "timer9";
128 ti,timer-pwm;
129 };
130
131 timer10: timer@48086000 {
132 compatible = "ti,omap2-timer";
133 reg = <0x48086000 0x400>;
134 interrupts = <46>;
135 ti,hwmods = "timer10";
136 ti,timer-pwm;
137 };
138
139 timer11: timer@48088000 {
140 compatible = "ti,omap2-timer";
141 reg = <0x48088000 0x400>;
142 interrupts = <47>;
143 ti,hwmods = "timer11";
144 ti,timer-pwm;
145 };
146
147 timer12: timer@4808a000 {
148 compatible = "ti,omap2-timer";
149 reg = <0x4808a000 0x400>;
150 interrupts = <48>;
151 ti,hwmods = "timer12";
152 ti,timer-pwm;
153 };
154 };
155};
diff --git a/arch/arm/boot/dts/omap2420-h4.dts b/arch/arm/boot/dts/omap2420-h4.dts
deleted file mode 100644
index 9b0d07746cb..00000000000
--- a/arch/arm/boot/dts/omap2420-h4.dts
+++ /dev/null
@@ -1,20 +0,0 @@
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10/include/ "omap2420.dtsi"
11
12/ {
13 model = "TI OMAP2420 H4 board";
14 compatible = "ti,omap2420-h4", "ti,omap2420", "ti,omap2";
15
16 memory {
17 device_type = "memory";
18 reg = <0x80000000 0x4000000>; /* 64 MB */
19 };
20};
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
deleted file mode 100644
index af656090890..00000000000
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ /dev/null
@@ -1,60 +0,0 @@
1/*
2 * Device Tree Source for OMAP2420 SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "omap2.dtsi"
12
13/ {
14 compatible = "ti,omap2420", "ti,omap2";
15
16 ocp {
17 counter32k: counter@48004000 {
18 compatible = "ti,omap-counter32k";
19 reg = <0x48004000 0x20>;
20 ti,hwmods = "counter_32k";
21 };
22
23 omap2420_pmx: pinmux@48000030 {
24 compatible = "ti,omap2420-padconf", "pinctrl-single";
25 reg = <0x48000030 0x0113>;
26 #address-cells = <1>;
27 #size-cells = <0>;
28 pinctrl-single,register-width = <8>;
29 pinctrl-single,function-mask = <0x3f>;
30 };
31
32 mcbsp1: mcbsp@48074000 {
33 compatible = "ti,omap2420-mcbsp";
34 reg = <0x48074000 0xff>;
35 reg-names = "mpu";
36 interrupts = <59>, /* TX interrupt */
37 <60>; /* RX interrupt */
38 interrupt-names = "tx", "rx";
39 ti,hwmods = "mcbsp1";
40 };
41
42 mcbsp2: mcbsp@48076000 {
43 compatible = "ti,omap2420-mcbsp";
44 reg = <0x48076000 0xff>;
45 reg-names = "mpu";
46 interrupts = <62>, /* TX interrupt */
47 <63>; /* RX interrupt */
48 interrupt-names = "tx", "rx";
49 ti,hwmods = "mcbsp2";
50 };
51
52 timer1: timer@48028000 {
53 compatible = "ti,omap2-timer";
54 reg = <0x48028000 0x400>;
55 interrupts = <37>;
56 ti,hwmods = "timer1";
57 ti,timer-alwon;
58 };
59 };
60};
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
deleted file mode 100644
index c3924457c9b..00000000000
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ /dev/null
@@ -1,101 +0,0 @@
1/*
2 * Device Tree Source for OMAP243x SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "omap2.dtsi"
12
13/ {
14 compatible = "ti,omap2430", "ti,omap2";
15
16 ocp {
17 counter32k: counter@49020000 {
18 compatible = "ti,omap-counter32k";
19 reg = <0x49020000 0x20>;
20 ti,hwmods = "counter_32k";
21 };
22
23 omap2430_pmx: pinmux@49002030 {
24 compatible = "ti,omap2430-padconf", "pinctrl-single";
25 reg = <0x49002030 0x0154>;
26 #address-cells = <1>;
27 #size-cells = <0>;
28 pinctrl-single,register-width = <8>;
29 pinctrl-single,function-mask = <0x3f>;
30 };
31
32 mcbsp1: mcbsp@48074000 {
33 compatible = "ti,omap2430-mcbsp";
34 reg = <0x48074000 0xff>;
35 reg-names = "mpu";
36 interrupts = <64>, /* OCP compliant interrupt */
37 <59>, /* TX interrupt */
38 <60>, /* RX interrupt */
39 <61>; /* RX overflow interrupt */
40 interrupt-names = "common", "tx", "rx", "rx_overflow";
41 ti,buffer-size = <128>;
42 ti,hwmods = "mcbsp1";
43 };
44
45 mcbsp2: mcbsp@48076000 {
46 compatible = "ti,omap2430-mcbsp";
47 reg = <0x48076000 0xff>;
48 reg-names = "mpu";
49 interrupts = <16>, /* OCP compliant interrupt */
50 <62>, /* TX interrupt */
51 <63>; /* RX interrupt */
52 interrupt-names = "common", "tx", "rx";
53 ti,buffer-size = <128>;
54 ti,hwmods = "mcbsp2";
55 };
56
57 mcbsp3: mcbsp@4808c000 {
58 compatible = "ti,omap2430-mcbsp";
59 reg = <0x4808c000 0xff>;
60 reg-names = "mpu";
61 interrupts = <17>, /* OCP compliant interrupt */
62 <89>, /* TX interrupt */
63 <90>; /* RX interrupt */
64 interrupt-names = "common", "tx", "rx";
65 ti,buffer-size = <128>;
66 ti,hwmods = "mcbsp3";
67 };
68
69 mcbsp4: mcbsp@4808e000 {
70 compatible = "ti,omap2430-mcbsp";
71 reg = <0x4808e000 0xff>;
72 reg-names = "mpu";
73 interrupts = <18>, /* OCP compliant interrupt */
74 <54>, /* TX interrupt */
75 <55>; /* RX interrupt */
76 interrupt-names = "common", "tx", "rx";
77 ti,buffer-size = <128>;
78 ti,hwmods = "mcbsp4";
79 };
80
81 mcbsp5: mcbsp@48096000 {
82 compatible = "ti,omap2430-mcbsp";
83 reg = <0x48096000 0xff>;
84 reg-names = "mpu";
85 interrupts = <19>, /* OCP compliant interrupt */
86 <81>, /* TX interrupt */
87 <82>; /* RX interrupt */
88 interrupt-names = "common", "tx", "rx";
89 ti,buffer-size = <128>;
90 ti,hwmods = "mcbsp5";
91 };
92
93 timer1: timer@49018000 {
94 compatible = "ti,omap2-timer";
95 reg = <0x49018000 0x400>;
96 interrupts = <37>;
97 ti,hwmods = "timer1";
98 ti,timer-alwon;
99 };
100 };
101};
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
deleted file mode 100644
index 3705a81c1fc..00000000000
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ /dev/null
@@ -1,109 +0,0 @@
1/*
2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10/include/ "omap36xx.dtsi"
11
12/ {
13 model = "TI OMAP3 BeagleBoard xM";
14 compatible = "ti,omap3-beagle-xm, ti,omap3-beagle", "ti,omap3";
15
16 memory {
17 device_type = "memory";
18 reg = <0x80000000 0x20000000>; /* 512 MB */
19 };
20
21 leds {
22 compatible = "gpio-leds";
23 pmu_stat {
24 label = "beagleboard::pmu_stat";
25 gpios = <&twl_gpio 19 0>; /* LEDB */
26 };
27
28 heartbeat {
29 label = "beagleboard::usr0";
30 gpios = <&gpio5 22 0>; /* 150 -> D6 LED */
31 linux,default-trigger = "heartbeat";
32 };
33
34 mmc {
35 label = "beagleboard::usr1";
36 gpios = <&gpio5 21 0>; /* 149 -> D7 LED */
37 linux,default-trigger = "mmc0";
38 };
39 };
40
41 sound {
42 compatible = "ti,omap-twl4030";
43 ti,model = "omap3beagle";
44
45 ti,mcbsp = <&mcbsp2>;
46 ti,codec = <&twl_audio>;
47 };
48};
49
50&i2c1 {
51 clock-frequency = <2600000>;
52
53 twl: twl@48 {
54 reg = <0x48>;
55 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
56 interrupt-parent = <&intc>;
57
58 twl_audio: audio {
59 compatible = "ti,twl4030-audio";
60 codec {
61 };
62 };
63 };
64};
65
66/include/ "twl4030.dtsi"
67
68&i2c2 {
69 clock-frequency = <400000>;
70};
71
72&i2c3 {
73 clock-frequency = <100000>;
74
75 /*
76 * Display monitor features are burnt in the EEPROM
77 * as EDID data.
78 */
79 eeprom@50 {
80 compatible = "ti,eeprom";
81 reg = <0x50>;
82 };
83};
84
85&mmc1 {
86 vmmc-supply = <&vmmc1>;
87 vmmc_aux-supply = <&vsim>;
88 bus-width = <8>;
89};
90
91&mmc2 {
92 status = "disabled";
93};
94
95&mmc3 {
96 status = "disabled";
97};
98
99&twl_gpio {
100 ti,use-leds;
101 /* pullups: BIT(1) */
102 ti,pullups = <0x000002>;
103 /*
104 * pulldowns:
105 * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13)
106 * BIT(15), BIT(16), BIT(17)
107 */
108 ti,pulldowns = <0x03a1c4>;
109};
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
deleted file mode 100644
index f624dc85d44..00000000000
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ /dev/null
@@ -1,67 +0,0 @@
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10/include/ "omap3.dtsi"
11
12/ {
13 model = "TI OMAP3 BeagleBoard";
14 compatible = "ti,omap3-beagle", "ti,omap3";
15
16 memory {
17 device_type = "memory";
18 reg = <0x80000000 0x10000000>; /* 256 MB */
19 };
20
21 leds {
22 compatible = "gpio-leds";
23 pmu_stat {
24 label = "beagleboard::pmu_stat";
25 gpios = <&twl_gpio 19 0>; /* LEDB */
26 };
27
28 heartbeat {
29 label = "beagleboard::usr0";
30 gpios = <&gpio5 22 0>; /* 150 -> D6 LED */
31 linux,default-trigger = "heartbeat";
32 };
33
34 mmc {
35 label = "beagleboard::usr1";
36 gpios = <&gpio5 21 0>; /* 149 -> D7 LED */
37 linux,default-trigger = "mmc0";
38 };
39 };
40
41};
42
43&i2c1 {
44 clock-frequency = <2600000>;
45
46 twl: twl@48 {
47 reg = <0x48>;
48 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
49 interrupt-parent = <&intc>;
50 };
51};
52
53/include/ "twl4030.dtsi"
54
55&mmc1 {
56 vmmc-supply = <&vmmc1>;
57 vmmc_aux-supply = <&vsim>;
58 bus-width = <8>;
59};
60
61&mmc2 {
62 status = "disabled";
63};
64
65&mmc3 {
66 status = "disabled";
67};
diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts
deleted file mode 100644
index e8ba1c247a3..00000000000
--- a/arch/arm/boot/dts/omap3-evm.dts
+++ /dev/null
@@ -1,61 +0,0 @@
1/*
2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10/include/ "omap3.dtsi"
11
12/ {
13 model = "TI OMAP3 EVM (OMAP3530, AM/DM37x)";
14 compatible = "ti,omap3-evm", "ti,omap3";
15
16 memory {
17 device_type = "memory";
18 reg = <0x80000000 0x10000000>; /* 256 MB */
19 };
20
21 leds {
22 compatible = "gpio-leds";
23 ledb {
24 label = "omap3evm::ledb";
25 gpios = <&twl_gpio 19 0>; /* LEDB */
26 linux,default-trigger = "default-on";
27 };
28 };
29};
30
31&i2c1 {
32 clock-frequency = <2600000>;
33
34 twl: twl@48 {
35 reg = <0x48>;
36 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
37 interrupt-parent = <&intc>;
38 };
39};
40
41/include/ "twl4030.dtsi"
42
43&i2c2 {
44 clock-frequency = <400000>;
45};
46
47&i2c3 {
48 clock-frequency = <400000>;
49
50 /*
51 * TVP5146 Video decoder-in for analog input support.
52 */
53 tvp5146@5c {
54 compatible = "ti,tvp5146m2";
55 reg = <0x5c>;
56 };
57};
58
59&twl_gpio {
60 ti,use-leds;
61};
diff --git a/arch/arm/boot/dts/omap3-overo.dtsi b/arch/arm/boot/dts/omap3-overo.dtsi
deleted file mode 100644
index 89808ce0167..00000000000
--- a/arch/arm/boot/dts/omap3-overo.dtsi
+++ /dev/null
@@ -1,57 +0,0 @@
1/*
2 * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * The Gumstix Overo must be combined with an expansion board.
11 */
12/dts-v1/;
13
14/include/ "omap3.dtsi"
15
16/ {
17 leds {
18 compatible = "gpio-leds";
19 overo {
20 label = "overo:blue:COM";
21 gpios = <&twl_gpio 19 0>;
22 linux,default-trigger = "mmc0";
23 };
24 };
25};
26
27&i2c1 {
28 clock-frequency = <2600000>;
29
30 twl: twl@48 {
31 reg = <0x48>;
32 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
33 interrupt-parent = <&intc>;
34 };
35};
36
37/include/ "twl4030.dtsi"
38
39/* i2c2 pins are used for gpio */
40&i2c2 {
41 status = "disabled";
42};
43
44/* on board microSD slot */
45&mmc1 {
46 vmmc-supply = <&vmmc1>;
47 bus-width = <4>;
48};
49
50/* optional on board WiFi */
51&mmc2 {
52 bus-width = <4>;
53};
54
55&twl_gpio {
56 ti,use-leds;
57};
diff --git a/arch/arm/boot/dts/omap3-tobi.dts b/arch/arm/boot/dts/omap3-tobi.dts
deleted file mode 100644
index a13d12de77f..00000000000
--- a/arch/arm/boot/dts/omap3-tobi.dts
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * Tobi expansion board is manufactured by Gumstix Inc.
11 */
12
13/include/ "omap3-overo.dtsi"
14
15/ {
16 model = "TI OMAP3 Gumstix Overo on Tobi";
17 compatible = "ti,omap3-tobi", "ti,omap3-overo", "ti,omap3";
18
19 leds {
20 compatible = "gpio-leds";
21 heartbeat {
22 label = "overo:red:gpio21";
23 gpios = <&gpio1 21 0>;
24 linux,default-trigger = "heartbeat";
25 };
26 };
27};
28
29&i2c3 {
30 clock-frequency = <100000>;
31};
32
33&mmc3 {
34 status = "disabled";
35};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
deleted file mode 100644
index 1acc26148ff..00000000000
--- a/arch/arm/boot/dts/omap3.dtsi
+++ /dev/null
@@ -1,401 +0,0 @@
1/*
2 * Device Tree Source for OMAP3 SoC
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "skeleton.dtsi"
12
13/ {
14 compatible = "ti,omap3430", "ti,omap3";
15 interrupt-parent = <&intc>;
16
17 aliases {
18 serial0 = &uart1;
19 serial1 = &uart2;
20 serial2 = &uart3;
21 };
22
23 cpus {
24 cpu@0 {
25 compatible = "arm,cortex-a8";
26 };
27 };
28
29 /*
30 * The soc node represents the soc top level view. It is uses for IPs
31 * that are not memory mapped in the MPU view or for the MPU itself.
32 */
33 soc {
34 compatible = "ti,omap-infra";
35 mpu {
36 compatible = "ti,omap3-mpu";
37 ti,hwmods = "mpu";
38 };
39
40 iva {
41 compatible = "ti,iva2.2";
42 ti,hwmods = "iva";
43
44 dsp {
45 compatible = "ti,omap3-c64";
46 };
47 };
48 };
49
50 /*
51 * XXX: Use a flat representation of the OMAP3 interconnect.
52 * The real OMAP interconnect network is quite complex.
53 * Since that will not bring real advantage to represent that in DT for
54 * the moment, just use a fake OCP bus entry to represent the whole bus
55 * hierarchy.
56 */
57 ocp {
58 compatible = "simple-bus";
59 #address-cells = <1>;
60 #size-cells = <1>;
61 ranges;
62 ti,hwmods = "l3_main";
63
64 counter32k: counter@48320000 {
65 compatible = "ti,omap-counter32k";
66 reg = <0x48320000 0x20>;
67 ti,hwmods = "counter_32k";
68 };
69
70 intc: interrupt-controller@48200000 {
71 compatible = "ti,omap2-intc";
72 interrupt-controller;
73 #interrupt-cells = <1>;
74 ti,intc-size = <96>;
75 reg = <0x48200000 0x1000>;
76 };
77
78 omap3_pmx_core: pinmux@48002030 {
79 compatible = "ti,omap3-padconf", "pinctrl-single";
80 reg = <0x48002030 0x05cc>;
81 #address-cells = <1>;
82 #size-cells = <0>;
83 pinctrl-single,register-width = <16>;
84 pinctrl-single,function-mask = <0x7fff>;
85 };
86
87 omap3_pmx_wkup: pinmux@0x48002a58 {
88 compatible = "ti,omap3-padconf", "pinctrl-single";
89 reg = <0x48002a58 0x5c>;
90 #address-cells = <1>;
91 #size-cells = <0>;
92 pinctrl-single,register-width = <16>;
93 pinctrl-single,function-mask = <0x7fff>;
94 };
95
96 gpio1: gpio@48310000 {
97 compatible = "ti,omap3-gpio";
98 ti,hwmods = "gpio1";
99 gpio-controller;
100 #gpio-cells = <2>;
101 interrupt-controller;
102 #interrupt-cells = <1>;
103 };
104
105 gpio2: gpio@49050000 {
106 compatible = "ti,omap3-gpio";
107 ti,hwmods = "gpio2";
108 gpio-controller;
109 #gpio-cells = <2>;
110 interrupt-controller;
111 #interrupt-cells = <1>;
112 };
113
114 gpio3: gpio@49052000 {
115 compatible = "ti,omap3-gpio";
116 ti,hwmods = "gpio3";
117 gpio-controller;
118 #gpio-cells = <2>;
119 interrupt-controller;
120 #interrupt-cells = <1>;
121 };
122
123 gpio4: gpio@49054000 {
124 compatible = "ti,omap3-gpio";
125 ti,hwmods = "gpio4";
126 gpio-controller;
127 #gpio-cells = <2>;
128 interrupt-controller;
129 #interrupt-cells = <1>;
130 };
131
132 gpio5: gpio@49056000 {
133 compatible = "ti,omap3-gpio";
134 ti,hwmods = "gpio5";
135 gpio-controller;
136 #gpio-cells = <2>;
137 interrupt-controller;
138 #interrupt-cells = <1>;
139 };
140
141 gpio6: gpio@49058000 {
142 compatible = "ti,omap3-gpio";
143 ti,hwmods = "gpio6";
144 gpio-controller;
145 #gpio-cells = <2>;
146 interrupt-controller;
147 #interrupt-cells = <1>;
148 };
149
150 uart1: serial@4806a000 {
151 compatible = "ti,omap3-uart";
152 ti,hwmods = "uart1";
153 clock-frequency = <48000000>;
154 };
155
156 uart2: serial@4806c000 {
157 compatible = "ti,omap3-uart";
158 ti,hwmods = "uart2";
159 clock-frequency = <48000000>;
160 };
161
162 uart3: serial@49020000 {
163 compatible = "ti,omap3-uart";
164 ti,hwmods = "uart3";
165 clock-frequency = <48000000>;
166 };
167
168 i2c1: i2c@48070000 {
169 compatible = "ti,omap3-i2c";
170 #address-cells = <1>;
171 #size-cells = <0>;
172 ti,hwmods = "i2c1";
173 };
174
175 i2c2: i2c@48072000 {
176 compatible = "ti,omap3-i2c";
177 #address-cells = <1>;
178 #size-cells = <0>;
179 ti,hwmods = "i2c2";
180 };
181
182 i2c3: i2c@48060000 {
183 compatible = "ti,omap3-i2c";
184 #address-cells = <1>;
185 #size-cells = <0>;
186 ti,hwmods = "i2c3";
187 };
188
189 mcspi1: spi@48098000 {
190 compatible = "ti,omap2-mcspi";
191 #address-cells = <1>;
192 #size-cells = <0>;
193 ti,hwmods = "mcspi1";
194 ti,spi-num-cs = <4>;
195 };
196
197 mcspi2: spi@4809a000 {
198 compatible = "ti,omap2-mcspi";
199 #address-cells = <1>;
200 #size-cells = <0>;
201 ti,hwmods = "mcspi2";
202 ti,spi-num-cs = <2>;
203 };
204
205 mcspi3: spi@480b8000 {
206 compatible = "ti,omap2-mcspi";
207 #address-cells = <1>;
208 #size-cells = <0>;
209 ti,hwmods = "mcspi3";
210 ti,spi-num-cs = <2>;
211 };
212
213 mcspi4: spi@480ba000 {
214 compatible = "ti,omap2-mcspi";
215 #address-cells = <1>;
216 #size-cells = <0>;
217 ti,hwmods = "mcspi4";
218 ti,spi-num-cs = <1>;
219 };
220
221 mmc1: mmc@4809c000 {
222 compatible = "ti,omap3-hsmmc";
223 ti,hwmods = "mmc1";
224 ti,dual-volt;
225 };
226
227 mmc2: mmc@480b4000 {
228 compatible = "ti,omap3-hsmmc";
229 ti,hwmods = "mmc2";
230 };
231
232 mmc3: mmc@480ad000 {
233 compatible = "ti,omap3-hsmmc";
234 ti,hwmods = "mmc3";
235 };
236
237 wdt2: wdt@48314000 {
238 compatible = "ti,omap3-wdt";
239 ti,hwmods = "wd_timer2";
240 };
241
242 mcbsp1: mcbsp@48074000 {
243 compatible = "ti,omap3-mcbsp";
244 reg = <0x48074000 0xff>;
245 reg-names = "mpu";
246 interrupts = <16>, /* OCP compliant interrupt */
247 <59>, /* TX interrupt */
248 <60>; /* RX interrupt */
249 interrupt-names = "common", "tx", "rx";
250 ti,buffer-size = <128>;
251 ti,hwmods = "mcbsp1";
252 };
253
254 mcbsp2: mcbsp@49022000 {
255 compatible = "ti,omap3-mcbsp";
256 reg = <0x49022000 0xff>,
257 <0x49028000 0xff>;
258 reg-names = "mpu", "sidetone";
259 interrupts = <17>, /* OCP compliant interrupt */
260 <62>, /* TX interrupt */
261 <63>, /* RX interrupt */
262 <4>; /* Sidetone */
263 interrupt-names = "common", "tx", "rx", "sidetone";
264 ti,buffer-size = <1280>;
265 ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
266 };
267
268 mcbsp3: mcbsp@49024000 {
269 compatible = "ti,omap3-mcbsp";
270 reg = <0x49024000 0xff>,
271 <0x4902a000 0xff>;
272 reg-names = "mpu", "sidetone";
273 interrupts = <22>, /* OCP compliant interrupt */
274 <89>, /* TX interrupt */
275 <90>, /* RX interrupt */
276 <5>; /* Sidetone */
277 interrupt-names = "common", "tx", "rx", "sidetone";
278 ti,buffer-size = <128>;
279 ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
280 };
281
282 mcbsp4: mcbsp@49026000 {
283 compatible = "ti,omap3-mcbsp";
284 reg = <0x49026000 0xff>;
285 reg-names = "mpu";
286 interrupts = <23>, /* OCP compliant interrupt */
287 <54>, /* TX interrupt */
288 <55>; /* RX interrupt */
289 interrupt-names = "common", "tx", "rx";
290 ti,buffer-size = <128>;
291 ti,hwmods = "mcbsp4";
292 };
293
294 mcbsp5: mcbsp@48096000 {
295 compatible = "ti,omap3-mcbsp";
296 reg = <0x48096000 0xff>;
297 reg-names = "mpu";
298 interrupts = <27>, /* OCP compliant interrupt */
299 <81>, /* TX interrupt */
300 <82>; /* RX interrupt */
301 interrupt-names = "common", "tx", "rx";
302 ti,buffer-size = <128>;
303 ti,hwmods = "mcbsp5";
304 };
305
306 timer1: timer@48318000 {
307 compatible = "ti,omap2-timer";
308 reg = <0x48318000 0x400>;
309 interrupts = <37>;
310 ti,hwmods = "timer1";
311 ti,timer-alwon;
312 };
313
314 timer2: timer@49032000 {
315 compatible = "ti,omap2-timer";
316 reg = <0x49032000 0x400>;
317 interrupts = <38>;
318 ti,hwmods = "timer2";
319 };
320
321 timer3: timer@49034000 {
322 compatible = "ti,omap2-timer";
323 reg = <0x49034000 0x400>;
324 interrupts = <39>;
325 ti,hwmods = "timer3";
326 };
327
328 timer4: timer@49036000 {
329 compatible = "ti,omap2-timer";
330 reg = <0x49036000 0x400>;
331 interrupts = <40>;
332 ti,hwmods = "timer4";
333 };
334
335 timer5: timer@49038000 {
336 compatible = "ti,omap2-timer";
337 reg = <0x49038000 0x400>;
338 interrupts = <41>;
339 ti,hwmods = "timer5";
340 ti,timer-dsp;
341 };
342
343 timer6: timer@4903a000 {
344 compatible = "ti,omap2-timer";
345 reg = <0x4903a000 0x400>;
346 interrupts = <42>;
347 ti,hwmods = "timer6";
348 ti,timer-dsp;
349 };
350
351 timer7: timer@4903c000 {
352 compatible = "ti,omap2-timer";
353 reg = <0x4903c000 0x400>;
354 interrupts = <43>;
355 ti,hwmods = "timer7";
356 ti,timer-dsp;
357 };
358
359 timer8: timer@4903e000 {
360 compatible = "ti,omap2-timer";
361 reg = <0x4903e000 0x400>;
362 interrupts = <44>;
363 ti,hwmods = "timer8";
364 ti,timer-pwm;
365 ti,timer-dsp;
366 };
367
368 timer9: timer@49040000 {
369 compatible = "ti,omap2-timer";
370 reg = <0x49040000 0x400>;
371 interrupts = <45>;
372 ti,hwmods = "timer9";
373 ti,timer-pwm;
374 };
375
376 timer10: timer@48086000 {
377 compatible = "ti,omap2-timer";
378 reg = <0x48086000 0x400>;
379 interrupts = <46>;
380 ti,hwmods = "timer10";
381 ti,timer-pwm;
382 };
383
384 timer11: timer@48088000 {
385 compatible = "ti,omap2-timer";
386 reg = <0x48088000 0x400>;
387 interrupts = <47>;
388 ti,hwmods = "timer11";
389 ti,timer-pwm;
390 };
391
392 timer12: timer@48304000 {
393 compatible = "ti,omap2-timer";
394 reg = <0x48304000 0x400>;
395 interrupts = <95>;
396 ti,hwmods = "timer12";
397 ti,timer-alwon;
398 ti,timer-secure;
399 };
400 };
401};
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
deleted file mode 100644
index 96bf0287cb9..00000000000
--- a/arch/arm/boot/dts/omap36xx.dtsi
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * Device Tree Source for OMAP3 SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "omap3.dtsi"
12
13/ {
14 aliases {
15 serial3 = &uart4;
16 };
17
18 ocp {
19 uart4: serial@49042000 {
20 compatible = "ti,omap3-uart";
21 ti,hwmods = "uart4";
22 clock-frequency = <48000000>;
23 };
24 };
25};
diff --git a/arch/arm/boot/dts/omap4-panda-a4.dts b/arch/arm/boot/dts/omap4-panda-a4.dts
deleted file mode 100644
index 75466d2abfb..00000000000
--- a/arch/arm/boot/dts/omap4-panda-a4.dts
+++ /dev/null
@@ -1,17 +0,0 @@
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/include/ "omap4-panda.dts"
9
10/* Pandaboard Rev A4+ have external pullups on SCL & SDA */
11&dss_hdmi_pins {
12 pinctrl-single,pins = <
13 0x5a 0x118 /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
14 0x5c 0x100 /* hdmi_scl.hdmi_scl INPUT | MODE 0 */
15 0x5e 0x100 /* hdmi_sda.hdmi_sda INPUT | MODE 0 */
16 >;
17};
diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts
deleted file mode 100644
index 73bc1a67e44..00000000000
--- a/arch/arm/boot/dts/omap4-panda-es.dts
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/include/ "omap4-panda.dts"
9
10/* Audio routing is differnet between PandaBoard4430 and PandaBoardES */
11&sound {
12 ti,model = "PandaBoardES";
13
14 /* Audio routing */
15 ti,audio-routing =
16 "Headset Stereophone", "HSOL",
17 "Headset Stereophone", "HSOR",
18 "Ext Spk", "HFL",
19 "Ext Spk", "HFR",
20 "Line Out", "AUXL",
21 "Line Out", "AUXR",
22 "AFML", "Line In",
23 "AFMR", "Line In";
24};
25
26/* PandaboardES has external pullups on SCL & SDA */
27&dss_hdmi_pins {
28 pinctrl-single,pins = <
29 0x5a 0x118 /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
30 0x5c 0x100 /* hdmi_scl.hdmi_scl INPUT | MODE 0 */
31 0x5e 0x100 /* hdmi_sda.hdmi_sda INPUT | MODE 0 */
32 >;
33};
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
deleted file mode 100644
index 4122efe31cf..00000000000
--- a/arch/arm/boot/dts/omap4-panda.dts
+++ /dev/null
@@ -1,208 +0,0 @@
1/*
2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10/include/ "omap4.dtsi"
11/include/ "elpida_ecb240abacn.dtsi"
12
13/ {
14 model = "TI OMAP4 PandaBoard";
15 compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4";
16
17 memory {
18 device_type = "memory";
19 reg = <0x80000000 0x40000000>; /* 1 GB */
20 };
21
22 leds {
23 compatible = "gpio-leds";
24 heartbeat {
25 label = "pandaboard::status1";
26 gpios = <&gpio1 7 0>;
27 linux,default-trigger = "heartbeat";
28 };
29
30 mmc {
31 label = "pandaboard::status2";
32 gpios = <&gpio1 8 0>;
33 linux,default-trigger = "mmc0";
34 };
35 };
36
37 sound: sound {
38 compatible = "ti,abe-twl6040";
39 ti,model = "PandaBoard";
40
41 ti,mclk-freq = <38400000>;
42
43 ti,mcpdm = <&mcpdm>;
44
45 ti,twl6040 = <&twl6040>;
46
47 /* Audio routing */
48 ti,audio-routing =
49 "Headset Stereophone", "HSOL",
50 "Headset Stereophone", "HSOR",
51 "Ext Spk", "HFL",
52 "Ext Spk", "HFR",
53 "Line Out", "AUXL",
54 "Line Out", "AUXR",
55 "HSMIC", "Headset Mic",
56 "Headset Mic", "Headset Mic Bias",
57 "AFML", "Line In",
58 "AFMR", "Line In";
59 };
60};
61
62&omap4_pmx_core {
63 pinctrl-names = "default";
64 pinctrl-0 = <
65 &twl6040_pins
66 &mcpdm_pins
67 &mcbsp1_pins
68 &dss_hdmi_pins
69 &tpd12s015_pins
70 >;
71
72 twl6040_pins: pinmux_twl6040_pins {
73 pinctrl-single,pins = <
74 0xe0 0x3 /* hdq_sio.gpio_127 OUTPUT | MODE3 */
75 0x160 0x100 /* sys_nirq2.sys_nirq2 INPUT | MODE0 */
76 >;
77 };
78
79 mcpdm_pins: pinmux_mcpdm_pins {
80 pinctrl-single,pins = <
81 0xc6 0x108 /* abe_pdm_ul_data.abe_pdm_ul_data INPUT PULLDOWN | MODE0 */
82 0xc8 0x108 /* abe_pdm_dl_data.abe_pdm_dl_data INPUT PULLDOWN | MODE0 */
83 0xca 0x118 /* abe_pdm_frame.abe_pdm_frame INPUT PULLUP | MODE0 */
84 0xcc 0x108 /* abe_pdm_lb_clk.abe_pdm_lb_clk INPUT PULLDOWN | MODE0 */
85 0xce 0x108 /* abe_clks.abe_clks INPUT PULLDOWN | MODE0 */
86 >;
87 };
88
89 mcbsp1_pins: pinmux_mcbsp1_pins {
90 pinctrl-single,pins = <
91 0xbe 0x100 /* abe_mcbsp1_clkx.abe_mcbsp1_clkx INPUT | MODE0 */
92 0xc0 0x108 /* abe_mcbsp1_dr.abe_mcbsp1_dr INPUT PULLDOWN | MODE0 */
93 0xc2 0x8 /* abe_mcbsp1_dx.abe_mcbsp1_dx OUTPUT PULLDOWN | MODE0 */
94 0xc4 0x100 /* abe_mcbsp1_fsx.abe_mcbsp1_fsx INPUT | MODE0 */
95 >;
96 };
97
98 dss_hdmi_pins: pinmux_dss_hdmi_pins {
99 pinctrl-single,pins = <
100 0x5a 0x118 /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
101 0x5c 0x118 /* hdmi_scl.hdmi_scl INPUT PULLUP | MODE 0 */
102 0x5e 0x118 /* hdmi_sda.hdmi_sda INPUT PULLUP | MODE 0 */
103 >;
104 };
105
106 tpd12s015_pins: pinmux_tpd12s015_pins {
107 pinctrl-single,pins = <
108 0x22 0x3 /* gpmc_a17.gpio_41 OUTPUT | MODE3 */
109 0x48 0x3 /* gpmc_nbe1.gpio_60 OUTPUT | MODE3 */
110 0x58 0x10b /* hdmi_hpd.gpio_63 INPUT PULLDOWN | MODE3 */
111 >;
112 };
113};
114
115&i2c1 {
116 clock-frequency = <400000>;
117
118 twl: twl@48 {
119 reg = <0x48>;
120 /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
121 interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
122 interrupt-parent = <&gic>;
123 };
124
125 twl6040: twl@4b {
126 compatible = "ti,twl6040";
127 reg = <0x4b>;
128 /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
129 interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */
130 interrupt-parent = <&gic>;
131 ti,audpwron-gpio = <&gpio4 31 0>; /* gpio line 127 */
132
133 vio-supply = <&v1v8>;
134 v2v1-supply = <&v2v1>;
135 enable-active-high;
136 };
137};
138
139/include/ "twl6030.dtsi"
140
141&i2c2 {
142 clock-frequency = <400000>;
143};
144
145&i2c3 {
146 clock-frequency = <100000>;
147
148 /*
149 * Display monitor features are burnt in their EEPROM as EDID data.
150 * The EEPROM is connected as I2C slave device.
151 */
152 eeprom@50 {
153 compatible = "ti,eeprom";
154 reg = <0x50>;
155 };
156};
157
158&i2c4 {
159 clock-frequency = <400000>;
160};
161
162&mmc1 {
163 vmmc-supply = <&vmmc>;
164 bus-width = <8>;
165};
166
167&mmc2 {
168 status = "disabled";
169};
170
171&mmc3 {
172 status = "disabled";
173};
174
175&mmc4 {
176 status = "disabled";
177};
178
179&mmc5 {
180 ti,non-removable;
181 bus-width = <4>;
182};
183
184&emif1 {
185 cs1-used;
186 device-handle = <&elpida_ECB240ABACN>;
187};
188
189&emif2 {
190 cs1-used;
191 device-handle = <&elpida_ECB240ABACN>;
192};
193
194&mcbsp2 {
195 status = "disabled";
196};
197
198&mcbsp3 {
199 status = "disabled";
200};
201
202&dmic {
203 status = "disabled";
204};
205
206&twl_usb_comparator {
207 usb-supply = <&vusb>;
208};
diff --git a/arch/arm/boot/dts/omap4-sdp-es23plus.dts b/arch/arm/boot/dts/omap4-sdp-es23plus.dts
deleted file mode 100644
index b4a40ffbce3..00000000000
--- a/arch/arm/boot/dts/omap4-sdp-es23plus.dts
+++ /dev/null
@@ -1,17 +0,0 @@
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/include/ "omap4-sdp.dts"
9
10/* SDP boards with 4430 ES2.3+ or 4460 have external pullups on SCL & SDA */
11&dss_hdmi_pins {
12 pinctrl-single,pins = <
13 0x5a 0x118 /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
14 0x5c 0x100 /* hdmi_scl.hdmi_scl INPUT | MODE 0 */
15 0x5e 0x100 /* hdmi_sda.hdmi_sda INPUT | MODE 0 */
16 >;
17};
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
deleted file mode 100644
index 43e5258a937..00000000000
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ /dev/null
@@ -1,430 +0,0 @@
1/*
2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10/include/ "omap4.dtsi"
11/include/ "elpida_ecb240abacn.dtsi"
12
13/ {
14 model = "TI OMAP4 SDP board";
15 compatible = "ti,omap4-sdp", "ti,omap4430", "ti,omap4";
16
17 memory {
18 device_type = "memory";
19 reg = <0x80000000 0x40000000>; /* 1 GB */
20 };
21
22 vdd_eth: fixedregulator-vdd-eth {
23 compatible = "regulator-fixed";
24 regulator-name = "VDD_ETH";
25 regulator-min-microvolt = <3300000>;
26 regulator-max-microvolt = <3300000>;
27 gpio = <&gpio2 16 0>; /* gpio line 48 */
28 enable-active-high;
29 regulator-boot-on;
30 };
31
32 vbat: fixedregulator-vbat {
33 compatible = "regulator-fixed";
34 regulator-name = "VBAT";
35 regulator-min-microvolt = <3750000>;
36 regulator-max-microvolt = <3750000>;
37 regulator-boot-on;
38 };
39
40 leds {
41 compatible = "gpio-leds";
42 debug0 {
43 label = "omap4:green:debug0";
44 gpios = <&gpio2 29 0>; /* 61 */
45 };
46
47 debug1 {
48 label = "omap4:green:debug1";
49 gpios = <&gpio1 30 0>; /* 30 */
50 };
51
52 debug2 {
53 label = "omap4:green:debug2";
54 gpios = <&gpio1 7 0>; /* 7 */
55 };
56
57 debug3 {
58 label = "omap4:green:debug3";
59 gpios = <&gpio1 8 0>; /* 8 */
60 };
61
62 debug4 {
63 label = "omap4:green:debug4";
64 gpios = <&gpio2 18 0>; /* 50 */
65 };
66
67 user1 {
68 label = "omap4:blue:user";
69 gpios = <&gpio6 9 0>; /* 169 */
70 };
71
72 user2 {
73 label = "omap4:red:user";
74 gpios = <&gpio6 10 0>; /* 170 */
75 };
76
77 user3 {
78 label = "omap4:green:user";
79 gpios = <&gpio5 11 0>; /* 139 */
80 };
81 };
82
83 sound {
84 compatible = "ti,abe-twl6040";
85 ti,model = "SDP4430";
86
87 ti,jack-detection = <1>;
88 ti,mclk-freq = <38400000>;
89
90 ti,mcpdm = <&mcpdm>;
91 ti,dmic = <&dmic>;
92
93 ti,twl6040 = <&twl6040>;
94
95 /* Audio routing */
96 ti,audio-routing =
97 "Headset Stereophone", "HSOL",
98 "Headset Stereophone", "HSOR",
99 "Earphone Spk", "EP",
100 "Ext Spk", "HFL",
101 "Ext Spk", "HFR",
102 "Line Out", "AUXL",
103 "Line Out", "AUXR",
104 "Vibrator", "VIBRAL",
105 "Vibrator", "VIBRAR",
106 "HSMIC", "Headset Mic",
107 "Headset Mic", "Headset Mic Bias",
108 "MAINMIC", "Main Handset Mic",
109 "Main Handset Mic", "Main Mic Bias",
110 "SUBMIC", "Sub Handset Mic",
111 "Sub Handset Mic", "Main Mic Bias",
112 "AFML", "Line In",
113 "AFMR", "Line In",
114 "DMic", "Digital Mic",
115 "Digital Mic", "Digital Mic1 Bias";
116 };
117};
118
119&omap4_pmx_core {
120 pinctrl-names = "default";
121 pinctrl-0 = <
122 &twl6040_pins
123 &mcpdm_pins
124 &dmic_pins
125 &mcbsp1_pins
126 &mcbsp2_pins
127 &dss_hdmi_pins
128 &tpd12s015_pins
129 >;
130
131 uart2_pins: pinmux_uart2_pins {
132 pinctrl-single,pins = <
133 0xd8 0x118 /* uart2_cts.uart2_cts INPUT_PULLUP | MODE0 */
134 0xda 0 /* uart2_rts.uart2_rts OUTPUT | MODE0 */
135 0xdc 0x118 /* uart2_rx.uart2_rx INPUT_PULLUP | MODE0 */
136 0xde 0 /* uart2_tx.uart2_tx OUTPUT | MODE0 */
137 >;
138 };
139
140 uart3_pins: pinmux_uart3_pins {
141 pinctrl-single,pins = <
142 0x100 0x118 /* uart3_cts_rctx.uart3_cts_rctx INPUT_PULLUP | MODE0 */
143 0x102 0 /* uart3_rts_sd.uart3_rts_sd OUTPUT | MODE0 */
144 0x104 0x100 /* uart3_rx_irrx.uart3_rx_irrx INPUT | MODE0 */
145 0x106 0 /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */
146 >;
147 };
148
149 uart4_pins: pinmux_uart4_pins {
150 pinctrl-single,pins = <
151 0x11c 0x100 /* uart4_rx.uart4_rx INPUT | MODE0 */
152 0x11e 0 /* uart4_tx.uart4_tx OUTPUT | MODE0 */
153 >;
154 };
155
156 twl6040_pins: pinmux_twl6040_pins {
157 pinctrl-single,pins = <
158 0xe0 0x3 /* hdq_sio.gpio_127 OUTPUT | MODE3 */
159 0x160 0x100 /* sys_nirq2.sys_nirq2 INPUT | MODE0 */
160 >;
161 };
162
163 mcpdm_pins: pinmux_mcpdm_pins {
164 pinctrl-single,pins = <
165 0xc6 0x108 /* abe_pdm_ul_data.abe_pdm_ul_data INPUT PULLDOWN | MODE0 */
166 0xc8 0x108 /* abe_pdm_dl_data.abe_pdm_dl_data INPUT PULLDOWN | MODE0 */
167 0xca 0x118 /* abe_pdm_frame.abe_pdm_frame INPUT PULLUP | MODE0 */
168 0xcc 0x108 /* abe_pdm_lb_clk.abe_pdm_lb_clk INPUT PULLDOWN | MODE0 */
169 0xce 0x108 /* abe_clks.abe_clks INPUT PULLDOWN | MODE0 */
170 >;
171 };
172
173 dmic_pins: pinmux_dmic_pins {
174 pinctrl-single,pins = <
175 0xd0 0 /* abe_dmic_clk1.abe_dmic_clk1 OUTPUT | MODE0 */
176 0xd2 0x100 /* abe_dmic_din1.abe_dmic_din1 INPUT | MODE0 */
177 0xd4 0x100 /* abe_dmic_din2.abe_dmic_din2 INPUT | MODE0 */
178 0xd6 0x100 /* abe_dmic_din3.abe_dmic_din3 INPUT | MODE0 */
179 >;
180 };
181
182 mcbsp1_pins: pinmux_mcbsp1_pins {
183 pinctrl-single,pins = <
184 0xbe 0x100 /* abe_mcbsp1_clkx.abe_mcbsp1_clkx INPUT | MODE0 */
185 0xc0 0x108 /* abe_mcbsp1_dr.abe_mcbsp1_dr INPUT PULLDOWN | MODE0 */
186 0xc2 0x8 /* abe_mcbsp1_dx.abe_mcbsp1_dx OUTPUT PULLDOWN | MODE0 */
187 0xc4 0x100 /* abe_mcbsp1_fsx.abe_mcbsp1_fsx INPUT | MODE0 */
188 >;
189 };
190
191 mcbsp2_pins: pinmux_mcbsp2_pins {
192 pinctrl-single,pins = <
193 0xb6 0x100 /* abe_mcbsp2_clkx.abe_mcbsp2_clkx INPUT | MODE0 */
194 0xb8 0x108 /* abe_mcbsp2_dr.abe_mcbsp2_dr INPUT PULLDOWN | MODE0 */
195 0xba 0x8 /* abe_mcbsp2_dx.abe_mcbsp2_dx OUTPUT PULLDOWN | MODE0 */
196 0xbc 0x100 /* abe_mcbsp2_fsx.abe_mcbsp2_fsx INPUT | MODE0 */
197 >;
198 };
199
200 dss_hdmi_pins: pinmux_dss_hdmi_pins {
201 pinctrl-single,pins = <
202 0x5a 0x118 /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
203 0x5c 0x118 /* hdmi_scl.hdmi_scl INPUT PULLUP | MODE 0 */
204 0x5e 0x118 /* hdmi_sda.hdmi_sda INPUT PULLUP | MODE 0 */
205 >;
206 };
207
208 tpd12s015_pins: pinmux_tpd12s015_pins {
209 pinctrl-single,pins = <
210 0x22 0x3 /* gpmc_a17.gpio_41 OUTPUT | MODE3 */
211 0x48 0x3 /* gpmc_nbe1.gpio_60 OUTPUT | MODE3 */
212 0x58 0x10b /* hdmi_hpd.gpio_63 INPUT PULLDOWN | MODE3 */
213 >;
214 };
215};
216
217&i2c1 {
218 clock-frequency = <400000>;
219
220 twl: twl@48 {
221 reg = <0x48>;
222 /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
223 interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
224 interrupt-parent = <&gic>;
225 };
226
227 twl6040: twl@4b {
228 compatible = "ti,twl6040";
229 reg = <0x4b>;
230 /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
231 interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */
232 interrupt-parent = <&gic>;
233 ti,audpwron-gpio = <&gpio4 31 0>; /* gpio line 127 */
234
235 vio-supply = <&v1v8>;
236 v2v1-supply = <&v2v1>;
237 enable-active-high;
238
239 /* regulators for vibra motor */
240 vddvibl-supply = <&vbat>;
241 vddvibr-supply = <&vbat>;
242
243 vibra {
244 /* Vibra driver, motor resistance parameters */
245 ti,vibldrv-res = <8>;
246 ti,vibrdrv-res = <3>;
247 ti,viblmotor-res = <10>;
248 ti,vibrmotor-res = <10>;
249 };
250 };
251};
252
253/include/ "twl6030.dtsi"
254
255&i2c2 {
256 clock-frequency = <400000>;
257};
258
259&i2c3 {
260 clock-frequency = <400000>;
261
262 /*
263 * Temperature Sensor
264 * http://www.ti.com/lit/ds/symlink/tmp105.pdf
265 */
266 tmp105@48 {
267 compatible = "ti,tmp105";
268 reg = <0x48>;
269 };
270
271 /*
272 * Ambient Light Sensor
273 * http://www.rohm.com/products/databook/sensor/pdf/bh1780gli-e.pdf
274 */
275 bh1780@29 {
276 compatible = "rohm,bh1780";
277 reg = <0x29>;
278 };
279};
280
281&i2c4 {
282 clock-frequency = <400000>;
283
284 /*
285 * 3-Axis Digital Compass
286 * http://www.sparkfun.com/datasheets/Sensors/Magneto/HMC5843.pdf
287 */
288 hmc5843@1e {
289 compatible = "honeywell,hmc5843";
290 reg = <0x1e>;
291 };
292};
293
294&mcspi1 {
295 eth@0 {
296 compatible = "ks8851";
297 spi-max-frequency = <24000000>;
298 reg = <0>;
299 interrupt-parent = <&gpio2>;
300 interrupts = <2>; /* gpio line 34 */
301 vdd-supply = <&vdd_eth>;
302 };
303};
304
305&mmc1 {
306 vmmc-supply = <&vmmc>;
307 bus-width = <8>;
308};
309
310&mmc2 {
311 vmmc-supply = <&vaux1>;
312 bus-width = <8>;
313 ti,non-removable;
314};
315
316&mmc3 {
317 status = "disabled";
318};
319
320&mmc4 {
321 status = "disabled";
322};
323
324&mmc5 {
325 bus-width = <4>;
326 ti,non-removable;
327};
328
329&emif1 {
330 cs1-used;
331 device-handle = <&elpida_ECB240ABACN>;
332};
333
334&emif2 {
335 cs1-used;
336 device-handle = <&elpida_ECB240ABACN>;
337};
338
339&keypad {
340 keypad,num-rows = <8>;
341 keypad,num-columns = <8>;
342 linux,keymap = <0x00000012 /* KEY_E */
343 0x00010013 /* KEY_R */
344 0x00020014 /* KEY_T */
345 0x00030066 /* KEY_HOME */
346 0x0004003f /* KEY_F5 */
347 0x000500f0 /* KEY_UNKNOWN */
348 0x00060017 /* KEY_I */
349 0x0007002a /* KEY_LEFTSHIFT */
350 0x01000020 /* KEY_D*/
351 0x01010021 /* KEY_F */
352 0x01020022 /* KEY_G */
353 0x010300e7 /* KEY_SEND */
354 0x01040040 /* KEY_F6 */
355 0x010500f0 /* KEY_UNKNOWN */
356 0x01060025 /* KEY_K */
357 0x0107001c /* KEY_ENTER */
358 0x0200002d /* KEY_X */
359 0x0201002e /* KEY_C */
360 0x0202002f /* KEY_V */
361 0x0203006b /* KEY_END */
362 0x02040041 /* KEY_F7 */
363 0x020500f0 /* KEY_UNKNOWN */
364 0x02060034 /* KEY_DOT */
365 0x0207003a /* KEY_CAPSLOCK */
366 0x0300002c /* KEY_Z */
367 0x0301004e /* KEY_KPLUS */
368 0x03020030 /* KEY_B */
369 0x0303003b /* KEY_F1 */
370 0x03040042 /* KEY_F8 */
371 0x030500f0 /* KEY_UNKNOWN */
372 0x03060018 /* KEY_O */
373 0x03070039 /* KEY_SPACE */
374 0x04000011 /* KEY_W */
375 0x04010015 /* KEY_Y */
376 0x04020016 /* KEY_U */
377 0x0403003c /* KEY_F2 */
378 0x04040073 /* KEY_VOLUMEUP */
379 0x040500f0 /* KEY_UNKNOWN */
380 0x04060026 /* KEY_L */
381 0x04070069 /* KEY_LEFT */
382 0x0500001f /* KEY_S */
383 0x05010023 /* KEY_H */
384 0x05020024 /* KEY_J */
385 0x0503003d /* KEY_F3 */
386 0x05040043 /* KEY_F9 */
387 0x05050072 /* KEY_VOLUMEDOWN */
388 0x05060032 /* KEY_M */
389 0x0507006a /* KEY_RIGHT */
390 0x06000010 /* KEY_Q */
391 0x0601001e /* KEY_A */
392 0x06020031 /* KEY_N */
393 0x0603009e /* KEY_BACK */
394 0x0604000e /* KEY_BACKSPACE */
395 0x060500f0 /* KEY_UNKNOWN */
396 0x06060019 /* KEY_P */
397 0x06070067 /* KEY_UP */
398 0x07000094 /* KEY_PROG1 */
399 0x07010095 /* KEY_PROG2 */
400 0x070200ca /* KEY_PROG3 */
401 0x070300cb /* KEY_PROG4 */
402 0x0704003e /* KEY_F4 */
403 0x070500f0 /* KEY_UNKNOWN */
404 0x07060160 /* KEY_OK */
405 0x0707006c>; /* KEY_DOWN */
406 linux,input-no-autorepeat;
407};
408
409&uart2 {
410 pinctrl-names = "default";
411 pinctrl-0 = <&uart2_pins>;
412};
413
414&uart3 {
415 pinctrl-names = "default";
416 pinctrl-0 = <&uart3_pins>;
417};
418
419&uart4 {
420 pinctrl-names = "default";
421 pinctrl-0 = <&uart4_pins>;
422};
423
424&mcbsp3 {
425 status = "disabled";
426};
427
428&twl_usb_comparator {
429 usb-supply = <&vusb>;
430};
diff --git a/arch/arm/boot/dts/omap4-var-som.dts b/arch/arm/boot/dts/omap4-var-som.dts
deleted file mode 100644
index 6601e6af609..00000000000
--- a/arch/arm/boot/dts/omap4-var-som.dts
+++ /dev/null
@@ -1,96 +0,0 @@
1/*
2 * Copyright (C) 2012 Variscite Ltd. - http://www.variscite.com
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10/include/ "omap4.dtsi"
11
12/ {
13 model = "Variscite OMAP4 SOM";
14 compatible = "var,omap4-var_som", "ti,omap4430", "ti,omap4";
15
16 memory {
17 device_type = "memory";
18 reg = <0x80000000 0x40000000>; /* 1 GB */
19 };
20
21 vdd_eth: fixedregulator@0 {
22 compatible = "regulator-fixed";
23 regulator-name = "VDD_ETH";
24 regulator-min-microvolt = <3300000>;
25 regulator-max-microvolt = <3300000>;
26 enable-active-high;
27 regulator-boot-on;
28 };
29};
30
31&i2c1 {
32 clock-frequency = <400000>;
33
34 twl: twl@48 {
35 reg = <0x48>;
36 /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
37 interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
38 interrupt-parent = <&gic>;
39 };
40};
41
42/include/ "twl6030.dtsi"
43
44&i2c2 {
45 clock-frequency = <400000>;
46};
47
48&i2c3 {
49 clock-frequency = <400000>;
50
51 /*
52 * Temperature Sensor
53 * http://www.ti.com/lit/ds/symlink/tmp105.pdf
54 */
55 tmp105@49 {
56 compatible = "ti,tmp105";
57 reg = <0x49>;
58 };
59};
60
61&i2c4 {
62 clock-frequency = <400000>;
63};
64
65&mcspi1 {
66 eth@0 {
67 compatible = "ks8851";
68 spi-max-frequency = <24000000>;
69 reg = <0>;
70 interrupt-parent = <&gpio6>;
71 interrupts = <11>; /* gpio line 171 */
72 vdd-supply = <&vdd_eth>;
73 };
74};
75
76&mmc1 {
77 vmmc-supply = <&vmmc>;
78 ti,bus-width = <8>;
79 ti,non-removable;
80};
81
82&mmc2 {
83 status = "disabled";
84};
85
86&mmc3 {
87 status = "disabled";
88};
89
90&mmc4 {
91 status = "disabled";
92};
93
94&mmc5 {
95 ti,bus-width = <4>;
96};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
deleted file mode 100644
index 739bb79e410..00000000000
--- a/arch/arm/boot/dts/omap4.dtsi
+++ /dev/null
@@ -1,533 +0,0 @@
1/*
2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * Carveout for multimedia usecases
11 * It should be the last 48MB of the first 512MB memory part
12 * In theory, it should not even exist. That zone should be reserved
13 * dynamically during the .reserve callback.
14 */
15/memreserve/ 0x9d000000 0x03000000;
16
17/include/ "skeleton.dtsi"
18
19/ {
20 compatible = "ti,omap4430", "ti,omap4";
21 interrupt-parent = <&gic>;
22
23 aliases {
24 serial0 = &uart1;
25 serial1 = &uart2;
26 serial2 = &uart3;
27 serial3 = &uart4;
28 };
29
30 cpus {
31 cpu@0 {
32 compatible = "arm,cortex-a9";
33 next-level-cache = <&L2>;
34 };
35 cpu@1 {
36 compatible = "arm,cortex-a9";
37 next-level-cache = <&L2>;
38 };
39 };
40
41 gic: interrupt-controller@48241000 {
42 compatible = "arm,cortex-a9-gic";
43 interrupt-controller;
44 #interrupt-cells = <3>;
45 reg = <0x48241000 0x1000>,
46 <0x48240100 0x0100>;
47 };
48
49 L2: l2-cache-controller@48242000 {
50 compatible = "arm,pl310-cache";
51 reg = <0x48242000 0x1000>;
52 cache-unified;
53 cache-level = <2>;
54 };
55
56 local-timer@0x48240600 {
57 compatible = "arm,cortex-a9-twd-timer";
58 reg = <0x48240600 0x20>;
59 interrupts = <1 13 0x304>;
60 };
61
62 /*
63 * The soc node represents the soc top level view. It is uses for IPs
64 * that are not memory mapped in the MPU view or for the MPU itself.
65 */
66 soc {
67 compatible = "ti,omap-infra";
68 mpu {
69 compatible = "ti,omap4-mpu";
70 ti,hwmods = "mpu";
71 };
72
73 dsp {
74 compatible = "ti,omap3-c64";
75 ti,hwmods = "dsp";
76 };
77
78 iva {
79 compatible = "ti,ivahd";
80 ti,hwmods = "iva";
81 };
82 };
83
84 /*
85 * XXX: Use a flat representation of the OMAP4 interconnect.
86 * The real OMAP interconnect network is quite complex.
87 * Since that will not bring real advantage to represent that in DT for
88 * the moment, just use a fake OCP bus entry to represent the whole bus
89 * hierarchy.
90 */
91 ocp {
92 compatible = "ti,omap4-l3-noc", "simple-bus";
93 #address-cells = <1>;
94 #size-cells = <1>;
95 ranges;
96 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
97
98 counter32k: counter@4a304000 {
99 compatible = "ti,omap-counter32k";
100 reg = <0x4a304000 0x20>;
101 ti,hwmods = "counter_32k";
102 };
103
104 omap4_pmx_core: pinmux@4a100040 {
105 compatible = "ti,omap4-padconf", "pinctrl-single";
106 reg = <0x4a100040 0x0196>;
107 #address-cells = <1>;
108 #size-cells = <0>;
109 pinctrl-single,register-width = <16>;
110 pinctrl-single,function-mask = <0x7fff>;
111 };
112 omap4_pmx_wkup: pinmux@4a31e040 {
113 compatible = "ti,omap4-padconf", "pinctrl-single";
114 reg = <0x4a31e040 0x0038>;
115 #address-cells = <1>;
116 #size-cells = <0>;
117 pinctrl-single,register-width = <16>;
118 pinctrl-single,function-mask = <0x7fff>;
119 };
120
121 gpio1: gpio@4a310000 {
122 compatible = "ti,omap4-gpio";
123 reg = <0x4a310000 0x200>;
124 interrupts = <0 29 0x4>;
125 ti,hwmods = "gpio1";
126 gpio-controller;
127 #gpio-cells = <2>;
128 interrupt-controller;
129 #interrupt-cells = <1>;
130 };
131
132 gpio2: gpio@48055000 {
133 compatible = "ti,omap4-gpio";
134 reg = <0x48055000 0x200>;
135 interrupts = <0 30 0x4>;
136 ti,hwmods = "gpio2";
137 gpio-controller;
138 #gpio-cells = <2>;
139 interrupt-controller;
140 #interrupt-cells = <1>;
141 };
142
143 gpio3: gpio@48057000 {
144 compatible = "ti,omap4-gpio";
145 reg = <0x48057000 0x200>;
146 interrupts = <0 31 0x4>;
147 ti,hwmods = "gpio3";
148 gpio-controller;
149 #gpio-cells = <2>;
150 interrupt-controller;
151 #interrupt-cells = <1>;
152 };
153
154 gpio4: gpio@48059000 {
155 compatible = "ti,omap4-gpio";
156 reg = <0x48059000 0x200>;
157 interrupts = <0 32 0x4>;
158 ti,hwmods = "gpio4";
159 gpio-controller;
160 #gpio-cells = <2>;
161 interrupt-controller;
162 #interrupt-cells = <1>;
163 };
164
165 gpio5: gpio@4805b000 {
166 compatible = "ti,omap4-gpio";
167 reg = <0x4805b000 0x200>;
168 interrupts = <0 33 0x4>;
169 ti,hwmods = "gpio5";
170 gpio-controller;
171 #gpio-cells = <2>;
172 interrupt-controller;
173 #interrupt-cells = <1>;
174 };
175
176 gpio6: gpio@4805d000 {
177 compatible = "ti,omap4-gpio";
178 reg = <0x4805d000 0x200>;
179 interrupts = <0 34 0x4>;
180 ti,hwmods = "gpio6";
181 gpio-controller;
182 #gpio-cells = <2>;
183 interrupt-controller;
184 #interrupt-cells = <1>;
185 };
186
187 uart1: serial@4806a000 {
188 compatible = "ti,omap4-uart";
189 reg = <0x4806a000 0x100>;
190 interrupts = <0 72 0x4>;
191 ti,hwmods = "uart1";
192 clock-frequency = <48000000>;
193 };
194
195 uart2: serial@4806c000 {
196 compatible = "ti,omap4-uart";
197 reg = <0x4806c000 0x100>;
198 interrupts = <0 73 0x4>;
199 ti,hwmods = "uart2";
200 clock-frequency = <48000000>;
201 };
202
203 uart3: serial@48020000 {
204 compatible = "ti,omap4-uart";
205 reg = <0x48020000 0x100>;
206 interrupts = <0 74 0x4>;
207 ti,hwmods = "uart3";
208 clock-frequency = <48000000>;
209 };
210
211 uart4: serial@4806e000 {
212 compatible = "ti,omap4-uart";
213 reg = <0x4806e000 0x100>;
214 interrupts = <0 70 0x4>;
215 ti,hwmods = "uart4";
216 clock-frequency = <48000000>;
217 };
218
219 i2c1: i2c@48070000 {
220 compatible = "ti,omap4-i2c";
221 reg = <0x48070000 0x100>;
222 interrupts = <0 56 0x4>;
223 #address-cells = <1>;
224 #size-cells = <0>;
225 ti,hwmods = "i2c1";
226 };
227
228 i2c2: i2c@48072000 {
229 compatible = "ti,omap4-i2c";
230 reg = <0x48072000 0x100>;
231 interrupts = <0 57 0x4>;
232 #address-cells = <1>;
233 #size-cells = <0>;
234 ti,hwmods = "i2c2";
235 };
236
237 i2c3: i2c@48060000 {
238 compatible = "ti,omap4-i2c";
239 reg = <0x48060000 0x100>;
240 interrupts = <0 61 0x4>;
241 #address-cells = <1>;
242 #size-cells = <0>;
243 ti,hwmods = "i2c3";
244 };
245
246 i2c4: i2c@48350000 {
247 compatible = "ti,omap4-i2c";
248 reg = <0x48350000 0x100>;
249 interrupts = <0 62 0x4>;
250 #address-cells = <1>;
251 #size-cells = <0>;
252 ti,hwmods = "i2c4";
253 };
254
255 mcspi1: spi@48098000 {
256 compatible = "ti,omap4-mcspi";
257 reg = <0x48098000 0x200>;
258 interrupts = <0 65 0x4>;
259 #address-cells = <1>;
260 #size-cells = <0>;
261 ti,hwmods = "mcspi1";
262 ti,spi-num-cs = <4>;
263 };
264
265 mcspi2: spi@4809a000 {
266 compatible = "ti,omap4-mcspi";
267 reg = <0x4809a000 0x200>;
268 interrupts = <0 66 0x4>;
269 #address-cells = <1>;
270 #size-cells = <0>;
271 ti,hwmods = "mcspi2";
272 ti,spi-num-cs = <2>;
273 };
274
275 mcspi3: spi@480b8000 {
276 compatible = "ti,omap4-mcspi";
277 reg = <0x480b8000 0x200>;
278 interrupts = <0 91 0x4>;
279 #address-cells = <1>;
280 #size-cells = <0>;
281 ti,hwmods = "mcspi3";
282 ti,spi-num-cs = <2>;
283 };
284
285 mcspi4: spi@480ba000 {
286 compatible = "ti,omap4-mcspi";
287 reg = <0x480ba000 0x200>;
288 interrupts = <0 48 0x4>;
289 #address-cells = <1>;
290 #size-cells = <0>;
291 ti,hwmods = "mcspi4";
292 ti,spi-num-cs = <1>;
293 };
294
295 mmc1: mmc@4809c000 {
296 compatible = "ti,omap4-hsmmc";
297 reg = <0x4809c000 0x400>;
298 interrupts = <0 83 0x4>;
299 ti,hwmods = "mmc1";
300 ti,dual-volt;
301 ti,needs-special-reset;
302 };
303
304 mmc2: mmc@480b4000 {
305 compatible = "ti,omap4-hsmmc";
306 reg = <0x480b4000 0x400>;
307 interrupts = <0 86 0x4>;
308 ti,hwmods = "mmc2";
309 ti,needs-special-reset;
310 };
311
312 mmc3: mmc@480ad000 {
313 compatible = "ti,omap4-hsmmc";
314 reg = <0x480ad000 0x400>;
315 interrupts = <0 94 0x4>;
316 ti,hwmods = "mmc3";
317 ti,needs-special-reset;
318 };
319
320 mmc4: mmc@480d1000 {
321 compatible = "ti,omap4-hsmmc";
322 reg = <0x480d1000 0x400>;
323 interrupts = <0 96 0x4>;
324 ti,hwmods = "mmc4";
325 ti,needs-special-reset;
326 };
327
328 mmc5: mmc@480d5000 {
329 compatible = "ti,omap4-hsmmc";
330 reg = <0x480d5000 0x400>;
331 interrupts = <0 59 0x4>;
332 ti,hwmods = "mmc5";
333 ti,needs-special-reset;
334 };
335
336 wdt2: wdt@4a314000 {
337 compatible = "ti,omap4-wdt", "ti,omap3-wdt";
338 reg = <0x4a314000 0x80>;
339 interrupts = <0 80 0x4>;
340 ti,hwmods = "wd_timer2";
341 };
342
343 mcpdm: mcpdm@40132000 {
344 compatible = "ti,omap4-mcpdm";
345 reg = <0x40132000 0x7f>, /* MPU private access */
346 <0x49032000 0x7f>; /* L3 Interconnect */
347 reg-names = "mpu", "dma";
348 interrupts = <0 112 0x4>;
349 ti,hwmods = "mcpdm";
350 };
351
352 dmic: dmic@4012e000 {
353 compatible = "ti,omap4-dmic";
354 reg = <0x4012e000 0x7f>, /* MPU private access */
355 <0x4902e000 0x7f>; /* L3 Interconnect */
356 reg-names = "mpu", "dma";
357 interrupts = <0 114 0x4>;
358 ti,hwmods = "dmic";
359 };
360
361 mcbsp1: mcbsp@40122000 {
362 compatible = "ti,omap4-mcbsp";
363 reg = <0x40122000 0xff>, /* MPU private access */
364 <0x49022000 0xff>; /* L3 Interconnect */
365 reg-names = "mpu", "dma";
366 interrupts = <0 17 0x4>;
367 interrupt-names = "common";
368 ti,buffer-size = <128>;
369 ti,hwmods = "mcbsp1";
370 };
371
372 mcbsp2: mcbsp@40124000 {
373 compatible = "ti,omap4-mcbsp";
374 reg = <0x40124000 0xff>, /* MPU private access */
375 <0x49024000 0xff>; /* L3 Interconnect */
376 reg-names = "mpu", "dma";
377 interrupts = <0 22 0x4>;
378 interrupt-names = "common";
379 ti,buffer-size = <128>;
380 ti,hwmods = "mcbsp2";
381 };
382
383 mcbsp3: mcbsp@40126000 {
384 compatible = "ti,omap4-mcbsp";
385 reg = <0x40126000 0xff>, /* MPU private access */
386 <0x49026000 0xff>; /* L3 Interconnect */
387 reg-names = "mpu", "dma";
388 interrupts = <0 23 0x4>;
389 interrupt-names = "common";
390 ti,buffer-size = <128>;
391 ti,hwmods = "mcbsp3";
392 };
393
394 mcbsp4: mcbsp@48096000 {
395 compatible = "ti,omap4-mcbsp";
396 reg = <0x48096000 0xff>; /* L4 Interconnect */
397 reg-names = "mpu";
398 interrupts = <0 16 0x4>;
399 interrupt-names = "common";
400 ti,buffer-size = <128>;
401 ti,hwmods = "mcbsp4";
402 };
403
404 keypad: keypad@4a31c000 {
405 compatible = "ti,omap4-keypad";
406 reg = <0x4a31c000 0x80>;
407 interrupts = <0 120 0x4>;
408 reg-names = "mpu";
409 ti,hwmods = "kbd";
410 };
411
412 emif1: emif@4c000000 {
413 compatible = "ti,emif-4d";
414 reg = <0x4c000000 0x100>;
415 interrupts = <0 110 0x4>;
416 ti,hwmods = "emif1";
417 phy-type = <1>;
418 hw-caps-read-idle-ctrl;
419 hw-caps-ll-interface;
420 hw-caps-temp-alert;
421 };
422
423 emif2: emif@4d000000 {
424 compatible = "ti,emif-4d";
425 reg = <0x4d000000 0x100>;
426 interrupts = <0 111 0x4>;
427 ti,hwmods = "emif2";
428 phy-type = <1>;
429 hw-caps-read-idle-ctrl;
430 hw-caps-ll-interface;
431 hw-caps-temp-alert;
432 };
433
434 ocp2scp@4a0ad000 {
435 compatible = "ti,omap-ocp2scp";
436 reg = <0x4a0ad000 0x1f>;
437 #address-cells = <1>;
438 #size-cells = <1>;
439 ranges;
440 ti,hwmods = "ocp2scp_usb_phy";
441 };
442
443 timer1: timer@4a318000 {
444 compatible = "ti,omap2-timer";
445 reg = <0x4a318000 0x80>;
446 interrupts = <0 37 0x4>;
447 ti,hwmods = "timer1";
448 ti,timer-alwon;
449 };
450
451 timer2: timer@48032000 {
452 compatible = "ti,omap2-timer";
453 reg = <0x48032000 0x80>;
454 interrupts = <0 38 0x4>;
455 ti,hwmods = "timer2";
456 };
457
458 timer3: timer@48034000 {
459 compatible = "ti,omap2-timer";
460 reg = <0x48034000 0x80>;
461 interrupts = <0 39 0x4>;
462 ti,hwmods = "timer3";
463 };
464
465 timer4: timer@48036000 {
466 compatible = "ti,omap2-timer";
467 reg = <0x48036000 0x80>;
468 interrupts = <0 40 0x4>;
469 ti,hwmods = "timer4";
470 };
471
472 timer5: timer@40138000 {
473 compatible = "ti,omap2-timer";
474 reg = <0x40138000 0x80>,
475 <0x49038000 0x80>;
476 interrupts = <0 41 0x4>;
477 ti,hwmods = "timer5";
478 ti,timer-dsp;
479 };
480
481 timer6: timer@4013a000 {
482 compatible = "ti,omap2-timer";
483 reg = <0x4013a000 0x80>,
484 <0x4903a000 0x80>;
485 interrupts = <0 42 0x4>;
486 ti,hwmods = "timer6";
487 ti,timer-dsp;
488 };
489
490 timer7: timer@4013c000 {
491 compatible = "ti,omap2-timer";
492 reg = <0x4013c000 0x80>,
493 <0x4903c000 0x80>;
494 interrupts = <0 43 0x4>;
495 ti,hwmods = "timer7";
496 ti,timer-dsp;
497 };
498
499 timer8: timer@4013e000 {
500 compatible = "ti,omap2-timer";
501 reg = <0x4013e000 0x80>,
502 <0x4903e000 0x80>;
503 interrupts = <0 44 0x4>;
504 ti,hwmods = "timer8";
505 ti,timer-pwm;
506 ti,timer-dsp;
507 };
508
509 timer9: timer@4803e000 {
510 compatible = "ti,omap2-timer";
511 reg = <0x4803e000 0x80>;
512 interrupts = <0 45 0x4>;
513 ti,hwmods = "timer9";
514 ti,timer-pwm;
515 };
516
517 timer10: timer@48086000 {
518 compatible = "ti,omap2-timer";
519 reg = <0x48086000 0x80>;
520 interrupts = <0 46 0x4>;
521 ti,hwmods = "timer10";
522 ti,timer-pwm;
523 };
524
525 timer11: timer@48088000 {
526 compatible = "ti,omap2-timer";
527 reg = <0x48088000 0x80>;
528 interrupts = <0 47 0x4>;
529 ti,hwmods = "timer11";
530 ti,timer-pwm;
531 };
532 };
533};
diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
deleted file mode 100644
index 8722c15bbba..00000000000
--- a/arch/arm/boot/dts/omap5-evm.dts
+++ /dev/null
@@ -1,153 +0,0 @@
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10/include/ "omap5.dtsi"
11/include/ "samsung_k3pe0e000b.dtsi"
12
13/ {
14 model = "TI OMAP5 EVM board";
15 compatible = "ti,omap5-evm", "ti,omap5";
16
17 memory {
18 device_type = "memory";
19 reg = <0x80000000 0x80000000>; /* 2 GB */
20 };
21
22 vmmcsd_fixed: fixedregulator-mmcsd {
23 compatible = "regulator-fixed";
24 regulator-name = "vmmcsd_fixed";
25 regulator-min-microvolt = <3000000>;
26 regulator-max-microvolt = <3000000>;
27 };
28
29};
30
31&omap5_pmx_core {
32 pinctrl-names = "default";
33 pinctrl-0 = <
34 &twl6040_pins
35 &mcpdm_pins
36 &dmic_pins
37 &mcbsp1_pins
38 &mcbsp2_pins
39 >;
40
41 twl6040_pins: pinmux_twl6040_pins {
42 pinctrl-single,pins = <
43 0x18a 0x6 /* perslimbus2_clock.gpio5_145 OUTPUT | MODE6 */
44 >;
45 };
46
47 mcpdm_pins: pinmux_mcpdm_pins {
48 pinctrl-single,pins = <
49 0x142 0x108 /* abe_clks.abe_clks INPUT PULLDOWN | MODE0 */
50 0x15c 0x108 /* abemcpdm_ul_data.abemcpdm_ul_data INPUT PULLDOWN | MODE0 */
51 0x15e 0x108 /* abemcpdm_dl_data.abemcpdm_dl_data INPUT PULLDOWN | MODE0 */
52 0x160 0x118 /* abemcpdm_frame.abemcpdm_frame INPUT PULLUP | MODE0 */
53 0x162 0x108 /* abemcpdm_lb_clk.abemcpdm_lb_clk INPUT PULLDOWN | MODE0 */
54 >;
55 };
56
57 dmic_pins: pinmux_dmic_pins {
58 pinctrl-single,pins = <
59 0x144 0x100 /* abedmic_din1.abedmic_din1 INPUT | MODE0 */
60 0x146 0x100 /* abedmic_din2.abedmic_din2 INPUT | MODE0 */
61 0x148 0x100 /* abedmic_din3.abedmic_din3 INPUT | MODE0 */
62 0x14a 0 /* abedmic_clk1.abedmic_clk1 OUTPUT | MODE0 */
63 >;
64 };
65
66 mcbsp1_pins: pinmux_mcbsp1_pins {
67 pinctrl-single,pins = <
68 0x14c 0x101 /* abedmic_clk2.abemcbsp1_fsx INPUT | MODE1 */
69 0x14e 0x9 /* abedmic_clk3.abemcbsp1_dx OUTPUT PULLDOWN | MODE1 */
70 0x150 0x101 /* abeslimbus1_clock.abemcbsp1_clkx INPUT | MODE0 */
71 0x152 0x109 /* abeslimbus1_data.abemcbsp1_dr INPUT PULLDOWN | MODE1 */
72 >;
73 };
74
75 mcbsp2_pins: pinmux_mcbsp2_pins {
76 pinctrl-single,pins = <
77 0x154 0x108 /* abemcbsp2_dr.abemcbsp2_dr INPUT PULLDOWN | MODE0 */
78 0x156 0x8 /* abemcbsp2_dx.abemcbsp2_dx OUTPUT PULLDOWN | MODE0 */
79 0x158 0x100 /* abemcbsp2_fsx.abemcbsp2_fsx INPUT | MODE0 */
80 0x15a 0x100 /* abemcbsp2_clkx.abemcbsp2_clkx INPUT | MODE0 */
81 >;
82 };
83};
84
85&mmc1 {
86 vmmc-supply = <&vmmcsd_fixed>;
87 bus-width = <4>;
88};
89
90&mmc2 {
91 vmmc-supply = <&vmmcsd_fixed>;
92 bus-width = <8>;
93 ti,non-removable;
94};
95
96&mmc3 {
97 bus-width = <4>;
98 ti,non-removable;
99};
100
101&mmc4 {
102 status = "disabled";
103};
104
105&mmc5 {
106 status = "disabled";
107};
108
109&i2c2 {
110 clock-frequency = <400000>;
111
112 /* Pressure Sensor */
113 bmp085@77 {
114 compatible = "bosch,bmp085";
115 reg = <0x77>;
116 };
117};
118
119&i2c4 {
120 clock-frequency = <400000>;
121
122 /* Temperature Sensor */
123 tmp102@48{
124 compatible = "ti,tmp102";
125 reg = <0x48>;
126 };
127};
128
129&keypad {
130 keypad,num-rows = <8>;
131 keypad,num-columns = <8>;
132 linux,keymap = <0x02020073 /* VOLUP */
133 0x02030072 /* VOLDOWM */
134 0x020400e7 /* SEND */
135 0x02050066 /* HOME */
136 0x0206006b /* END */
137 0x020700d9>; /* SEARCH */
138 linux,input-no-autorepeat;
139};
140
141&mcbsp3 {
142 status = "disabled";
143};
144
145&emif1 {
146 cs1-used;
147 device-handle = <&samsung_K3PE0E000B>;
148};
149
150&emif2 {
151 cs1-used;
152 device-handle = <&samsung_K3PE0E000B>;
153};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
deleted file mode 100644
index 790bb2a4b34..00000000000
--- a/arch/arm/boot/dts/omap5.dtsi
+++ /dev/null
@@ -1,500 +0,0 @@
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
10/*
11 * Carveout for multimedia usecases
12 * It should be the last 48MB of the first 512MB memory part
13 * In theory, it should not even exist. That zone should be reserved
14 * dynamically during the .reserve callback.
15 */
16/memreserve/ 0x9d000000 0x03000000;
17
18/include/ "skeleton.dtsi"
19
20/ {
21 compatible = "ti,omap5";
22 interrupt-parent = <&gic>;
23
24 aliases {
25 serial0 = &uart1;
26 serial1 = &uart2;
27 serial2 = &uart3;
28 serial3 = &uart4;
29 serial4 = &uart5;
30 serial5 = &uart6;
31 };
32
33 cpus {
34 cpu@0 {
35 compatible = "arm,cortex-a15";
36 timer {
37 compatible = "arm,armv7-timer";
38 /* 14th PPI IRQ, active low level-sensitive */
39 interrupts = <1 14 0x308>;
40 clock-frequency = <6144000>;
41 };
42 };
43 cpu@1 {
44 compatible = "arm,cortex-a15";
45 timer {
46 compatible = "arm,armv7-timer";
47 /* 14th PPI IRQ, active low level-sensitive */
48 interrupts = <1 14 0x308>;
49 clock-frequency = <6144000>;
50 };
51 };
52 };
53
54 /*
55 * The soc node represents the soc top level view. It is uses for IPs
56 * that are not memory mapped in the MPU view or for the MPU itself.
57 */
58 soc {
59 compatible = "ti,omap-infra";
60 mpu {
61 compatible = "ti,omap5-mpu";
62 ti,hwmods = "mpu";
63 };
64 };
65
66 /*
67 * XXX: Use a flat representation of the OMAP3 interconnect.
68 * The real OMAP interconnect network is quite complex.
69 * Since that will not bring real advantage to represent that in DT for
70 * the moment, just use a fake OCP bus entry to represent the whole bus
71 * hierarchy.
72 */
73 ocp {
74 compatible = "ti,omap4-l3-noc", "simple-bus";
75 #address-cells = <1>;
76 #size-cells = <1>;
77 ranges;
78 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
79
80 counter32k: counter@4ae04000 {
81 compatible = "ti,omap-counter32k";
82 reg = <0x4ae04000 0x40>;
83 ti,hwmods = "counter_32k";
84 };
85
86 omap5_pmx_core: pinmux@4a002840 {
87 compatible = "ti,omap4-padconf", "pinctrl-single";
88 reg = <0x4a002840 0x01b6>;
89 #address-cells = <1>;
90 #size-cells = <0>;
91 pinctrl-single,register-width = <16>;
92 pinctrl-single,function-mask = <0x7fff>;
93 };
94 omap5_pmx_wkup: pinmux@4ae0c840 {
95 compatible = "ti,omap4-padconf", "pinctrl-single";
96 reg = <0x4ae0c840 0x0038>;
97 #address-cells = <1>;
98 #size-cells = <0>;
99 pinctrl-single,register-width = <16>;
100 pinctrl-single,function-mask = <0x7fff>;
101 };
102
103 gic: interrupt-controller@48211000 {
104 compatible = "arm,cortex-a15-gic";
105 interrupt-controller;
106 #interrupt-cells = <3>;
107 reg = <0x48211000 0x1000>,
108 <0x48212000 0x1000>;
109 };
110
111 gpio1: gpio@4ae10000 {
112 compatible = "ti,omap4-gpio";
113 reg = <0x4ae10000 0x200>;
114 interrupts = <0 29 0x4>;
115 ti,hwmods = "gpio1";
116 gpio-controller;
117 #gpio-cells = <2>;
118 interrupt-controller;
119 #interrupt-cells = <1>;
120 };
121
122 gpio2: gpio@48055000 {
123 compatible = "ti,omap4-gpio";
124 reg = <0x48055000 0x200>;
125 interrupts = <0 30 0x4>;
126 ti,hwmods = "gpio2";
127 gpio-controller;
128 #gpio-cells = <2>;
129 interrupt-controller;
130 #interrupt-cells = <1>;
131 };
132
133 gpio3: gpio@48057000 {
134 compatible = "ti,omap4-gpio";
135 reg = <0x48057000 0x200>;
136 interrupts = <0 31 0x4>;
137 ti,hwmods = "gpio3";
138 gpio-controller;
139 #gpio-cells = <2>;
140 interrupt-controller;
141 #interrupt-cells = <1>;
142 };
143
144 gpio4: gpio@48059000 {
145 compatible = "ti,omap4-gpio";
146 reg = <0x48059000 0x200>;
147 interrupts = <0 32 0x4>;
148 ti,hwmods = "gpio4";
149 gpio-controller;
150 #gpio-cells = <2>;
151 interrupt-controller;
152 #interrupt-cells = <1>;
153 };
154
155 gpio5: gpio@4805b000 {
156 compatible = "ti,omap4-gpio";
157 reg = <0x4805b000 0x200>;
158 interrupts = <0 33 0x4>;
159 ti,hwmods = "gpio5";
160 gpio-controller;
161 #gpio-cells = <2>;
162 interrupt-controller;
163 #interrupt-cells = <1>;
164 };
165
166 gpio6: gpio@4805d000 {
167 compatible = "ti,omap4-gpio";
168 reg = <0x4805d000 0x200>;
169 interrupts = <0 34 0x4>;
170 ti,hwmods = "gpio6";
171 gpio-controller;
172 #gpio-cells = <2>;
173 interrupt-controller;
174 #interrupt-cells = <1>;
175 };
176
177 gpio7: gpio@48051000 {
178 compatible = "ti,omap4-gpio";
179 reg = <0x48051000 0x200>;
180 interrupts = <0 35 0x4>;
181 ti,hwmods = "gpio7";
182 gpio-controller;
183 #gpio-cells = <2>;
184 interrupt-controller;
185 #interrupt-cells = <1>;
186 };
187
188 gpio8: gpio@48053000 {
189 compatible = "ti,omap4-gpio";
190 reg = <0x48053000 0x200>;
191 interrupts = <0 121 0x4>;
192 ti,hwmods = "gpio8";
193 gpio-controller;
194 #gpio-cells = <2>;
195 interrupt-controller;
196 #interrupt-cells = <1>;
197 };
198
199 i2c1: i2c@48070000 {
200 compatible = "ti,omap4-i2c";
201 reg = <0x48070000 0x100>;
202 interrupts = <0 56 0x4>;
203 #address-cells = <1>;
204 #size-cells = <0>;
205 ti,hwmods = "i2c1";
206 };
207
208 i2c2: i2c@48072000 {
209 compatible = "ti,omap4-i2c";
210 reg = <0x48072000 0x100>;
211 interrupts = <0 57 0x4>;
212 #address-cells = <1>;
213 #size-cells = <0>;
214 ti,hwmods = "i2c2";
215 };
216
217 i2c3: i2c@48060000 {
218 compatible = "ti,omap4-i2c";
219 reg = <0x48060000 0x100>;
220 interrupts = <0 61 0x4>;
221 #address-cells = <1>;
222 #size-cells = <0>;
223 ti,hwmods = "i2c3";
224 };
225
226 i2c4: i2c@4807a000 {
227 compatible = "ti,omap4-i2c";
228 reg = <0x4807a000 0x100>;
229 interrupts = <0 62 0x4>;
230 #address-cells = <1>;
231 #size-cells = <0>;
232 ti,hwmods = "i2c4";
233 };
234
235 i2c5: i2c@4807c000 {
236 compatible = "ti,omap4-i2c";
237 reg = <0x4807c000 0x100>;
238 interrupts = <0 60 0x4>;
239 #address-cells = <1>;
240 #size-cells = <0>;
241 ti,hwmods = "i2c5";
242 };
243
244 uart1: serial@4806a000 {
245 compatible = "ti,omap4-uart";
246 reg = <0x4806a000 0x100>;
247 interrupts = <0 72 0x4>;
248 ti,hwmods = "uart1";
249 clock-frequency = <48000000>;
250 };
251
252 uart2: serial@4806c000 {
253 compatible = "ti,omap4-uart";
254 reg = <0x4806c000 0x100>;
255 interrupts = <0 73 0x4>;
256 ti,hwmods = "uart2";
257 clock-frequency = <48000000>;
258 };
259
260 uart3: serial@48020000 {
261 compatible = "ti,omap4-uart";
262 reg = <0x48020000 0x100>;
263 interrupts = <0 74 0x4>;
264 ti,hwmods = "uart3";
265 clock-frequency = <48000000>;
266 };
267
268 uart4: serial@4806e000 {
269 compatible = "ti,omap4-uart";
270 reg = <0x4806e000 0x100>;
271 interrupts = <0 70 0x4>;
272 ti,hwmods = "uart4";
273 clock-frequency = <48000000>;
274 };
275
276 uart5: serial@48066000 {
277 compatible = "ti,omap4-uart";
278 reg = <0x48066000 0x100>;
279 interrupts = <0 105 0x4>;
280 ti,hwmods = "uart5";
281 clock-frequency = <48000000>;
282 };
283
284 uart6: serial@48068000 {
285 compatible = "ti,omap4-uart";
286 reg = <0x48068000 0x100>;
287 interrupts = <0 106 0x4>;
288 ti,hwmods = "uart6";
289 clock-frequency = <48000000>;
290 };
291
292 mmc1: mmc@4809c000 {
293 compatible = "ti,omap4-hsmmc";
294 reg = <0x4809c000 0x400>;
295 interrupts = <0 83 0x4>;
296 ti,hwmods = "mmc1";
297 ti,dual-volt;
298 ti,needs-special-reset;
299 };
300
301 mmc2: mmc@480b4000 {
302 compatible = "ti,omap4-hsmmc";
303 reg = <0x480b4000 0x400>;
304 interrupts = <0 86 0x4>;
305 ti,hwmods = "mmc2";
306 ti,needs-special-reset;
307 };
308
309 mmc3: mmc@480ad000 {
310 compatible = "ti,omap4-hsmmc";
311 reg = <0x480ad000 0x400>;
312 interrupts = <0 94 0x4>;
313 ti,hwmods = "mmc3";
314 ti,needs-special-reset;
315 };
316
317 mmc4: mmc@480d1000 {
318 compatible = "ti,omap4-hsmmc";
319 reg = <0x480d1000 0x400>;
320 interrupts = <0 96 0x4>;
321 ti,hwmods = "mmc4";
322 ti,needs-special-reset;
323 };
324
325 mmc5: mmc@480d5000 {
326 compatible = "ti,omap4-hsmmc";
327 reg = <0x480d5000 0x400>;
328 interrupts = <0 59 0x4>;
329 ti,hwmods = "mmc5";
330 ti,needs-special-reset;
331 };
332
333 keypad: keypad@4ae1c000 {
334 compatible = "ti,omap4-keypad";
335 ti,hwmods = "kbd";
336 };
337
338 mcpdm: mcpdm@40132000 {
339 compatible = "ti,omap4-mcpdm";
340 reg = <0x40132000 0x7f>, /* MPU private access */
341 <0x49032000 0x7f>; /* L3 Interconnect */
342 reg-names = "mpu", "dma";
343 interrupts = <0 112 0x4>;
344 ti,hwmods = "mcpdm";
345 };
346
347 dmic: dmic@4012e000 {
348 compatible = "ti,omap4-dmic";
349 reg = <0x4012e000 0x7f>, /* MPU private access */
350 <0x4902e000 0x7f>; /* L3 Interconnect */
351 reg-names = "mpu", "dma";
352 interrupts = <0 114 0x4>;
353 ti,hwmods = "dmic";
354 };
355
356 mcbsp1: mcbsp@40122000 {
357 compatible = "ti,omap4-mcbsp";
358 reg = <0x40122000 0xff>, /* MPU private access */
359 <0x49022000 0xff>; /* L3 Interconnect */
360 reg-names = "mpu", "dma";
361 interrupts = <0 17 0x4>;
362 interrupt-names = "common";
363 ti,buffer-size = <128>;
364 ti,hwmods = "mcbsp1";
365 };
366
367 mcbsp2: mcbsp@40124000 {
368 compatible = "ti,omap4-mcbsp";
369 reg = <0x40124000 0xff>, /* MPU private access */
370 <0x49024000 0xff>; /* L3 Interconnect */
371 reg-names = "mpu", "dma";
372 interrupts = <0 22 0x4>;
373 interrupt-names = "common";
374 ti,buffer-size = <128>;
375 ti,hwmods = "mcbsp2";
376 };
377
378 mcbsp3: mcbsp@40126000 {
379 compatible = "ti,omap4-mcbsp";
380 reg = <0x40126000 0xff>, /* MPU private access */
381 <0x49026000 0xff>; /* L3 Interconnect */
382 reg-names = "mpu", "dma";
383 interrupts = <0 23 0x4>;
384 interrupt-names = "common";
385 ti,buffer-size = <128>;
386 ti,hwmods = "mcbsp3";
387 };
388
389 timer1: timer@4ae18000 {
390 compatible = "ti,omap2-timer";
391 reg = <0x4ae18000 0x80>;
392 interrupts = <0 37 0x4>;
393 ti,hwmods = "timer1";
394 ti,timer-alwon;
395 };
396
397 timer2: timer@48032000 {
398 compatible = "ti,omap2-timer";
399 reg = <0x48032000 0x80>;
400 interrupts = <0 38 0x4>;
401 ti,hwmods = "timer2";
402 };
403
404 timer3: timer@48034000 {
405 compatible = "ti,omap2-timer";
406 reg = <0x48034000 0x80>;
407 interrupts = <0 39 0x4>;
408 ti,hwmods = "timer3";
409 };
410
411 timer4: timer@48036000 {
412 compatible = "ti,omap2-timer";
413 reg = <0x48036000 0x80>;
414 interrupts = <0 40 0x4>;
415 ti,hwmods = "timer4";
416 };
417
418 timer5: timer@40138000 {
419 compatible = "ti,omap2-timer";
420 reg = <0x40138000 0x80>,
421 <0x49038000 0x80>;
422 interrupts = <0 41 0x4>;
423 ti,hwmods = "timer5";
424 ti,timer-dsp;
425 };
426
427 timer6: timer@4013a000 {
428 compatible = "ti,omap2-timer";
429 reg = <0x4013a000 0x80>,
430 <0x4903a000 0x80>;
431 interrupts = <0 42 0x4>;
432 ti,hwmods = "timer6";
433 ti,timer-dsp;
434 ti,timer-pwm;
435 };
436
437 timer7: timer@4013c000 {
438 compatible = "ti,omap2-timer";
439 reg = <0x4013c000 0x80>,
440 <0x4903c000 0x80>;
441 interrupts = <0 43 0x4>;
442 ti,hwmods = "timer7";
443 ti,timer-dsp;
444 };
445
446 timer8: timer@4013e000 {
447 compatible = "ti,omap2-timer";
448 reg = <0x4013e000 0x80>,
449 <0x4903e000 0x80>;
450 interrupts = <0 44 0x4>;
451 ti,hwmods = "timer8";
452 ti,timer-dsp;
453 ti,timer-pwm;
454 };
455
456 timer9: timer@4803e000 {
457 compatible = "ti,omap2-timer";
458 reg = <0x4803e000 0x80>;
459 interrupts = <0 45 0x4>;
460 ti,hwmods = "timer9";
461 };
462
463 timer10: timer@48086000 {
464 compatible = "ti,omap2-timer";
465 reg = <0x48086000 0x80>;
466 interrupts = <0 46 0x4>;
467 ti,hwmods = "timer10";
468 };
469
470 timer11: timer@48088000 {
471 compatible = "ti,omap2-timer";
472 reg = <0x48088000 0x80>;
473 interrupts = <0 47 0x4>;
474 ti,hwmods = "timer11";
475 ti,timer-pwm;
476 };
477
478 emif1: emif@0x4c000000 {
479 compatible = "ti,emif-4d5";
480 ti,hwmods = "emif1";
481 phy-type = <2>; /* DDR PHY type: Intelli PHY */
482 reg = <0x4c000000 0x400>;
483 interrupts = <0 110 0x4>;
484 hw-caps-read-idle-ctrl;
485 hw-caps-ll-interface;
486 hw-caps-temp-alert;
487 };
488
489 emif2: emif@0x4d000000 {
490 compatible = "ti,emif-4d5";
491 ti,hwmods = "emif2";
492 phy-type = <2>; /* DDR PHY type: Intelli PHY */
493 reg = <0x4d000000 0x400>;
494 interrupts = <0 111 0x4>;
495 hw-caps-read-idle-ctrl;
496 hw-caps-ll-interface;
497 hw-caps-temp-alert;
498 };
499 };
500};
diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
deleted file mode 100644
index 5a3a58b7e18..00000000000
--- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
+++ /dev/null
@@ -1,55 +0,0 @@
1/*
2 * Copyright (C) 2012 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9/dts-v1/;
10/include/ "orion5x.dtsi"
11
12/ {
13 model = "LaCie Ethernet Disk mini V2";
14 compatible = "lacie,ethernet-disk-mini-v2", "marvell-orion5x-88f5182", "marvell,orion5x";
15
16 memory {
17 reg = <0x00000000 0x4000000>; /* 64 MB */
18 };
19
20 chosen {
21 bootargs = "console=ttyS0,115200n8 earlyprintk";
22 };
23
24 ocp@f1000000 {
25 serial@12000 {
26 clock-frequency = <166666667>;
27 status = "okay";
28 };
29
30 sata@80000 {
31 status = "okay";
32 nr-ports = <2>;
33 };
34 };
35
36 gpio_keys {
37 compatible = "gpio-keys";
38 #address-cells = <1>;
39 #size-cells = <0>;
40 button@1 {
41 label = "Power-on Switch";
42 linux,code = <116>; /* KEY_POWER */
43 gpios = <&gpio0 18 0>;
44 };
45 };
46
47 gpio_leds {
48 compatible = "gpio-leds";
49
50 led@1 {
51 label = "power:blue";
52 gpios = <&gpio0 16 1>;
53 };
54 };
55};
diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
deleted file mode 100644
index 8aad00f81ed..00000000000
--- a/arch/arm/boot/dts/orion5x.dtsi
+++ /dev/null
@@ -1,98 +0,0 @@
1/*
2 * Copyright (C) 2012 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9/include/ "skeleton.dtsi"
10
11/ {
12 model = "Marvell Orion5x SoC";
13 compatible = "marvell,orion5x";
14 interrupt-parent = <&intc>;
15
16 intc: interrupt-controller {
17 compatible = "marvell,orion-intc", "marvell,intc";
18 interrupt-controller;
19 #interrupt-cells = <1>;
20 reg = <0xf1020204 0x04>;
21 };
22
23 ocp@f1000000 {
24 compatible = "simple-bus";
25 ranges = <0x00000000 0xf1000000 0x4000000
26 0xf2200000 0xf2200000 0x0000800>;
27 #address-cells = <1>;
28 #size-cells = <1>;
29
30 gpio0: gpio@10100 {
31 compatible = "marvell,orion-gpio";
32 #gpio-cells = <2>;
33 gpio-controller;
34 reg = <0x10100 0x40>;
35 ngpio = <32>;
36 interrupts = <6>, <7>, <8>, <9>;
37 };
38
39 serial@12000 {
40 compatible = "ns16550a";
41 reg = <0x12000 0x100>;
42 reg-shift = <2>;
43 interrupts = <3>;
44 /* set clock-frequency in board dts */
45 status = "disabled";
46 };
47
48 serial@12100 {
49 compatible = "ns16550a";
50 reg = <0x12100 0x100>;
51 reg-shift = <2>;
52 interrupts = <4>;
53 /* set clock-frequency in board dts */
54 status = "disabled";
55 };
56
57 spi@10600 {
58 compatible = "marvell,orion-spi";
59 #address-cells = <1>;
60 #size-cells = <0>;
61 cell-index = <0>;
62 reg = <0x10600 0x28>;
63 status = "disabled";
64 };
65
66 wdt@20300 {
67 compatible = "marvell,orion-wdt";
68 reg = <0x20300 0x28>;
69 status = "okay";
70 };
71
72 sata@80000 {
73 compatible = "marvell,orion-sata";
74 reg = <0x80000 0x5000>;
75 interrupts = <29>;
76 status = "disabled";
77 };
78
79 i2c@11000 {
80 compatible = "marvell,mv64xxx-i2c";
81 reg = <0x11000 0x20>;
82 #address-cells = <1>;
83 #size-cells = <0>;
84 interrupts = <5>;
85 clock-frequency = <100000>;
86 status = "disabled";
87 };
88
89 crypto@90000 {
90 compatible = "marvell,orion-crypto";
91 reg = <0x90000 0x10000>,
92 <0xf2200000 0x800>;
93 reg-names = "regs", "sram";
94 interrupts = <22>;
95 status = "okay";
96 };
97 };
98};
diff --git a/arch/arm/boot/dts/phy3250.dts b/arch/arm/boot/dts/phy3250.dts
deleted file mode 100644
index 90fdbd77f27..00000000000
--- a/arch/arm/boot/dts/phy3250.dts
+++ /dev/null
@@ -1,202 +0,0 @@
1/*
2 * PHYTEC phyCORE-LPC3250 board
3 *
4 * Copyright 2012 Roland Stigge <stigge@antcom.de>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "lpc32xx.dtsi"
16
17/ {
18 model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250";
19 compatible = "phytec,phy3250", "nxp,lpc3250";
20 #address-cells = <1>;
21 #size-cells = <1>;
22
23 memory {
24 device_type = "memory";
25 reg = <0 0x4000000>;
26 };
27
28 ahb {
29 mac: ethernet@31060000 {
30 phy-mode = "rmii";
31 use-iram;
32 };
33
34 /* Here, choose exactly one from: ohci, usbd */
35 ohci@31020000 {
36 transceiver = <&isp1301>;
37 status = "okay";
38 };
39
40/*
41 usbd@31020000 {
42 transceiver = <&isp1301>;
43 status = "okay";
44 };
45*/
46
47 clcd@31040000 {
48 status = "okay";
49 };
50
51 /* 64MB Flash via SLC NAND controller */
52 slc: flash@20020000 {
53 status = "okay";
54 #address-cells = <1>;
55 #size-cells = <1>;
56
57 nxp,wdr-clks = <14>;
58 nxp,wwidth = <40000000>;
59 nxp,whold = <100000000>;
60 nxp,wsetup = <100000000>;
61 nxp,rdr-clks = <14>;
62 nxp,rwidth = <40000000>;
63 nxp,rhold = <66666666>;
64 nxp,rsetup = <100000000>;
65 nand-on-flash-bbt;
66 gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
67
68 mtd0@00000000 {
69 label = "phy3250-boot";
70 reg = <0x00000000 0x00064000>;
71 read-only;
72 };
73
74 mtd1@00064000 {
75 label = "phy3250-uboot";
76 reg = <0x00064000 0x00190000>;
77 read-only;
78 };
79
80 mtd2@001f4000 {
81 label = "phy3250-ubt-prms";
82 reg = <0x001f4000 0x00010000>;
83 };
84
85 mtd3@00204000 {
86 label = "phy3250-kernel";
87 reg = <0x00204000 0x00400000>;
88 };
89
90 mtd4@00604000 {
91 label = "phy3250-rootfs";
92 reg = <0x00604000 0x039fc000>;
93 };
94 };
95
96 apb {
97 uart5: serial@40090000 {
98 status = "okay";
99 };
100
101 uart3: serial@40080000 {
102 status = "okay";
103 };
104
105 i2c1: i2c@400A0000 {
106 clock-frequency = <100000>;
107
108 pcf8563: rtc@51 {
109 compatible = "nxp,pcf8563";
110 reg = <0x51>;
111 };
112
113 uda1380: uda1380@18 {
114 compatible = "nxp,uda1380";
115 reg = <0x18>;
116 power-gpio = <&gpio 0x59 0>;
117 reset-gpio = <&gpio 0x51 0>;
118 dac-clk = "wspll";
119 };
120 };
121
122 i2c2: i2c@400A8000 {
123 clock-frequency = <100000>;
124 };
125
126 i2cusb: i2c@31020300 {
127 clock-frequency = <100000>;
128
129 isp1301: usb-transceiver@2c {
130 compatible = "nxp,isp1301";
131 reg = <0x2c>;
132 };
133 };
134
135 ssp0: ssp@20084000 {
136 #address-cells = <1>;
137 #size-cells = <0>;
138 num-cs = <1>;
139 cs-gpios = <&gpio 3 5 0>;
140
141 eeprom: at25@0 {
142 pl022,interface = <0>;
143 pl022,com-mode = <0>;
144 pl022,rx-level-trig = <1>;
145 pl022,tx-level-trig = <1>;
146 pl022,ctrl-len = <11>;
147 pl022,wait-state = <0>;
148 pl022,duplex = <0>;
149
150 at25,byte-len = <0x8000>;
151 at25,addr-mode = <2>;
152 at25,page-size = <64>;
153
154 compatible = "atmel,at25";
155 reg = <0>;
156 spi-max-frequency = <5000000>;
157 };
158 };
159
160 sd@20098000 {
161 wp-gpios = <&gpio 3 0 0>;
162 cd-gpios = <&gpio 3 1 0>;
163 cd-inverted;
164 bus-width = <4>;
165 status = "okay";
166 };
167 };
168
169 fab {
170 uart2: serial@40018000 {
171 status = "okay";
172 };
173
174 tsc@40048000 {
175 status = "okay";
176 };
177
178 key@40050000 {
179 status = "okay";
180 keypad,num-rows = <1>;
181 keypad,num-columns = <1>;
182 nxp,debounce-delay-ms = <3>;
183 nxp,scan-delay-ms = <34>;
184 linux,keymap = <0x00000002>;
185 };
186 };
187 };
188
189 leds {
190 compatible = "gpio-leds";
191
192 led0 { /* red */
193 gpios = <&gpio 5 1 0>; /* GPO_P3 1, GPIO 80, active high */
194 default-state = "off";
195 };
196
197 led1 { /* green */
198 gpios = <&gpio 5 14 0>; /* GPO_P3 14, GPIO 93, active high */
199 linux,default-trigger = "heartbeat";
200 };
201 };
202};
diff --git a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
deleted file mode 100644
index f0a8c2068ea..00000000000
--- a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
+++ /dev/null
@@ -1,249 +0,0 @@
1/*
2 * Copyright (C) 2011 Picochip, Jamie Iles
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13/include/ "skeleton.dtsi"
14/ {
15 model = "Picochip picoXcell PC3X2";
16 compatible = "picochip,pc3x2";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 cpus {
21 #address-cells = <1>;
22 #size-cells = <0>;
23
24 cpu@0 {
25 compatible = "arm,1176jz-s";
26 clock-frequency = <400000000>;
27 reg = <0>;
28 d-cache-line-size = <32>;
29 d-cache-size = <32768>;
30 i-cache-line-size = <32>;
31 i-cache-size = <32768>;
32 };
33 };
34
35 clocks {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 ranges;
39
40 pclk: clock@0 {
41 compatible = "fixed-clock";
42 clock-outputs = "bus", "pclk";
43 clock-frequency = <200000000>;
44 ref-clock = <&ref_clk>, "ref";
45 };
46 };
47
48 paxi {
49 compatible = "simple-bus";
50 #address-cells = <1>;
51 #size-cells = <1>;
52 ranges = <0 0x80000000 0x400000>;
53
54 emac: gem@30000 {
55 compatible = "cadence,gem";
56 reg = <0x30000 0x10000>;
57 interrupts = <31>;
58 };
59
60 dmac1: dmac@40000 {
61 compatible = "snps,dw-dmac";
62 reg = <0x40000 0x10000>;
63 interrupts = <25>;
64 };
65
66 dmac2: dmac@50000 {
67 compatible = "snps,dw-dmac";
68 reg = <0x50000 0x10000>;
69 interrupts = <26>;
70 };
71
72 vic0: interrupt-controller@60000 {
73 compatible = "arm,pl192-vic";
74 interrupt-controller;
75 reg = <0x60000 0x1000>;
76 #interrupt-cells = <1>;
77 };
78
79 vic1: interrupt-controller@64000 {
80 compatible = "arm,pl192-vic";
81 interrupt-controller;
82 reg = <0x64000 0x1000>;
83 #interrupt-cells = <1>;
84 };
85
86 fuse: picoxcell-fuse@80000 {
87 compatible = "picoxcell,fuse-pc3x2";
88 reg = <0x80000 0x10000>;
89 };
90
91 ssi: picoxcell-spi@90000 {
92 compatible = "picoxcell,spi";
93 reg = <0x90000 0x10000>;
94 interrupt-parent = <&vic0>;
95 interrupts = <10>;
96 };
97
98 ipsec: spacc@100000 {
99 compatible = "picochip,spacc-ipsec";
100 reg = <0x100000 0x10000>;
101 interrupt-parent = <&vic0>;
102 interrupts = <24>;
103 ref-clock = <&pclk>, "ref";
104 };
105
106 srtp: spacc@140000 {
107 compatible = "picochip,spacc-srtp";
108 reg = <0x140000 0x10000>;
109 interrupt-parent = <&vic0>;
110 interrupts = <23>;
111 };
112
113 l2_engine: spacc@180000 {
114 compatible = "picochip,spacc-l2";
115 reg = <0x180000 0x10000>;
116 interrupt-parent = <&vic0>;
117 interrupts = <22>;
118 ref-clock = <&pclk>, "ref";
119 };
120
121 apb {
122 compatible = "simple-bus";
123 #address-cells = <1>;
124 #size-cells = <1>;
125 ranges = <0 0x200000 0x80000>;
126
127 rtc0: rtc@00000 {
128 compatible = "picochip,pc3x2-rtc";
129 clock-freq = <200000000>;
130 reg = <0x00000 0xf>;
131 interrupt-parent = <&vic1>;
132 interrupts = <8>;
133 };
134
135 timer0: timer@10000 {
136 compatible = "picochip,pc3x2-timer";
137 interrupt-parent = <&vic0>;
138 interrupts = <4>;
139 clock-freq = <200000000>;
140 reg = <0x10000 0x14>;
141 };
142
143 timer1: timer@10014 {
144 compatible = "picochip,pc3x2-timer";
145 interrupt-parent = <&vic0>;
146 interrupts = <5>;
147 clock-freq = <200000000>;
148 reg = <0x10014 0x14>;
149 };
150
151 timer2: timer@10028 {
152 compatible = "picochip,pc3x2-timer";
153 interrupt-parent = <&vic0>;
154 interrupts = <6>;
155 clock-freq = <200000000>;
156 reg = <0x10028 0x14>;
157 };
158
159 timer3: timer@1003c {
160 compatible = "picochip,pc3x2-timer";
161 interrupt-parent = <&vic0>;
162 interrupts = <7>;
163 clock-freq = <200000000>;
164 reg = <0x1003c 0x14>;
165 };
166
167 gpio: gpio@20000 {
168 compatible = "snps,dw-apb-gpio";
169 reg = <0x20000 0x1000>;
170 #address-cells = <1>;
171 #size-cells = <0>;
172 reg-io-width = <4>;
173
174 banka: gpio-controller@0 {
175 compatible = "snps,dw-apb-gpio-bank";
176 gpio-controller;
177 #gpio-cells = <2>;
178 gpio-generic,nr-gpio = <8>;
179
180 regoffset-dat = <0x50>;
181 regoffset-set = <0x00>;
182 regoffset-dirout = <0x04>;
183 };
184
185 bankb: gpio-controller@1 {
186 compatible = "snps,dw-apb-gpio-bank";
187 gpio-controller;
188 #gpio-cells = <2>;
189 gpio-generic,nr-gpio = <8>;
190
191 regoffset-dat = <0x54>;
192 regoffset-set = <0x0c>;
193 regoffset-dirout = <0x10>;
194 };
195 };
196
197 uart0: uart@30000 {
198 compatible = "snps,dw-apb-uart";
199 reg = <0x30000 0x1000>;
200 interrupt-parent = <&vic1>;
201 interrupts = <10>;
202 clock-frequency = <3686400>;
203 reg-shift = <2>;
204 reg-io-width = <4>;
205 };
206
207 uart1: uart@40000 {
208 compatible = "snps,dw-apb-uart";
209 reg = <0x40000 0x1000>;
210 interrupt-parent = <&vic1>;
211 interrupts = <9>;
212 clock-frequency = <3686400>;
213 reg-shift = <2>;
214 reg-io-width = <4>;
215 };
216
217 wdog: watchdog@50000 {
218 compatible = "snps,dw-apb-wdg";
219 reg = <0x50000 0x10000>;
220 interrupt-parent = <&vic0>;
221 interrupts = <11>;
222 bus-clock = <&pclk>, "bus";
223 };
224 };
225 };
226
227 rwid-axi {
228 #address-cells = <1>;
229 #size-cells = <1>;
230 compatible = "simple-bus";
231 ranges;
232
233 ebi@50000000 {
234 compatible = "simple-bus";
235 #address-cells = <2>;
236 #size-cells = <1>;
237 ranges = <0 0 0x40000000 0x08000000
238 1 0 0x48000000 0x08000000
239 2 0 0x50000000 0x08000000
240 3 0 0x58000000 0x08000000>;
241 };
242
243 axi2pico@c0000000 {
244 compatible = "picochip,axi2pico-pc3x2";
245 reg = <0xc0000000 0x10000>;
246 interrupts = <13 14 15 16 17 18 19 20 21>;
247 };
248 };
249};
diff --git a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
deleted file mode 100644
index daa962d191e..00000000000
--- a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
+++ /dev/null
@@ -1,365 +0,0 @@
1/*
2 * Copyright (C) 2011 Picochip, Jamie Iles
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13/include/ "skeleton.dtsi"
14/ {
15 model = "Picochip picoXcell PC3X3";
16 compatible = "picochip,pc3x3";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 cpus {
21 #address-cells = <1>;
22 #size-cells = <0>;
23
24 cpu@0 {
25 compatible = "arm,1176jz-s";
26 cpu-clock = <&arm_clk>, "cpu";
27 reg = <0>;
28 d-cache-line-size = <32>;
29 d-cache-size = <32768>;
30 i-cache-line-size = <32>;
31 i-cache-size = <32768>;
32 };
33 };
34
35 clocks {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 ranges;
39
40 clkgate: clkgate@800a0048 {
41 #address-cells = <1>;
42 #size-cells = <0>;
43 reg = <0x800a0048 4>;
44 compatible = "picochip,pc3x3-clk-gate";
45
46 tzprot_clk: clock@0 {
47 compatible = "picochip,pc3x3-gated-clk";
48 clock-outputs = "bus";
49 picochip,clk-disable-bit = <0>;
50 clock-frequency = <200000000>;
51 ref-clock = <&ref_clk>, "ref";
52 };
53
54 spi_clk: clock@1 {
55 compatible = "picochip,pc3x3-gated-clk";
56 clock-outputs = "bus";
57 picochip,clk-disable-bit = <1>;
58 clock-frequency = <200000000>;
59 ref-clock = <&ref_clk>, "ref";
60 };
61
62 dmac0_clk: clock@2 {
63 compatible = "picochip,pc3x3-gated-clk";
64 clock-outputs = "bus";
65 picochip,clk-disable-bit = <2>;
66 clock-frequency = <200000000>;
67 ref-clock = <&ref_clk>, "ref";
68 };
69
70 dmac1_clk: clock@3 {
71 compatible = "picochip,pc3x3-gated-clk";
72 clock-outputs = "bus";
73 picochip,clk-disable-bit = <3>;
74 clock-frequency = <200000000>;
75 ref-clock = <&ref_clk>, "ref";
76 };
77
78 ebi_clk: clock@4 {
79 compatible = "picochip,pc3x3-gated-clk";
80 clock-outputs = "bus";
81 picochip,clk-disable-bit = <4>;
82 clock-frequency = <200000000>;
83 ref-clock = <&ref_clk>, "ref";
84 };
85
86 ipsec_clk: clock@5 {
87 compatible = "picochip,pc3x3-gated-clk";
88 clock-outputs = "bus";
89 picochip,clk-disable-bit = <5>;
90 clock-frequency = <200000000>;
91 ref-clock = <&ref_clk>, "ref";
92 };
93
94 l2_clk: clock@6 {
95 compatible = "picochip,pc3x3-gated-clk";
96 clock-outputs = "bus";
97 picochip,clk-disable-bit = <6>;
98 clock-frequency = <200000000>;
99 ref-clock = <&ref_clk>, "ref";
100 };
101
102 trng_clk: clock@7 {
103 compatible = "picochip,pc3x3-gated-clk";
104 clock-outputs = "bus";
105 picochip,clk-disable-bit = <7>;
106 clock-frequency = <200000000>;
107 ref-clock = <&ref_clk>, "ref";
108 };
109
110 fuse_clk: clock@8 {
111 compatible = "picochip,pc3x3-gated-clk";
112 clock-outputs = "bus";
113 picochip,clk-disable-bit = <8>;
114 clock-frequency = <200000000>;
115 ref-clock = <&ref_clk>, "ref";
116 };
117
118 otp_clk: clock@9 {
119 compatible = "picochip,pc3x3-gated-clk";
120 clock-outputs = "bus";
121 picochip,clk-disable-bit = <9>;
122 clock-frequency = <200000000>;
123 ref-clock = <&ref_clk>, "ref";
124 };
125 };
126
127 arm_clk: clock@11 {
128 compatible = "picochip,pc3x3-pll";
129 reg = <0x800a0050 0x8>;
130 picochip,min-freq = <140000000>;
131 picochip,max-freq = <700000000>;
132 ref-clock = <&ref_clk>, "ref";
133 clock-outputs = "cpu";
134 };
135
136 pclk: clock@12 {
137 compatible = "fixed-clock";
138 clock-outputs = "bus", "pclk";
139 clock-frequency = <200000000>;
140 ref-clock = <&ref_clk>, "ref";
141 };
142 };
143
144 paxi {
145 compatible = "simple-bus";
146 #address-cells = <1>;
147 #size-cells = <1>;
148 ranges = <0 0x80000000 0x400000>;
149
150 emac: gem@30000 {
151 compatible = "cadence,gem";
152 reg = <0x30000 0x10000>;
153 interrupt-parent = <&vic0>;
154 interrupts = <31>;
155 };
156
157 dmac1: dmac@40000 {
158 compatible = "snps,dw-dmac";
159 reg = <0x40000 0x10000>;
160 interrupt-parent = <&vic0>;
161 interrupts = <25>;
162 };
163
164 dmac2: dmac@50000 {
165 compatible = "snps,dw-dmac";
166 reg = <0x50000 0x10000>;
167 interrupt-parent = <&vic0>;
168 interrupts = <26>;
169 };
170
171 vic0: interrupt-controller@60000 {
172 compatible = "arm,pl192-vic";
173 interrupt-controller;
174 reg = <0x60000 0x1000>;
175 #interrupt-cells = <1>;
176 };
177
178 vic1: interrupt-controller@64000 {
179 compatible = "arm,pl192-vic";
180 interrupt-controller;
181 reg = <0x64000 0x1000>;
182 #interrupt-cells = <1>;
183 };
184
185 fuse: picoxcell-fuse@80000 {
186 compatible = "picoxcell,fuse-pc3x3";
187 reg = <0x80000 0x10000>;
188 };
189
190 ssi: picoxcell-spi@90000 {
191 compatible = "picoxcell,spi";
192 reg = <0x90000 0x10000>;
193 interrupt-parent = <&vic0>;
194 interrupts = <10>;
195 };
196
197 ipsec: spacc@100000 {
198 compatible = "picochip,spacc-ipsec";
199 reg = <0x100000 0x10000>;
200 interrupt-parent = <&vic0>;
201 interrupts = <24>;
202 ref-clock = <&ipsec_clk>, "ref";
203 };
204
205 srtp: spacc@140000 {
206 compatible = "picochip,spacc-srtp";
207 reg = <0x140000 0x10000>;
208 interrupt-parent = <&vic0>;
209 interrupts = <23>;
210 };
211
212 l2_engine: spacc@180000 {
213 compatible = "picochip,spacc-l2";
214 reg = <0x180000 0x10000>;
215 interrupt-parent = <&vic0>;
216 interrupts = <22>;
217 ref-clock = <&l2_clk>, "ref";
218 };
219
220 apb {
221 compatible = "simple-bus";
222 #address-cells = <1>;
223 #size-cells = <1>;
224 ranges = <0 0x200000 0x80000>;
225
226 rtc0: rtc@00000 {
227 compatible = "picochip,pc3x2-rtc";
228 clock-freq = <200000000>;
229 reg = <0x00000 0xf>;
230 interrupt-parent = <&vic0>;
231 interrupts = <8>;
232 };
233
234 timer0: timer@10000 {
235 compatible = "picochip,pc3x2-timer";
236 interrupt-parent = <&vic0>;
237 interrupts = <4>;
238 clock-freq = <200000000>;
239 reg = <0x10000 0x14>;
240 };
241
242 timer1: timer@10014 {
243 compatible = "picochip,pc3x2-timer";
244 interrupt-parent = <&vic0>;
245 interrupts = <5>;
246 clock-freq = <200000000>;
247 reg = <0x10014 0x14>;
248 };
249
250 gpio: gpio@20000 {
251 compatible = "snps,dw-apb-gpio";
252 reg = <0x20000 0x1000>;
253 #address-cells = <1>;
254 #size-cells = <0>;
255 reg-io-width = <4>;
256
257 banka: gpio-controller@0 {
258 compatible = "snps,dw-apb-gpio-bank";
259 gpio-controller;
260 #gpio-cells = <2>;
261 gpio-generic,nr-gpio = <8>;
262
263 regoffset-dat = <0x50>;
264 regoffset-set = <0x00>;
265 regoffset-dirout = <0x04>;
266 };
267
268 bankb: gpio-controller@1 {
269 compatible = "snps,dw-apb-gpio-bank";
270 gpio-controller;
271 #gpio-cells = <2>;
272 gpio-generic,nr-gpio = <16>;
273
274 regoffset-dat = <0x54>;
275 regoffset-set = <0x0c>;
276 regoffset-dirout = <0x10>;
277 };
278
279 bankd: gpio-controller@2 {
280 compatible = "snps,dw-apb-gpio-bank";
281 gpio-controller;
282 #gpio-cells = <2>;
283 gpio-generic,nr-gpio = <30>;
284
285 regoffset-dat = <0x5c>;
286 regoffset-set = <0x24>;
287 regoffset-dirout = <0x28>;
288 };
289 };
290
291 uart0: uart@30000 {
292 compatible = "snps,dw-apb-uart";
293 reg = <0x30000 0x1000>;
294 interrupt-parent = <&vic1>;
295 interrupts = <10>;
296 clock-frequency = <3686400>;
297 reg-shift = <2>;
298 reg-io-width = <4>;
299 };
300
301 uart1: uart@40000 {
302 compatible = "snps,dw-apb-uart";
303 reg = <0x40000 0x1000>;
304 interrupt-parent = <&vic1>;
305 interrupts = <9>;
306 clock-frequency = <3686400>;
307 reg-shift = <2>;
308 reg-io-width = <4>;
309 };
310
311 wdog: watchdog@50000 {
312 compatible = "snps,dw-apb-wdg";
313 reg = <0x50000 0x10000>;
314 interrupt-parent = <&vic0>;
315 interrupts = <11>;
316 bus-clock = <&pclk>, "bus";
317 };
318
319 timer2: timer@60000 {
320 compatible = "picochip,pc3x2-timer";
321 interrupt-parent = <&vic0>;
322 interrupts = <6>;
323 clock-freq = <200000000>;
324 reg = <0x60000 0x14>;
325 };
326
327 timer3: timer@60014 {
328 compatible = "picochip,pc3x2-timer";
329 interrupt-parent = <&vic0>;
330 interrupts = <7>;
331 clock-freq = <200000000>;
332 reg = <0x60014 0x14>;
333 };
334 };
335 };
336
337 rwid-axi {
338 #address-cells = <1>;
339 #size-cells = <1>;
340 compatible = "simple-bus";
341 ranges;
342
343 ebi@50000000 {
344 compatible = "simple-bus";
345 #address-cells = <2>;
346 #size-cells = <1>;
347 ranges = <0 0 0x40000000 0x08000000
348 1 0 0x48000000 0x08000000
349 2 0 0x50000000 0x08000000
350 3 0 0x58000000 0x08000000>;
351 };
352
353 axi2pico@c0000000 {
354 compatible = "picochip,axi2pico-pc3x3";
355 reg = <0xc0000000 0x10000>;
356 interrupt-parent = <&vic0>;
357 interrupts = <13 14 15 16 17 18 19 20 21>;
358 };
359
360 otp@ffff8000 {
361 compatible = "picochip,otp-pc3x3";
362 reg = <0xffff8000 0x8000>;
363 };
364 };
365};
diff --git a/arch/arm/boot/dts/picoxcell-pc7302-pc3x2.dts b/arch/arm/boot/dts/picoxcell-pc7302-pc3x2.dts
deleted file mode 100644
index 1297414dd64..00000000000
--- a/arch/arm/boot/dts/picoxcell-pc7302-pc3x2.dts
+++ /dev/null
@@ -1,86 +0,0 @@
1/*
2 * Copyright (C) 2011 Picochip, Jamie Iles
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14/dts-v1/;
15/include/ "picoxcell-pc3x2.dtsi"
16/ {
17 model = "Picochip PC7302 (PC3X2)";
18 compatible = "picochip,pc7302-pc3x2", "picochip,pc3x2";
19
20 memory {
21 device_type = "memory";
22 reg = <0x0 0x08000000>;
23 };
24
25 chosen {
26 linux,stdout-path = &uart0;
27 };
28
29 clocks {
30 ref_clk: clock@1 {
31 compatible = "fixed-clock";
32 clock-outputs = "ref";
33 clock-frequency = <20000000>;
34 };
35 };
36
37 rwid-axi {
38 ebi@50000000 {
39 nand: gpio-nand@2,0 {
40 compatible = "gpio-control-nand";
41 #address-cells = <1>;
42 #size-cells = <1>;
43 reg = <2 0x0000 0x1000>;
44 bus-clock = <&pclk>, "bus";
45 gpio-control-nand,io-sync-reg =
46 <0x00000000 0x80220000>;
47
48 gpios = <&banka 1 0 /* rdy */
49 &banka 2 0 /* nce */
50 &banka 3 0 /* ale */
51 &banka 4 0 /* cle */
52 0 /* nwp */>;
53
54 boot@100000 {
55 label = "Boot";
56 reg = <0x100000 0x80000>;
57 };
58
59 redundant-boot@200000 {
60 label = "Redundant Boot";
61 reg = <0x200000 0x80000>;
62 };
63
64 boot-env@300000 {
65 label = "Boot Evironment";
66 reg = <0x300000 0x20000>;
67 };
68
69 redundant-boot-env@320000 {
70 label = "Redundant Boot Environment";
71 reg = <0x300000 0x20000>;
72 };
73
74 kernel@380000 {
75 label = "Kernel";
76 reg = <0x380000 0x800000>;
77 };
78
79 fs@b80000 {
80 label = "File System";
81 reg = <0xb80000 0xf480000>;
82 };
83 };
84 };
85 };
86};
diff --git a/arch/arm/boot/dts/picoxcell-pc7302-pc3x3.dts b/arch/arm/boot/dts/picoxcell-pc7302-pc3x3.dts
deleted file mode 100644
index 9e317a4f431..00000000000
--- a/arch/arm/boot/dts/picoxcell-pc7302-pc3x3.dts
+++ /dev/null
@@ -1,92 +0,0 @@
1/*
2 * Copyright (C) 2011 Picochip, Jamie Iles
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14/dts-v1/;
15/include/ "picoxcell-pc3x3.dtsi"
16/ {
17 model = "Picochip PC7302 (PC3X3)";
18 compatible = "picochip,pc7302-pc3x3", "picochip,pc3x3";
19
20 memory {
21 device_type = "memory";
22 reg = <0x0 0x08000000>;
23 };
24
25 chosen {
26 linux,stdout-path = &uart0;
27 };
28
29 clocks {
30 ref_clk: clock@10 {
31 compatible = "fixed-clock";
32 clock-outputs = "ref";
33 clock-frequency = <20000000>;
34 };
35
36 clkgate: clkgate@800a0048 {
37 clock@4 {
38 picochip,clk-no-disable;
39 };
40 };
41 };
42
43 rwid-axi {
44 ebi@50000000 {
45 nand: gpio-nand@2,0 {
46 compatible = "gpio-control-nand";
47 #address-cells = <1>;
48 #size-cells = <1>;
49 reg = <2 0x0000 0x1000>;
50 bus-clock = <&ebi_clk>, "bus";
51 gpio-control-nand,io-sync-reg =
52 <0x00000000 0x80220000>;
53
54 gpios = <&banka 1 0 /* rdy */
55 &banka 2 0 /* nce */
56 &banka 3 0 /* ale */
57 &banka 4 0 /* cle */
58 0 /* nwp */>;
59
60 boot@100000 {
61 label = "Boot";
62 reg = <0x100000 0x80000>;
63 };
64
65 redundant-boot@200000 {
66 label = "Redundant Boot";
67 reg = <0x200000 0x80000>;
68 };
69
70 boot-env@300000 {
71 label = "Boot Evironment";
72 reg = <0x300000 0x20000>;
73 };
74
75 redundant-boot-env@320000 {
76 label = "Redundant Boot Environment";
77 reg = <0x300000 0x20000>;
78 };
79
80 kernel@380000 {
81 label = "Kernel";
82 reg = <0x380000 0x800000>;
83 };
84
85 fs@b80000 {
86 label = "File System";
87 reg = <0xb80000 0xf480000>;
88 };
89 };
90 };
91 };
92};
diff --git a/arch/arm/boot/dts/pm9g45.dts b/arch/arm/boot/dts/pm9g45.dts
deleted file mode 100644
index 387fedb5898..00000000000
--- a/arch/arm/boot/dts/pm9g45.dts
+++ /dev/null
@@ -1,165 +0,0 @@
1/*
2 * pm9g45.dts - Device Tree file for Ronetix pm9g45 board
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8/dts-v1/;
9/include/ "at91sam9g45.dtsi"
10
11/ {
12 model = "Ronetix pm9g45";
13 compatible = "ronetix,pm9g45", "atmel,at91sam9g45", "atmel,at91sam9";
14
15 chosen {
16 bootargs = "console=ttyS0,115200";
17 };
18
19 memory {
20 reg = <0x70000000 0x8000000>;
21 };
22
23 clocks {
24 #address-cells = <1>;
25 #size-cells = <1>;
26 ranges;
27
28 main_clock: clock@0 {
29 compatible = "atmel,osc", "fixed-clock";
30 clock-frequency = <12000000>;
31 };
32 };
33
34 ahb {
35 apb {
36 dbgu: serial@ffffee00 {
37 status = "okay";
38 };
39
40 pinctrl@fffff200 {
41
42 board {
43 pinctrl_board_nand: nand0-board {
44 atmel,pins =
45 <3 3 0x0 0x1 /* PD3 gpio RDY pin pull_up*/
46 2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
47 };
48 };
49
50 mmc {
51 pinctrl_board_mmc: mmc0-board {
52 atmel,pins =
53 <3 6 0x0 0x5>; /* PD6 gpio CD pin pull_up and deglitch */
54 };
55 };
56 };
57
58 mmc0: mmc@fff80000 {
59 pinctrl-0 = <
60 &pinctrl_board_mmc
61 &pinctrl_mmc0_slot0_clk_cmd_dat0
62 &pinctrl_mmc0_slot0_dat1_3>;
63 status = "okay";
64 slot@0 {
65 reg = <0>;
66 bus-width = <4>;
67 cd-gpios = <&pioD 6 0>;
68 };
69 };
70
71 macb0: ethernet@fffbc000 {
72 phy-mode = "rmii";
73 status = "okay";
74 };
75
76 };
77
78 nand0: nand@40000000 {
79 nand-bus-width = <8>;
80 nand-ecc-mode = "soft";
81 nand-on-flash-bbt;
82 pinctrl-0 = <&pinctrl_board_nand>;
83
84 gpios = <&pioD 3 0
85 &pioC 14 0
86 0
87 >;
88
89 status = "okay";
90
91 at91bootstrap@0 {
92 label = "at91bootstrap";
93 reg = <0x0 0x20000>;
94 };
95
96 barebox@20000 {
97 label = "barebox";
98 reg = <0x20000 0x40000>;
99 };
100
101 bareboxenv@60000 {
102 label = "bareboxenv";
103 reg = <0x60000 0x1A0000>;
104 };
105
106 kernel@200000 {
107 label = "bareboxenv2";
108 reg = <0x200000 0x300000>;
109 };
110
111 kernel@500000 {
112 label = "root";
113 reg = <0x500000 0x400000>;
114 };
115
116 data@900000 {
117 label = "data";
118 reg = <0x900000 0x8340000>;
119 };
120 };
121
122 usb0: ohci@00700000 {
123 status = "okay";
124 num-ports = <2>;
125 };
126
127 usb1: ehci@00800000 {
128 status = "okay";
129 };
130 };
131
132 leds {
133 compatible = "gpio-leds";
134
135 led0 {
136 label = "led0";
137 gpios = <&pioD 0 1>;
138 linux,default-trigger = "nand-disk";
139 };
140
141 led1 {
142 label = "led1";
143 gpios = <&pioD 31 0>;
144 linux,default-trigger = "heartbeat";
145 };
146 };
147
148 gpio_keys {
149 compatible = "gpio-keys";
150 #address-cells = <1>;
151 #size-cells = <0>;
152
153 right {
154 label = "SW4";
155 gpios = <&pioE 7 1>;
156 linux,code = <106>;
157 };
158
159 up {
160 label = "SW3";
161 gpios = <&pioE 8 1>;
162 linux,code = <103>;
163 };
164 };
165};
diff --git a/arch/arm/boot/dts/prima2-evb.dts b/arch/arm/boot/dts/prima2-evb.dts
deleted file mode 100644
index 57286b4e7b8..00000000000
--- a/arch/arm/boot/dts/prima2-evb.dts
+++ /dev/null
@@ -1,37 +0,0 @@
1/*
2 * DTS file for CSR SiRFprimaII Evaluation Board
3 *
4 * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9/dts-v1/;
10
11/include/ "prima2.dtsi"
12
13/ {
14 model = "CSR SiRFprimaII Evaluation Board";
15 compatible = "sirf,prima2", "sirf,prima2-cb";
16
17 memory {
18 reg = <0x00000000 0x20000000>;
19 };
20
21 axi {
22 peri-iobg {
23 uart@b0060000 {
24 pinctrl-names = "default";
25 pinctrl-0 = <&uart1_pins_a>;
26 };
27 spi@b00d0000 {
28 pinctrl-names = "default";
29 pinctrl-0 = <&spi0_pins_a>;
30 };
31 spi@b0170000 {
32 pinctrl-names = "default";
33 pinctrl-0 = <&spi1_pins_a>;
34 };
35 };
36 };
37};
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
deleted file mode 100644
index 055fca54212..00000000000
--- a/arch/arm/boot/dts/prima2.dtsi
+++ /dev/null
@@ -1,640 +0,0 @@
1/*
2 * DTS file for CSR SiRFprimaII SoC
3 *
4 * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9/include/ "skeleton.dtsi"
10/ {
11 compatible = "sirf,prima2";
12 #address-cells = <1>;
13 #size-cells = <1>;
14 interrupt-parent = <&intc>;
15
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19
20 cpu@0 {
21 reg = <0x0>;
22 d-cache-line-size = <32>;
23 i-cache-line-size = <32>;
24 d-cache-size = <32768>;
25 i-cache-size = <32768>;
26 /* from bootloader */
27 timebase-frequency = <0>;
28 bus-frequency = <0>;
29 clock-frequency = <0>;
30 };
31 };
32
33 axi {
34 compatible = "simple-bus";
35 #address-cells = <1>;
36 #size-cells = <1>;
37 ranges = <0x40000000 0x40000000 0x80000000>;
38
39 l2-cache-controller@80040000 {
40 compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache";
41 reg = <0x80040000 0x1000>;
42 interrupts = <59>;
43 arm,tag-latency = <1 1 1>;
44 arm,data-latency = <1 1 1>;
45 arm,filter-ranges = <0 0x40000000>;
46 };
47
48 intc: interrupt-controller@80020000 {
49 #interrupt-cells = <1>;
50 interrupt-controller;
51 compatible = "sirf,prima2-intc";
52 reg = <0x80020000 0x1000>;
53 };
54
55 sys-iobg {
56 compatible = "simple-bus";
57 #address-cells = <1>;
58 #size-cells = <1>;
59 ranges = <0x88000000 0x88000000 0x40000>;
60
61 clock-controller@88000000 {
62 compatible = "sirf,prima2-clkc";
63 reg = <0x88000000 0x1000>;
64 interrupts = <3>;
65 };
66
67 reset-controller@88010000 {
68 compatible = "sirf,prima2-rstc";
69 reg = <0x88010000 0x1000>;
70 };
71
72 rsc-controller@88020000 {
73 compatible = "sirf,prima2-rsc";
74 reg = <0x88020000 0x1000>;
75 };
76 };
77
78 mem-iobg {
79 compatible = "simple-bus";
80 #address-cells = <1>;
81 #size-cells = <1>;
82 ranges = <0x90000000 0x90000000 0x10000>;
83
84 memory-controller@90000000 {
85 compatible = "sirf,prima2-memc";
86 reg = <0x90000000 0x10000>;
87 interrupts = <27>;
88 };
89 };
90
91 disp-iobg {
92 compatible = "simple-bus";
93 #address-cells = <1>;
94 #size-cells = <1>;
95 ranges = <0x90010000 0x90010000 0x30000>;
96
97 display@90010000 {
98 compatible = "sirf,prima2-lcd";
99 reg = <0x90010000 0x20000>;
100 interrupts = <30>;
101 };
102
103 vpp@90020000 {
104 compatible = "sirf,prima2-vpp";
105 reg = <0x90020000 0x10000>;
106 interrupts = <31>;
107 };
108 };
109
110 graphics-iobg {
111 compatible = "simple-bus";
112 #address-cells = <1>;
113 #size-cells = <1>;
114 ranges = <0x98000000 0x98000000 0x8000000>;
115
116 graphics@98000000 {
117 compatible = "powervr,sgx531";
118 reg = <0x98000000 0x8000000>;
119 interrupts = <6>;
120 };
121 };
122
123 multimedia-iobg {
124 compatible = "simple-bus";
125 #address-cells = <1>;
126 #size-cells = <1>;
127 ranges = <0xa0000000 0xa0000000 0x8000000>;
128
129 multimedia@a0000000 {
130 compatible = "sirf,prima2-video-codec";
131 reg = <0xa0000000 0x8000000>;
132 interrupts = <5>;
133 };
134 };
135
136 dsp-iobg {
137 compatible = "simple-bus";
138 #address-cells = <1>;
139 #size-cells = <1>;
140 ranges = <0xa8000000 0xa8000000 0x2000000>;
141
142 dspif@a8000000 {
143 compatible = "sirf,prima2-dspif";
144 reg = <0xa8000000 0x10000>;
145 interrupts = <9>;
146 };
147
148 gps@a8010000 {
149 compatible = "sirf,prima2-gps";
150 reg = <0xa8010000 0x10000>;
151 interrupts = <7>;
152 };
153
154 dsp@a9000000 {
155 compatible = "sirf,prima2-dsp";
156 reg = <0xa9000000 0x1000000>;
157 interrupts = <8>;
158 };
159 };
160
161 peri-iobg {
162 compatible = "simple-bus";
163 #address-cells = <1>;
164 #size-cells = <1>;
165 ranges = <0xb0000000 0xb0000000 0x180000>;
166
167 timer@b0020000 {
168 compatible = "sirf,prima2-tick";
169 reg = <0xb0020000 0x1000>;
170 interrupts = <0>;
171 };
172
173 nand@b0030000 {
174 compatible = "sirf,prima2-nand";
175 reg = <0xb0030000 0x10000>;
176 interrupts = <41>;
177 };
178
179 audio@b0040000 {
180 compatible = "sirf,prima2-audio";
181 reg = <0xb0040000 0x10000>;
182 interrupts = <35>;
183 };
184
185 uart0: uart@b0050000 {
186 cell-index = <0>;
187 compatible = "sirf,prima2-uart";
188 reg = <0xb0050000 0x10000>;
189 interrupts = <17>;
190 };
191
192 uart1: uart@b0060000 {
193 cell-index = <1>;
194 compatible = "sirf,prima2-uart";
195 reg = <0xb0060000 0x10000>;
196 interrupts = <18>;
197 };
198
199 uart2: uart@b0070000 {
200 cell-index = <2>;
201 compatible = "sirf,prima2-uart";
202 reg = <0xb0070000 0x10000>;
203 interrupts = <19>;
204 };
205
206 usp0: usp@b0080000 {
207 cell-index = <0>;
208 compatible = "sirf,prima2-usp";
209 reg = <0xb0080000 0x10000>;
210 interrupts = <20>;
211 };
212
213 usp1: usp@b0090000 {
214 cell-index = <1>;
215 compatible = "sirf,prima2-usp";
216 reg = <0xb0090000 0x10000>;
217 interrupts = <21>;
218 };
219
220 usp2: usp@b00a0000 {
221 cell-index = <2>;
222 compatible = "sirf,prima2-usp";
223 reg = <0xb00a0000 0x10000>;
224 interrupts = <22>;
225 };
226
227 dmac0: dma-controller@b00b0000 {
228 cell-index = <0>;
229 compatible = "sirf,prima2-dmac";
230 reg = <0xb00b0000 0x10000>;
231 interrupts = <12>;
232 };
233
234 dmac1: dma-controller@b0160000 {
235 cell-index = <1>;
236 compatible = "sirf,prima2-dmac";
237 reg = <0xb0160000 0x10000>;
238 interrupts = <13>;
239 };
240
241 vip@b00C0000 {
242 compatible = "sirf,prima2-vip";
243 reg = <0xb00C0000 0x10000>;
244 };
245
246 spi0: spi@b00d0000 {
247 cell-index = <0>;
248 compatible = "sirf,prima2-spi";
249 reg = <0xb00d0000 0x10000>;
250 interrupts = <15>;
251 };
252
253 spi1: spi@b0170000 {
254 cell-index = <1>;
255 compatible = "sirf,prima2-spi";
256 reg = <0xb0170000 0x10000>;
257 interrupts = <16>;
258 };
259
260 i2c0: i2c@b00e0000 {
261 cell-index = <0>;
262 compatible = "sirf,prima2-i2c";
263 reg = <0xb00e0000 0x10000>;
264 interrupts = <24>;
265 };
266
267 i2c1: i2c@b00f0000 {
268 cell-index = <1>;
269 compatible = "sirf,prima2-i2c";
270 reg = <0xb00f0000 0x10000>;
271 interrupts = <25>;
272 };
273
274 tsc@b0110000 {
275 compatible = "sirf,prima2-tsc";
276 reg = <0xb0110000 0x10000>;
277 interrupts = <33>;
278 };
279
280 gpio: pinctrl@b0120000 {
281 #gpio-cells = <2>;
282 #interrupt-cells = <2>;
283 compatible = "sirf,prima2-pinctrl";
284 reg = <0xb0120000 0x10000>;
285 interrupts = <43 44 45 46 47>;
286 gpio-controller;
287 interrupt-controller;
288
289 lcd_16pins_a: lcd0@0 {
290 lcd {
291 sirf,pins = "lcd_16bitsgrp";
292 sirf,function = "lcd_16bits";
293 };
294 };
295 lcd_18pins_a: lcd0@1 {
296 lcd {
297 sirf,pins = "lcd_18bitsgrp";
298 sirf,function = "lcd_18bits";
299 };
300 };
301 lcd_24pins_a: lcd0@2 {
302 lcd {
303 sirf,pins = "lcd_24bitsgrp";
304 sirf,function = "lcd_24bits";
305 };
306 };
307 lcdrom_pins_a: lcdrom0@0 {
308 lcd {
309 sirf,pins = "lcdromgrp";
310 sirf,function = "lcdrom";
311 };
312 };
313 uart0_pins_a: uart0@0 {
314 uart {
315 sirf,pins = "uart0grp";
316 sirf,function = "uart0";
317 };
318 };
319 uart1_pins_a: uart1@0 {
320 uart {
321 sirf,pins = "uart1grp";
322 sirf,function = "uart1";
323 };
324 };
325 uart2_pins_a: uart2@0 {
326 uart {
327 sirf,pins = "uart2grp";
328 sirf,function = "uart2";
329 };
330 };
331 uart2_noflow_pins_a: uart2@1 {
332 uart {
333 sirf,pins = "uart2_nostreamctrlgrp";
334 sirf,function = "uart2_nostreamctrl";
335 };
336 };
337 spi0_pins_a: spi0@0 {
338 spi {
339 sirf,pins = "spi0grp";
340 sirf,function = "spi0";
341 };
342 };
343 spi1_pins_a: spi1@0 {
344 spi {
345 sirf,pins = "spi1grp";
346 sirf,function = "spi1";
347 };
348 };
349 i2c0_pins_a: i2c0@0 {
350 i2c {
351 sirf,pins = "i2c0grp";
352 sirf,function = "i2c0";
353 };
354 };
355 i2c1_pins_a: i2c1@0 {
356 i2c {
357 sirf,pins = "i2c1grp";
358 sirf,function = "i2c1";
359 };
360 };
361 pwm0_pins_a: pwm0@0 {
362 pwm {
363 sirf,pins = "pwm0grp";
364 sirf,function = "pwm0";
365 };
366 };
367 pwm1_pins_a: pwm1@0 {
368 pwm {
369 sirf,pins = "pwm1grp";
370 sirf,function = "pwm1";
371 };
372 };
373 pwm2_pins_a: pwm2@0 {
374 pwm {
375 sirf,pins = "pwm2grp";
376 sirf,function = "pwm2";
377 };
378 };
379 pwm3_pins_a: pwm3@0 {
380 pwm {
381 sirf,pins = "pwm3grp";
382 sirf,function = "pwm3";
383 };
384 };
385 gps_pins_a: gps@0 {
386 gps {
387 sirf,pins = "gpsgrp";
388 sirf,function = "gps";
389 };
390 };
391 vip_pins_a: vip@0 {
392 vip {
393 sirf,pins = "vipgrp";
394 sirf,function = "vip";
395 };
396 };
397 sdmmc0_pins_a: sdmmc0@0 {
398 sdmmc0 {
399 sirf,pins = "sdmmc0grp";
400 sirf,function = "sdmmc0";
401 };
402 };
403 sdmmc1_pins_a: sdmmc1@0 {
404 sdmmc1 {
405 sirf,pins = "sdmmc1grp";
406 sirf,function = "sdmmc1";
407 };
408 };
409 sdmmc2_pins_a: sdmmc2@0 {
410 sdmmc2 {
411 sirf,pins = "sdmmc2grp";
412 sirf,function = "sdmmc2";
413 };
414 };
415 sdmmc3_pins_a: sdmmc3@0 {
416 sdmmc3 {
417 sirf,pins = "sdmmc3grp";
418 sirf,function = "sdmmc3";
419 };
420 };
421 sdmmc4_pins_a: sdmmc4@0 {
422 sdmmc4 {
423 sirf,pins = "sdmmc4grp";
424 sirf,function = "sdmmc4";
425 };
426 };
427 sdmmc5_pins_a: sdmmc5@0 {
428 sdmmc5 {
429 sirf,pins = "sdmmc5grp";
430 sirf,function = "sdmmc5";
431 };
432 };
433 i2s_pins_a: i2s@0 {
434 i2s {
435 sirf,pins = "i2sgrp";
436 sirf,function = "i2s";
437 };
438 };
439 ac97_pins_a: ac97@0 {
440 ac97 {
441 sirf,pins = "ac97grp";
442 sirf,function = "ac97";
443 };
444 };
445 nand_pins_a: nand@0 {
446 nand {
447 sirf,pins = "nandgrp";
448 sirf,function = "nand";
449 };
450 };
451 usp0_pins_a: usp0@0 {
452 usp0 {
453 sirf,pins = "usp0grp";
454 sirf,function = "usp0";
455 };
456 };
457 usp1_pins_a: usp1@0 {
458 usp1 {
459 sirf,pins = "usp1grp";
460 sirf,function = "usp1";
461 };
462 };
463 usp2_pins_a: usp2@0 {
464 usp2 {
465 sirf,pins = "usp2grp";
466 sirf,function = "usp2";
467 };
468 };
469 usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus@0 {
470 usb0_utmi_drvbus {
471 sirf,pins = "usb0_utmi_drvbusgrp";
472 sirf,function = "usb0_utmi_drvbus";
473 };
474 };
475 usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 {
476 usb1_utmi_drvbus {
477 sirf,pins = "usb1_utmi_drvbusgrp";
478 sirf,function = "usb1_utmi_drvbus";
479 };
480 };
481 warm_rst_pins_a: warm_rst@0 {
482 warm_rst {
483 sirf,pins = "warm_rstgrp";
484 sirf,function = "warm_rst";
485 };
486 };
487 pulse_count_pins_a: pulse_count@0 {
488 pulse_count {
489 sirf,pins = "pulse_countgrp";
490 sirf,function = "pulse_count";
491 };
492 };
493 cko0_rst_pins_a: cko0_rst@0 {
494 cko0_rst {
495 sirf,pins = "cko0_rstgrp";
496 sirf,function = "cko0_rst";
497 };
498 };
499 cko1_rst_pins_a: cko1_rst@0 {
500 cko1_rst {
501 sirf,pins = "cko1_rstgrp";
502 sirf,function = "cko1_rst";
503 };
504 };
505 };
506
507 pwm@b0130000 {
508 compatible = "sirf,prima2-pwm";
509 reg = <0xb0130000 0x10000>;
510 };
511
512 efusesys@b0140000 {
513 compatible = "sirf,prima2-efuse";
514 reg = <0xb0140000 0x10000>;
515 };
516
517 pulsec@b0150000 {
518 compatible = "sirf,prima2-pulsec";
519 reg = <0xb0150000 0x10000>;
520 interrupts = <48>;
521 };
522
523 pci-iobg {
524 compatible = "sirf,prima2-pciiobg", "simple-bus";
525 #address-cells = <1>;
526 #size-cells = <1>;
527 ranges = <0x56000000 0x56000000 0x1b00000>;
528
529 sd0: sdhci@56000000 {
530 cell-index = <0>;
531 compatible = "sirf,prima2-sdhc";
532 reg = <0x56000000 0x100000>;
533 interrupts = <38>;
534 };
535
536 sd1: sdhci@56100000 {
537 cell-index = <1>;
538 compatible = "sirf,prima2-sdhc";
539 reg = <0x56100000 0x100000>;
540 interrupts = <38>;
541 };
542
543 sd2: sdhci@56200000 {
544 cell-index = <2>;
545 compatible = "sirf,prima2-sdhc";
546 reg = <0x56200000 0x100000>;
547 interrupts = <23>;
548 };
549
550 sd3: sdhci@56300000 {
551 cell-index = <3>;
552 compatible = "sirf,prima2-sdhc";
553 reg = <0x56300000 0x100000>;
554 interrupts = <23>;
555 };
556
557 sd4: sdhci@56400000 {
558 cell-index = <4>;
559 compatible = "sirf,prima2-sdhc";
560 reg = <0x56400000 0x100000>;
561 interrupts = <39>;
562 };
563
564 sd5: sdhci@56500000 {
565 cell-index = <5>;
566 compatible = "sirf,prima2-sdhc";
567 reg = <0x56500000 0x100000>;
568 interrupts = <39>;
569 };
570
571 pci-copy@57900000 {
572 compatible = "sirf,prima2-pcicp";
573 reg = <0x57900000 0x100000>;
574 interrupts = <40>;
575 };
576
577 rom-interface@57a00000 {
578 compatible = "sirf,prima2-romif";
579 reg = <0x57a00000 0x100000>;
580 };
581 };
582 };
583
584 rtc-iobg {
585 compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus";
586 #address-cells = <1>;
587 #size-cells = <1>;
588 reg = <0x80030000 0x10000>;
589
590 gpsrtc@1000 {
591 compatible = "sirf,prima2-gpsrtc";
592 reg = <0x1000 0x1000>;
593 interrupts = <55 56 57>;
594 };
595
596 sysrtc@2000 {
597 compatible = "sirf,prima2-sysrtc";
598 reg = <0x2000 0x1000>;
599 interrupts = <52 53 54>;
600 };
601
602 pwrc@3000 {
603 compatible = "sirf,prima2-pwrc";
604 reg = <0x3000 0x1000>;
605 interrupts = <32>;
606 };
607 };
608
609 uus-iobg {
610 compatible = "simple-bus";
611 #address-cells = <1>;
612 #size-cells = <1>;
613 ranges = <0xb8000000 0xb8000000 0x40000>;
614
615 usb0: usb@b00e0000 {
616 compatible = "chipidea,ci13611a-prima2";
617 reg = <0xb8000000 0x10000>;
618 interrupts = <10>;
619 };
620
621 usb1: usb@b00f0000 {
622 compatible = "chipidea,ci13611a-prima2";
623 reg = <0xb8010000 0x10000>;
624 interrupts = <11>;
625 };
626
627 sata@b00f0000 {
628 compatible = "synopsys,dwc-ahsata";
629 reg = <0xb8020000 0x10000>;
630 interrupts = <37>;
631 };
632
633 security@b00f0000 {
634 compatible = "sirf,prima2-security";
635 reg = <0xb8030000 0x10000>;
636 interrupts = <42>;
637 };
638 };
639 };
640};
diff --git a/arch/arm/boot/dts/pxa168-aspenite.dts b/arch/arm/boot/dts/pxa168-aspenite.dts
deleted file mode 100644
index e762facb3fa..00000000000
--- a/arch/arm/boot/dts/pxa168-aspenite.dts
+++ /dev/null
@@ -1,38 +0,0 @@
1/*
2 * Copyright (C) 2012 Marvell Technology Group Ltd.
3 * Author: Haojian Zhuang <haojian.zhuang@marvell.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9
10/dts-v1/;
11/include/ "pxa168.dtsi"
12
13/ {
14 model = "Marvell PXA168 Aspenite Development Board";
15 compatible = "mrvl,pxa168-aspenite", "mrvl,pxa168";
16
17 chosen {
18 bootargs = "console=ttyS0,115200 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on";
19 };
20
21 memory {
22 reg = <0x00000000 0x04000000>;
23 };
24
25 soc {
26 apb@d4000000 {
27 uart1: uart@d4017000 {
28 status = "okay";
29 };
30 twsi1: i2c@d4011000 {
31 status = "okay";
32 };
33 rtc: rtc@d4010000 {
34 status = "okay";
35 };
36 };
37 };
38};
diff --git a/arch/arm/boot/dts/pxa168.dtsi b/arch/arm/boot/dts/pxa168.dtsi
deleted file mode 100644
index 31a71869608..00000000000
--- a/arch/arm/boot/dts/pxa168.dtsi
+++ /dev/null
@@ -1,133 +0,0 @@
1/*
2 * Copyright (C) 2012 Marvell Technology Group Ltd.
3 * Author: Haojian Zhuang <haojian.zhuang@marvell.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9
10/include/ "skeleton.dtsi"
11
12/ {
13 aliases {
14 serial0 = &uart1;
15 serial1 = &uart2;
16 serial2 = &uart3;
17 i2c0 = &twsi1;
18 i2c1 = &twsi2;
19 };
20
21 soc {
22 #address-cells = <1>;
23 #size-cells = <1>;
24 compatible = "simple-bus";
25 interrupt-parent = <&intc>;
26 ranges;
27
28 axi@d4200000 { /* AXI */
29 compatible = "mrvl,axi-bus", "simple-bus";
30 #address-cells = <1>;
31 #size-cells = <1>;
32 reg = <0xd4200000 0x00200000>;
33 ranges;
34
35 intc: interrupt-controller@d4282000 {
36 compatible = "mrvl,mmp-intc";
37 interrupt-controller;
38 #interrupt-cells = <1>;
39 reg = <0xd4282000 0x1000>;
40 mrvl,intc-nr-irqs = <64>;
41 };
42
43 };
44
45 apb@d4000000 { /* APB */
46 compatible = "mrvl,apb-bus", "simple-bus";
47 #address-cells = <1>;
48 #size-cells = <1>;
49 reg = <0xd4000000 0x00200000>;
50 ranges;
51
52 timer0: timer@d4014000 {
53 compatible = "mrvl,mmp-timer";
54 reg = <0xd4014000 0x100>;
55 interrupts = <13>;
56 };
57
58 uart1: uart@d4017000 {
59 compatible = "mrvl,mmp-uart";
60 reg = <0xd4017000 0x1000>;
61 interrupts = <27>;
62 status = "disabled";
63 };
64
65 uart2: uart@d4018000 {
66 compatible = "mrvl,mmp-uart";
67 reg = <0xd4018000 0x1000>;
68 interrupts = <28>;
69 status = "disabled";
70 };
71
72 uart3: uart@d4026000 {
73 compatible = "mrvl,mmp-uart";
74 reg = <0xd4026000 0x1000>;
75 interrupts = <29>;
76 status = "disabled";
77 };
78
79 gpio@d4019000 {
80 compatible = "mrvl,mmp-gpio";
81 #address-cells = <1>;
82 #size-cells = <1>;
83 reg = <0xd4019000 0x1000>;
84 gpio-controller;
85 #gpio-cells = <2>;
86 interrupts = <49>;
87 interrupt-names = "gpio_mux";
88 interrupt-controller;
89 #interrupt-cells = <1>;
90 ranges;
91
92 gcb0: gpio@d4019000 {
93 reg = <0xd4019000 0x4>;
94 };
95
96 gcb1: gpio@d4019004 {
97 reg = <0xd4019004 0x4>;
98 };
99
100 gcb2: gpio@d4019008 {
101 reg = <0xd4019008 0x4>;
102 };
103
104 gcb3: gpio@d4019100 {
105 reg = <0xd4019100 0x4>;
106 };
107 };
108
109 twsi1: i2c@d4011000 {
110 compatible = "mrvl,mmp-twsi";
111 reg = <0xd4011000 0x1000>;
112 interrupts = <7>;
113 mrvl,i2c-fast-mode;
114 status = "disabled";
115 };
116
117 twsi2: i2c@d4025000 {
118 compatible = "mrvl,mmp-twsi";
119 reg = <0xd4025000 0x1000>;
120 interrupts = <58>;
121 status = "disabled";
122 };
123
124 rtc: rtc@d4010000 {
125 compatible = "mrvl,mmp-rtc";
126 reg = <0xd4010000 0x1000>;
127 interrupts = <5 6>;
128 interrupt-names = "rtc 1Hz", "rtc alarm";
129 status = "disabled";
130 };
131 };
132 };
133};
diff --git a/arch/arm/boot/dts/pxa27x.dtsi b/arch/arm/boot/dts/pxa27x.dtsi
deleted file mode 100644
index d7c5d721a5c..00000000000
--- a/arch/arm/boot/dts/pxa27x.dtsi
+++ /dev/null
@@ -1,14 +0,0 @@
1/* The pxa3xx skeleton simply augments the 2xx version */
2/include/ "pxa2xx.dtsi"
3
4/ {
5 model = "Marvell PXA27x familiy SoC";
6 compatible = "marvell,pxa27x";
7
8 pxabus {
9 pxairq: interrupt-controller@40d00000 {
10 marvell,intc-priority;
11 marvell,intc-nr-irqs = <34>;
12 };
13 };
14};
diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi
deleted file mode 100644
index f18aad35e8b..00000000000
--- a/arch/arm/boot/dts/pxa2xx.dtsi
+++ /dev/null
@@ -1,132 +0,0 @@
1/*
2 * pxa2xx.dtsi - Device Tree Include file for Marvell PXA2xx family SoC
3 *
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9/include/ "skeleton.dtsi"
10
11/ {
12 model = "Marvell PXA2xx family SoC";
13 compatible = "marvell,pxa2xx";
14 interrupt-parent = <&pxairq>;
15
16 aliases {
17 serial0 = &ffuart;
18 serial1 = &btuart;
19 serial2 = &stuart;
20 serial3 = &hwuart;
21 i2c0 = &pwri2c;
22 i2c1 = &pxai2c1;
23 };
24
25 cpus {
26 cpu@0 {
27 compatible = "arm,xscale";
28 };
29 };
30
31 pxabus {
32 compatible = "simple-bus";
33 #address-cells = <1>;
34 #size-cells = <1>;
35 ranges;
36
37 pxairq: interrupt-controller@40d00000 {
38 #interrupt-cells = <1>;
39 compatible = "marvell,pxa-intc";
40 interrupt-controller;
41 interrupt-parent;
42 marvell,intc-nr-irqs = <32>;
43 reg = <0x40d00000 0xd0>;
44 };
45
46 gpio: gpio@40e00000 {
47 compatible = "mrvl,pxa-gpio";
48 #address-cells = <0x1>;
49 #size-cells = <0x1>;
50 reg = <0x40e00000 0x10000>;
51 gpio-controller;
52 #gpio-cells = <0x2>;
53 interrupts = <10>;
54 interrupt-names = "gpio_mux";
55 interrupt-controller;
56 #interrupt-cells = <0x2>;
57 ranges;
58
59 gcb0: gpio@40e00000 {
60 reg = <0x40e00000 0x4>;
61 };
62
63 gcb1: gpio@40e00004 {
64 reg = <0x40e00004 0x4>;
65 };
66
67 gcb2: gpio@40e00008 {
68 reg = <0x40e00008 0x4>;
69 };
70 gcb3: gpio@40e0000c {
71 reg = <0x40e0000c 0x4>;
72 };
73 };
74
75 ffuart: uart@40100000 {
76 compatible = "mrvl,pxa-uart";
77 reg = <0x40100000 0x30>;
78 interrupts = <22>;
79 status = "disabled";
80 };
81
82 btuart: uart@40200000 {
83 compatible = "mrvl,pxa-uart";
84 reg = <0x40200000 0x30>;
85 interrupts = <21>;
86 status = "disabled";
87 };
88
89 stuart: uart@40700000 {
90 compatible = "mrvl,pxa-uart";
91 reg = <0x40700000 0x30>;
92 interrupts = <20>;
93 status = "disabled";
94 };
95
96 hwuart: uart@41100000 {
97 compatible = "mrvl,pxa-uart";
98 reg = <0x41100000 0x30>;
99 interrupts = <7>;
100 status = "disabled";
101 };
102
103 pxai2c1: i2c@40301680 {
104 compatible = "mrvl,pxa-i2c";
105 reg = <0x40301680 0x30>;
106 interrupts = <18>;
107 #address-cells = <0x1>;
108 #size-cells = <0>;
109 status = "disabled";
110 };
111
112 usb0: ohci@4c000000 {
113 compatible = "mrvl,pxa-ohci";
114 reg = <0x4c000000 0x10000>;
115 interrupts = <3>;
116 status = "disabled";
117 };
118
119 mmc0: mmc@41100000 {
120 compatible = "mrvl,pxa-mmc";
121 reg = <0x41100000 0x1000>;
122 interrupts = <23>;
123 status = "disabled";
124 };
125
126 rtc@40900000 {
127 compatible = "marvell,pxa-rtc";
128 reg = <0x40900000 0x3c>;
129 interrupts = <30 31>;
130 };
131 };
132};
diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi
deleted file mode 100644
index f9d92da8678..00000000000
--- a/arch/arm/boot/dts/pxa3xx.dtsi
+++ /dev/null
@@ -1,32 +0,0 @@
1/* The pxa3xx skeleton simply augments the 2xx version */
2/include/ "pxa2xx.dtsi"
3
4/ {
5 model = "Marvell PXA3xx familiy SoC";
6 compatible = "marvell,pxa3xx";
7
8 pxabus {
9 pwri2c: i2c@40f500c0 {
10 compatible = "mrvl,pwri2c";
11 reg = <0x40f500c0 0x30>;
12 interrupts = <6>;
13 #address-cells = <0x1>;
14 #size-cells = <0>;
15 status = "disabled";
16 };
17
18 nand0: nand@43100000 {
19 compatible = "marvell,pxa3xx-nand";
20 reg = <0x43100000 90>;
21 interrupts = <45>;
22 #address-cells = <1>;
23 #size-cells = <1>;
24 status = "disabled";
25 };
26
27 pxairq: interrupt-controller@40d00000 {
28 marvell,intc-priority;
29 marvell,intc-nr-irqs = <56>;
30 };
31 };
32};
diff --git a/arch/arm/boot/dts/pxa910-dkb.dts b/arch/arm/boot/dts/pxa910-dkb.dts
deleted file mode 100644
index 595492aa505..00000000000
--- a/arch/arm/boot/dts/pxa910-dkb.dts
+++ /dev/null
@@ -1,175 +0,0 @@
1/*
2 * Copyright (C) 2012 Marvell Technology Group Ltd.
3 * Author: Haojian Zhuang <haojian.zhuang@marvell.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9
10/dts-v1/;
11/include/ "pxa910.dtsi"
12
13/ {
14 model = "Marvell PXA910 DKB Development Board";
15 compatible = "mrvl,pxa910-dkb", "mrvl,pxa910";
16
17 chosen {
18 bootargs = "console=ttyS0,115200 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on";
19 };
20
21 memory {
22 reg = <0x00000000 0x10000000>;
23 };
24
25 soc {
26 apb@d4000000 {
27 uart1: uart@d4017000 {
28 status = "okay";
29 };
30 twsi1: i2c@d4011000 {
31 status = "okay";
32
33 pmic: 88pm860x@34 {
34 compatible = "marvell,88pm860x";
35 reg = <0x34>;
36 interrupts = <4>;
37 interrupt-parent = <&intc>;
38 interrupt-controller;
39 #interrupt-cells = <1>;
40
41 marvell,88pm860x-irq-read-clr;
42 marvell,88pm860x-slave-addr = <0x11>;
43
44 regulators {
45 BUCK1 {
46 regulator-min-microvolt = <1000000>;
47 regulator-max-microvolt = <1500000>;
48 regulator-boot-on;
49 regulator-always-on;
50 };
51 BUCK2 {
52 regulator-min-microvolt = <1000000>;
53 regulator-max-microvolt = <1500000>;
54 regulator-boot-on;
55 regulator-always-on;
56 };
57 BUCK3 {
58 regulator-min-microvolt = <1000000>;
59 regulator-max-microvolt = <3000000>;
60 regulator-boot-on;
61 regulator-always-on;
62 };
63 LDO1 {
64 regulator-min-microvolt = <1200000>;
65 regulator-max-microvolt = <2800000>;
66 regulator-boot-on;
67 regulator-always-on;
68 };
69 LDO2 {
70 regulator-min-microvolt = <1800000>;
71 regulator-max-microvolt = <3300000>;
72 regulator-boot-on;
73 regulator-always-on;
74 };
75 LDO3 {
76 regulator-min-microvolt = <1800000>;
77 regulator-max-microvolt = <3300000>;
78 regulator-boot-on;
79 regulator-always-on;
80 };
81 LDO4 {
82 regulator-min-microvolt = <1800000>;
83 regulator-max-microvolt = <3300000>;
84 regulator-always-on;
85 };
86 LDO5 {
87 regulator-min-microvolt = <2900000>;
88 regulator-max-microvolt = <3300000>;
89 regulator-boot-on;
90 regulator-always-on;
91 };
92 LDO6 {
93 regulator-min-microvolt = <1800000>;
94 regulator-max-microvolt = <3300000>;
95 regulator-boot-on;
96 regulator-always-on;
97 };
98 LDO7 {
99 regulator-min-microvolt = <1800000>;
100 regulator-max-microvolt = <2900000>;
101 regulator-boot-on;
102 regulator-always-on;
103 };
104 LDO8 {
105 regulator-min-microvolt = <1800000>;
106 regulator-max-microvolt = <2900000>;
107 regulator-boot-on;
108 regulator-always-on;
109 };
110 LDO9 {
111 regulator-min-microvolt = <1800000>;
112 regulator-max-microvolt = <3300000>;
113 regulator-boot-on;
114 regulator-always-on;
115 };
116 LDO10 {
117 regulator-min-microvolt = <1200000>;
118 regulator-max-microvolt = <3300000>;
119 regulator-boot-on;
120 regulator-always-on;
121 };
122 LDO12 {
123 regulator-min-microvolt = <1200000>;
124 regulator-max-microvolt = <3300000>;
125 regulator-always-on;
126 };
127 LDO13 {
128 regulator-min-microvolt = <1200000>;
129 regulator-max-microvolt = <3300000>;
130 regulator-always-on;
131 };
132 LDO14 {
133 regulator-min-microvolt = <1800000>;
134 regulator-max-microvolt = <3300000>;
135 regulator-always-on;
136 };
137 };
138 rtc {
139 marvell,88pm860x-vrtc = <1>;
140 };
141 touch {
142 marvell,88pm860x-gpadc-prebias = <1>;
143 marvell,88pm860x-gpadc-slot-cycle = <1>;
144 marvell,88pm860x-tsi-prebias = <6>;
145 marvell,88pm860x-pen-prebias = <16>;
146 marvell,88pm860x-pen-prechg = <2>;
147 marvell,88pm860x-resistor-X = <300>;
148 };
149 backlights {
150 backlight-0 {
151 marvell,88pm860x-iset = <4>;
152 marvell,88pm860x-pwm = <3>;
153 };
154 backlight-2 {
155 };
156 };
157 leds {
158 led0-red {
159 marvell,88pm860x-iset = <12>;
160 };
161 led0-green {
162 marvell,88pm860x-iset = <12>;
163 };
164 led0-blue {
165 marvell,88pm860x-iset = <12>;
166 };
167 };
168 };
169 };
170 rtc: rtc@d4010000 {
171 status = "okay";
172 };
173 };
174 };
175};
diff --git a/arch/arm/boot/dts/pxa910.dtsi b/arch/arm/boot/dts/pxa910.dtsi
deleted file mode 100644
index 825aaca3303..00000000000
--- a/arch/arm/boot/dts/pxa910.dtsi
+++ /dev/null
@@ -1,149 +0,0 @@
1/*
2 * Copyright (C) 2012 Marvell Technology Group Ltd.
3 * Author: Haojian Zhuang <haojian.zhuang@marvell.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9
10/include/ "skeleton.dtsi"
11
12/ {
13 aliases {
14 serial0 = &uart1;
15 serial1 = &uart2;
16 serial2 = &uart3;
17 i2c0 = &twsi1;
18 i2c1 = &twsi2;
19 };
20
21 soc {
22 #address-cells = <1>;
23 #size-cells = <1>;
24 compatible = "simple-bus";
25 interrupt-parent = <&intc>;
26 ranges;
27
28 L2: l2-cache {
29 compatible = "marvell,tauros2-cache";
30 marvell,tauros2-cache-features = <0x3>;
31 };
32
33 axi@d4200000 { /* AXI */
34 compatible = "mrvl,axi-bus", "simple-bus";
35 #address-cells = <1>;
36 #size-cells = <1>;
37 reg = <0xd4200000 0x00200000>;
38 ranges;
39
40 intc: interrupt-controller@d4282000 {
41 compatible = "mrvl,mmp-intc";
42 interrupt-controller;
43 #interrupt-cells = <1>;
44 reg = <0xd4282000 0x1000>;
45 mrvl,intc-nr-irqs = <64>;
46 };
47
48 };
49
50 apb@d4000000 { /* APB */
51 compatible = "mrvl,apb-bus", "simple-bus";
52 #address-cells = <1>;
53 #size-cells = <1>;
54 reg = <0xd4000000 0x00200000>;
55 ranges;
56
57 timer0: timer@d4014000 {
58 compatible = "mrvl,mmp-timer";
59 reg = <0xd4014000 0x100>;
60 interrupts = <13>;
61 };
62
63 timer1: timer@d4016000 {
64 compatible = "mrvl,mmp-timer";
65 reg = <0xd4016000 0x100>;
66 interrupts = <29>;
67 status = "disabled";
68 };
69
70 uart1: uart@d4017000 {
71 compatible = "mrvl,mmp-uart";
72 reg = <0xd4017000 0x1000>;
73 interrupts = <27>;
74 status = "disabled";
75 };
76
77 uart2: uart@d4018000 {
78 compatible = "mrvl,mmp-uart";
79 reg = <0xd4018000 0x1000>;
80 interrupts = <28>;
81 status = "disabled";
82 };
83
84 uart3: uart@d4036000 {
85 compatible = "mrvl,mmp-uart";
86 reg = <0xd4036000 0x1000>;
87 interrupts = <59>;
88 status = "disabled";
89 };
90
91 gpio@d4019000 {
92 compatible = "mrvl,mmp-gpio";
93 #address-cells = <1>;
94 #size-cells = <1>;
95 reg = <0xd4019000 0x1000>;
96 gpio-controller;
97 #gpio-cells = <2>;
98 interrupts = <49>;
99 interrupt-names = "gpio_mux";
100 interrupt-controller;
101 #interrupt-cells = <1>;
102 ranges;
103
104 gcb0: gpio@d4019000 {
105 reg = <0xd4019000 0x4>;
106 };
107
108 gcb1: gpio@d4019004 {
109 reg = <0xd4019004 0x4>;
110 };
111
112 gcb2: gpio@d4019008 {
113 reg = <0xd4019008 0x4>;
114 };
115
116 gcb3: gpio@d4019100 {
117 reg = <0xd4019100 0x4>;
118 };
119 };
120
121 twsi1: i2c@d4011000 {
122 compatible = "mrvl,mmp-twsi";
123 #address-cells = <1>;
124 #size-cells = <0>;
125 reg = <0xd4011000 0x1000>;
126 interrupts = <7>;
127 mrvl,i2c-fast-mode;
128 status = "disabled";
129 };
130
131 twsi2: i2c@d4037000 {
132 compatible = "mrvl,mmp-twsi";
133 #address-cells = <1>;
134 #size-cells = <0>;
135 reg = <0xd4037000 0x1000>;
136 interrupts = <54>;
137 status = "disabled";
138 };
139
140 rtc: rtc@d4010000 {
141 compatible = "mrvl,mmp-rtc";
142 reg = <0xd4010000 0x1000>;
143 interrupts = <5 6>;
144 interrupt-names = "rtc 1Hz", "rtc alarm";
145 status = "disabled";
146 };
147 };
148 };
149};
diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
deleted file mode 100644
index a7505a95a3b..00000000000
--- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * Device Tree Source for the armadillo 800 eva board
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/dts-v1/;
12/include/ "skeleton.dtsi"
13
14/ {
15 model = "armadillo 800 eva";
16 compatible = "renesas,armadillo800eva";
17
18 memory {
19 device_type = "memory";
20 reg = <0x40000000 0x20000000>;
21 };
22};
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
deleted file mode 100644
index 798fa35c000..00000000000
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * Device Tree Source for the r8a7740 SoC
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "skeleton.dtsi"
12
13/ {
14 compatible = "renesas,r8a7740";
15
16 cpus {
17 cpu@0 {
18 compatible = "arm,cortex-a9";
19 };
20 };
21};
diff --git a/arch/arm/boot/dts/samsung_k3pe0e000b.dtsi b/arch/arm/boot/dts/samsung_k3pe0e000b.dtsi
deleted file mode 100644
index 9657a5cbc3a..00000000000
--- a/arch/arm/boot/dts/samsung_k3pe0e000b.dtsi
+++ /dev/null
@@ -1,67 +0,0 @@
1/*
2 * Timings and Geometry for Samsung K3PE0E000B memory part
3 */
4
5/ {
6 samsung_K3PE0E000B: lpddr2 {
7 compatible = "Samsung,K3PE0E000B","jedec,lpddr2-s4";
8 density = <4096>;
9 io-width = <32>;
10
11 tRPab-min-tck = <3>;
12 tRCD-min-tck = <3>;
13 tWR-min-tck = <3>;
14 tRASmin-min-tck = <3>;
15 tRRD-min-tck = <2>;
16 tWTR-min-tck = <2>;
17 tXP-min-tck = <2>;
18 tRTP-min-tck = <2>;
19 tCKE-min-tck = <3>;
20 tCKESR-min-tck = <3>;
21 tFAW-min-tck = <8>;
22
23 timings_samsung_K3PE0E000B_533MHz: lpddr2-timings@0 {
24 compatible = "jedec,lpddr2-timings";
25 min-freq = <10000000>;
26 max-freq = <533333333>;
27 tRPab = <21000>;
28 tRCD = <18000>;
29 tWR = <15000>;
30 tRAS-min = <42000>;
31 tRRD = <10000>;
32 tWTR = <7500>;
33 tXP = <7500>;
34 tRTP = <7500>;
35 tCKESR = <15000>;
36 tDQSCK-max = <5500>;
37 tFAW = <50000>;
38 tZQCS = <90000>;
39 tZQCL = <360000>;
40 tZQinit = <1000000>;
41 tRAS-max-ns = <70000>;
42 tDQSCK-max-derated = <6000>;
43 };
44
45 timings_samsung_K3PE0E000B_266MHz: lpddr2-timings@1 {
46 compatible = "jedec,lpddr2-timings";
47 min-freq = <10000000>;
48 max-freq = <266666666>;
49 tRPab = <21000>;
50 tRCD = <18000>;
51 tWR = <15000>;
52 tRAS-min = <42000>;
53 tRRD = <10000>;
54 tWTR = <7500>;
55 tXP = <7500>;
56 tRTP = <7500>;
57 tCKESR = <15000>;
58 tDQSCK-max = <5500>;
59 tFAW = <50000>;
60 tZQCS = <90000>;
61 tZQCL = <360000>;
62 tZQinit = <1000000>;
63 tRAS-max-ns = <70000>;
64 tDQSCK-max-derated = <6000>;
65 };
66 };
67};
diff --git a/arch/arm/boot/dts/sh7372-mackerel.dts b/arch/arm/boot/dts/sh7372-mackerel.dts
deleted file mode 100644
index 286f0caef01..00000000000
--- a/arch/arm/boot/dts/sh7372-mackerel.dts
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * Device Tree Source for the mackerel board
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/dts-v1/;
12/include/ "skeleton.dtsi"
13
14/ {
15 model = "Mackerel (AP4 EVM 2nd)";
16 compatible = "renesas,mackerel";
17
18 memory {
19 device_type = "memory";
20 reg = <0x40000000 0x10000000>;
21 };
22};
diff --git a/arch/arm/boot/dts/sh7372.dtsi b/arch/arm/boot/dts/sh7372.dtsi
deleted file mode 100644
index 677fc603f8b..00000000000
--- a/arch/arm/boot/dts/sh7372.dtsi
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * Device Tree Source for the sh7372 SoC
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "skeleton.dtsi"
12
13/ {
14 compatible = "renesas,sh7372";
15
16 cpus {
17 cpu@0 {
18 compatible = "arm,cortex-a8";
19 };
20 };
21};
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g.dts b/arch/arm/boot/dts/sh73a0-kzm9g.dts
deleted file mode 100644
index bcb91195197..00000000000
--- a/arch/arm/boot/dts/sh73a0-kzm9g.dts
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * Device Tree Source for the KZM-A9-GT board
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/dts-v1/;
12/include/ "skeleton.dtsi"
13
14/ {
15 model = "KZM-A9-GT";
16 compatible = "renesas,kzm9g", "renesas,sh73a0";
17
18 memory {
19 device_type = "memory";
20 reg = <0x41000000 0x1e800000>;
21 };
22};
diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
deleted file mode 100644
index 27f31a5fa49..00000000000
--- a/arch/arm/boot/dts/snowball.dts
+++ /dev/null
@@ -1,350 +0,0 @@
1/*
2 * Copyright 2011 ST-Ericsson AB
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "dbx5x0.dtsi"
14
15/ {
16 model = "Calao Systems Snowball platform with device tree";
17 compatible = "calaosystems,snowball-a9500", "st-ericsson,u9500";
18
19 memory {
20 reg = <0x00000000 0x20000000>;
21 };
22
23 en_3v3_reg: en_3v3 {
24 compatible = "regulator-fixed";
25 regulator-name = "en-3v3-fixed-supply";
26 regulator-min-microvolt = <3300000>;
27 regulator-max-microvolt = <3300000>;
28 gpios = <&gpio0 26 0x4>; // 26
29 startup-delay-us = <5000>;
30 enable-active-high;
31 };
32
33 gpio_keys {
34 compatible = "gpio-keys";
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 button@1 {
39 debounce_interval = <50>;
40 wakeup = <1>;
41 linux,code = <2>;
42 label = "userpb";
43 gpios = <&gpio1 0 0x4>;
44 };
45 button@2 {
46 debounce_interval = <50>;
47 wakeup = <1>;
48 linux,code = <3>;
49 label = "extkb1";
50 gpios = <&gpio4 23 0x4>;
51 };
52 button@3 {
53 debounce_interval = <50>;
54 wakeup = <1>;
55 linux,code = <4>;
56 label = "extkb2";
57 gpios = <&gpio4 24 0x4>;
58 };
59 button@4 {
60 debounce_interval = <50>;
61 wakeup = <1>;
62 linux,code = <5>;
63 label = "extkb3";
64 gpios = <&gpio5 1 0x4>;
65 };
66 button@5 {
67 debounce_interval = <50>;
68 wakeup = <1>;
69 linux,code = <6>;
70 label = "extkb4";
71 gpios = <&gpio5 2 0x4>;
72 };
73 };
74
75 leds {
76 compatible = "gpio-leds";
77 used-led {
78 label = "user_led";
79 gpios = <&gpio4 14 0x4>;
80 default-state = "on";
81 linux,default-trigger = "heartbeat";
82 };
83 };
84
85 soc-u9500 {
86
87 sound {
88 compatible = "stericsson,snd-soc-mop500";
89
90 stericsson,cpu-dai = <&msp1 &msp3>;
91 stericsson,audio-codec = <&codec>;
92 };
93
94 msp1: msp@80124000 {
95 status = "okay";
96 };
97
98 msp3: msp@80125000 {
99 status = "okay";
100 };
101
102 prcmu@80157000 {
103 thermal@801573c0 {
104 num-trips = <4>;
105
106 trip0-temp = <70000>;
107 trip0-type = "active";
108 trip0-cdev-num = <1>;
109 trip0-cdev-name0 = "thermal-cpufreq-0";
110
111 trip1-temp = <75000>;
112 trip1-type = "active";
113 trip1-cdev-num = <1>;
114 trip1-cdev-name0 = "thermal-cpufreq-0";
115
116 trip2-temp = <80000>;
117 trip2-type = "active";
118 trip2-cdev-num = <1>;
119 trip2-cdev-name0 = "thermal-cpufreq-0";
120
121 trip3-temp = <85000>;
122 trip3-type = "critical";
123 trip3-cdev-num = <0>;
124
125 status = "okay";
126 };
127 };
128
129 external-bus@50000000 {
130 status = "okay";
131
132 ethernet@0 {
133 compatible = "smsc,lan9115";
134 reg = <0 0x10000>;
135 interrupts = <12 0x1>;
136 interrupt-parent = <&gpio4>;
137 vdd33a-supply = <&en_3v3_reg>;
138 vddvario-supply = <&db8500_vape_reg>;
139
140
141 reg-shift = <1>;
142 reg-io-width = <2>;
143 smsc,force-internal-phy;
144 smsc,irq-active-high;
145 smsc,irq-push-pull;
146 };
147 };
148
149 // External Micro SD slot
150 sdi0_per1@80126000 {
151 arm,primecell-periphid = <0x10480180>;
152 max-frequency = <50000000>;
153 bus-width = <4>;
154 mmc-cap-mmc-highspeed;
155 vmmc-supply = <&ab8500_ldo_aux3_reg>;
156
157 cd-gpios = <&gpio6 26 0x4>; // 218
158 cd-inverted;
159
160 status = "okay";
161 };
162
163 // On-board eMMC
164 sdi4_per2@80114000 {
165 arm,primecell-periphid = <0x10480180>;
166 max-frequency = <50000000>;
167 bus-width = <8>;
168 mmc-cap-mmc-highspeed;
169 vmmc-supply = <&ab8500_ldo_aux2_reg>;
170
171 status = "okay";
172 };
173
174 uart@80120000 {
175 status = "okay";
176 };
177
178 uart@80121000 {
179 status = "okay";
180 };
181
182 uart@80007000 {
183 status = "okay";
184 };
185
186 i2c@80004000 {
187 tc3589x@42 {
188 //compatible = "tc3589x";
189 reg = <0x42>;
190 gpios = <&gpio6 25 0x4>;
191 interrupt-parent = <&gpio6>;
192 };
193 tps61052@33 {
194 //compatible = "tps61052";
195 reg = <0x33>;
196 };
197 };
198
199 i2c@80128000 {
200 lp5521@0x33 {
201 // compatible = "lp5521";
202 reg = <0x33>;
203 };
204 lp5521@0x34 {
205 // compatible = "lp5521";
206 reg = <0x34>;
207 };
208 bh1780@0x29 {
209 // compatible = "rohm,bh1780gli";
210 reg = <0x33>;
211 };
212 };
213
214 cpufreq-cooling {
215 status = "okay";
216 };
217
218 prcmu@80157000 {
219 db8500-prcmu-regulators {
220 db8500_vape_reg: db8500_vape {
221 regulator-name = "db8500-vape";
222 };
223
224 db8500_varm_reg: db8500_varm {
225 regulator-name = "db8500-varm";
226 };
227
228 db8500_vmodem_reg: db8500_vmodem {
229 regulator-name = "db8500-vmodem";
230 };
231
232 db8500_vpll_reg: db8500_vpll {
233 regulator-name = "db8500-vpll";
234 };
235
236 db8500_vsmps1_reg: db8500_vsmps1 {
237 regulator-name = "db8500-vsmps1";
238 };
239
240 db8500_vsmps2_reg: db8500_vsmps2 {
241 regulator-name = "db8500-vsmps2";
242 };
243
244 db8500_vsmps3_reg: db8500_vsmps3 {
245 regulator-name = "db8500-vsmps3";
246 };
247
248 db8500_vrf1_reg: db8500_vrf1 {
249 regulator-name = "db8500-vrf1";
250 };
251
252 db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
253 regulator-name = "db8500-sva-mmdsp";
254 };
255
256 db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
257 regulator-name = "db8500-sva-mmdsp-ret";
258 };
259
260 db8500_sva_pipe_reg: db8500_sva_pipe {
261 regulator-name = "db8500_sva_pipe";
262 };
263
264 db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
265 regulator-name = "db8500_sia_mmdsp";
266 };
267
268 db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
269 regulator-name = "db8500-sia-mmdsp-ret";
270 };
271
272 db8500_sia_pipe_reg: db8500_sia_pipe {
273 regulator-name = "db8500-sia-pipe";
274 };
275
276 db8500_sga_reg: db8500_sga {
277 regulator-name = "db8500-sga";
278 };
279
280 db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
281 regulator-name = "db8500-b2r2-mcde";
282 };
283
284 db8500_esram12_reg: db8500_esram12 {
285 regulator-name = "db8500-esram12";
286 };
287
288 db8500_esram12_ret_reg: db8500_esram12_ret {
289 regulator-name = "db8500-esram12-ret";
290 };
291
292 db8500_esram34_reg: db8500_esram34 {
293 regulator-name = "db8500-esram34";
294 };
295
296 db8500_esram34_ret_reg: db8500_esram34_ret {
297 regulator-name = "db8500-esram34-ret";
298 };
299 };
300
301 ab8500@5 {
302 ab8500-regulators {
303 ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
304 regulator-name = "V-DISPLAY";
305 };
306
307 ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
308 regulator-name = "V-eMMC1";
309 };
310
311 ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
312 regulator-name = "V-MMC-SD";
313 };
314
315 ab8500_ldo_initcore_reg: ab8500_ldo_initcore {
316 regulator-name = "V-INTCORE";
317 };
318
319 ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
320 regulator-name = "V-TVOUT";
321 };
322
323 ab8500_ldo_usb_reg: ab8500_ldo_usb {
324 regulator-name = "dummy";
325 };
326
327 ab8500_ldo_audio_reg: ab8500_ldo_audio {
328 regulator-name = "V-AUD";
329 };
330
331 ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
332 regulator-name = "V-AMIC1";
333 };
334
335 ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
336 regulator-name = "V-AMIC2";
337 };
338
339 ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
340 regulator-name = "V-DMIC";
341 };
342
343 ab8500_ldo_ana_reg: ab8500_ldo_ana {
344 regulator-name = "V-CSI/DSI";
345 };
346 };
347 };
348 };
349 };
350};
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
deleted file mode 100644
index 19aec421bb2..00000000000
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ /dev/null
@@ -1,157 +0,0 @@
1/*
2 * Copyright (C) 2012 Altera <www.altera.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18/include/ "skeleton.dtsi"
19
20/ {
21 #address-cells = <1>;
22 #size-cells = <1>;
23
24 aliases {
25 ethernet0 = &gmac0;
26 serial0 = &uart0;
27 serial1 = &uart1;
28 };
29
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33
34 cpu@0 {
35 compatible = "arm,cortex-a9";
36 device_type = "cpu";
37 reg = <0>;
38 next-level-cache = <&L2>;
39 };
40 cpu@1 {
41 compatible = "arm,cortex-a9";
42 device_type = "cpu";
43 reg = <1>;
44 next-level-cache = <&L2>;
45 };
46 };
47
48 intc: intc@fffed000 {
49 compatible = "arm,cortex-a9-gic";
50 #interrupt-cells = <3>;
51 interrupt-controller;
52 reg = <0xfffed000 0x1000>,
53 <0xfffec100 0x100>;
54 };
55
56 soc {
57 #address-cells = <1>;
58 #size-cells = <1>;
59 compatible = "simple-bus";
60 device_type = "soc";
61 interrupt-parent = <&intc>;
62 ranges;
63
64 amba {
65 compatible = "arm,amba-bus";
66 #address-cells = <1>;
67 #size-cells = <1>;
68 ranges;
69
70 pdma: pdma@ffe01000 {
71 compatible = "arm,pl330", "arm,primecell";
72 reg = <0xffe01000 0x1000>;
73 interrupts = <0 180 4>;
74 };
75 };
76
77 gmac0: stmmac@ff700000 {
78 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
79 reg = <0xff700000 0x2000>;
80 interrupts = <0 115 4>;
81 interrupt-names = "macirq";
82 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
83 phy-mode = "gmii";
84 };
85
86 L2: l2-cache@fffef000 {
87 compatible = "arm,pl310-cache";
88 reg = <0xfffef000 0x1000>;
89 interrupts = <0 38 0x04>;
90 cache-unified;
91 cache-level = <2>;
92 };
93
94 /* Local timer */
95 timer@fffec600 {
96 compatible = "arm,cortex-a9-twd-timer";
97 reg = <0xfffec600 0x100>;
98 interrupts = <1 13 0xf04>;
99 };
100
101 timer0: timer@ffc08000 {
102 compatible = "snps,dw-apb-timer-sp";
103 interrupts = <0 167 4>;
104 clock-frequency = <200000000>;
105 reg = <0xffc08000 0x1000>;
106 };
107
108 timer1: timer@ffc09000 {
109 compatible = "snps,dw-apb-timer-sp";
110 interrupts = <0 168 4>;
111 clock-frequency = <200000000>;
112 reg = <0xffc09000 0x1000>;
113 };
114
115 timer2: timer@ffd00000 {
116 compatible = "snps,dw-apb-timer-osc";
117 interrupts = <0 169 4>;
118 clock-frequency = <200000000>;
119 reg = <0xffd00000 0x1000>;
120 };
121
122 timer3: timer@ffd01000 {
123 compatible = "snps,dw-apb-timer-osc";
124 interrupts = <0 170 4>;
125 clock-frequency = <200000000>;
126 reg = <0xffd01000 0x1000>;
127 };
128
129 uart0: uart@ffc02000 {
130 compatible = "snps,dw-apb-uart";
131 reg = <0xffc02000 0x1000>;
132 clock-frequency = <7372800>;
133 interrupts = <0 162 4>;
134 reg-shift = <2>;
135 reg-io-width = <4>;
136 };
137
138 uart1: uart@ffc03000 {
139 compatible = "snps,dw-apb-uart";
140 reg = <0xffc03000 0x1000>;
141 clock-frequency = <7372800>;
142 interrupts = <0 163 4>;
143 reg-shift = <2>;
144 reg-io-width = <4>;
145 };
146
147 rstmgr@ffd05000 {
148 compatible = "altr,rst-mgr";
149 reg = <0xffd05000 0x1000>;
150 };
151
152 sysmgr@ffd08000 {
153 compatible = "altr,sys-mgr";
154 reg = <0xffd08000 0x4000>;
155 };
156 };
157};
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts
deleted file mode 100644
index ab7e4a94299..00000000000
--- a/arch/arm/boot/dts/socfpga_cyclone5.dts
+++ /dev/null
@@ -1,34 +0,0 @@
1/*
2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18/dts-v1/;
19/include/ "socfpga.dtsi"
20
21/ {
22 model = "Altera SOCFPGA Cyclone V";
23 compatible = "altr,socfpga-cyclone5";
24
25 chosen {
26 bootargs = "console=ttyS0,57600";
27 };
28
29 memory {
30 name = "memory";
31 device_type = "memory";
32 reg = <0x0 0x10000000>; /* 256MB */
33 };
34};
diff --git a/arch/arm/boot/dts/spear1310-evb.dts b/arch/arm/boot/dts/spear1310-evb.dts
deleted file mode 100644
index b56a801e42a..00000000000
--- a/arch/arm/boot/dts/spear1310-evb.dts
+++ /dev/null
@@ -1,423 +0,0 @@
1/*
2 * DTS file for SPEAr1310 Evaluation Baord
3 *
4 * Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "spear1310.dtsi"
16
17/ {
18 model = "ST SPEAr1310 Evaluation Board";
19 compatible = "st,spear1310-evb", "st,spear1310";
20 #address-cells = <1>;
21 #size-cells = <1>;
22
23 memory {
24 reg = <0 0x40000000>;
25 };
26
27 ahb {
28 pinmux@e0700000 {
29 pinctrl-names = "default";
30 pinctrl-0 = <&state_default>;
31
32 state_default: pinmux {
33 i2c0 {
34 st,pins = "i2c0_grp";
35 st,function = "i2c0";
36 };
37 i2s0 {
38 st,pins = "i2s0_grp";
39 st,function = "i2s0";
40 };
41 i2s1 {
42 st,pins = "i2s1_grp";
43 st,function = "i2s1";
44 };
45 gpio {
46 st,pins = "arm_gpio_grp";
47 st,function = "arm_gpio";
48 };
49 clcd {
50 st,pins = "clcd_grp" , "clcd_high_res";
51 st,function = "clcd";
52 };
53 eth {
54 st,pins = "gmii_grp";
55 st,function = "gmii";
56 };
57 ssp0 {
58 st,pins = "ssp0_grp";
59 st,function = "ssp0";
60 };
61 kbd {
62 st,pins = "keyboard_6x6_grp";
63 st,function = "keyboard";
64 };
65 sdhci {
66 st,pins = "sdhci_grp";
67 st,function = "sdhci";
68 };
69 smi-pmx {
70 st,pins = "smi_2_chips_grp";
71 st,function = "smi";
72 };
73 uart0 {
74 st,pins = "uart0_grp";
75 st,function = "uart0";
76 };
77 rs485 {
78 st,pins = "rs485_0_1_tdm_0_1_grp";
79 st,function = "rs485_0_1_tdm_0_1";
80 };
81 i2c1_2 {
82 st,pins = "i2c_1_2_grp";
83 st,function = "i2c_1_2";
84 };
85 smii {
86 st,pins = "smii_0_1_2_grp";
87 st,function = "smii_0_1_2";
88 };
89 nand {
90 st,pins = "nand_8bit_grp",
91 "nand_16bit_grp";
92 st,function = "nand";
93 };
94 sata {
95 st,pins = "sata0_grp";
96 st,function = "sata";
97 };
98 pcie {
99 st,pins = "pcie1_grp", "pcie2_grp";
100 st,function = "pci_express";
101 };
102 };
103 };
104
105 ahci@b1000000 {
106 status = "okay";
107 };
108
109 cf@b2800000 {
110 status = "okay";
111 };
112
113 dma@ea800000 {
114 status = "okay";
115 };
116
117 dma@eb000000 {
118 status = "okay";
119 };
120
121 fsmc: flash@b0000000 {
122 status = "okay";
123
124 partition@0 {
125 label = "xloader";
126 reg = <0x0 0x80000>;
127 };
128 partition@80000 {
129 label = "u-boot";
130 reg = <0x80000 0x140000>;
131 };
132 partition@1C0000 {
133 label = "environment";
134 reg = <0x1C0000 0x40000>;
135 };
136 partition@200000 {
137 label = "dtb";
138 reg = <0x200000 0x40000>;
139 };
140 partition@240000 {
141 label = "linux";
142 reg = <0x240000 0xC00000>;
143 };
144 partition@E40000 {
145 label = "rootfs";
146 reg = <0xE40000 0x0>;
147 };
148 };
149
150 gpio_keys {
151 compatible = "gpio-keys";
152 #address-cells = <1>;
153 #size-cells = <0>;
154
155 button@1 {
156 label = "wakeup";
157 linux,code = <0x100>;
158 gpios = <&gpio0 7 0x4>;
159 debounce-interval = <20>;
160 gpio-key,wakeup = <1>;
161 };
162 };
163
164 gmac0: eth@e2000000 {
165 phy-mode = "gmii";
166 status = "okay";
167 };
168
169 sdhci@b3000000 {
170 status = "okay";
171 };
172
173 smi: flash@ea000000 {
174 status = "okay";
175 clock-rate=<50000000>;
176
177 flash@e6000000 {
178 #address-cells = <1>;
179 #size-cells = <1>;
180 reg = <0xe6000000 0x800000>;
181 st,smi-fast-mode;
182
183 partition@0 {
184 label = "xloader";
185 reg = <0x0 0x10000>;
186 };
187 partition@10000 {
188 label = "u-boot";
189 reg = <0x10000 0x50000>;
190 };
191 partition@60000 {
192 label = "environment";
193 reg = <0x60000 0x10000>;
194 };
195 partition@70000 {
196 label = "dtb";
197 reg = <0x70000 0x10000>;
198 };
199 partition@80000 {
200 label = "linux";
201 reg = <0x80000 0x310000>;
202 };
203 partition@390000 {
204 label = "rootfs";
205 reg = <0x390000 0x0>;
206 };
207 };
208 };
209
210 ehci@e4800000 {
211 status = "okay";
212 };
213
214 ehci@e5800000 {
215 status = "okay";
216 };
217
218 ohci@e4000000 {
219 status = "okay";
220 };
221
222 ohci@e5000000 {
223 status = "okay";
224 };
225
226 apb {
227 adc@e0080000 {
228 status = "okay";
229 };
230
231 gpio0: gpio@e0600000 {
232 status = "okay";
233 };
234
235 gpio1: gpio@e0680000 {
236 status = "okay";
237 };
238
239 gpio@d8400000 {
240 status = "okay";
241 };
242
243 i2c0: i2c@e0280000 {
244 status = "okay";
245 };
246
247 kbd@e0300000 {
248 linux,keymap = < 0x00000001
249 0x00010002
250 0x00020003
251 0x00030004
252 0x00040005
253 0x00050006
254 0x00060007
255 0x00070008
256 0x00080009
257 0x0100000a
258 0x0101000c
259 0x0102000d
260 0x0103000e
261 0x0104000f
262 0x01050010
263 0x01060011
264 0x01070012
265 0x01080013
266 0x02000014
267 0x02010015
268 0x02020016
269 0x02030017
270 0x02040018
271 0x02050019
272 0x0206001a
273 0x0207001b
274 0x0208001c
275 0x0300001d
276 0x0301001e
277 0x0302001f
278 0x03030020
279 0x03040021
280 0x03050022
281 0x03060023
282 0x03070024
283 0x03080025
284 0x04000026
285 0x04010027
286 0x04020028
287 0x04030029
288 0x0404002a
289 0x0405002b
290 0x0406002c
291 0x0407002d
292 0x0408002e
293 0x0500002f
294 0x05010030
295 0x05020031
296 0x05030032
297 0x05040033
298 0x05050034
299 0x05060035
300 0x05070036
301 0x05080037
302 0x06000038
303 0x06010039
304 0x0602003a
305 0x0603003b
306 0x0604003c
307 0x0605003d
308 0x0606003e
309 0x0607003f
310 0x06080040
311 0x07000041
312 0x07010042
313 0x07020043
314 0x07030044
315 0x07040045
316 0x07050046
317 0x07060047
318 0x07070048
319 0x07080049
320 0x0800004a
321 0x0801004b
322 0x0802004c
323 0x0803004d
324 0x0804004e
325 0x0805004f
326 0x08060050
327 0x08070051
328 0x08080052 >;
329 autorepeat;
330 st,mode = <0>;
331 suspended_rate = <2000000>;
332 status = "okay";
333 };
334
335 rtc@e0580000 {
336 status = "okay";
337 };
338
339 serial@e0000000 {
340 status = "okay";
341 pinctrl-names = "default";
342 pinctrl-0 = <>;
343 };
344
345 spi0: spi@e0100000 {
346 status = "okay";
347 num-cs = <3>;
348 cs-gpios = <&gpio1 7 0>, <&spics 0>, <&spics 1>;
349
350 stmpe610@0 {
351 compatible = "st,stmpe610";
352 reg = <0>;
353 #address-cells = <1>;
354 #size-cells = <0>;
355 spi-max-frequency = <1000000>;
356 spi-cpha;
357 pl022,hierarchy = <0>;
358 pl022,interface = <0>;
359 pl022,slave-tx-disable;
360 pl022,com-mode = <0>;
361 pl022,rx-level-trig = <0>;
362 pl022,tx-level-trig = <0>;
363 pl022,ctrl-len = <0x7>;
364 pl022,wait-state = <0>;
365 pl022,duplex = <0>;
366 interrupts = <6 0x4>;
367 interrupt-parent = <&gpio1>;
368 irq-trigger = <0x2>;
369
370 stmpe_touchscreen {
371 compatible = "st,stmpe-ts";
372 ts,sample-time = <4>;
373 ts,mod-12b = <1>;
374 ts,ref-sel = <0>;
375 ts,adc-freq = <1>;
376 ts,ave-ctrl = <1>;
377 ts,touch-det-delay = <2>;
378 ts,settling = <2>;
379 ts,fraction-z = <7>;
380 ts,i-drive = <1>;
381 };
382 };
383
384 m25p80@1 {
385 compatible = "st,m25p80";
386 reg = <1>;
387 spi-max-frequency = <12000000>;
388 spi-cpol;
389 spi-cpha;
390 pl022,hierarchy = <0>;
391 pl022,interface = <0>;
392 pl022,slave-tx-disable;
393 pl022,com-mode = <0x2>;
394 pl022,rx-level-trig = <0>;
395 pl022,tx-level-trig = <0>;
396 pl022,ctrl-len = <0x11>;
397 pl022,wait-state = <0>;
398 pl022,duplex = <0>;
399 };
400
401 spidev@2 {
402 compatible = "spidev";
403 reg = <2>;
404 spi-max-frequency = <25000000>;
405 spi-cpha;
406 pl022,hierarchy = <0>;
407 pl022,interface = <0>;
408 pl022,slave-tx-disable;
409 pl022,com-mode = <0x2>;
410 pl022,rx-level-trig = <0>;
411 pl022,tx-level-trig = <0>;
412 pl022,ctrl-len = <0x11>;
413 pl022,wait-state = <0>;
414 pl022,duplex = <0>;
415 };
416 };
417
418 wdt@ec800620 {
419 status = "okay";
420 };
421 };
422 };
423};
diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi
deleted file mode 100644
index 1513c1927cc..00000000000
--- a/arch/arm/boot/dts/spear1310.dtsi
+++ /dev/null
@@ -1,229 +0,0 @@
1/*
2 * DTS file for all SPEAr1310 SoCs
3 *
4 * Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "spear13xx.dtsi"
15
16/ {
17 compatible = "st,spear1310";
18
19 ahb {
20 spics: spics@e0700000{
21 compatible = "st,spear-spics-gpio";
22 reg = <0xe0700000 0x1000>;
23 st-spics,peripcfg-reg = <0x3b0>;
24 st-spics,sw-enable-bit = <12>;
25 st-spics,cs-value-bit = <11>;
26 st-spics,cs-enable-mask = <3>;
27 st-spics,cs-enable-shift = <8>;
28 gpio-controller;
29 #gpio-cells = <2>;
30 };
31
32 ahci@b1000000 {
33 compatible = "snps,spear-ahci";
34 reg = <0xb1000000 0x10000>;
35 interrupts = <0 68 0x4>;
36 status = "disabled";
37 };
38
39 ahci@b1800000 {
40 compatible = "snps,spear-ahci";
41 reg = <0xb1800000 0x10000>;
42 interrupts = <0 69 0x4>;
43 status = "disabled";
44 };
45
46 ahci@b4000000 {
47 compatible = "snps,spear-ahci";
48 reg = <0xb4000000 0x10000>;
49 interrupts = <0 70 0x4>;
50 status = "disabled";
51 };
52
53 gmac1: eth@5c400000 {
54 compatible = "st,spear600-gmac";
55 reg = <0x5c400000 0x8000>;
56 interrupts = <0 95 0x4>;
57 interrupt-names = "macirq";
58 phy-mode = "mii";
59 status = "disabled";
60 };
61
62 gmac2: eth@5c500000 {
63 compatible = "st,spear600-gmac";
64 reg = <0x5c500000 0x8000>;
65 interrupts = <0 96 0x4>;
66 interrupt-names = "macirq";
67 phy-mode = "mii";
68 status = "disabled";
69 };
70
71 gmac3: eth@5c600000 {
72 compatible = "st,spear600-gmac";
73 reg = <0x5c600000 0x8000>;
74 interrupts = <0 97 0x4>;
75 interrupt-names = "macirq";
76 phy-mode = "rmii";
77 status = "disabled";
78 };
79
80 gmac4: eth@5c700000 {
81 compatible = "st,spear600-gmac";
82 reg = <0x5c700000 0x8000>;
83 interrupts = <0 98 0x4>;
84 interrupt-names = "macirq";
85 phy-mode = "rgmii";
86 status = "disabled";
87 };
88
89 pinmux: pinmux@e0700000 {
90 compatible = "st,spear1310-pinmux";
91 reg = <0xe0700000 0x1000>;
92 #gpio-range-cells = <2>;
93 };
94
95 apb {
96 i2c1: i2c@5cd00000 {
97 #address-cells = <1>;
98 #size-cells = <0>;
99 compatible = "snps,designware-i2c";
100 reg = <0x5cd00000 0x1000>;
101 interrupts = <0 87 0x4>;
102 status = "disabled";
103 };
104
105 i2c2: i2c@5ce00000 {
106 #address-cells = <1>;
107 #size-cells = <0>;
108 compatible = "snps,designware-i2c";
109 reg = <0x5ce00000 0x1000>;
110 interrupts = <0 88 0x4>;
111 status = "disabled";
112 };
113
114 i2c3: i2c@5cf00000 {
115 #address-cells = <1>;
116 #size-cells = <0>;
117 compatible = "snps,designware-i2c";
118 reg = <0x5cf00000 0x1000>;
119 interrupts = <0 89 0x4>;
120 status = "disabled";
121 };
122
123 i2c4: i2c@5d000000 {
124 #address-cells = <1>;
125 #size-cells = <0>;
126 compatible = "snps,designware-i2c";
127 reg = <0x5d000000 0x1000>;
128 interrupts = <0 90 0x4>;
129 status = "disabled";
130 };
131
132 i2c5: i2c@5d100000 {
133 #address-cells = <1>;
134 #size-cells = <0>;
135 compatible = "snps,designware-i2c";
136 reg = <0x5d100000 0x1000>;
137 interrupts = <0 91 0x4>;
138 status = "disabled";
139 };
140
141 i2c6: i2c@5d200000 {
142 #address-cells = <1>;
143 #size-cells = <0>;
144 compatible = "snps,designware-i2c";
145 reg = <0x5d200000 0x1000>;
146 interrupts = <0 92 0x4>;
147 status = "disabled";
148 };
149
150 i2c7: i2c@5d300000 {
151 #address-cells = <1>;
152 #size-cells = <0>;
153 compatible = "snps,designware-i2c";
154 reg = <0x5d300000 0x1000>;
155 interrupts = <0 93 0x4>;
156 status = "disabled";
157 };
158
159 spi1: spi@5d400000 {
160 compatible = "arm,pl022", "arm,primecell";
161 reg = <0x5d400000 0x1000>;
162 interrupts = <0 99 0x4>;
163 #address-cells = <1>;
164 #size-cells = <0>;
165 status = "disabled";
166 };
167
168 serial@5c800000 {
169 compatible = "arm,pl011", "arm,primecell";
170 reg = <0x5c800000 0x1000>;
171 interrupts = <0 82 0x4>;
172 status = "disabled";
173 };
174
175 serial@5c900000 {
176 compatible = "arm,pl011", "arm,primecell";
177 reg = <0x5c900000 0x1000>;
178 interrupts = <0 83 0x4>;
179 status = "disabled";
180 };
181
182 serial@5ca00000 {
183 compatible = "arm,pl011", "arm,primecell";
184 reg = <0x5ca00000 0x1000>;
185 interrupts = <0 84 0x4>;
186 status = "disabled";
187 };
188
189 serial@5cb00000 {
190 compatible = "arm,pl011", "arm,primecell";
191 reg = <0x5cb00000 0x1000>;
192 interrupts = <0 85 0x4>;
193 status = "disabled";
194 };
195
196 serial@5cc00000 {
197 compatible = "arm,pl011", "arm,primecell";
198 reg = <0x5cc00000 0x1000>;
199 interrupts = <0 86 0x4>;
200 status = "disabled";
201 };
202
203 thermal@e07008c4 {
204 st,thermal-flags = <0x7000>;
205 };
206
207 gpiopinctrl: gpio@d8400000 {
208 compatible = "st,spear-plgpio";
209 reg = <0xd8400000 0x1000>;
210 interrupts = <0 100 0x4>;
211 #interrupt-cells = <1>;
212 interrupt-controller;
213 gpio-controller;
214 #gpio-cells = <2>;
215 gpio-ranges = <&pinmux 0 246>;
216 status = "disabled";
217
218 st-plgpio,ngpio = <246>;
219 st-plgpio,enb-reg = <0xd0>;
220 st-plgpio,wdata-reg = <0x90>;
221 st-plgpio,dir-reg = <0xb0>;
222 st-plgpio,ie-reg = <0x30>;
223 st-plgpio,rdata-reg = <0x70>;
224 st-plgpio,mis-reg = <0x10>;
225 st-plgpio,eit-reg = <0x50>;
226 };
227 };
228 };
229};
diff --git a/arch/arm/boot/dts/spear1340-evb.dts b/arch/arm/boot/dts/spear1340-evb.dts
deleted file mode 100644
index d6c30ae0a8d..00000000000
--- a/arch/arm/boot/dts/spear1340-evb.dts
+++ /dev/null
@@ -1,521 +0,0 @@
1/*
2 * DTS file for SPEAr1340 Evaluation Baord
3 *
4 * Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "spear1340.dtsi"
16
17/ {
18 model = "ST SPEAr1340 Evaluation Board";
19 compatible = "st,spear1340-evb", "st,spear1340";
20 #address-cells = <1>;
21 #size-cells = <1>;
22
23 memory {
24 reg = <0 0x40000000>;
25 };
26
27 ahb {
28 pinmux@e0700000 {
29 pinctrl-names = "default";
30 pinctrl-0 = <&state_default>;
31
32 state_default: pinmux {
33 pads_as_gpio {
34 st,pins = "pads_as_gpio_grp";
35 st,function = "pads_as_gpio";
36 };
37 fsmc {
38 st,pins = "fsmc_8bit_grp";
39 st,function = "fsmc";
40 };
41 uart0 {
42 st,pins = "uart0_grp";
43 st,function = "uart0";
44 };
45 i2c0 {
46 st,pins = "i2c0_grp";
47 st,function = "i2c0";
48 };
49 i2c1 {
50 st,pins = "i2c1_grp";
51 st,function = "i2c1";
52 };
53 spdif-in {
54 st,pins = "spdif_in_grp";
55 st,function = "spdif_in";
56 };
57 spdif-out {
58 st,pins = "spdif_out_grp";
59 st,function = "spdif_out";
60 };
61 ssp0 {
62 st,pins = "ssp0_grp", "ssp0_cs1_grp", "ssp0_cs2_grp", "ssp0_cs3_grp";
63 st,function = "ssp0";
64 };
65 smi-pmx {
66 st,pins = "smi_grp";
67 st,function = "smi";
68 };
69 i2s {
70 st,pins = "i2s_in_grp", "i2s_out_grp";
71 st,function = "i2s";
72 };
73 gmac {
74 st,pins = "gmii_grp", "rgmii_grp";
75 st,function = "gmac";
76 };
77 cam0 {
78 st,pins = "cam0_grp";
79 st,function = "cam0";
80 };
81 cam1 {
82 st,pins = "cam1_grp";
83 st,function = "cam1";
84 };
85 cam2 {
86 st,pins = "cam2_grp";
87 st,function = "cam2";
88 };
89 cam3 {
90 st,pins = "cam3_grp";
91 st,function = "cam3";
92 };
93 cec0 {
94 st,pins = "cec0_grp";
95 st,function = "cec0";
96 };
97 cec1 {
98 st,pins = "cec1_grp";
99 st,function = "cec1";
100 };
101 sdhci {
102 st,pins = "sdhci_grp";
103 st,function = "sdhci";
104 };
105 clcd {
106 st,pins = "clcd_grp";
107 st,function = "clcd";
108 };
109 sata {
110 st,pins = "sata_grp";
111 st,function = "sata";
112 };
113 pcie {
114 st,pins = "pcie_grp";
115 st,function = "pcie";
116 };
117
118 };
119 };
120
121 ahci@b1000000 {
122 status = "okay";
123 };
124
125 dma@ea800000 {
126 status = "okay";
127 };
128
129 dma@eb000000 {
130 status = "okay";
131 };
132
133 fsmc: flash@b0000000 {
134 status = "okay";
135
136 partition@0 {
137 label = "xloader";
138 reg = <0x0 0x200000>;
139 };
140 partition@200000 {
141 label = "u-boot";
142 reg = <0x200000 0x200000>;
143 };
144 partition@400000 {
145 label = "environment";
146 reg = <0x400000 0x100000>;
147 };
148 partition@500000 {
149 label = "dtb";
150 reg = <0x500000 0x100000>;
151 };
152 partition@600000 {
153 label = "linux";
154 reg = <0x600000 0xC00000>;
155 };
156 partition@1200000 {
157 label = "rootfs";
158 reg = <0x1200000 0x0>;
159 };
160 };
161
162 gmac0: eth@e2000000 {
163 phy-mode = "rgmii";
164 status = "okay";
165 };
166
167 sdhci@b3000000 {
168 status = "okay";
169 };
170
171 smi: flash@ea000000 {
172 status = "okay";
173 clock-rate=<50000000>;
174
175 flash@e6000000 {
176 #address-cells = <1>;
177 #size-cells = <1>;
178 reg = <0xe6000000 0x800000>;
179 st,smi-fast-mode;
180
181 partition@0 {
182 label = "xloader";
183 reg = <0x0 0x10000>;
184 };
185 partition@10000 {
186 label = "u-boot";
187 reg = <0x10000 0x50000>;
188 };
189 partition@60000 {
190 label = "environment";
191 reg = <0x60000 0x10000>;
192 };
193 partition@70000 {
194 label = "dtb";
195 reg = <0x70000 0x10000>;
196 };
197 partition@80000 {
198 label = "linux";
199 reg = <0x80000 0x310000>;
200 };
201 partition@390000 {
202 label = "rootfs";
203 reg = <0x390000 0x0>;
204 };
205 };
206 };
207
208 ehci@e4800000 {
209 status = "okay";
210 };
211
212 gpio_keys {
213 compatible = "gpio-keys";
214 #address-cells = <1>;
215 #size-cells = <0>;
216
217 button@1 {
218 label = "wakeup";
219 linux,code = <0x100>;
220 gpios = <&gpio1 1 0x4>;
221 debounce-interval = <20>;
222 gpio-key,wakeup = <1>;
223 };
224 };
225
226 ehci@e5800000 {
227 status = "okay";
228 };
229
230 i2s0: i2s-play@b2400000 {
231 status = "okay";
232 };
233
234 i2s1: i2s-rec@b2000000 {
235 status = "okay";
236 };
237
238 incodec: dir-hifi {
239 compatible = "dummy,dir-hifi";
240 status = "okay";
241 };
242
243 ohci@e4000000 {
244 status = "okay";
245 };
246
247 ohci@e5000000 {
248 status = "okay";
249 };
250
251 outcodec: dit-hifi {
252 compatible = "dummy,dit-hifi";
253 status = "okay";
254 };
255
256 sound {
257 compatible = "spear,spear-evb";
258 audio-controllers = <&spdif0 &spdif1 &i2s0 &i2s1>;
259 audio-codecs = <&incodec &outcodec &sta529 &sta529>;
260 codec_dai_name = "dir-hifi", "dit-hifi", "sta529-audio", "sta529-audio";
261 stream_name = "spdif-cap", "spdif-play", "i2s-play", "i2s-cap";
262 dai_name = "spdifin-pcm", "spdifout-pcm", "i2s0-pcm", "i2s1-pcm";
263 nr_controllers = <4>;
264 status = "okay";
265 };
266
267 spdif0: spdif-in@d0100000 {
268 status = "okay";
269 };
270
271 spdif1: spdif-out@d0000000 {
272 status = "okay";
273 };
274
275 apb {
276 adc@e0080000 {
277 status = "okay";
278 };
279
280 i2s-play@b2400000 {
281 status = "okay";
282 };
283
284 i2s-rec@b2000000 {
285 status = "okay";
286 };
287
288 gpio0: gpio@e0600000 {
289 status = "okay";
290 };
291
292 gpio1: gpio@e0680000 {
293 status = "okay";
294 };
295
296 gpio@e2800000 {
297 status = "okay";
298 };
299
300 i2c0: i2c@e0280000 {
301 status = "okay";
302
303 sta529: sta529@1a {
304 compatible = "st,sta529";
305 reg = <0x1a>;
306 };
307 };
308
309 i2c1: i2c@b4000000 {
310 status = "okay";
311
312 eeprom0@56 {
313 compatible = "st,eeprom";
314 reg = <0x56>;
315 };
316
317 stmpe801@41 {
318 compatible = "st,stmpe801";
319 #address-cells = <1>;
320 #size-cells = <0>;
321 reg = <0x41>;
322 interrupts = <4 0x4>;
323 interrupt-parent = <&gpio0>;
324 irq-trigger = <0x2>;
325
326 stmpegpio: stmpe_gpio {
327 compatible = "st,stmpe-gpio";
328 gpio-controller;
329 #gpio-cells = <2>;
330 };
331 };
332 };
333
334 kbd@e0300000 {
335 linux,keymap = < 0x00000001
336 0x00010002
337 0x00020003
338 0x00030004
339 0x00040005
340 0x00050006
341 0x00060007
342 0x00070008
343 0x00080009
344 0x0100000a
345 0x0101000c
346 0x0102000d
347 0x0103000e
348 0x0104000f
349 0x01050010
350 0x01060011
351 0x01070012
352 0x01080013
353 0x02000014
354 0x02010015
355 0x02020016
356 0x02030017
357 0x02040018
358 0x02050019
359 0x0206001a
360 0x0207001b
361 0x0208001c
362 0x0300001d
363 0x0301001e
364 0x0302001f
365 0x03030020
366 0x03040021
367 0x03050022
368 0x03060023
369 0x03070024
370 0x03080025
371 0x04000026
372 0x04010027
373 0x04020028
374 0x04030029
375 0x0404002a
376 0x0405002b
377 0x0406002c
378 0x0407002d
379 0x0408002e
380 0x0500002f
381 0x05010030
382 0x05020031
383 0x05030032
384 0x05040033
385 0x05050034
386 0x05060035
387 0x05070036
388 0x05080037
389 0x06000038
390 0x06010039
391 0x0602003a
392 0x0603003b
393 0x0604003c
394 0x0605003d
395 0x0606003e
396 0x0607003f
397 0x06080040
398 0x07000041
399 0x07010042
400 0x07020043
401 0x07030044
402 0x07040045
403 0x07050046
404 0x07060047
405 0x07070048
406 0x07080049
407 0x0800004a
408 0x0801004b
409 0x0802004c
410 0x0803004d
411 0x0804004e
412 0x0805004f
413 0x08060050
414 0x08070051
415 0x08080052 >;
416 autorepeat;
417 st,mode = <0>;
418 suspended_rate = <2000000>;
419 status = "okay";
420 };
421
422 rtc@e0580000 {
423 status = "okay";
424 };
425
426 serial@e0000000 {
427 status = "okay";
428 pinctrl-names = "default";
429 pinctrl-0 = <>;
430 };
431
432 serial@b4100000 {
433 status = "okay";
434 pinctrl-names = "default";
435 pinctrl-0 = <>;
436 };
437
438 spi0: spi@e0100000 {
439 status = "okay";
440 num-cs = <3>;
441 cs-gpios = <&gpiopinctrl 80 0>, <&gpiopinctrl 24 0>,
442 <&gpiopinctrl 85 0>;
443
444 m25p80@0 {
445 compatible = "m25p80";
446 reg = <0>;
447 spi-max-frequency = <12000000>;
448 spi-cpol;
449 spi-cpha;
450 pl022,hierarchy = <0>;
451 pl022,interface = <0>;
452 pl022,slave-tx-disable;
453 pl022,com-mode = <0x2>;
454 pl022,rx-level-trig = <0>;
455 pl022,tx-level-trig = <0>;
456 pl022,ctrl-len = <0x11>;
457 pl022,wait-state = <0>;
458 pl022,duplex = <0>;
459 };
460
461 stmpe610@1 {
462 compatible = "st,stmpe610";
463 spi-max-frequency = <1000000>;
464 spi-cpha;
465 reg = <1>;
466 pl022,hierarchy = <0>;
467 pl022,interface = <0>;
468 pl022,slave-tx-disable;
469 pl022,com-mode = <0>;
470 pl022,rx-level-trig = <0>;
471 pl022,tx-level-trig = <0>;
472 pl022,ctrl-len = <0x7>;
473 pl022,wait-state = <0>;
474 pl022,duplex = <0>;
475 interrupts = <100 0>;
476 interrupt-parent = <&gpiopinctrl>;
477 irq-trigger = <0x2>;
478 #address-cells = <1>;
479 #size-cells = <0>;
480
481 stmpe_touchscreen {
482 compatible = "st,stmpe-ts";
483 ts,sample-time = <4>;
484 ts,mod-12b = <1>;
485 ts,ref-sel = <0>;
486 ts,adc-freq = <1>;
487 ts,ave-ctrl = <1>;
488 ts,touch-det-delay = <2>;
489 ts,settling = <2>;
490 ts,fraction-z = <7>;
491 ts,i-drive = <1>;
492 };
493 };
494
495 spidev@2 {
496 compatible = "spidev";
497 reg = <2>;
498 spi-max-frequency = <25000000>;
499 spi-cpha;
500 pl022,hierarchy = <0>;
501 pl022,interface = <0>;
502 pl022,slave-tx-disable;
503 pl022,com-mode = <0x2>;
504 pl022,rx-level-trig = <0>;
505 pl022,tx-level-trig = <0>;
506 pl022,ctrl-len = <0x11>;
507 pl022,wait-state = <0>;
508 pl022,duplex = <0>;
509 };
510 };
511
512 timer@ec800600 {
513 status = "okay";
514 };
515
516 wdt@ec800620 {
517 status = "okay";
518 };
519 };
520 };
521};
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
deleted file mode 100644
index 34da11aa679..00000000000
--- a/arch/arm/boot/dts/spear1340.dtsi
+++ /dev/null
@@ -1,143 +0,0 @@
1/*
2 * DTS file for all SPEAr1340 SoCs
3 *
4 * Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "spear13xx.dtsi"
15
16/ {
17 compatible = "st,spear1340";
18
19 ahb {
20
21 spics: spics@e0700000{
22 compatible = "st,spear-spics-gpio";
23 reg = <0xe0700000 0x1000>;
24 st-spics,peripcfg-reg = <0x42c>;
25 st-spics,sw-enable-bit = <21>;
26 st-spics,cs-value-bit = <20>;
27 st-spics,cs-enable-mask = <3>;
28 st-spics,cs-enable-shift = <18>;
29 gpio-controller;
30 #gpio-cells = <2>;
31 status = "disabled";
32 };
33
34 ahci@b1000000 {
35 compatible = "snps,spear-ahci";
36 reg = <0xb1000000 0x10000>;
37 interrupts = <0 72 0x4>;
38 status = "disabled";
39 };
40
41 i2s-play@b2400000 {
42 compatible = "snps,designware-i2s";
43 reg = <0xb2400000 0x10000>;
44 interrupt-names = "play_irq";
45 interrupts = <0 98 0x4
46 0 99 0x4>;
47 play;
48 channel = <8>;
49 status = "disabled";
50 };
51
52 i2s-rec@b2000000 {
53 compatible = "snps,designware-i2s";
54 reg = <0xb2000000 0x10000>;
55 interrupt-names = "record_irq";
56 interrupts = <0 100 0x4
57 0 101 0x4>;
58 record;
59 channel = <8>;
60 status = "disabled";
61 };
62
63 pinmux: pinmux@e0700000 {
64 compatible = "st,spear1340-pinmux";
65 reg = <0xe0700000 0x1000>;
66 #gpio-range-cells = <2>;
67 };
68
69 pwm: pwm@e0180000 {
70 compatible ="st,spear13xx-pwm";
71 reg = <0xe0180000 0x1000>;
72 #pwm-cells = <2>;
73 status = "disabled";
74 };
75
76 spdif-in@d0100000 {
77 compatible = "st,spdif-in";
78 reg = < 0xd0100000 0x20000
79 0xd0110000 0x10000 >;
80 interrupts = <0 84 0x4>;
81 status = "disabled";
82 };
83
84 spdif-out@d0000000 {
85 compatible = "st,spdif-out";
86 reg = <0xd0000000 0x20000>;
87 interrupts = <0 85 0x4>;
88 status = "disabled";
89 };
90
91 spi1: spi@5d400000 {
92 compatible = "arm,pl022", "arm,primecell";
93 reg = <0x5d400000 0x1000>;
94 #address-cells = <1>;
95 #size-cells = <0>;
96 interrupts = <0 99 0x4>;
97 status = "disabled";
98 };
99
100 apb {
101 i2c1: i2c@b4000000 {
102 #address-cells = <1>;
103 #size-cells = <0>;
104 compatible = "snps,designware-i2c";
105 reg = <0xb4000000 0x1000>;
106 interrupts = <0 104 0x4>;
107 write-16bit;
108 status = "disabled";
109 };
110
111 serial@b4100000 {
112 compatible = "arm,pl011", "arm,primecell";
113 reg = <0xb4100000 0x1000>;
114 interrupts = <0 105 0x4>;
115 status = "disabled";
116 };
117
118 thermal@e07008c4 {
119 st,thermal-flags = <0x2a00>;
120 };
121
122 gpiopinctrl: gpio@e2800000 {
123 compatible = "st,spear-plgpio";
124 reg = <0xe2800000 0x1000>;
125 interrupts = <0 107 0x4>;
126 #interrupt-cells = <1>;
127 interrupt-controller;
128 gpio-controller;
129 #gpio-cells = <2>;
130 gpio-ranges = <&pinmux 0 252>;
131 status = "disabled";
132
133 st-plgpio,ngpio = <250>;
134 st-plgpio,wdata-reg = <0x40>;
135 st-plgpio,dir-reg = <0x00>;
136 st-plgpio,ie-reg = <0x80>;
137 st-plgpio,rdata-reg = <0x20>;
138 st-plgpio,mis-reg = <0xa0>;
139 st-plgpio,eit-reg = <0x60>;
140 };
141 };
142 };
143};
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
deleted file mode 100644
index b4ca60f4eb4..00000000000
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ /dev/null
@@ -1,313 +0,0 @@
1/*
2 * DTS file for all SPEAr13xx SoCs
3 *
4 * Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "skeleton.dtsi"
15
16/ {
17 interrupt-parent = <&gic>;
18
19 cpus {
20 #address-cells = <1>;
21 #size-cells = <0>;
22
23 cpu@0 {
24 compatible = "arm,cortex-a9";
25 reg = <0>;
26 next-level-cache = <&L2>;
27 };
28
29 cpu@1 {
30 compatible = "arm,cortex-a9";
31 reg = <1>;
32 next-level-cache = <&L2>;
33 };
34 };
35
36 gic: interrupt-controller@ec801000 {
37 compatible = "arm,cortex-a9-gic";
38 interrupt-controller;
39 #interrupt-cells = <3>;
40 reg = < 0xec801000 0x1000 >,
41 < 0xec800100 0x0100 >;
42 };
43
44 pmu {
45 compatible = "arm,cortex-a9-pmu";
46 interrupts = <0 6 0x04
47 0 7 0x04>;
48 };
49
50 L2: l2-cache {
51 compatible = "arm,pl310-cache";
52 reg = <0xed000000 0x1000>;
53 cache-unified;
54 cache-level = <2>;
55 };
56
57 memory {
58 name = "memory";
59 device_type = "memory";
60 reg = <0 0x40000000>;
61 };
62
63 chosen {
64 bootargs = "console=ttyAMA0,115200";
65 };
66
67 cpufreq {
68 compatible = "st,cpufreq-spear";
69 cpufreq_tbl = < 166000
70 200000
71 250000
72 300000
73 400000
74 500000
75 600000 >;
76 status = "disabled";
77 };
78
79 ahb {
80 #address-cells = <1>;
81 #size-cells = <1>;
82 compatible = "simple-bus";
83 ranges = <0x50000000 0x50000000 0x10000000
84 0xb0000000 0xb0000000 0x10000000
85 0xd0000000 0xd0000000 0x02000000
86 0xd8000000 0xd8000000 0x01000000
87 0xe0000000 0xe0000000 0x10000000>;
88
89 sdhci@b3000000 {
90 compatible = "st,sdhci-spear";
91 reg = <0xb3000000 0x100>;
92 interrupts = <0 28 0x4>;
93 status = "disabled";
94 };
95
96 cf@b2800000 {
97 compatible = "arasan,cf-spear1340";
98 reg = <0xb2800000 0x1000>;
99 interrupts = <0 29 0x4>;
100 status = "disabled";
101 };
102
103 dma@ea800000 {
104 compatible = "snps,dma-spear1340";
105 reg = <0xea800000 0x1000>;
106 interrupts = <0 19 0x4>;
107 status = "disabled";
108 };
109
110 dma@eb000000 {
111 compatible = "snps,dma-spear1340";
112 reg = <0xeb000000 0x1000>;
113 interrupts = <0 59 0x4>;
114 status = "disabled";
115 };
116
117 fsmc: flash@b0000000 {
118 compatible = "st,spear600-fsmc-nand";
119 #address-cells = <1>;
120 #size-cells = <1>;
121 reg = <0xb0000000 0x1000 /* FSMC Register*/
122 0xb0800000 0x0010 /* NAND Base DATA */
123 0xb0820000 0x0010 /* NAND Base ADDR */
124 0xb0810000 0x0010>; /* NAND Base CMD */
125 reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
126 interrupts = <0 20 0x4
127 0 21 0x4
128 0 22 0x4
129 0 23 0x4>;
130 st,mode = <2>;
131 status = "disabled";
132 };
133
134 gmac0: eth@e2000000 {
135 compatible = "st,spear600-gmac";
136 reg = <0xe2000000 0x8000>;
137 interrupts = <0 33 0x4
138 0 34 0x4>;
139 interrupt-names = "macirq", "eth_wake_irq";
140 status = "disabled";
141 };
142
143 pcm {
144 compatible = "st,pcm-audio";
145 #address-cells = <0>;
146 #size-cells = <0>;
147 status = "disabled";
148 };
149
150 smi: flash@ea000000 {
151 compatible = "st,spear600-smi";
152 #address-cells = <1>;
153 #size-cells = <1>;
154 reg = <0xea000000 0x1000>;
155 interrupts = <0 30 0x4>;
156 status = "disabled";
157 };
158
159 ehci@e4800000 {
160 compatible = "st,spear600-ehci", "usb-ehci";
161 reg = <0xe4800000 0x1000>;
162 interrupts = <0 64 0x4>;
163 usbh0_id = <0>;
164 status = "disabled";
165 };
166
167 ehci@e5800000 {
168 compatible = "st,spear600-ehci", "usb-ehci";
169 reg = <0xe5800000 0x1000>;
170 interrupts = <0 66 0x4>;
171 usbh1_id = <1>;
172 status = "disabled";
173 };
174
175 ohci@e4000000 {
176 compatible = "st,spear600-ohci", "usb-ohci";
177 reg = <0xe4000000 0x1000>;
178 interrupts = <0 65 0x4>;
179 usbh0_id = <0>;
180 status = "disabled";
181 };
182
183 ohci@e5000000 {
184 compatible = "st,spear600-ohci", "usb-ohci";
185 reg = <0xe5000000 0x1000>;
186 interrupts = <0 67 0x4>;
187 usbh1_id = <1>;
188 status = "disabled";
189 };
190
191 apb {
192 #address-cells = <1>;
193 #size-cells = <1>;
194 compatible = "simple-bus";
195 ranges = <0x50000000 0x50000000 0x10000000
196 0xb0000000 0xb0000000 0x10000000
197 0xd0000000 0xd0000000 0x02000000
198 0xd8000000 0xd8000000 0x01000000
199 0xe0000000 0xe0000000 0x10000000>;
200
201 gpio0: gpio@e0600000 {
202 compatible = "arm,pl061", "arm,primecell";
203 reg = <0xe0600000 0x1000>;
204 interrupts = <0 24 0x4>;
205 gpio-controller;
206 #gpio-cells = <2>;
207 interrupt-controller;
208 #interrupt-cells = <2>;
209 status = "disabled";
210 };
211
212 gpio1: gpio@e0680000 {
213 compatible = "arm,pl061", "arm,primecell";
214 reg = <0xe0680000 0x1000>;
215 interrupts = <0 25 0x4>;
216 gpio-controller;
217 #gpio-cells = <2>;
218 interrupt-controller;
219 #interrupt-cells = <2>;
220 status = "disabled";
221 };
222
223 kbd@e0300000 {
224 compatible = "st,spear300-kbd";
225 reg = <0xe0300000 0x1000>;
226 interrupts = <0 52 0x4>;
227 status = "disabled";
228 };
229
230 i2c0: i2c@e0280000 {
231 #address-cells = <1>;
232 #size-cells = <0>;
233 compatible = "snps,designware-i2c";
234 reg = <0xe0280000 0x1000>;
235 interrupts = <0 41 0x4>;
236 status = "disabled";
237 };
238
239 i2s@e0180000 {
240 compatible = "st,designware-i2s";
241 reg = <0xe0180000 0x1000>;
242 interrupt-names = "play_irq", "record_irq";
243 interrupts = <0 10 0x4
244 0 11 0x4 >;
245 status = "disabled";
246 };
247
248 i2s@e0200000 {
249 compatible = "st,designware-i2s";
250 reg = <0xe0200000 0x1000>;
251 interrupt-names = "play_irq", "record_irq";
252 interrupts = <0 26 0x4
253 0 53 0x4>;
254 status = "disabled";
255 };
256
257 spi0: spi@e0100000 {
258 compatible = "arm,pl022", "arm,primecell";
259 reg = <0xe0100000 0x1000>;
260 #address-cells = <1>;
261 #size-cells = <0>;
262 interrupts = <0 31 0x4>;
263 status = "disabled";
264 };
265
266 rtc@e0580000 {
267 compatible = "st,spear600-rtc";
268 reg = <0xe0580000 0x1000>;
269 interrupts = <0 36 0x4>;
270 status = "disabled";
271 };
272
273 serial@e0000000 {
274 compatible = "arm,pl011", "arm,primecell";
275 reg = <0xe0000000 0x1000>;
276 interrupts = <0 35 0x4>;
277 status = "disabled";
278 };
279
280 adc@e0080000 {
281 compatible = "st,spear600-adc";
282 reg = <0xe0080000 0x1000>;
283 interrupts = <0 12 0x4>;
284 status = "disabled";
285 };
286
287 timer@e0380000 {
288 compatible = "st,spear-timer";
289 reg = <0xe0380000 0x400>;
290 interrupts = <0 37 0x4>;
291 };
292
293 timer@ec800600 {
294 compatible = "arm,cortex-a9-twd-timer";
295 reg = <0xec800600 0x20>;
296 interrupts = <1 13 0x4>;
297 status = "disabled";
298 };
299
300 wdt@ec800620 {
301 compatible = "arm,cortex-a9-twd-wdt";
302 reg = <0xec800620 0x20>;
303 status = "disabled";
304 };
305
306 thermal@e07008c4 {
307 compatible = "st,thermal-spear1340";
308 reg = <0xe07008c4 0x4>;
309 thermal_flags = <0x7000>;
310 };
311 };
312 };
313};
diff --git a/arch/arm/boot/dts/spear300-evb.dts b/arch/arm/boot/dts/spear300-evb.dts
deleted file mode 100644
index 5de1431653e..00000000000
--- a/arch/arm/boot/dts/spear300-evb.dts
+++ /dev/null
@@ -1,255 +0,0 @@
1/*
2 * DTS file for SPEAr300 Evaluation Baord
3 *
4 * Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "spear300.dtsi"
16
17/ {
18 model = "ST SPEAr300 Evaluation Board";
19 compatible = "st,spear300-evb", "st,spear300";
20 #address-cells = <1>;
21 #size-cells = <1>;
22
23 memory {
24 reg = <0 0x40000000>;
25 };
26
27 ahb {
28 pinmux@99000000 {
29 st,pinmux-mode = <2>;
30 pinctrl-names = "default";
31 pinctrl-0 = <&state_default>;
32
33 state_default: pinmux {
34 i2c0 {
35 st,pins = "i2c0_grp";
36 st,function = "i2c0";
37 };
38 ssp0 {
39 st,pins = "ssp0_grp";
40 st,function = "ssp0";
41 };
42 mii0 {
43 st,pins = "mii0_grp";
44 st,function = "mii0";
45 };
46 uart0 {
47 st,pins = "uart0_grp";
48 st,function = "uart0";
49 };
50 clcd {
51 st,pins = "clcd_pfmode_grp";
52 st,function = "clcd";
53 };
54 sdhci {
55 st,pins = "sdhci_4bit_grp";
56 st,function = "sdhci";
57 };
58 gpio1 {
59 st,pins = "gpio1_4_to_7_grp",
60 "gpio1_0_to_3_grp";
61 st,function = "gpio1";
62 };
63 };
64 };
65
66 clcd@60000000 {
67 status = "okay";
68 };
69
70 dma@fc400000 {
71 status = "okay";
72 };
73
74 fsmc: flash@94000000 {
75 status = "okay";
76 };
77
78 gmac: eth@e0800000 {
79 status = "okay";
80 };
81
82 sdhci@70000000 {
83 cd-gpios = <&gpio1 0 0>;
84 status = "okay";
85 };
86
87 smi: flash@fc000000 {
88 status = "okay";
89 clock-rate=<50000000>;
90
91 flash@f8000000 {
92 #address-cells = <1>;
93 #size-cells = <1>;
94 reg = <0xf8000000 0x800000>;
95 st,smi-fast-mode;
96
97 partition@0 {
98 label = "xloader";
99 reg = <0x0 0x10000>;
100 };
101 partition@10000 {
102 label = "u-boot";
103 reg = <0x10000 0x50000>;
104 };
105 partition@60000 {
106 label = "environment";
107 reg = <0x60000 0x10000>;
108 };
109 partition@70000 {
110 label = "dtb";
111 reg = <0x70000 0x10000>;
112 };
113 partition@80000 {
114 label = "linux";
115 reg = <0x80000 0x310000>;
116 };
117 partition@390000 {
118 label = "rootfs";
119 reg = <0x390000 0x0>;
120 };
121 };
122 };
123
124 spi0: spi@d0100000 {
125 status = "okay";
126 };
127
128 ehci@e1800000 {
129 status = "okay";
130 };
131
132 ohci@e1900000 {
133 status = "okay";
134 };
135
136 ohci@e2100000 {
137 status = "okay";
138 };
139
140 apb {
141 gpio0: gpio@fc980000 {
142 status = "okay";
143 };
144
145 gpio1: gpio@a9000000 {
146 status = "okay";
147 };
148
149 i2c0: i2c@d0180000 {
150 status = "okay";
151 };
152
153 kbd@a0000000 {
154 linux,keymap = < 0x00000001
155 0x00010002
156 0x00020003
157 0x00030004
158 0x00040005
159 0x00050006
160 0x00060007
161 0x00070008
162 0x00080009
163 0x0100000a
164 0x0101000c
165 0x0102000d
166 0x0103000e
167 0x0104000f
168 0x01050010
169 0x01060011
170 0x01070012
171 0x01080013
172 0x02000014
173 0x02010015
174 0x02020016
175 0x02030017
176 0x02040018
177 0x02050019
178 0x0206001a
179 0x0207001b
180 0x0208001c
181 0x0300001d
182 0x0301001e
183 0x0302001f
184 0x03030020
185 0x03040021
186 0x03050022
187 0x03060023
188 0x03070024
189 0x03080025
190 0x04000026
191 0x04010027
192 0x04020028
193 0x04030029
194 0x0404002a
195 0x0405002b
196 0x0406002c
197 0x0407002d
198 0x0408002e
199 0x0500002f
200 0x05010030
201 0x05020031
202 0x05030032
203 0x05040033
204 0x05050034
205 0x05060035
206 0x05070036
207 0x05080037
208 0x06000038
209 0x06010039
210 0x0602003a
211 0x0603003b
212 0x0604003c
213 0x0605003d
214 0x0606003e
215 0x0607003f
216 0x06080040
217 0x07000041
218 0x07010042
219 0x07020043
220 0x07030044
221 0x07040045
222 0x07050046
223 0x07060047
224 0x07070048
225 0x07080049
226 0x0800004a
227 0x0801004b
228 0x0802004c
229 0x0803004d
230 0x0804004e
231 0x0805004f
232 0x08060050
233 0x08070051
234 0x08080052 >;
235 autorepeat;
236 st,mode = <0>;
237 status = "okay";
238 };
239
240 rtc@fc900000 {
241 status = "okay";
242 };
243
244 serial@d0000000 {
245 status = "okay";
246 pinctrl-names = "default";
247 pinctrl-0 = <>;
248 };
249
250 wdt@fc880000 {
251 status = "okay";
252 };
253 };
254 };
255};
diff --git a/arch/arm/boot/dts/spear300.dtsi b/arch/arm/boot/dts/spear300.dtsi
deleted file mode 100644
index f79b3dfaabe..00000000000
--- a/arch/arm/boot/dts/spear300.dtsi
+++ /dev/null
@@ -1,89 +0,0 @@
1/*
2 * DTS file for SPEAr300 SoC
3 *
4 * Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "spear3xx.dtsi"
15
16/ {
17 ahb {
18 #address-cells = <1>;
19 #size-cells = <1>;
20 compatible = "simple-bus";
21 ranges = <0x60000000 0x60000000 0x50000000
22 0xd0000000 0xd0000000 0x30000000>;
23
24 pinmux@99000000 {
25 compatible = "st,spear300-pinmux";
26 reg = <0x99000000 0x1000>;
27 };
28
29 clcd@60000000 {
30 compatible = "arm,pl110", "arm,primecell";
31 reg = <0x60000000 0x1000>;
32 interrupts = <30>;
33 status = "disabled";
34 };
35
36 fsmc: flash@94000000 {
37 compatible = "st,spear600-fsmc-nand";
38 #address-cells = <1>;
39 #size-cells = <1>;
40 reg = <0x94000000 0x1000 /* FSMC Register */
41 0x80000000 0x0010 /* NAND Base DATA */
42 0x80020000 0x0010 /* NAND Base ADDR */
43 0x80010000 0x0010>; /* NAND Base CMD */
44 reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
45 status = "disabled";
46 };
47
48 sdhci@70000000 {
49 compatible = "st,sdhci-spear";
50 reg = <0x70000000 0x100>;
51 interrupts = <1>;
52 status = "disabled";
53 };
54
55 shirq: interrupt-controller@0x50000000 {
56 compatible = "st,spear300-shirq";
57 reg = <0x50000000 0x1000>;
58 interrupts = <28>;
59 #interrupt-cells = <1>;
60 interrupt-controller;
61 };
62
63 apb {
64 #address-cells = <1>;
65 #size-cells = <1>;
66 compatible = "simple-bus";
67 ranges = <0xa0000000 0xa0000000 0x10000000
68 0xd0000000 0xd0000000 0x30000000>;
69
70 gpio1: gpio@a9000000 {
71 #gpio-cells = <2>;
72 compatible = "arm,pl061", "arm,primecell";
73 gpio-controller;
74 reg = <0xa9000000 0x1000>;
75 interrupts = <8>;
76 interrupt-parent = <&shirq>;
77 status = "disabled";
78 };
79
80 kbd@a0000000 {
81 compatible = "st,spear300-kbd";
82 reg = <0xa0000000 0x1000>;
83 interrupts = <7>;
84 interrupt-parent = <&shirq>;
85 status = "disabled";
86 };
87 };
88 };
89};
diff --git a/arch/arm/boot/dts/spear310-evb.dts b/arch/arm/boot/dts/spear310-evb.dts
deleted file mode 100644
index b09632963d1..00000000000
--- a/arch/arm/boot/dts/spear310-evb.dts
+++ /dev/null
@@ -1,208 +0,0 @@
1/*
2 * DTS file for SPEAr310 Evaluation Baord
3 *
4 * Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "spear310.dtsi"
16
17/ {
18 model = "ST SPEAr310 Evaluation Board";
19 compatible = "st,spear310-evb", "st,spear310";
20 #address-cells = <1>;
21 #size-cells = <1>;
22
23 memory {
24 reg = <0 0x40000000>;
25 };
26
27 ahb {
28 pinmux@b4000000 {
29 pinctrl-names = "default";
30 pinctrl-0 = <&state_default>;
31
32 state_default: pinmux {
33 gpio0 {
34 st,pins = "gpio0_pin0_grp",
35 "gpio0_pin1_grp",
36 "gpio0_pin2_grp",
37 "gpio0_pin3_grp",
38 "gpio0_pin4_grp",
39 "gpio0_pin5_grp";
40 st,function = "gpio0";
41 };
42 i2c0 {
43 st,pins = "i2c0_grp";
44 st,function = "i2c0";
45 };
46 mii0 {
47 st,pins = "mii0_grp";
48 st,function = "mii0";
49 };
50 ssp0 {
51 st,pins = "ssp0_grp";
52 st,function = "ssp0";
53 };
54 uart0 {
55 st,pins = "uart0_grp";
56 st,function = "uart0";
57 };
58 emi {
59 st,pins = "emi_cs_0_to_5_grp";
60 st,function = "emi";
61 };
62 fsmc {
63 st,pins = "fsmc_grp";
64 st,function = "fsmc";
65 };
66 uart1 {
67 st,pins = "uart1_grp";
68 st,function = "uart1";
69 };
70 uart2 {
71 st,pins = "uart2_grp";
72 st,function = "uart2";
73 };
74 uart3 {
75 st,pins = "uart3_grp";
76 st,function = "uart3";
77 };
78 uart4 {
79 st,pins = "uart4_grp";
80 st,function = "uart4";
81 };
82 uart5 {
83 st,pins = "uart5_grp";
84 st,function = "uart5";
85 };
86 };
87 };
88
89 dma@fc400000 {
90 status = "okay";
91 };
92
93 fsmc: flash@44000000 {
94 status = "okay";
95 };
96
97 gmac: eth@e0800000 {
98 status = "okay";
99 };
100
101 smi: flash@fc000000 {
102 status = "okay";
103 clock-rate=<50000000>;
104
105 flash@f8000000 {
106 #address-cells = <1>;
107 #size-cells = <1>;
108 reg = <0xf8000000 0x800000>;
109 st,smi-fast-mode;
110
111 partition@0 {
112 label = "xloader";
113 reg = <0x0 0x10000>;
114 };
115 partition@10000 {
116 label = "u-boot";
117 reg = <0x10000 0x50000>;
118 };
119 partition@60000 {
120 label = "environment";
121 reg = <0x60000 0x10000>;
122 };
123 partition@70000 {
124 label = "dtb";
125 reg = <0x70000 0x10000>;
126 };
127 partition@80000 {
128 label = "linux";
129 reg = <0x80000 0x310000>;
130 };
131 partition@390000 {
132 label = "rootfs";
133 reg = <0x390000 0x0>;
134 };
135 };
136 };
137
138 spi0: spi@d0100000 {
139 status = "okay";
140 };
141
142 ehci@e1800000 {
143 status = "okay";
144 };
145
146 ohci@e1900000 {
147 status = "okay";
148 };
149
150 ohci@e2100000 {
151 status = "okay";
152 };
153
154 apb {
155 gpio0: gpio@fc980000 {
156 status = "okay";
157 };
158
159 i2c0: i2c@d0180000 {
160 status = "okay";
161 };
162
163 rtc@fc900000 {
164 status = "okay";
165 };
166
167 serial@d0000000 {
168 status = "okay";
169 pinctrl-names = "default";
170 pinctrl-0 = <>;
171 };
172
173 serial@b2000000 {
174 status = "okay";
175 pinctrl-names = "default";
176 pinctrl-0 = <>;
177 };
178
179 serial@b2080000 {
180 status = "okay";
181 pinctrl-names = "default";
182 pinctrl-0 = <>;
183 };
184
185 serial@b2100000 {
186 status = "okay";
187 pinctrl-names = "default";
188 pinctrl-0 = <>;
189 };
190
191 serial@b2180000 {
192 status = "okay";
193 pinctrl-names = "default";
194 pinctrl-0 = <>;
195 };
196
197 serial@b2200000 {
198 status = "okay";
199 pinctrl-names = "default";
200 pinctrl-0 = <>;
201 };
202
203 wdt@fc880000 {
204 status = "okay";
205 };
206 };
207 };
208};
diff --git a/arch/arm/boot/dts/spear310.dtsi b/arch/arm/boot/dts/spear310.dtsi
deleted file mode 100644
index ab45b8c8198..00000000000
--- a/arch/arm/boot/dts/spear310.dtsi
+++ /dev/null
@@ -1,118 +0,0 @@
1/*
2 * DTS file for SPEAr310 SoC
3 *
4 * Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "spear3xx.dtsi"
15
16/ {
17 ahb {
18 #address-cells = <1>;
19 #size-cells = <1>;
20 compatible = "simple-bus";
21 ranges = <0x40000000 0x40000000 0x10000000
22 0xb0000000 0xb0000000 0x10000000
23 0xd0000000 0xd0000000 0x30000000>;
24
25 pinmux: pinmux@b4000000 {
26 compatible = "st,spear310-pinmux";
27 reg = <0xb4000000 0x1000>;
28 #gpio-range-cells = <2>;
29 };
30
31 fsmc: flash@44000000 {
32 compatible = "st,spear600-fsmc-nand";
33 #address-cells = <1>;
34 #size-cells = <1>;
35 reg = <0x44000000 0x1000 /* FSMC Register */
36 0x40000000 0x0010 /* NAND Base DATA */
37 0x40020000 0x0010 /* NAND Base ADDR */
38 0x40010000 0x0010>; /* NAND Base CMD */
39 reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
40 status = "disabled";
41 };
42
43 shirq: interrupt-controller@0xb4000000 {
44 compatible = "st,spear310-shirq";
45 reg = <0xb4000000 0x1000>;
46 interrupts = <28 29 30 1>;
47 #interrupt-cells = <1>;
48 interrupt-controller;
49 };
50
51 apb {
52 #address-cells = <1>;
53 #size-cells = <1>;
54 compatible = "simple-bus";
55 ranges = <0xb0000000 0xb0000000 0x10000000
56 0xd0000000 0xd0000000 0x30000000>;
57
58 serial@b2000000 {
59 compatible = "arm,pl011", "arm,primecell";
60 reg = <0xb2000000 0x1000>;
61 interrupts = <8>;
62 interrupt-parent = <&shirq>;
63 status = "disabled";
64 };
65
66 serial@b2080000 {
67 compatible = "arm,pl011", "arm,primecell";
68 reg = <0xb2080000 0x1000>;
69 interrupts = <9>;
70 interrupt-parent = <&shirq>;
71 status = "disabled";
72 };
73
74 serial@b2100000 {
75 compatible = "arm,pl011", "arm,primecell";
76 reg = <0xb2100000 0x1000>;
77 interrupts = <10>;
78 interrupt-parent = <&shirq>;
79 status = "disabled";
80 };
81
82 serial@b2180000 {
83 compatible = "arm,pl011", "arm,primecell";
84 reg = <0xb2180000 0x1000>;
85 interrupts = <11>;
86 interrupt-parent = <&shirq>;
87 status = "disabled";
88 };
89
90 serial@b2200000 {
91 compatible = "arm,pl011", "arm,primecell";
92 reg = <0xb2200000 0x1000>;
93 interrupts = <12>;
94 interrupt-parent = <&shirq>;
95 status = "disabled";
96 };
97
98 gpiopinctrl: gpio@b4000000 {
99 compatible = "st,spear-plgpio";
100 reg = <0xb4000000 0x1000>;
101 #interrupt-cells = <1>;
102 interrupt-controller;
103 gpio-controller;
104 #gpio-cells = <2>;
105 gpio-ranges = <&pinmux 0 102>;
106 status = "disabled";
107
108 st-plgpio,ngpio = <102>;
109 st-plgpio,enb-reg = <0x10>;
110 st-plgpio,wdata-reg = <0x20>;
111 st-plgpio,dir-reg = <0x30>;
112 st-plgpio,ie-reg = <0x50>;
113 st-plgpio,rdata-reg = <0x40>;
114 st-plgpio,mis-reg = <0x60>;
115 };
116 };
117 };
118};
diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts
deleted file mode 100644
index fdedbb51410..00000000000
--- a/arch/arm/boot/dts/spear320-evb.dts
+++ /dev/null
@@ -1,207 +0,0 @@
1/*
2 * DTS file for SPEAr320 Evaluation Baord
3 *
4 * Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "spear320.dtsi"
16
17/ {
18 model = "ST SPEAr320 Evaluation Board";
19 compatible = "st,spear320-evb", "st,spear320";
20 #address-cells = <1>;
21 #size-cells = <1>;
22
23 memory {
24 reg = <0 0x40000000>;
25 };
26
27 ahb {
28 pinmux@b3000000 {
29 st,pinmux-mode = <4>;
30 pinctrl-names = "default";
31 pinctrl-0 = <&state_default>;
32
33 state_default: pinmux {
34 i2c0 {
35 st,pins = "i2c0_grp";
36 st,function = "i2c0";
37 };
38 mii0 {
39 st,pins = "mii0_grp";
40 st,function = "mii0";
41 };
42 ssp0 {
43 st,pins = "ssp0_grp";
44 st,function = "ssp0";
45 };
46 uart0 {
47 st,pins = "uart0_grp";
48 st,function = "uart0";
49 };
50 sdhci {
51 st,pins = "sdhci_cd_51_grp";
52 st,function = "sdhci";
53 };
54 i2s {
55 st,pins = "i2s_grp";
56 st,function = "i2s";
57 };
58 uart1 {
59 st,pins = "uart1_grp";
60 st,function = "uart1";
61 };
62 uart2 {
63 st,pins = "uart2_grp";
64 st,function = "uart2";
65 };
66 can0 {
67 st,pins = "can0_grp";
68 st,function = "can0";
69 };
70 can1 {
71 st,pins = "can1_grp";
72 st,function = "can1";
73 };
74 mii2 {
75 st,pins = "mii2_grp";
76 st,function = "mii2";
77 };
78 pwm0_1 {
79 st,pins = "pwm0_1_pin_37_38_grp";
80 st,function = "pwm0_1";
81 };
82 };
83 };
84
85 dma@fc400000 {
86 status = "okay";
87 };
88
89 fsmc: flash@4c000000 {
90 status = "okay";
91 };
92
93 gmac: eth@e0800000 {
94 status = "okay";
95 };
96
97 sdhci@70000000 {
98 power-gpio = <&gpiopinctrl 61 1>;
99 status = "okay";
100 };
101
102 smi: flash@fc000000 {
103 status = "okay";
104 clock-rate=<50000000>;
105
106 flash@f8000000 {
107 #address-cells = <1>;
108 #size-cells = <1>;
109 reg = <0xf8000000 0x800000>;
110 st,smi-fast-mode;
111
112 partition@0 {
113 label = "xloader";
114 reg = <0x0 0x10000>;
115 };
116 partition@10000 {
117 label = "u-boot";
118 reg = <0x10000 0x50000>;
119 };
120 partition@60000 {
121 label = "environment";
122 reg = <0x60000 0x10000>;
123 };
124 partition@70000 {
125 label = "dtb";
126 reg = <0x70000 0x10000>;
127 };
128 partition@80000 {
129 label = "linux";
130 reg = <0x80000 0x310000>;
131 };
132 partition@390000 {
133 label = "rootfs";
134 reg = <0x390000 0x0>;
135 };
136 };
137 };
138
139 spi0: spi@d0100000 {
140 status = "okay";
141 };
142
143 spi1: spi@a5000000 {
144 status = "okay";
145 };
146
147 spi2: spi@a6000000 {
148 status = "okay";
149 };
150
151 ehci@e1800000 {
152 status = "okay";
153 };
154
155 ohci@e1900000 {
156 status = "okay";
157 };
158
159 ohci@e2100000 {
160 status = "okay";
161 };
162
163 apb {
164 gpio0: gpio@fc980000 {
165 status = "okay";
166 };
167
168 gpio@b3000000 {
169 status = "okay";
170 };
171
172 i2c0: i2c@d0180000 {
173 status = "okay";
174 };
175
176 i2c1: i2c@a7000000 {
177 status = "okay";
178 };
179
180 rtc@fc900000 {
181 status = "okay";
182 };
183
184 serial@d0000000 {
185 status = "okay";
186 pinctrl-names = "default";
187 pinctrl-0 = <>;
188 };
189
190 serial@a3000000 {
191 status = "okay";
192 pinctrl-names = "default";
193 pinctrl-0 = <>;
194 };
195
196 serial@a4000000 {
197 status = "okay";
198 pinctrl-names = "default";
199 pinctrl-0 = <>;
200 };
201
202 wdt@fc880000 {
203 status = "okay";
204 };
205 };
206 };
207};
diff --git a/arch/arm/boot/dts/spear320-hmi.dts b/arch/arm/boot/dts/spear320-hmi.dts
deleted file mode 100644
index 3075d2d3a8b..00000000000
--- a/arch/arm/boot/dts/spear320-hmi.dts
+++ /dev/null
@@ -1,305 +0,0 @@
1/*
2 * DTS file for SPEAr320 Evaluation Baord
3 *
4 * Copyright 2012 Shiraz Hashim <shiraz.hashim@st.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "spear320.dtsi"
16
17/ {
18 model = "ST SPEAr320 HMI Board";
19 compatible = "st,spear320-hmi", "st,spear320";
20 #address-cells = <1>;
21 #size-cells = <1>;
22
23 memory {
24 reg = <0 0x40000000>;
25 };
26
27 ahb {
28 pinmux@b3000000 {
29 st,pinmux-mode = <4>;
30 pinctrl-names = "default";
31 pinctrl-0 = <&state_default>;
32
33 state_default: pinmux {
34 i2c0 {
35 st,pins = "i2c0_grp";
36 st,function = "i2c0";
37 };
38 ssp0 {
39 st,pins = "ssp0_grp";
40 st,function = "ssp0";
41 };
42 uart0 {
43 st,pins = "uart0_grp";
44 st,function = "uart0";
45 };
46 clcd {
47 st,pins = "clcd_grp";
48 st,function = "clcd";
49 };
50 fsmc {
51 st,pins = "fsmc_8bit_grp";
52 st,function = "fsmc";
53 };
54 sdhci {
55 st,pins = "sdhci_cd_12_grp";
56 st,function = "sdhci";
57 };
58 i2s {
59 st,pins = "i2s_grp";
60 st,function = "i2s";
61 };
62 uart1 {
63 st,pins = "uart1_grp";
64 st,function = "uart1";
65 };
66 uart2 {
67 st,pins = "uart2_grp";
68 st,function = "uart2";
69 };
70 can0 {
71 st,pins = "can0_grp";
72 st,function = "can0";
73 };
74 can1 {
75 st,pins = "can1_grp";
76 st,function = "can1";
77 };
78 mii0_1 {
79 st,pins = "rmii0_1_grp";
80 st,function = "mii0_1";
81 };
82 pwm0_1 {
83 st,pins = "pwm0_1_pin_37_38_grp";
84 st,function = "pwm0_1";
85 };
86 pwm2 {
87 st,pins = "pwm2_pin_34_grp";
88 st,function = "pwm2";
89 };
90 };
91 };
92
93 clcd@90000000 {
94 status = "okay";
95 };
96
97 dma@fc400000 {
98 status = "okay";
99 };
100
101 ehci@e1800000 {
102 status = "okay";
103 };
104
105 fsmc: flash@4c000000 {
106 status = "okay";
107
108 partition@0 {
109 label = "xloader";
110 reg = <0x0 0x80000>;
111 };
112 partition@80000 {
113 label = "u-boot";
114 reg = <0x80000 0x140000>;
115 };
116 partition@1C0000 {
117 label = "environment";
118 reg = <0x1C0000 0x40000>;
119 };
120 partition@200000 {
121 label = "dtb";
122 reg = <0x200000 0x40000>;
123 };
124 partition@240000 {
125 label = "linux";
126 reg = <0x240000 0xC00000>;
127 };
128 partition@E40000 {
129 label = "rootfs";
130 reg = <0xE40000 0x0>;
131 };
132 };
133
134 gpio_keys {
135 compatible = "gpio-keys";
136 #address-cells = <1>;
137 #size-cells = <0>;
138
139 button@1 {
140 label = "user button 1";
141 linux,code = <0x100>;
142 gpios = <&stmpegpio 3 0x4>;
143 debounce-interval = <20>;
144 gpio-key,wakeup = <1>;
145 };
146
147 button@2 {
148 label = "user button 2";
149 linux,code = <0x200>;
150 gpios = <&stmpegpio 2 0x4>;
151 debounce-interval = <20>;
152 gpio-key,wakeup = <1>;
153 };
154 };
155
156 ohci@e1900000 {
157 status = "okay";
158 };
159
160 ohci@e2100000 {
161 status = "okay";
162 };
163
164 pwm: pwm@a8000000 {
165 status = "okay";
166 };
167
168 sdhci@70000000 {
169 power-gpio = <&gpiopinctrl 50 1>;
170 power_always_enb;
171 status = "okay";
172 };
173
174 smi: flash@fc000000 {
175 status = "okay";
176 clock-rate=<50000000>;
177
178 flash@f8000000 {
179 #address-cells = <1>;
180 #size-cells = <1>;
181 reg = <0xf8000000 0x800000>;
182 st,smi-fast-mode;
183
184 partition@0 {
185 label = "xloader";
186 reg = <0x0 0x10000>;
187 };
188 partition@10000 {
189 label = "u-boot";
190 reg = <0x10000 0x50000>;
191 };
192 partition@60000 {
193 label = "environment";
194 reg = <0x60000 0x10000>;
195 };
196 partition@70000 {
197 label = "dtb";
198 reg = <0x70000 0x10000>;
199 };
200 partition@80000 {
201 label = "linux";
202 reg = <0x80000 0x310000>;
203 };
204 partition@390000 {
205 label = "rootfs";
206 reg = <0x390000 0x0>;
207 };
208 };
209 };
210
211 spi0: spi@d0100000 {
212 status = "okay";
213 };
214
215 spi1: spi@a5000000 {
216 status = "okay";
217 };
218
219 spi2: spi@a6000000 {
220 status = "okay";
221 };
222
223 usbd@e1100000 {
224 status = "okay";
225 };
226
227 apb {
228 gpio0: gpio@fc980000 {
229 status = "okay";
230 };
231
232 gpio@b3000000 {
233 status = "okay";
234 };
235
236 i2c0: i2c@d0180000 {
237 status = "okay";
238
239 stmpe811@41 {
240 compatible = "st,stmpe811";
241 #address-cells = <1>;
242 #size-cells = <0>;
243 reg = <0x41>;
244 irq-over-gpio;
245 irq-gpios = <&gpiopinctrl 29 0x4>;
246 id = <0>;
247 blocks = <0x5>;
248 irq-trigger = <0x1>;
249
250 stmpegpio: stmpe-gpio {
251 compatible = "stmpe,gpio";
252 reg = <0>;
253 gpio-controller;
254 #gpio-cells = <2>;
255 gpio,norequest-mask = <0xF3>;
256 };
257
258 stmpe610-ts {
259 compatible = "stmpe,ts";
260 reg = <0>;
261 ts,sample-time = <4>;
262 ts,mod-12b = <1>;
263 ts,ref-sel = <0>;
264 ts,adc-freq = <1>;
265 ts,ave-ctrl = <1>;
266 ts,touch-det-delay = <3>;
267 ts,settling = <4>;
268 ts,fraction-z = <7>;
269 ts,i-drive = <1>;
270 };
271 };
272 };
273
274 i2c1: i2c@a7000000 {
275 status = "okay";
276 };
277
278 rtc@fc900000 {
279 status = "okay";
280 };
281
282 serial@d0000000 {
283 status = "okay";
284 pinctrl-names = "default";
285 pinctrl-0 = <>;
286 };
287
288 serial@a3000000 {
289 status = "okay";
290 pinctrl-names = "default";
291 pinctrl-0 = <>;
292 };
293
294 serial@a4000000 {
295 status = "okay";
296 pinctrl-names = "default";
297 pinctrl-0 = <>;
298 };
299
300 wdt@fc880000 {
301 status = "okay";
302 };
303 };
304 };
305};
diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi
deleted file mode 100644
index caa5520b1fd..00000000000
--- a/arch/arm/boot/dts/spear320.dtsi
+++ /dev/null
@@ -1,147 +0,0 @@
1/*
2 * DTS file for SPEAr320 SoC
3 *
4 * Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "spear3xx.dtsi"
15
16/ {
17 ahb {
18 #address-cells = <1>;
19 #size-cells = <1>;
20 compatible = "simple-bus";
21 ranges = <0x40000000 0x40000000 0x80000000
22 0xd0000000 0xd0000000 0x30000000>;
23
24 pinmux: pinmux@b3000000 {
25 compatible = "st,spear320-pinmux";
26 reg = <0xb3000000 0x1000>;
27 #gpio-range-cells = <2>;
28 };
29
30 clcd@90000000 {
31 compatible = "arm,pl110", "arm,primecell";
32 reg = <0x90000000 0x1000>;
33 interrupts = <8>;
34 interrupt-parent = <&shirq>;
35 status = "disabled";
36 };
37
38 fsmc: flash@4c000000 {
39 compatible = "st,spear600-fsmc-nand";
40 #address-cells = <1>;
41 #size-cells = <1>;
42 reg = <0x4c000000 0x1000 /* FSMC Register */
43 0x50000000 0x0010 /* NAND Base DATA */
44 0x50020000 0x0010 /* NAND Base ADDR */
45 0x50010000 0x0010>; /* NAND Base CMD */
46 reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
47 status = "disabled";
48 };
49
50 sdhci@70000000 {
51 compatible = "st,sdhci-spear";
52 reg = <0x70000000 0x100>;
53 interrupts = <10>;
54 interrupt-parent = <&shirq>;
55 status = "disabled";
56 };
57
58 shirq: interrupt-controller@0xb3000000 {
59 compatible = "st,spear320-shirq";
60 reg = <0xb3000000 0x1000>;
61 interrupts = <30 28 29 1>;
62 #interrupt-cells = <1>;
63 interrupt-controller;
64 };
65
66 spi1: spi@a5000000 {
67 compatible = "arm,pl022", "arm,primecell";
68 reg = <0xa5000000 0x1000>;
69 interrupts = <15>;
70 interrupt-parent = <&shirq>;
71 #address-cells = <1>;
72 #size-cells = <0>;
73 status = "disabled";
74 };
75
76 spi2: spi@a6000000 {
77 compatible = "arm,pl022", "arm,primecell";
78 reg = <0xa6000000 0x1000>;
79 interrupts = <16>;
80 interrupt-parent = <&shirq>;
81 #address-cells = <1>;
82 #size-cells = <0>;
83 status = "disabled";
84 };
85
86 pwm: pwm@a8000000 {
87 compatible ="st,spear-pwm";
88 reg = <0xa8000000 0x1000>;
89 #pwm-cells = <2>;
90 status = "disabled";
91 };
92
93 apb {
94 #address-cells = <1>;
95 #size-cells = <1>;
96 compatible = "simple-bus";
97 ranges = <0xa0000000 0xa0000000 0x20000000
98 0xd0000000 0xd0000000 0x30000000>;
99
100 i2c1: i2c@a7000000 {
101 #address-cells = <1>;
102 #size-cells = <0>;
103 compatible = "snps,designware-i2c";
104 reg = <0xa7000000 0x1000>;
105 interrupts = <21>;
106 interrupt-parent = <&shirq>;
107 status = "disabled";
108 };
109
110 serial@a3000000 {
111 compatible = "arm,pl011", "arm,primecell";
112 reg = <0xa3000000 0x1000>;
113 interrupts = <13>;
114 interrupt-parent = <&shirq>;
115 status = "disabled";
116 };
117
118 serial@a4000000 {
119 compatible = "arm,pl011", "arm,primecell";
120 reg = <0xa4000000 0x1000>;
121 interrupts = <14>;
122 interrupt-parent = <&shirq>;
123 status = "disabled";
124 };
125
126 gpiopinctrl: gpio@b3000000 {
127 compatible = "st,spear-plgpio";
128 reg = <0xb3000000 0x1000>;
129 #interrupt-cells = <1>;
130 interrupt-controller;
131 gpio-controller;
132 #gpio-cells = <2>;
133 gpio-ranges = <&pinmux 0 102>;
134 status = "disabled";
135
136 st-plgpio,ngpio = <102>;
137 st-plgpio,enb-reg = <0x24>;
138 st-plgpio,wdata-reg = <0x34>;
139 st-plgpio,dir-reg = <0x44>;
140 st-plgpio,ie-reg = <0x64>;
141 st-plgpio,rdata-reg = <0x54>;
142 st-plgpio,mis-reg = <0x84>;
143 st-plgpio,eit-reg = <0x94>;
144 };
145 };
146 };
147};
diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi
deleted file mode 100644
index c2a852d43c4..00000000000
--- a/arch/arm/boot/dts/spear3xx.dtsi
+++ /dev/null
@@ -1,153 +0,0 @@
1/*
2 * DTS file for all SPEAr3xx SoCs
3 *
4 * Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "skeleton.dtsi"
15
16/ {
17 interrupt-parent = <&vic>;
18
19 cpus {
20 cpu@0 {
21 compatible = "arm,arm926ejs";
22 };
23 };
24
25 memory {
26 device_type = "memory";
27 reg = <0 0x40000000>;
28 };
29
30 ahb {
31 #address-cells = <1>;
32 #size-cells = <1>;
33 compatible = "simple-bus";
34 ranges = <0xd0000000 0xd0000000 0x30000000>;
35
36 vic: interrupt-controller@f1100000 {
37 compatible = "arm,pl190-vic";
38 interrupt-controller;
39 reg = <0xf1100000 0x1000>;
40 #interrupt-cells = <1>;
41 };
42
43 dma@fc400000 {
44 compatible = "arm,pl080", "arm,primecell";
45 reg = <0xfc400000 0x1000>;
46 interrupt-parent = <&vic>;
47 interrupts = <8>;
48 status = "disabled";
49 };
50
51 gmac: eth@e0800000 {
52 compatible = "st,spear600-gmac";
53 reg = <0xe0800000 0x8000>;
54 interrupts = <23 22>;
55 interrupt-names = "macirq", "eth_wake_irq";
56 phy-mode = "mii";
57 status = "disabled";
58 };
59
60 smi: flash@fc000000 {
61 compatible = "st,spear600-smi";
62 #address-cells = <1>;
63 #size-cells = <1>;
64 reg = <0xfc000000 0x1000>;
65 interrupts = <9>;
66 status = "disabled";
67 };
68
69 spi0: spi@d0100000 {
70 compatible = "arm,pl022", "arm,primecell";
71 reg = <0xd0100000 0x1000>;
72 interrupts = <20>;
73 #address-cells = <1>;
74 #size-cells = <0>;
75 status = "disabled";
76 };
77
78 ehci@e1800000 {
79 compatible = "st,spear600-ehci", "usb-ehci";
80 reg = <0xe1800000 0x1000>;
81 interrupts = <26>;
82 status = "disabled";
83 };
84
85 ohci@e1900000 {
86 compatible = "st,spear600-ohci", "usb-ohci";
87 reg = <0xe1900000 0x1000>;
88 interrupts = <25>;
89 status = "disabled";
90 };
91
92 ohci@e2100000 {
93 compatible = "st,spear600-ohci", "usb-ohci";
94 reg = <0xe2100000 0x1000>;
95 interrupts = <27>;
96 status = "disabled";
97 };
98
99 apb {
100 #address-cells = <1>;
101 #size-cells = <1>;
102 compatible = "simple-bus";
103 ranges = <0xd0000000 0xd0000000 0x30000000>;
104
105 gpio0: gpio@fc980000 {
106 compatible = "arm,pl061", "arm,primecell";
107 reg = <0xfc980000 0x1000>;
108 interrupts = <11>;
109 gpio-controller;
110 #gpio-cells = <2>;
111 interrupt-controller;
112 #interrupt-cells = <2>;
113 status = "disabled";
114 };
115
116 i2c0: i2c@d0180000 {
117 #address-cells = <1>;
118 #size-cells = <0>;
119 compatible = "snps,designware-i2c";
120 reg = <0xd0180000 0x1000>;
121 interrupts = <21>;
122 status = "disabled";
123 };
124
125 rtc@fc900000 {
126 compatible = "st,spear600-rtc";
127 reg = <0xfc900000 0x1000>;
128 interrupts = <10>;
129 status = "disabled";
130 };
131
132 serial@d0000000 {
133 compatible = "arm,pl011", "arm,primecell";
134 reg = <0xd0000000 0x1000>;
135 interrupts = <19>;
136 status = "disabled";
137 };
138
139 wdt@fc880000 {
140 compatible = "arm,sp805", "arm,primecell";
141 reg = <0xfc880000 0x1000>;
142 interrupts = <12>;
143 status = "disabled";
144 };
145
146 timer@f0000000 {
147 compatible = "st,spear-timer";
148 reg = <0xf0000000 0x400>;
149 interrupts = <2>;
150 };
151 };
152 };
153};
diff --git a/arch/arm/boot/dts/spear600-evb.dts b/arch/arm/boot/dts/spear600-evb.dts
deleted file mode 100644
index d865a891776..00000000000
--- a/arch/arm/boot/dts/spear600-evb.dts
+++ /dev/null
@@ -1,116 +0,0 @@
1/*
2 * Copyright 2012 Stefan Roese <sr@denx.de>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "spear600.dtsi"
14
15/ {
16 model = "ST SPEAr600 Evaluation Board";
17 compatible = "st,spear600-evb", "st,spear600";
18 #address-cells = <1>;
19 #size-cells = <1>;
20
21 memory {
22 device_type = "memory";
23 reg = <0 0x10000000>;
24 };
25
26 ahb {
27 clcd@fc200000 {
28 status = "okay";
29 };
30
31 dma@fc400000 {
32 status = "okay";
33 };
34
35 ehci@e1800000 {
36 status = "okay";
37 };
38
39 ehci@e2000000 {
40 status = "okay";
41 };
42
43 gmac: ethernet@e0800000 {
44 phy-mode = "gmii";
45 status = "okay";
46 };
47
48 ohci@e1900000 {
49 status = "okay";
50 };
51
52 ohci@e2100000 {
53 status = "okay";
54 };
55
56 smi: flash@fc000000 {
57 status = "okay";
58 clock-rate=<50000000>;
59
60 flash@f8000000 {
61 #address-cells = <1>;
62 #size-cells = <1>;
63 reg = <0xf8000000 0x800000>;
64 st,smi-fast-mode;
65
66 partition@0 {
67 label = "xloader";
68 reg = <0x0 0x10000>;
69 };
70 partition@10000 {
71 label = "u-boot";
72 reg = <0x10000 0x50000>;
73 };
74 partition@60000 {
75 label = "environment";
76 reg = <0x60000 0x10000>;
77 };
78 partition@70000 {
79 label = "dtb";
80 reg = <0x70000 0x10000>;
81 };
82 partition@80000 {
83 label = "linux";
84 reg = <0x80000 0x310000>;
85 };
86 partition@390000 {
87 label = "rootfs";
88 reg = <0x390000 0x0>;
89 };
90 };
91 };
92
93 apb {
94 serial@d0000000 {
95 status = "okay";
96 pinctrl-names = "default";
97 pinctrl-0 = <>;
98 };
99
100 serial@d0080000 {
101 status = "okay";
102 pinctrl-names = "default";
103 pinctrl-0 = <>;
104 };
105
106 rtc@fc900000 {
107 status = "okay";
108 };
109
110 i2c@d0200000 {
111 clock-frequency = <400000>;
112 status = "okay";
113 };
114 };
115 };
116};
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
deleted file mode 100644
index 19f99dc4115..00000000000
--- a/arch/arm/boot/dts/spear600.dtsi
+++ /dev/null
@@ -1,205 +0,0 @@
1/*
2 * Copyright 2012 Stefan Roese <sr@denx.de>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 compatible = "st,spear600";
16
17 cpus {
18 cpu@0 {
19 compatible = "arm,arm926ejs";
20 };
21 };
22
23 memory {
24 device_type = "memory";
25 reg = <0 0x40000000>;
26 };
27
28 ahb {
29 #address-cells = <1>;
30 #size-cells = <1>;
31 compatible = "simple-bus";
32 ranges = <0xd0000000 0xd0000000 0x30000000>;
33
34 vic0: interrupt-controller@f1100000 {
35 compatible = "arm,pl190-vic";
36 interrupt-controller;
37 reg = <0xf1100000 0x1000>;
38 #interrupt-cells = <1>;
39 };
40
41 vic1: interrupt-controller@f1000000 {
42 compatible = "arm,pl190-vic";
43 interrupt-controller;
44 reg = <0xf1000000 0x1000>;
45 #interrupt-cells = <1>;
46 };
47
48 clcd@fc200000 {
49 compatible = "arm,pl110", "arm,primecell";
50 reg = <0xfc200000 0x1000>;
51 interrupt-parent = <&vic1>;
52 interrupts = <12>;
53 status = "disabled";
54 };
55
56 dma@fc400000 {
57 compatible = "arm,pl080", "arm,primecell";
58 reg = <0xfc400000 0x1000>;
59 interrupt-parent = <&vic1>;
60 interrupts = <10>;
61 status = "disabled";
62 };
63
64 gmac: ethernet@e0800000 {
65 compatible = "st,spear600-gmac";
66 reg = <0xe0800000 0x8000>;
67 interrupt-parent = <&vic1>;
68 interrupts = <24 23>;
69 interrupt-names = "macirq", "eth_wake_irq";
70 phy-mode = "gmii";
71 status = "disabled";
72 };
73
74 fsmc: flash@d1800000 {
75 compatible = "st,spear600-fsmc-nand";
76 #address-cells = <1>;
77 #size-cells = <1>;
78 reg = <0xd1800000 0x1000 /* FSMC Register */
79 0xd2000000 0x0010 /* NAND Base DATA */
80 0xd2020000 0x0010 /* NAND Base ADDR */
81 0xd2010000 0x0010>; /* NAND Base CMD */
82 reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
83 status = "disabled";
84 };
85
86 smi: flash@fc000000 {
87 compatible = "st,spear600-smi";
88 #address-cells = <1>;
89 #size-cells = <1>;
90 reg = <0xfc000000 0x1000>;
91 interrupt-parent = <&vic1>;
92 interrupts = <12>;
93 status = "disabled";
94 };
95
96 ehci@e1800000 {
97 compatible = "st,spear600-ehci", "usb-ehci";
98 reg = <0xe1800000 0x1000>;
99 interrupt-parent = <&vic1>;
100 interrupts = <27>;
101 status = "disabled";
102 };
103
104 ehci@e2000000 {
105 compatible = "st,spear600-ehci", "usb-ehci";
106 reg = <0xe2000000 0x1000>;
107 interrupt-parent = <&vic1>;
108 interrupts = <29>;
109 status = "disabled";
110 };
111
112 ohci@e1900000 {
113 compatible = "st,spear600-ohci", "usb-ohci";
114 reg = <0xe1900000 0x1000>;
115 interrupt-parent = <&vic1>;
116 interrupts = <26>;
117 status = "disabled";
118 };
119
120 ohci@e2100000 {
121 compatible = "st,spear600-ohci", "usb-ohci";
122 reg = <0xe2100000 0x1000>;
123 interrupt-parent = <&vic1>;
124 interrupts = <28>;
125 status = "disabled";
126 };
127
128 apb {
129 #address-cells = <1>;
130 #size-cells = <1>;
131 compatible = "simple-bus";
132 ranges = <0xd0000000 0xd0000000 0x30000000>;
133
134 serial@d0000000 {
135 compatible = "arm,pl011", "arm,primecell";
136 reg = <0xd0000000 0x1000>;
137 interrupt-parent = <&vic0>;
138 interrupts = <24>;
139 status = "disabled";
140 };
141
142 serial@d0080000 {
143 compatible = "arm,pl011", "arm,primecell";
144 reg = <0xd0080000 0x1000>;
145 interrupt-parent = <&vic0>;
146 interrupts = <25>;
147 status = "disabled";
148 };
149
150 /* local/cpu GPIO */
151 gpio0: gpio@f0100000 {
152 #gpio-cells = <2>;
153 compatible = "arm,pl061", "arm,primecell";
154 gpio-controller;
155 reg = <0xf0100000 0x1000>;
156 interrupt-parent = <&vic0>;
157 interrupts = <18>;
158 };
159
160 /* basic GPIO */
161 gpio1: gpio@fc980000 {
162 #gpio-cells = <2>;
163 compatible = "arm,pl061", "arm,primecell";
164 gpio-controller;
165 reg = <0xfc980000 0x1000>;
166 interrupt-parent = <&vic1>;
167 interrupts = <19>;
168 };
169
170 /* appl GPIO */
171 gpio2: gpio@d8100000 {
172 #gpio-cells = <2>;
173 compatible = "arm,pl061", "arm,primecell";
174 gpio-controller;
175 reg = <0xd8100000 0x1000>;
176 interrupt-parent = <&vic1>;
177 interrupts = <4>;
178 };
179
180 i2c@d0200000 {
181 #address-cells = <1>;
182 #size-cells = <0>;
183 compatible = "snps,designware-i2c";
184 reg = <0xd0200000 0x1000>;
185 interrupt-parent = <&vic0>;
186 interrupts = <28>;
187 status = "disabled";
188 };
189
190 rtc@fc900000 {
191 compatible = "st,spear600-rtc";
192 reg = <0xfc900000 0x1000>;
193 interrupts = <10>;
194 status = "disabled";
195 };
196
197 timer@f0000000 {
198 compatible = "st,spear-timer";
199 reg = <0xf0000000 0x400>;
200 interrupt-parent = <&vic0>;
201 interrupts = <16>;
202 };
203 };
204 };
205};
diff --git a/arch/arm/boot/dts/stuib.dtsi b/arch/arm/boot/dts/stuib.dtsi
deleted file mode 100644
index 39446a247e7..00000000000
--- a/arch/arm/boot/dts/stuib.dtsi
+++ /dev/null
@@ -1,78 +0,0 @@
1/*
2 * Copyright 2012 ST-Ericsson AB
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/ {
13 soc-u9500 {
14 i2c@80004000 {
15 stmpe1601: stmpe1601@40 {
16 compatible = "st,stmpe1601";
17 reg = <0x40>;
18 interrupts = <26 0x1>;
19 interrupt-parent = <&gpio6>;
20 interrupt-controller;
21
22 wakeup-source;
23 st,autosleep-timeout = <1024>;
24
25 stmpe_keypad {
26 compatible = "st,stmpe-keypad";
27
28 debounce-interval = <64>;
29 st,scan-count = <8>;
30 st,no-autorepeat;
31
32 linux,keymap = <0x205006b
33 0x4010074
34 0x3050072
35 0x1030004
36 0x502006a
37 0x500000a
38 0x5008b
39 0x706001c
40 0x405000b
41 0x6070003
42 0x3040067
43 0x303006c
44 0x60400e7
45 0x602009e
46 0x4020073
47 0x5050002
48 0x4030069
49 0x3020008>;
50 };
51 };
52 };
53
54 i2c@80110000 {
55 bu21013_tp@0x5c {
56 compatible = "rhom,bu21013_tp";
57 reg = <0x5c>;
58 touch-gpio = <&gpio2 20 0x4>;
59 avdd-supply = <&ab8500_ldo_aux1_reg>;
60
61 rhom,touch-max-x = <384>;
62 rhom,touch-max-y = <704>;
63 rhom,flip-y;
64 };
65
66 bu21013_tp@0x5d {
67 compatible = "rhom,bu21013_tp";
68 reg = <0x5d>;
69 touch-gpio = <&gpio2 20 0x4>;
70 avdd-supply = <&ab8500_ldo_aux1_reg>;
71
72 rhom,touch-max-x = <384>;
73 rhom,touch-max-y = <704>;
74 rhom,flip-y;
75 };
76 };
77 };
78};
diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
deleted file mode 100644
index 5cab8254043..00000000000
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ /dev/null
@@ -1,38 +0,0 @@
1/*
2 * Copyright 2012 Stefan Roese
3 * Stefan Roese <sr@denx.de>
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
14/include/ "sun4i-a10.dtsi"
15
16/ {
17 model = "Cubietech Cubieboard";
18 compatible = "cubietech,a10-cubieboard", "allwinner,sun4i-a10";
19
20 aliases {
21 serial0 = &uart0;
22 serial1 = &uart1;
23 };
24
25 chosen {
26 bootargs = "earlyprintk console=ttyS0,115200";
27 };
28
29 soc {
30 uart0: uart@01c28000 {
31 status = "okay";
32 };
33
34 uart1: uart@01c28400 {
35 status = "okay";
36 };
37 };
38};
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
deleted file mode 100644
index e61fdd47bd0..00000000000
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * Copyright 2012 Stefan Roese
3 * Stefan Roese <sr@denx.de>
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/include/ "sunxi.dtsi"
14
15/ {
16 memory {
17 reg = <0x40000000 0x80000000>;
18 };
19};
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
deleted file mode 100644
index 498a091a4ea..00000000000
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * Copyright 2012 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "sun5i-a13.dtsi"
16
17/ {
18 model = "Olimex A13-Olinuxino";
19 compatible = "olimex,a13-olinuxino", "allwinner,sun5i-a13";
20
21 chosen {
22 bootargs = "earlyprintk console=ttyS0,115200";
23 };
24
25 soc {
26 uart1: uart@01c28400 {
27 status = "okay";
28 };
29 };
30};
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
deleted file mode 100644
index 59a2d265a98..00000000000
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ /dev/null
@@ -1,20 +0,0 @@
1/*
2 * Copyright 2012 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "sunxi.dtsi"
15
16/ {
17 memory {
18 reg = <0x40000000 0x20000000>;
19 };
20};
diff --git a/arch/arm/boot/dts/sunxi.dtsi b/arch/arm/boot/dts/sunxi.dtsi
deleted file mode 100644
index 8bbc2bfef22..00000000000
--- a/arch/arm/boot/dts/sunxi.dtsi
+++ /dev/null
@@ -1,80 +0,0 @@
1/*
2 * Copyright 2012 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "skeleton.dtsi"
15
16/ {
17 interrupt-parent = <&intc>;
18
19 cpus {
20 cpu@0 {
21 compatible = "arm,cortex-a8";
22 };
23 };
24
25 clocks {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 osc: oscillator {
30 #clock-cells = <0>;
31 compatible = "fixed-clock";
32 clock-frequency = <24000000>;
33 };
34 };
35
36 soc {
37 compatible = "simple-bus";
38 #address-cells = <1>;
39 #size-cells = <1>;
40 reg = <0x01c20000 0x300000>;
41 ranges;
42
43 timer@01c20c00 {
44 compatible = "allwinner,sunxi-timer";
45 reg = <0x01c20c00 0x90>;
46 interrupts = <22>;
47 clocks = <&osc>;
48 };
49
50 wdt: watchdog@01c20c90 {
51 compatible = "allwinner,sunxi-wdt";
52 reg = <0x01c20c90 0x10>;
53 };
54
55 intc: interrupt-controller@01c20400 {
56 compatible = "allwinner,sunxi-ic";
57 reg = <0x01c20400 0x400>;
58 interrupt-controller;
59 #interrupt-cells = <1>;
60 };
61
62 uart0: uart@01c28000 {
63 compatible = "ns8250";
64 reg = <0x01c28000 0x400>;
65 interrupts = <1>;
66 reg-shift = <2>;
67 clock-frequency = <24000000>;
68 status = "disabled";
69 };
70
71 uart1: uart@01c28400 {
72 compatible = "ns8250";
73 reg = <0x01c28400 0x400>;
74 interrupts = <2>;
75 reg-shift = <2>;
76 clock-frequency = <24000000>;
77 status = "disabled";
78 };
79 };
80};
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
deleted file mode 100644
index 43eb72af894..00000000000
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ /dev/null
@@ -1,540 +0,0 @@
1/dts-v1/;
2
3/include/ "tegra20.dtsi"
4
5/ {
6 model = "NVIDIA Tegra2 Harmony evaluation board";
7 compatible = "nvidia,harmony", "nvidia,tegra20";
8
9 memory {
10 reg = <0x00000000 0x40000000>;
11 };
12
13 host1x {
14 hdmi {
15 status = "okay";
16
17 vdd-supply = <&hdmi_vdd_reg>;
18 pll-supply = <&hdmi_pll_reg>;
19
20 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
21 nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
22 };
23 };
24
25 pinmux {
26 pinctrl-names = "default";
27 pinctrl-0 = <&state_default>;
28
29 state_default: pinmux {
30 ata {
31 nvidia,pins = "ata";
32 nvidia,function = "ide";
33 };
34 atb {
35 nvidia,pins = "atb", "gma", "gme";
36 nvidia,function = "sdio4";
37 };
38 atc {
39 nvidia,pins = "atc";
40 nvidia,function = "nand";
41 };
42 atd {
43 nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
44 "spia", "spib", "spic";
45 nvidia,function = "gmi";
46 };
47 cdev1 {
48 nvidia,pins = "cdev1";
49 nvidia,function = "plla_out";
50 };
51 cdev2 {
52 nvidia,pins = "cdev2";
53 nvidia,function = "pllp_out4";
54 };
55 crtp {
56 nvidia,pins = "crtp";
57 nvidia,function = "crt";
58 };
59 csus {
60 nvidia,pins = "csus";
61 nvidia,function = "vi_sensor_clk";
62 };
63 dap1 {
64 nvidia,pins = "dap1";
65 nvidia,function = "dap1";
66 };
67 dap2 {
68 nvidia,pins = "dap2";
69 nvidia,function = "dap2";
70 };
71 dap3 {
72 nvidia,pins = "dap3";
73 nvidia,function = "dap3";
74 };
75 dap4 {
76 nvidia,pins = "dap4";
77 nvidia,function = "dap4";
78 };
79 ddc {
80 nvidia,pins = "ddc";
81 nvidia,function = "i2c2";
82 };
83 dta {
84 nvidia,pins = "dta", "dtd";
85 nvidia,function = "sdio2";
86 };
87 dtb {
88 nvidia,pins = "dtb", "dtc", "dte";
89 nvidia,function = "rsvd1";
90 };
91 dtf {
92 nvidia,pins = "dtf";
93 nvidia,function = "i2c3";
94 };
95 gmc {
96 nvidia,pins = "gmc";
97 nvidia,function = "uartd";
98 };
99 gpu7 {
100 nvidia,pins = "gpu7";
101 nvidia,function = "rtck";
102 };
103 gpv {
104 nvidia,pins = "gpv", "slxa", "slxk";
105 nvidia,function = "pcie";
106 };
107 hdint {
108 nvidia,pins = "hdint", "pta";
109 nvidia,function = "hdmi";
110 };
111 i2cp {
112 nvidia,pins = "i2cp";
113 nvidia,function = "i2cp";
114 };
115 irrx {
116 nvidia,pins = "irrx", "irtx";
117 nvidia,function = "uarta";
118 };
119 kbca {
120 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
121 "kbce", "kbcf";
122 nvidia,function = "kbc";
123 };
124 lcsn {
125 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
126 "ld3", "ld4", "ld5", "ld6", "ld7",
127 "ld8", "ld9", "ld10", "ld11", "ld12",
128 "ld13", "ld14", "ld15", "ld16", "ld17",
129 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
130 "lhs", "lm0", "lm1", "lpp", "lpw0",
131 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
132 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
133 "lvs";
134 nvidia,function = "displaya";
135 };
136 owc {
137 nvidia,pins = "owc", "spdi", "spdo", "uac";
138 nvidia,function = "rsvd2";
139 };
140 pmc {
141 nvidia,pins = "pmc";
142 nvidia,function = "pwr_on";
143 };
144 rm {
145 nvidia,pins = "rm";
146 nvidia,function = "i2c1";
147 };
148 sdb {
149 nvidia,pins = "sdb", "sdc", "sdd";
150 nvidia,function = "pwm";
151 };
152 sdio1 {
153 nvidia,pins = "sdio1";
154 nvidia,function = "sdio1";
155 };
156 slxc {
157 nvidia,pins = "slxc", "slxd";
158 nvidia,function = "spdif";
159 };
160 spid {
161 nvidia,pins = "spid", "spie", "spif";
162 nvidia,function = "spi1";
163 };
164 spig {
165 nvidia,pins = "spig", "spih";
166 nvidia,function = "spi2_alt";
167 };
168 uaa {
169 nvidia,pins = "uaa", "uab", "uda";
170 nvidia,function = "ulpi";
171 };
172 uad {
173 nvidia,pins = "uad";
174 nvidia,function = "irda";
175 };
176 uca {
177 nvidia,pins = "uca", "ucb";
178 nvidia,function = "uartc";
179 };
180 conf_ata {
181 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
182 "cdev1", "cdev2", "dap1", "dtb", "gma",
183 "gmb", "gmc", "gmd", "gme", "gpu7",
184 "gpv", "i2cp", "pta", "rm", "slxa",
185 "slxk", "spia", "spib", "uac";
186 nvidia,pull = <0>;
187 nvidia,tristate = <0>;
188 };
189 conf_ck32 {
190 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
191 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
192 nvidia,pull = <0>;
193 };
194 conf_csus {
195 nvidia,pins = "csus", "spid", "spif";
196 nvidia,pull = <1>;
197 nvidia,tristate = <1>;
198 };
199 conf_crtp {
200 nvidia,pins = "crtp", "dap2", "dap3", "dap4",
201 "dtc", "dte", "dtf", "gpu", "sdio1",
202 "slxc", "slxd", "spdi", "spdo", "spig",
203 "uda";
204 nvidia,pull = <0>;
205 nvidia,tristate = <1>;
206 };
207 conf_ddc {
208 nvidia,pins = "ddc", "dta", "dtd", "kbca",
209 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
210 "sdc";
211 nvidia,pull = <2>;
212 nvidia,tristate = <0>;
213 };
214 conf_hdint {
215 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
216 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
217 "lvp0", "owc", "sdb";
218 nvidia,tristate = <1>;
219 };
220 conf_irrx {
221 nvidia,pins = "irrx", "irtx", "sdd", "spic",
222 "spie", "spih", "uaa", "uab", "uad",
223 "uca", "ucb";
224 nvidia,pull = <2>;
225 nvidia,tristate = <1>;
226 };
227 conf_lc {
228 nvidia,pins = "lc", "ls";
229 nvidia,pull = <2>;
230 };
231 conf_ld0 {
232 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
233 "ld5", "ld6", "ld7", "ld8", "ld9",
234 "ld10", "ld11", "ld12", "ld13", "ld14",
235 "ld15", "ld16", "ld17", "ldi", "lhp0",
236 "lhp1", "lhp2", "lhs", "lm0", "lpp",
237 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
238 "lvs", "pmc";
239 nvidia,tristate = <0>;
240 };
241 conf_ld17_0 {
242 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
243 "ld23_22";
244 nvidia,pull = <1>;
245 };
246 };
247 };
248
249 i2s@70002800 {
250 status = "okay";
251 };
252
253 serial@70006300 {
254 status = "okay";
255 clock-frequency = <216000000>;
256 };
257
258 i2c@7000c000 {
259 status = "okay";
260 clock-frequency = <400000>;
261
262 wm8903: wm8903@1a {
263 compatible = "wlf,wm8903";
264 reg = <0x1a>;
265 interrupt-parent = <&gpio>;
266 interrupts = <187 0x04>;
267
268 gpio-controller;
269 #gpio-cells = <2>;
270
271 micdet-cfg = <0>;
272 micdet-delay = <100>;
273 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
274 };
275 };
276
277 hdmi_ddc: i2c@7000c400 {
278 status = "okay";
279 clock-frequency = <100000>;
280 };
281
282 i2c@7000c500 {
283 status = "okay";
284 clock-frequency = <400000>;
285 };
286
287 i2c@7000d000 {
288 status = "okay";
289 clock-frequency = <400000>;
290
291 pmic: tps6586x@34 {
292 compatible = "ti,tps6586x";
293 reg = <0x34>;
294 interrupts = <0 86 0x4>;
295
296 ti,system-power-controller;
297
298 #gpio-cells = <2>;
299 gpio-controller;
300
301 sys-supply = <&vdd_5v0_reg>;
302 vin-sm0-supply = <&sys_reg>;
303 vin-sm1-supply = <&sys_reg>;
304 vin-sm2-supply = <&sys_reg>;
305 vinldo01-supply = <&sm2_reg>;
306 vinldo23-supply = <&sm2_reg>;
307 vinldo4-supply = <&sm2_reg>;
308 vinldo678-supply = <&sm2_reg>;
309 vinldo9-supply = <&sm2_reg>;
310
311 regulators {
312 sys_reg: sys {
313 regulator-name = "vdd_sys";
314 regulator-always-on;
315 };
316
317 sm0 {
318 regulator-name = "vdd_sm0,vdd_core";
319 regulator-min-microvolt = <1200000>;
320 regulator-max-microvolt = <1200000>;
321 regulator-always-on;
322 };
323
324 sm1 {
325 regulator-name = "vdd_sm1,vdd_cpu";
326 regulator-min-microvolt = <1000000>;
327 regulator-max-microvolt = <1000000>;
328 regulator-always-on;
329 };
330
331 sm2_reg: sm2 {
332 regulator-name = "vdd_sm2,vin_ldo*";
333 regulator-min-microvolt = <3700000>;
334 regulator-max-microvolt = <3700000>;
335 regulator-always-on;
336 };
337
338 ldo0 {
339 regulator-name = "vdd_ldo0,vddio_pex_clk";
340 regulator-min-microvolt = <3300000>;
341 regulator-max-microvolt = <3300000>;
342 };
343
344 ldo1 {
345 regulator-name = "vdd_ldo1,avdd_pll*";
346 regulator-min-microvolt = <1100000>;
347 regulator-max-microvolt = <1100000>;
348 regulator-always-on;
349 };
350
351 ldo2 {
352 regulator-name = "vdd_ldo2,vdd_rtc";
353 regulator-min-microvolt = <1200000>;
354 regulator-max-microvolt = <1200000>;
355 };
356
357 ldo3 {
358 regulator-name = "vdd_ldo3,avdd_usb*";
359 regulator-min-microvolt = <3300000>;
360 regulator-max-microvolt = <3300000>;
361 regulator-always-on;
362 };
363
364 ldo4 {
365 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
366 regulator-min-microvolt = <1800000>;
367 regulator-max-microvolt = <1800000>;
368 regulator-always-on;
369 };
370
371 ldo5 {
372 regulator-name = "vdd_ldo5,vcore_mmc";
373 regulator-min-microvolt = <2850000>;
374 regulator-max-microvolt = <2850000>;
375 regulator-always-on;
376 };
377
378 ldo6 {
379 regulator-name = "vdd_ldo6,avdd_vdac";
380 regulator-min-microvolt = <1800000>;
381 regulator-max-microvolt = <1800000>;
382 };
383
384 hdmi_vdd_reg: ldo7 {
385 regulator-name = "vdd_ldo7,avdd_hdmi";
386 regulator-min-microvolt = <3300000>;
387 regulator-max-microvolt = <3300000>;
388 };
389
390 hdmi_pll_reg: ldo8 {
391 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
392 regulator-min-microvolt = <1800000>;
393 regulator-max-microvolt = <1800000>;
394 };
395
396 ldo9 {
397 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
398 regulator-min-microvolt = <2850000>;
399 regulator-max-microvolt = <2850000>;
400 regulator-always-on;
401 };
402
403 ldo_rtc {
404 regulator-name = "vdd_rtc_out,vdd_cell";
405 regulator-min-microvolt = <3300000>;
406 regulator-max-microvolt = <3300000>;
407 regulator-always-on;
408 };
409 };
410 };
411
412 temperature-sensor@4c {
413 compatible = "adi,adt7461";
414 reg = <0x4c>;
415 };
416 };
417
418 pmc {
419 nvidia,invert-interrupt;
420 };
421
422 usb@c5000000 {
423 status = "okay";
424 };
425
426 usb@c5004000 {
427 status = "okay";
428 nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
429 };
430
431 usb@c5008000 {
432 status = "okay";
433 };
434
435 sdhci@c8000200 {
436 status = "okay";
437 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
438 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
439 power-gpios = <&gpio 155 0>; /* gpio PT3 */
440 bus-width = <4>;
441 };
442
443 sdhci@c8000600 {
444 status = "okay";
445 cd-gpios = <&gpio 58 0>; /* gpio PH2 */
446 wp-gpios = <&gpio 59 0>; /* gpio PH3 */
447 power-gpios = <&gpio 70 0>; /* gpio PI6 */
448 bus-width = <8>;
449 };
450
451 regulators {
452 compatible = "simple-bus";
453 #address-cells = <1>;
454 #size-cells = <0>;
455
456 vdd_5v0_reg: regulator@0 {
457 compatible = "regulator-fixed";
458 reg = <0>;
459 regulator-name = "vdd_5v0";
460 regulator-min-microvolt = <5000000>;
461 regulator-max-microvolt = <5000000>;
462 regulator-always-on;
463 };
464
465 regulator@1 {
466 compatible = "regulator-fixed";
467 reg = <1>;
468 regulator-name = "vdd_1v5";
469 regulator-min-microvolt = <1500000>;
470 regulator-max-microvolt = <1500000>;
471 gpio = <&pmic 0 0>;
472 };
473
474 regulator@2 {
475 compatible = "regulator-fixed";
476 reg = <2>;
477 regulator-name = "vdd_1v2";
478 regulator-min-microvolt = <1200000>;
479 regulator-max-microvolt = <1200000>;
480 gpio = <&pmic 1 0>;
481 enable-active-high;
482 };
483
484 regulator@3 {
485 compatible = "regulator-fixed";
486 reg = <3>;
487 regulator-name = "vdd_1v05";
488 regulator-min-microvolt = <1050000>;
489 regulator-max-microvolt = <1050000>;
490 gpio = <&pmic 2 0>;
491 enable-active-high;
492 /* Hack until board-harmony-pcie.c is removed */
493 status = "disabled";
494 };
495
496 regulator@4 {
497 compatible = "regulator-fixed";
498 reg = <4>;
499 regulator-name = "vdd_pnl";
500 regulator-min-microvolt = <2800000>;
501 regulator-max-microvolt = <2800000>;
502 gpio = <&gpio 22 0>; /* gpio PC6 */
503 enable-active-high;
504 };
505
506 regulator@5 {
507 compatible = "regulator-fixed";
508 reg = <5>;
509 regulator-name = "vdd_bl";
510 regulator-min-microvolt = <2800000>;
511 regulator-max-microvolt = <2800000>;
512 gpio = <&gpio 176 0>; /* gpio PW0 */
513 enable-active-high;
514 };
515 };
516
517 sound {
518 compatible = "nvidia,tegra-audio-wm8903-harmony",
519 "nvidia,tegra-audio-wm8903";
520 nvidia,model = "NVIDIA Tegra Harmony";
521
522 nvidia,audio-routing =
523 "Headphone Jack", "HPOUTR",
524 "Headphone Jack", "HPOUTL",
525 "Int Spk", "ROP",
526 "Int Spk", "RON",
527 "Int Spk", "LOP",
528 "Int Spk", "LON",
529 "Mic Jack", "MICBIAS",
530 "IN1L", "Mic Jack";
531
532 nvidia,i2s-controller = <&tegra_i2s1>;
533 nvidia,audio-codec = <&wm8903>;
534
535 nvidia,spkr-en-gpios = <&wm8903 2 0>;
536 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
537 nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
538 nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
539 };
540};
diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts
deleted file mode 100644
index a2d6d6541f8..00000000000
--- a/arch/arm/boot/dts/tegra20-medcom-wide.dts
+++ /dev/null
@@ -1,58 +0,0 @@
1/dts-v1/;
2
3/include/ "tegra20-tamonten.dtsi"
4
5/ {
6 model = "Avionic Design Medcom-Wide board";
7 compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20";
8
9 i2c@7000c000 {
10 wm8903: wm8903@1a {
11 compatible = "wlf,wm8903";
12 reg = <0x1a>;
13 interrupt-parent = <&gpio>;
14 interrupts = <187 0x04>;
15
16 gpio-controller;
17 #gpio-cells = <2>;
18
19 micdet-cfg = <0>;
20 micdet-delay = <100>;
21 gpio-cfg = <0xffffffff
22 0xffffffff
23 0
24 0xffffffff
25 0xffffffff>;
26 };
27 };
28
29 backlight {
30 compatible = "pwm-backlight";
31 pwms = <&pwm 0 5000000>;
32
33 brightness-levels = <0 4 8 16 32 64 128 255>;
34 default-brightness-level = <6>;
35 };
36
37 sound {
38 compatible = "ad,tegra-audio-wm8903-medcom-wide",
39 "nvidia,tegra-audio-wm8903";
40 nvidia,model = "Avionic Design Medcom-Wide";
41
42 nvidia,audio-routing =
43 "Headphone Jack", "HPOUTR",
44 "Headphone Jack", "HPOUTL",
45 "Int Spk", "ROP",
46 "Int Spk", "RON",
47 "Int Spk", "LOP",
48 "Int Spk", "LON",
49 "Mic Jack", "MICBIAS",
50 "IN1L", "Mic Jack";
51
52 nvidia,i2s-controller = <&tegra_i2s1>;
53 nvidia,audio-codec = <&wm8903>;
54
55 nvidia,spkr-en-gpios = <&wm8903 2 0>;
56 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
57 };
58};
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
deleted file mode 100644
index 6a93d1404c7..00000000000
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ /dev/null
@@ -1,489 +0,0 @@
1/dts-v1/;
2
3/include/ "tegra20.dtsi"
4
5/ {
6 model = "Toshiba AC100 / Dynabook AZ";
7 compatible = "compal,paz00", "nvidia,tegra20";
8
9 memory {
10 reg = <0x00000000 0x20000000>;
11 };
12
13 pinmux {
14 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>;
16
17 state_default: pinmux {
18 ata {
19 nvidia,pins = "ata", "atc", "atd", "ate",
20 "dap2", "gmb", "gmc", "gmd", "spia",
21 "spib", "spic", "spid", "spie";
22 nvidia,function = "gmi";
23 };
24 atb {
25 nvidia,pins = "atb", "gma", "gme";
26 nvidia,function = "sdio4";
27 };
28 cdev1 {
29 nvidia,pins = "cdev1";
30 nvidia,function = "plla_out";
31 };
32 cdev2 {
33 nvidia,pins = "cdev2";
34 nvidia,function = "pllp_out4";
35 };
36 crtp {
37 nvidia,pins = "crtp";
38 nvidia,function = "crt";
39 };
40 csus {
41 nvidia,pins = "csus";
42 nvidia,function = "pllc_out1";
43 };
44 dap1 {
45 nvidia,pins = "dap1";
46 nvidia,function = "dap1";
47 };
48 dap3 {
49 nvidia,pins = "dap3";
50 nvidia,function = "dap3";
51 };
52 dap4 {
53 nvidia,pins = "dap4";
54 nvidia,function = "dap4";
55 };
56 ddc {
57 nvidia,pins = "ddc";
58 nvidia,function = "i2c2";
59 };
60 dta {
61 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
62 nvidia,function = "rsvd1";
63 };
64 dtf {
65 nvidia,pins = "dtf";
66 nvidia,function = "i2c3";
67 };
68 gpu {
69 nvidia,pins = "gpu", "sdb", "sdd";
70 nvidia,function = "pwm";
71 };
72 gpu7 {
73 nvidia,pins = "gpu7";
74 nvidia,function = "rtck";
75 };
76 gpv {
77 nvidia,pins = "gpv", "slxa", "slxk";
78 nvidia,function = "pcie";
79 };
80 hdint {
81 nvidia,pins = "hdint", "pta";
82 nvidia,function = "hdmi";
83 };
84 i2cp {
85 nvidia,pins = "i2cp";
86 nvidia,function = "i2cp";
87 };
88 irrx {
89 nvidia,pins = "irrx", "irtx";
90 nvidia,function = "uarta";
91 };
92 kbca {
93 nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
94 nvidia,function = "kbc";
95 };
96 kbcb {
97 nvidia,pins = "kbcb", "kbcd";
98 nvidia,function = "sdio2";
99 };
100 lcsn {
101 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
102 "ld3", "ld4", "ld5", "ld6", "ld7",
103 "ld8", "ld9", "ld10", "ld11", "ld12",
104 "ld13", "ld14", "ld15", "ld16", "ld17",
105 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
106 "lhs", "lm0", "lm1", "lpp", "lpw0",
107 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
108 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
109 "lvs";
110 nvidia,function = "displaya";
111 };
112 owc {
113 nvidia,pins = "owc";
114 nvidia,function = "owr";
115 };
116 pmc {
117 nvidia,pins = "pmc";
118 nvidia,function = "pwr_on";
119 };
120 rm {
121 nvidia,pins = "rm";
122 nvidia,function = "i2c1";
123 };
124 sdc {
125 nvidia,pins = "sdc";
126 nvidia,function = "twc";
127 };
128 sdio1 {
129 nvidia,pins = "sdio1";
130 nvidia,function = "sdio1";
131 };
132 slxc {
133 nvidia,pins = "slxc", "slxd";
134 nvidia,function = "spi4";
135 };
136 spdi {
137 nvidia,pins = "spdi", "spdo";
138 nvidia,function = "rsvd2";
139 };
140 spif {
141 nvidia,pins = "spif", "uac";
142 nvidia,function = "rsvd4";
143 };
144 spig {
145 nvidia,pins = "spig", "spih";
146 nvidia,function = "spi2_alt";
147 };
148 uaa {
149 nvidia,pins = "uaa", "uab", "uda";
150 nvidia,function = "ulpi";
151 };
152 uad {
153 nvidia,pins = "uad";
154 nvidia,function = "spdif";
155 };
156 uca {
157 nvidia,pins = "uca", "ucb";
158 nvidia,function = "uartc";
159 };
160 conf_ata {
161 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
162 "cdev1", "cdev2", "dap1", "dap2", "dtf",
163 "gma", "gmb", "gmc", "gmd", "gme",
164 "gpu", "gpu7", "gpv", "i2cp", "pta",
165 "rm", "sdio1", "slxk", "spdo", "uac",
166 "uda";
167 nvidia,pull = <0>;
168 nvidia,tristate = <0>;
169 };
170 conf_ck32 {
171 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
172 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
173 nvidia,pull = <0>;
174 };
175 conf_crtp {
176 nvidia,pins = "crtp", "dap3", "dap4", "dtb",
177 "dtc", "dte", "slxa", "slxc", "slxd",
178 "spdi";
179 nvidia,pull = <0>;
180 nvidia,tristate = <1>;
181 };
182 conf_csus {
183 nvidia,pins = "csus", "spia", "spib", "spid",
184 "spif";
185 nvidia,pull = <1>;
186 nvidia,tristate = <1>;
187 };
188 conf_ddc {
189 nvidia,pins = "ddc", "irrx", "irtx", "kbca",
190 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
191 "spic", "spig", "uaa", "uab";
192 nvidia,pull = <2>;
193 nvidia,tristate = <0>;
194 };
195 conf_dta {
196 nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
197 "spie", "spih", "uad", "uca", "ucb";
198 nvidia,pull = <2>;
199 nvidia,tristate = <1>;
200 };
201 conf_hdint {
202 nvidia,pins = "hdint", "ld0", "ld1", "ld2",
203 "ld3", "ld4", "ld5", "ld6", "ld7",
204 "ld8", "ld9", "ld10", "ld11", "ld12",
205 "ld13", "ld14", "ld15", "ld16", "ld17",
206 "ldc", "ldi", "lhs", "lsc0", "lspi",
207 "lvs", "pmc";
208 nvidia,tristate = <0>;
209 };
210 conf_lc {
211 nvidia,pins = "lc", "ls";
212 nvidia,pull = <2>;
213 };
214 conf_lcsn {
215 nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
216 "lm0", "lm1", "lpp", "lpw0", "lpw1",
217 "lpw2", "lsc1", "lsck", "lsda", "lsdi",
218 "lvp0", "lvp1", "sdb";
219 nvidia,tristate = <1>;
220 };
221 conf_ld17_0 {
222 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
223 "ld23_22";
224 nvidia,pull = <1>;
225 };
226 };
227 };
228
229 i2s@70002800 {
230 status = "okay";
231 };
232
233 serial@70006000 {
234 status = "okay";
235 clock-frequency = <216000000>;
236 };
237
238 serial@70006200 {
239 status = "okay";
240 clock-frequency = <216000000>;
241 };
242
243 i2c@7000c000 {
244 status = "okay";
245 clock-frequency = <400000>;
246
247 alc5632: alc5632@1e {
248 compatible = "realtek,alc5632";
249 reg = <0x1e>;
250 gpio-controller;
251 #gpio-cells = <2>;
252 };
253 };
254
255 i2c@7000c400 {
256 status = "okay";
257 clock-frequency = <400000>;
258 };
259
260 nvec {
261 compatible = "nvidia,nvec";
262 reg = <0x7000c500 0x100>;
263 interrupts = <0 92 0x04>;
264 #address-cells = <1>;
265 #size-cells = <0>;
266 clock-frequency = <80000>;
267 request-gpios = <&gpio 170 0>; /* gpio PV2 */
268 slave-addr = <138>;
269 };
270
271 i2c@7000d000 {
272 status = "okay";
273 clock-frequency = <400000>;
274
275 pmic: tps6586x@34 {
276 compatible = "ti,tps6586x";
277 reg = <0x34>;
278 interrupts = <0 86 0x4>;
279
280 #gpio-cells = <2>;
281 gpio-controller;
282
283 sys-supply = <&p5valw_reg>;
284 vin-sm0-supply = <&sys_reg>;
285 vin-sm1-supply = <&sys_reg>;
286 vin-sm2-supply = <&sys_reg>;
287 vinldo01-supply = <&sm2_reg>;
288 vinldo23-supply = <&sm2_reg>;
289 vinldo4-supply = <&sm2_reg>;
290 vinldo678-supply = <&sm2_reg>;
291 vinldo9-supply = <&sm2_reg>;
292
293 regulators {
294 sys_reg: sys {
295 regulator-name = "vdd_sys";
296 regulator-always-on;
297 };
298
299 sm0 {
300 regulator-name = "+1.2vs_sm0,vdd_core";
301 regulator-min-microvolt = <1200000>;
302 regulator-max-microvolt = <1200000>;
303 regulator-always-on;
304 };
305
306 sm1 {
307 regulator-name = "+1.0vs_sm1,vdd_cpu";
308 regulator-min-microvolt = <1000000>;
309 regulator-max-microvolt = <1000000>;
310 regulator-always-on;
311 };
312
313 sm2_reg: sm2 {
314 regulator-name = "+3.7vs_sm2,vin_ldo*";
315 regulator-min-microvolt = <3700000>;
316 regulator-max-microvolt = <3700000>;
317 regulator-always-on;
318 };
319
320 /* LDO0 is not connected to anything */
321
322 ldo1 {
323 regulator-name = "+1.1vs_ldo1,avdd_pll*";
324 regulator-min-microvolt = <1100000>;
325 regulator-max-microvolt = <1100000>;
326 regulator-always-on;
327 };
328
329 ldo2 {
330 regulator-name = "+1.2vs_ldo2,vdd_rtc";
331 regulator-min-microvolt = <1200000>;
332 regulator-max-microvolt = <1200000>;
333 };
334
335 ldo3 {
336 regulator-name = "+3.3vs_ldo3,avdd_usb*";
337 regulator-min-microvolt = <3300000>;
338 regulator-max-microvolt = <3300000>;
339 regulator-always-on;
340 };
341
342 ldo4 {
343 regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys";
344 regulator-min-microvolt = <1800000>;
345 regulator-max-microvolt = <1800000>;
346 regulator-always-on;
347 };
348
349 ldo5 {
350 regulator-name = "+2.85vs_ldo5,vcore_mmc";
351 regulator-min-microvolt = <2850000>;
352 regulator-max-microvolt = <2850000>;
353 regulator-always-on;
354 };
355
356 ldo6 {
357 /*
358 * Research indicates this should be
359 * 1.8v; other boards that use this
360 * rail for the same purpose need it
361 * set to 1.8v. The schematic signal
362 * name is incorrect; perhaps copied
363 * from an incorrect NVIDIA reference.
364 */
365 regulator-name = "+2.85vs_ldo6,avdd_vdac";
366 regulator-min-microvolt = <1800000>;
367 regulator-max-microvolt = <1800000>;
368 };
369
370 ldo7 {
371 regulator-name = "+3.3vs_ldo7,avdd_hdmi";
372 regulator-min-microvolt = <3300000>;
373 regulator-max-microvolt = <3300000>;
374 };
375
376 ldo8 {
377 regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll";
378 regulator-min-microvolt = <1800000>;
379 regulator-max-microvolt = <1800000>;
380 };
381
382 ldo9 {
383 regulator-name = "+2.85vs_ldo9,vdd_ddr_rx";
384 regulator-min-microvolt = <2850000>;
385 regulator-max-microvolt = <2850000>;
386 regulator-always-on;
387 };
388
389 ldo_rtc {
390 regulator-name = "+3.3vs_rtc";
391 regulator-min-microvolt = <3300000>;
392 regulator-max-microvolt = <3300000>;
393 regulator-always-on;
394 };
395 };
396 };
397
398 adt7461@4c {
399 compatible = "adi,adt7461";
400 reg = <0x4c>;
401 };
402 };
403
404 pmc {
405 nvidia,invert-interrupt;
406 };
407
408 usb@c5000000 {
409 status = "okay";
410 };
411
412 usb@c5004000 {
413 status = "okay";
414 nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
415 };
416
417 usb@c5008000 {
418 status = "okay";
419 };
420
421 sdhci@c8000000 {
422 status = "okay";
423 cd-gpios = <&gpio 173 0>; /* gpio PV5 */
424 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
425 power-gpios = <&gpio 169 0>; /* gpio PV1 */
426 bus-width = <4>;
427 };
428
429 sdhci@c8000600 {
430 status = "okay";
431 bus-width = <8>;
432 };
433
434 gpio-keys {
435 compatible = "gpio-keys";
436
437 power {
438 label = "Power";
439 gpios = <&gpio 79 1>; /* gpio PJ7, active low */
440 linux,code = <116>; /* KEY_POWER */
441 gpio-key,wakeup;
442 };
443 };
444
445 gpio-leds {
446 compatible = "gpio-leds";
447
448 wifi {
449 label = "wifi-led";
450 gpios = <&gpio 24 0>; /* gpio PD0 */
451 linux,default-trigger = "rfkill0";
452 };
453 };
454
455 regulators {
456 compatible = "simple-bus";
457 #address-cells = <1>;
458 #size-cells = <0>;
459
460 p5valw_reg: regulator@0 {
461 compatible = "regulator-fixed";
462 reg = <0>;
463 regulator-name = "+5valw";
464 regulator-min-microvolt = <5000000>;
465 regulator-max-microvolt = <5000000>;
466 regulator-always-on;
467 };
468 };
469
470 sound {
471 compatible = "nvidia,tegra-audio-alc5632-paz00",
472 "nvidia,tegra-audio-alc5632";
473
474 nvidia,model = "Compal PAZ00";
475
476 nvidia,audio-routing =
477 "Int Spk", "SPKOUT",
478 "Int Spk", "SPKOUTN",
479 "Headset Mic", "MICBIAS1",
480 "MIC1", "Headset Mic",
481 "Headset Stereophone", "HPR",
482 "Headset Stereophone", "HPL",
483 "DMICDAT", "Digital Mic";
484
485 nvidia,audio-codec = <&alc5632>;
486 nvidia,i2s-controller = <&tegra_i2s1>;
487 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
488 };
489};
diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts
deleted file mode 100644
index 289480026fb..00000000000
--- a/arch/arm/boot/dts/tegra20-plutux.dts
+++ /dev/null
@@ -1,56 +0,0 @@
1/dts-v1/;
2
3/include/ "tegra20-tamonten.dtsi"
4
5/ {
6 model = "Avionic Design Plutux board";
7 compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20";
8
9 host1x {
10 hdmi {
11 status = "okay";
12 };
13 };
14
15 i2c@7000c000 {
16 wm8903: wm8903@1a {
17 compatible = "wlf,wm8903";
18 reg = <0x1a>;
19 interrupt-parent = <&gpio>;
20 interrupts = <187 0x04>;
21
22 gpio-controller;
23 #gpio-cells = <2>;
24
25 micdet-cfg = <0>;
26 micdet-delay = <100>;
27 gpio-cfg = <0xffffffff
28 0xffffffff
29 0
30 0xffffffff
31 0xffffffff>;
32 };
33 };
34
35 sound {
36 compatible = "ad,tegra-audio-plutux",
37 "nvidia,tegra-audio-wm8903";
38 nvidia,model = "Avionic Design Plutux";
39
40 nvidia,audio-routing =
41 "Headphone Jack", "HPOUTR",
42 "Headphone Jack", "HPOUTL",
43 "Int Spk", "ROP",
44 "Int Spk", "RON",
45 "Int Spk", "LOP",
46 "Int Spk", "LON",
47 "Mic Jack", "MICBIAS",
48 "IN1L", "Mic Jack";
49
50 nvidia,i2s-controller = <&tegra_i2s1>;
51 nvidia,audio-codec = <&wm8903>;
52
53 nvidia,spkr-en-gpios = <&wm8903 2 0>;
54 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
55 };
56};
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
deleted file mode 100644
index 420459825b4..00000000000
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ /dev/null
@@ -1,658 +0,0 @@
1/dts-v1/;
2
3/include/ "tegra20.dtsi"
4
5/ {
6 model = "NVIDIA Seaboard";
7 compatible = "nvidia,seaboard", "nvidia,tegra20";
8
9 memory {
10 reg = <0x00000000 0x40000000>;
11 };
12
13 pinmux {
14 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>;
16
17 state_default: pinmux {
18 ata {
19 nvidia,pins = "ata";
20 nvidia,function = "ide";
21 };
22 atb {
23 nvidia,pins = "atb", "gma", "gme";
24 nvidia,function = "sdio4";
25 };
26 atc {
27 nvidia,pins = "atc";
28 nvidia,function = "nand";
29 };
30 atd {
31 nvidia,pins = "atd", "ate", "gmb", "spia",
32 "spib", "spic";
33 nvidia,function = "gmi";
34 };
35 cdev1 {
36 nvidia,pins = "cdev1";
37 nvidia,function = "plla_out";
38 };
39 cdev2 {
40 nvidia,pins = "cdev2";
41 nvidia,function = "pllp_out4";
42 };
43 crtp {
44 nvidia,pins = "crtp", "lm1";
45 nvidia,function = "crt";
46 };
47 csus {
48 nvidia,pins = "csus";
49 nvidia,function = "vi_sensor_clk";
50 };
51 dap1 {
52 nvidia,pins = "dap1";
53 nvidia,function = "dap1";
54 };
55 dap2 {
56 nvidia,pins = "dap2";
57 nvidia,function = "dap2";
58 };
59 dap3 {
60 nvidia,pins = "dap3";
61 nvidia,function = "dap3";
62 };
63 dap4 {
64 nvidia,pins = "dap4";
65 nvidia,function = "dap4";
66 };
67 dta {
68 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
69 nvidia,function = "vi";
70 };
71 dtf {
72 nvidia,pins = "dtf";
73 nvidia,function = "i2c3";
74 };
75 gmc {
76 nvidia,pins = "gmc";
77 nvidia,function = "uartd";
78 };
79 gmd {
80 nvidia,pins = "gmd";
81 nvidia,function = "sflash";
82 };
83 gpu {
84 nvidia,pins = "gpu";
85 nvidia,function = "pwm";
86 };
87 gpu7 {
88 nvidia,pins = "gpu7";
89 nvidia,function = "rtck";
90 };
91 gpv {
92 nvidia,pins = "gpv", "slxa", "slxk";
93 nvidia,function = "pcie";
94 };
95 hdint {
96 nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1",
97 "lsck", "lsda";
98 nvidia,function = "hdmi";
99 };
100 i2cp {
101 nvidia,pins = "i2cp";
102 nvidia,function = "i2cp";
103 };
104 irrx {
105 nvidia,pins = "irrx", "irtx";
106 nvidia,function = "uartb";
107 };
108 kbca {
109 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
110 "kbce", "kbcf";
111 nvidia,function = "kbc";
112 };
113 lcsn {
114 nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
115 "lsdi", "lvp0";
116 nvidia,function = "rsvd4";
117 };
118 ld0 {
119 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
120 "ld5", "ld6", "ld7", "ld8", "ld9",
121 "ld10", "ld11", "ld12", "ld13", "ld14",
122 "ld15", "ld16", "ld17", "ldi", "lhp0",
123 "lhp1", "lhp2", "lhs", "lpp", "lsc0",
124 "lspi", "lvp1", "lvs";
125 nvidia,function = "displaya";
126 };
127 owc {
128 nvidia,pins = "owc", "spdi", "spdo", "uac";
129 nvidia,function = "rsvd2";
130 };
131 pmc {
132 nvidia,pins = "pmc";
133 nvidia,function = "pwr_on";
134 };
135 rm {
136 nvidia,pins = "rm";
137 nvidia,function = "i2c1";
138 };
139 sdb {
140 nvidia,pins = "sdb", "sdc", "sdd";
141 nvidia,function = "sdio3";
142 };
143 sdio1 {
144 nvidia,pins = "sdio1";
145 nvidia,function = "sdio1";
146 };
147 slxc {
148 nvidia,pins = "slxc", "slxd";
149 nvidia,function = "spdif";
150 };
151 spid {
152 nvidia,pins = "spid", "spie", "spif";
153 nvidia,function = "spi1";
154 };
155 spig {
156 nvidia,pins = "spig", "spih";
157 nvidia,function = "spi2_alt";
158 };
159 uaa {
160 nvidia,pins = "uaa", "uab", "uda";
161 nvidia,function = "ulpi";
162 };
163 uad {
164 nvidia,pins = "uad";
165 nvidia,function = "irda";
166 };
167 uca {
168 nvidia,pins = "uca", "ucb";
169 nvidia,function = "uartc";
170 };
171 conf_ata {
172 nvidia,pins = "ata", "atb", "atc", "atd",
173 "cdev1", "cdev2", "dap1", "dap2",
174 "dap4", "ddc", "dtf", "gma", "gmc", "gmd",
175 "gme", "gpu", "gpu7", "i2cp", "irrx",
176 "irtx", "pta", "rm", "sdc", "sdd",
177 "slxd", "slxk", "spdi", "spdo", "uac",
178 "uad", "uca", "ucb", "uda";
179 nvidia,pull = <0>;
180 nvidia,tristate = <0>;
181 };
182 conf_ate {
183 nvidia,pins = "ate", "csus", "dap3",
184 "gpv", "owc", "slxc", "spib", "spid",
185 "spie";
186 nvidia,pull = <0>;
187 nvidia,tristate = <1>;
188 };
189 conf_ck32 {
190 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
191 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
192 nvidia,pull = <0>;
193 };
194 conf_crtp {
195 nvidia,pins = "crtp", "gmb", "slxa", "spia",
196 "spig", "spih";
197 nvidia,pull = <2>;
198 nvidia,tristate = <1>;
199 };
200 conf_dta {
201 nvidia,pins = "dta", "dtb", "dtc", "dtd";
202 nvidia,pull = <1>;
203 nvidia,tristate = <0>;
204 };
205 conf_dte {
206 nvidia,pins = "dte", "spif";
207 nvidia,pull = <1>;
208 nvidia,tristate = <1>;
209 };
210 conf_hdint {
211 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
212 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
213 "lvp0";
214 nvidia,tristate = <1>;
215 };
216 conf_kbca {
217 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
218 "kbce", "kbcf", "sdio1", "spic", "uaa",
219 "uab";
220 nvidia,pull = <2>;
221 nvidia,tristate = <0>;
222 };
223 conf_lc {
224 nvidia,pins = "lc", "ls";
225 nvidia,pull = <2>;
226 };
227 conf_ld0 {
228 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
229 "ld5", "ld6", "ld7", "ld8", "ld9",
230 "ld10", "ld11", "ld12", "ld13", "ld14",
231 "ld15", "ld16", "ld17", "ldi", "lhp0",
232 "lhp1", "lhp2", "lhs", "lm0", "lpp",
233 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
234 "lvs", "pmc", "sdb";
235 nvidia,tristate = <0>;
236 };
237 conf_ld17_0 {
238 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
239 "ld23_22";
240 nvidia,pull = <1>;
241 };
242 drive_sdio1 {
243 nvidia,pins = "drive_sdio1";
244 nvidia,high-speed-mode = <0>;
245 nvidia,schmitt = <0>;
246 nvidia,low-power-mode = <3>;
247 nvidia,pull-down-strength = <31>;
248 nvidia,pull-up-strength = <31>;
249 nvidia,slew-rate-rising = <3>;
250 nvidia,slew-rate-falling = <3>;
251 };
252 };
253
254 state_i2cmux_ddc: pinmux_i2cmux_ddc {
255 ddc {
256 nvidia,pins = "ddc";
257 nvidia,function = "i2c2";
258 };
259 pta {
260 nvidia,pins = "pta";
261 nvidia,function = "rsvd4";
262 };
263 };
264
265 state_i2cmux_pta: pinmux_i2cmux_pta {
266 ddc {
267 nvidia,pins = "ddc";
268 nvidia,function = "rsvd4";
269 };
270 pta {
271 nvidia,pins = "pta";
272 nvidia,function = "i2c2";
273 };
274 };
275
276 state_i2cmux_idle: pinmux_i2cmux_idle {
277 ddc {
278 nvidia,pins = "ddc";
279 nvidia,function = "rsvd4";
280 };
281 pta {
282 nvidia,pins = "pta";
283 nvidia,function = "rsvd4";
284 };
285 };
286 };
287
288 i2s@70002800 {
289 status = "okay";
290 };
291
292 serial@70006300 {
293 status = "okay";
294 clock-frequency = <216000000>;
295 };
296
297 i2c@7000c000 {
298 status = "okay";
299 clock-frequency = <400000>;
300
301 wm8903: wm8903@1a {
302 compatible = "wlf,wm8903";
303 reg = <0x1a>;
304 interrupt-parent = <&gpio>;
305 interrupts = <187 0x04>;
306
307 gpio-controller;
308 #gpio-cells = <2>;
309
310 micdet-cfg = <0>;
311 micdet-delay = <100>;
312 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
313 };
314
315 /* ALS and proximity sensor */
316 isl29018@44 {
317 compatible = "isil,isl29018";
318 reg = <0x44>;
319 interrupt-parent = <&gpio>;
320 interrupts = <202 0x04>; /* GPIO PZ2 */
321 };
322
323 gyrometer@68 {
324 compatible = "invn,mpu3050";
325 reg = <0x68>;
326 interrupt-parent = <&gpio>;
327 interrupts = <204 0x04>; /* gpio PZ4 */
328 };
329 };
330
331 i2c@7000c400 {
332 status = "okay";
333 clock-frequency = <100000>;
334 };
335
336 i2cmux {
337 compatible = "i2c-mux-pinctrl";
338 #address-cells = <1>;
339 #size-cells = <0>;
340
341 i2c-parent = <&{/i2c@7000c400}>;
342
343 pinctrl-names = "ddc", "pta", "idle";
344 pinctrl-0 = <&state_i2cmux_ddc>;
345 pinctrl-1 = <&state_i2cmux_pta>;
346 pinctrl-2 = <&state_i2cmux_idle>;
347
348 i2c@0 {
349 reg = <0>;
350 #address-cells = <1>;
351 #size-cells = <0>;
352 };
353
354 i2c@1 {
355 reg = <1>;
356 #address-cells = <1>;
357 #size-cells = <0>;
358
359 smart-battery@b {
360 compatible = "ti,bq20z75", "smart-battery-1.1";
361 reg = <0xb>;
362 ti,i2c-retry-count = <2>;
363 ti,poll-retry-count = <10>;
364 };
365 };
366 };
367
368 i2c@7000c500 {
369 status = "okay";
370 clock-frequency = <400000>;
371 };
372
373 i2c@7000d000 {
374 status = "okay";
375 clock-frequency = <400000>;
376
377 pmic: tps6586x@34 {
378 compatible = "ti,tps6586x";
379 reg = <0x34>;
380 interrupts = <0 86 0x4>;
381
382 ti,system-power-controller;
383
384 #gpio-cells = <2>;
385 gpio-controller;
386
387 sys-supply = <&vdd_5v0_reg>;
388 vin-sm0-supply = <&sys_reg>;
389 vin-sm1-supply = <&sys_reg>;
390 vin-sm2-supply = <&sys_reg>;
391 vinldo01-supply = <&sm2_reg>;
392 vinldo23-supply = <&sm2_reg>;
393 vinldo4-supply = <&sm2_reg>;
394 vinldo678-supply = <&sm2_reg>;
395 vinldo9-supply = <&sm2_reg>;
396
397 regulators {
398 sys_reg: sys {
399 regulator-name = "vdd_sys";
400 regulator-always-on;
401 };
402
403 sm0 {
404 regulator-name = "vdd_sm0,vdd_core";
405 regulator-min-microvolt = <1300000>;
406 regulator-max-microvolt = <1300000>;
407 regulator-always-on;
408 };
409
410 sm1 {
411 regulator-name = "vdd_sm1,vdd_cpu";
412 regulator-min-microvolt = <1125000>;
413 regulator-max-microvolt = <1125000>;
414 regulator-always-on;
415 };
416
417 sm2_reg: sm2 {
418 regulator-name = "vdd_sm2,vin_ldo*";
419 regulator-min-microvolt = <3700000>;
420 regulator-max-microvolt = <3700000>;
421 regulator-always-on;
422 };
423
424 /* LDO0 is not connected to anything */
425
426 ldo1 {
427 regulator-name = "vdd_ldo1,avdd_pll*";
428 regulator-min-microvolt = <1100000>;
429 regulator-max-microvolt = <1100000>;
430 regulator-always-on;
431 };
432
433 ldo2 {
434 regulator-name = "vdd_ldo2,vdd_rtc";
435 regulator-min-microvolt = <1200000>;
436 regulator-max-microvolt = <1200000>;
437 };
438
439 ldo3 {
440 regulator-name = "vdd_ldo3,avdd_usb*";
441 regulator-min-microvolt = <3300000>;
442 regulator-max-microvolt = <3300000>;
443 regulator-always-on;
444 };
445
446 ldo4 {
447 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
448 regulator-min-microvolt = <1800000>;
449 regulator-max-microvolt = <1800000>;
450 regulator-always-on;
451 };
452
453 ldo5 {
454 regulator-name = "vdd_ldo5,vcore_mmc";
455 regulator-min-microvolt = <2850000>;
456 regulator-max-microvolt = <2850000>;
457 regulator-always-on;
458 };
459
460 ldo6 {
461 regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
462 regulator-min-microvolt = <1800000>;
463 regulator-max-microvolt = <1800000>;
464 };
465
466 ldo7 {
467 regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
468 regulator-min-microvolt = <3300000>;
469 regulator-max-microvolt = <3300000>;
470 };
471
472 ldo8 {
473 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
474 regulator-min-microvolt = <1800000>;
475 regulator-max-microvolt = <1800000>;
476 };
477
478 ldo9 {
479 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
480 regulator-min-microvolt = <2850000>;
481 regulator-max-microvolt = <2850000>;
482 regulator-always-on;
483 };
484
485 ldo_rtc {
486 regulator-name = "vdd_rtc_out,vdd_cell";
487 regulator-min-microvolt = <3300000>;
488 regulator-max-microvolt = <3300000>;
489 regulator-always-on;
490 };
491 };
492 };
493
494 temperature-sensor@4c {
495 compatible = "onnn,nct1008";
496 reg = <0x4c>;
497 };
498
499 magnetometer@c {
500 compatible = "ak,ak8975";
501 reg = <0xc>;
502 interrupt-parent = <&gpio>;
503 interrupts = <109 0x04>; /* gpio PN5 */
504 };
505 };
506
507 pmc {
508 nvidia,invert-interrupt;
509 };
510
511 memory-controller@7000f400 {
512 emc-table@190000 {
513 reg = <190000>;
514 compatible = "nvidia,tegra20-emc-table";
515 clock-frequency = <190000>;
516 nvidia,emc-registers = <0x0000000c 0x00000026
517 0x00000009 0x00000003 0x00000004 0x00000004
518 0x00000002 0x0000000c 0x00000003 0x00000003
519 0x00000002 0x00000001 0x00000004 0x00000005
520 0x00000004 0x00000009 0x0000000d 0x0000059f
521 0x00000000 0x00000003 0x00000003 0x00000003
522 0x00000003 0x00000001 0x0000000b 0x000000c8
523 0x00000003 0x00000007 0x00000004 0x0000000f
524 0x00000002 0x00000000 0x00000000 0x00000002
525 0x00000000 0x00000000 0x00000083 0xa06204ae
526 0x007dc010 0x00000000 0x00000000 0x00000000
527 0x00000000 0x00000000 0x00000000 0x00000000>;
528 };
529
530 emc-table@380000 {
531 reg = <380000>;
532 compatible = "nvidia,tegra20-emc-table";
533 clock-frequency = <380000>;
534 nvidia,emc-registers = <0x00000017 0x0000004b
535 0x00000012 0x00000006 0x00000004 0x00000005
536 0x00000003 0x0000000c 0x00000006 0x00000006
537 0x00000003 0x00000001 0x00000004 0x00000005
538 0x00000004 0x00000009 0x0000000d 0x00000b5f
539 0x00000000 0x00000003 0x00000003 0x00000006
540 0x00000006 0x00000001 0x00000011 0x000000c8
541 0x00000003 0x0000000e 0x00000007 0x0000000f
542 0x00000002 0x00000000 0x00000000 0x00000002
543 0x00000000 0x00000000 0x00000083 0xe044048b
544 0x007d8010 0x00000000 0x00000000 0x00000000
545 0x00000000 0x00000000 0x00000000 0x00000000>;
546 };
547 };
548
549 usb@c5000000 {
550 status = "okay";
551 nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
552 dr_mode = "otg";
553 };
554
555 usb@c5004000 {
556 status = "okay";
557 nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
558 };
559
560 usb@c5008000 {
561 status = "okay";
562 };
563
564 sdhci@c8000000 {
565 status = "okay";
566 power-gpios = <&gpio 86 0>; /* gpio PK6 */
567 bus-width = <4>;
568 };
569
570 sdhci@c8000400 {
571 status = "okay";
572 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
573 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
574 power-gpios = <&gpio 70 0>; /* gpio PI6 */
575 bus-width = <4>;
576 };
577
578 sdhci@c8000600 {
579 status = "okay";
580 bus-width = <8>;
581 };
582
583 gpio-keys {
584 compatible = "gpio-keys";
585
586 power {
587 label = "Power";
588 gpios = <&gpio 170 1>; /* gpio PV2, active low */
589 linux,code = <116>; /* KEY_POWER */
590 gpio-key,wakeup;
591 };
592
593 lid {
594 label = "Lid";
595 gpios = <&gpio 23 0>; /* gpio PC7 */
596 linux,input-type = <5>; /* EV_SW */
597 linux,code = <0>; /* SW_LID */
598 debounce-interval = <1>;
599 gpio-key,wakeup;
600 };
601 };
602
603 regulators {
604 compatible = "simple-bus";
605 #address-cells = <1>;
606 #size-cells = <0>;
607
608 vdd_5v0_reg: regulator@0 {
609 compatible = "regulator-fixed";
610 reg = <0>;
611 regulator-name = "vdd_5v0";
612 regulator-min-microvolt = <5000000>;
613 regulator-max-microvolt = <5000000>;
614 regulator-always-on;
615 };
616
617 regulator@1 {
618 compatible = "regulator-fixed";
619 reg = <1>;
620 regulator-name = "vdd_1v5";
621 regulator-min-microvolt = <1500000>;
622 regulator-max-microvolt = <1500000>;
623 gpio = <&pmic 0 0>;
624 };
625
626 regulator@2 {
627 compatible = "regulator-fixed";
628 reg = <2>;
629 regulator-name = "vdd_1v2";
630 regulator-min-microvolt = <1200000>;
631 regulator-max-microvolt = <1200000>;
632 gpio = <&pmic 1 0>;
633 enable-active-high;
634 };
635 };
636
637 sound {
638 compatible = "nvidia,tegra-audio-wm8903-seaboard",
639 "nvidia,tegra-audio-wm8903";
640 nvidia,model = "NVIDIA Tegra Seaboard";
641
642 nvidia,audio-routing =
643 "Headphone Jack", "HPOUTR",
644 "Headphone Jack", "HPOUTL",
645 "Int Spk", "ROP",
646 "Int Spk", "RON",
647 "Int Spk", "LOP",
648 "Int Spk", "LON",
649 "Mic Jack", "MICBIAS",
650 "IN1R", "Mic Jack";
651
652 nvidia,i2s-controller = <&tegra_i2s1>;
653 nvidia,audio-codec = <&wm8903>;
654
655 nvidia,spkr-en-gpios = <&wm8903 2 0>;
656 nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */
657 };
658};
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
deleted file mode 100644
index a239ccdfaa5..00000000000
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ /dev/null
@@ -1,490 +0,0 @@
1/include/ "tegra20.dtsi"
2
3/ {
4 model = "Avionic Design Tamonten SOM";
5 compatible = "ad,tamonten", "nvidia,tegra20";
6
7 memory {
8 reg = <0x00000000 0x20000000>;
9 };
10
11 host1x {
12 hdmi {
13 vdd-supply = <&hdmi_vdd_reg>;
14 pll-supply = <&hdmi_pll_reg>;
15
16 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
17 nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
18 };
19 };
20
21 pinmux {
22 pinctrl-names = "default";
23 pinctrl-0 = <&state_default>;
24
25 state_default: pinmux {
26 ata {
27 nvidia,pins = "ata";
28 nvidia,function = "ide";
29 };
30 atb {
31 nvidia,pins = "atb", "gma", "gme";
32 nvidia,function = "sdio4";
33 };
34 atc {
35 nvidia,pins = "atc";
36 nvidia,function = "nand";
37 };
38 atd {
39 nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
40 "spia", "spib", "spic";
41 nvidia,function = "gmi";
42 };
43 cdev1 {
44 nvidia,pins = "cdev1";
45 nvidia,function = "plla_out";
46 };
47 cdev2 {
48 nvidia,pins = "cdev2";
49 nvidia,function = "pllp_out4";
50 };
51 crtp {
52 nvidia,pins = "crtp";
53 nvidia,function = "crt";
54 };
55 csus {
56 nvidia,pins = "csus";
57 nvidia,function = "vi_sensor_clk";
58 };
59 dap1 {
60 nvidia,pins = "dap1";
61 nvidia,function = "dap1";
62 };
63 dap2 {
64 nvidia,pins = "dap2";
65 nvidia,function = "dap2";
66 };
67 dap3 {
68 nvidia,pins = "dap3";
69 nvidia,function = "dap3";
70 };
71 dap4 {
72 nvidia,pins = "dap4";
73 nvidia,function = "dap4";
74 };
75 dta {
76 nvidia,pins = "dta", "dtd";
77 nvidia,function = "sdio2";
78 };
79 dtb {
80 nvidia,pins = "dtb", "dtc", "dte";
81 nvidia,function = "rsvd1";
82 };
83 dtf {
84 nvidia,pins = "dtf";
85 nvidia,function = "i2c3";
86 };
87 gmc {
88 nvidia,pins = "gmc";
89 nvidia,function = "uartd";
90 };
91 gpu7 {
92 nvidia,pins = "gpu7";
93 nvidia,function = "rtck";
94 };
95 gpv {
96 nvidia,pins = "gpv", "slxa", "slxk";
97 nvidia,function = "pcie";
98 };
99 hdint {
100 nvidia,pins = "hdint";
101 nvidia,function = "hdmi";
102 };
103 i2cp {
104 nvidia,pins = "i2cp";
105 nvidia,function = "i2cp";
106 };
107 irrx {
108 nvidia,pins = "irrx", "irtx";
109 nvidia,function = "uarta";
110 };
111 kbca {
112 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
113 "kbce", "kbcf";
114 nvidia,function = "kbc";
115 };
116 lcsn {
117 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
118 "ld3", "ld4", "ld5", "ld6", "ld7",
119 "ld8", "ld9", "ld10", "ld11", "ld12",
120 "ld13", "ld14", "ld15", "ld16", "ld17",
121 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
122 "lhs", "lm0", "lm1", "lpp", "lpw0",
123 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
124 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
125 "lvs";
126 nvidia,function = "displaya";
127 };
128 owc {
129 nvidia,pins = "owc", "spdi", "spdo", "uac";
130 nvidia,function = "rsvd2";
131 };
132 pmc {
133 nvidia,pins = "pmc";
134 nvidia,function = "pwr_on";
135 };
136 rm {
137 nvidia,pins = "rm";
138 nvidia,function = "i2c1";
139 };
140 sdb {
141 nvidia,pins = "sdb", "sdc", "sdd";
142 nvidia,function = "pwm";
143 };
144 sdio1 {
145 nvidia,pins = "sdio1";
146 nvidia,function = "sdio1";
147 };
148 slxc {
149 nvidia,pins = "slxc", "slxd";
150 nvidia,function = "spdif";
151 };
152 spid {
153 nvidia,pins = "spid", "spie", "spif";
154 nvidia,function = "spi1";
155 };
156 spig {
157 nvidia,pins = "spig", "spih";
158 nvidia,function = "spi2_alt";
159 };
160 uaa {
161 nvidia,pins = "uaa", "uab", "uda";
162 nvidia,function = "ulpi";
163 };
164 uad {
165 nvidia,pins = "uad";
166 nvidia,function = "irda";
167 };
168 uca {
169 nvidia,pins = "uca", "ucb";
170 nvidia,function = "uartc";
171 };
172 conf_ata {
173 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
174 "cdev1", "cdev2", "dap1", "dtb", "gma",
175 "gmb", "gmc", "gmd", "gme", "gpu7",
176 "gpv", "i2cp", "pta", "rm", "slxa",
177 "slxk", "spia", "spib", "uac";
178 nvidia,pull = <0>;
179 nvidia,tristate = <0>;
180 };
181 conf_ck32 {
182 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
183 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
184 nvidia,pull = <0>;
185 };
186 conf_csus {
187 nvidia,pins = "csus", "spid", "spif";
188 nvidia,pull = <1>;
189 nvidia,tristate = <1>;
190 };
191 conf_crtp {
192 nvidia,pins = "crtp", "dap2", "dap3", "dap4",
193 "dtc", "dte", "dtf", "gpu", "sdio1",
194 "slxc", "slxd", "spdi", "spdo", "spig",
195 "uda";
196 nvidia,pull = <0>;
197 nvidia,tristate = <1>;
198 };
199 conf_ddc {
200 nvidia,pins = "ddc", "dta", "dtd", "kbca",
201 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
202 "sdc";
203 nvidia,pull = <2>;
204 nvidia,tristate = <0>;
205 };
206 conf_hdint {
207 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
208 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
209 "lvp0", "owc", "sdb";
210 nvidia,tristate = <1>;
211 };
212 conf_irrx {
213 nvidia,pins = "irrx", "irtx", "sdd", "spic",
214 "spie", "spih", "uaa", "uab", "uad",
215 "uca", "ucb";
216 nvidia,pull = <2>;
217 nvidia,tristate = <1>;
218 };
219 conf_lc {
220 nvidia,pins = "lc", "ls";
221 nvidia,pull = <2>;
222 };
223 conf_ld0 {
224 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
225 "ld5", "ld6", "ld7", "ld8", "ld9",
226 "ld10", "ld11", "ld12", "ld13", "ld14",
227 "ld15", "ld16", "ld17", "ldi", "lhp0",
228 "lhp1", "lhp2", "lhs", "lm0", "lpp",
229 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
230 "lvs", "pmc";
231 nvidia,tristate = <0>;
232 };
233 conf_ld17_0 {
234 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
235 "ld23_22";
236 nvidia,pull = <1>;
237 };
238 };
239
240 state_i2cmux_ddc: pinmux_i2cmux_ddc {
241 ddc {
242 nvidia,pins = "ddc";
243 nvidia,function = "i2c2";
244 };
245 pta {
246 nvidia,pins = "pta";
247 nvidia,function = "rsvd4";
248 };
249 };
250
251 state_i2cmux_pta: pinmux_i2cmux_pta {
252 ddc {
253 nvidia,pins = "ddc";
254 nvidia,function = "rsvd4";
255 };
256 pta {
257 nvidia,pins = "pta";
258 nvidia,function = "i2c2";
259 };
260 };
261
262 state_i2cmux_idle: pinmux_i2cmux_idle {
263 ddc {
264 nvidia,pins = "ddc";
265 nvidia,function = "rsvd4";
266 };
267 pta {
268 nvidia,pins = "pta";
269 nvidia,function = "rsvd4";
270 };
271 };
272 };
273
274 i2s@70002800 {
275 status = "okay";
276 };
277
278 serial@70006300 {
279 clock-frequency = <216000000>;
280 status = "okay";
281 };
282
283 i2c@7000c000 {
284 clock-frequency = <400000>;
285 status = "okay";
286 };
287
288 i2c@7000c400 {
289 clock-frequency = <100000>;
290 status = "okay";
291 };
292
293 i2cmux {
294 compatible = "i2c-mux-pinctrl";
295 #address-cells = <1>;
296 #size-cells = <0>;
297
298 i2c-parent = <&{/i2c@7000c400}>;
299
300 pinctrl-names = "ddc", "pta", "idle";
301 pinctrl-0 = <&state_i2cmux_ddc>;
302 pinctrl-1 = <&state_i2cmux_pta>;
303 pinctrl-2 = <&state_i2cmux_idle>;
304
305 hdmi_ddc: i2c@0 {
306 reg = <0>;
307 #address-cells = <1>;
308 #size-cells = <0>;
309 };
310
311 i2c@1 {
312 reg = <1>;
313 #address-cells = <1>;
314 #size-cells = <0>;
315 };
316 };
317
318 i2c@7000d000 {
319 clock-frequency = <400000>;
320 status = "okay";
321
322 pmic: tps6586x@34 {
323 compatible = "ti,tps6586x";
324 reg = <0x34>;
325 interrupts = <0 86 0x4>;
326
327 ti,system-power-controller;
328
329 #gpio-cells = <2>;
330 gpio-controller;
331
332 sys-supply = <&vdd_5v0_reg>;
333 vin-sm0-supply = <&sys_reg>;
334 vin-sm1-supply = <&sys_reg>;
335 vin-sm2-supply = <&sys_reg>;
336 vinldo01-supply = <&sm2_reg>;
337 vinldo23-supply = <&sm2_reg>;
338 vinldo4-supply = <&sm2_reg>;
339 vinldo678-supply = <&sm2_reg>;
340 vinldo9-supply = <&sm2_reg>;
341
342 regulators {
343 sys_reg: sys {
344 regulator-name = "vdd_sys";
345 regulator-always-on;
346 };
347
348 sm0 {
349 regulator-name = "vdd_sys_sm0,vdd_core";
350 regulator-min-microvolt = <1200000>;
351 regulator-max-microvolt = <1200000>;
352 regulator-always-on;
353 };
354
355 sm1 {
356 regulator-name = "vdd_sys_sm1,vdd_cpu";
357 regulator-min-microvolt = <1000000>;
358 regulator-max-microvolt = <1000000>;
359 regulator-always-on;
360 };
361
362 sm2_reg: sm2 {
363 regulator-name = "vdd_sys_sm2,vin_ldo*";
364 regulator-min-microvolt = <3700000>;
365 regulator-max-microvolt = <3700000>;
366 regulator-always-on;
367 };
368
369 ldo0 {
370 regulator-name = "vdd_ldo0,vddio_pex_clk";
371 regulator-min-microvolt = <3300000>;
372 regulator-max-microvolt = <3300000>;
373 };
374
375 ldo1 {
376 regulator-name = "vdd_ldo1,avdd_pll*";
377 regulator-min-microvolt = <1100000>;
378 regulator-max-microvolt = <1100000>;
379 regulator-always-on;
380 };
381
382 ldo2 {
383 regulator-name = "vdd_ldo2,vdd_rtc";
384 regulator-min-microvolt = <1200000>;
385 regulator-max-microvolt = <1200000>;
386 };
387
388 ldo3 {
389 regulator-name = "vdd_ldo3,avdd_usb*";
390 regulator-min-microvolt = <3300000>;
391 regulator-max-microvolt = <3300000>;
392 regulator-always-on;
393 };
394
395 ldo4 {
396 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
397 regulator-min-microvolt = <1800000>;
398 regulator-max-microvolt = <1800000>;
399 regulator-always-on;
400 };
401
402 ldo5 {
403 regulator-name = "vdd_ldo5,vcore_mmc";
404 regulator-min-microvolt = <2850000>;
405 regulator-max-microvolt = <2850000>;
406 };
407
408 ldo6 {
409 regulator-name = "vdd_ldo6,avdd_vdac";
410 /*
411 * According to the Tegra 2 Automotive
412 * DataSheet, a typical value for this
413 * would be 2.8V, but the PMIC only
414 * supports 2.85V.
415 */
416 regulator-min-microvolt = <2850000>;
417 regulator-max-microvolt = <2850000>;
418 };
419
420 hdmi_vdd_reg: ldo7 {
421 regulator-name = "vdd_ldo7,avdd_hdmi";
422 regulator-min-microvolt = <3300000>;
423 regulator-max-microvolt = <3300000>;
424 };
425
426 hdmi_pll_reg: ldo8 {
427 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
428 regulator-min-microvolt = <1800000>;
429 regulator-max-microvolt = <1800000>;
430 };
431
432 ldo9 {
433 regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam";
434 /*
435 * According to the Tegra 2 Automotive
436 * DataSheet, a typical value for this
437 * would be 2.8V, but the PMIC only
438 * supports 2.85V.
439 */
440 regulator-min-microvolt = <2850000>;
441 regulator-max-microvolt = <2850000>;
442 regulator-always-on;
443 };
444
445 ldo_rtc {
446 regulator-name = "vdd_rtc_out";
447 regulator-min-microvolt = <3300000>;
448 regulator-max-microvolt = <3300000>;
449 regulator-always-on;
450 };
451 };
452 };
453
454 temperature-sensor@4c {
455 compatible = "onnn,nct1008";
456 reg = <0x4c>;
457 };
458 };
459
460 pmc {
461 nvidia,invert-interrupt;
462 };
463
464 usb@c5008000 {
465 status = "okay";
466 };
467
468 sdhci@c8000600 {
469 cd-gpios = <&gpio 58 0>; /* gpio PH2 */
470 wp-gpios = <&gpio 59 0>; /* gpio PH3 */
471 bus-width = <4>;
472 status = "okay";
473 };
474
475 regulators {
476 compatible = "simple-bus";
477
478 #address-cells = <1>;
479 #size-cells = <0>;
480
481 vdd_5v0_reg: regulator@0 {
482 compatible = "regulator-fixed";
483 reg = <0>;
484 regulator-name = "vdd_5v0";
485 regulator-min-microvolt = <5000000>;
486 regulator-max-microvolt = <5000000>;
487 regulator-always-on;
488 };
489 };
490};
diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts
deleted file mode 100644
index 402b21004be..00000000000
--- a/arch/arm/boot/dts/tegra20-tec.dts
+++ /dev/null
@@ -1,56 +0,0 @@
1/dts-v1/;
2
3/include/ "tegra20-tamonten.dtsi"
4
5/ {
6 model = "Avionic Design Tamonten Evaluation Carrier";
7 compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20";
8
9 host1x {
10 hdmi {
11 status = "okay";
12 };
13 };
14
15 i2c@7000c000 {
16 wm8903: wm8903@1a {
17 compatible = "wlf,wm8903";
18 reg = <0x1a>;
19 interrupt-parent = <&gpio>;
20 interrupts = <187 0x04>;
21
22 gpio-controller;
23 #gpio-cells = <2>;
24
25 micdet-cfg = <0>;
26 micdet-delay = <100>;
27 gpio-cfg = <0xffffffff
28 0xffffffff
29 0
30 0xffffffff
31 0xffffffff>;
32 };
33 };
34
35 sound {
36 compatible = "ad,tegra-audio-wm8903-tec",
37 "nvidia,tegra-audio-wm8903";
38 nvidia,model = "Avionic Design TEC";
39
40 nvidia,audio-routing =
41 "Headphone Jack", "HPOUTR",
42 "Headphone Jack", "HPOUTL",
43 "Int Spk", "ROP",
44 "Int Spk", "RON",
45 "Int Spk", "LOP",
46 "Int Spk", "LON",
47 "Mic Jack", "MICBIAS",
48 "IN1L", "Mic Jack";
49
50 nvidia,i2s-controller = <&tegra_i2s1>;
51 nvidia,audio-codec = <&wm8903>;
52
53 nvidia,spkr-en-gpios = <&wm8903 2 0>;
54 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
55 };
56};
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
deleted file mode 100644
index b70b4cb754c..00000000000
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ /dev/null
@@ -1,354 +0,0 @@
1/dts-v1/;
2
3/include/ "tegra20.dtsi"
4
5/ {
6 model = "Compulab TrimSlice board";
7 compatible = "compulab,trimslice", "nvidia,tegra20";
8
9 memory {
10 reg = <0x00000000 0x40000000>;
11 };
12
13 host1x {
14 hdmi {
15 status = "okay";
16
17 vdd-supply = <&hdmi_vdd_reg>;
18 pll-supply = <&hdmi_pll_reg>;
19
20 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
21 nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
22 };
23 };
24
25 pinmux {
26 pinctrl-names = "default";
27 pinctrl-0 = <&state_default>;
28
29 state_default: pinmux {
30 ata {
31 nvidia,pins = "ata";
32 nvidia,function = "ide";
33 };
34 atb {
35 nvidia,pins = "atb", "gma";
36 nvidia,function = "sdio4";
37 };
38 atc {
39 nvidia,pins = "atc", "gmb";
40 nvidia,function = "nand";
41 };
42 atd {
43 nvidia,pins = "atd", "ate", "gme", "pta";
44 nvidia,function = "gmi";
45 };
46 cdev1 {
47 nvidia,pins = "cdev1";
48 nvidia,function = "plla_out";
49 };
50 cdev2 {
51 nvidia,pins = "cdev2";
52 nvidia,function = "pllp_out4";
53 };
54 crtp {
55 nvidia,pins = "crtp";
56 nvidia,function = "crt";
57 };
58 csus {
59 nvidia,pins = "csus";
60 nvidia,function = "vi_sensor_clk";
61 };
62 dap1 {
63 nvidia,pins = "dap1";
64 nvidia,function = "dap1";
65 };
66 dap2 {
67 nvidia,pins = "dap2";
68 nvidia,function = "dap2";
69 };
70 dap3 {
71 nvidia,pins = "dap3";
72 nvidia,function = "dap3";
73 };
74 dap4 {
75 nvidia,pins = "dap4";
76 nvidia,function = "dap4";
77 };
78 ddc {
79 nvidia,pins = "ddc";
80 nvidia,function = "i2c2";
81 };
82 dta {
83 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
84 nvidia,function = "vi";
85 };
86 dtf {
87 nvidia,pins = "dtf";
88 nvidia,function = "i2c3";
89 };
90 gmc {
91 nvidia,pins = "gmc", "gmd";
92 nvidia,function = "sflash";
93 };
94 gpu {
95 nvidia,pins = "gpu";
96 nvidia,function = "uarta";
97 };
98 gpu7 {
99 nvidia,pins = "gpu7";
100 nvidia,function = "rtck";
101 };
102 gpv {
103 nvidia,pins = "gpv", "slxa", "slxk";
104 nvidia,function = "pcie";
105 };
106 hdint {
107 nvidia,pins = "hdint";
108 nvidia,function = "hdmi";
109 };
110 i2cp {
111 nvidia,pins = "i2cp";
112 nvidia,function = "i2cp";
113 };
114 irrx {
115 nvidia,pins = "irrx", "irtx";
116 nvidia,function = "uartb";
117 };
118 kbca {
119 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
120 "kbce", "kbcf";
121 nvidia,function = "kbc";
122 };
123 lcsn {
124 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
125 "ld3", "ld4", "ld5", "ld6", "ld7",
126 "ld8", "ld9", "ld10", "ld11", "ld12",
127 "ld13", "ld14", "ld15", "ld16", "ld17",
128 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
129 "lhs", "lm0", "lm1", "lpp", "lpw0",
130 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
131 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
132 "lvs";
133 nvidia,function = "displaya";
134 };
135 owc {
136 nvidia,pins = "owc", "uac";
137 nvidia,function = "rsvd2";
138 };
139 pmc {
140 nvidia,pins = "pmc";
141 nvidia,function = "pwr_on";
142 };
143 rm {
144 nvidia,pins = "rm";
145 nvidia,function = "i2c1";
146 };
147 sdb {
148 nvidia,pins = "sdb", "sdc", "sdd";
149 nvidia,function = "pwm";
150 };
151 sdio1 {
152 nvidia,pins = "sdio1";
153 nvidia,function = "sdio1";
154 };
155 slxc {
156 nvidia,pins = "slxc", "slxd";
157 nvidia,function = "sdio3";
158 };
159 spdi {
160 nvidia,pins = "spdi", "spdo";
161 nvidia,function = "spdif";
162 };
163 spia {
164 nvidia,pins = "spia", "spib", "spic";
165 nvidia,function = "spi2";
166 };
167 spid {
168 nvidia,pins = "spid", "spie", "spif";
169 nvidia,function = "spi1";
170 };
171 spig {
172 nvidia,pins = "spig", "spih";
173 nvidia,function = "spi2_alt";
174 };
175 uaa {
176 nvidia,pins = "uaa", "uab", "uda";
177 nvidia,function = "ulpi";
178 };
179 uad {
180 nvidia,pins = "uad";
181 nvidia,function = "irda";
182 };
183 uca {
184 nvidia,pins = "uca", "ucb";
185 nvidia,function = "uartc";
186 };
187 conf_ata {
188 nvidia,pins = "ata", "atc", "atd", "ate",
189 "crtp", "dap2", "dap3", "dap4", "dta",
190 "dtb", "dtc", "dtd", "dte", "gmb",
191 "gme", "i2cp", "pta", "slxc", "slxd",
192 "spdi", "spdo", "uda";
193 nvidia,pull = <0>;
194 nvidia,tristate = <1>;
195 };
196 conf_atb {
197 nvidia,pins = "atb", "cdev1", "cdev2", "dap1",
198 "gma", "gmc", "gmd", "gpu", "gpu7",
199 "gpv", "sdio1", "slxa", "slxk", "uac";
200 nvidia,pull = <0>;
201 nvidia,tristate = <0>;
202 };
203 conf_ck32 {
204 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
205 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
206 nvidia,pull = <0>;
207 };
208 conf_csus {
209 nvidia,pins = "csus", "spia", "spib",
210 "spid", "spif";
211 nvidia,pull = <1>;
212 nvidia,tristate = <1>;
213 };
214 conf_ddc {
215 nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd";
216 nvidia,pull = <2>;
217 nvidia,tristate = <0>;
218 };
219 conf_hdint {
220 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
221 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
222 "lvp0", "pmc";
223 nvidia,tristate = <1>;
224 };
225 conf_irrx {
226 nvidia,pins = "irrx", "irtx", "kbca", "kbcb",
227 "kbcc", "kbcd", "kbce", "kbcf", "owc",
228 "spic", "spie", "spig", "spih", "uaa",
229 "uab", "uad", "uca", "ucb";
230 nvidia,pull = <2>;
231 nvidia,tristate = <1>;
232 };
233 conf_lc {
234 nvidia,pins = "lc", "ls";
235 nvidia,pull = <2>;
236 };
237 conf_ld0 {
238 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
239 "ld5", "ld6", "ld7", "ld8", "ld9",
240 "ld10", "ld11", "ld12", "ld13", "ld14",
241 "ld15", "ld16", "ld17", "ldi", "lhp0",
242 "lhp1", "lhp2", "lhs", "lm0", "lpp",
243 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
244 "lvs", "sdb";
245 nvidia,tristate = <0>;
246 };
247 conf_ld17_0 {
248 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
249 "ld23_22";
250 nvidia,pull = <1>;
251 };
252 };
253 };
254
255 i2s@70002800 {
256 status = "okay";
257 };
258
259 serial@70006000 {
260 status = "okay";
261 clock-frequency = <216000000>;
262 };
263
264 dvi_ddc: i2c@7000c000 {
265 status = "okay";
266 clock-frequency = <100000>;
267 };
268
269 spi@7000c380 {
270 status = "okay";
271 spi-max-frequency = <48000000>;
272 spi-flash@0 {
273 compatible = "winbond,w25q80bl";
274 reg = <0>;
275 spi-max-frequency = <48000000>;
276 };
277 };
278
279 hdmi_ddc: i2c@7000c400 {
280 status = "okay";
281 clock-frequency = <100000>;
282 };
283
284 i2c@7000c500 {
285 status = "okay";
286 clock-frequency = <400000>;
287
288 codec: codec@1a {
289 compatible = "ti,tlv320aic23";
290 reg = <0x1a>;
291 };
292
293 rtc@56 {
294 compatible = "emmicro,em3027";
295 reg = <0x56>;
296 };
297 };
298
299 usb@c5000000 {
300 status = "okay";
301 nvidia,vbus-gpio = <&gpio 170 0>; /* gpio PV2 */
302 };
303
304 usb@c5004000 {
305 status = "okay";
306 nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
307 };
308
309 usb@c5008000 {
310 status = "okay";
311 };
312
313 sdhci@c8000000 {
314 status = "okay";
315 bus-width = <4>;
316 };
317
318 sdhci@c8000600 {
319 status = "okay";
320 cd-gpios = <&gpio 121 0>; /* gpio PP1 */
321 wp-gpios = <&gpio 122 0>; /* gpio PP2 */
322 bus-width = <4>;
323 };
324
325 regulators {
326 compatible = "simple-bus";
327 #address-cells = <1>;
328 #size-cells = <0>;
329
330 hdmi_vdd_reg: regulator@0 {
331 compatible = "regulator-fixed";
332 reg = <0>;
333 regulator-name = "avdd_hdmi";
334 regulator-min-microvolt = <3300000>;
335 regulator-max-microvolt = <3300000>;
336 regulator-always-on;
337 };
338
339 hdmi_pll_reg: regulator@1 {
340 compatible = "regulator-fixed";
341 reg = <1>;
342 regulator-name = "avdd_hdmi_pll";
343 regulator-min-microvolt = <1800000>;
344 regulator-max-microvolt = <1800000>;
345 regulator-always-on;
346 };
347 };
348
349 sound {
350 compatible = "nvidia,tegra-audio-trimslice";
351 nvidia,i2s-controller = <&tegra_i2s1>;
352 nvidia,audio-codec = <&codec>;
353 };
354};
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
deleted file mode 100644
index adc47547eaa..00000000000
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ /dev/null
@@ -1,596 +0,0 @@
1/dts-v1/;
2
3/include/ "tegra20.dtsi"
4
5/ {
6 model = "NVIDIA Tegra2 Ventana evaluation board";
7 compatible = "nvidia,ventana", "nvidia,tegra20";
8
9 memory {
10 reg = <0x00000000 0x40000000>;
11 };
12
13 pinmux {
14 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>;
16
17 state_default: pinmux {
18 ata {
19 nvidia,pins = "ata";
20 nvidia,function = "ide";
21 };
22 atb {
23 nvidia,pins = "atb", "gma", "gme";
24 nvidia,function = "sdio4";
25 };
26 atc {
27 nvidia,pins = "atc";
28 nvidia,function = "nand";
29 };
30 atd {
31 nvidia,pins = "atd", "ate", "gmb", "spia",
32 "spib", "spic";
33 nvidia,function = "gmi";
34 };
35 cdev1 {
36 nvidia,pins = "cdev1";
37 nvidia,function = "plla_out";
38 };
39 cdev2 {
40 nvidia,pins = "cdev2";
41 nvidia,function = "pllp_out4";
42 };
43 crtp {
44 nvidia,pins = "crtp", "lm1";
45 nvidia,function = "crt";
46 };
47 csus {
48 nvidia,pins = "csus";
49 nvidia,function = "vi_sensor_clk";
50 };
51 dap1 {
52 nvidia,pins = "dap1";
53 nvidia,function = "dap1";
54 };
55 dap2 {
56 nvidia,pins = "dap2";
57 nvidia,function = "dap2";
58 };
59 dap3 {
60 nvidia,pins = "dap3";
61 nvidia,function = "dap3";
62 };
63 dap4 {
64 nvidia,pins = "dap4";
65 nvidia,function = "dap4";
66 };
67 dta {
68 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
69 nvidia,function = "vi";
70 };
71 dtf {
72 nvidia,pins = "dtf";
73 nvidia,function = "i2c3";
74 };
75 gmc {
76 nvidia,pins = "gmc";
77 nvidia,function = "uartd";
78 };
79 gmd {
80 nvidia,pins = "gmd";
81 nvidia,function = "sflash";
82 };
83 gpu {
84 nvidia,pins = "gpu";
85 nvidia,function = "pwm";
86 };
87 gpu7 {
88 nvidia,pins = "gpu7";
89 nvidia,function = "rtck";
90 };
91 gpv {
92 nvidia,pins = "gpv", "slxa", "slxk";
93 nvidia,function = "pcie";
94 };
95 hdint {
96 nvidia,pins = "hdint";
97 nvidia,function = "hdmi";
98 };
99 i2cp {
100 nvidia,pins = "i2cp";
101 nvidia,function = "i2cp";
102 };
103 irrx {
104 nvidia,pins = "irrx", "irtx";
105 nvidia,function = "uartb";
106 };
107 kbca {
108 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
109 "kbce", "kbcf";
110 nvidia,function = "kbc";
111 };
112 lcsn {
113 nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
114 "lsdi", "lvp0";
115 nvidia,function = "rsvd4";
116 };
117 ld0 {
118 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
119 "ld5", "ld6", "ld7", "ld8", "ld9",
120 "ld10", "ld11", "ld12", "ld13", "ld14",
121 "ld15", "ld16", "ld17", "ldi", "lhp0",
122 "lhp1", "lhp2", "lhs", "lpp", "lpw0",
123 "lpw2", "lsc0", "lsc1", "lsck", "lsda",
124 "lspi", "lvp1", "lvs";
125 nvidia,function = "displaya";
126 };
127 owc {
128 nvidia,pins = "owc", "spdi", "spdo", "uac";
129 nvidia,function = "rsvd2";
130 };
131 pmc {
132 nvidia,pins = "pmc";
133 nvidia,function = "pwr_on";
134 };
135 rm {
136 nvidia,pins = "rm";
137 nvidia,function = "i2c1";
138 };
139 sdb {
140 nvidia,pins = "sdb", "sdc", "sdd", "slxc";
141 nvidia,function = "sdio3";
142 };
143 sdio1 {
144 nvidia,pins = "sdio1";
145 nvidia,function = "sdio1";
146 };
147 slxd {
148 nvidia,pins = "slxd";
149 nvidia,function = "spdif";
150 };
151 spid {
152 nvidia,pins = "spid", "spie", "spif";
153 nvidia,function = "spi1";
154 };
155 spig {
156 nvidia,pins = "spig", "spih";
157 nvidia,function = "spi2_alt";
158 };
159 uaa {
160 nvidia,pins = "uaa", "uab", "uda";
161 nvidia,function = "ulpi";
162 };
163 uad {
164 nvidia,pins = "uad";
165 nvidia,function = "irda";
166 };
167 uca {
168 nvidia,pins = "uca", "ucb";
169 nvidia,function = "uartc";
170 };
171 conf_ata {
172 nvidia,pins = "ata", "atb", "atc", "atd",
173 "cdev1", "cdev2", "dap1", "dap2",
174 "dap4", "ddc", "dtf", "gma", "gmc",
175 "gme", "gpu", "gpu7", "i2cp", "irrx",
176 "irtx", "pta", "rm", "sdc", "sdd",
177 "slxc", "slxd", "slxk", "spdi", "spdo",
178 "uac", "uad", "uca", "ucb", "uda";
179 nvidia,pull = <0>;
180 nvidia,tristate = <0>;
181 };
182 conf_ate {
183 nvidia,pins = "ate", "csus", "dap3", "gmd",
184 "gpv", "owc", "spia", "spib", "spic",
185 "spid", "spie", "spig";
186 nvidia,pull = <0>;
187 nvidia,tristate = <1>;
188 };
189 conf_ck32 {
190 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
191 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
192 nvidia,pull = <0>;
193 };
194 conf_crtp {
195 nvidia,pins = "crtp", "gmb", "slxa", "spih";
196 nvidia,pull = <2>;
197 nvidia,tristate = <1>;
198 };
199 conf_dta {
200 nvidia,pins = "dta", "dtb", "dtc", "dtd";
201 nvidia,pull = <1>;
202 nvidia,tristate = <0>;
203 };
204 conf_dte {
205 nvidia,pins = "dte", "spif";
206 nvidia,pull = <1>;
207 nvidia,tristate = <1>;
208 };
209 conf_hdint {
210 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
211 "lpw1", "lsck", "lsda", "lsdi", "lvp0";
212 nvidia,tristate = <1>;
213 };
214 conf_kbca {
215 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
216 "kbce", "kbcf", "sdio1", "uaa", "uab";
217 nvidia,pull = <2>;
218 nvidia,tristate = <0>;
219 };
220 conf_lc {
221 nvidia,pins = "lc", "ls";
222 nvidia,pull = <2>;
223 };
224 conf_ld0 {
225 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
226 "ld5", "ld6", "ld7", "ld8", "ld9",
227 "ld10", "ld11", "ld12", "ld13", "ld14",
228 "ld15", "ld16", "ld17", "ldi", "lhp0",
229 "lhp1", "lhp2", "lhs", "lm0", "lpp",
230 "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
231 "lvp1", "lvs", "pmc", "sdb";
232 nvidia,tristate = <0>;
233 };
234 conf_ld17_0 {
235 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
236 "ld23_22";
237 nvidia,pull = <1>;
238 };
239 drive_sdio1 {
240 nvidia,pins = "drive_sdio1";
241 nvidia,high-speed-mode = <0>;
242 nvidia,schmitt = <1>;
243 nvidia,low-power-mode = <3>;
244 nvidia,pull-down-strength = <31>;
245 nvidia,pull-up-strength = <31>;
246 nvidia,slew-rate-rising = <3>;
247 nvidia,slew-rate-falling = <3>;
248 };
249 };
250
251 state_i2cmux_ddc: pinmux_i2cmux_ddc {
252 ddc {
253 nvidia,pins = "ddc";
254 nvidia,function = "i2c2";
255 };
256 pta {
257 nvidia,pins = "pta";
258 nvidia,function = "rsvd4";
259 };
260 };
261
262 state_i2cmux_pta: pinmux_i2cmux_pta {
263 ddc {
264 nvidia,pins = "ddc";
265 nvidia,function = "rsvd4";
266 };
267 pta {
268 nvidia,pins = "pta";
269 nvidia,function = "i2c2";
270 };
271 };
272
273 state_i2cmux_idle: pinmux_i2cmux_idle {
274 ddc {
275 nvidia,pins = "ddc";
276 nvidia,function = "rsvd4";
277 };
278 pta {
279 nvidia,pins = "pta";
280 nvidia,function = "rsvd4";
281 };
282 };
283 };
284
285 i2s@70002800 {
286 status = "okay";
287 };
288
289 serial@70006300 {
290 status = "okay";
291 clock-frequency = <216000000>;
292 };
293
294 i2c@7000c000 {
295 status = "okay";
296 clock-frequency = <400000>;
297
298 wm8903: wm8903@1a {
299 compatible = "wlf,wm8903";
300 reg = <0x1a>;
301 interrupt-parent = <&gpio>;
302 interrupts = <187 0x04>;
303
304 gpio-controller;
305 #gpio-cells = <2>;
306
307 micdet-cfg = <0>;
308 micdet-delay = <100>;
309 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
310 };
311
312 /* ALS and proximity sensor */
313 isl29018@44 {
314 compatible = "isil,isl29018";
315 reg = <0x44>;
316 interrupt-parent = <&gpio>;
317 interrupts = <202 0x04>; /*gpio PZ2 */
318 };
319 };
320
321 i2c@7000c400 {
322 status = "okay";
323 clock-frequency = <400000>;
324 };
325
326 i2cmux {
327 compatible = "i2c-mux-pinctrl";
328 #address-cells = <1>;
329 #size-cells = <0>;
330
331 i2c-parent = <&{/i2c@7000c400}>;
332
333 pinctrl-names = "ddc", "pta", "idle";
334 pinctrl-0 = <&state_i2cmux_ddc>;
335 pinctrl-1 = <&state_i2cmux_pta>;
336 pinctrl-2 = <&state_i2cmux_idle>;
337
338 i2c@0 {
339 reg = <0>;
340 #address-cells = <1>;
341 #size-cells = <0>;
342 };
343
344 i2c@1 {
345 reg = <1>;
346 #address-cells = <1>;
347 #size-cells = <0>;
348 };
349 };
350
351 i2c@7000c500 {
352 status = "okay";
353 clock-frequency = <400000>;
354 };
355
356 i2c@7000d000 {
357 status = "okay";
358 clock-frequency = <400000>;
359
360 pmic: tps6586x@34 {
361 compatible = "ti,tps6586x";
362 reg = <0x34>;
363 interrupts = <0 86 0x4>;
364
365 ti,system-power-controller;
366
367 #gpio-cells = <2>;
368 gpio-controller;
369
370 sys-supply = <&vdd_5v0_reg>;
371 vin-sm0-supply = <&sys_reg>;
372 vin-sm1-supply = <&sys_reg>;
373 vin-sm2-supply = <&sys_reg>;
374 vinldo01-supply = <&sm2_reg>;
375 vinldo23-supply = <&sm2_reg>;
376 vinldo4-supply = <&sm2_reg>;
377 vinldo678-supply = <&sm2_reg>;
378 vinldo9-supply = <&sm2_reg>;
379
380 regulators {
381 sys_reg: sys {
382 regulator-name = "vdd_sys";
383 regulator-always-on;
384 };
385
386 sm0 {
387 regulator-name = "vdd_sm0,vdd_core";
388 regulator-min-microvolt = <1200000>;
389 regulator-max-microvolt = <1200000>;
390 regulator-always-on;
391 };
392
393 sm1 {
394 regulator-name = "vdd_sm1,vdd_cpu";
395 regulator-min-microvolt = <1000000>;
396 regulator-max-microvolt = <1000000>;
397 regulator-always-on;
398 };
399
400 sm2_reg: sm2 {
401 regulator-name = "vdd_sm2,vin_ldo*";
402 regulator-min-microvolt = <3700000>;
403 regulator-max-microvolt = <3700000>;
404 regulator-always-on;
405 };
406
407 /* LDO0 is not connected to anything */
408
409 ldo1 {
410 regulator-name = "vdd_ldo1,avdd_pll*";
411 regulator-min-microvolt = <1100000>;
412 regulator-max-microvolt = <1100000>;
413 regulator-always-on;
414 };
415
416 ldo2 {
417 regulator-name = "vdd_ldo2,vdd_rtc";
418 regulator-min-microvolt = <1200000>;
419 regulator-max-microvolt = <1200000>;
420 };
421
422 ldo3 {
423 regulator-name = "vdd_ldo3,avdd_usb*";
424 regulator-min-microvolt = <3300000>;
425 regulator-max-microvolt = <3300000>;
426 regulator-always-on;
427 };
428
429 ldo4 {
430 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
431 regulator-min-microvolt = <1800000>;
432 regulator-max-microvolt = <1800000>;
433 regulator-always-on;
434 };
435
436 ldo5 {
437 regulator-name = "vdd_ldo5,vcore_mmc";
438 regulator-min-microvolt = <2850000>;
439 regulator-max-microvolt = <2850000>;
440 regulator-always-on;
441 };
442
443 ldo6 {
444 regulator-name = "vdd_ldo6,avdd_vdac";
445 regulator-min-microvolt = <1800000>;
446 regulator-max-microvolt = <1800000>;
447 };
448
449 ldo7 {
450 regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
451 regulator-min-microvolt = <3300000>;
452 regulator-max-microvolt = <3300000>;
453 };
454
455 ldo8 {
456 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
457 regulator-min-microvolt = <1800000>;
458 regulator-max-microvolt = <1800000>;
459 };
460
461 ldo9 {
462 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
463 regulator-min-microvolt = <2850000>;
464 regulator-max-microvolt = <2850000>;
465 regulator-always-on;
466 };
467
468 ldo_rtc {
469 regulator-name = "vdd_rtc_out,vdd_cell";
470 regulator-min-microvolt = <3300000>;
471 regulator-max-microvolt = <3300000>;
472 regulator-always-on;
473 };
474 };
475 };
476
477 temperature-sensor@4c {
478 compatible = "onnn,nct1008";
479 reg = <0x4c>;
480 };
481 };
482
483 pmc {
484 nvidia,invert-interrupt;
485 };
486
487 usb@c5000000 {
488 status = "okay";
489 };
490
491 usb@c5004000 {
492 status = "okay";
493 nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
494 };
495
496 usb@c5008000 {
497 status = "okay";
498 };
499
500 sdhci@c8000000 {
501 status = "okay";
502 power-gpios = <&gpio 86 0>; /* gpio PK6 */
503 bus-width = <4>;
504 };
505
506 sdhci@c8000400 {
507 status = "okay";
508 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
509 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
510 power-gpios = <&gpio 70 0>; /* gpio PI6 */
511 bus-width = <4>;
512 };
513
514 sdhci@c8000600 {
515 status = "okay";
516 bus-width = <8>;
517 };
518
519 regulators {
520 compatible = "simple-bus";
521 #address-cells = <1>;
522 #size-cells = <0>;
523
524 vdd_5v0_reg: regulator@0 {
525 compatible = "regulator-fixed";
526 reg = <0>;
527 regulator-name = "vdd_5v0";
528 regulator-min-microvolt = <5000000>;
529 regulator-max-microvolt = <5000000>;
530 regulator-always-on;
531 };
532
533 regulator@1 {
534 compatible = "regulator-fixed";
535 reg = <1>;
536 regulator-name = "vdd_1v5";
537 regulator-min-microvolt = <1500000>;
538 regulator-max-microvolt = <1500000>;
539 gpio = <&pmic 0 0>;
540 };
541
542 regulator@2 {
543 compatible = "regulator-fixed";
544 reg = <2>;
545 regulator-name = "vdd_1v2";
546 regulator-min-microvolt = <1200000>;
547 regulator-max-microvolt = <1200000>;
548 gpio = <&pmic 1 0>;
549 enable-active-high;
550 };
551
552 regulator@3 {
553 compatible = "regulator-fixed";
554 reg = <3>;
555 regulator-name = "vdd_pnl";
556 regulator-min-microvolt = <2800000>;
557 regulator-max-microvolt = <2800000>;
558 gpio = <&gpio 22 0>; /* gpio PC6 */
559 enable-active-high;
560 };
561
562 regulator@4 {
563 compatible = "regulator-fixed";
564 reg = <4>;
565 regulator-name = "vdd_bl";
566 regulator-min-microvolt = <2800000>;
567 regulator-max-microvolt = <2800000>;
568 gpio = <&gpio 176 0>; /* gpio PW0 */
569 enable-active-high;
570 };
571 };
572
573 sound {
574 compatible = "nvidia,tegra-audio-wm8903-ventana",
575 "nvidia,tegra-audio-wm8903";
576 nvidia,model = "NVIDIA Tegra Ventana";
577
578 nvidia,audio-routing =
579 "Headphone Jack", "HPOUTR",
580 "Headphone Jack", "HPOUTL",
581 "Int Spk", "ROP",
582 "Int Spk", "RON",
583 "Int Spk", "LOP",
584 "Int Spk", "LON",
585 "Mic Jack", "MICBIAS",
586 "IN1L", "Mic Jack";
587
588 nvidia,i2s-controller = <&tegra_i2s1>;
589 nvidia,audio-codec = <&wm8903>;
590
591 nvidia,spkr-en-gpios = <&wm8903 2 0>;
592 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
593 nvidia,int-mic-en-gpios = <&gpio 184 0>; /* gpio PX0 */
594 nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
595 };
596};
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
deleted file mode 100644
index 20d576ecd55..00000000000
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ /dev/null
@@ -1,552 +0,0 @@
1/dts-v1/;
2
3/include/ "tegra20.dtsi"
4
5/ {
6 model = "NVIDIA Tegra2 Whistler evaluation board";
7 compatible = "nvidia,whistler", "nvidia,tegra20";
8
9 memory {
10 reg = <0x00000000 0x20000000>;
11 };
12
13 host1x {
14 hdmi {
15 status = "okay";
16
17 vdd-supply = <&hdmi_vdd_reg>;
18 pll-supply = <&hdmi_pll_reg>;
19
20 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
21 nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
22 };
23 };
24
25 pinmux {
26 pinctrl-names = "default";
27 pinctrl-0 = <&state_default>;
28
29 state_default: pinmux {
30 ata {
31 nvidia,pins = "ata", "atb", "ate", "gma", "gmb",
32 "gmc", "gmd", "gpu";
33 nvidia,function = "gmi";
34 };
35 atc {
36 nvidia,pins = "atc", "atd";
37 nvidia,function = "sdio4";
38 };
39 cdev1 {
40 nvidia,pins = "cdev1";
41 nvidia,function = "plla_out";
42 };
43 cdev2 {
44 nvidia,pins = "cdev2";
45 nvidia,function = "osc";
46 };
47 crtp {
48 nvidia,pins = "crtp";
49 nvidia,function = "crt";
50 };
51 csus {
52 nvidia,pins = "csus";
53 nvidia,function = "vi_sensor_clk";
54 };
55 dap1 {
56 nvidia,pins = "dap1";
57 nvidia,function = "dap1";
58 };
59 dap2 {
60 nvidia,pins = "dap2";
61 nvidia,function = "dap2";
62 };
63 dap3 {
64 nvidia,pins = "dap3";
65 nvidia,function = "dap3";
66 };
67 dap4 {
68 nvidia,pins = "dap4";
69 nvidia,function = "dap4";
70 };
71 ddc {
72 nvidia,pins = "ddc";
73 nvidia,function = "i2c2";
74 };
75 dta {
76 nvidia,pins = "dta", "dtb", "dtc", "dtd";
77 nvidia,function = "vi";
78 };
79 dte {
80 nvidia,pins = "dte";
81 nvidia,function = "rsvd1";
82 };
83 dtf {
84 nvidia,pins = "dtf";
85 nvidia,function = "i2c3";
86 };
87 gme {
88 nvidia,pins = "gme";
89 nvidia,function = "dap5";
90 };
91 gpu7 {
92 nvidia,pins = "gpu7";
93 nvidia,function = "rtck";
94 };
95 gpv {
96 nvidia,pins = "gpv";
97 nvidia,function = "pcie";
98 };
99 hdint {
100 nvidia,pins = "hdint", "pta";
101 nvidia,function = "hdmi";
102 };
103 i2cp {
104 nvidia,pins = "i2cp";
105 nvidia,function = "i2cp";
106 };
107 irrx {
108 nvidia,pins = "irrx", "irtx";
109 nvidia,function = "uartb";
110 };
111 kbca {
112 nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
113 nvidia,function = "kbc";
114 };
115 kbcb {
116 nvidia,pins = "kbcb", "kbcd";
117 nvidia,function = "sdio2";
118 };
119 lcsn {
120 nvidia,pins = "lcsn", "lsck", "lsda", "lsdi",
121 "spia", "spib", "spic";
122 nvidia,function = "spi3";
123 };
124 ld0 {
125 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
126 "ld5", "ld6", "ld7", "ld8", "ld9",
127 "ld10", "ld11", "ld12", "ld13", "ld14",
128 "ld15", "ld16", "ld17", "ldc", "ldi",
129 "lhp0", "lhp1", "lhp2", "lhs", "lm0",
130 "lm1", "lpp", "lpw0", "lpw1", "lpw2",
131 "lsc0", "lsc1", "lspi", "lvp0", "lvp1",
132 "lvs";
133 nvidia,function = "displaya";
134 };
135 owc {
136 nvidia,pins = "owc", "uac";
137 nvidia,function = "owr";
138 };
139 pmc {
140 nvidia,pins = "pmc";
141 nvidia,function = "pwr_on";
142 };
143 rm {
144 nvidia,pins = "rm";
145 nvidia,function = "i2c1";
146 };
147 sdb {
148 nvidia,pins = "sdb", "sdc", "sdd", "slxa",
149 "slxc", "slxd", "slxk";
150 nvidia,function = "sdio3";
151 };
152 sdio1 {
153 nvidia,pins = "sdio1";
154 nvidia,function = "sdio1";
155 };
156 spdi {
157 nvidia,pins = "spdi", "spdo";
158 nvidia,function = "rsvd2";
159 };
160 spid {
161 nvidia,pins = "spid", "spie", "spig", "spih";
162 nvidia,function = "spi2_alt";
163 };
164 spif {
165 nvidia,pins = "spif";
166 nvidia,function = "spi2";
167 };
168 uaa {
169 nvidia,pins = "uaa", "uab";
170 nvidia,function = "uarta";
171 };
172 uad {
173 nvidia,pins = "uad";
174 nvidia,function = "irda";
175 };
176 uca {
177 nvidia,pins = "uca", "ucb";
178 nvidia,function = "uartc";
179 };
180 uda {
181 nvidia,pins = "uda";
182 nvidia,function = "spi1";
183 };
184 conf_ata {
185 nvidia,pins = "ata", "atb", "atc", "ddc", "gma",
186 "gmb", "gmc", "gmd", "irrx", "irtx",
187 "kbca", "kbcb", "kbcc", "kbcd", "kbce",
188 "kbcf", "sdc", "sdd", "spie", "spig",
189 "spih", "uaa", "uab", "uad", "uca",
190 "ucb";
191 nvidia,pull = <2>;
192 nvidia,tristate = <0>;
193 };
194 conf_atd {
195 nvidia,pins = "atd", "ate", "cdev1", "csus",
196 "dap1", "dap2", "dap3", "dap4", "dte",
197 "dtf", "gpu", "gpu7", "gpv", "i2cp",
198 "rm", "sdio1", "slxa", "slxc", "slxd",
199 "slxk", "spdi", "spdo", "uac", "uda";
200 nvidia,pull = <0>;
201 nvidia,tristate = <0>;
202 };
203 conf_cdev2 {
204 nvidia,pins = "cdev2", "spia", "spib";
205 nvidia,pull = <1>;
206 nvidia,tristate = <1>;
207 };
208 conf_ck32 {
209 nvidia,pins = "ck32", "ddrc", "lc", "pmca",
210 "pmcb", "pmcc", "pmcd", "xm2c",
211 "xm2d";
212 nvidia,pull = <0>;
213 };
214 conf_crtp {
215 nvidia,pins = "crtp";
216 nvidia,pull = <0>;
217 nvidia,tristate = <1>;
218 };
219 conf_dta {
220 nvidia,pins = "dta", "dtb", "dtc", "dtd",
221 "spid", "spif";
222 nvidia,pull = <1>;
223 nvidia,tristate = <0>;
224 };
225 conf_gme {
226 nvidia,pins = "gme", "owc", "pta", "spic";
227 nvidia,pull = <2>;
228 nvidia,tristate = <1>;
229 };
230 conf_ld17_0 {
231 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
232 "ld23_22";
233 nvidia,pull = <1>;
234 };
235 conf_ls {
236 nvidia,pins = "ls", "pmce";
237 nvidia,pull = <2>;
238 };
239 drive_dap1 {
240 nvidia,pins = "drive_dap1";
241 nvidia,high-speed-mode = <0>;
242 nvidia,schmitt = <1>;
243 nvidia,low-power-mode = <0>;
244 nvidia,pull-down-strength = <0>;
245 nvidia,pull-up-strength = <0>;
246 nvidia,slew-rate-rising = <0>;
247 nvidia,slew-rate-falling = <0>;
248 };
249 };
250 };
251
252 i2s@70002800 {
253 status = "okay";
254 };
255
256 serial@70006000 {
257 status = "okay";
258 clock-frequency = <216000000>;
259 };
260
261 hdmi_ddc: i2c@7000c400 {
262 status = "okay";
263 clock-frequency = <100000>;
264 };
265
266 i2c@7000d000 {
267 status = "okay";
268 clock-frequency = <100000>;
269
270 codec: codec@1a {
271 compatible = "wlf,wm8753";
272 reg = <0x1a>;
273 };
274
275 tca6416: gpio@20 {
276 compatible = "ti,tca6416";
277 reg = <0x20>;
278 gpio-controller;
279 #gpio-cells = <2>;
280 };
281
282 max8907@3c {
283 compatible = "maxim,max8907";
284 reg = <0x3c>;
285 interrupts = <0 86 0x4>;
286
287 maxim,system-power-controller;
288
289 mbatt-supply = <&usb0_vbus_reg>;
290 in-v1-supply = <&mbatt_reg>;
291 in-v2-supply = <&mbatt_reg>;
292 in-v3-supply = <&mbatt_reg>;
293 in1-supply = <&mbatt_reg>;
294 in2-supply = <&nvvdd_sv3_reg>;
295 in3-supply = <&mbatt_reg>;
296 in4-supply = <&mbatt_reg>;
297 in5-supply = <&mbatt_reg>;
298 in6-supply = <&mbatt_reg>;
299 in7-supply = <&mbatt_reg>;
300 in8-supply = <&mbatt_reg>;
301 in9-supply = <&mbatt_reg>;
302 in10-supply = <&mbatt_reg>;
303 in11-supply = <&mbatt_reg>;
304 in12-supply = <&mbatt_reg>;
305 in13-supply = <&mbatt_reg>;
306 in14-supply = <&mbatt_reg>;
307 in15-supply = <&mbatt_reg>;
308 in16-supply = <&mbatt_reg>;
309 in17-supply = <&nvvdd_sv3_reg>;
310 in18-supply = <&nvvdd_sv3_reg>;
311 in19-supply = <&mbatt_reg>;
312 in20-supply = <&mbatt_reg>;
313
314 regulators {
315 mbatt_reg: mbatt {
316 regulator-name = "vbat_pmu";
317 regulator-always-on;
318 };
319
320 sd1 {
321 regulator-name = "nvvdd_sv1,vdd_cpu_pmu";
322 regulator-min-microvolt = <1000000>;
323 regulator-max-microvolt = <1000000>;
324 regulator-always-on;
325 };
326
327 sd2 {
328 regulator-name = "nvvdd_sv2,vdd_core";
329 regulator-min-microvolt = <1200000>;
330 regulator-max-microvolt = <1200000>;
331 regulator-always-on;
332 };
333
334 nvvdd_sv3_reg: sd3 {
335 regulator-name = "nvvdd_sv3";
336 regulator-min-microvolt = <1800000>;
337 regulator-max-microvolt = <1800000>;
338 regulator-always-on;
339 };
340
341 ldo1 {
342 regulator-name = "nvvdd_ldo1,vddio_rx_ddr,vcore_acc";
343 regulator-min-microvolt = <3300000>;
344 regulator-max-microvolt = <3300000>;
345 regulator-always-on;
346 };
347
348 ldo2 {
349 regulator-name = "nvvdd_ldo2,avdd_pll*";
350 regulator-min-microvolt = <1100000>;
351 regulator-max-microvolt = <1100000>;
352 regulator-always-on;
353 };
354
355 ldo3 {
356 regulator-name = "nvvdd_ldo3,vcom_1v8b";
357 regulator-min-microvolt = <1800000>;
358 regulator-max-microvolt = <1800000>;
359 regulator-always-on;
360 };
361
362 ldo4 {
363 regulator-name = "nvvdd_ldo4,avdd_usb*";
364 regulator-min-microvolt = <3300000>;
365 regulator-max-microvolt = <3300000>;
366 regulator-always-on;
367 };
368
369 ldo5 {
370 regulator-name = "nvvdd_ldo5,vcore_mmc,avdd_lcd1,vddio_1wire";
371 regulator-min-microvolt = <2800000>;
372 regulator-max-microvolt = <2800000>;
373 regulator-always-on;
374 };
375
376 hdmi_pll_reg: ldo6 {
377 regulator-name = "nvvdd_ldo6,avdd_hdmi_pll";
378 regulator-min-microvolt = <1800000>;
379 regulator-max-microvolt = <1800000>;
380 };
381
382 ldo7 {
383 regulator-name = "nvvdd_ldo7,avddio_audio";
384 regulator-min-microvolt = <2800000>;
385 regulator-max-microvolt = <2800000>;
386 regulator-always-on;
387 };
388
389 ldo8 {
390 regulator-name = "nvvdd_ldo8,vcom_3v0,vcore_cmps";
391 regulator-min-microvolt = <3000000>;
392 regulator-max-microvolt = <3000000>;
393 };
394
395 ldo9 {
396 regulator-name = "nvvdd_ldo9,avdd_cam*";
397 regulator-min-microvolt = <2800000>;
398 regulator-max-microvolt = <2800000>;
399 };
400
401 ldo10 {
402 regulator-name = "nvvdd_ldo10,avdd_usb_ic_3v0";
403 regulator-min-microvolt = <3000000>;
404 regulator-max-microvolt = <3000000>;
405 regulator-always-on;
406 };
407
408 hdmi_vdd_reg: ldo11 {
409 regulator-name = "nvvdd_ldo11,vddio_pex_clk,vcom_33,avdd_hdmi";
410 regulator-min-microvolt = <3300000>;
411 regulator-max-microvolt = <3300000>;
412 };
413
414 ldo12 {
415 regulator-name = "nvvdd_ldo12,vddio_sdio";
416 regulator-min-microvolt = <2800000>;
417 regulator-max-microvolt = <2800000>;
418 regulator-always-on;
419 };
420
421 ldo13 {
422 regulator-name = "nvvdd_ldo13,vcore_phtn,vdd_af";
423 regulator-min-microvolt = <2800000>;
424 regulator-max-microvolt = <2800000>;
425 };
426
427 ldo14 {
428 regulator-name = "nvvdd_ldo14,avdd_vdac";
429 regulator-min-microvolt = <2800000>;
430 regulator-max-microvolt = <2800000>;
431 };
432
433 ldo15 {
434 regulator-name = "nvvdd_ldo15,vcore_temp,vddio_hdcp";
435 regulator-min-microvolt = <3300000>;
436 regulator-max-microvolt = <3300000>;
437 };
438
439 ldo16 {
440 regulator-name = "nvvdd_ldo16,vdd_dbrtr";
441 regulator-min-microvolt = <1300000>;
442 regulator-max-microvolt = <1300000>;
443 };
444
445 ldo17 {
446 regulator-name = "nvvdd_ldo17,vddio_mipi";
447 regulator-min-microvolt = <1200000>;
448 regulator-max-microvolt = <1200000>;
449 };
450
451 ldo18 {
452 regulator-name = "nvvdd_ldo18,vddio_vi,vcore_cam*";
453 regulator-min-microvolt = <1800000>;
454 regulator-max-microvolt = <1800000>;
455 };
456
457 ldo19 {
458 regulator-name = "nvvdd_ldo19,avdd_lcd2,vddio_lx";
459 regulator-min-microvolt = <2800000>;
460 regulator-max-microvolt = <2800000>;
461 };
462
463 ldo20 {
464 regulator-name = "nvvdd_ldo20,vddio_ddr_1v2,vddio_hsic,vcom_1v2";
465 regulator-min-microvolt = <1200000>;
466 regulator-max-microvolt = <1200000>;
467 regulator-always-on;
468 };
469
470 out5v {
471 regulator-name = "usb0_vbus_reg";
472 };
473
474 out33v {
475 regulator-name = "pmu_out3v3";
476 };
477
478 bbat {
479 regulator-name = "pmu_bbat";
480 regulator-min-microvolt = <2400000>;
481 regulator-max-microvolt = <2400000>;
482 regulator-always-on;
483 };
484
485 sdby {
486 regulator-name = "vdd_aon";
487 regulator-always-on;
488 };
489
490 vrtc {
491 regulator-name = "vrtc,pmu_vccadc";
492 regulator-always-on;
493 };
494 };
495 };
496 };
497
498 pmc {
499 nvidia,invert-interrupt;
500 };
501
502 usb@c5000000 {
503 status = "okay";
504 nvidia,vbus-gpio = <&tca6416 0 0>; /* GPIO_PMU0 */
505 };
506
507 usb@c5008000 {
508 status = "okay";
509 nvidia,vbus-gpio = <&tca6416 1 0>; /* GPIO_PMU1 */
510 };
511
512 sdhci@c8000400 {
513 status = "okay";
514 wp-gpios = <&gpio 173 0>; /* gpio PV5 */
515 bus-width = <8>;
516 };
517
518 sdhci@c8000600 {
519 status = "okay";
520 bus-width = <8>;
521 };
522
523 regulators {
524 compatible = "simple-bus";
525 #address-cells = <1>;
526 #size-cells = <0>;
527
528 usb0_vbus_reg: regulator {
529 compatible = "regulator-fixed";
530 reg = <0>;
531 regulator-name = "usb0_vbus";
532 regulator-min-microvolt = <5000000>;
533 regulator-max-microvolt = <5000000>;
534 regulator-always-on;
535 };
536 };
537
538 sound {
539 compatible = "nvidia,tegra-audio-wm8753-whistler",
540 "nvidia,tegra-audio-wm8753";
541 nvidia,model = "NVIDIA Tegra Whistler";
542
543 nvidia,audio-routing =
544 "Headphone Jack", "LOUT1",
545 "Headphone Jack", "ROUT1",
546 "MIC2", "Mic Jack",
547 "MIC2N", "Mic Jack";
548
549 nvidia,i2s-controller = <&tegra_i2s1>;
550 nvidia,audio-codec = <&codec>;
551 };
552};
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index b8effa1cbda..5727595cde6 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -4,415 +4,136 @@
4 compatible = "nvidia,tegra20"; 4 compatible = "nvidia,tegra20";
5 interrupt-parent = <&intc>; 5 interrupt-parent = <&intc>;
6 6
7 host1x { 7 intc: interrupt-controller@50041000 {
8 compatible = "nvidia,tegra20-host1x", "simple-bus"; 8 compatible = "nvidia,tegra20-gic";
9 reg = <0x50000000 0x00024000>; 9 interrupt-controller;
10 interrupts = <0 65 0x04 /* mpcore syncpt */ 10 #interrupt-cells = <1>;
11 0 67 0x04>; /* mpcore general */ 11 reg = < 0x50041000 0x1000 >,
12 < 0x50040100 0x0100 >;
13 };
12 14
15 i2c@7000c000 {
13 #address-cells = <1>; 16 #address-cells = <1>;
14 #size-cells = <1>; 17 #size-cells = <0>;
15 18 compatible = "nvidia,tegra20-i2c";
16 ranges = <0x54000000 0x54000000 0x04000000>; 19 reg = <0x7000C000 0x100>;
17 20 interrupts = < 70 >;
18 mpe {
19 compatible = "nvidia,tegra20-mpe";
20 reg = <0x54040000 0x00040000>;
21 interrupts = <0 68 0x04>;
22 };
23
24 vi {
25 compatible = "nvidia,tegra20-vi";
26 reg = <0x54080000 0x00040000>;
27 interrupts = <0 69 0x04>;
28 };
29
30 epp {
31 compatible = "nvidia,tegra20-epp";
32 reg = <0x540c0000 0x00040000>;
33 interrupts = <0 70 0x04>;
34 };
35
36 isp {
37 compatible = "nvidia,tegra20-isp";
38 reg = <0x54100000 0x00040000>;
39 interrupts = <0 71 0x04>;
40 };
41
42 gr2d {
43 compatible = "nvidia,tegra20-gr2d";
44 reg = <0x54140000 0x00040000>;
45 interrupts = <0 72 0x04>;
46 };
47
48 gr3d {
49 compatible = "nvidia,tegra20-gr3d";
50 reg = <0x54180000 0x00040000>;
51 };
52
53 dc@54200000 {
54 compatible = "nvidia,tegra20-dc";
55 reg = <0x54200000 0x00040000>;
56 interrupts = <0 73 0x04>;
57
58 rgb {
59 status = "disabled";
60 };
61 };
62
63 dc@54240000 {
64 compatible = "nvidia,tegra20-dc";
65 reg = <0x54240000 0x00040000>;
66 interrupts = <0 74 0x04>;
67
68 rgb {
69 status = "disabled";
70 };
71 };
72
73 hdmi {
74 compatible = "nvidia,tegra20-hdmi";
75 reg = <0x54280000 0x00040000>;
76 interrupts = <0 75 0x04>;
77 status = "disabled";
78 };
79
80 tvo {
81 compatible = "nvidia,tegra20-tvo";
82 reg = <0x542c0000 0x00040000>;
83 interrupts = <0 76 0x04>;
84 status = "disabled";
85 };
86
87 dsi {
88 compatible = "nvidia,tegra20-dsi";
89 reg = <0x54300000 0x00040000>;
90 status = "disabled";
91 };
92 }; 21 };
93 22
94 timer@50004600 { 23 i2c@7000c400 {
95 compatible = "arm,cortex-a9-twd-timer"; 24 #address-cells = <1>;
96 reg = <0x50040600 0x20>; 25 #size-cells = <0>;
97 interrupts = <1 13 0x304>; 26 compatible = "nvidia,tegra20-i2c";
27 reg = <0x7000C400 0x100>;
28 interrupts = < 116 >;
98 }; 29 };
99 30
100 cache-controller@50043000 { 31 i2c@7000c500 {
101 compatible = "arm,pl310-cache"; 32 #address-cells = <1>;
102 reg = <0x50043000 0x1000>; 33 #size-cells = <0>;
103 arm,data-latency = <5 5 2>; 34 compatible = "nvidia,tegra20-i2c";
104 arm,tag-latency = <4 4 2>; 35 reg = <0x7000C500 0x100>;
105 cache-unified; 36 interrupts = < 124 >;
106 cache-level = <2>;
107 }; 37 };
108 38
109 intc: interrupt-controller { 39 i2c@7000d000 {
110 compatible = "arm,cortex-a9-gic"; 40 #address-cells = <1>;
111 reg = <0x50041000 0x1000 41 #size-cells = <0>;
112 0x50040100 0x0100>; 42 compatible = "nvidia,tegra20-i2c";
113 interrupt-controller; 43 reg = <0x7000D000 0x200>;
114 #interrupt-cells = <3>; 44 interrupts = < 85 >;
115 }; 45 };
116 46
117 timer@60005000 { 47 i2s@70002800 {
118 compatible = "nvidia,tegra20-timer"; 48 #address-cells = <1>;
119 reg = <0x60005000 0x60>; 49 #size-cells = <0>;
120 interrupts = <0 0 0x04 50 compatible = "nvidia,tegra20-i2s";
121 0 1 0x04 51 reg = <0x70002800 0x200>;
122 0 41 0x04 52 interrupts = < 45 >;
123 0 42 0x04>; 53 dma-channel = < 2 >;
124 }; 54 };
125 55
126 apbdma: dma { 56 i2s@70002a00 {
127 compatible = "nvidia,tegra20-apbdma"; 57 #address-cells = <1>;
128 reg = <0x6000a000 0x1200>; 58 #size-cells = <0>;
129 interrupts = <0 104 0x04 59 compatible = "nvidia,tegra20-i2s";
130 0 105 0x04 60 reg = <0x70002a00 0x200>;
131 0 106 0x04 61 interrupts = < 35 >;
132 0 107 0x04 62 dma-channel = < 1 >;
133 0 108 0x04
134 0 109 0x04
135 0 110 0x04
136 0 111 0x04
137 0 112 0x04
138 0 113 0x04
139 0 114 0x04
140 0 115 0x04
141 0 116 0x04
142 0 117 0x04
143 0 118 0x04
144 0 119 0x04>;
145 }; 63 };
146 64
147 ahb { 65 das@70000c00 {
148 compatible = "nvidia,tegra20-ahb"; 66 #address-cells = <1>;
149 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */ 67 #size-cells = <0>;
68 compatible = "nvidia,tegra20-das";
69 reg = <0x70000c00 0x80>;
150 }; 70 };
151 71
152 gpio: gpio { 72 gpio: gpio@6000d000 {
153 compatible = "nvidia,tegra20-gpio"; 73 compatible = "nvidia,tegra20-gpio";
154 reg = <0x6000d000 0x1000>; 74 reg = < 0x6000d000 0x1000 >;
155 interrupts = <0 32 0x04 75 interrupts = < 64 65 66 67 87 119 121 >;
156 0 33 0x04
157 0 34 0x04
158 0 35 0x04
159 0 55 0x04
160 0 87 0x04
161 0 89 0x04>;
162 #gpio-cells = <2>; 76 #gpio-cells = <2>;
163 gpio-controller; 77 gpio-controller;
164 #interrupt-cells = <2>;
165 interrupt-controller;
166 };
167
168 pinmux: pinmux {
169 compatible = "nvidia,tegra20-pinmux";
170 reg = <0x70000014 0x10 /* Tri-state registers */
171 0x70000080 0x20 /* Mux registers */
172 0x700000a0 0x14 /* Pull-up/down registers */
173 0x70000868 0xa8>; /* Pad control registers */
174 };
175
176 das {
177 compatible = "nvidia,tegra20-das";
178 reg = <0x70000c00 0x80>;
179 };
180
181 tegra_i2s1: i2s@70002800 {
182 compatible = "nvidia,tegra20-i2s";
183 reg = <0x70002800 0x200>;
184 interrupts = <0 13 0x04>;
185 nvidia,dma-request-selector = <&apbdma 2>;
186 status = "disabled";
187 };
188
189 tegra_i2s2: i2s@70002a00 {
190 compatible = "nvidia,tegra20-i2s";
191 reg = <0x70002a00 0x200>;
192 interrupts = <0 3 0x04>;
193 nvidia,dma-request-selector = <&apbdma 1>;
194 status = "disabled";
195 }; 78 };
196 79
197 serial@70006000 { 80 serial@70006000 {
198 compatible = "nvidia,tegra20-uart"; 81 compatible = "nvidia,tegra20-uart";
199 reg = <0x70006000 0x40>; 82 reg = <0x70006000 0x40>;
200 reg-shift = <2>; 83 reg-shift = <2>;
201 interrupts = <0 36 0x04>; 84 interrupts = < 68 >;
202 status = "disabled";
203 }; 85 };
204 86
205 serial@70006040 { 87 serial@70006040 {
206 compatible = "nvidia,tegra20-uart"; 88 compatible = "nvidia,tegra20-uart";
207 reg = <0x70006040 0x40>; 89 reg = <0x70006040 0x40>;
208 reg-shift = <2>; 90 reg-shift = <2>;
209 interrupts = <0 37 0x04>; 91 interrupts = < 69 >;
210 status = "disabled";
211 }; 92 };
212 93
213 serial@70006200 { 94 serial@70006200 {
214 compatible = "nvidia,tegra20-uart"; 95 compatible = "nvidia,tegra20-uart";
215 reg = <0x70006200 0x100>; 96 reg = <0x70006200 0x100>;
216 reg-shift = <2>; 97 reg-shift = <2>;
217 interrupts = <0 46 0x04>; 98 interrupts = < 78 >;
218 status = "disabled";
219 }; 99 };
220 100
221 serial@70006300 { 101 serial@70006300 {
222 compatible = "nvidia,tegra20-uart"; 102 compatible = "nvidia,tegra20-uart";
223 reg = <0x70006300 0x100>; 103 reg = <0x70006300 0x100>;
224 reg-shift = <2>; 104 reg-shift = <2>;
225 interrupts = <0 90 0x04>; 105 interrupts = < 122 >;
226 status = "disabled";
227 }; 106 };
228 107
229 serial@70006400 { 108 serial@70006400 {
230 compatible = "nvidia,tegra20-uart"; 109 compatible = "nvidia,tegra20-uart";
231 reg = <0x70006400 0x100>; 110 reg = <0x70006400 0x100>;
232 reg-shift = <2>; 111 reg-shift = <2>;
233 interrupts = <0 91 0x04>; 112 interrupts = < 123 >;
234 status = "disabled";
235 };
236
237 pwm: pwm {
238 compatible = "nvidia,tegra20-pwm";
239 reg = <0x7000a000 0x100>;
240 #pwm-cells = <2>;
241 };
242
243 rtc {
244 compatible = "nvidia,tegra20-rtc";
245 reg = <0x7000e000 0x100>;
246 interrupts = <0 2 0x04>;
247 };
248
249 i2c@7000c000 {
250 compatible = "nvidia,tegra20-i2c";
251 reg = <0x7000c000 0x100>;
252 interrupts = <0 38 0x04>;
253 #address-cells = <1>;
254 #size-cells = <0>;
255 status = "disabled";
256 };
257
258 spi@7000c380 {
259 compatible = "nvidia,tegra20-sflash";
260 reg = <0x7000c380 0x80>;
261 interrupts = <0 39 0x04>;
262 nvidia,dma-request-selector = <&apbdma 11>;
263 #address-cells = <1>;
264 #size-cells = <0>;
265 status = "disabled";
266 };
267
268 i2c@7000c400 {
269 compatible = "nvidia,tegra20-i2c";
270 reg = <0x7000c400 0x100>;
271 interrupts = <0 84 0x04>;
272 #address-cells = <1>;
273 #size-cells = <0>;
274 status = "disabled";
275 };
276
277 i2c@7000c500 {
278 compatible = "nvidia,tegra20-i2c";
279 reg = <0x7000c500 0x100>;
280 interrupts = <0 92 0x04>;
281 #address-cells = <1>;
282 #size-cells = <0>;
283 status = "disabled";
284 };
285
286 i2c@7000d000 {
287 compatible = "nvidia,tegra20-i2c-dvc";
288 reg = <0x7000d000 0x200>;
289 interrupts = <0 53 0x04>;
290 #address-cells = <1>;
291 #size-cells = <0>;
292 status = "disabled";
293 };
294
295 spi@7000d400 {
296 compatible = "nvidia,tegra20-slink";
297 reg = <0x7000d400 0x200>;
298 interrupts = <0 59 0x04>;
299 nvidia,dma-request-selector = <&apbdma 15>;
300 #address-cells = <1>;
301 #size-cells = <0>;
302 status = "disabled";
303 };
304
305 spi@7000d600 {
306 compatible = "nvidia,tegra20-slink";
307 reg = <0x7000d600 0x200>;
308 interrupts = <0 82 0x04>;
309 nvidia,dma-request-selector = <&apbdma 16>;
310 #address-cells = <1>;
311 #size-cells = <0>;
312 status = "disabled";
313 };
314
315 spi@7000d800 {
316 compatible = "nvidia,tegra20-slink";
317 reg = <0x7000d480 0x200>;
318 interrupts = <0 83 0x04>;
319 nvidia,dma-request-selector = <&apbdma 17>;
320 #address-cells = <1>;
321 #size-cells = <0>;
322 status = "disabled";
323 };
324
325 spi@7000da00 {
326 compatible = "nvidia,tegra20-slink";
327 reg = <0x7000da00 0x200>;
328 interrupts = <0 93 0x04>;
329 nvidia,dma-request-selector = <&apbdma 18>;
330 #address-cells = <1>;
331 #size-cells = <0>;
332 status = "disabled";
333 };
334
335 pmc {
336 compatible = "nvidia,tegra20-pmc";
337 reg = <0x7000e400 0x400>;
338 };
339
340 memory-controller@7000f000 {
341 compatible = "nvidia,tegra20-mc";
342 reg = <0x7000f000 0x024
343 0x7000f03c 0x3c4>;
344 interrupts = <0 77 0x04>;
345 };
346
347 gart {
348 compatible = "nvidia,tegra20-gart";
349 reg = <0x7000f024 0x00000018 /* controller registers */
350 0x58000000 0x02000000>; /* GART aperture */
351 };
352
353 memory-controller@7000f400 {
354 compatible = "nvidia,tegra20-emc";
355 reg = <0x7000f400 0x200>;
356 #address-cells = <1>;
357 #size-cells = <0>;
358 };
359
360 usb@c5000000 {
361 compatible = "nvidia,tegra20-ehci", "usb-ehci";
362 reg = <0xc5000000 0x4000>;
363 interrupts = <0 20 0x04>;
364 phy_type = "utmi";
365 nvidia,has-legacy-mode;
366 status = "disabled";
367 };
368
369 usb@c5004000 {
370 compatible = "nvidia,tegra20-ehci", "usb-ehci";
371 reg = <0xc5004000 0x4000>;
372 interrupts = <0 21 0x04>;
373 phy_type = "ulpi";
374 status = "disabled";
375 };
376
377 usb@c5008000 {
378 compatible = "nvidia,tegra20-ehci", "usb-ehci";
379 reg = <0xc5008000 0x4000>;
380 interrupts = <0 97 0x04>;
381 phy_type = "utmi";
382 status = "disabled";
383 }; 113 };
384 114
385 sdhci@c8000000 { 115 sdhci@c8000000 {
386 compatible = "nvidia,tegra20-sdhci"; 116 compatible = "nvidia,tegra20-sdhci";
387 reg = <0xc8000000 0x200>; 117 reg = <0xc8000000 0x200>;
388 interrupts = <0 14 0x04>; 118 interrupts = < 46 >;
389 status = "disabled";
390 }; 119 };
391 120
392 sdhci@c8000200 { 121 sdhci@c8000200 {
393 compatible = "nvidia,tegra20-sdhci"; 122 compatible = "nvidia,tegra20-sdhci";
394 reg = <0xc8000200 0x200>; 123 reg = <0xc8000200 0x200>;
395 interrupts = <0 15 0x04>; 124 interrupts = < 47 >;
396 status = "disabled";
397 }; 125 };
398 126
399 sdhci@c8000400 { 127 sdhci@c8000400 {
400 compatible = "nvidia,tegra20-sdhci"; 128 compatible = "nvidia,tegra20-sdhci";
401 reg = <0xc8000400 0x200>; 129 reg = <0xc8000400 0x200>;
402 interrupts = <0 19 0x04>; 130 interrupts = < 51 >;
403 status = "disabled";
404 }; 131 };
405 132
406 sdhci@c8000600 { 133 sdhci@c8000600 {
407 compatible = "nvidia,tegra20-sdhci"; 134 compatible = "nvidia,tegra20-sdhci";
408 reg = <0xc8000600 0x200>; 135 reg = <0xc8000600 0x200>;
409 interrupts = <0 31 0x04>; 136 interrupts = < 63 >;
410 status = "disabled";
411 };
412
413 pmu {
414 compatible = "arm,cortex-a9-pmu";
415 interrupts = <0 56 0x04
416 0 57 0x04>;
417 }; 137 };
418}; 138};
139
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
deleted file mode 100644
index adc88aa50eb..00000000000
--- a/arch/arm/boot/dts/tegra30-cardhu-a02.dts
+++ /dev/null
@@ -1,93 +0,0 @@
1/dts-v1/;
2
3/include/ "tegra30-cardhu.dtsi"
4
5/* This dts file support the cardhu A02 version of board */
6
7/ {
8 model = "NVIDIA Tegra30 Cardhu A02 evaluation board";
9 compatible = "nvidia,cardhu-a02", "nvidia,cardhu", "nvidia,tegra30";
10
11 regulators {
12 compatible = "simple-bus";
13 #address-cells = <1>;
14 #size-cells = <0>;
15
16 ddr_reg: regulator@100 {
17 compatible = "regulator-fixed";
18 reg = <100>;
19 regulator-name = "vdd_ddr";
20 regulator-min-microvolt = <1500000>;
21 regulator-max-microvolt = <1500000>;
22 regulator-always-on;
23 regulator-boot-on;
24 enable-active-high;
25 gpio = <&pmic 6 0>;
26 };
27
28 sys_3v3_reg: regulator@101 {
29 compatible = "regulator-fixed";
30 reg = <101>;
31 regulator-name = "sys_3v3";
32 regulator-min-microvolt = <3300000>;
33 regulator-max-microvolt = <3300000>;
34 regulator-always-on;
35 regulator-boot-on;
36 enable-active-high;
37 gpio = <&pmic 7 0>;
38 };
39
40 usb1_vbus_reg: regulator@102 {
41 compatible = "regulator-fixed";
42 reg = <102>;
43 regulator-name = "usb1_vbus";
44 regulator-min-microvolt = <5000000>;
45 regulator-max-microvolt = <5000000>;
46 enable-active-high;
47 gpio = <&gpio 68 0>; /* GPIO PI4 */
48 gpio-open-drain;
49 vin-supply = <&vdd_5v0_reg>;
50 };
51
52 usb3_vbus_reg: regulator@103 {
53 compatible = "regulator-fixed";
54 reg = <103>;
55 regulator-name = "usb3_vbus";
56 regulator-min-microvolt = <5000000>;
57 regulator-max-microvolt = <5000000>;
58 enable-active-high;
59 gpio = <&gpio 63 0>; /* GPIO PH7 */
60 gpio-open-drain;
61 vin-supply = <&vdd_5v0_reg>;
62 };
63
64 vdd_5v0_reg: regulator@104 {
65 compatible = "regulator-fixed";
66 reg = <104>;
67 regulator-name = "5v0";
68 regulator-min-microvolt = <5000000>;
69 regulator-max-microvolt = <5000000>;
70 enable-active-high;
71 gpio = <&pmic 2 0>;
72 };
73
74 vdd_bl_reg: regulator@105 {
75 compatible = "regulator-fixed";
76 reg = <105>;
77 regulator-name = "vdd_bl";
78 regulator-min-microvolt = <5000000>;
79 regulator-max-microvolt = <5000000>;
80 regulator-always-on;
81 regulator-boot-on;
82 enable-active-high;
83 gpio = <&gpio 83 0>; /* GPIO PK3 */
84 };
85 };
86
87 sdhci@78000400 {
88 status = "okay";
89 power-gpios = <&gpio 28 0>; /* gpio PD4 */
90 bus-width = <4>;
91 };
92};
93
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
deleted file mode 100644
index 08163e145d5..00000000000
--- a/arch/arm/boot/dts/tegra30-cardhu-a04.dts
+++ /dev/null
@@ -1,104 +0,0 @@
1/dts-v1/;
2
3/include/ "tegra30-cardhu.dtsi"
4
5/* This dts file support the cardhu A04 and later versions of board */
6
7/ {
8 model = "NVIDIA Tegra30 Cardhu A04 (A05, A06, A07) evaluation board";
9 compatible = "nvidia,cardhu-a04", "nvidia,cardhu", "nvidia,tegra30";
10
11 regulators {
12 compatible = "simple-bus";
13 #address-cells = <1>;
14 #size-cells = <0>;
15
16 ddr_reg: regulator@100 {
17 compatible = "regulator-fixed";
18 regulator-name = "ddr";
19 reg = <100>;
20 regulator-min-microvolt = <1500000>;
21 regulator-max-microvolt = <1500000>;
22 regulator-always-on;
23 regulator-boot-on;
24 enable-active-high;
25 gpio = <&pmic 7 0>;
26 };
27
28 sys_3v3_reg: regulator@101 {
29 compatible = "regulator-fixed";
30 reg = <101>;
31 regulator-name = "sys_3v3";
32 regulator-min-microvolt = <3300000>;
33 regulator-max-microvolt = <3300000>;
34 regulator-always-on;
35 regulator-boot-on;
36 enable-active-high;
37 gpio = <&pmic 6 0>;
38 };
39
40 usb1_vbus_reg: regulator@102 {
41 compatible = "regulator-fixed";
42 reg = <102>;
43 regulator-name = "usb1_vbus";
44 regulator-min-microvolt = <5000000>;
45 regulator-max-microvolt = <5000000>;
46 enable-active-high;
47 gpio = <&gpio 238 0>; /* GPIO PDD6 */
48 gpio-open-drain;
49 vin-supply = <&vdd_5v0_reg>;
50 };
51
52 usb3_vbus_reg: regulator@103 {
53 compatible = "regulator-fixed";
54 reg = <103>;
55 regulator-name = "usb3_vbus";
56 regulator-min-microvolt = <5000000>;
57 regulator-max-microvolt = <5000000>;
58 enable-active-high;
59 gpio = <&gpio 236 0>; /* GPIO PDD4 */
60 gpio-open-drain;
61 vin-supply = <&vdd_5v0_reg>;
62 };
63
64 vdd_5v0_reg: regulator@104 {
65 compatible = "regulator-fixed";
66 reg = <104>;
67 regulator-name = "5v0";
68 regulator-min-microvolt = <5000000>;
69 regulator-max-microvolt = <5000000>;
70 enable-active-high;
71 gpio = <&pmic 8 0>;
72 };
73
74 vdd_bl_reg: regulator@105 {
75 compatible = "regulator-fixed";
76 reg = <105>;
77 regulator-name = "vdd_bl";
78 regulator-min-microvolt = <5000000>;
79 regulator-max-microvolt = <5000000>;
80 regulator-always-on;
81 regulator-boot-on;
82 enable-active-high;
83 gpio = <&gpio 234 0>; /* GPIO PDD2 */
84 };
85
86 vdd_bl2_reg: regulator@106 {
87 compatible = "regulator-fixed";
88 reg = <106>;
89 regulator-name = "vdd_bl2";
90 regulator-min-microvolt = <5000000>;
91 regulator-max-microvolt = <5000000>;
92 regulator-always-on;
93 regulator-boot-on;
94 enable-active-high;
95 gpio = <&gpio 232 0>; /* GPIO PDD0 */
96 };
97 };
98
99 sdhci@78000400 {
100 status = "okay";
101 power-gpios = <&gpio 27 0>; /* gpio PD3 */
102 bus-width = <4>;
103 };
104};
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
deleted file mode 100644
index bdb2a660f37..00000000000
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ /dev/null
@@ -1,487 +0,0 @@
1/include/ "tegra30.dtsi"
2
3/**
4 * This file contains common DT entry for all fab version of Cardhu.
5 * There is multiple fab version of Cardhu starting from A01 to A07.
6 * Cardhu fab version A01 and A03 are not supported. Cardhu fab version
7 * A02 will have different sets of GPIOs for fixed regulator compare to
8 * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are
9 * compatible with fab version A04. Based on Cardhu fab version, the
10 * related dts file need to be chosen like for Cardhu fab version A02,
11 * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
12 * tegra30-cardhu-a04.dts.
13 * The identification of board is done in two ways, by looking the sticker
14 * on PCB and by reading board id eeprom.
15 * The stciker will have number like 600-81291-1000-002 C.3. In this 4th
16 * number is the fab version like here it is 002 and hence fab version A02.
17 * The (downstream internal) U-Boot of Cardhu display the board-id as
18 * follows:
19 * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00
20 * In this Fab version is 02 i.e. A02.
21 * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56).
22 * The location 0x8 of this eeprom contains the Fab version. It is 1 byte
23 * wide.
24 */
25
26/ {
27 model = "NVIDIA Tegra30 Cardhu evaluation board";
28 compatible = "nvidia,cardhu", "nvidia,tegra30";
29
30 memory {
31 reg = <0x80000000 0x40000000>;
32 };
33
34 pinmux {
35 pinctrl-names = "default";
36 pinctrl-0 = <&state_default>;
37
38 state_default: pinmux {
39 sdmmc1_clk_pz0 {
40 nvidia,pins = "sdmmc1_clk_pz0";
41 nvidia,function = "sdmmc1";
42 nvidia,pull = <0>;
43 nvidia,tristate = <0>;
44 };
45 sdmmc1_cmd_pz1 {
46 nvidia,pins = "sdmmc1_cmd_pz1",
47 "sdmmc1_dat0_py7",
48 "sdmmc1_dat1_py6",
49 "sdmmc1_dat2_py5",
50 "sdmmc1_dat3_py4";
51 nvidia,function = "sdmmc1";
52 nvidia,pull = <2>;
53 nvidia,tristate = <0>;
54 };
55 sdmmc3_clk_pa6 {
56 nvidia,pins = "sdmmc3_clk_pa6";
57 nvidia,function = "sdmmc3";
58 nvidia,pull = <0>;
59 nvidia,tristate = <0>;
60 };
61 sdmmc3_cmd_pa7 {
62 nvidia,pins = "sdmmc3_cmd_pa7",
63 "sdmmc3_dat0_pb7",
64 "sdmmc3_dat1_pb6",
65 "sdmmc3_dat2_pb5",
66 "sdmmc3_dat3_pb4";
67 nvidia,function = "sdmmc3";
68 nvidia,pull = <2>;
69 nvidia,tristate = <0>;
70 };
71 sdmmc4_clk_pcc4 {
72 nvidia,pins = "sdmmc4_clk_pcc4",
73 "sdmmc4_rst_n_pcc3";
74 nvidia,function = "sdmmc4";
75 nvidia,pull = <0>;
76 nvidia,tristate = <0>;
77 };
78 sdmmc4_dat0_paa0 {
79 nvidia,pins = "sdmmc4_dat0_paa0",
80 "sdmmc4_dat1_paa1",
81 "sdmmc4_dat2_paa2",
82 "sdmmc4_dat3_paa3",
83 "sdmmc4_dat4_paa4",
84 "sdmmc4_dat5_paa5",
85 "sdmmc4_dat6_paa6",
86 "sdmmc4_dat7_paa7";
87 nvidia,function = "sdmmc4";
88 nvidia,pull = <2>;
89 nvidia,tristate = <0>;
90 };
91 dap2_fs_pa2 {
92 nvidia,pins = "dap2_fs_pa2",
93 "dap2_sclk_pa3",
94 "dap2_din_pa4",
95 "dap2_dout_pa5";
96 nvidia,function = "i2s1";
97 nvidia,pull = <0>;
98 nvidia,tristate = <0>;
99 };
100 sdio3 {
101 nvidia,pins = "drive_sdio3";
102 nvidia,high-speed-mode = <0>;
103 nvidia,schmitt = <0>;
104 nvidia,pull-down-strength = <46>;
105 nvidia,pull-up-strength = <42>;
106 nvidia,slew-rate-rising = <1>;
107 nvidia,slew-rate-falling = <1>;
108 };
109 };
110 };
111
112 serial@70006000 {
113 status = "okay";
114 clock-frequency = <408000000>;
115 };
116
117 i2c@7000c000 {
118 status = "okay";
119 clock-frequency = <100000>;
120 };
121
122 i2c@7000c400 {
123 status = "okay";
124 clock-frequency = <100000>;
125 };
126
127 i2c@7000c500 {
128 status = "okay";
129 clock-frequency = <100000>;
130
131 /* ALS and Proximity sensor */
132 isl29028@44 {
133 compatible = "isil,isl29028";
134 reg = <0x44>;
135 interrupt-parent = <&gpio>;
136 interrupts = <88 0x04>; /*gpio PL0 */
137 };
138 };
139
140 i2c@7000c700 {
141 status = "okay";
142 clock-frequency = <100000>;
143 };
144
145 i2c@7000d000 {
146 status = "okay";
147 clock-frequency = <100000>;
148
149 wm8903: wm8903@1a {
150 compatible = "wlf,wm8903";
151 reg = <0x1a>;
152 interrupt-parent = <&gpio>;
153 interrupts = <179 0x04>; /* gpio PW3 */
154
155 gpio-controller;
156 #gpio-cells = <2>;
157
158 micdet-cfg = <0>;
159 micdet-delay = <100>;
160 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
161 };
162
163 tps62361 {
164 compatible = "ti,tps62361";
165 reg = <0x60>;
166
167 regulator-name = "tps62361-vout";
168 regulator-min-microvolt = <500000>;
169 regulator-max-microvolt = <1500000>;
170 regulator-boot-on;
171 regulator-always-on;
172 ti,vsel0-state-high;
173 ti,vsel1-state-high;
174 };
175
176 pmic: tps65911@2d {
177 compatible = "ti,tps65911";
178 reg = <0x2d>;
179
180 interrupts = <0 86 0x4>;
181 #interrupt-cells = <2>;
182 interrupt-controller;
183
184 ti,system-power-controller;
185
186 #gpio-cells = <2>;
187 gpio-controller;
188
189 vcc1-supply = <&vdd_ac_bat_reg>;
190 vcc2-supply = <&vdd_ac_bat_reg>;
191 vcc3-supply = <&vio_reg>;
192 vcc4-supply = <&vdd_5v0_reg>;
193 vcc5-supply = <&vdd_ac_bat_reg>;
194 vcc6-supply = <&vdd2_reg>;
195 vcc7-supply = <&vdd_ac_bat_reg>;
196 vccio-supply = <&vdd_ac_bat_reg>;
197
198 regulators {
199 vdd1_reg: vdd1 {
200 regulator-name = "vddio_ddr_1v2";
201 regulator-min-microvolt = <1200000>;
202 regulator-max-microvolt = <1200000>;
203 regulator-always-on;
204 };
205
206 vdd2_reg: vdd2 {
207 regulator-name = "vdd_1v5_gen";
208 regulator-min-microvolt = <1500000>;
209 regulator-max-microvolt = <1500000>;
210 regulator-always-on;
211 };
212
213 vddctrl_reg: vddctrl {
214 regulator-name = "vdd_cpu,vdd_sys";
215 regulator-min-microvolt = <1000000>;
216 regulator-max-microvolt = <1000000>;
217 regulator-always-on;
218 };
219
220 vio_reg: vio {
221 regulator-name = "vdd_1v8_gen";
222 regulator-min-microvolt = <1800000>;
223 regulator-max-microvolt = <1800000>;
224 regulator-always-on;
225 };
226
227 ldo1_reg: ldo1 {
228 regulator-name = "vdd_pexa,vdd_pexb";
229 regulator-min-microvolt = <1050000>;
230 regulator-max-microvolt = <1050000>;
231 };
232
233 ldo2_reg: ldo2 {
234 regulator-name = "vdd_sata,avdd_plle";
235 regulator-min-microvolt = <1050000>;
236 regulator-max-microvolt = <1050000>;
237 };
238
239 /* LDO3 is not connected to anything */
240
241 ldo4_reg: ldo4 {
242 regulator-name = "vdd_rtc";
243 regulator-min-microvolt = <1200000>;
244 regulator-max-microvolt = <1200000>;
245 regulator-always-on;
246 };
247
248 ldo5_reg: ldo5 {
249 regulator-name = "vddio_sdmmc,avdd_vdac";
250 regulator-min-microvolt = <3300000>;
251 regulator-max-microvolt = <3300000>;
252 regulator-always-on;
253 };
254
255 ldo6_reg: ldo6 {
256 regulator-name = "avdd_dsi_csi,pwrdet_mipi";
257 regulator-min-microvolt = <1200000>;
258 regulator-max-microvolt = <1200000>;
259 };
260
261 ldo7_reg: ldo7 {
262 regulator-name = "vdd_pllm,x,u,a_p_c_s";
263 regulator-min-microvolt = <1200000>;
264 regulator-max-microvolt = <1200000>;
265 regulator-always-on;
266 };
267
268 ldo8_reg: ldo8 {
269 regulator-name = "vdd_ddr_hs";
270 regulator-min-microvolt = <1000000>;
271 regulator-max-microvolt = <1000000>;
272 regulator-always-on;
273 };
274 };
275 };
276 };
277
278 spi@7000da00 {
279 status = "okay";
280 spi-max-frequency = <25000000>;
281 spi-flash@1 {
282 compatible = "winbond,w25q32";
283 reg = <1>;
284 spi-max-frequency = <20000000>;
285 };
286 };
287
288 ahub {
289 i2s@70080400 {
290 status = "okay";
291 };
292 };
293
294 pmc {
295 status = "okay";
296 nvidia,invert-interrupt;
297 };
298
299 sdhci@78000000 {
300 status = "okay";
301 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
302 wp-gpios = <&gpio 155 0>; /* gpio PT3 */
303 power-gpios = <&gpio 31 0>; /* gpio PD7 */
304 bus-width = <4>;
305 };
306
307 sdhci@78000600 {
308 status = "okay";
309 bus-width = <8>;
310 };
311
312 regulators {
313 compatible = "simple-bus";
314 #address-cells = <1>;
315 #size-cells = <0>;
316
317 vdd_ac_bat_reg: regulator@0 {
318 compatible = "regulator-fixed";
319 reg = <0>;
320 regulator-name = "vdd_ac_bat";
321 regulator-min-microvolt = <5000000>;
322 regulator-max-microvolt = <5000000>;
323 regulator-always-on;
324 };
325
326 cam_1v8_reg: regulator@1 {
327 compatible = "regulator-fixed";
328 reg = <1>;
329 regulator-name = "cam_1v8";
330 regulator-min-microvolt = <1800000>;
331 regulator-max-microvolt = <1800000>;
332 enable-active-high;
333 gpio = <&gpio 220 0>; /* gpio PBB4 */
334 vin-supply = <&vio_reg>;
335 };
336
337 cp_5v_reg: regulator@2 {
338 compatible = "regulator-fixed";
339 reg = <2>;
340 regulator-name = "cp_5v";
341 regulator-min-microvolt = <5000000>;
342 regulator-max-microvolt = <5000000>;
343 regulator-boot-on;
344 regulator-always-on;
345 enable-active-high;
346 gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */
347 };
348
349 emmc_3v3_reg: regulator@3 {
350 compatible = "regulator-fixed";
351 reg = <3>;
352 regulator-name = "emmc_3v3";
353 regulator-min-microvolt = <3300000>;
354 regulator-max-microvolt = <3300000>;
355 regulator-always-on;
356 regulator-boot-on;
357 enable-active-high;
358 gpio = <&gpio 25 0>; /* gpio PD1 */
359 vin-supply = <&sys_3v3_reg>;
360 };
361
362 modem_3v3_reg: regulator@4 {
363 compatible = "regulator-fixed";
364 reg = <4>;
365 regulator-name = "modem_3v3";
366 regulator-min-microvolt = <3300000>;
367 regulator-max-microvolt = <3300000>;
368 enable-active-high;
369 gpio = <&gpio 30 0>; /* gpio PD6 */
370 };
371
372 pex_hvdd_3v3_reg: regulator@5 {
373 compatible = "regulator-fixed";
374 reg = <5>;
375 regulator-name = "pex_hvdd_3v3";
376 regulator-min-microvolt = <3300000>;
377 regulator-max-microvolt = <3300000>;
378 enable-active-high;
379 gpio = <&gpio 95 0>; /* gpio PL7 */
380 vin-supply = <&sys_3v3_reg>;
381 };
382
383 vdd_cam1_ldo_reg: regulator@6 {
384 compatible = "regulator-fixed";
385 reg = <6>;
386 regulator-name = "vdd_cam1_ldo";
387 regulator-min-microvolt = <2800000>;
388 regulator-max-microvolt = <2800000>;
389 enable-active-high;
390 gpio = <&gpio 142 0>; /* gpio PR6 */
391 vin-supply = <&sys_3v3_reg>;
392 };
393
394 vdd_cam2_ldo_reg: regulator@7 {
395 compatible = "regulator-fixed";
396 reg = <7>;
397 regulator-name = "vdd_cam2_ldo";
398 regulator-min-microvolt = <2800000>;
399 regulator-max-microvolt = <2800000>;
400 enable-active-high;
401 gpio = <&gpio 143 0>; /* gpio PR7 */
402 vin-supply = <&sys_3v3_reg>;
403 };
404
405 vdd_cam3_ldo_reg: regulator@8 {
406 compatible = "regulator-fixed";
407 reg = <8>;
408 regulator-name = "vdd_cam3_ldo";
409 regulator-min-microvolt = <3300000>;
410 regulator-max-microvolt = <3300000>;
411 enable-active-high;
412 gpio = <&gpio 144 0>; /* gpio PS0 */
413 vin-supply = <&sys_3v3_reg>;
414 };
415
416 vdd_com_reg: regulator@9 {
417 compatible = "regulator-fixed";
418 reg = <9>;
419 regulator-name = "vdd_com";
420 regulator-min-microvolt = <3300000>;
421 regulator-max-microvolt = <3300000>;
422 regulator-always-on;
423 regulator-boot-on;
424 enable-active-high;
425 gpio = <&gpio 24 0>; /* gpio PD0 */
426 vin-supply = <&sys_3v3_reg>;
427 };
428
429 vdd_fuse_3v3_reg: regulator@10 {
430 compatible = "regulator-fixed";
431 reg = <10>;
432 regulator-name = "vdd_fuse_3v3";
433 regulator-min-microvolt = <3300000>;
434 regulator-max-microvolt = <3300000>;
435 enable-active-high;
436 gpio = <&gpio 94 0>; /* gpio PL6 */
437 vin-supply = <&sys_3v3_reg>;
438 };
439
440 vdd_pnl1_reg: regulator@11 {
441 compatible = "regulator-fixed";
442 reg = <11>;
443 regulator-name = "vdd_pnl1";
444 regulator-min-microvolt = <3300000>;
445 regulator-max-microvolt = <3300000>;
446 regulator-always-on;
447 regulator-boot-on;
448 enable-active-high;
449 gpio = <&gpio 92 0>; /* gpio PL4 */
450 vin-supply = <&sys_3v3_reg>;
451 };
452
453 vdd_vid_reg: regulator@12 {
454 compatible = "regulator-fixed";
455 reg = <12>;
456 regulator-name = "vddio_vid";
457 regulator-min-microvolt = <5000000>;
458 regulator-max-microvolt = <5000000>;
459 enable-active-high;
460 gpio = <&gpio 152 0>; /* GPIO PT0 */
461 gpio-open-drain;
462 vin-supply = <&vdd_5v0_reg>;
463 };
464 };
465
466 sound {
467 compatible = "nvidia,tegra-audio-wm8903-cardhu",
468 "nvidia,tegra-audio-wm8903";
469 nvidia,model = "NVIDIA Tegra Cardhu";
470
471 nvidia,audio-routing =
472 "Headphone Jack", "HPOUTR",
473 "Headphone Jack", "HPOUTL",
474 "Int Spk", "ROP",
475 "Int Spk", "RON",
476 "Int Spk", "LOP",
477 "Int Spk", "LON",
478 "Mic Jack", "MICBIAS",
479 "IN1L", "Mic Jack";
480
481 nvidia,i2s-controller = <&tegra_i2s1>;
482 nvidia,audio-codec = <&wm8903>;
483
484 nvidia,spkr-en-gpios = <&wm8903 2 0>;
485 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
486 };
487};
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
deleted file mode 100644
index 529fdb82dfd..00000000000
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ /dev/null
@@ -1,456 +0,0 @@
1/include/ "skeleton.dtsi"
2
3/ {
4 compatible = "nvidia,tegra30";
5 interrupt-parent = <&intc>;
6
7 host1x {
8 compatible = "nvidia,tegra30-host1x", "simple-bus";
9 reg = <0x50000000 0x00024000>;
10 interrupts = <0 65 0x04 /* mpcore syncpt */
11 0 67 0x04>; /* mpcore general */
12
13 #address-cells = <1>;
14 #size-cells = <1>;
15
16 ranges = <0x54000000 0x54000000 0x04000000>;
17
18 mpe {
19 compatible = "nvidia,tegra30-mpe";
20 reg = <0x54040000 0x00040000>;
21 interrupts = <0 68 0x04>;
22 };
23
24 vi {
25 compatible = "nvidia,tegra30-vi";
26 reg = <0x54080000 0x00040000>;
27 interrupts = <0 69 0x04>;
28 };
29
30 epp {
31 compatible = "nvidia,tegra30-epp";
32 reg = <0x540c0000 0x00040000>;
33 interrupts = <0 70 0x04>;
34 };
35
36 isp {
37 compatible = "nvidia,tegra30-isp";
38 reg = <0x54100000 0x00040000>;
39 interrupts = <0 71 0x04>;
40 };
41
42 gr2d {
43 compatible = "nvidia,tegra30-gr2d";
44 reg = <0x54140000 0x00040000>;
45 interrupts = <0 72 0x04>;
46 };
47
48 gr3d {
49 compatible = "nvidia,tegra30-gr3d";
50 reg = <0x54180000 0x00040000>;
51 };
52
53 dc@54200000 {
54 compatible = "nvidia,tegra30-dc";
55 reg = <0x54200000 0x00040000>;
56 interrupts = <0 73 0x04>;
57
58 rgb {
59 status = "disabled";
60 };
61 };
62
63 dc@54240000 {
64 compatible = "nvidia,tegra30-dc";
65 reg = <0x54240000 0x00040000>;
66 interrupts = <0 74 0x04>;
67
68 rgb {
69 status = "disabled";
70 };
71 };
72
73 hdmi {
74 compatible = "nvidia,tegra30-hdmi";
75 reg = <0x54280000 0x00040000>;
76 interrupts = <0 75 0x04>;
77 status = "disabled";
78 };
79
80 tvo {
81 compatible = "nvidia,tegra30-tvo";
82 reg = <0x542c0000 0x00040000>;
83 interrupts = <0 76 0x04>;
84 status = "disabled";
85 };
86
87 dsi {
88 compatible = "nvidia,tegra30-dsi";
89 reg = <0x54300000 0x00040000>;
90 status = "disabled";
91 };
92 };
93
94 timer@50004600 {
95 compatible = "arm,cortex-a9-twd-timer";
96 reg = <0x50040600 0x20>;
97 interrupts = <1 13 0xf04>;
98 };
99
100 cache-controller@50043000 {
101 compatible = "arm,pl310-cache";
102 reg = <0x50043000 0x1000>;
103 arm,data-latency = <6 6 2>;
104 arm,tag-latency = <5 5 2>;
105 cache-unified;
106 cache-level = <2>;
107 };
108
109 intc: interrupt-controller {
110 compatible = "arm,cortex-a9-gic";
111 reg = <0x50041000 0x1000
112 0x50040100 0x0100>;
113 interrupt-controller;
114 #interrupt-cells = <3>;
115 };
116
117 timer@60005000 {
118 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
119 reg = <0x60005000 0x400>;
120 interrupts = <0 0 0x04
121 0 1 0x04
122 0 41 0x04
123 0 42 0x04
124 0 121 0x04
125 0 122 0x04>;
126 };
127
128 apbdma: dma {
129 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
130 reg = <0x6000a000 0x1400>;
131 interrupts = <0 104 0x04
132 0 105 0x04
133 0 106 0x04
134 0 107 0x04
135 0 108 0x04
136 0 109 0x04
137 0 110 0x04
138 0 111 0x04
139 0 112 0x04
140 0 113 0x04
141 0 114 0x04
142 0 115 0x04
143 0 116 0x04
144 0 117 0x04
145 0 118 0x04
146 0 119 0x04
147 0 128 0x04
148 0 129 0x04
149 0 130 0x04
150 0 131 0x04
151 0 132 0x04
152 0 133 0x04
153 0 134 0x04
154 0 135 0x04
155 0 136 0x04
156 0 137 0x04
157 0 138 0x04
158 0 139 0x04
159 0 140 0x04
160 0 141 0x04
161 0 142 0x04
162 0 143 0x04>;
163 };
164
165 ahb: ahb {
166 compatible = "nvidia,tegra30-ahb";
167 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
168 };
169
170 gpio: gpio {
171 compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio";
172 reg = <0x6000d000 0x1000>;
173 interrupts = <0 32 0x04
174 0 33 0x04
175 0 34 0x04
176 0 35 0x04
177 0 55 0x04
178 0 87 0x04
179 0 89 0x04
180 0 125 0x04>;
181 #gpio-cells = <2>;
182 gpio-controller;
183 #interrupt-cells = <2>;
184 interrupt-controller;
185 };
186
187 pinmux: pinmux {
188 compatible = "nvidia,tegra30-pinmux";
189 reg = <0x70000868 0xd4 /* Pad control registers */
190 0x70003000 0x3e4>; /* Mux registers */
191 };
192
193 serial@70006000 {
194 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
195 reg = <0x70006000 0x40>;
196 reg-shift = <2>;
197 interrupts = <0 36 0x04>;
198 status = "disabled";
199 };
200
201 serial@70006040 {
202 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
203 reg = <0x70006040 0x40>;
204 reg-shift = <2>;
205 interrupts = <0 37 0x04>;
206 status = "disabled";
207 };
208
209 serial@70006200 {
210 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
211 reg = <0x70006200 0x100>;
212 reg-shift = <2>;
213 interrupts = <0 46 0x04>;
214 status = "disabled";
215 };
216
217 serial@70006300 {
218 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
219 reg = <0x70006300 0x100>;
220 reg-shift = <2>;
221 interrupts = <0 90 0x04>;
222 status = "disabled";
223 };
224
225 serial@70006400 {
226 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
227 reg = <0x70006400 0x100>;
228 reg-shift = <2>;
229 interrupts = <0 91 0x04>;
230 status = "disabled";
231 };
232
233 pwm: pwm {
234 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
235 reg = <0x7000a000 0x100>;
236 #pwm-cells = <2>;
237 };
238
239 rtc {
240 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
241 reg = <0x7000e000 0x100>;
242 interrupts = <0 2 0x04>;
243 };
244
245 i2c@7000c000 {
246 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
247 reg = <0x7000c000 0x100>;
248 interrupts = <0 38 0x04>;
249 #address-cells = <1>;
250 #size-cells = <0>;
251 status = "disabled";
252 };
253
254 i2c@7000c400 {
255 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
256 reg = <0x7000c400 0x100>;
257 interrupts = <0 84 0x04>;
258 #address-cells = <1>;
259 #size-cells = <0>;
260 status = "disabled";
261 };
262
263 i2c@7000c500 {
264 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
265 reg = <0x7000c500 0x100>;
266 interrupts = <0 92 0x04>;
267 #address-cells = <1>;
268 #size-cells = <0>;
269 status = "disabled";
270 };
271
272 i2c@7000c700 {
273 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
274 reg = <0x7000c700 0x100>;
275 interrupts = <0 120 0x04>;
276 #address-cells = <1>;
277 #size-cells = <0>;
278 status = "disabled";
279 };
280
281 i2c@7000d000 {
282 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
283 reg = <0x7000d000 0x100>;
284 interrupts = <0 53 0x04>;
285 #address-cells = <1>;
286 #size-cells = <0>;
287 status = "disabled";
288 };
289
290 spi@7000d400 {
291 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
292 reg = <0x7000d400 0x200>;
293 interrupts = <0 59 0x04>;
294 nvidia,dma-request-selector = <&apbdma 15>;
295 #address-cells = <1>;
296 #size-cells = <0>;
297 status = "disabled";
298 };
299
300 spi@7000d600 {
301 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
302 reg = <0x7000d600 0x200>;
303 interrupts = <0 82 0x04>;
304 nvidia,dma-request-selector = <&apbdma 16>;
305 #address-cells = <1>;
306 #size-cells = <0>;
307 status = "disabled";
308 };
309
310 spi@7000d800 {
311 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
312 reg = <0x7000d480 0x200>;
313 interrupts = <0 83 0x04>;
314 nvidia,dma-request-selector = <&apbdma 17>;
315 #address-cells = <1>;
316 #size-cells = <0>;
317 status = "disabled";
318 };
319
320 spi@7000da00 {
321 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
322 reg = <0x7000da00 0x200>;
323 interrupts = <0 93 0x04>;
324 nvidia,dma-request-selector = <&apbdma 18>;
325 #address-cells = <1>;
326 #size-cells = <0>;
327 status = "disabled";
328 };
329
330 spi@7000dc00 {
331 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
332 reg = <0x7000dc00 0x200>;
333 interrupts = <0 94 0x04>;
334 nvidia,dma-request-selector = <&apbdma 27>;
335 #address-cells = <1>;
336 #size-cells = <0>;
337 status = "disabled";
338 };
339
340 spi@7000de00 {
341 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
342 reg = <0x7000de00 0x200>;
343 interrupts = <0 79 0x04>;
344 nvidia,dma-request-selector = <&apbdma 28>;
345 #address-cells = <1>;
346 #size-cells = <0>;
347 status = "disabled";
348 };
349
350 pmc {
351 compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
352 reg = <0x7000e400 0x400>;
353 };
354
355 memory-controller {
356 compatible = "nvidia,tegra30-mc";
357 reg = <0x7000f000 0x010
358 0x7000f03c 0x1b4
359 0x7000f200 0x028
360 0x7000f284 0x17c>;
361 interrupts = <0 77 0x04>;
362 };
363
364 smmu {
365 compatible = "nvidia,tegra30-smmu";
366 reg = <0x7000f010 0x02c
367 0x7000f1f0 0x010
368 0x7000f228 0x05c>;
369 nvidia,#asids = <4>; /* # of ASIDs */
370 dma-window = <0 0x40000000>; /* IOVA start & length */
371 nvidia,ahb = <&ahb>;
372 };
373
374 ahub {
375 compatible = "nvidia,tegra30-ahub";
376 reg = <0x70080000 0x200
377 0x70080200 0x100>;
378 interrupts = <0 103 0x04>;
379 nvidia,dma-request-selector = <&apbdma 1>;
380
381 ranges;
382 #address-cells = <1>;
383 #size-cells = <1>;
384
385 tegra_i2s0: i2s@70080300 {
386 compatible = "nvidia,tegra30-i2s";
387 reg = <0x70080300 0x100>;
388 nvidia,ahub-cif-ids = <4 4>;
389 status = "disabled";
390 };
391
392 tegra_i2s1: i2s@70080400 {
393 compatible = "nvidia,tegra30-i2s";
394 reg = <0x70080400 0x100>;
395 nvidia,ahub-cif-ids = <5 5>;
396 status = "disabled";
397 };
398
399 tegra_i2s2: i2s@70080500 {
400 compatible = "nvidia,tegra30-i2s";
401 reg = <0x70080500 0x100>;
402 nvidia,ahub-cif-ids = <6 6>;
403 status = "disabled";
404 };
405
406 tegra_i2s3: i2s@70080600 {
407 compatible = "nvidia,tegra30-i2s";
408 reg = <0x70080600 0x100>;
409 nvidia,ahub-cif-ids = <7 7>;
410 status = "disabled";
411 };
412
413 tegra_i2s4: i2s@70080700 {
414 compatible = "nvidia,tegra30-i2s";
415 reg = <0x70080700 0x100>;
416 nvidia,ahub-cif-ids = <8 8>;
417 status = "disabled";
418 };
419 };
420
421 sdhci@78000000 {
422 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
423 reg = <0x78000000 0x200>;
424 interrupts = <0 14 0x04>;
425 status = "disabled";
426 };
427
428 sdhci@78000200 {
429 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
430 reg = <0x78000200 0x200>;
431 interrupts = <0 15 0x04>;
432 status = "disabled";
433 };
434
435 sdhci@78000400 {
436 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
437 reg = <0x78000400 0x200>;
438 interrupts = <0 19 0x04>;
439 status = "disabled";
440 };
441
442 sdhci@78000600 {
443 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
444 reg = <0x78000600 0x200>;
445 interrupts = <0 31 0x04>;
446 status = "disabled";
447 };
448
449 pmu {
450 compatible = "arm,cortex-a9-pmu";
451 interrupts = <0 144 0x04
452 0 145 0x04
453 0 146 0x04
454 0 147 0x04>;
455 };
456};
diff --git a/arch/arm/boot/dts/testcases/tests-phandle.dtsi b/arch/arm/boot/dts/testcases/tests-phandle.dtsi
deleted file mode 100644
index 0007d3cd7dc..00000000000
--- a/arch/arm/boot/dts/testcases/tests-phandle.dtsi
+++ /dev/null
@@ -1,39 +0,0 @@
1
2/ {
3 testcase-data {
4 phandle-tests {
5 provider0: provider0 {
6 #phandle-cells = <0>;
7 };
8
9 provider1: provider1 {
10 #phandle-cells = <1>;
11 };
12
13 provider2: provider2 {
14 #phandle-cells = <2>;
15 };
16
17 provider3: provider3 {
18 #phandle-cells = <3>;
19 };
20
21 consumer-a {
22 phandle-list = <&provider1 1>,
23 <&provider2 2 0>,
24 <0>,
25 <&provider3 4 4 3>,
26 <&provider2 5 100>,
27 <&provider0>,
28 <&provider1 7>;
29 phandle-list-names = "first", "second", "third";
30
31 phandle-list-bad-phandle = <12345678 0 0>;
32 phandle-list-bad-args = <&provider2 1 0>,
33 <&provider3 0>;
34 empty-property;
35 unterminated-string = [40 41 42 43];
36 };
37 };
38 };
39};
diff --git a/arch/arm/boot/dts/testcases/tests.dtsi b/arch/arm/boot/dts/testcases/tests.dtsi
deleted file mode 100644
index a7c5067622e..00000000000
--- a/arch/arm/boot/dts/testcases/tests.dtsi
+++ /dev/null
@@ -1 +0,0 @@
1/include/ "tests-phandle.dtsi"
diff --git a/arch/arm/boot/dts/tny_a9260.dts b/arch/arm/boot/dts/tny_a9260.dts
deleted file mode 100644
index 367a16dcd5e..00000000000
--- a/arch/arm/boot/dts/tny_a9260.dts
+++ /dev/null
@@ -1,15 +0,0 @@
1/*
2 * tny_a9260.dts - Device Tree file for Caloa TNY A9260 board
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8/dts-v1/;
9/include/ "at91sam9260.dtsi"
10/include/ "tny_a9260_common.dtsi"
11
12/ {
13 model = "Calao TNY A9260";
14 compatible = "calao,tny-a9260", "atmel,at91sam9260", "atmel,at91sam9";
15};
diff --git a/arch/arm/boot/dts/tny_a9260_common.dtsi b/arch/arm/boot/dts/tny_a9260_common.dtsi
deleted file mode 100644
index 0e6d3de2e09..00000000000
--- a/arch/arm/boot/dts/tny_a9260_common.dtsi
+++ /dev/null
@@ -1,83 +0,0 @@
1/*
2 * tny_a9260_common.dtsi - Device Tree file for Caloa TNY A926x board
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8
9/ {
10 chosen {
11 bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock6 rw rootfstype=ubifs";
12 };
13
14 memory {
15 reg = <0x20000000 0x4000000>;
16 };
17
18 clocks {
19 #address-cells = <1>;
20 #size-cells = <1>;
21 ranges;
22
23 main_clock: clock@0 {
24 compatible = "atmel,osc", "fixed-clock";
25 clock-frequency = <12000000>;
26 };
27 };
28
29 ahb {
30 apb {
31 dbgu: serial@fffff200 {
32 status = "okay";
33 };
34 };
35
36 nand0: nand@40000000 {
37 nand-bus-width = <8>;
38 nand-ecc-mode = "soft";
39 nand-on-flash-bbt;
40 status = "okay";
41
42 at91bootstrap@0 {
43 label = "at91bootstrap";
44 reg = <0x0 0x20000>;
45 };
46
47 barebox@20000 {
48 label = "barebox";
49 reg = <0x20000 0x40000>;
50 };
51
52 bareboxenv@60000 {
53 label = "bareboxenv";
54 reg = <0x60000 0x20000>;
55 };
56
57 bareboxenv2@80000 {
58 label = "bareboxenv2";
59 reg = <0x80000 0x20000>;
60 };
61
62 oftree@80000 {
63 label = "oftree";
64 reg = <0xa0000 0x20000>;
65 };
66
67 kernel@a0000 {
68 label = "kernel";
69 reg = <0xc0000 0x400000>;
70 };
71
72 rootfs@4a0000 {
73 label = "rootfs";
74 reg = <0x4c0000 0x7800000>;
75 };
76
77 data@7ca0000 {
78 label = "data";
79 reg = <0x7cc0000 0x8340000>;
80 };
81 };
82 };
83};
diff --git a/arch/arm/boot/dts/tny_a9263.dts b/arch/arm/boot/dts/tny_a9263.dts
deleted file mode 100644
index dee9c571306..00000000000
--- a/arch/arm/boot/dts/tny_a9263.dts
+++ /dev/null
@@ -1,97 +0,0 @@
1/*
2 * usb_a9263.dts - Device Tree file for Caloa USB A9293 board
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2 only
7 */
8/dts-v1/;
9/include/ "at91sam9263.dtsi"
10
11/ {
12 model = "Calao TNY A9263";
13 compatible = "atmel,tny-a9263", "atmel,at91sam9263", "atmel,at91sam9";
14
15 chosen {
16 bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
17 };
18
19 memory {
20 reg = <0x20000000 0x4000000>;
21 };
22
23 clocks {
24 #address-cells = <1>;
25 #size-cells = <1>;
26 ranges;
27
28 main_clock: clock@0 {
29 compatible = "atmel,osc", "fixed-clock";
30 clock-frequency = <12000000>;
31 };
32 };
33
34 ahb {
35 apb {
36 dbgu: serial@ffffee00 {
37 status = "okay";
38 };
39
40 usb1: gadget@fff78000 {
41 atmel,vbus-gpio = <&pioB 11 0>;
42 status = "okay";
43 };
44 };
45
46 nand0: nand@40000000 {
47 nand-bus-width = <8>;
48 nand-ecc-mode = "soft";
49 nand-on-flash-bbt;
50 status = "okay";
51
52 at91bootstrap@0 {
53 label = "at91bootstrap";
54 reg = <0x0 0x20000>;
55 };
56
57 barebox@20000 {
58 label = "barebox";
59 reg = <0x20000 0x40000>;
60 };
61
62 bareboxenv@60000 {
63 label = "bareboxenv";
64 reg = <0x60000 0x20000>;
65 };
66
67 bareboxenv2@80000 {
68 label = "bareboxenv2";
69 reg = <0x80000 0x20000>;
70 };
71
72 oftree@80000 {
73 label = "oftree";
74 reg = <0xa0000 0x20000>;
75 };
76
77 kernel@a0000 {
78 label = "kernel";
79 reg = <0xc0000 0x400000>;
80 };
81
82 rootfs@4a0000 {
83 label = "rootfs";
84 reg = <0x4c0000 0x7800000>;
85 };
86
87 data@7ca0000 {
88 label = "data";
89 reg = <0x7cc0000 0x8340000>;
90 };
91 };
92 };
93
94 i2c@0 {
95 status = "okay";
96 };
97};
diff --git a/arch/arm/boot/dts/tny_a9g20.dts b/arch/arm/boot/dts/tny_a9g20.dts
deleted file mode 100644
index e1ab64c72db..00000000000
--- a/arch/arm/boot/dts/tny_a9g20.dts
+++ /dev/null
@@ -1,15 +0,0 @@
1/*
2 * tny_a9g20.dts - Device Tree file for Caloa TNY A9G20 board
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8/dts-v1/;
9/include/ "at91sam9g20.dtsi"
10/include/ "tny_a9260_common.dtsi"
11
12/ {
13 model = "Calao TNY A9G20";
14 compatible = "calao,tny-a9g20", "atmel,at91sam9g20", "atmel,at91sam9";
15};
diff --git a/arch/arm/boot/dts/tps65217.dtsi b/arch/arm/boot/dts/tps65217.dtsi
deleted file mode 100644
index a63272422d7..00000000000
--- a/arch/arm/boot/dts/tps65217.dtsi
+++ /dev/null
@@ -1,56 +0,0 @@
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * Integrated Power Management Chip
11 * http://www.ti.com/lit/ds/symlink/tps65217.pdf
12 */
13
14&tps {
15 compatible = "ti,tps65217";
16
17 regulators {
18 #address-cells = <1>;
19 #size-cells = <0>;
20
21 dcdc1_reg: regulator@0 {
22 reg = <0>;
23 regulator-compatible = "dcdc1";
24 };
25
26 dcdc2_reg: regulator@1 {
27 reg = <1>;
28 regulator-compatible = "dcdc2";
29 };
30
31 dcdc3_reg: regulator@2 {
32 reg = <2>;
33 regulator-compatible = "dcdc3";
34 };
35
36 ldo1_reg: regulator@3 {
37 reg = <3>;
38 regulator-compatible = "ldo1";
39 };
40
41 ldo2_reg: regulator@4 {
42 reg = <4>;
43 regulator-compatible = "ldo2";
44 };
45
46 ldo3_reg: regulator@5 {
47 reg = <5>;
48 regulator-compatible = "ldo3";
49 };
50
51 ldo4_reg: regulator@6 {
52 reg = <6>;
53 regulator-compatible = "ldo4";
54 };
55 };
56};
diff --git a/arch/arm/boot/dts/tps65910.dtsi b/arch/arm/boot/dts/tps65910.dtsi
deleted file mode 100644
index 92693a89160..00000000000
--- a/arch/arm/boot/dts/tps65910.dtsi
+++ /dev/null
@@ -1,86 +0,0 @@
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * Integrated Power Management Chip
11 * http://www.ti.com/lit/ds/symlink/tps65910.pdf
12 */
13
14&tps {
15 compatible = "ti,tps65910";
16
17 regulators {
18 #address-cells = <1>;
19 #size-cells = <0>;
20
21 vrtc_reg: regulator@0 {
22 reg = <0>;
23 regulator-compatible = "vrtc";
24 };
25
26 vio_reg: regulator@1 {
27 reg = <1>;
28 regulator-compatible = "vio";
29 };
30
31 vdd1_reg: regulator@2 {
32 reg = <2>;
33 regulator-compatible = "vdd1";
34 };
35
36 vdd2_reg: regulator@3 {
37 reg = <3>;
38 regulator-compatible = "vdd2";
39 };
40
41 vdd3_reg: regulator@4 {
42 reg = <4>;
43 regulator-compatible = "vdd3";
44 };
45
46 vdig1_reg: regulator@5 {
47 reg = <5>;
48 regulator-compatible = "vdig1";
49 };
50
51 vdig2_reg: regulator@6 {
52 reg = <6>;
53 regulator-compatible = "vdig2";
54 };
55
56 vpll_reg: regulator@7 {
57 reg = <7>;
58 regulator-compatible = "vpll";
59 };
60
61 vdac_reg: regulator@8 {
62 reg = <8>;
63 regulator-compatible = "vdac";
64 };
65
66 vaux1_reg: regulator@9 {
67 reg = <9>;
68 regulator-compatible = "vaux1";
69 };
70
71 vaux2_reg: regulator@10 {
72 reg = <10>;
73 regulator-compatible = "vaux2";
74 };
75
76 vaux33_reg: regulator@11 {
77 reg = <11>;
78 regulator-compatible = "vaux33";
79 };
80
81 vmmc_reg: regulator@12 {
82 reg = <12>;
83 regulator-compatible = "vmmc";
84 };
85 };
86};
diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/twl4030.dtsi
deleted file mode 100644
index ed0bc954683..00000000000
--- a/arch/arm/boot/dts/twl4030.dtsi
+++ /dev/null
@@ -1,78 +0,0 @@
1/*
2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * Integrated Power Management Chip
11 */
12&twl {
13 compatible = "ti,twl4030";
14 interrupt-controller;
15 #interrupt-cells = <1>;
16
17 rtc {
18 compatible = "ti,twl4030-rtc";
19 interrupts = <11>;
20 };
21
22 watchdog {
23 compatible = "ti,twl4030-wdt";
24 };
25
26 vdac: regulator-vdac {
27 compatible = "ti,twl4030-vdac";
28 regulator-min-microvolt = <1800000>;
29 regulator-max-microvolt = <1800000>;
30 };
31
32 vpll2: regulator-vpll2 {
33 compatible = "ti,twl4030-vpll2";
34 regulator-min-microvolt = <1800000>;
35 regulator-max-microvolt = <1800000>;
36 };
37
38 vmmc1: regulator-vmmc1 {
39 compatible = "ti,twl4030-vmmc1";
40 regulator-min-microvolt = <1850000>;
41 regulator-max-microvolt = <3150000>;
42 };
43
44 vusb1v5: regulator-vusb1v5 {
45 compatible = "ti,twl4030-vusb1v5";
46 };
47
48 vusb1v8: regulator-vusb1v8 {
49 compatible = "ti,twl4030-vusb1v8";
50 };
51
52 vusb3v1: regulator-vusb3v1 {
53 compatible = "ti,twl4030-vusb3v1";
54 };
55
56 vsim: regulator-vsim {
57 compatible = "ti,twl4030-vsim";
58 regulator-min-microvolt = <1800000>;
59 regulator-max-microvolt = <3000000>;
60 };
61
62 twl_gpio: gpio {
63 compatible = "ti,twl4030-gpio";
64 gpio-controller;
65 #gpio-cells = <2>;
66 interrupt-controller;
67 #interrupt-cells = <1>;
68 };
69
70 twl4030-usb {
71 compatible = "ti,twl4030-usb";
72 interrupts = <10>, <4>;
73 usb1v5-supply = <&vusb1v5>;
74 usb1v8-supply = <&vusb1v8>;
75 usb3v1-supply = <&vusb3v1>;
76 usb_mode = <1>;
77 };
78};
diff --git a/arch/arm/boot/dts/twl6030.dtsi b/arch/arm/boot/dts/twl6030.dtsi
deleted file mode 100644
index 9996cfc5ee8..00000000000
--- a/arch/arm/boot/dts/twl6030.dtsi
+++ /dev/null
@@ -1,94 +0,0 @@
1/*
2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * Integrated Power Management Chip
11 * http://www.ti.com/lit/ds/symlink/twl6030.pdf
12 */
13&twl {
14 compatible = "ti,twl6030";
15 interrupt-controller;
16 #interrupt-cells = <1>;
17
18 rtc {
19 compatible = "ti,twl4030-rtc";
20 interrupts = <11>;
21 };
22
23 vaux1: regulator-vaux1 {
24 compatible = "ti,twl6030-vaux1";
25 regulator-min-microvolt = <1000000>;
26 regulator-max-microvolt = <3000000>;
27 };
28
29 vaux2: regulator-vaux2 {
30 compatible = "ti,twl6030-vaux2";
31 regulator-min-microvolt = <1200000>;
32 regulator-max-microvolt = <2800000>;
33 };
34
35 vaux3: regulator-vaux3 {
36 compatible = "ti,twl6030-vaux3";
37 regulator-min-microvolt = <1000000>;
38 regulator-max-microvolt = <3000000>;
39 };
40
41 vmmc: regulator-vmmc {
42 compatible = "ti,twl6030-vmmc";
43 regulator-min-microvolt = <1200000>;
44 regulator-max-microvolt = <3000000>;
45 };
46
47 vpp: regulator-vpp {
48 compatible = "ti,twl6030-vpp";
49 regulator-min-microvolt = <1800000>;
50 regulator-max-microvolt = <2500000>;
51 };
52
53 vusim: regulator-vusim {
54 compatible = "ti,twl6030-vusim";
55 regulator-min-microvolt = <1200000>;
56 regulator-max-microvolt = <2900000>;
57 };
58
59 vdac: regulator-vdac {
60 compatible = "ti,twl6030-vdac";
61 };
62
63 vana: regulator-vana {
64 compatible = "ti,twl6030-vana";
65 };
66
67 vcxio: regulator-vcxio {
68 compatible = "ti,twl6030-vcxio";
69 regulator-always-on;
70 };
71
72 vusb: regulator-vusb {
73 compatible = "ti,twl6030-vusb";
74 };
75
76 v1v8: regulator-v1v8 {
77 compatible = "ti,twl6030-v1v8";
78 regulator-always-on;
79 };
80
81 v2v1: regulator-v2v1 {
82 compatible = "ti,twl6030-v2v1";
83 regulator-always-on;
84 };
85
86 clk32kg: regulator-clk32kg {
87 compatible = "ti,twl6030-clk32kg";
88 };
89
90 twl_usb_comparator: usb-comparator {
91 compatible = "ti,twl6030-usb";
92 interrupts = <4>, <10>;
93 };
94};
diff --git a/arch/arm/boot/dts/u9540.dts b/arch/arm/boot/dts/u9540.dts
deleted file mode 100644
index 95892ec6c34..00000000000
--- a/arch/arm/boot/dts/u9540.dts
+++ /dev/null
@@ -1,72 +0,0 @@
1/*
2 * Copyright 2012 ST-Ericsson AB
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "dbx5x0.dtsi"
14
15/ {
16 model = "ST-Ericsson U9540 platform with Device Tree";
17 compatible = "st-ericsson,u9540";
18
19 memory {
20 reg = <0x00000000 0x20000000>;
21 };
22
23 soc-u9500 {
24 uart@80120000 {
25 status = "okay";
26 };
27
28 uart@80121000 {
29 status = "okay";
30 };
31
32 uart@80007000 {
33 status = "okay";
34 };
35
36 // External Micro SD slot
37 sdi0_per1@80126000 {
38 arm,primecell-periphid = <0x10480180>;
39 max-frequency = <100000000>;
40 bus-width = <4>;
41 mmc-cap-sd-highspeed;
42 mmc-cap-mmc-highspeed;
43 vmmc-supply = <&ab8500_ldo_aux3_reg>;
44
45 cd-gpios = <&gpio7 6 0x4>; // 230
46 cd-inverted;
47
48 status = "okay";
49 };
50
51
52 // WLAN SDIO channel
53 sdi1_per2@80118000 {
54 arm,primecell-periphid = <0x10480180>;
55 max-frequency = <50000000>;
56 bus-width = <4>;
57
58 status = "okay";
59 };
60
61 // On-board eMMC
62 sdi4_per2@80114000 {
63 arm,primecell-periphid = <0x10480180>;
64 max-frequency = <100000000>;
65 bus-width = <8>;
66 mmc-cap-mmc-highspeed;
67 vmmc-supply = <&ab8500_ldo_aux2_reg>;
68
69 status = "okay";
70 };
71 };
72};
diff --git a/arch/arm/boot/dts/usb_a9260.dts b/arch/arm/boot/dts/usb_a9260.dts
deleted file mode 100644
index 296216058c1..00000000000
--- a/arch/arm/boot/dts/usb_a9260.dts
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * usb_a9260.dts - Device Tree file for Caloa USB A9260 board
3 *
4 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2 or later.
7 */
8/dts-v1/;
9/include/ "at91sam9260.dtsi"
10/include/ "usb_a9260_common.dtsi"
11
12/ {
13 model = "Calao USB A9260";
14 compatible = "calao,usb-a9260", "atmel,at91sam9260", "atmel,at91sam9";
15
16 chosen {
17 bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
18 };
19
20 memory {
21 reg = <0x20000000 0x4000000>;
22 };
23};
diff --git a/arch/arm/boot/dts/usb_a9260_common.dtsi b/arch/arm/boot/dts/usb_a9260_common.dtsi
deleted file mode 100644
index e70d229baef..00000000000
--- a/arch/arm/boot/dts/usb_a9260_common.dtsi
+++ /dev/null
@@ -1,117 +0,0 @@
1/*
2 * usb_a926x.dts - Device Tree file for Caloa USB A926x board
3 *
4 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9/ {
10 clocks {
11 #address-cells = <1>;
12 #size-cells = <1>;
13 ranges;
14
15 main_clock: clock@0 {
16 compatible = "atmel,osc", "fixed-clock";
17 clock-frequency = <12000000>;
18 };
19 };
20
21 ahb {
22 apb {
23 dbgu: serial@fffff200 {
24 status = "okay";
25 };
26
27 macb0: ethernet@fffc4000 {
28 phy-mode = "rmii";
29 status = "okay";
30 };
31
32 usb1: gadget@fffa4000 {
33 atmel,vbus-gpio = <&pioC 5 0>;
34 status = "okay";
35 };
36 };
37
38 nand0: nand@40000000 {
39 nand-bus-width = <8>;
40 nand-ecc-mode = "soft";
41 nand-on-flash-bbt;
42 status = "okay";
43
44 at91bootstrap@0 {
45 label = "at91bootstrap";
46 reg = <0x0 0x20000>;
47 };
48
49 barebox@20000 {
50 label = "barebox";
51 reg = <0x20000 0x40000>;
52 };
53
54 bareboxenv@60000 {
55 label = "bareboxenv";
56 reg = <0x60000 0x20000>;
57 };
58
59 bareboxenv2@80000 {
60 label = "bareboxenv2";
61 reg = <0x80000 0x20000>;
62 };
63
64 oftree@80000 {
65 label = "oftree";
66 reg = <0xa0000 0x20000>;
67 };
68
69 kernel@a0000 {
70 label = "kernel";
71 reg = <0xc0000 0x400000>;
72 };
73
74 rootfs@4a0000 {
75 label = "rootfs";
76 reg = <0x4c0000 0x7800000>;
77 };
78
79 data@7ca0000 {
80 label = "data";
81 reg = <0x7cc0000 0x8340000>;
82 };
83 };
84
85 usb0: ohci@00500000 {
86 num-ports = <2>;
87 status = "okay";
88 };
89 };
90
91 leds {
92 compatible = "gpio-leds";
93
94 user_led {
95 label = "user_led";
96 gpios = <&pioB 21 1>;
97 linux,default-trigger = "heartbeat";
98 };
99 };
100
101 gpio_keys {
102 compatible = "gpio-keys";
103 #address-cells = <1>;
104 #size-cells = <0>;
105
106 user_pb {
107 label = "user_pb";
108 gpios = <&pioB 10 1>;
109 linux,code = <28>;
110 gpio-key,wakeup;
111 };
112 };
113
114 i2c@0 {
115 status = "okay";
116 };
117};
diff --git a/arch/arm/boot/dts/usb_a9263.dts b/arch/arm/boot/dts/usb_a9263.dts
deleted file mode 100644
index 6fe05ccb620..00000000000
--- a/arch/arm/boot/dts/usb_a9263.dts
+++ /dev/null
@@ -1,131 +0,0 @@
1/*
2 * usb_a9263.dts - Device Tree file for Caloa USB A9293 board
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2 only
7 */
8/dts-v1/;
9/include/ "at91sam9263.dtsi"
10
11/ {
12 model = "Calao USB A9263";
13 compatible = "atmel,usb-a9263", "atmel,at91sam9263", "atmel,at91sam9";
14
15 chosen {
16 bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
17 };
18
19 memory {
20 reg = <0x20000000 0x4000000>;
21 };
22
23 clocks {
24 #address-cells = <1>;
25 #size-cells = <1>;
26 ranges;
27
28 main_clock: clock@0 {
29 compatible = "atmel,osc", "fixed-clock";
30 clock-frequency = <12000000>;
31 };
32 };
33
34 ahb {
35 apb {
36 dbgu: serial@ffffee00 {
37 status = "okay";
38 };
39
40 macb0: ethernet@fffbc000 {
41 phy-mode = "rmii";
42 status = "okay";
43 };
44
45 usb1: gadget@fff78000 {
46 atmel,vbus-gpio = <&pioB 11 0>;
47 status = "okay";
48 };
49
50 };
51
52 nand0: nand@40000000 {
53 nand-bus-width = <8>;
54 nand-ecc-mode = "soft";
55 nand-on-flash-bbt;
56 status = "okay";
57
58 at91bootstrap@0 {
59 label = "at91bootstrap";
60 reg = <0x0 0x20000>;
61 };
62
63 barebox@20000 {
64 label = "barebox";
65 reg = <0x20000 0x40000>;
66 };
67
68 bareboxenv@60000 {
69 label = "bareboxenv";
70 reg = <0x60000 0x20000>;
71 };
72
73 bareboxenv2@80000 {
74 label = "bareboxenv2";
75 reg = <0x80000 0x20000>;
76 };
77
78 oftree@80000 {
79 label = "oftree";
80 reg = <0xa0000 0x20000>;
81 };
82
83 kernel@a0000 {
84 label = "kernel";
85 reg = <0xc0000 0x400000>;
86 };
87
88 rootfs@4a0000 {
89 label = "rootfs";
90 reg = <0x4c0000 0x7800000>;
91 };
92
93 data@7ca0000 {
94 label = "data";
95 reg = <0x7cc0000 0x8340000>;
96 };
97 };
98
99 usb0: ohci@00a00000 {
100 num-ports = <2>;
101 status = "okay";
102 };
103 };
104
105 leds {
106 compatible = "gpio-leds";
107
108 user_led {
109 label = "user_led";
110 gpios = <&pioB 21 0>;
111 linux,default-trigger = "heartbeat";
112 };
113 };
114
115 gpio_keys {
116 compatible = "gpio-keys";
117 #address-cells = <1>;
118 #size-cells = <0>;
119
120 user_pb {
121 label = "user_pb";
122 gpios = <&pioB 10 1>;
123 linux,code = <28>;
124 gpio-key,wakeup;
125 };
126 };
127
128 i2c@0 {
129 status = "okay";
130 };
131};
diff --git a/arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi b/arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi
deleted file mode 100644
index ad3eca17c43..00000000000
--- a/arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi
+++ /dev/null
@@ -1,96 +0,0 @@
1/*
2 * calao-dab-mmx.dtsi - Device Tree Include file for Calao DAB-MMX Daughter Board
3 *
4 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8
9/ {
10 ahb {
11 apb {
12 usart1: serial@fffb4000 {
13 status = "okay";
14 };
15
16 usart3: serial@fffd0000 {
17 status = "okay";
18 };
19 };
20 };
21
22 i2c-gpio@0 {
23 status = "okay";
24 };
25
26 leds {
27 compatible = "gpio-leds";
28
29 user_led1 {
30 label = "user_led1";
31 gpios = <&pioB 20 1>;
32 };
33
34/*
35* led already used by mother board but active as high
36* user_led2 {
37* label = "user_led2";
38* gpios = <&pioB 21 1>;
39* };
40*/
41 user_led3 {
42 label = "user_led3";
43 gpios = <&pioB 22 1>;
44 };
45
46 user_led4 {
47 label = "user_led4";
48 gpios = <&pioB 23 1>;
49 };
50
51 red {
52 label = "red";
53 gpios = <&pioB 24 1>;
54 };
55
56 orange {
57 label = "orange";
58 gpios = <&pioB 30 1>;
59 };
60
61 green {
62 label = "green";
63 gpios = <&pioB 31 1>;
64 };
65 };
66
67 gpio_keys {
68 compatible = "gpio-keys";
69 #address-cells = <1>;
70 #size-cells = <0>;
71
72 user_pb1 {
73 label = "user_pb1";
74 gpios = <&pioB 25 1>;
75 linux,code = <0x100>;
76 };
77
78 user_pb2 {
79 label = "user_pb2";
80 gpios = <&pioB 13 1>;
81 linux,code = <0x101>;
82 };
83
84 user_pb3 {
85 label = "user_pb3";
86 gpios = <&pioA 26 1>;
87 linux,code = <0x102>;
88 };
89
90 user_pb4 {
91 label = "user_pb4";
92 gpios = <&pioC 9 1>;
93 linux,code = <0x103>;
94 };
95 };
96};
diff --git a/arch/arm/boot/dts/usb_a9g20.dts b/arch/arm/boot/dts/usb_a9g20.dts
deleted file mode 100644
index 2dacb16ce4a..00000000000
--- a/arch/arm/boot/dts/usb_a9g20.dts
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * usb_a9g20.dts - Device Tree file for Caloa USB A9G20 board
3 *
4 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2 or later.
7 */
8/dts-v1/;
9/include/ "at91sam9g20.dtsi"
10/include/ "usb_a9260_common.dtsi"
11
12/ {
13 model = "Calao USB A9G20";
14 compatible = "calao,usb-a9g20", "atmel,at91sam9g20", "atmel,at91sam9";
15
16 chosen {
17 bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
18 };
19
20 memory {
21 reg = <0x20000000 0x4000000>;
22 };
23
24 i2c@0 {
25 rv3029c2@56 {
26 compatible = "rv3029c2";
27 reg = <0x56>;
28 };
29 };
30};
diff --git a/arch/arm/boot/dts/versatile-ab.dts b/arch/arm/boot/dts/versatile-ab.dts
index e2fe3195c0d..0b32925f214 100644
--- a/arch/arm/boot/dts/versatile-ab.dts
+++ b/arch/arm/boot/dts/versatile-ab.dts
@@ -173,7 +173,7 @@
173 mmc@5000 { 173 mmc@5000 {
174 compatible = "arm,primecell"; 174 compatible = "arm,primecell";
175 reg = < 0x5000 0x1000>; 175 reg = < 0x5000 0x1000>;
176 interrupts = <22 34>; 176 interrupts = <22>;
177 }; 177 };
178 kmi@6000 { 178 kmi@6000 {
179 compatible = "arm,pl050", "arm,primecell"; 179 compatible = "arm,pl050", "arm,primecell";
diff --git a/arch/arm/boot/dts/versatile-pb.dts b/arch/arm/boot/dts/versatile-pb.dts
index 7e817526906..8a614e39800 100644
--- a/arch/arm/boot/dts/versatile-pb.dts
+++ b/arch/arm/boot/dts/versatile-pb.dts
@@ -41,10 +41,8 @@
41 mmc@b000 { 41 mmc@b000 {
42 compatible = "arm,primecell"; 42 compatible = "arm,primecell";
43 reg = <0xb000 0x1000>; 43 reg = <0xb000 0x1000>;
44 interrupts = <23 34>; 44 interrupts = <23>;
45 }; 45 };
46 }; 46 };
47 }; 47 };
48}; 48};
49
50/include/ "testcases/tests.dtsi"
diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
deleted file mode 100644
index ac870fb3fa0..00000000000
--- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
+++ /dev/null
@@ -1,340 +0,0 @@
1/*
2 * ARM Ltd. Versatile Express
3 *
4 * Motherboard Express uATX
5 * V2M-P1
6 *
7 * HBI-0190D
8 *
9 * RS1 memory map ("ARM Cortex-A Series memory map" in the board's
10 * Technical Reference Manual)
11 *
12 * WARNING! The hardware described in this file is independent from the
13 * original variant (vexpress-v2m.dtsi), but there is a strong
14 * correspondence between the two configurations.
15 *
16 * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
17 * CHANGES TO vexpress-v2m.dtsi!
18 */
19
20 motherboard {
21 model = "V2M-P1";
22 arm,hbi = <0x190>;
23 arm,vexpress,site = <0>;
24 arm,v2m-memory-map = "rs1";
25 compatible = "arm,vexpress,v2m-p1", "simple-bus";
26 #address-cells = <2>; /* SMB chipselect number and offset */
27 #size-cells = <1>;
28 #interrupt-cells = <1>;
29 ranges;
30
31 flash@0,00000000 {
32 compatible = "arm,vexpress-flash", "cfi-flash";
33 reg = <0 0x00000000 0x04000000>,
34 <4 0x00000000 0x04000000>;
35 bank-width = <4>;
36 };
37
38 psram@1,00000000 {
39 compatible = "arm,vexpress-psram", "mtd-ram";
40 reg = <1 0x00000000 0x02000000>;
41 bank-width = <4>;
42 };
43
44 vram@2,00000000 {
45 compatible = "arm,vexpress-vram";
46 reg = <2 0x00000000 0x00800000>;
47 };
48
49 ethernet@2,02000000 {
50 compatible = "smsc,lan9118", "smsc,lan9115";
51 reg = <2 0x02000000 0x10000>;
52 interrupts = <15>;
53 phy-mode = "mii";
54 reg-io-width = <4>;
55 smsc,irq-active-high;
56 smsc,irq-push-pull;
57 vdd33a-supply = <&v2m_fixed_3v3>;
58 vddvario-supply = <&v2m_fixed_3v3>;
59 };
60
61 usb@2,03000000 {
62 compatible = "nxp,usb-isp1761";
63 reg = <2 0x03000000 0x20000>;
64 interrupts = <16>;
65 port1-otg;
66 };
67
68 iofpga@3,00000000 {
69 compatible = "arm,amba-bus", "simple-bus";
70 #address-cells = <1>;
71 #size-cells = <1>;
72 ranges = <0 3 0 0x200000>;
73
74 v2m_sysreg: sysreg@010000 {
75 compatible = "arm,vexpress-sysreg";
76 reg = <0x010000 0x1000>;
77 gpio-controller;
78 #gpio-cells = <2>;
79 };
80
81 v2m_sysctl: sysctl@020000 {
82 compatible = "arm,sp810", "arm,primecell";
83 reg = <0x020000 0x1000>;
84 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
85 clock-names = "refclk", "timclk", "apb_pclk";
86 #clock-cells = <1>;
87 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
88 };
89
90 /* PCI-E I2C bus */
91 v2m_i2c_pcie: i2c@030000 {
92 compatible = "arm,versatile-i2c";
93 reg = <0x030000 0x1000>;
94
95 #address-cells = <1>;
96 #size-cells = <0>;
97
98 pcie-switch@60 {
99 compatible = "idt,89hpes32h8";
100 reg = <0x60>;
101 };
102 };
103
104 aaci@040000 {
105 compatible = "arm,pl041", "arm,primecell";
106 reg = <0x040000 0x1000>;
107 interrupts = <11>;
108 clocks = <&smbclk>;
109 clock-names = "apb_pclk";
110 };
111
112 mmci@050000 {
113 compatible = "arm,pl180", "arm,primecell";
114 reg = <0x050000 0x1000>;
115 interrupts = <9 10>;
116 cd-gpios = <&v2m_sysreg 0 0>;
117 wp-gpios = <&v2m_sysreg 1 0>;
118 max-frequency = <12000000>;
119 vmmc-supply = <&v2m_fixed_3v3>;
120 clocks = <&v2m_clk24mhz>, <&smbclk>;
121 clock-names = "mclk", "apb_pclk";
122 };
123
124 kmi@060000 {
125 compatible = "arm,pl050", "arm,primecell";
126 reg = <0x060000 0x1000>;
127 interrupts = <12>;
128 clocks = <&v2m_clk24mhz>, <&smbclk>;
129 clock-names = "KMIREFCLK", "apb_pclk";
130 };
131
132 kmi@070000 {
133 compatible = "arm,pl050", "arm,primecell";
134 reg = <0x070000 0x1000>;
135 interrupts = <13>;
136 clocks = <&v2m_clk24mhz>, <&smbclk>;
137 clock-names = "KMIREFCLK", "apb_pclk";
138 };
139
140 v2m_serial0: uart@090000 {
141 compatible = "arm,pl011", "arm,primecell";
142 reg = <0x090000 0x1000>;
143 interrupts = <5>;
144 clocks = <&v2m_oscclk2>, <&smbclk>;
145 clock-names = "uartclk", "apb_pclk";
146 };
147
148 v2m_serial1: uart@0a0000 {
149 compatible = "arm,pl011", "arm,primecell";
150 reg = <0x0a0000 0x1000>;
151 interrupts = <6>;
152 clocks = <&v2m_oscclk2>, <&smbclk>;
153 clock-names = "uartclk", "apb_pclk";
154 };
155
156 v2m_serial2: uart@0b0000 {
157 compatible = "arm,pl011", "arm,primecell";
158 reg = <0x0b0000 0x1000>;
159 interrupts = <7>;
160 clocks = <&v2m_oscclk2>, <&smbclk>;
161 clock-names = "uartclk", "apb_pclk";
162 };
163
164 v2m_serial3: uart@0c0000 {
165 compatible = "arm,pl011", "arm,primecell";
166 reg = <0x0c0000 0x1000>;
167 interrupts = <8>;
168 clocks = <&v2m_oscclk2>, <&smbclk>;
169 clock-names = "uartclk", "apb_pclk";
170 };
171
172 wdt@0f0000 {
173 compatible = "arm,sp805", "arm,primecell";
174 reg = <0x0f0000 0x1000>;
175 interrupts = <0>;
176 clocks = <&v2m_refclk32khz>, <&smbclk>;
177 clock-names = "wdogclk", "apb_pclk";
178 };
179
180 v2m_timer01: timer@110000 {
181 compatible = "arm,sp804", "arm,primecell";
182 reg = <0x110000 0x1000>;
183 interrupts = <2>;
184 clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
185 clock-names = "timclken1", "timclken2", "apb_pclk";
186 };
187
188 v2m_timer23: timer@120000 {
189 compatible = "arm,sp804", "arm,primecell";
190 reg = <0x120000 0x1000>;
191 interrupts = <3>;
192 clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
193 clock-names = "timclken1", "timclken2", "apb_pclk";
194 };
195
196 /* DVI I2C bus */
197 v2m_i2c_dvi: i2c@160000 {
198 compatible = "arm,versatile-i2c";
199 reg = <0x160000 0x1000>;
200
201 #address-cells = <1>;
202 #size-cells = <0>;
203
204 dvi-transmitter@39 {
205 compatible = "sil,sii9022-tpi", "sil,sii9022";
206 reg = <0x39>;
207 };
208
209 dvi-transmitter@60 {
210 compatible = "sil,sii9022-cpi", "sil,sii9022";
211 reg = <0x60>;
212 };
213 };
214
215 rtc@170000 {
216 compatible = "arm,pl031", "arm,primecell";
217 reg = <0x170000 0x1000>;
218 interrupts = <4>;
219 clocks = <&smbclk>;
220 clock-names = "apb_pclk";
221 };
222
223 compact-flash@1a0000 {
224 compatible = "arm,vexpress-cf", "ata-generic";
225 reg = <0x1a0000 0x100
226 0x1a0100 0xf00>;
227 reg-shift = <2>;
228 };
229
230 clcd@1f0000 {
231 compatible = "arm,pl111", "arm,primecell";
232 reg = <0x1f0000 0x1000>;
233 interrupts = <14>;
234 clocks = <&v2m_oscclk1>, <&smbclk>;
235 clock-names = "clcdclk", "apb_pclk";
236 };
237 };
238
239 v2m_fixed_3v3: fixedregulator@0 {
240 compatible = "regulator-fixed";
241 regulator-name = "3V3";
242 regulator-min-microvolt = <3300000>;
243 regulator-max-microvolt = <3300000>;
244 regulator-always-on;
245 };
246
247 v2m_clk24mhz: clk24mhz {
248 compatible = "fixed-clock";
249 #clock-cells = <0>;
250 clock-frequency = <24000000>;
251 clock-output-names = "v2m:clk24mhz";
252 };
253
254 v2m_refclk1mhz: refclk1mhz {
255 compatible = "fixed-clock";
256 #clock-cells = <0>;
257 clock-frequency = <1000000>;
258 clock-output-names = "v2m:refclk1mhz";
259 };
260
261 v2m_refclk32khz: refclk32khz {
262 compatible = "fixed-clock";
263 #clock-cells = <0>;
264 clock-frequency = <32768>;
265 clock-output-names = "v2m:refclk32khz";
266 };
267
268 mcc {
269 compatible = "arm,vexpress,config-bus";
270 arm,vexpress,config-bridge = <&v2m_sysreg>;
271
272 osc@0 {
273 /* MCC static memory clock */
274 compatible = "arm,vexpress-osc";
275 arm,vexpress-sysreg,func = <1 0>;
276 freq-range = <25000000 60000000>;
277 #clock-cells = <0>;
278 clock-output-names = "v2m:oscclk0";
279 };
280
281 v2m_oscclk1: osc@1 {
282 /* CLCD clock */
283 compatible = "arm,vexpress-osc";
284 arm,vexpress-sysreg,func = <1 1>;
285 freq-range = <23750000 63500000>;
286 #clock-cells = <0>;
287 clock-output-names = "v2m:oscclk1";
288 };
289
290 v2m_oscclk2: osc@2 {
291 /* IO FPGA peripheral clock */
292 compatible = "arm,vexpress-osc";
293 arm,vexpress-sysreg,func = <1 2>;
294 freq-range = <24000000 24000000>;
295 #clock-cells = <0>;
296 clock-output-names = "v2m:oscclk2";
297 };
298
299 volt@0 {
300 /* Logic level voltage */
301 compatible = "arm,vexpress-volt";
302 arm,vexpress-sysreg,func = <2 0>;
303 regulator-name = "VIO";
304 regulator-always-on;
305 label = "VIO";
306 };
307
308 temp@0 {
309 /* MCC internal operating temperature */
310 compatible = "arm,vexpress-temp";
311 arm,vexpress-sysreg,func = <4 0>;
312 label = "MCC";
313 };
314
315 reset@0 {
316 compatible = "arm,vexpress-reset";
317 arm,vexpress-sysreg,func = <5 0>;
318 };
319
320 muxfpga@0 {
321 compatible = "arm,vexpress-muxfpga";
322 arm,vexpress-sysreg,func = <7 0>;
323 };
324
325 shutdown@0 {
326 compatible = "arm,vexpress-shutdown";
327 arm,vexpress-sysreg,func = <8 0>;
328 };
329
330 reboot@0 {
331 compatible = "arm,vexpress-reboot";
332 arm,vexpress-sysreg,func = <9 0>;
333 };
334
335 dvimode@0 {
336 compatible = "arm,vexpress-dvimode";
337 arm,vexpress-sysreg,func = <11 0>;
338 };
339 };
340 };
diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi
deleted file mode 100644
index f1420368355..00000000000
--- a/arch/arm/boot/dts/vexpress-v2m.dtsi
+++ /dev/null
@@ -1,339 +0,0 @@
1/*
2 * ARM Ltd. Versatile Express
3 *
4 * Motherboard Express uATX
5 * V2M-P1
6 *
7 * HBI-0190D
8 *
9 * Original memory map ("Legacy memory map" in the board's
10 * Technical Reference Manual)
11 *
12 * WARNING! The hardware described in this file is independent from the
13 * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
14 * correspondence between the two configurations.
15 *
16 * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
17 * CHANGES TO vexpress-v2m-rs1.dtsi!
18 */
19
20 motherboard {
21 model = "V2M-P1";
22 arm,hbi = <0x190>;
23 arm,vexpress,site = <0>;
24 compatible = "arm,vexpress,v2m-p1", "simple-bus";
25 #address-cells = <2>; /* SMB chipselect number and offset */
26 #size-cells = <1>;
27 #interrupt-cells = <1>;
28 ranges;
29
30 flash@0,00000000 {
31 compatible = "arm,vexpress-flash", "cfi-flash";
32 reg = <0 0x00000000 0x04000000>,
33 <1 0x00000000 0x04000000>;
34 bank-width = <4>;
35 };
36
37 psram@2,00000000 {
38 compatible = "arm,vexpress-psram", "mtd-ram";
39 reg = <2 0x00000000 0x02000000>;
40 bank-width = <4>;
41 };
42
43 vram@3,00000000 {
44 compatible = "arm,vexpress-vram";
45 reg = <3 0x00000000 0x00800000>;
46 };
47
48 ethernet@3,02000000 {
49 compatible = "smsc,lan9118", "smsc,lan9115";
50 reg = <3 0x02000000 0x10000>;
51 interrupts = <15>;
52 phy-mode = "mii";
53 reg-io-width = <4>;
54 smsc,irq-active-high;
55 smsc,irq-push-pull;
56 vdd33a-supply = <&v2m_fixed_3v3>;
57 vddvario-supply = <&v2m_fixed_3v3>;
58 };
59
60 usb@3,03000000 {
61 compatible = "nxp,usb-isp1761";
62 reg = <3 0x03000000 0x20000>;
63 interrupts = <16>;
64 port1-otg;
65 };
66
67 iofpga@7,00000000 {
68 compatible = "arm,amba-bus", "simple-bus";
69 #address-cells = <1>;
70 #size-cells = <1>;
71 ranges = <0 7 0 0x20000>;
72
73 v2m_sysreg: sysreg@00000 {
74 compatible = "arm,vexpress-sysreg";
75 reg = <0x00000 0x1000>;
76 gpio-controller;
77 #gpio-cells = <2>;
78 };
79
80 v2m_sysctl: sysctl@01000 {
81 compatible = "arm,sp810", "arm,primecell";
82 reg = <0x01000 0x1000>;
83 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
84 clock-names = "refclk", "timclk", "apb_pclk";
85 #clock-cells = <1>;
86 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
87 };
88
89 /* PCI-E I2C bus */
90 v2m_i2c_pcie: i2c@02000 {
91 compatible = "arm,versatile-i2c";
92 reg = <0x02000 0x1000>;
93
94 #address-cells = <1>;
95 #size-cells = <0>;
96
97 pcie-switch@60 {
98 compatible = "idt,89hpes32h8";
99 reg = <0x60>;
100 };
101 };
102
103 aaci@04000 {
104 compatible = "arm,pl041", "arm,primecell";
105 reg = <0x04000 0x1000>;
106 interrupts = <11>;
107 clocks = <&smbclk>;
108 clock-names = "apb_pclk";
109 };
110
111 mmci@05000 {
112 compatible = "arm,pl180", "arm,primecell";
113 reg = <0x05000 0x1000>;
114 interrupts = <9 10>;
115 cd-gpios = <&v2m_sysreg 0 0>;
116 wp-gpios = <&v2m_sysreg 1 0>;
117 max-frequency = <12000000>;
118 vmmc-supply = <&v2m_fixed_3v3>;
119 clocks = <&v2m_clk24mhz>, <&smbclk>;
120 clock-names = "mclk", "apb_pclk";
121 };
122
123 kmi@06000 {
124 compatible = "arm,pl050", "arm,primecell";
125 reg = <0x06000 0x1000>;
126 interrupts = <12>;
127 clocks = <&v2m_clk24mhz>, <&smbclk>;
128 clock-names = "KMIREFCLK", "apb_pclk";
129 };
130
131 kmi@07000 {
132 compatible = "arm,pl050", "arm,primecell";
133 reg = <0x07000 0x1000>;
134 interrupts = <13>;
135 clocks = <&v2m_clk24mhz>, <&smbclk>;
136 clock-names = "KMIREFCLK", "apb_pclk";
137 };
138
139 v2m_serial0: uart@09000 {
140 compatible = "arm,pl011", "arm,primecell";
141 reg = <0x09000 0x1000>;
142 interrupts = <5>;
143 clocks = <&v2m_oscclk2>, <&smbclk>;
144 clock-names = "uartclk", "apb_pclk";
145 };
146
147 v2m_serial1: uart@0a000 {
148 compatible = "arm,pl011", "arm,primecell";
149 reg = <0x0a000 0x1000>;
150 interrupts = <6>;
151 clocks = <&v2m_oscclk2>, <&smbclk>;
152 clock-names = "uartclk", "apb_pclk";
153 };
154
155 v2m_serial2: uart@0b000 {
156 compatible = "arm,pl011", "arm,primecell";
157 reg = <0x0b000 0x1000>;
158 interrupts = <7>;
159 clocks = <&v2m_oscclk2>, <&smbclk>;
160 clock-names = "uartclk", "apb_pclk";
161 };
162
163 v2m_serial3: uart@0c000 {
164 compatible = "arm,pl011", "arm,primecell";
165 reg = <0x0c000 0x1000>;
166 interrupts = <8>;
167 clocks = <&v2m_oscclk2>, <&smbclk>;
168 clock-names = "uartclk", "apb_pclk";
169 };
170
171 wdt@0f000 {
172 compatible = "arm,sp805", "arm,primecell";
173 reg = <0x0f000 0x1000>;
174 interrupts = <0>;
175 clocks = <&v2m_refclk32khz>, <&smbclk>;
176 clock-names = "wdogclk", "apb_pclk";
177 };
178
179 v2m_timer01: timer@11000 {
180 compatible = "arm,sp804", "arm,primecell";
181 reg = <0x11000 0x1000>;
182 interrupts = <2>;
183 clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
184 clock-names = "timclken1", "timclken2", "apb_pclk";
185 };
186
187 v2m_timer23: timer@12000 {
188 compatible = "arm,sp804", "arm,primecell";
189 reg = <0x12000 0x1000>;
190 interrupts = <3>;
191 clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
192 clock-names = "timclken1", "timclken2", "apb_pclk";
193 };
194
195 /* DVI I2C bus */
196 v2m_i2c_dvi: i2c@16000 {
197 compatible = "arm,versatile-i2c";
198 reg = <0x16000 0x1000>;
199
200 #address-cells = <1>;
201 #size-cells = <0>;
202
203 dvi-transmitter@39 {
204 compatible = "sil,sii9022-tpi", "sil,sii9022";
205 reg = <0x39>;
206 };
207
208 dvi-transmitter@60 {
209 compatible = "sil,sii9022-cpi", "sil,sii9022";
210 reg = <0x60>;
211 };
212 };
213
214 rtc@17000 {
215 compatible = "arm,pl031", "arm,primecell";
216 reg = <0x17000 0x1000>;
217 interrupts = <4>;
218 clocks = <&smbclk>;
219 clock-names = "apb_pclk";
220 };
221
222 compact-flash@1a000 {
223 compatible = "arm,vexpress-cf", "ata-generic";
224 reg = <0x1a000 0x100
225 0x1a100 0xf00>;
226 reg-shift = <2>;
227 };
228
229 clcd@1f000 {
230 compatible = "arm,pl111", "arm,primecell";
231 reg = <0x1f000 0x1000>;
232 interrupts = <14>;
233 clocks = <&v2m_oscclk1>, <&smbclk>;
234 clock-names = "clcdclk", "apb_pclk";
235 };
236 };
237
238 v2m_fixed_3v3: fixedregulator@0 {
239 compatible = "regulator-fixed";
240 regulator-name = "3V3";
241 regulator-min-microvolt = <3300000>;
242 regulator-max-microvolt = <3300000>;
243 regulator-always-on;
244 };
245
246 v2m_clk24mhz: clk24mhz {
247 compatible = "fixed-clock";
248 #clock-cells = <0>;
249 clock-frequency = <24000000>;
250 clock-output-names = "v2m:clk24mhz";
251 };
252
253 v2m_refclk1mhz: refclk1mhz {
254 compatible = "fixed-clock";
255 #clock-cells = <0>;
256 clock-frequency = <1000000>;
257 clock-output-names = "v2m:refclk1mhz";
258 };
259
260 v2m_refclk32khz: refclk32khz {
261 compatible = "fixed-clock";
262 #clock-cells = <0>;
263 clock-frequency = <32768>;
264 clock-output-names = "v2m:refclk32khz";
265 };
266
267 mcc {
268 compatible = "arm,vexpress,config-bus";
269 arm,vexpress,config-bridge = <&v2m_sysreg>;
270
271 osc@0 {
272 /* MCC static memory clock */
273 compatible = "arm,vexpress-osc";
274 arm,vexpress-sysreg,func = <1 0>;
275 freq-range = <25000000 60000000>;
276 #clock-cells = <0>;
277 clock-output-names = "v2m:oscclk0";
278 };
279
280 v2m_oscclk1: osc@1 {
281 /* CLCD clock */
282 compatible = "arm,vexpress-osc";
283 arm,vexpress-sysreg,func = <1 1>;
284 freq-range = <23750000 63500000>;
285 #clock-cells = <0>;
286 clock-output-names = "v2m:oscclk1";
287 };
288
289 v2m_oscclk2: osc@2 {
290 /* IO FPGA peripheral clock */
291 compatible = "arm,vexpress-osc";
292 arm,vexpress-sysreg,func = <1 2>;
293 freq-range = <24000000 24000000>;
294 #clock-cells = <0>;
295 clock-output-names = "v2m:oscclk2";
296 };
297
298 volt@0 {
299 /* Logic level voltage */
300 compatible = "arm,vexpress-volt";
301 arm,vexpress-sysreg,func = <2 0>;
302 regulator-name = "VIO";
303 regulator-always-on;
304 label = "VIO";
305 };
306
307 temp@0 {
308 /* MCC internal operating temperature */
309 compatible = "arm,vexpress-temp";
310 arm,vexpress-sysreg,func = <4 0>;
311 label = "MCC";
312 };
313
314 reset@0 {
315 compatible = "arm,vexpress-reset";
316 arm,vexpress-sysreg,func = <5 0>;
317 };
318
319 muxfpga@0 {
320 compatible = "arm,vexpress-muxfpga";
321 arm,vexpress-sysreg,func = <7 0>;
322 };
323
324 shutdown@0 {
325 compatible = "arm,vexpress-shutdown";
326 arm,vexpress-sysreg,func = <8 0>;
327 };
328
329 reboot@0 {
330 compatible = "arm,vexpress-reboot";
331 arm,vexpress-sysreg,func = <9 0>;
332 };
333
334 dvimode@0 {
335 compatible = "arm,vexpress-dvimode";
336 arm,vexpress-sysreg,func = <11 0>;
337 };
338 };
339 };
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
deleted file mode 100644
index a3d37ec2655..00000000000
--- a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
+++ /dev/null
@@ -1,283 +0,0 @@
1/*
2 * ARM Ltd. Versatile Express
3 *
4 * CoreTile Express A15x2 (version with Test Chip 1)
5 * Cortex-A15 MPCore (V2P-CA15)
6 *
7 * HBI-0237A
8 */
9
10/dts-v1/;
11
12/ {
13 model = "V2P-CA15";
14 arm,hbi = <0x237>;
15 arm,vexpress,site = <0xf>;
16 compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 chosen { };
22
23 aliases {
24 serial0 = &v2m_serial0;
25 serial1 = &v2m_serial1;
26 serial2 = &v2m_serial2;
27 serial3 = &v2m_serial3;
28 i2c0 = &v2m_i2c_dvi;
29 i2c1 = &v2m_i2c_pcie;
30 };
31
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 cpu@0 {
37 device_type = "cpu";
38 compatible = "arm,cortex-a15";
39 reg = <0>;
40 };
41
42 cpu@1 {
43 device_type = "cpu";
44 compatible = "arm,cortex-a15";
45 reg = <1>;
46 };
47 };
48
49 memory@80000000 {
50 device_type = "memory";
51 reg = <0 0x80000000 0 0x40000000>;
52 };
53
54 hdlcd@2b000000 {
55 compatible = "arm,hdlcd";
56 reg = <0 0x2b000000 0 0x1000>;
57 interrupts = <0 85 4>;
58 clocks = <&oscclk5>;
59 clock-names = "pxlclk";
60 };
61
62 memory-controller@2b0a0000 {
63 compatible = "arm,pl341", "arm,primecell";
64 reg = <0 0x2b0a0000 0 0x1000>;
65 clocks = <&oscclk7>;
66 clock-names = "apb_pclk";
67 };
68
69 wdt@2b060000 {
70 compatible = "arm,sp805", "arm,primecell";
71 status = "disabled";
72 reg = <0 0x2b060000 0 0x1000>;
73 interrupts = <98>;
74 clocks = <&oscclk7>;
75 clock-names = "apb_pclk";
76 };
77
78 gic: interrupt-controller@2c001000 {
79 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
80 #interrupt-cells = <3>;
81 #address-cells = <0>;
82 interrupt-controller;
83 reg = <0 0x2c001000 0 0x1000>,
84 <0 0x2c002000 0 0x1000>,
85 <0 0x2c004000 0 0x2000>,
86 <0 0x2c006000 0 0x2000>;
87 interrupts = <1 9 0xf04>;
88 };
89
90 memory-controller@7ffd0000 {
91 compatible = "arm,pl354", "arm,primecell";
92 reg = <0 0x7ffd0000 0 0x1000>;
93 interrupts = <0 86 4>,
94 <0 87 4>;
95 clocks = <&oscclk7>;
96 clock-names = "apb_pclk";
97 };
98
99 dma@7ffb0000 {
100 compatible = "arm,pl330", "arm,primecell";
101 reg = <0 0x7ffb0000 0 0x1000>;
102 interrupts = <0 92 4>,
103 <0 88 4>,
104 <0 89 4>,
105 <0 90 4>,
106 <0 91 4>;
107 clocks = <&oscclk7>;
108 clock-names = "apb_pclk";
109 };
110
111 timer {
112 compatible = "arm,armv7-timer";
113 interrupts = <1 13 0xf08>,
114 <1 14 0xf08>,
115 <1 11 0xf08>,
116 <1 10 0xf08>;
117 };
118
119 pmu {
120 compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
121 interrupts = <0 68 4>,
122 <0 69 4>;
123 };
124
125 dcc {
126 compatible = "arm,vexpress,config-bus";
127 arm,vexpress,config-bridge = <&v2m_sysreg>;
128
129 osc@0 {
130 /* CPU PLL reference clock */
131 compatible = "arm,vexpress-osc";
132 arm,vexpress-sysreg,func = <1 0>;
133 freq-range = <50000000 60000000>;
134 #clock-cells = <0>;
135 clock-output-names = "oscclk0";
136 };
137
138 osc@4 {
139 /* Multiplexed AXI master clock */
140 compatible = "arm,vexpress-osc";
141 arm,vexpress-sysreg,func = <1 4>;
142 freq-range = <20000000 40000000>;
143 #clock-cells = <0>;
144 clock-output-names = "oscclk4";
145 };
146
147 oscclk5: osc@5 {
148 /* HDLCD PLL reference clock */
149 compatible = "arm,vexpress-osc";
150 arm,vexpress-sysreg,func = <1 5>;
151 freq-range = <23750000 165000000>;
152 #clock-cells = <0>;
153 clock-output-names = "oscclk5";
154 };
155
156 smbclk: osc@6 {
157 /* SMB clock */
158 compatible = "arm,vexpress-osc";
159 arm,vexpress-sysreg,func = <1 6>;
160 freq-range = <20000000 50000000>;
161 #clock-cells = <0>;
162 clock-output-names = "oscclk6";
163 };
164
165 oscclk7: osc@7 {
166 /* SYS PLL reference clock */
167 compatible = "arm,vexpress-osc";
168 arm,vexpress-sysreg,func = <1 7>;
169 freq-range = <20000000 60000000>;
170 #clock-cells = <0>;
171 clock-output-names = "oscclk7";
172 };
173
174 osc@8 {
175 /* DDR2 PLL reference clock */
176 compatible = "arm,vexpress-osc";
177 arm,vexpress-sysreg,func = <1 8>;
178 freq-range = <40000000 40000000>;
179 #clock-cells = <0>;
180 clock-output-names = "oscclk8";
181 };
182
183 volt@0 {
184 /* CPU core voltage */
185 compatible = "arm,vexpress-volt";
186 arm,vexpress-sysreg,func = <2 0>;
187 regulator-name = "Cores";
188 regulator-min-microvolt = <800000>;
189 regulator-max-microvolt = <1050000>;
190 regulator-always-on;
191 label = "Cores";
192 };
193
194 amp@0 {
195 /* Total current for the two cores */
196 compatible = "arm,vexpress-amp";
197 arm,vexpress-sysreg,func = <3 0>;
198 label = "Cores";
199 };
200
201 temp@0 {
202 /* DCC internal temperature */
203 compatible = "arm,vexpress-temp";
204 arm,vexpress-sysreg,func = <4 0>;
205 label = "DCC";
206 };
207
208 power@0 {
209 /* Total power */
210 compatible = "arm,vexpress-power";
211 arm,vexpress-sysreg,func = <12 0>;
212 label = "Cores";
213 };
214
215 energy@0 {
216 /* Total energy */
217 compatible = "arm,vexpress-energy";
218 arm,vexpress-sysreg,func = <13 0>;
219 label = "Cores";
220 };
221 };
222
223 smb {
224 compatible = "simple-bus";
225
226 #address-cells = <2>;
227 #size-cells = <1>;
228 ranges = <0 0 0 0x08000000 0x04000000>,
229 <1 0 0 0x14000000 0x04000000>,
230 <2 0 0 0x18000000 0x04000000>,
231 <3 0 0 0x1c000000 0x04000000>,
232 <4 0 0 0x0c000000 0x04000000>,
233 <5 0 0 0x10000000 0x04000000>;
234
235 #interrupt-cells = <1>;
236 interrupt-map-mask = <0 0 63>;
237 interrupt-map = <0 0 0 &gic 0 0 4>,
238 <0 0 1 &gic 0 1 4>,
239 <0 0 2 &gic 0 2 4>,
240 <0 0 3 &gic 0 3 4>,
241 <0 0 4 &gic 0 4 4>,
242 <0 0 5 &gic 0 5 4>,
243 <0 0 6 &gic 0 6 4>,
244 <0 0 7 &gic 0 7 4>,
245 <0 0 8 &gic 0 8 4>,
246 <0 0 9 &gic 0 9 4>,
247 <0 0 10 &gic 0 10 4>,
248 <0 0 11 &gic 0 11 4>,
249 <0 0 12 &gic 0 12 4>,
250 <0 0 13 &gic 0 13 4>,
251 <0 0 14 &gic 0 14 4>,
252 <0 0 15 &gic 0 15 4>,
253 <0 0 16 &gic 0 16 4>,
254 <0 0 17 &gic 0 17 4>,
255 <0 0 18 &gic 0 18 4>,
256 <0 0 19 &gic 0 19 4>,
257 <0 0 20 &gic 0 20 4>,
258 <0 0 21 &gic 0 21 4>,
259 <0 0 22 &gic 0 22 4>,
260 <0 0 23 &gic 0 23 4>,
261 <0 0 24 &gic 0 24 4>,
262 <0 0 25 &gic 0 25 4>,
263 <0 0 26 &gic 0 26 4>,
264 <0 0 27 &gic 0 27 4>,
265 <0 0 28 &gic 0 28 4>,
266 <0 0 29 &gic 0 29 4>,
267 <0 0 30 &gic 0 30 4>,
268 <0 0 31 &gic 0 31 4>,
269 <0 0 32 &gic 0 32 4>,
270 <0 0 33 &gic 0 33 4>,
271 <0 0 34 &gic 0 34 4>,
272 <0 0 35 &gic 0 35 4>,
273 <0 0 36 &gic 0 36 4>,
274 <0 0 37 &gic 0 37 4>,
275 <0 0 38 &gic 0 38 4>,
276 <0 0 39 &gic 0 39 4>,
277 <0 0 40 &gic 0 40 4>,
278 <0 0 41 &gic 0 41 4>,
279 <0 0 42 &gic 0 42 4>;
280
281 /include/ "vexpress-v2m-rs1.dtsi"
282 };
283};
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
deleted file mode 100644
index 1fc405a9ecf..00000000000
--- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+++ /dev/null
@@ -1,368 +0,0 @@
1/*
2 * ARM Ltd. Versatile Express
3 *
4 * CoreTile Express A15x2 A7x3
5 * Cortex-A15_A7 MPCore (V2P-CA15_A7)
6 *
7 * HBI-0249A
8 */
9
10/dts-v1/;
11
12/ {
13 model = "V2P-CA15_CA7";
14 arm,hbi = <0x249>;
15 arm,vexpress,site = <0xf>;
16 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 chosen { };
22
23 aliases {
24 serial0 = &v2m_serial0;
25 serial1 = &v2m_serial1;
26 serial2 = &v2m_serial2;
27 serial3 = &v2m_serial3;
28 i2c0 = &v2m_i2c_dvi;
29 i2c1 = &v2m_i2c_pcie;
30 };
31
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 cpu0: cpu@0 {
37 device_type = "cpu";
38 compatible = "arm,cortex-a15";
39 reg = <0>;
40 };
41
42 cpu1: cpu@1 {
43 device_type = "cpu";
44 compatible = "arm,cortex-a15";
45 reg = <1>;
46 };
47
48/* A7s disabled till big.LITTLE patches are available...
49 cpu2: cpu@2 {
50 device_type = "cpu";
51 compatible = "arm,cortex-a7";
52 reg = <0x100>;
53 };
54
55 cpu3: cpu@3 {
56 device_type = "cpu";
57 compatible = "arm,cortex-a7";
58 reg = <0x101>;
59 };
60
61 cpu4: cpu@4 {
62 device_type = "cpu";
63 compatible = "arm,cortex-a7";
64 reg = <0x102>;
65 };
66*/
67 };
68
69 memory@80000000 {
70 device_type = "memory";
71 reg = <0 0x80000000 0 0x40000000>;
72 };
73
74 wdt@2a490000 {
75 compatible = "arm,sp805", "arm,primecell";
76 reg = <0 0x2a490000 0 0x1000>;
77 interrupts = <98>;
78 clocks = <&oscclk6a>, <&oscclk6a>;
79 clock-names = "wdogclk", "apb_pclk";
80 };
81
82 hdlcd@2b000000 {
83 compatible = "arm,hdlcd";
84 reg = <0 0x2b000000 0 0x1000>;
85 interrupts = <0 85 4>;
86 clocks = <&oscclk5>;
87 clock-names = "pxlclk";
88 };
89
90 memory-controller@2b0a0000 {
91 compatible = "arm,pl341", "arm,primecell";
92 reg = <0 0x2b0a0000 0 0x1000>;
93 clocks = <&oscclk6a>;
94 clock-names = "apb_pclk";
95 };
96
97 gic: interrupt-controller@2c001000 {
98 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
99 #interrupt-cells = <3>;
100 #address-cells = <0>;
101 interrupt-controller;
102 reg = <0 0x2c001000 0 0x1000>,
103 <0 0x2c002000 0 0x1000>,
104 <0 0x2c004000 0 0x2000>,
105 <0 0x2c006000 0 0x2000>;
106 interrupts = <1 9 0xf04>;
107 };
108
109 memory-controller@7ffd0000 {
110 compatible = "arm,pl354", "arm,primecell";
111 reg = <0 0x7ffd0000 0 0x1000>;
112 interrupts = <0 86 4>,
113 <0 87 4>;
114 clocks = <&oscclk6a>;
115 clock-names = "apb_pclk";
116 };
117
118 dma@7ff00000 {
119 compatible = "arm,pl330", "arm,primecell";
120 reg = <0 0x7ff00000 0 0x1000>;
121 interrupts = <0 92 4>,
122 <0 88 4>,
123 <0 89 4>,
124 <0 90 4>,
125 <0 91 4>;
126 clocks = <&oscclk6a>;
127 clock-names = "apb_pclk";
128 };
129
130 timer {
131 compatible = "arm,armv7-timer";
132 interrupts = <1 13 0xf08>,
133 <1 14 0xf08>,
134 <1 11 0xf08>,
135 <1 10 0xf08>;
136 };
137
138 pmu {
139 compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
140 interrupts = <0 68 4>,
141 <0 69 4>;
142 };
143
144 oscclk6a: oscclk6a {
145 /* Reference 24MHz clock */
146 compatible = "fixed-clock";
147 #clock-cells = <0>;
148 clock-frequency = <24000000>;
149 clock-output-names = "oscclk6a";
150 };
151
152 dcc {
153 compatible = "arm,vexpress,config-bus";
154 arm,vexpress,config-bridge = <&v2m_sysreg>;
155
156 osc@0 {
157 /* A15 PLL 0 reference clock */
158 compatible = "arm,vexpress-osc";
159 arm,vexpress-sysreg,func = <1 0>;
160 freq-range = <17000000 50000000>;
161 #clock-cells = <0>;
162 clock-output-names = "oscclk0";
163 };
164
165 osc@1 {
166 /* A15 PLL 1 reference clock */
167 compatible = "arm,vexpress-osc";
168 arm,vexpress-sysreg,func = <1 1>;
169 freq-range = <17000000 50000000>;
170 #clock-cells = <0>;
171 clock-output-names = "oscclk1";
172 };
173
174 osc@2 {
175 /* A7 PLL 0 reference clock */
176 compatible = "arm,vexpress-osc";
177 arm,vexpress-sysreg,func = <1 2>;
178 freq-range = <17000000 50000000>;
179 #clock-cells = <0>;
180 clock-output-names = "oscclk2";
181 };
182
183 osc@3 {
184 /* A7 PLL 1 reference clock */
185 compatible = "arm,vexpress-osc";
186 arm,vexpress-sysreg,func = <1 3>;
187 freq-range = <17000000 50000000>;
188 #clock-cells = <0>;
189 clock-output-names = "oscclk3";
190 };
191
192 osc@4 {
193 /* External AXI master clock */
194 compatible = "arm,vexpress-osc";
195 arm,vexpress-sysreg,func = <1 4>;
196 freq-range = <20000000 40000000>;
197 #clock-cells = <0>;
198 clock-output-names = "oscclk4";
199 };
200
201 oscclk5: osc@5 {
202 /* HDLCD PLL reference clock */
203 compatible = "arm,vexpress-osc";
204 arm,vexpress-sysreg,func = <1 5>;
205 freq-range = <23750000 165000000>;
206 #clock-cells = <0>;
207 clock-output-names = "oscclk5";
208 };
209
210 smbclk: osc@6 {
211 /* Static memory controller clock */
212 compatible = "arm,vexpress-osc";
213 arm,vexpress-sysreg,func = <1 6>;
214 freq-range = <20000000 40000000>;
215 #clock-cells = <0>;
216 clock-output-names = "oscclk6";
217 };
218
219 osc@7 {
220 /* SYS PLL reference clock */
221 compatible = "arm,vexpress-osc";
222 arm,vexpress-sysreg,func = <1 7>;
223 freq-range = <17000000 50000000>;
224 #clock-cells = <0>;
225 clock-output-names = "oscclk7";
226 };
227
228 osc@8 {
229 /* DDR2 PLL reference clock */
230 compatible = "arm,vexpress-osc";
231 arm,vexpress-sysreg,func = <1 8>;
232 freq-range = <20000000 50000000>;
233 #clock-cells = <0>;
234 clock-output-names = "oscclk8";
235 };
236
237 volt@0 {
238 /* A15 CPU core voltage */
239 compatible = "arm,vexpress-volt";
240 arm,vexpress-sysreg,func = <2 0>;
241 regulator-name = "A15 Vcore";
242 regulator-min-microvolt = <800000>;
243 regulator-max-microvolt = <1050000>;
244 regulator-always-on;
245 label = "A15 Vcore";
246 };
247
248 volt@1 {
249 /* A7 CPU core voltage */
250 compatible = "arm,vexpress-volt";
251 arm,vexpress-sysreg,func = <2 1>;
252 regulator-name = "A7 Vcore";
253 regulator-min-microvolt = <800000>;
254 regulator-max-microvolt = <1050000>;
255 regulator-always-on;
256 label = "A7 Vcore";
257 };
258
259 amp@0 {
260 /* Total current for the two A15 cores */
261 compatible = "arm,vexpress-amp";
262 arm,vexpress-sysreg,func = <3 0>;
263 label = "A15 Icore";
264 };
265
266 amp@1 {
267 /* Total current for the three A7 cores */
268 compatible = "arm,vexpress-amp";
269 arm,vexpress-sysreg,func = <3 1>;
270 label = "A7 Icore";
271 };
272
273 temp@0 {
274 /* DCC internal temperature */
275 compatible = "arm,vexpress-temp";
276 arm,vexpress-sysreg,func = <4 0>;
277 label = "DCC";
278 };
279
280 power@0 {
281 /* Total power for the two A15 cores */
282 compatible = "arm,vexpress-power";
283 arm,vexpress-sysreg,func = <12 0>;
284 label = "A15 Pcore";
285 };
286 power@1 {
287 /* Total power for the three A7 cores */
288 compatible = "arm,vexpress-power";
289 arm,vexpress-sysreg,func = <12 1>;
290 label = "A7 Pcore";
291 };
292
293 energy@0 {
294 /* Total energy for the two A15 cores */
295 compatible = "arm,vexpress-energy";
296 arm,vexpress-sysreg,func = <13 0>;
297 label = "A15 Jcore";
298 };
299
300 energy@2 {
301 /* Total energy for the three A7 cores */
302 compatible = "arm,vexpress-energy";
303 arm,vexpress-sysreg,func = <13 2>;
304 label = "A7 Jcore";
305 };
306 };
307
308 smb {
309 compatible = "simple-bus";
310
311 #address-cells = <2>;
312 #size-cells = <1>;
313 ranges = <0 0 0 0x08000000 0x04000000>,
314 <1 0 0 0x14000000 0x04000000>,
315 <2 0 0 0x18000000 0x04000000>,
316 <3 0 0 0x1c000000 0x04000000>,
317 <4 0 0 0x0c000000 0x04000000>,
318 <5 0 0 0x10000000 0x04000000>;
319
320 #interrupt-cells = <1>;
321 interrupt-map-mask = <0 0 63>;
322 interrupt-map = <0 0 0 &gic 0 0 4>,
323 <0 0 1 &gic 0 1 4>,
324 <0 0 2 &gic 0 2 4>,
325 <0 0 3 &gic 0 3 4>,
326 <0 0 4 &gic 0 4 4>,
327 <0 0 5 &gic 0 5 4>,
328 <0 0 6 &gic 0 6 4>,
329 <0 0 7 &gic 0 7 4>,
330 <0 0 8 &gic 0 8 4>,
331 <0 0 9 &gic 0 9 4>,
332 <0 0 10 &gic 0 10 4>,
333 <0 0 11 &gic 0 11 4>,
334 <0 0 12 &gic 0 12 4>,
335 <0 0 13 &gic 0 13 4>,
336 <0 0 14 &gic 0 14 4>,
337 <0 0 15 &gic 0 15 4>,
338 <0 0 16 &gic 0 16 4>,
339 <0 0 17 &gic 0 17 4>,
340 <0 0 18 &gic 0 18 4>,
341 <0 0 19 &gic 0 19 4>,
342 <0 0 20 &gic 0 20 4>,
343 <0 0 21 &gic 0 21 4>,
344 <0 0 22 &gic 0 22 4>,
345 <0 0 23 &gic 0 23 4>,
346 <0 0 24 &gic 0 24 4>,
347 <0 0 25 &gic 0 25 4>,
348 <0 0 26 &gic 0 26 4>,
349 <0 0 27 &gic 0 27 4>,
350 <0 0 28 &gic 0 28 4>,
351 <0 0 29 &gic 0 29 4>,
352 <0 0 30 &gic 0 30 4>,
353 <0 0 31 &gic 0 31 4>,
354 <0 0 32 &gic 0 32 4>,
355 <0 0 33 &gic 0 33 4>,
356 <0 0 34 &gic 0 34 4>,
357 <0 0 35 &gic 0 35 4>,
358 <0 0 36 &gic 0 36 4>,
359 <0 0 37 &gic 0 37 4>,
360 <0 0 38 &gic 0 38 4>,
361 <0 0 39 &gic 0 39 4>,
362 <0 0 40 &gic 0 40 4>,
363 <0 0 41 &gic 0 41 4>,
364 <0 0 42 &gic 0 42 4>;
365
366 /include/ "vexpress-v2m-rs1.dtsi"
367 };
368};
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
deleted file mode 100644
index 6328cbc71d3..00000000000
--- a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
+++ /dev/null
@@ -1,245 +0,0 @@
1/*
2 * ARM Ltd. Versatile Express
3 *
4 * CoreTile Express A5x2
5 * Cortex-A5 MPCore (V2P-CA5s)
6 *
7 * HBI-0225B
8 */
9
10/dts-v1/;
11
12/ {
13 model = "V2P-CA5s";
14 arm,hbi = <0x225>;
15 arm,vexpress,site = <0xf>;
16 compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
17 interrupt-parent = <&gic>;
18 #address-cells = <1>;
19 #size-cells = <1>;
20
21 chosen { };
22
23 aliases {
24 serial0 = &v2m_serial0;
25 serial1 = &v2m_serial1;
26 serial2 = &v2m_serial2;
27 serial3 = &v2m_serial3;
28 i2c0 = &v2m_i2c_dvi;
29 i2c1 = &v2m_i2c_pcie;
30 };
31
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 cpu@0 {
37 device_type = "cpu";
38 compatible = "arm,cortex-a5";
39 reg = <0>;
40 next-level-cache = <&L2>;
41 };
42
43 cpu@1 {
44 device_type = "cpu";
45 compatible = "arm,cortex-a5";
46 reg = <1>;
47 next-level-cache = <&L2>;
48 };
49 };
50
51 memory@80000000 {
52 device_type = "memory";
53 reg = <0x80000000 0x40000000>;
54 };
55
56 hdlcd@2a110000 {
57 compatible = "arm,hdlcd";
58 reg = <0x2a110000 0x1000>;
59 interrupts = <0 85 4>;
60 clocks = <&oscclk3>;
61 clock-names = "pxlclk";
62 };
63
64 memory-controller@2a150000 {
65 compatible = "arm,pl341", "arm,primecell";
66 reg = <0x2a150000 0x1000>;
67 clocks = <&oscclk1>;
68 clock-names = "apb_pclk";
69 };
70
71 memory-controller@2a190000 {
72 compatible = "arm,pl354", "arm,primecell";
73 reg = <0x2a190000 0x1000>;
74 interrupts = <0 86 4>,
75 <0 87 4>;
76 clocks = <&oscclk1>;
77 clock-names = "apb_pclk";
78 };
79
80 scu@2c000000 {
81 compatible = "arm,cortex-a5-scu";
82 reg = <0x2c000000 0x58>;
83 };
84
85 timer@2c000600 {
86 compatible = "arm,cortex-a5-twd-timer";
87 reg = <0x2c000600 0x20>;
88 interrupts = <1 13 0x304>;
89 };
90
91 watchdog@2c000620 {
92 compatible = "arm,cortex-a5-twd-wdt";
93 reg = <0x2c000620 0x20>;
94 interrupts = <1 14 0x304>;
95 };
96
97 gic: interrupt-controller@2c001000 {
98 compatible = "arm,cortex-a5-gic", "arm,cortex-a9-gic";
99 #interrupt-cells = <3>;
100 #address-cells = <0>;
101 interrupt-controller;
102 reg = <0x2c001000 0x1000>,
103 <0x2c000100 0x100>;
104 };
105
106 L2: cache-controller@2c0f0000 {
107 compatible = "arm,pl310-cache";
108 reg = <0x2c0f0000 0x1000>;
109 interrupts = <0 84 4>;
110 cache-level = <2>;
111 };
112
113 pmu {
114 compatible = "arm,cortex-a5-pmu", "arm,cortex-a9-pmu";
115 interrupts = <0 68 4>,
116 <0 69 4>;
117 };
118
119 dcc {
120 compatible = "arm,vexpress,config-bus";
121 arm,vexpress,config-bridge = <&v2m_sysreg>;
122
123 osc@0 {
124 /* CPU and internal AXI reference clock */
125 compatible = "arm,vexpress-osc";
126 arm,vexpress-sysreg,func = <1 0>;
127 freq-range = <50000000 100000000>;
128 #clock-cells = <0>;
129 clock-output-names = "oscclk0";
130 };
131
132 oscclk1: osc@1 {
133 /* Multiplexed AXI master clock */
134 compatible = "arm,vexpress-osc";
135 arm,vexpress-sysreg,func = <1 1>;
136 freq-range = <5000000 50000000>;
137 #clock-cells = <0>;
138 clock-output-names = "oscclk1";
139 };
140
141 osc@2 {
142 /* DDR2 */
143 compatible = "arm,vexpress-osc";
144 arm,vexpress-sysreg,func = <1 2>;
145 freq-range = <80000000 120000000>;
146 #clock-cells = <0>;
147 clock-output-names = "oscclk2";
148 };
149
150 oscclk3: osc@3 {
151 /* HDLCD */
152 compatible = "arm,vexpress-osc";
153 arm,vexpress-sysreg,func = <1 3>;
154 freq-range = <23750000 165000000>;
155 #clock-cells = <0>;
156 clock-output-names = "oscclk3";
157 };
158
159 osc@4 {
160 /* Test chip gate configuration */
161 compatible = "arm,vexpress-osc";
162 arm,vexpress-sysreg,func = <1 4>;
163 freq-range = <80000000 80000000>;
164 #clock-cells = <0>;
165 clock-output-names = "oscclk4";
166 };
167
168 smbclk: osc@5 {
169 /* SMB clock */
170 compatible = "arm,vexpress-osc";
171 arm,vexpress-sysreg,func = <1 5>;
172 freq-range = <25000000 60000000>;
173 #clock-cells = <0>;
174 clock-output-names = "oscclk5";
175 };
176
177 temp@0 {
178 /* DCC internal operating temperature */
179 compatible = "arm,vexpress-temp";
180 arm,vexpress-sysreg,func = <4 0>;
181 label = "DCC";
182 };
183 };
184
185 smb {
186 compatible = "simple-bus";
187
188 #address-cells = <2>;
189 #size-cells = <1>;
190 ranges = <0 0 0x08000000 0x04000000>,
191 <1 0 0x14000000 0x04000000>,
192 <2 0 0x18000000 0x04000000>,
193 <3 0 0x1c000000 0x04000000>,
194 <4 0 0x0c000000 0x04000000>,
195 <5 0 0x10000000 0x04000000>;
196
197 #interrupt-cells = <1>;
198 interrupt-map-mask = <0 0 63>;
199 interrupt-map = <0 0 0 &gic 0 0 4>,
200 <0 0 1 &gic 0 1 4>,
201 <0 0 2 &gic 0 2 4>,
202 <0 0 3 &gic 0 3 4>,
203 <0 0 4 &gic 0 4 4>,
204 <0 0 5 &gic 0 5 4>,
205 <0 0 6 &gic 0 6 4>,
206 <0 0 7 &gic 0 7 4>,
207 <0 0 8 &gic 0 8 4>,
208 <0 0 9 &gic 0 9 4>,
209 <0 0 10 &gic 0 10 4>,
210 <0 0 11 &gic 0 11 4>,
211 <0 0 12 &gic 0 12 4>,
212 <0 0 13 &gic 0 13 4>,
213 <0 0 14 &gic 0 14 4>,
214 <0 0 15 &gic 0 15 4>,
215 <0 0 16 &gic 0 16 4>,
216 <0 0 17 &gic 0 17 4>,
217 <0 0 18 &gic 0 18 4>,
218 <0 0 19 &gic 0 19 4>,
219 <0 0 20 &gic 0 20 4>,
220 <0 0 21 &gic 0 21 4>,
221 <0 0 22 &gic 0 22 4>,
222 <0 0 23 &gic 0 23 4>,
223 <0 0 24 &gic 0 24 4>,
224 <0 0 25 &gic 0 25 4>,
225 <0 0 26 &gic 0 26 4>,
226 <0 0 27 &gic 0 27 4>,
227 <0 0 28 &gic 0 28 4>,
228 <0 0 29 &gic 0 29 4>,
229 <0 0 30 &gic 0 30 4>,
230 <0 0 31 &gic 0 31 4>,
231 <0 0 32 &gic 0 32 4>,
232 <0 0 33 &gic 0 33 4>,
233 <0 0 34 &gic 0 34 4>,
234 <0 0 35 &gic 0 35 4>,
235 <0 0 36 &gic 0 36 4>,
236 <0 0 37 &gic 0 37 4>,
237 <0 0 38 &gic 0 38 4>,
238 <0 0 39 &gic 0 39 4>,
239 <0 0 40 &gic 0 40 4>,
240 <0 0 41 &gic 0 41 4>,
241 <0 0 42 &gic 0 42 4>;
242
243 /include/ "vexpress-v2m-rs1.dtsi"
244 };
245};
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
deleted file mode 100644
index 1420bb14d95..00000000000
--- a/arch/arm/boot/dts/vexpress-v2p-ca9.dts
+++ /dev/null
@@ -1,327 +0,0 @@
1/*
2 * ARM Ltd. Versatile Express
3 *
4 * CoreTile Express A9x4
5 * Cortex-A9 MPCore (V2P-CA9)
6 *
7 * HBI-0191B
8 */
9
10/dts-v1/;
11
12/ {
13 model = "V2P-CA9";
14 arm,hbi = <0x191>;
15 arm,vexpress,site = <0xf>;
16 compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
17 interrupt-parent = <&gic>;
18 #address-cells = <1>;
19 #size-cells = <1>;
20
21 chosen { };
22
23 aliases {
24 serial0 = &v2m_serial0;
25 serial1 = &v2m_serial1;
26 serial2 = &v2m_serial2;
27 serial3 = &v2m_serial3;
28 i2c0 = &v2m_i2c_dvi;
29 i2c1 = &v2m_i2c_pcie;
30 };
31
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 cpu@0 {
37 device_type = "cpu";
38 compatible = "arm,cortex-a9";
39 reg = <0>;
40 next-level-cache = <&L2>;
41 };
42
43 cpu@1 {
44 device_type = "cpu";
45 compatible = "arm,cortex-a9";
46 reg = <1>;
47 next-level-cache = <&L2>;
48 };
49
50 cpu@2 {
51 device_type = "cpu";
52 compatible = "arm,cortex-a9";
53 reg = <2>;
54 next-level-cache = <&L2>;
55 };
56
57 cpu@3 {
58 device_type = "cpu";
59 compatible = "arm,cortex-a9";
60 reg = <3>;
61 next-level-cache = <&L2>;
62 };
63 };
64
65 memory@60000000 {
66 device_type = "memory";
67 reg = <0x60000000 0x40000000>;
68 };
69
70 clcd@10020000 {
71 compatible = "arm,pl111", "arm,primecell";
72 reg = <0x10020000 0x1000>;
73 interrupts = <0 44 4>;
74 clocks = <&oscclk1>, <&oscclk2>;
75 clock-names = "clcdclk", "apb_pclk";
76 };
77
78 memory-controller@100e0000 {
79 compatible = "arm,pl341", "arm,primecell";
80 reg = <0x100e0000 0x1000>;
81 clocks = <&oscclk2>;
82 clock-names = "apb_pclk";
83 };
84
85 memory-controller@100e1000 {
86 compatible = "arm,pl354", "arm,primecell";
87 reg = <0x100e1000 0x1000>;
88 interrupts = <0 45 4>,
89 <0 46 4>;
90 clocks = <&oscclk2>;
91 clock-names = "apb_pclk";
92 };
93
94 timer@100e4000 {
95 compatible = "arm,sp804", "arm,primecell";
96 reg = <0x100e4000 0x1000>;
97 interrupts = <0 48 4>,
98 <0 49 4>;
99 clocks = <&oscclk2>, <&oscclk2>;
100 clock-names = "timclk", "apb_pclk";
101 };
102
103 watchdog@100e5000 {
104 compatible = "arm,sp805", "arm,primecell";
105 reg = <0x100e5000 0x1000>;
106 interrupts = <0 51 4>;
107 clocks = <&oscclk2>, <&oscclk2>;
108 clock-names = "wdogclk", "apb_pclk";
109 };
110
111 scu@1e000000 {
112 compatible = "arm,cortex-a9-scu";
113 reg = <0x1e000000 0x58>;
114 };
115
116 timer@1e000600 {
117 compatible = "arm,cortex-a9-twd-timer";
118 reg = <0x1e000600 0x20>;
119 interrupts = <1 13 0xf04>;
120 };
121
122 watchdog@1e000620 {
123 compatible = "arm,cortex-a9-twd-wdt";
124 reg = <0x1e000620 0x20>;
125 interrupts = <1 14 0xf04>;
126 };
127
128 gic: interrupt-controller@1e001000 {
129 compatible = "arm,cortex-a9-gic";
130 #interrupt-cells = <3>;
131 #address-cells = <0>;
132 interrupt-controller;
133 reg = <0x1e001000 0x1000>,
134 <0x1e000100 0x100>;
135 };
136
137 L2: cache-controller@1e00a000 {
138 compatible = "arm,pl310-cache";
139 reg = <0x1e00a000 0x1000>;
140 interrupts = <0 43 4>;
141 cache-level = <2>;
142 arm,data-latency = <1 1 1>;
143 arm,tag-latency = <1 1 1>;
144 };
145
146 pmu {
147 compatible = "arm,cortex-a9-pmu";
148 interrupts = <0 60 4>,
149 <0 61 4>,
150 <0 62 4>,
151 <0 63 4>;
152 };
153
154 dcc {
155 compatible = "arm,vexpress,config-bus";
156 arm,vexpress,config-bridge = <&v2m_sysreg>;
157
158 osc@0 {
159 /* ACLK clock to the AXI master port on the test chip */
160 compatible = "arm,vexpress-osc";
161 arm,vexpress-sysreg,func = <1 0>;
162 freq-range = <30000000 50000000>;
163 #clock-cells = <0>;
164 clock-output-names = "extsaxiclk";
165 };
166
167 oscclk1: osc@1 {
168 /* Reference clock for the CLCD */
169 compatible = "arm,vexpress-osc";
170 arm,vexpress-sysreg,func = <1 1>;
171 freq-range = <10000000 80000000>;
172 #clock-cells = <0>;
173 clock-output-names = "clcdclk";
174 };
175
176 smbclk: oscclk2: osc@2 {
177 /* Reference clock for the test chip internal PLLs */
178 compatible = "arm,vexpress-osc";
179 arm,vexpress-sysreg,func = <1 2>;
180 freq-range = <33000000 100000000>;
181 #clock-cells = <0>;
182 clock-output-names = "tcrefclk";
183 };
184
185 volt@0 {
186 /* Test Chip internal logic voltage */
187 compatible = "arm,vexpress-volt";
188 arm,vexpress-sysreg,func = <2 0>;
189 regulator-name = "VD10";
190 regulator-always-on;
191 label = "VD10";
192 };
193
194 volt@1 {
195 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
196 compatible = "arm,vexpress-volt";
197 arm,vexpress-sysreg,func = <2 1>;
198 regulator-name = "VD10_S2";
199 regulator-always-on;
200 label = "VD10_S2";
201 };
202
203 volt@2 {
204 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
205 compatible = "arm,vexpress-volt";
206 arm,vexpress-sysreg,func = <2 2>;
207 regulator-name = "VD10_S3";
208 regulator-always-on;
209 label = "VD10_S3";
210 };
211
212 volt@3 {
213 /* DDR2 SDRAM and Test Chip DDR2 I/O supply */
214 compatible = "arm,vexpress-volt";
215 arm,vexpress-sysreg,func = <2 3>;
216 regulator-name = "VCC1V8";
217 regulator-always-on;
218 label = "VCC1V8";
219 };
220
221 volt@4 {
222 /* DDR2 SDRAM VTT termination voltage */
223 compatible = "arm,vexpress-volt";
224 arm,vexpress-sysreg,func = <2 4>;
225 regulator-name = "DDR2VTT";
226 regulator-always-on;
227 label = "DDR2VTT";
228 };
229
230 volt@5 {
231 /* Local board supply for miscellaneous logic external to the Test Chip */
232 arm,vexpress-sysreg,func = <2 5>;
233 compatible = "arm,vexpress-volt";
234 regulator-name = "VCC3V3";
235 regulator-always-on;
236 label = "VCC3V3";
237 };
238
239 amp@0 {
240 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
241 compatible = "arm,vexpress-amp";
242 arm,vexpress-sysreg,func = <3 0>;
243 label = "VD10_S2";
244 };
245
246 amp@1 {
247 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
248 compatible = "arm,vexpress-amp";
249 arm,vexpress-sysreg,func = <3 1>;
250 label = "VD10_S3";
251 };
252
253 power@0 {
254 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
255 compatible = "arm,vexpress-power";
256 arm,vexpress-sysreg,func = <12 0>;
257 label = "PVD10_S2";
258 };
259
260 power@1 {
261 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
262 compatible = "arm,vexpress-power";
263 arm,vexpress-sysreg,func = <12 1>;
264 label = "PVD10_S3";
265 };
266 };
267
268 smb {
269 compatible = "simple-bus";
270
271 #address-cells = <2>;
272 #size-cells = <1>;
273 ranges = <0 0 0x40000000 0x04000000>,
274 <1 0 0x44000000 0x04000000>,
275 <2 0 0x48000000 0x04000000>,
276 <3 0 0x4c000000 0x04000000>,
277 <7 0 0x10000000 0x00020000>;
278
279 #interrupt-cells = <1>;
280 interrupt-map-mask = <0 0 63>;
281 interrupt-map = <0 0 0 &gic 0 0 4>,
282 <0 0 1 &gic 0 1 4>,
283 <0 0 2 &gic 0 2 4>,
284 <0 0 3 &gic 0 3 4>,
285 <0 0 4 &gic 0 4 4>,
286 <0 0 5 &gic 0 5 4>,
287 <0 0 6 &gic 0 6 4>,
288 <0 0 7 &gic 0 7 4>,
289 <0 0 8 &gic 0 8 4>,
290 <0 0 9 &gic 0 9 4>,
291 <0 0 10 &gic 0 10 4>,
292 <0 0 11 &gic 0 11 4>,
293 <0 0 12 &gic 0 12 4>,
294 <0 0 13 &gic 0 13 4>,
295 <0 0 14 &gic 0 14 4>,
296 <0 0 15 &gic 0 15 4>,
297 <0 0 16 &gic 0 16 4>,
298 <0 0 17 &gic 0 17 4>,
299 <0 0 18 &gic 0 18 4>,
300 <0 0 19 &gic 0 19 4>,
301 <0 0 20 &gic 0 20 4>,
302 <0 0 21 &gic 0 21 4>,
303 <0 0 22 &gic 0 22 4>,
304 <0 0 23 &gic 0 23 4>,
305 <0 0 24 &gic 0 24 4>,
306 <0 0 25 &gic 0 25 4>,
307 <0 0 26 &gic 0 26 4>,
308 <0 0 27 &gic 0 27 4>,
309 <0 0 28 &gic 0 28 4>,
310 <0 0 29 &gic 0 29 4>,
311 <0 0 30 &gic 0 30 4>,
312 <0 0 31 &gic 0 31 4>,
313 <0 0 32 &gic 0 32 4>,
314 <0 0 33 &gic 0 33 4>,
315 <0 0 34 &gic 0 34 4>,
316 <0 0 35 &gic 0 35 4>,
317 <0 0 36 &gic 0 36 4>,
318 <0 0 37 &gic 0 37 4>,
319 <0 0 38 &gic 0 38 4>,
320 <0 0 39 &gic 0 39 4>,
321 <0 0 40 &gic 0 40 4>,
322 <0 0 41 &gic 0 41 4>,
323 <0 0 42 &gic 0 42 4>;
324
325 /include/ "vexpress-v2m.dtsi"
326 };
327};
diff --git a/arch/arm/boot/dts/vt8500-bv07.dts b/arch/arm/boot/dts/vt8500-bv07.dts
deleted file mode 100644
index 567cf4e8ab8..00000000000
--- a/arch/arm/boot/dts/vt8500-bv07.dts
+++ /dev/null
@@ -1,36 +0,0 @@
1/*
2 * vt8500-bv07.dts - Device tree file for Benign BV07 Netbook
3 *
4 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
5 *
6 * Licensed under GPLv2 or later
7 */
8
9/dts-v1/;
10/include/ "vt8500.dtsi"
11
12/ {
13 model = "Benign BV07 Netbook";
14
15 /*
16 * Display node is based on Sascha Hauer's patch on dri-devel.
17 * Added a bpp property to calculate the size of the framebuffer
18 * until the binding is formalized.
19 */
20 display: display@0 {
21 modes {
22 mode0: mode@0 {
23 hactive = <800>;
24 vactive = <480>;
25 hback-porch = <88>;
26 hfront-porch = <40>;
27 hsync-len = <0>;
28 vback-porch = <32>;
29 vfront-porch = <11>;
30 vsync-len = <1>;
31 clock = <0>; /* unused but required */
32 bpp = <16>; /* non-standard but required */
33 };
34 };
35 };
36};
diff --git a/arch/arm/boot/dts/vt8500.dtsi b/arch/arm/boot/dts/vt8500.dtsi
deleted file mode 100644
index d8645e990b2..00000000000
--- a/arch/arm/boot/dts/vt8500.dtsi
+++ /dev/null
@@ -1,116 +0,0 @@
1/*
2 * vt8500.dtsi - Device tree file for VIA VT8500 SoC
3 *
4 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
5 *
6 * Licensed under GPLv2 or later
7 */
8
9/include/ "skeleton.dtsi"
10
11/ {
12 compatible = "via,vt8500";
13
14 soc {
15 #address-cells = <1>;
16 #size-cells = <1>;
17 compatible = "simple-bus";
18 ranges;
19 interrupt-parent = <&intc>;
20
21 intc: interrupt-controller@d8140000 {
22 compatible = "via,vt8500-intc";
23 interrupt-controller;
24 reg = <0xd8140000 0x10000>;
25 #interrupt-cells = <1>;
26 };
27
28 gpio: gpio-controller@d8110000 {
29 compatible = "via,vt8500-gpio";
30 gpio-controller;
31 reg = <0xd8110000 0x10000>;
32 #gpio-cells = <3>;
33 };
34
35 pmc@d8130000 {
36 compatible = "via,vt8500-pmc";
37 reg = <0xd8130000 0x1000>;
38
39 clocks {
40 #address-cells = <1>;
41 #size-cells = <0>;
42
43 ref24: ref24M {
44 #clock-cells = <0>;
45 compatible = "fixed-clock";
46 clock-frequency = <24000000>;
47 };
48 };
49 };
50
51 timer@d8130100 {
52 compatible = "via,vt8500-timer";
53 reg = <0xd8130100 0x28>;
54 interrupts = <36>;
55 };
56
57 ehci@d8007900 {
58 compatible = "via,vt8500-ehci";
59 reg = <0xd8007900 0x200>;
60 interrupts = <43>;
61 };
62
63 uhci@d8007b00 {
64 compatible = "platform-uhci";
65 reg = <0xd8007b00 0x200>;
66 interrupts = <43>;
67 };
68
69 fb@d800e400 {
70 compatible = "via,vt8500-fb";
71 reg = <0xd800e400 0x400>;
72 interrupts = <12>;
73 display = <&display>;
74 default-mode = <&mode0>;
75 };
76
77 ge_rops@d8050400 {
78 compatible = "wm,prizm-ge-rops";
79 reg = <0xd8050400 0x100>;
80 };
81
82 uart@d8200000 {
83 compatible = "via,vt8500-uart";
84 reg = <0xd8200000 0x1040>;
85 interrupts = <32>;
86 clocks = <&ref24>;
87 };
88
89 uart@d82b0000 {
90 compatible = "via,vt8500-uart";
91 reg = <0xd82b0000 0x1040>;
92 interrupts = <33>;
93 clocks = <&ref24>;
94 };
95
96 uart@d8210000 {
97 compatible = "via,vt8500-uart";
98 reg = <0xd8210000 0x1040>;
99 interrupts = <47>;
100 clocks = <&ref24>;
101 };
102
103 uart@d82c0000 {
104 compatible = "via,vt8500-uart";
105 reg = <0xd82c0000 0x1040>;
106 interrupts = <50>;
107 clocks = <&ref24>;
108 };
109
110 rtc@d8100000 {
111 compatible = "via,vt8500-rtc";
112 reg = <0xd8100000 0x10000>;
113 interrupts = <48>;
114 };
115 };
116};
diff --git a/arch/arm/boot/dts/wm8505-ref.dts b/arch/arm/boot/dts/wm8505-ref.dts
deleted file mode 100644
index fd4e248074c..00000000000
--- a/arch/arm/boot/dts/wm8505-ref.dts
+++ /dev/null
@@ -1,36 +0,0 @@
1/*
2 * wm8505-ref.dts - Device tree file for Wondermedia WM8505 reference netbook
3 *
4 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
5 *
6 * Licensed under GPLv2 or later
7 */
8
9/dts-v1/;
10/include/ "wm8505.dtsi"
11
12/ {
13 model = "Wondermedia WM8505 Netbook";
14
15 /*
16 * Display node is based on Sascha Hauer's patch on dri-devel.
17 * Added a bpp property to calculate the size of the framebuffer
18 * until the binding is formalized.
19 */
20 display: display@0 {
21 modes {
22 mode0: mode@0 {
23 hactive = <800>;
24 vactive = <480>;
25 hback-porch = <88>;
26 hfront-porch = <40>;
27 hsync-len = <0>;
28 vback-porch = <32>;
29 vfront-porch = <11>;
30 vsync-len = <1>;
31 clock = <0>; /* unused but required */
32 bpp = <32>; /* non-standard but required */
33 };
34 };
35 };
36};
diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi
deleted file mode 100644
index 330f833ac3b..00000000000
--- a/arch/arm/boot/dts/wm8505.dtsi
+++ /dev/null
@@ -1,143 +0,0 @@
1/*
2 * wm8505.dtsi - Device tree file for Wondermedia WM8505 SoC
3 *
4 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
5 *
6 * Licensed under GPLv2 or later
7 */
8
9/include/ "skeleton.dtsi"
10
11/ {
12 compatible = "wm,wm8505";
13
14 cpus {
15 cpu@0 {
16 compatible = "arm,arm926ejs";
17 };
18 };
19
20 soc {
21 #address-cells = <1>;
22 #size-cells = <1>;
23 compatible = "simple-bus";
24 ranges;
25 interrupt-parent = <&intc0>;
26
27 intc0: interrupt-controller@d8140000 {
28 compatible = "via,vt8500-intc";
29 interrupt-controller;
30 reg = <0xd8140000 0x10000>;
31 #interrupt-cells = <1>;
32 };
33
34 /* Secondary IC cascaded to intc0 */
35 intc1: interrupt-controller@d8150000 {
36 compatible = "via,vt8500-intc";
37 interrupt-controller;
38 #interrupt-cells = <1>;
39 reg = <0xD8150000 0x10000>;
40 interrupts = <56 57 58 59 60 61 62 63>;
41 };
42
43 gpio: gpio-controller@d8110000 {
44 compatible = "wm,wm8505-gpio";
45 gpio-controller;
46 reg = <0xd8110000 0x10000>;
47 #gpio-cells = <3>;
48 };
49
50 pmc@d8130000 {
51 compatible = "via,vt8500-pmc";
52 reg = <0xd8130000 0x1000>;
53 clocks {
54 #address-cells = <1>;
55 #size-cells = <0>;
56
57 ref24: ref24M {
58 #clock-cells = <0>;
59 compatible = "fixed-clock";
60 clock-frequency = <24000000>;
61 };
62 };
63 };
64
65 timer@d8130100 {
66 compatible = "via,vt8500-timer";
67 reg = <0xd8130100 0x28>;
68 interrupts = <36>;
69 };
70
71 ehci@d8007100 {
72 compatible = "via,vt8500-ehci";
73 reg = <0xd8007100 0x200>;
74 interrupts = <1>;
75 };
76
77 uhci@d8007300 {
78 compatible = "platform-uhci";
79 reg = <0xd8007300 0x200>;
80 interrupts = <0>;
81 };
82
83 fb@d8050800 {
84 compatible = "wm,wm8505-fb";
85 reg = <0xd8050800 0x200>;
86 display = <&display>;
87 default-mode = <&mode0>;
88 };
89
90 ge_rops@d8050400 {
91 compatible = "wm,prizm-ge-rops";
92 reg = <0xd8050400 0x100>;
93 };
94
95 uart@d8200000 {
96 compatible = "via,vt8500-uart";
97 reg = <0xd8200000 0x1040>;
98 interrupts = <32>;
99 clocks = <&ref24>;
100 };
101
102 uart@d82b0000 {
103 compatible = "via,vt8500-uart";
104 reg = <0xd82b0000 0x1040>;
105 interrupts = <33>;
106 clocks = <&ref24>;
107 };
108
109 uart@d8210000 {
110 compatible = "via,vt8500-uart";
111 reg = <0xd8210000 0x1040>;
112 interrupts = <47>;
113 clocks = <&ref24>;
114 };
115
116 uart@d82c0000 {
117 compatible = "via,vt8500-uart";
118 reg = <0xd82c0000 0x1040>;
119 interrupts = <50>;
120 clocks = <&ref24>;
121 };
122
123 uart@d8370000 {
124 compatible = "via,vt8500-uart";
125 reg = <0xd8370000 0x1040>;
126 interrupts = <31>;
127 clocks = <&ref24>;
128 };
129
130 uart@d8380000 {
131 compatible = "via,vt8500-uart";
132 reg = <0xd8380000 0x1040>;
133 interrupts = <30>;
134 clocks = <&ref24>;
135 };
136
137 rtc@d8100000 {
138 compatible = "via,vt8500-rtc";
139 reg = <0xd8100000 0x10000>;
140 interrupts = <48>;
141 };
142 };
143};
diff --git a/arch/arm/boot/dts/wm8650-mid.dts b/arch/arm/boot/dts/wm8650-mid.dts
deleted file mode 100644
index cefd938f842..00000000000
--- a/arch/arm/boot/dts/wm8650-mid.dts
+++ /dev/null
@@ -1,36 +0,0 @@
1/*
2 * wm8650-mid.dts - Device tree file for Wondermedia WM8650-MID Tablet
3 *
4 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
5 *
6 * Licensed under GPLv2 or later
7 */
8
9/dts-v1/;
10/include/ "wm8650.dtsi"
11
12/ {
13 model = "Wondermedia WM8650-MID Tablet";
14
15 /*
16 * Display node is based on Sascha Hauer's patch on dri-devel.
17 * Added a bpp property to calculate the size of the framebuffer
18 * until the binding is formalized.
19 */
20 display: display@0 {
21 modes {
22 mode0: mode@0 {
23 hactive = <800>;
24 vactive = <480>;
25 hback-porch = <88>;
26 hfront-porch = <40>;
27 hsync-len = <0>;
28 vback-porch = <32>;
29 vfront-porch = <11>;
30 vsync-len = <1>;
31 clock = <0>; /* unused but required */
32 bpp = <16>; /* non-standard but required */
33 };
34 };
35 };
36};
diff --git a/arch/arm/boot/dts/wm8650.dtsi b/arch/arm/boot/dts/wm8650.dtsi
deleted file mode 100644
index 83b9467559b..00000000000
--- a/arch/arm/boot/dts/wm8650.dtsi
+++ /dev/null
@@ -1,147 +0,0 @@
1/*
2 * wm8650.dtsi - Device tree file for Wondermedia WM8650 SoC
3 *
4 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
5 *
6 * Licensed under GPLv2 or later
7 */
8
9/include/ "skeleton.dtsi"
10
11/ {
12 compatible = "wm,wm8650";
13
14 soc {
15 #address-cells = <1>;
16 #size-cells = <1>;
17 compatible = "simple-bus";
18 ranges;
19 interrupt-parent = <&intc0>;
20
21 intc0: interrupt-controller@d8140000 {
22 compatible = "via,vt8500-intc";
23 interrupt-controller;
24 reg = <0xd8140000 0x10000>;
25 #interrupt-cells = <1>;
26 };
27
28 /* Secondary IC cascaded to intc0 */
29 intc1: interrupt-controller@d8150000 {
30 compatible = "via,vt8500-intc";
31 interrupt-controller;
32 #interrupt-cells = <1>;
33 reg = <0xD8150000 0x10000>;
34 interrupts = <56 57 58 59 60 61 62 63>;
35 };
36
37 gpio: gpio-controller@d8110000 {
38 compatible = "wm,wm8650-gpio";
39 gpio-controller;
40 reg = <0xd8110000 0x10000>;
41 #gpio-cells = <3>;
42 };
43
44 pmc@d8130000 {
45 compatible = "via,vt8500-pmc";
46 reg = <0xd8130000 0x1000>;
47
48 clocks {
49 #address-cells = <1>;
50 #size-cells = <0>;
51
52 ref25: ref25M {
53 #clock-cells = <0>;
54 compatible = "fixed-clock";
55 clock-frequency = <25000000>;
56 };
57
58 ref24: ref24M {
59 #clock-cells = <0>;
60 compatible = "fixed-clock";
61 clock-frequency = <24000000>;
62 };
63
64 plla: plla {
65 #clock-cells = <0>;
66 compatible = "wm,wm8650-pll-clock";
67 clocks = <&ref25>;
68 reg = <0x200>;
69 };
70
71 pllb: pllb {
72 #clock-cells = <0>;
73 compatible = "wm,wm8650-pll-clock";
74 clocks = <&ref25>;
75 reg = <0x204>;
76 };
77
78 arm: arm {
79 #clock-cells = <0>;
80 compatible = "via,vt8500-device-clock";
81 clocks = <&plla>;
82 divisor-reg = <0x300>;
83 };
84
85 sdhc: sdhc {
86 #clock-cells = <0>;
87 compatible = "via,vt8500-device-clock";
88 clocks = <&pllb>;
89 divisor-reg = <0x328>;
90 divisor-mask = <0x3f>;
91 enable-reg = <0x254>;
92 enable-bit = <18>;
93 };
94 };
95 };
96
97 timer@d8130100 {
98 compatible = "via,vt8500-timer";
99 reg = <0xd8130100 0x28>;
100 interrupts = <36>;
101 };
102
103 ehci@d8007900 {
104 compatible = "via,vt8500-ehci";
105 reg = <0xd8007900 0x200>;
106 interrupts = <43>;
107 };
108
109 uhci@d8007b00 {
110 compatible = "platform-uhci";
111 reg = <0xd8007b00 0x200>;
112 interrupts = <43>;
113 };
114
115 fb@d8050800 {
116 compatible = "wm,wm8505-fb";
117 reg = <0xd8050800 0x200>;
118 display = <&display>;
119 default-mode = <&mode0>;
120 };
121
122 ge_rops@d8050400 {
123 compatible = "wm,prizm-ge-rops";
124 reg = <0xd8050400 0x100>;
125 };
126
127 uart@d8200000 {
128 compatible = "via,vt8500-uart";
129 reg = <0xd8200000 0x1040>;
130 interrupts = <32>;
131 clocks = <&ref24>;
132 };
133
134 uart@d82b0000 {
135 compatible = "via,vt8500-uart";
136 reg = <0xd82b0000 0x1040>;
137 interrupts = <33>;
138 clocks = <&ref24>;
139 };
140
141 rtc@d8100000 {
142 compatible = "via,vt8500-rtc";
143 reg = <0xd8100000 0x10000>;
144 interrupts = <48>;
145 };
146 };
147};
diff --git a/arch/arm/boot/dts/xenvm-4.2.dts b/arch/arm/boot/dts/xenvm-4.2.dts
deleted file mode 100644
index ec3f9528e18..00000000000
--- a/arch/arm/boot/dts/xenvm-4.2.dts
+++ /dev/null
@@ -1,68 +0,0 @@
1/*
2 * Xen Virtual Machine for unprivileged guests
3 *
4 * Based on ARM Ltd. Versatile Express CoreTile Express (single CPU)
5 * Cortex-A15 MPCore (V2P-CA15)
6 *
7 */
8
9/dts-v1/;
10
11/ {
12 model = "XENVM-4.2";
13 compatible = "xen,xenvm-4.2", "xen,xenvm";
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 chosen {
19 /* this field is going to be adjusted by the hypervisor */
20 bootargs = "console=hvc0 root=/dev/xvda";
21 };
22
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 cpu@0 {
28 device_type = "cpu";
29 compatible = "arm,cortex-a15";
30 reg = <0>;
31 };
32 };
33
34 memory@80000000 {
35 device_type = "memory";
36 /* this field is going to be adjusted by the hypervisor */
37 reg = <0 0x80000000 0 0x08000000>;
38 };
39
40 gic: interrupt-controller@2c001000 {
41 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
42 #interrupt-cells = <3>;
43 #address-cells = <0>;
44 interrupt-controller;
45 reg = <0 0x2c001000 0 0x1000>,
46 <0 0x2c002000 0 0x100>;
47 };
48
49 timer {
50 compatible = "arm,armv7-timer";
51 interrupts = <1 13 0xf08>,
52 <1 14 0xf08>,
53 <1 11 0xf08>,
54 <1 10 0xf08>;
55 };
56
57 hypervisor {
58 compatible = "xen,xen-4.2", "xen,xen";
59 /* this field is going to be adjusted by the hypervisor */
60 reg = <0 0xb0000000 0 0x20000>;
61 /* this field is going to be adjusted by the hypervisor */
62 interrupts = <1 15 0xf08>;
63 };
64
65 motherboard {
66 arm,v2m-memory-map = "rs1";
67 };
68};
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
deleted file mode 100644
index 401c1262d4e..00000000000
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ /dev/null
@@ -1,166 +0,0 @@
1/*
2 * Copyright (C) 2011 Xilinx
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13/include/ "skeleton.dtsi"
14
15/ {
16 compatible = "xlnx,zynq-7000";
17
18 amba {
19 compatible = "simple-bus";
20 #address-cells = <1>;
21 #size-cells = <1>;
22 interrupt-parent = <&intc>;
23 ranges;
24
25 intc: interrupt-controller@f8f01000 {
26 compatible = "arm,cortex-a9-gic";
27 #interrupt-cells = <3>;
28 #address-cells = <1>;
29 interrupt-controller;
30 reg = <0xF8F01000 0x1000>,
31 <0xF8F00100 0x100>;
32 };
33
34 L2: cache-controller {
35 compatible = "arm,pl310-cache";
36 reg = <0xF8F02000 0x1000>;
37 arm,data-latency = <2 3 2>;
38 arm,tag-latency = <2 3 2>;
39 cache-unified;
40 cache-level = <2>;
41 };
42
43 uart0: uart@e0000000 {
44 compatible = "xlnx,xuartps";
45 reg = <0xE0000000 0x1000>;
46 interrupts = <0 27 4>;
47 clock = <50000000>;
48 };
49
50 uart1: uart@e0001000 {
51 compatible = "xlnx,xuartps";
52 reg = <0xE0001000 0x1000>;
53 interrupts = <0 50 4>;
54 clock = <50000000>;
55 };
56
57 slcr: slcr@f8000000 {
58 compatible = "xlnx,zynq-slcr";
59 reg = <0xF8000000 0x1000>;
60
61 clocks {
62 #address-cells = <1>;
63 #size-cells = <0>;
64
65 ps_clk: ps_clk {
66 #clock-cells = <0>;
67 compatible = "fixed-clock";
68 /* clock-frequency set in board-specific file */
69 clock-output-names = "ps_clk";
70 };
71 armpll: armpll {
72 #clock-cells = <0>;
73 compatible = "xlnx,zynq-pll";
74 clocks = <&ps_clk>;
75 reg = <0x100 0x110>;
76 clock-output-names = "armpll";
77 };
78 ddrpll: ddrpll {
79 #clock-cells = <0>;
80 compatible = "xlnx,zynq-pll";
81 clocks = <&ps_clk>;
82 reg = <0x104 0x114>;
83 clock-output-names = "ddrpll";
84 };
85 iopll: iopll {
86 #clock-cells = <0>;
87 compatible = "xlnx,zynq-pll";
88 clocks = <&ps_clk>;
89 reg = <0x108 0x118>;
90 clock-output-names = "iopll";
91 };
92 uart_clk: uart_clk {
93 #clock-cells = <1>;
94 compatible = "xlnx,zynq-periph-clock";
95 clocks = <&iopll &armpll &ddrpll>;
96 reg = <0x154>;
97 clock-output-names = "uart0_ref_clk",
98 "uart1_ref_clk";
99 };
100 cpu_clk: cpu_clk {
101 #clock-cells = <1>;
102 compatible = "xlnx,zynq-cpu-clock";
103 clocks = <&iopll &armpll &ddrpll>;
104 reg = <0x120 0x1C4>;
105 clock-output-names = "cpu_6x4x",
106 "cpu_3x2x",
107 "cpu_2x",
108 "cpu_1x";
109 };
110 };
111 };
112
113 ttc0: ttc0@f8001000 {
114 #address-cells = <1>;
115 #size-cells = <0>;
116 compatible = "xlnx,ttc";
117 reg = <0xF8001000 0x1000>;
118 clocks = <&cpu_clk 3>;
119 clock-names = "cpu_1x";
120 clock-ranges;
121
122 ttc0_0: ttc0.0 {
123 status = "disabled";
124 reg = <0>;
125 interrupts = <0 10 4>;
126 };
127 ttc0_1: ttc0.1 {
128 status = "disabled";
129 reg = <1>;
130 interrupts = <0 11 4>;
131 };
132 ttc0_2: ttc0.2 {
133 status = "disabled";
134 reg = <2>;
135 interrupts = <0 12 4>;
136 };
137 };
138
139 ttc1: ttc1@f8002000 {
140 #interrupt-parent = <&intc>;
141 #address-cells = <1>;
142 #size-cells = <0>;
143 compatible = "xlnx,ttc";
144 reg = <0xF8002000 0x1000>;
145 clocks = <&cpu_clk 3>;
146 clock-names = "cpu_1x";
147 clock-ranges;
148
149 ttc1_0: ttc1.0 {
150 status = "disabled";
151 reg = <0>;
152 interrupts = <0 37 4>;
153 };
154 ttc1_1: ttc1.1 {
155 status = "disabled";
156 reg = <1>;
157 interrupts = <0 38 4>;
158 };
159 ttc1_2: ttc1.2 {
160 status = "disabled";
161 reg = <2>;
162 interrupts = <0 39 4>;
163 };
164 };
165 };
166};
diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts
deleted file mode 100644
index c772942a399..00000000000
--- a/arch/arm/boot/dts/zynq-zc702.dts
+++ /dev/null
@@ -1,44 +0,0 @@
1/*
2 * Copyright (C) 2011 Xilinx
3 * Copyright (C) 2012 National Instruments Corp.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14/dts-v1/;
15/include/ "zynq-7000.dtsi"
16
17/ {
18 model = "Zynq ZC702 Development Board";
19 compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
20
21 memory {
22 device_type = "memory";
23 reg = <0x0 0x40000000>;
24 };
25
26 chosen {
27 bootargs = "console=ttyPS1,115200 earlyprintk";
28 };
29
30};
31
32&ps_clk {
33 clock-frequency = <33333330>;
34};
35
36&ttc0_0 {
37 status = "ok";
38 compatible = "xlnx,ttc-counter-clocksource";
39};
40
41&ttc0_1 {
42 status = "ok";
43 compatible = "xlnx,ttc-counter-clockevent";
44};
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-29 03:50:02 -0400