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authorBarry Song <Baohua.Song@csr.com>2012-08-22 22:47:53 -0400
committerBarry Song <Barry.Song@csr.com>2012-09-05 02:46:44 -0400
commit434e1c574cc304eaff630f4e92ed239f7886815f (patch)
tree147f8e8b5c362763f2d0493cb610ddbe622856cd /arch/arm/boot/dts/prima2-cb.dts
parent500b6ae3c1edbc8fc7a3ba551f9e09acffaa4304 (diff)
ARM: PRIMA2: rename prima2-cb.dts to prima2.dtsi as it only has SoC features
The current prima2-cb.dts only includes prima2 SoC feature without board- specific descriptions. This patches rename it to dtsi and clean some useless content. Signed-off-by: Barry Song <Baohua.Song@csr.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/prima2-cb.dts')
-rw-r--r--arch/arm/boot/dts/prima2-cb.dts425
1 files changed, 0 insertions, 425 deletions
diff --git a/arch/arm/boot/dts/prima2-cb.dts b/arch/arm/boot/dts/prima2-cb.dts
deleted file mode 100644
index 4245306d60e..00000000000
--- a/arch/arm/boot/dts/prima2-cb.dts
+++ /dev/null
@@ -1,425 +0,0 @@
1/dts-v1/;
2/ {
3 model = "SiRF Prima2 eVB";
4 compatible = "sirf,prima2-cb", "sirf,prima2";
5 #address-cells = <1>;
6 #size-cells = <1>;
7 interrupt-parent = <&intc>;
8
9 memory {
10 reg = <0x00000000 0x20000000>;
11 };
12
13 chosen {
14 bootargs = "mem=512M real_root=/dev/mmcblk0p2 console=ttyS0 panel=1 bootsplash=true bpp=16 androidboot.console=ttyS1";
15 linux,stdout-path = &uart1;
16 };
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 cpu@0 {
23 reg = <0x0>;
24 d-cache-line-size = <32>;
25 i-cache-line-size = <32>;
26 d-cache-size = <32768>;
27 i-cache-size = <32768>;
28 /* from bootloader */
29 timebase-frequency = <0>;
30 bus-frequency = <0>;
31 clock-frequency = <0>;
32 };
33 };
34
35 axi {
36 compatible = "simple-bus";
37 #address-cells = <1>;
38 #size-cells = <1>;
39 ranges = <0x40000000 0x40000000 0x80000000>;
40
41 l2-cache-controller@80040000 {
42 compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache";
43 reg = <0x80040000 0x1000>;
44 interrupts = <59>;
45 arm,tag-latency = <1 1 1>;
46 arm,data-latency = <1 1 1>;
47 arm,filter-ranges = <0 0x40000000>;
48 };
49
50 intc: interrupt-controller@80020000 {
51 #interrupt-cells = <1>;
52 interrupt-controller;
53 compatible = "sirf,prima2-intc";
54 reg = <0x80020000 0x1000>;
55 };
56
57 sys-iobg {
58 compatible = "simple-bus";
59 #address-cells = <1>;
60 #size-cells = <1>;
61 ranges = <0x88000000 0x88000000 0x40000>;
62
63 clock-controller@88000000 {
64 compatible = "sirf,prima2-clkc";
65 reg = <0x88000000 0x1000>;
66 interrupts = <3>;
67 };
68
69 reset-controller@88010000 {
70 compatible = "sirf,prima2-rstc";
71 reg = <0x88010000 0x1000>;
72 };
73
74 rsc-controller@88020000 {
75 compatible = "sirf,prima2-rsc";
76 reg = <0x88020000 0x1000>;
77 };
78 };
79
80 mem-iobg {
81 compatible = "simple-bus";
82 #address-cells = <1>;
83 #size-cells = <1>;
84 ranges = <0x90000000 0x90000000 0x10000>;
85
86 memory-controller@90000000 {
87 compatible = "sirf,prima2-memc";
88 reg = <0x90000000 0x10000>;
89 interrupts = <27>;
90 };
91 };
92
93 disp-iobg {
94 compatible = "simple-bus";
95 #address-cells = <1>;
96 #size-cells = <1>;
97 ranges = <0x90010000 0x90010000 0x30000>;
98
99 display@90010000 {
100 compatible = "sirf,prima2-lcd";
101 reg = <0x90010000 0x20000>;
102 interrupts = <30>;
103 };
104
105 vpp@90020000 {
106 compatible = "sirf,prima2-vpp";
107 reg = <0x90020000 0x10000>;
108 interrupts = <31>;
109 };
110 };
111
112 graphics-iobg {
113 compatible = "simple-bus";
114 #address-cells = <1>;
115 #size-cells = <1>;
116 ranges = <0x98000000 0x98000000 0x8000000>;
117
118 graphics@98000000 {
119 compatible = "powervr,sgx531";
120 reg = <0x98000000 0x8000000>;
121 interrupts = <6>;
122 };
123 };
124
125 multimedia-iobg {
126 compatible = "simple-bus";
127 #address-cells = <1>;
128 #size-cells = <1>;
129 ranges = <0xa0000000 0xa0000000 0x8000000>;
130
131 multimedia@a0000000 {
132 compatible = "sirf,prima2-video-codec";
133 reg = <0xa0000000 0x8000000>;
134 interrupts = <5>;
135 };
136 };
137
138 dsp-iobg {
139 compatible = "simple-bus";
140 #address-cells = <1>;
141 #size-cells = <1>;
142 ranges = <0xa8000000 0xa8000000 0x2000000>;
143
144 dspif@a8000000 {
145 compatible = "sirf,prima2-dspif";
146 reg = <0xa8000000 0x10000>;
147 interrupts = <9>;
148 };
149
150 gps@a8010000 {
151 compatible = "sirf,prima2-gps";
152 reg = <0xa8010000 0x10000>;
153 interrupts = <7>;
154 };
155
156 dsp@a9000000 {
157 compatible = "sirf,prima2-dsp";
158 reg = <0xa9000000 0x1000000>;
159 interrupts = <8>;
160 };
161 };
162
163 peri-iobg {
164 compatible = "simple-bus";
165 #address-cells = <1>;
166 #size-cells = <1>;
167 ranges = <0xb0000000 0xb0000000 0x180000>;
168
169 timer@b0020000 {
170 compatible = "sirf,prima2-tick";
171 reg = <0xb0020000 0x1000>;
172 interrupts = <0>;
173 };
174
175 nand@b0030000 {
176 compatible = "sirf,prima2-nand";
177 reg = <0xb0030000 0x10000>;
178 interrupts = <41>;
179 };
180
181 audio@b0040000 {
182 compatible = "sirf,prima2-audio";
183 reg = <0xb0040000 0x10000>;
184 interrupts = <35>;
185 };
186
187 uart0: uart@b0050000 {
188 cell-index = <0>;
189 compatible = "sirf,prima2-uart";
190 reg = <0xb0050000 0x10000>;
191 interrupts = <17>;
192 };
193
194 uart1: uart@b0060000 {
195 cell-index = <1>;
196 compatible = "sirf,prima2-uart";
197 reg = <0xb0060000 0x10000>;
198 interrupts = <18>;
199 };
200
201 uart2: uart@b0070000 {
202 cell-index = <2>;
203 compatible = "sirf,prima2-uart";
204 reg = <0xb0070000 0x10000>;
205 interrupts = <19>;
206 };
207
208 usp0: usp@b0080000 {
209 cell-index = <0>;
210 compatible = "sirf,prima2-usp";
211 reg = <0xb0080000 0x10000>;
212 interrupts = <20>;
213 };
214
215 usp1: usp@b0090000 {
216 cell-index = <1>;
217 compatible = "sirf,prima2-usp";
218 reg = <0xb0090000 0x10000>;
219 interrupts = <21>;
220 };
221
222 usp2: usp@b00a0000 {
223 cell-index = <2>;
224 compatible = "sirf,prima2-usp";
225 reg = <0xb00a0000 0x10000>;
226 interrupts = <22>;
227 };
228
229 dmac0: dma-controller@b00b0000 {
230 cell-index = <0>;
231 compatible = "sirf,prima2-dmac";
232 reg = <0xb00b0000 0x10000>;
233 interrupts = <12>;
234 };
235
236 dmac1: dma-controller@b0160000 {
237 cell-index = <1>;
238 compatible = "sirf,prima2-dmac";
239 reg = <0xb0160000 0x10000>;
240 interrupts = <13>;
241 };
242
243 vip@b00C0000 {
244 compatible = "sirf,prima2-vip";
245 reg = <0xb00C0000 0x10000>;
246 };
247
248 spi0: spi@b00d0000 {
249 cell-index = <0>;
250 compatible = "sirf,prima2-spi";
251 reg = <0xb00d0000 0x10000>;
252 interrupts = <15>;
253 };
254
255 spi1: spi@b0170000 {
256 cell-index = <1>;
257 compatible = "sirf,prima2-spi";
258 reg = <0xb0170000 0x10000>;
259 interrupts = <16>;
260 };
261
262 i2c0: i2c@b00e0000 {
263 cell-index = <0>;
264 compatible = "sirf,prima2-i2c";
265 reg = <0xb00e0000 0x10000>;
266 interrupts = <24>;
267 };
268
269 i2c1: i2c@b00f0000 {
270 cell-index = <1>;
271 compatible = "sirf,prima2-i2c";
272 reg = <0xb00f0000 0x10000>;
273 interrupts = <25>;
274 };
275
276 tsc@b0110000 {
277 compatible = "sirf,prima2-tsc";
278 reg = <0xb0110000 0x10000>;
279 interrupts = <33>;
280 };
281
282 gpio: gpio-controller@b0120000 {
283 #gpio-cells = <2>;
284 #interrupt-cells = <2>;
285 compatible = "sirf,prima2-gpio-pinmux";
286 reg = <0xb0120000 0x10000>;
287 interrupts = <43 44 45 46 47>;
288 gpio-controller;
289 interrupt-controller;
290 };
291
292 pwm@b0130000 {
293 compatible = "sirf,prima2-pwm";
294 reg = <0xb0130000 0x10000>;
295 };
296
297 efusesys@b0140000 {
298 compatible = "sirf,prima2-efuse";
299 reg = <0xb0140000 0x10000>;
300 };
301
302 pulsec@b0150000 {
303 compatible = "sirf,prima2-pulsec";
304 reg = <0xb0150000 0x10000>;
305 interrupts = <48>;
306 };
307
308 pci-iobg {
309 compatible = "sirf,prima2-pciiobg", "simple-bus";
310 #address-cells = <1>;
311 #size-cells = <1>;
312 ranges = <0x56000000 0x56000000 0x1b00000>;
313
314 sd0: sdhci@56000000 {
315 cell-index = <0>;
316 compatible = "sirf,prima2-sdhc";
317 reg = <0x56000000 0x100000>;
318 interrupts = <38>;
319 };
320
321 sd1: sdhci@56100000 {
322 cell-index = <1>;
323 compatible = "sirf,prima2-sdhc";
324 reg = <0x56100000 0x100000>;
325 interrupts = <38>;
326 };
327
328 sd2: sdhci@56200000 {
329 cell-index = <2>;
330 compatible = "sirf,prima2-sdhc";
331 reg = <0x56200000 0x100000>;
332 interrupts = <23>;
333 };
334
335 sd3: sdhci@56300000 {
336 cell-index = <3>;
337 compatible = "sirf,prima2-sdhc";
338 reg = <0x56300000 0x100000>;
339 interrupts = <23>;
340 };
341
342 sd4: sdhci@56400000 {
343 cell-index = <4>;
344 compatible = "sirf,prima2-sdhc";
345 reg = <0x56400000 0x100000>;
346 interrupts = <39>;
347 };
348
349 sd5: sdhci@56500000 {
350 cell-index = <5>;
351 compatible = "sirf,prima2-sdhc";
352 reg = <0x56500000 0x100000>;
353 interrupts = <39>;
354 };
355
356 pci-copy@57900000 {
357 compatible = "sirf,prima2-pcicp";
358 reg = <0x57900000 0x100000>;
359 interrupts = <40>;
360 };
361
362 rom-interface@57a00000 {
363 compatible = "sirf,prima2-romif";
364 reg = <0x57a00000 0x100000>;
365 };
366 };
367 };
368
369 rtc-iobg {
370 compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus";
371 #address-cells = <1>;
372 #size-cells = <1>;
373 reg = <0x80030000 0x10000>;
374
375 gpsrtc@1000 {
376 compatible = "sirf,prima2-gpsrtc";
377 reg = <0x1000 0x1000>;
378 interrupts = <55 56 57>;
379 };
380
381 sysrtc@2000 {
382 compatible = "sirf,prima2-sysrtc";
383 reg = <0x2000 0x1000>;
384 interrupts = <52 53 54>;
385 };
386
387 pwrc@3000 {
388 compatible = "sirf,prima2-pwrc";
389 reg = <0x3000 0x1000>;
390 interrupts = <32>;
391 };
392 };
393
394 uus-iobg {
395 compatible = "simple-bus";
396 #address-cells = <1>;
397 #size-cells = <1>;
398 ranges = <0xb8000000 0xb8000000 0x40000>;
399
400 usb0: usb@b00e0000 {
401 compatible = "chipidea,ci13611a-prima2";
402 reg = <0xb8000000 0x10000>;
403 interrupts = <10>;
404 };
405
406 usb1: usb@b00f0000 {
407 compatible = "chipidea,ci13611a-prima2";
408 reg = <0xb8010000 0x10000>;
409 interrupts = <11>;
410 };
411
412 sata@b00f0000 {
413 compatible = "synopsys,dwc-ahsata";
414 reg = <0xb8020000 0x10000>;
415 interrupts = <37>;
416 };
417
418 security@b00f0000 {
419 compatible = "sirf,prima2-security";
420 reg = <0xb8030000 0x10000>;
421 interrupts = <42>;
422 };
423 };
424 };
425};
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-21 19:38:13 -0400