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authorLinus Torvalds <torvalds@linux-foundation.org>2012-10-01 21:28:06 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-10-01 21:28:06 -0400
commit2a2bf85f05e42b12ea6bfe821e2d19221cf93555 (patch)
tree11abcdaef6e4f8307574056998d306d21558b6ed /arch/arm/boot/dts/imx53.dtsi
parent11801e9de26992d37cb869cc74f389b6a7677e0e (diff)
parent99261fbad0a16f105b262d7525801697588ba526 (diff)
Merge tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM soc device tree updates from Olof Johansson: "Device tree conversion and enablement branch. Mostly a bunch of new bindings and setup for various platforms, but the Via/Winchip VT8500 platform is also converted over from being 100% legacy to now use device tree for probing. More of that will come for 3.8." Trivial conflicts due to removal of vt8500 files, and one documentation file that was added with slightly different contents both here and in the USb tree. * tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (212 commits) arm: vt8500: Fixup for missing gpio.h ARM: LPC32xx: LED fix in PHY3250 DTS file ARM: dt: mmp-dma: add binding file arm: vt8500: Update arch-vt8500 to devicetree support. arm: vt8500: gpio: Devicetree support for arch-vt8500 arm: vt8500: doc: Add device tree bindings for arch-vt8500 devices arm: vt8500: clk: Add Common Clock Framework support video: vt8500: Add devicetree support for vt8500-fb and wm8505-fb serial: vt8500: Add devicetree support for vt8500-serial rtc: vt8500: Add devicetree support for vt8500-rtc arm: vt8500: Add device tree files for VIA/Wondermedia SoC's ARM: tegra: Add Avionic Design Tamonten Evaluation Carrier support ARM: tegra: Add Avionic Design Medcom-Wide support ARM: tegra: Add Avionic Design Plutux support ARM: tegra: Add Avionic Design Tamonten support ARM: tegra: dts: Add pwm label ARM: ux500: Fix SSP register address format ARM: ux500: Apply tc3589x's GPIO/IRQ properties to HREF's DT ARM: ux500: Remove redundant #gpio-cell properties from Snowball DT ARM: ux500: Add all encompassing sound node to the HREF Device Tree ...
Diffstat (limited to 'arch/arm/boot/dts/imx53.dtsi')
-rw-r--r--arch/arm/boot/dts/imx53.dtsi199
1 files changed, 198 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index cd37165edce..221cf3321b0 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -135,6 +135,34 @@
135 }; 135 };
136 }; 136 };
137 137
138 usb@53f80000 {
139 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
140 reg = <0x53f80000 0x0200>;
141 interrupts = <18>;
142 status = "disabled";
143 };
144
145 usb@53f80200 {
146 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
147 reg = <0x53f80200 0x0200>;
148 interrupts = <14>;
149 status = "disabled";
150 };
151
152 usb@53f80400 {
153 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
154 reg = <0x53f80400 0x0200>;
155 interrupts = <16>;
156 status = "disabled";
157 };
158
159 usb@53f80600 {
160 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
161 reg = <0x53f80600 0x0200>;
162 interrupts = <17>;
163 status = "disabled";
164 };
165
138 gpio1: gpio@53f84000 { 166 gpio1: gpio@53f84000 {
139 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 167 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
140 reg = <0x53f84000 0x4000>; 168 reg = <0x53f84000 0x4000>;
@@ -179,7 +207,6 @@
179 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; 207 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
180 reg = <0x53f98000 0x4000>; 208 reg = <0x53f98000 0x4000>;
181 interrupts = <58>; 209 interrupts = <58>;
182 status = "disabled";
183 }; 210 };
184 211
185 wdog@53f9c000 { /* WDOG2 */ 212 wdog@53f9c000 { /* WDOG2 */
@@ -189,6 +216,161 @@
189 status = "disabled"; 216 status = "disabled";
190 }; 217 };
191 218
219 iomuxc@53fa8000 {
220 compatible = "fsl,imx53-iomuxc";
221 reg = <0x53fa8000 0x4000>;
222
223 audmux {
224 pinctrl_audmux_1: audmuxgrp-1 {
225 fsl,pins = <
226 10 0x80000000 /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */
227 17 0x80000000 /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */
228 23 0x80000000 /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */
229 30 0x80000000 /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */
230 >;
231 };
232 };
233
234 fec {
235 pinctrl_fec_1: fecgrp-1 {
236 fsl,pins = <
237 820 0x80000000 /* MX53_PAD_FEC_MDC__FEC_MDC */
238 779 0x80000000 /* MX53_PAD_FEC_MDIO__FEC_MDIO */
239 786 0x80000000 /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */
240 791 0x80000000 /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */
241 796 0x80000000 /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */
242 799 0x80000000 /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */
243 804 0x80000000 /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */
244 808 0x80000000 /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */
245 811 0x80000000 /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */
246 816 0x80000000 /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */
247 >;
248 };
249 };
250
251 ecspi1 {
252 pinctrl_ecspi1_1: ecspi1grp-1 {
253 fsl,pins = <
254 433 0x80000000 /* MX53_PAD_EIM_D16__ECSPI1_SCLK */
255 439 0x80000000 /* MX53_PAD_EIM_D17__ECSPI1_MISO */
256 445 0x80000000 /* MX53_PAD_EIM_D18__ECSPI1_MOSI */
257 >;
258 };
259 };
260
261 esdhc1 {
262 pinctrl_esdhc1_1: esdhc1grp-1 {
263 fsl,pins = <
264 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
265 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
266 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
267 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
268 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
269 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
270 >;
271 };
272
273 pinctrl_esdhc1_2: esdhc1grp-2 {
274 fsl,pins = <
275 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
276 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
277 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
278 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
279 941 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */
280 948 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */
281 955 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */
282 962 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */
283 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
284 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
285 >;
286 };
287 };
288
289 esdhc2 {
290 pinctrl_esdhc2_1: esdhc2grp-1 {
291 fsl,pins = <
292 1038 0x1d5 /* MX53_PAD_SD2_CMD__ESDHC2_CMD */
293 1032 0x1d5 /* MX53_PAD_SD2_CLK__ESDHC2_CLK */
294 1062 0x1d5 /* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */
295 1056 0x1d5 /* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */
296 1050 0x1d5 /* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */
297 1044 0x1d5 /* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */
298 >;
299 };
300 };
301
302 esdhc3 {
303 pinctrl_esdhc3_1: esdhc3grp-1 {
304 fsl,pins = <
305 943 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */
306 950 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */
307 957 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */
308 964 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */
309 893 0x1d5 /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */
310 900 0x1d5 /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */
311 906 0x1d5 /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */
312 912 0x1d5 /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */
313 857 0x1d5 /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */
314 863 0x1d5 /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */
315 >;
316 };
317 };
318
319 i2c1 {
320 pinctrl_i2c1_1: i2c1grp-1 {
321 fsl,pins = <
322 333 0xc0000000 /* MX53_PAD_CSI0_DAT8__I2C1_SDA */
323 341 0xc0000000 /* MX53_PAD_CSI0_DAT9__I2C1_SCL */
324 >;
325 };
326 };
327
328 i2c2 {
329 pinctrl_i2c2_1: i2c2grp-1 {
330 fsl,pins = <
331 61 0xc0000000 /* MX53_PAD_KEY_ROW3__I2C2_SDA */
332 53 0xc0000000 /* MX53_PAD_KEY_COL3__I2C2_SCL */
333 >;
334 };
335 };
336
337 uart1 {
338 pinctrl_uart1_1: uart1grp-1 {
339 fsl,pins = <
340 346 0x1c5 /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */
341 354 0x1c5 /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */
342 >;
343 };
344
345 pinctrl_uart1_2: uart1grp-2 {
346 fsl,pins = <
347 828 0x1c5 /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */
348 832 0x1c5 /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */
349 >;
350 };
351 };
352
353 uart2 {
354 pinctrl_uart2_1: uart2grp-1 {
355 fsl,pins = <
356 841 0x1c5 /* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */
357 836 0x1c5 /* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */
358 >;
359 };
360 };
361
362 uart3 {
363 pinctrl_uart3_1: uart3grp-1 {
364 fsl,pins = <
365 884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */
366 888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */
367 875 0x1c5 /* MX53_PAD_PATA_DA_1__UART3_CTS */
368 880 0x1c5 /* MX53_PAD_PATA_DA_2__UART3_RTS */
369 >;
370 };
371 };
372 };
373
192 uart1: serial@53fbc000 { 374 uart1: serial@53fbc000 {
193 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 375 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
194 reg = <0x53fbc000 0x4000>; 376 reg = <0x53fbc000 0x4000>;
@@ -203,6 +385,20 @@
203 status = "disabled"; 385 status = "disabled";
204 }; 386 };
205 387
388 can1: can@53fc8000 {
389 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
390 reg = <0x53fc8000 0x4000>;
391 interrupts = <82>;
392 status = "disabled";
393 };
394
395 can2: can@53fcc000 {
396 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
397 reg = <0x53fcc000 0x4000>;
398 interrupts = <83>;
399 status = "disabled";
400 };
401
206 gpio5: gpio@53fdc000 { 402 gpio5: gpio@53fdc000 {
207 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 403 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
208 reg = <0x53fdc000 0x4000>; 404 reg = <0x53fdc000 0x4000>;
@@ -277,6 +473,7 @@
277 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; 473 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
278 reg = <0x63fb0000 0x4000>; 474 reg = <0x63fb0000 0x4000>;
279 interrupts = <6>; 475 interrupts = <6>;
476 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
280 }; 477 };
281 478
282 cspi@63fc0000 { 479 cspi@63fc0000 {
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-22 00:43:21 -0400