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authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
commitfcc9d2e5a6c89d22b8b773a64fb4ad21ac318446 (patch)
treea57612d1888735a2ec7972891b68c1ac5ec8faea /arch/alpha/include/asm/auxvec.h
parent8dea78da5cee153b8af9c07a2745f6c55057fe12 (diff)
Added missing tegra files.HEADmaster
Diffstat (limited to 'arch/alpha/include/asm/auxvec.h')
-rw-r--r--arch/alpha/include/asm/auxvec.h24
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/alpha/include/asm/auxvec.h b/arch/alpha/include/asm/auxvec.h
new file mode 100644
index 00000000000..e96fe880e31
--- /dev/null
+++ b/arch/alpha/include/asm/auxvec.h
@@ -0,0 +1,24 @@
1#ifndef __ASM_ALPHA_AUXVEC_H
2#define __ASM_ALPHA_AUXVEC_H
3
4/* Reserve these numbers for any future use of a VDSO. */
5#if 0
6#define AT_SYSINFO 32
7#define AT_SYSINFO_EHDR 33
8#endif
9
10/* More complete cache descriptions than AT_[DIU]CACHEBSIZE. If the
11 value is -1, then the cache doesn't exist. Otherwise:
12
13 bit 0-3: Cache set-associativity; 0 means fully associative.
14 bit 4-7: Log2 of cacheline size.
15 bit 8-31: Size of the entire cache >> 8.
16 bit 32-63: Reserved.
17*/
18
19#define AT_L1I_CACHESHAPE 34
20#define AT_L1D_CACHESHAPE 35
21#define AT_L2_CACHESHAPE 36
22#define AT_L3_CACHESHAPE 37
23
24#endif /* __ASM_ALPHA_AUXVEC_H */