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authorAneesh V <aneesh@ti.com>2011-12-17 06:54:25 -0500
committerBenoit Cousson <b-cousson@ti.com>2012-09-07 13:18:38 -0400
commit6bc9c66e5657a33d19559fce730bfa36112cb1cc (patch)
tree4e7ecda1a16d1006e79bc98a3b3a4da21c7e85f5 /Documentation
parent274c27b1f18060db6cc6bedad7812e5a7f97c6a4 (diff)
Documentation: dt: emif: device tree bindings for TI's EMIF sdram controller
EMIF - External Memory Interface - is an SDRAM controller used in TI SoCs. EMIF supports, based on the IP revision, one or more of DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance of the EMIF IP and memory parts attached to it. Reviewed-by: Grant Likely <grant.likely@secretlab.ca> Tested-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Aneesh V <aneesh@ti.com> [santosh.shilimkar@ti.com: Rebased against 3.6-rc] Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Benoit Cousson <b-cousson@ti.com>
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1* EMIF family of TI SDRAM controllers
2
3EMIF - External Memory Interface - is an SDRAM controller used in
4TI SoCs. EMIF supports, based on the IP revision, one or more of
5DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance
6of the EMIF IP and memory parts attached to it.
7
8Required properties:
9- compatible : Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
10 is the IP revision of the specific EMIF instance.
11
12- phy-type : <u32> indicating the DDR phy type. Following are the
13 allowed values
14 <1> : Attila PHY
15 <2> : Intelli PHY
16
17- device-handle : phandle to a "lpddr2" node representing the memory part
18
19- ti,hwmods : For TI hwmods processing and omap device creation
20 the value shall be "emif<n>" where <n> is the number of the EMIF
21 instance with base 1.
22
23Optional properties:
24- cs1-used : Have this property if CS1 of this EMIF
25 instance has a memory part attached to it. If there is a memory
26 part attached to CS1, it should be the same type as the one on CS0,
27 so there is no need to give the details of this memory part.
28
29- cal-resistor-per-cs : Have this property if the board has one
30 calibration resistor per chip-select.
31
32- hw-caps-read-idle-ctrl: Have this property if the controller
33 supports read idle window programming
34
35- hw-caps-dll-calib-ctrl: Have this property if the controller
36 supports dll calibration control
37
38- hw-caps-ll-interface : Have this property if the controller
39 has a low latency interface and corresponding interrupt events
40
41- hw-caps-temp-alert : Have this property if the controller
42 has capability for generating SDRAM temperature alerts
43
44Example:
45
46emif1: emif@0x4c000000 {
47 compatible = "ti,emif-4d";
48 ti,hwmods = "emif2";
49 phy-type = <1>;
50 device-handle = <&elpida_ECB240ABACN>;
51 cs1-used;
52 hw-caps-read-idle-ctrl;
53 hw-caps-ll-interface;
54 hw-caps-temp-alert;
55};