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authorviresh kumar <viresh.kumar@st.com>2011-02-16 01:40:28 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2011-03-09 04:49:44 -0500
commitf9324a85c10ee109022672ec72db9e2eb37050ee (patch)
tree8ad796a19197f68759b942d5844f42fc6b94c45d
parenta5abba989deceb731047425812d268daf7536575 (diff)
ARM: 6677/1: SPEAr: add IOMEM(x) definition and update declaration of MISC_BASE
Add IOMEM(x) definition, and use it with MISC_BASE for SPEAr platform. With this there is no need to typecast misc macros to (unsigned int *). Reviewed-by: Stanley Miao <stanley.miao@windriver.com> Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat
-rw-r--r--arch/arm/mach-spear3xx/include/mach/hardware.h2
-rw-r--r--arch/arm/mach-spear3xx/include/mach/misc_regs.h136
-rw-r--r--arch/arm/mach-spear6xx/include/mach/hardware.h3
-rw-r--r--arch/arm/mach-spear6xx/include/mach/misc_regs.h136
-rw-r--r--arch/arm/plat-spear/include/plat/hardware.h23
5 files changed, 163 insertions, 137 deletions
diff --git a/arch/arm/mach-spear3xx/include/mach/hardware.h b/arch/arm/mach-spear3xx/include/mach/hardware.h
index 4a86e6a3c44..490e86a6b0c 100644
--- a/arch/arm/mach-spear3xx/include/mach/hardware.h
+++ b/arch/arm/mach-spear3xx/include/mach/hardware.h
@@ -14,6 +14,8 @@
14#ifndef __MACH_HARDWARE_H 14#ifndef __MACH_HARDWARE_H
15#define __MACH_HARDWARE_H 15#define __MACH_HARDWARE_H
16 16
17#include <plat/hardware.h>
18
17/* Vitual to physical translation of statically mapped space */ 19/* Vitual to physical translation of statically mapped space */
18#define IO_ADDRESS(x) (x | 0xF0000000) 20#define IO_ADDRESS(x) (x | 0xF0000000)
19 21
diff --git a/arch/arm/mach-spear3xx/include/mach/misc_regs.h b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
index 38d767a1aba..6c919e1f9c4 100644
--- a/arch/arm/mach-spear3xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
@@ -16,14 +16,14 @@
16 16
17#include <mach/spear.h> 17#include <mach/spear.h>
18 18
19#define MISC_BASE VA_SPEAR3XX_ICM3_MISC_REG_BASE 19#define MISC_BASE IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE)
20 20
21#define SOC_CFG_CTR ((unsigned int *)(MISC_BASE + 0x000)) 21#define SOC_CFG_CTR (MISC_BASE + 0x000)
22#define DIAG_CFG_CTR ((unsigned int *)(MISC_BASE + 0x004)) 22#define DIAG_CFG_CTR (MISC_BASE + 0x004)
23#define PLL1_CTR ((unsigned int *)(MISC_BASE + 0x008)) 23#define PLL1_CTR (MISC_BASE + 0x008)
24#define PLL1_FRQ ((unsigned int *)(MISC_BASE + 0x00C)) 24#define PLL1_FRQ (MISC_BASE + 0x00C)
25#define PLL1_MOD ((unsigned int *)(MISC_BASE + 0x010)) 25#define PLL1_MOD (MISC_BASE + 0x010)
26#define PLL2_CTR ((unsigned int *)(MISC_BASE + 0x014)) 26#define PLL2_CTR (MISC_BASE + 0x014)
27/* PLL_CTR register masks */ 27/* PLL_CTR register masks */
28#define PLL_ENABLE 2 28#define PLL_ENABLE 2
29#define PLL_MODE_SHIFT 4 29#define PLL_MODE_SHIFT 4
@@ -33,7 +33,7 @@
33#define PLL_MODE_DITH_DSB 2 33#define PLL_MODE_DITH_DSB 2
34#define PLL_MODE_DITH_SSB 3 34#define PLL_MODE_DITH_SSB 3
35 35
36#define PLL2_FRQ ((unsigned int *)(MISC_BASE + 0x018)) 36#define PLL2_FRQ (MISC_BASE + 0x018)
37/* PLL FRQ register masks */ 37/* PLL FRQ register masks */
38#define PLL_DIV_N_SHIFT 0 38#define PLL_DIV_N_SHIFT 0
39#define PLL_DIV_N_MASK 0xFF 39#define PLL_DIV_N_MASK 0xFF
@@ -44,16 +44,16 @@
44#define PLL_DITH_FDBK_M_SHIFT 16 44#define PLL_DITH_FDBK_M_SHIFT 16
45#define PLL_DITH_FDBK_M_MASK 0xFFFF 45#define PLL_DITH_FDBK_M_MASK 0xFFFF
46 46
47#define PLL2_MOD ((unsigned int *)(MISC_BASE + 0x01C)) 47#define PLL2_MOD (MISC_BASE + 0x01C)
48#define PLL_CLK_CFG ((unsigned int *)(MISC_BASE + 0x020)) 48#define PLL_CLK_CFG (MISC_BASE + 0x020)
49#define CORE_CLK_CFG ((unsigned int *)(MISC_BASE + 0x024)) 49#define CORE_CLK_CFG (MISC_BASE + 0x024)
50/* CORE CLK CFG register masks */ 50/* CORE CLK CFG register masks */
51#define PLL_HCLK_RATIO_SHIFT 10 51#define PLL_HCLK_RATIO_SHIFT 10
52#define PLL_HCLK_RATIO_MASK 0x3 52#define PLL_HCLK_RATIO_MASK 0x3
53#define HCLK_PCLK_RATIO_SHIFT 8 53#define HCLK_PCLK_RATIO_SHIFT 8
54#define HCLK_PCLK_RATIO_MASK 0x3 54#define HCLK_PCLK_RATIO_MASK 0x3
55 55
56#define PERIP_CLK_CFG ((unsigned int *)(MISC_BASE + 0x028)) 56#define PERIP_CLK_CFG (MISC_BASE + 0x028)
57/* PERIP_CLK_CFG register masks */ 57/* PERIP_CLK_CFG register masks */
58#define UART_CLK_SHIFT 4 58#define UART_CLK_SHIFT 4
59#define UART_CLK_MASK 0x1 59#define UART_CLK_MASK 0x1
@@ -66,7 +66,7 @@
66#define AUX_CLK_PLL3_MASK 0 66#define AUX_CLK_PLL3_MASK 0
67#define AUX_CLK_PLL1_MASK 1 67#define AUX_CLK_PLL1_MASK 1
68 68
69#define PERIP1_CLK_ENB ((unsigned int *)(MISC_BASE + 0x02C)) 69#define PERIP1_CLK_ENB (MISC_BASE + 0x02C)
70/* PERIP1_CLK_ENB register masks */ 70/* PERIP1_CLK_ENB register masks */
71#define UART_CLK_ENB 3 71#define UART_CLK_ENB 3
72#define SSP_CLK_ENB 5 72#define SSP_CLK_ENB 5
@@ -85,33 +85,33 @@
85#define USBH_CLK_ENB 25 85#define USBH_CLK_ENB 25
86#define C3_CLK_ENB 31 86#define C3_CLK_ENB 31
87 87
88#define SOC_CORE_ID ((unsigned int *)(MISC_BASE + 0x030)) 88#define SOC_CORE_ID (MISC_BASE + 0x030)
89#define RAS_CLK_ENB ((unsigned int *)(MISC_BASE + 0x034)) 89#define RAS_CLK_ENB (MISC_BASE + 0x034)
90#define PERIP1_SOF_RST ((unsigned int *)(MISC_BASE + 0x038)) 90#define PERIP1_SOF_RST (MISC_BASE + 0x038)
91/* PERIP1_SOF_RST register masks */ 91/* PERIP1_SOF_RST register masks */
92#define JPEG_SOF_RST 8 92#define JPEG_SOF_RST 8
93 93
94#define SOC_USER_ID ((unsigned int *)(MISC_BASE + 0x03C)) 94#define SOC_USER_ID (MISC_BASE + 0x03C)
95#define RAS_SOF_RST ((unsigned int *)(MISC_BASE + 0x040)) 95#define RAS_SOF_RST (MISC_BASE + 0x040)
96#define PRSC1_CLK_CFG ((unsigned int *)(MISC_BASE + 0x044)) 96#define PRSC1_CLK_CFG (MISC_BASE + 0x044)
97#define PRSC2_CLK_CFG ((unsigned int *)(MISC_BASE + 0x048)) 97#define PRSC2_CLK_CFG (MISC_BASE + 0x048)
98#define PRSC3_CLK_CFG ((unsigned int *)(MISC_BASE + 0x04C)) 98#define PRSC3_CLK_CFG (MISC_BASE + 0x04C)
99/* gpt synthesizer register masks */ 99/* gpt synthesizer register masks */
100#define GPT_MSCALE_SHIFT 0 100#define GPT_MSCALE_SHIFT 0
101#define GPT_MSCALE_MASK 0xFFF 101#define GPT_MSCALE_MASK 0xFFF
102#define GPT_NSCALE_SHIFT 12 102#define GPT_NSCALE_SHIFT 12
103#define GPT_NSCALE_MASK 0xF 103#define GPT_NSCALE_MASK 0xF
104 104
105#define AMEM_CLK_CFG ((unsigned int *)(MISC_BASE + 0x050)) 105#define AMEM_CLK_CFG (MISC_BASE + 0x050)
106#define EXPI_CLK_CFG ((unsigned int *)(MISC_BASE + 0x054)) 106#define EXPI_CLK_CFG (MISC_BASE + 0x054)
107#define CLCD_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x05C)) 107#define CLCD_CLK_SYNT (MISC_BASE + 0x05C)
108#define FIRDA_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x060)) 108#define FIRDA_CLK_SYNT (MISC_BASE + 0x060)
109#define UART_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x064)) 109#define UART_CLK_SYNT (MISC_BASE + 0x064)
110#define GMAC_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x068)) 110#define GMAC_CLK_SYNT (MISC_BASE + 0x068)
111#define RAS1_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x06C)) 111#define RAS1_CLK_SYNT (MISC_BASE + 0x06C)
112#define RAS2_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x070)) 112#define RAS2_CLK_SYNT (MISC_BASE + 0x070)
113#define RAS3_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x074)) 113#define RAS3_CLK_SYNT (MISC_BASE + 0x074)
114#define RAS4_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x078)) 114#define RAS4_CLK_SYNT (MISC_BASE + 0x078)
115/* aux clk synthesiser register masks for irda to ras4 */ 115/* aux clk synthesiser register masks for irda to ras4 */
116#define AUX_EQ_SEL_SHIFT 30 116#define AUX_EQ_SEL_SHIFT 30
117#define AUX_EQ_SEL_MASK 1 117#define AUX_EQ_SEL_MASK 1
@@ -122,42 +122,42 @@
122#define AUX_YSCALE_SHIFT 0 122#define AUX_YSCALE_SHIFT 0
123#define AUX_YSCALE_MASK 0xFFF 123#define AUX_YSCALE_MASK 0xFFF
124 124
125#define ICM1_ARB_CFG ((unsigned int *)(MISC_BASE + 0x07C)) 125#define ICM1_ARB_CFG (MISC_BASE + 0x07C)
126#define ICM2_ARB_CFG ((unsigned int *)(MISC_BASE + 0x080)) 126#define ICM2_ARB_CFG (MISC_BASE + 0x080)
127#define ICM3_ARB_CFG ((unsigned int *)(MISC_BASE + 0x084)) 127#define ICM3_ARB_CFG (MISC_BASE + 0x084)
128#define ICM4_ARB_CFG ((unsigned int *)(MISC_BASE + 0x088)) 128#define ICM4_ARB_CFG (MISC_BASE + 0x088)
129#define ICM5_ARB_CFG ((unsigned int *)(MISC_BASE + 0x08C)) 129#define ICM5_ARB_CFG (MISC_BASE + 0x08C)
130#define ICM6_ARB_CFG ((unsigned int *)(MISC_BASE + 0x090)) 130#define ICM6_ARB_CFG (MISC_BASE + 0x090)
131#define ICM7_ARB_CFG ((unsigned int *)(MISC_BASE + 0x094)) 131#define ICM7_ARB_CFG (MISC_BASE + 0x094)
132#define ICM8_ARB_CFG ((unsigned int *)(MISC_BASE + 0x098)) 132#define ICM8_ARB_CFG (MISC_BASE + 0x098)
133#define ICM9_ARB_CFG ((unsigned int *)(MISC_BASE + 0x09C)) 133#define ICM9_ARB_CFG (MISC_BASE + 0x09C)
134#define DMA_CHN_CFG ((unsigned int *)(MISC_BASE + 0x0A0)) 134#define DMA_CHN_CFG (MISC_BASE + 0x0A0)
135#define USB2_PHY_CFG ((unsigned int *)(MISC_BASE + 0x0A4)) 135#define USB2_PHY_CFG (MISC_BASE + 0x0A4)
136#define GMAC_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0A8)) 136#define GMAC_CFG_CTR (MISC_BASE + 0x0A8)
137#define EXPI_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0AC)) 137#define EXPI_CFG_CTR (MISC_BASE + 0x0AC)
138#define PRC1_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C0)) 138#define PRC1_LOCK_CTR (MISC_BASE + 0x0C0)
139#define PRC2_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C4)) 139#define PRC2_LOCK_CTR (MISC_BASE + 0x0C4)
140#define PRC3_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C8)) 140#define PRC3_LOCK_CTR (MISC_BASE + 0x0C8)
141#define PRC4_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0CC)) 141#define PRC4_LOCK_CTR (MISC_BASE + 0x0CC)
142#define PRC1_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D0)) 142#define PRC1_IRQ_CTR (MISC_BASE + 0x0D0)
143#define PRC2_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D4)) 143#define PRC2_IRQ_CTR (MISC_BASE + 0x0D4)
144#define PRC3_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D8)) 144#define PRC3_IRQ_CTR (MISC_BASE + 0x0D8)
145#define PRC4_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0DC)) 145#define PRC4_IRQ_CTR (MISC_BASE + 0x0DC)
146#define PWRDOWN_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0E0)) 146#define PWRDOWN_CFG_CTR (MISC_BASE + 0x0E0)
147#define COMPSSTL_1V8_CFG ((unsigned int *)(MISC_BASE + 0x0E4)) 147#define COMPSSTL_1V8_CFG (MISC_BASE + 0x0E4)
148#define COMPSSTL_2V5_CFG ((unsigned int *)(MISC_BASE + 0x0E8)) 148#define COMPSSTL_2V5_CFG (MISC_BASE + 0x0E8)
149#define COMPCOR_3V3_CFG ((unsigned int *)(MISC_BASE + 0x0EC)) 149#define COMPCOR_3V3_CFG (MISC_BASE + 0x0EC)
150#define SSTLPAD_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F0)) 150#define SSTLPAD_CFG_CTR (MISC_BASE + 0x0F0)
151#define BIST1_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F4)) 151#define BIST1_CFG_CTR (MISC_BASE + 0x0F4)
152#define BIST2_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F8)) 152#define BIST2_CFG_CTR (MISC_BASE + 0x0F8)
153#define BIST3_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0FC)) 153#define BIST3_CFG_CTR (MISC_BASE + 0x0FC)
154#define BIST4_CFG_CTR ((unsigned int *)(MISC_BASE + 0x100)) 154#define BIST4_CFG_CTR (MISC_BASE + 0x100)
155#define BIST5_CFG_CTR ((unsigned int *)(MISC_BASE + 0x104)) 155#define BIST5_CFG_CTR (MISC_BASE + 0x104)
156#define BIST1_STS_RES ((unsigned int *)(MISC_BASE + 0x108)) 156#define BIST1_STS_RES (MISC_BASE + 0x108)
157#define BIST2_STS_RES ((unsigned int *)(MISC_BASE + 0x10C)) 157#define BIST2_STS_RES (MISC_BASE + 0x10C)
158#define BIST3_STS_RES ((unsigned int *)(MISC_BASE + 0x110)) 158#define BIST3_STS_RES (MISC_BASE + 0x110)
159#define BIST4_STS_RES ((unsigned int *)(MISC_BASE + 0x114)) 159#define BIST4_STS_RES (MISC_BASE + 0x114)
160#define BIST5_STS_RES ((unsigned int *)(MISC_BASE + 0x118)) 160#define BIST5_STS_RES (MISC_BASE + 0x118)
161#define SYSERR_CFG_CTR ((unsigned int *)(MISC_BASE + 0x11C)) 161#define SYSERR_CFG_CTR (MISC_BASE + 0x11C)
162 162
163#endif /* __MACH_MISC_REGS_H */ 163#endif /* __MACH_MISC_REGS_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/hardware.h b/arch/arm/mach-spear6xx/include/mach/hardware.h
index 7545116deca..0291476ca6d 100644
--- a/arch/arm/mach-spear6xx/include/mach/hardware.h
+++ b/arch/arm/mach-spear6xx/include/mach/hardware.h
@@ -14,8 +14,9 @@
14#ifndef __MACH_HARDWARE_H 14#ifndef __MACH_HARDWARE_H
15#define __MACH_HARDWARE_H 15#define __MACH_HARDWARE_H
16 16
17#include <plat/hardware.h>
18
17/* Vitual to physical translation of statically mapped space */ 19/* Vitual to physical translation of statically mapped space */
18#define IO_ADDRESS(x) (x | 0xF0000000) 20#define IO_ADDRESS(x) (x | 0xF0000000)
19 21
20#endif /* __MACH_HARDWARE_H */ 22#endif /* __MACH_HARDWARE_H */
21
diff --git a/arch/arm/mach-spear6xx/include/mach/misc_regs.h b/arch/arm/mach-spear6xx/include/mach/misc_regs.h
index 03908036b0d..d15317788d0 100644
--- a/arch/arm/mach-spear6xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear6xx/include/mach/misc_regs.h
@@ -16,14 +16,14 @@
16 16
17#include <mach/spear.h> 17#include <mach/spear.h>
18 18
19#define MISC_BASE VA_SPEAR6XX_ICM3_MISC_REG_BASE 19#define MISC_BASE IOMEM(VA_SPEAR6XX_ICM3_MISC_REG_BASE)
20 20
21#define SOC_CFG_CTR ((unsigned int *)(MISC_BASE + 0x000)) 21#define SOC_CFG_CTR (MISC_BASE + 0x000)
22#define DIAG_CFG_CTR ((unsigned int *)(MISC_BASE + 0x004)) 22#define DIAG_CFG_CTR (MISC_BASE + 0x004)
23#define PLL1_CTR ((unsigned int *)(MISC_BASE + 0x008)) 23#define PLL1_CTR (MISC_BASE + 0x008)
24#define PLL1_FRQ ((unsigned int *)(MISC_BASE + 0x00C)) 24#define PLL1_FRQ (MISC_BASE + 0x00C)
25#define PLL1_MOD ((unsigned int *)(MISC_BASE + 0x010)) 25#define PLL1_MOD (MISC_BASE + 0x010)
26#define PLL2_CTR ((unsigned int *)(MISC_BASE + 0x014)) 26#define PLL2_CTR (MISC_BASE + 0x014)
27/* PLL_CTR register masks */ 27/* PLL_CTR register masks */
28#define PLL_ENABLE 2 28#define PLL_ENABLE 2
29#define PLL_MODE_SHIFT 4 29#define PLL_MODE_SHIFT 4
@@ -33,7 +33,7 @@
33#define PLL_MODE_DITH_DSB 2 33#define PLL_MODE_DITH_DSB 2
34#define PLL_MODE_DITH_SSB 3 34#define PLL_MODE_DITH_SSB 3
35 35
36#define PLL2_FRQ ((unsigned int *)(MISC_BASE + 0x018)) 36#define PLL2_FRQ (MISC_BASE + 0x018)
37/* PLL FRQ register masks */ 37/* PLL FRQ register masks */
38#define PLL_DIV_N_SHIFT 0 38#define PLL_DIV_N_SHIFT 0
39#define PLL_DIV_N_MASK 0xFF 39#define PLL_DIV_N_MASK 0xFF
@@ -44,16 +44,16 @@
44#define PLL_DITH_FDBK_M_SHIFT 16 44#define PLL_DITH_FDBK_M_SHIFT 16
45#define PLL_DITH_FDBK_M_MASK 0xFFFF 45#define PLL_DITH_FDBK_M_MASK 0xFFFF
46 46
47#define PLL2_MOD ((unsigned int *)(MISC_BASE + 0x01C)) 47#define PLL2_MOD (MISC_BASE + 0x01C)
48#define PLL_CLK_CFG ((unsigned int *)(MISC_BASE + 0x020)) 48#define PLL_CLK_CFG (MISC_BASE + 0x020)
49#define CORE_CLK_CFG ((unsigned int *)(MISC_BASE + 0x024)) 49#define CORE_CLK_CFG (MISC_BASE + 0x024)
50/* CORE CLK CFG register masks */ 50/* CORE CLK CFG register masks */
51#define PLL_HCLK_RATIO_SHIFT 10 51#define PLL_HCLK_RATIO_SHIFT 10
52#define PLL_HCLK_RATIO_MASK 0x3 52#define PLL_HCLK_RATIO_MASK 0x3
53#define HCLK_PCLK_RATIO_SHIFT 8 53#define HCLK_PCLK_RATIO_SHIFT 8
54#define HCLK_PCLK_RATIO_MASK 0x3 54#define HCLK_PCLK_RATIO_MASK 0x3
55 55
56#define PERIP_CLK_CFG ((unsigned int *)(MISC_BASE + 0x028)) 56#define PERIP_CLK_CFG (MISC_BASE + 0x028)
57/* PERIP_CLK_CFG register masks */ 57/* PERIP_CLK_CFG register masks */
58#define CLCD_CLK_SHIFT 2 58#define CLCD_CLK_SHIFT 2
59#define CLCD_CLK_MASK 0x3 59#define CLCD_CLK_MASK 0x3
@@ -69,7 +69,7 @@
69#define AUX_CLK_PLL3_MASK 0 69#define AUX_CLK_PLL3_MASK 0
70#define AUX_CLK_PLL1_MASK 1 70#define AUX_CLK_PLL1_MASK 1
71 71
72#define PERIP1_CLK_ENB ((unsigned int *)(MISC_BASE + 0x02C)) 72#define PERIP1_CLK_ENB (MISC_BASE + 0x02C)
73/* PERIP1_CLK_ENB register masks */ 73/* PERIP1_CLK_ENB register masks */
74#define UART0_CLK_ENB 3 74#define UART0_CLK_ENB 3
75#define UART1_CLK_ENB 4 75#define UART1_CLK_ENB 4
@@ -95,33 +95,33 @@
95#define USBH0_CLK_ENB 25 95#define USBH0_CLK_ENB 25
96#define USBH1_CLK_ENB 26 96#define USBH1_CLK_ENB 26
97 97
98#define SOC_CORE_ID ((unsigned int *)(MISC_BASE + 0x030)) 98#define SOC_CORE_ID (MISC_BASE + 0x030)
99#define RAS_CLK_ENB ((unsigned int *)(MISC_BASE + 0x034)) 99#define RAS_CLK_ENB (MISC_BASE + 0x034)
100#define PERIP1_SOF_RST ((unsigned int *)(MISC_BASE + 0x038)) 100#define PERIP1_SOF_RST (MISC_BASE + 0x038)
101/* PERIP1_SOF_RST register masks */ 101/* PERIP1_SOF_RST register masks */
102#define JPEG_SOF_RST 8 102#define JPEG_SOF_RST 8
103 103
104#define SOC_USER_ID ((unsigned int *)(MISC_BASE + 0x03C)) 104#define SOC_USER_ID (MISC_BASE + 0x03C)
105#define RAS_SOF_RST ((unsigned int *)(MISC_BASE + 0x040)) 105#define RAS_SOF_RST (MISC_BASE + 0x040)
106#define PRSC1_CLK_CFG ((unsigned int *)(MISC_BASE + 0x044)) 106#define PRSC1_CLK_CFG (MISC_BASE + 0x044)
107#define PRSC2_CLK_CFG ((unsigned int *)(MISC_BASE + 0x048)) 107#define PRSC2_CLK_CFG (MISC_BASE + 0x048)
108#define PRSC3_CLK_CFG ((unsigned int *)(MISC_BASE + 0x04C)) 108#define PRSC3_CLK_CFG (MISC_BASE + 0x04C)
109/* gpt synthesizer register masks */ 109/* gpt synthesizer register masks */
110#define GPT_MSCALE_SHIFT 0 110#define GPT_MSCALE_SHIFT 0
111#define GPT_MSCALE_MASK 0xFFF 111#define GPT_MSCALE_MASK 0xFFF
112#define GPT_NSCALE_SHIFT 12 112#define GPT_NSCALE_SHIFT 12
113#define GPT_NSCALE_MASK 0xF 113#define GPT_NSCALE_MASK 0xF
114 114
115#define AMEM_CLK_CFG ((unsigned int *)(MISC_BASE + 0x050)) 115#define AMEM_CLK_CFG (MISC_BASE + 0x050)
116#define EXPI_CLK_CFG ((unsigned int *)(MISC_BASE + 0x054)) 116#define EXPI_CLK_CFG (MISC_BASE + 0x054)
117#define CLCD_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x05C)) 117#define CLCD_CLK_SYNT (MISC_BASE + 0x05C)
118#define FIRDA_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x060)) 118#define FIRDA_CLK_SYNT (MISC_BASE + 0x060)
119#define UART_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x064)) 119#define UART_CLK_SYNT (MISC_BASE + 0x064)
120#define GMAC_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x068)) 120#define GMAC_CLK_SYNT (MISC_BASE + 0x068)
121#define RAS1_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x06C)) 121#define RAS1_CLK_SYNT (MISC_BASE + 0x06C)
122#define RAS2_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x070)) 122#define RAS2_CLK_SYNT (MISC_BASE + 0x070)
123#define RAS3_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x074)) 123#define RAS3_CLK_SYNT (MISC_BASE + 0x074)
124#define RAS4_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x078)) 124#define RAS4_CLK_SYNT (MISC_BASE + 0x078)
125/* aux clk synthesiser register masks for irda to ras4 */ 125/* aux clk synthesiser register masks for irda to ras4 */
126#define AUX_EQ_SEL_SHIFT 30 126#define AUX_EQ_SEL_SHIFT 30
127#define AUX_EQ_SEL_MASK 1 127#define AUX_EQ_SEL_MASK 1
@@ -132,42 +132,42 @@
132#define AUX_YSCALE_SHIFT 0 132#define AUX_YSCALE_SHIFT 0
133#define AUX_YSCALE_MASK 0xFFF 133#define AUX_YSCALE_MASK 0xFFF
134 134
135#define ICM1_ARB_CFG ((unsigned int *)(MISC_BASE + 0x07C)) 135#define ICM1_ARB_CFG (MISC_BASE + 0x07C)
136#define ICM2_ARB_CFG ((unsigned int *)(MISC_BASE + 0x080)) 136#define ICM2_ARB_CFG (MISC_BASE + 0x080)
137#define ICM3_ARB_CFG ((unsigned int *)(MISC_BASE + 0x084)) 137#define ICM3_ARB_CFG (MISC_BASE + 0x084)
138#define ICM4_ARB_CFG ((unsigned int *)(MISC_BASE + 0x088)) 138#define ICM4_ARB_CFG (MISC_BASE + 0x088)
139#define ICM5_ARB_CFG ((unsigned int *)(MISC_BASE + 0x08C)) 139#define ICM5_ARB_CFG (MISC_BASE + 0x08C)
140#define ICM6_ARB_CFG ((unsigned int *)(MISC_BASE + 0x090)) 140#define ICM6_ARB_CFG (MISC_BASE + 0x090)
141#define ICM7_ARB_CFG ((unsigned int *)(MISC_BASE + 0x094)) 141#define ICM7_ARB_CFG (MISC_BASE + 0x094)
142#define ICM8_ARB_CFG ((unsigned int *)(MISC_BASE + 0x098)) 142#define ICM8_ARB_CFG (MISC_BASE + 0x098)
143#define ICM9_ARB_CFG ((unsigned int *)(MISC_BASE + 0x09C)) 143#define ICM9_ARB_CFG (MISC_BASE + 0x09C)
144#define DMA_CHN_CFG ((unsigned int *)(MISC_BASE + 0x0A0)) 144#define DMA_CHN_CFG (MISC_BASE + 0x0A0)
145#define USB2_PHY_CFG ((unsigned int *)(MISC_BASE + 0x0A4)) 145#define USB2_PHY_CFG (MISC_BASE + 0x0A4)
146#define GMAC_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0A8)) 146#define GMAC_CFG_CTR (MISC_BASE + 0x0A8)
147#define EXPI_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0AC)) 147#define EXPI_CFG_CTR (MISC_BASE + 0x0AC)
148#define PRC1_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C0)) 148#define PRC1_LOCK_CTR (MISC_BASE + 0x0C0)
149#define PRC2_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C4)) 149#define PRC2_LOCK_CTR (MISC_BASE + 0x0C4)
150#define PRC3_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C8)) 150#define PRC3_LOCK_CTR (MISC_BASE + 0x0C8)
151#define PRC4_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0CC)) 151#define PRC4_LOCK_CTR (MISC_BASE + 0x0CC)
152#define PRC1_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D0)) 152#define PRC1_IRQ_CTR (MISC_BASE + 0x0D0)
153#define PRC2_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D4)) 153#define PRC2_IRQ_CTR (MISC_BASE + 0x0D4)
154#define PRC3_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D8)) 154#define PRC3_IRQ_CTR (MISC_BASE + 0x0D8)
155#define PRC4_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0DC)) 155#define PRC4_IRQ_CTR (MISC_BASE + 0x0DC)
156#define PWRDOWN_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0E0)) 156#define PWRDOWN_CFG_CTR (MISC_BASE + 0x0E0)
157#define COMPSSTL_1V8_CFG ((unsigned int *)(MISC_BASE + 0x0E4)) 157#define COMPSSTL_1V8_CFG (MISC_BASE + 0x0E4)
158#define COMPSSTL_2V5_CFG ((unsigned int *)(MISC_BASE + 0x0E8)) 158#define COMPSSTL_2V5_CFG (MISC_BASE + 0x0E8)
159#define COMPCOR_3V3_CFG ((unsigned int *)(MISC_BASE + 0x0EC)) 159#define COMPCOR_3V3_CFG (MISC_BASE + 0x0EC)
160#define SSTLPAD_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F0)) 160#define SSTLPAD_CFG_CTR (MISC_BASE + 0x0F0)
161#define BIST1_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F4)) 161#define BIST1_CFG_CTR (MISC_BASE + 0x0F4)
162#define BIST2_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F8)) 162#define BIST2_CFG_CTR (MISC_BASE + 0x0F8)
163#define BIST3_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0FC)) 163#define BIST3_CFG_CTR (MISC_BASE + 0x0FC)
164#define BIST4_CFG_CTR ((unsigned int *)(MISC_BASE + 0x100)) 164#define BIST4_CFG_CTR (MISC_BASE + 0x100)
165#define BIST5_CFG_CTR ((unsigned int *)(MISC_BASE + 0x104)) 165#define BIST5_CFG_CTR (MISC_BASE + 0x104)
166#define BIST1_STS_RES ((unsigned int *)(MISC_BASE + 0x108)) 166#define BIST1_STS_RES (MISC_BASE + 0x108)
167#define BIST2_STS_RES ((unsigned int *)(MISC_BASE + 0x10C)) 167#define BIST2_STS_RES (MISC_BASE + 0x10C)
168#define BIST3_STS_RES ((unsigned int *)(MISC_BASE + 0x110)) 168#define BIST3_STS_RES (MISC_BASE + 0x110)
169#define BIST4_STS_RES ((unsigned int *)(MISC_BASE + 0x114)) 169#define BIST4_STS_RES (MISC_BASE + 0x114)
170#define BIST5_STS_RES ((unsigned int *)(MISC_BASE + 0x118)) 170#define BIST5_STS_RES (MISC_BASE + 0x118)
171#define SYSERR_CFG_CTR ((unsigned int *)(MISC_BASE + 0x11C)) 171#define SYSERR_CFG_CTR (MISC_BASE + 0x11C)
172 172
173#endif /* __MACH_MISC_REGS_H */ 173#endif /* __MACH_MISC_REGS_H */
diff --git a/arch/arm/plat-spear/include/plat/hardware.h b/arch/arm/plat-spear/include/plat/hardware.h
new file mode 100644
index 00000000000..66d677225d1
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/hardware.h
@@ -0,0 +1,23 @@
1/*
2 * arch/arm/plat-spear/include/plat/hardware.h
3 *
4 * Hardware definitions for SPEAr
5 *
6 * Copyright (C) 2010 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __PLAT_HARDWARE_H
15#define __PLAT_HARDWARE_H
16
17#ifndef __ASSEMBLY__
18#define IOMEM(x) ((void __iomem __force *)(x))
19#else
20#define IOMEM(x) (x)
21#endif
22
23#endif /* __PLAT_HARDWARE_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-19 20:54:26 -0400