diff options
author | Manuel Lauss <manuel.lauss@googlemail.com> | 2011-12-08 05:42:15 -0500 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2011-12-08 05:42:15 -0500 |
commit | f267c882c73db2f8d77b10902450666044b16633 (patch) | |
tree | 93de1007011718941b9d552ee381ec2791beada4 | |
parent | 2a32daf117bdd1958d9297b19f1684737e742723 (diff) |
MIPS: Alchemy: irq: register pm at irq init time
No need for a device_initcall.
Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2934/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r-- | arch/mips/alchemy/common/gpioint.c | 74 | ||||
-rw-r--r-- | arch/mips/alchemy/common/irq.c | 113 |
2 files changed, 91 insertions, 96 deletions
diff --git a/arch/mips/alchemy/common/gpioint.c b/arch/mips/alchemy/common/gpioint.c index b8cd3364ff6..5d7729a5990 100644 --- a/arch/mips/alchemy/common/gpioint.c +++ b/arch/mips/alchemy/common/gpioint.c | |||
@@ -278,41 +278,7 @@ static int au1300_gpic_settype(struct irq_data *d, unsigned int type) | |||
278 | return 0; | 278 | return 0; |
279 | } | 279 | } |
280 | 280 | ||
281 | static void __init alchemy_gpic_init_irq(const struct gpic_devint_data *dints) | 281 | /******************************************************************************/ |
282 | { | ||
283 | int i; | ||
284 | void __iomem *bank_base; | ||
285 | |||
286 | mips_cpu_irq_init(); | ||
287 | |||
288 | /* disable & ack all possible interrupt sources */ | ||
289 | for (i = 0; i < 4; i++) { | ||
290 | bank_base = AU1300_GPIC_ADDR + (i * 4); | ||
291 | __raw_writel(~0UL, bank_base + AU1300_GPIC_IDIS); | ||
292 | wmb(); | ||
293 | __raw_writel(~0UL, bank_base + AU1300_GPIC_IPEND); | ||
294 | wmb(); | ||
295 | } | ||
296 | |||
297 | /* register an irq_chip for them, with 2nd highest priority */ | ||
298 | for (i = ALCHEMY_GPIC_INT_BASE; i <= ALCHEMY_GPIC_INT_LAST; i++) { | ||
299 | au1300_set_irq_priority(i, 1); | ||
300 | au1300_gpic_settype(irq_get_irq_data(i), IRQ_TYPE_NONE); | ||
301 | } | ||
302 | |||
303 | /* setup known on-chip sources */ | ||
304 | while ((i = dints->irq) != -1) { | ||
305 | au1300_gpic_settype(irq_get_irq_data(i), dints->type); | ||
306 | au1300_set_irq_priority(i, dints->prio); | ||
307 | |||
308 | if (dints->internal) | ||
309 | au1300_pinfunc_to_dev(i - ALCHEMY_GPIC_INT_BASE); | ||
310 | |||
311 | dints++; | ||
312 | } | ||
313 | |||
314 | set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3); | ||
315 | } | ||
316 | 282 | ||
317 | static unsigned long alchemy_gpic_pmdata[ALCHEMY_GPIC_INT_NUM + 6]; | 283 | static unsigned long alchemy_gpic_pmdata[ALCHEMY_GPIC_INT_NUM + 6]; |
318 | 284 | ||
@@ -383,6 +349,43 @@ static struct syscore_ops alchemy_gpic_pmops = { | |||
383 | .resume = alchemy_gpic_resume, | 349 | .resume = alchemy_gpic_resume, |
384 | }; | 350 | }; |
385 | 351 | ||
352 | static void __init alchemy_gpic_init_irq(const struct gpic_devint_data *dints) | ||
353 | { | ||
354 | int i; | ||
355 | void __iomem *bank_base; | ||
356 | |||
357 | register_syscore_ops(&alchemy_gpic_pmops); | ||
358 | mips_cpu_irq_init(); | ||
359 | |||
360 | /* disable & ack all possible interrupt sources */ | ||
361 | for (i = 0; i < 4; i++) { | ||
362 | bank_base = AU1300_GPIC_ADDR + (i * 4); | ||
363 | __raw_writel(~0UL, bank_base + AU1300_GPIC_IDIS); | ||
364 | wmb(); | ||
365 | __raw_writel(~0UL, bank_base + AU1300_GPIC_IPEND); | ||
366 | wmb(); | ||
367 | } | ||
368 | |||
369 | /* register an irq_chip for them, with 2nd highest priority */ | ||
370 | for (i = ALCHEMY_GPIC_INT_BASE; i <= ALCHEMY_GPIC_INT_LAST; i++) { | ||
371 | au1300_set_irq_priority(i, 1); | ||
372 | au1300_gpic_settype(irq_get_irq_data(i), IRQ_TYPE_NONE); | ||
373 | } | ||
374 | |||
375 | /* setup known on-chip sources */ | ||
376 | while ((i = dints->irq) != -1) { | ||
377 | au1300_gpic_settype(irq_get_irq_data(i), dints->type); | ||
378 | au1300_set_irq_priority(i, dints->prio); | ||
379 | |||
380 | if (dints->internal) | ||
381 | au1300_pinfunc_to_dev(i - ALCHEMY_GPIC_INT_BASE); | ||
382 | |||
383 | dints++; | ||
384 | } | ||
385 | |||
386 | set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3); | ||
387 | } | ||
388 | |||
386 | /**********************************************************************/ | 389 | /**********************************************************************/ |
387 | 390 | ||
388 | void __init arch_init_irq(void) | 391 | void __init arch_init_irq(void) |
@@ -390,7 +393,6 @@ void __init arch_init_irq(void) | |||
390 | switch (alchemy_get_cputype()) { | 393 | switch (alchemy_get_cputype()) { |
391 | case ALCHEMY_CPU_AU1300: | 394 | case ALCHEMY_CPU_AU1300: |
392 | alchemy_gpic_init_irq(&au1300_devints[0]); | 395 | alchemy_gpic_init_irq(&au1300_devints[0]); |
393 | register_syscore_ops(&alchemy_gpic_pmops); | ||
394 | break; | 396 | break; |
395 | } | 397 | } |
396 | } | 398 | } |
diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c index 2a94a64b733..f206e24961c 100644 --- a/arch/mips/alchemy/common/irq.c +++ b/arch/mips/alchemy/common/irq.c | |||
@@ -510,6 +510,58 @@ static inline void ic_init(void __iomem *base) | |||
510 | wmb(); | 510 | wmb(); |
511 | } | 511 | } |
512 | 512 | ||
513 | static unsigned long alchemy_ic_pmdata[7 * 2]; | ||
514 | |||
515 | static inline void alchemy_ic_suspend_one(void __iomem *base, unsigned long *d) | ||
516 | { | ||
517 | d[0] = __raw_readl(base + IC_CFG0RD); | ||
518 | d[1] = __raw_readl(base + IC_CFG1RD); | ||
519 | d[2] = __raw_readl(base + IC_CFG2RD); | ||
520 | d[3] = __raw_readl(base + IC_SRCRD); | ||
521 | d[4] = __raw_readl(base + IC_ASSIGNRD); | ||
522 | d[5] = __raw_readl(base + IC_WAKERD); | ||
523 | d[6] = __raw_readl(base + IC_MASKRD); | ||
524 | ic_init(base); /* shut it up too while at it */ | ||
525 | } | ||
526 | |||
527 | static inline void alchemy_ic_resume_one(void __iomem *base, unsigned long *d) | ||
528 | { | ||
529 | ic_init(base); | ||
530 | |||
531 | __raw_writel(d[0], base + IC_CFG0SET); | ||
532 | __raw_writel(d[1], base + IC_CFG1SET); | ||
533 | __raw_writel(d[2], base + IC_CFG2SET); | ||
534 | __raw_writel(d[3], base + IC_SRCSET); | ||
535 | __raw_writel(d[4], base + IC_ASSIGNSET); | ||
536 | __raw_writel(d[5], base + IC_WAKESET); | ||
537 | wmb(); | ||
538 | |||
539 | __raw_writel(d[6], base + IC_MASKSET); | ||
540 | wmb(); | ||
541 | } | ||
542 | |||
543 | static int alchemy_ic_suspend(void) | ||
544 | { | ||
545 | alchemy_ic_suspend_one((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR), | ||
546 | alchemy_ic_pmdata); | ||
547 | alchemy_ic_suspend_one((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR), | ||
548 | &alchemy_ic_pmdata[7]); | ||
549 | return 0; | ||
550 | } | ||
551 | |||
552 | static void alchemy_ic_resume(void) | ||
553 | { | ||
554 | alchemy_ic_resume_one((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR), | ||
555 | &alchemy_ic_pmdata[7]); | ||
556 | alchemy_ic_resume_one((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR), | ||
557 | alchemy_ic_pmdata); | ||
558 | } | ||
559 | |||
560 | static struct syscore_ops alchemy_ic_syscore_ops = { | ||
561 | .suspend = alchemy_ic_suspend, | ||
562 | .resume = alchemy_ic_resume, | ||
563 | }; | ||
564 | |||
513 | static void __init au1000_init_irq(struct au1xxx_irqmap *map) | 565 | static void __init au1000_init_irq(struct au1xxx_irqmap *map) |
514 | { | 566 | { |
515 | unsigned int bit, irq_nr; | 567 | unsigned int bit, irq_nr; |
@@ -517,6 +569,7 @@ static void __init au1000_init_irq(struct au1xxx_irqmap *map) | |||
517 | 569 | ||
518 | ic_init((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR)); | 570 | ic_init((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR)); |
519 | ic_init((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR)); | 571 | ic_init((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR)); |
572 | register_syscore_ops(&alchemy_ic_syscore_ops); | ||
520 | mips_cpu_irq_init(); | 573 | mips_cpu_irq_init(); |
521 | 574 | ||
522 | /* register all 64 possible IC0+IC1 irq sources as type "none". | 575 | /* register all 64 possible IC0+IC1 irq sources as type "none". |
@@ -573,63 +626,3 @@ void __init arch_init_irq(void) | |||
573 | break; | 626 | break; |
574 | } | 627 | } |
575 | } | 628 | } |
576 | |||
577 | |||
578 | static unsigned long alchemy_ic_pmdata[7 * 2]; | ||
579 | |||
580 | static inline void alchemy_ic_suspend_one(void __iomem *base, unsigned long *d) | ||
581 | { | ||
582 | d[0] = __raw_readl(base + IC_CFG0RD); | ||
583 | d[1] = __raw_readl(base + IC_CFG1RD); | ||
584 | d[2] = __raw_readl(base + IC_CFG2RD); | ||
585 | d[3] = __raw_readl(base + IC_SRCRD); | ||
586 | d[4] = __raw_readl(base + IC_ASSIGNRD); | ||
587 | d[5] = __raw_readl(base + IC_WAKERD); | ||
588 | d[6] = __raw_readl(base + IC_MASKRD); | ||
589 | ic_init(base); /* shut it up too while at it */ | ||
590 | } | ||
591 | |||
592 | static inline void alchemy_ic_resume_one(void __iomem *base, unsigned long *d) | ||
593 | { | ||
594 | ic_init(base); | ||
595 | |||
596 | __raw_writel(d[0], base + IC_CFG0SET); | ||
597 | __raw_writel(d[1], base + IC_CFG1SET); | ||
598 | __raw_writel(d[2], base + IC_CFG2SET); | ||
599 | __raw_writel(d[3], base + IC_SRCSET); | ||
600 | __raw_writel(d[4], base + IC_ASSIGNSET); | ||
601 | __raw_writel(d[5], base + IC_WAKESET); | ||
602 | wmb(); | ||
603 | |||
604 | __raw_writel(d[6], base + IC_MASKSET); | ||
605 | wmb(); | ||
606 | } | ||
607 | |||
608 | static int alchemy_ic_suspend(void) | ||
609 | { | ||
610 | alchemy_ic_suspend_one((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR), | ||
611 | alchemy_ic_pmdata); | ||
612 | alchemy_ic_suspend_one((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR), | ||
613 | &alchemy_ic_pmdata[7]); | ||
614 | return 0; | ||
615 | } | ||
616 | |||
617 | static void alchemy_ic_resume(void) | ||
618 | { | ||
619 | alchemy_ic_resume_one((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR), | ||
620 | &alchemy_ic_pmdata[7]); | ||
621 | alchemy_ic_resume_one((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR), | ||
622 | alchemy_ic_pmdata); | ||
623 | } | ||
624 | |||
625 | static struct syscore_ops alchemy_ic_syscore_ops = { | ||
626 | .suspend = alchemy_ic_suspend, | ||
627 | .resume = alchemy_ic_resume, | ||
628 | }; | ||
629 | |||
630 | static int __init alchemy_ic_pm_init(void) | ||
631 | { | ||
632 | register_syscore_ops(&alchemy_ic_syscore_ops); | ||
633 | return 0; | ||
634 | } | ||
635 | device_initcall(alchemy_ic_pm_init); | ||