diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2010-10-27 22:04:36 -0400 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2010-10-27 22:04:36 -0400 |
| commit | e3e1288e86a07cdeb0aee5860a2dff111c6eff79 (patch) | |
| tree | cd22f8051a456c9d2b95698b6fe402776a67469b | |
| parent | 9ae6d039224def926656206725ae6e89d1331417 (diff) | |
| parent | 964dc256bb91e990277010a3f6dc66daa130be8b (diff) | |
Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx
* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx: (48 commits)
DMAENGINE: move COH901318 to arch_initcall
dma: imx-dma: fix signedness bug
dma/timberdale: simplify conditional
ste_dma40: remove channel_type
ste_dma40: remove enum for endianess
ste_dma40: remove TIM_FOR_LINK option
ste_dma40: move mode_opt to separate config
ste_dma40: move channel mode to a separate field
ste_dma40: move priority to separate field
ste_dma40: add variable to indicate valid dma_cfg
async_tx: make async_tx channel switching opt-in
move async raid6 test to lib/Kconfig.debug
dmaengine: Add Freescale i.MX1/21/27 DMA driver
intel_mid_dma: change the slave interface
intel_mid_dma: fix the WARN_ONs
intel_mid_dma: Add sg list support to DMA driver
intel_mid_dma: Allow DMAC2 to share interrupt
intel_mid_dma: Allow IRQ sharing
intel_mid_dma: Add runtime PM support
DMAENGINE: define a dummy filter function for ste_dma40
...
25 files changed, 5716 insertions, 1159 deletions
diff --git a/arch/arm/mach-imx/include/mach/dma-v1.h b/arch/arm/mach-imx/include/mach/dma-v1.h index 287431cc13e..ac6fd713828 100644 --- a/arch/arm/mach-imx/include/mach/dma-v1.h +++ b/arch/arm/mach-imx/include/mach/dma-v1.h | |||
| @@ -27,6 +27,8 @@ | |||
| 27 | 27 | ||
| 28 | #define imx_has_dma_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27()) | 28 | #define imx_has_dma_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27()) |
| 29 | 29 | ||
| 30 | #include <mach/dma.h> | ||
| 31 | |||
| 30 | #define IMX_DMA_CHANNELS 16 | 32 | #define IMX_DMA_CHANNELS 16 |
| 31 | 33 | ||
| 32 | #define DMA_MODE_READ 0 | 34 | #define DMA_MODE_READ 0 |
| @@ -96,12 +98,6 @@ int imx_dma_request(int channel, const char *name); | |||
| 96 | 98 | ||
| 97 | void imx_dma_free(int channel); | 99 | void imx_dma_free(int channel); |
| 98 | 100 | ||
| 99 | enum imx_dma_prio { | ||
| 100 | DMA_PRIO_HIGH = 0, | ||
| 101 | DMA_PRIO_MEDIUM = 1, | ||
| 102 | DMA_PRIO_LOW = 2 | ||
| 103 | }; | ||
| 104 | |||
| 105 | int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio); | 101 | int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio); |
| 106 | 102 | ||
| 107 | #endif /* __MACH_DMA_V1_H__ */ | 103 | #endif /* __MACH_DMA_V1_H__ */ |
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c index cbbe69a76a7..4a94be3304b 100644 --- a/arch/arm/mach-ux500/devices-db8500.c +++ b/arch/arm/mach-ux500/devices-db8500.c | |||
| @@ -208,35 +208,25 @@ static struct resource dma40_resources[] = { | |||
| 208 | 208 | ||
| 209 | /* Default configuration for physcial memcpy */ | 209 | /* Default configuration for physcial memcpy */ |
| 210 | struct stedma40_chan_cfg dma40_memcpy_conf_phy = { | 210 | struct stedma40_chan_cfg dma40_memcpy_conf_phy = { |
| 211 | .channel_type = (STEDMA40_CHANNEL_IN_PHY_MODE | | 211 | .mode = STEDMA40_MODE_PHYSICAL, |
| 212 | STEDMA40_LOW_PRIORITY_CHANNEL | | ||
| 213 | STEDMA40_PCHAN_BASIC_MODE), | ||
| 214 | .dir = STEDMA40_MEM_TO_MEM, | 212 | .dir = STEDMA40_MEM_TO_MEM, |
| 215 | 213 | ||
| 216 | .src_info.endianess = STEDMA40_LITTLE_ENDIAN, | ||
| 217 | .src_info.data_width = STEDMA40_BYTE_WIDTH, | 214 | .src_info.data_width = STEDMA40_BYTE_WIDTH, |
| 218 | .src_info.psize = STEDMA40_PSIZE_PHY_1, | 215 | .src_info.psize = STEDMA40_PSIZE_PHY_1, |
| 219 | .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, | 216 | .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, |
| 220 | 217 | ||
| 221 | .dst_info.endianess = STEDMA40_LITTLE_ENDIAN, | ||
| 222 | .dst_info.data_width = STEDMA40_BYTE_WIDTH, | 218 | .dst_info.data_width = STEDMA40_BYTE_WIDTH, |
| 223 | .dst_info.psize = STEDMA40_PSIZE_PHY_1, | 219 | .dst_info.psize = STEDMA40_PSIZE_PHY_1, |
| 224 | .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, | 220 | .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, |
| 225 | }; | 221 | }; |
| 226 | /* Default configuration for logical memcpy */ | 222 | /* Default configuration for logical memcpy */ |
| 227 | struct stedma40_chan_cfg dma40_memcpy_conf_log = { | 223 | struct stedma40_chan_cfg dma40_memcpy_conf_log = { |
| 228 | .channel_type = (STEDMA40_CHANNEL_IN_LOG_MODE | | ||
| 229 | STEDMA40_LOW_PRIORITY_CHANNEL | | ||
| 230 | STEDMA40_LCHAN_SRC_LOG_DST_LOG | | ||
| 231 | STEDMA40_NO_TIM_FOR_LINK), | ||
| 232 | .dir = STEDMA40_MEM_TO_MEM, | 224 | .dir = STEDMA40_MEM_TO_MEM, |
| 233 | 225 | ||
| 234 | .src_info.endianess = STEDMA40_LITTLE_ENDIAN, | ||
| 235 | .src_info.data_width = STEDMA40_BYTE_WIDTH, | 226 | .src_info.data_width = STEDMA40_BYTE_WIDTH, |
| 236 | .src_info.psize = STEDMA40_PSIZE_LOG_1, | 227 | .src_info.psize = STEDMA40_PSIZE_LOG_1, |
| 237 | .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, | 228 | .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, |
| 238 | 229 | ||
| 239 | .dst_info.endianess = STEDMA40_LITTLE_ENDIAN, | ||
| 240 | .dst_info.data_width = STEDMA40_BYTE_WIDTH, | 230 | .dst_info.data_width = STEDMA40_BYTE_WIDTH, |
| 241 | .dst_info.psize = STEDMA40_PSIZE_LOG_1, | 231 | .dst_info.psize = STEDMA40_PSIZE_LOG_1, |
| 242 | .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, | 232 | .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, |
| @@ -269,7 +259,6 @@ static struct stedma40_platform_data dma40_plat_data = { | |||
| 269 | .memcpy_len = ARRAY_SIZE(dma40_memcpy_event), | 259 | .memcpy_len = ARRAY_SIZE(dma40_memcpy_event), |
| 270 | .memcpy_conf_phy = &dma40_memcpy_conf_phy, | 260 | .memcpy_conf_phy = &dma40_memcpy_conf_phy, |
| 271 | .memcpy_conf_log = &dma40_memcpy_conf_log, | 261 | .memcpy_conf_log = &dma40_memcpy_conf_log, |
| 272 | .llis_per_log = 8, | ||
| 273 | .disabled_channels = {-1}, | 262 | .disabled_channels = {-1}, |
| 274 | }; | 263 | }; |
| 275 | 264 | ||
diff --git a/arch/arm/plat-mxc/include/mach/dma.h b/arch/arm/plat-mxc/include/mach/dma.h new file mode 100644 index 00000000000..ef7751546f5 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/dma.h | |||
| @@ -0,0 +1,67 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef __ASM_ARCH_MXC_DMA_H__ | ||
| 10 | #define __ASM_ARCH_MXC_DMA_H__ | ||
| 11 | |||
| 12 | #include <linux/scatterlist.h> | ||
| 13 | #include <linux/device.h> | ||
| 14 | #include <linux/dmaengine.h> | ||
| 15 | |||
| 16 | /* | ||
| 17 | * This enumerates peripheral types. Used for SDMA. | ||
| 18 | */ | ||
| 19 | enum sdma_peripheral_type { | ||
| 20 | IMX_DMATYPE_SSI, /* MCU domain SSI */ | ||
| 21 | IMX_DMATYPE_SSI_SP, /* Shared SSI */ | ||
| 22 | IMX_DMATYPE_MMC, /* MMC */ | ||
| 23 | IMX_DMATYPE_SDHC, /* SDHC */ | ||
| 24 | IMX_DMATYPE_UART, /* MCU domain UART */ | ||
| 25 | IMX_DMATYPE_UART_SP, /* Shared UART */ | ||
| 26 | IMX_DMATYPE_FIRI, /* FIRI */ | ||
| 27 | IMX_DMATYPE_CSPI, /* MCU domain CSPI */ | ||
| 28 | IMX_DMATYPE_CSPI_SP, /* Shared CSPI */ | ||
| 29 | IMX_DMATYPE_SIM, /* SIM */ | ||
| 30 | IMX_DMATYPE_ATA, /* ATA */ | ||
| 31 | IMX_DMATYPE_CCM, /* CCM */ | ||
| 32 | IMX_DMATYPE_EXT, /* External peripheral */ | ||
| 33 | IMX_DMATYPE_MSHC, /* Memory Stick Host Controller */ | ||
| 34 | IMX_DMATYPE_MSHC_SP, /* Shared Memory Stick Host Controller */ | ||
| 35 | IMX_DMATYPE_DSP, /* DSP */ | ||
| 36 | IMX_DMATYPE_MEMORY, /* Memory */ | ||
| 37 | IMX_DMATYPE_FIFO_MEMORY,/* FIFO type Memory */ | ||
| 38 | IMX_DMATYPE_SPDIF, /* SPDIF */ | ||
| 39 | IMX_DMATYPE_IPU_MEMORY, /* IPU Memory */ | ||
| 40 | IMX_DMATYPE_ASRC, /* ASRC */ | ||
| 41 | IMX_DMATYPE_ESAI, /* ESAI */ | ||
| 42 | }; | ||
| 43 | |||
| 44 | enum imx_dma_prio { | ||
| 45 | DMA_PRIO_HIGH = 0, | ||
| 46 | DMA_PRIO_MEDIUM = 1, | ||
| 47 | DMA_PRIO_LOW = 2 | ||
| 48 | }; | ||
| 49 | |||
| 50 | struct imx_dma_data { | ||
| 51 | int dma_request; /* DMA request line */ | ||
| 52 | enum sdma_peripheral_type peripheral_type; | ||
| 53 | int priority; | ||
| 54 | }; | ||
| 55 | |||
| 56 | static inline int imx_dma_is_ipu(struct dma_chan *chan) | ||
| 57 | { | ||
| 58 | return !strcmp(dev_name(chan->device->dev), "ipu-core"); | ||
| 59 | } | ||
| 60 | |||
| 61 | static inline int imx_dma_is_general_purpose(struct dma_chan *chan) | ||
| 62 | { | ||
| 63 | return !strcmp(dev_name(chan->device->dev), "imx-sdma") || | ||
| 64 | !strcmp(dev_name(chan->device->dev), "imx-dma"); | ||
| 65 | } | ||
| 66 | |||
| 67 | #endif | ||
diff --git a/arch/arm/plat-mxc/include/mach/sdma.h b/arch/arm/plat-mxc/include/mach/sdma.h new file mode 100644 index 00000000000..9be112227ac --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/sdma.h | |||
| @@ -0,0 +1,17 @@ | |||
| 1 | #ifndef __MACH_MXC_SDMA_H__ | ||
| 2 | #define __MACH_MXC_SDMA_H__ | ||
