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authorAxel Lin <axel.lin@gmail.com>2011-10-16 11:29:12 -0400
committerMark Brown <broonie@opensource.wolfsonmicro.com>2011-10-17 17:49:28 -0400
commitde5035b1dda4993f432a796c1d1ddc7b8006b8fe (patch)
tree7c2377d4c4956569eef281bda4287eb92d2840d9
parent151b75995a5180834a0609dced3d76ab978cae3b (diff)
ASoC: wm8900: Fix the mask defines
Now we have done bitwise NOT against the mask bits for the defines of WM8900_REG_CLOCKING1_BCLK_MASK, WM8900_REG_CLOCKING1_OPCLK_MASK and WM8900_LRC_MASK. But we don't have the bitwise NOT against the mask bits for the defines of WM8900_REG_CLOCKING2_DAC_CLKDIV, WM8900_REG_CLOCKING2_ADC_CLKDIV and WM8900_REG_DACCTRL_AIF_LRCLKRATE. It is error prone to mix the inconsistent meaning for different mask defines. So lets make the defines for each mask to be corresponding to the bits defines in datasheet. Don't add extra "bitwise NOT" to the defines. Signed-off-by: Axel Lin <axel.lin@gmail.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
-rw-r--r--sound/soc/codecs/wm8900.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/sound/soc/codecs/wm8900.c b/sound/soc/codecs/wm8900.c
index b16522ff3ae..86de396fb69 100644
--- a/sound/soc/codecs/wm8900.c
+++ b/sound/soc/codecs/wm8900.c
@@ -110,8 +110,8 @@
110 110
111#define WM8900_REG_CLOCKING1_BCLK_DIR 0x1 111#define WM8900_REG_CLOCKING1_BCLK_DIR 0x1
112#define WM8900_REG_CLOCKING1_MCLK_SRC 0x100 112#define WM8900_REG_CLOCKING1_MCLK_SRC 0x100
113#define WM8900_REG_CLOCKING1_BCLK_MASK (~0x01e) 113#define WM8900_REG_CLOCKING1_BCLK_MASK 0x01e
114#define WM8900_REG_CLOCKING1_OPCLK_MASK (~0x7000) 114#define WM8900_REG_CLOCKING1_OPCLK_MASK 0x7000
115 115
116#define WM8900_REG_CLOCKING2_ADC_CLKDIV 0xe0 116#define WM8900_REG_CLOCKING2_ADC_CLKDIV 0xe0
117#define WM8900_REG_CLOCKING2_DAC_CLKDIV 0x1c 117#define WM8900_REG_CLOCKING2_DAC_CLKDIV 0x1c
@@ -135,7 +135,7 @@
135#define WM8900_REG_HPCTL1_HP_SHORT 0x08 135#define WM8900_REG_HPCTL1_HP_SHORT 0x08
136#define WM8900_REG_HPCTL1_HP_SHORT2 0x04 136#define WM8900_REG_HPCTL1_HP_SHORT2 0x04
137 137
138#define WM8900_LRC_MASK 0xfc00 138#define WM8900_LRC_MASK 0x03ff
139 139
140struct wm8900_priv { 140struct wm8900_priv {
141 enum snd_soc_control_type control_type; 141 enum snd_soc_control_type control_type;
@@ -824,22 +824,22 @@ static int wm8900_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
824 case WM8900_BCLK_DIV: 824 case WM8900_BCLK_DIV:
825 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1); 825 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
826 snd_soc_write(codec, WM8900_REG_CLOCKING1, 826 snd_soc_write(codec, WM8900_REG_CLOCKING1,
827 div | (reg & WM8900_REG_CLOCKING1_BCLK_MASK)); 827 div | (reg & ~WM8900_REG_CLOCKING1_BCLK_MASK));
828 break; 828 break;
829 case WM8900_OPCLK_DIV: 829 case WM8900_OPCLK_DIV:
830 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1); 830 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
831 snd_soc_write(codec, WM8900_REG_CLOCKING1, 831 snd_soc_write(codec, WM8900_REG_CLOCKING1,
832 div | (reg & WM8900_REG_CLOCKING1_OPCLK_MASK)); 832 div | (reg & ~WM8900_REG_CLOCKING1_OPCLK_MASK));
833 break; 833 break;
834 case WM8900_DAC_LRCLK: 834 case WM8900_DAC_LRCLK:
835 reg = snd_soc_read(codec, WM8900_REG_AUDIO4); 835 reg = snd_soc_read(codec, WM8900_REG_AUDIO4);
836 snd_soc_write(codec, WM8900_REG_AUDIO4, 836 snd_soc_write(codec, WM8900_REG_AUDIO4,
837 div | (reg & WM8900_LRC_MASK)); 837 div | (reg & ~WM8900_LRC_MASK));
838 break; 838 break;
839 case WM8900_ADC_LRCLK: 839 case WM8900_ADC_LRCLK:
840 reg = snd_soc_read(codec, WM8900_REG_AUDIO3); 840 reg = snd_soc_read(codec, WM8900_REG_AUDIO3);
841 snd_soc_write(codec, WM8900_REG_AUDIO3, 841 snd_soc_write(codec, WM8900_REG_AUDIO3,
842 div | (reg & WM8900_LRC_MASK)); 842 div | (reg & ~WM8900_LRC_MASK));
843 break; 843 break;
844 case WM8900_DAC_CLKDIV: 844 case WM8900_DAC_CLKDIV:
845 reg = snd_soc_read(codec, WM8900_REG_CLOCKING2); 845 reg = snd_soc_read(codec, WM8900_REG_CLOCKING2);