drm/i915: fix transcoder PLL select masking

Transcoder A will always use PLL A and transcoder B will use PLL B.  But
transcoder C could use either, so always mask the select bits off before
or'ing in a new value.

Reported-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Tested-By: Eugeni Dodonov <eugeni.dodonov@intel.com>
Reviewed-By: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Keith Packard <keithp@keithp.com>

1 files changed, 10 insertions, 5 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2371a8e3804..ed5d4f4d702 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2906,12 +2906,16 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
 
                 /* Be sure PCH DPLL SEL is set */
                 temp = I915_READ(PCH_DPLL_SEL);
-                if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
+                if (pipe == 0) {
+                        temp &= ~(TRANSA_DPLLB_SEL);
                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
-                else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
+                } else if (pipe == 1) {
+                        temp &= ~(TRANSB_DPLLB_SEL);
                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
-                else if (pipe == 2 && (temp & TRANSC_DPLL_ENABLE) == 0)
+                } else if (pipe == 2) {
+                        temp &= ~(TRANSC_DPLLB_SEL);
                         temp |= (TRANSC_DPLL_ENABLE | transc_sel);
+                }
                 I915_WRITE(PCH_DPLL_SEL, temp);
         }
 
@@ -3077,14 +3081,14 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
                 temp = I915_READ(PCH_DPLL_SEL);
                 switch (pipe) {
                 case 0:
-                        temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
+                        temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
                         break;
                 case 1:
                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
                         break;
                 case 2:
                         /* C shares PLL A or B */
-                        temp &= ~(TRANSC_DPLL_ENABLE | TRANSB_DPLLB_SEL);
+                        temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
                         break;
                 default:
                         BUG(); /* wtf */
@@ -5590,6 +5594,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
                         temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
                         break;
                 case 2:
+                        temp &= ~(TRANSC_DPLLB_SEL);
                         temp |= TRANSC_DPLL_ENABLE | transc_sel;
                         break;
                 default: