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authorBen Skeggs <bskeggs@redhat.com>2012-07-10 20:44:20 -0400
committerBen Skeggs <bskeggs@redhat.com>2012-10-02 23:12:47 -0400
commitcb75d97e9c77743ecfcc43375be135a55a4d9b25 (patch)
treee7903f00db28b25a88d295dcc863f14b3d3bd707
parent70790f4f819875e8f390871fd15bbbf823f28e1b (diff)
drm/nouveau: implement devinit subdev, and new init table parser
v2: - make sure not to execute display scripts unless resuming Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat
-rw-r--r--drivers/gpu/drm/nouveau/Makefile10
-rw-r--r--drivers/gpu/drm/nouveau/core/include/subdev/bios/conn.h27
-rw-r--r--drivers/gpu/drm/nouveau/core/include/subdev/bios/dcb.h73
-rw-r--r--drivers/gpu/drm/nouveau/core/include/subdev/bios/dp.h8
-rw-r--r--drivers/gpu/drm/nouveau/core/include/subdev/bios/init.h21
-rw-r--r--drivers/gpu/drm/nouveau/core/include/subdev/devinit.h40
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/bios/conn.c55
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/bios/dp.c76
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/bios/init.c2120
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/device/nv04.c3
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/device/nv10.c9
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/device/nv20.c5
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/device/nv30.c6
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/device/nv40.c17
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/device/nv50.c15
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/device/nvc0.c9
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/device/nve0.c3
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/devinit/base.c69
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/devinit/fbmem.h98
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.c189
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/devinit/nv05.c159
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/devinit/nv10.c124
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/devinit/nv1a.c58
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/devinit/nv20.c96
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.c87
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_agp.c72
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_agp.h8
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_backlight.c4
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bios.c3535
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bios.h64
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_compat.c38
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_compat.h6
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_connector.c86
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_dp.c4
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drm.c36
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drm.h10
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drv.c7
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drv.h23
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_encoder.h14
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_hw.h4
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_mem.c6
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_mxm.c4
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_state.c4
-rw-r--r--drivers/gpu/drm/nouveau/nv04_crtc.c10
-rw-r--r--drivers/gpu/drm/nouveau/nv04_dac.c26
-rw-r--r--drivers/gpu/drm/nouveau/nv04_dfp.c46
-rw-r--r--drivers/gpu/drm/nouveau/nv04_display.c76
-rw-r--r--drivers/gpu/drm/nouveau/nv04_tv.c2
-rw-r--r--drivers/gpu/drm/nouveau/nv17_tv.c12
-rw-r--r--drivers/gpu/drm/nouveau/nv50_dac.c6
-rw-r--r--drivers/gpu/drm/nouveau/nv50_display.c128
-rw-r--r--drivers/gpu/drm/nouveau/nv50_display.h2
-rw-r--r--drivers/gpu/drm/nouveau/nv50_sor.c30
-rw-r--r--drivers/gpu/drm/nouveau/nvd0_display.c70
54 files changed, 3796 insertions, 3914 deletions
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
index 2574fd35122..522bc1c1e4d 100644
--- a/drivers/gpu/drm/nouveau/Makefile
+++ b/drivers/gpu/drm/nouveau/Makefile
@@ -20,9 +20,12 @@ nouveau-y += core/core/subdev.o
20 20
21nouveau-y += core/subdev/bios/base.o 21nouveau-y += core/subdev/bios/base.o
22nouveau-y += core/subdev/bios/bit.o 22nouveau-y += core/subdev/bios/bit.o
23nouveau-y += core/subdev/bios/conn.o
23nouveau-y += core/subdev/bios/dcb.o 24nouveau-y += core/subdev/bios/dcb.o
25nouveau-y += core/subdev/bios/dp.o
24nouveau-y += core/subdev/bios/gpio.o 26nouveau-y += core/subdev/bios/gpio.o
25nouveau-y += core/subdev/bios/i2c.o 27nouveau-y += core/subdev/bios/i2c.o
28nouveau-y += core/subdev/bios/init.o
26nouveau-y += core/subdev/bios/pll.o 29nouveau-y += core/subdev/bios/pll.o
27nouveau-y += core/subdev/clock/nv04.o 30nouveau-y += core/subdev/clock/nv04.o
28nouveau-y += core/subdev/clock/nv40.o 31nouveau-y += core/subdev/clock/nv40.o
@@ -40,6 +43,13 @@ nouveau-y += core/subdev/device/nv40.o
40nouveau-y += core/subdev/device/nv50.o 43nouveau-y += core/subdev/device/nv50.o
41nouveau-y += core/subdev/device/nvc0.o 44nouveau-y += core/subdev/device/nvc0.o
42nouveau-y += core/subdev/device/nve0.o 45nouveau-y += core/subdev/device/nve0.o
46nouveau-y += core/subdev/devinit/base.o
47nouveau-y += core/subdev/devinit/nv04.o
48nouveau-y += core/subdev/devinit/nv05.o
49nouveau-y += core/subdev/devinit/nv10.o
50nouveau-y += core/subdev/devinit/nv1a.o
51nouveau-y += core/subdev/devinit/nv20.o
52nouveau-y += core/subdev/devinit/nv50.o
43nouveau-y += core/subdev/fb/nv04.o 53nouveau-y += core/subdev/fb/nv04.o
44nouveau-y += core/subdev/fb/nv10.o 54nouveau-y += core/subdev/fb/nv10.o
45nouveau-y += core/subdev/fb/nv20.o 55nouveau-y += core/subdev/fb/nv20.o
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/conn.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/conn.h
new file mode 100644
index 00000000000..c1270548fd0
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/bios/conn.h
@@ -0,0 +1,27 @@
1#ifndef __NVBIOS_CONN_H__
2#define __NVBIOS_CONN_H__
3
4enum dcb_connector_type {
5 DCB_CONNECTOR_VGA = 0x00,
6 DCB_CONNECTOR_TV_0 = 0x10,
7 DCB_CONNECTOR_TV_1 = 0x11,
8 DCB_CONNECTOR_TV_3 = 0x13,
9 DCB_CONNECTOR_DVI_I = 0x30,
10 DCB_CONNECTOR_DVI_D = 0x31,
11 DCB_CONNECTOR_DMS59_0 = 0x38,
12 DCB_CONNECTOR_DMS59_1 = 0x39,
13 DCB_CONNECTOR_LVDS = 0x40,
14 DCB_CONNECTOR_LVDS_SPWG = 0x41,
15 DCB_CONNECTOR_DP = 0x46,
16 DCB_CONNECTOR_eDP = 0x47,
17 DCB_CONNECTOR_HDMI_0 = 0x60,
18 DCB_CONNECTOR_HDMI_1 = 0x61,
19 DCB_CONNECTOR_DMS59_DP0 = 0x64,
20 DCB_CONNECTOR_DMS59_DP1 = 0x65,
21 DCB_CONNECTOR_NONE = 0xff
22};
23
24u16 dcb_conntab(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
25u16 dcb_conn(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *len);
26
27#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/dcb.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/dcb.h
index 7000dcf2ae9..d682fb62583 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/dcb.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/bios/dcb.h
@@ -1,14 +1,56 @@
1#ifndef __NVBIOS_DCB_H__ 1#ifndef __NVBIOS_DCB_H__
2#define __NVBIOS_DCB_H__ 2#define __NVBIOS_DCB_H__
3 3
4struct nouveau_bios;
5
4enum dcb_output_type { 6enum dcb_output_type {
5 DCB_OUTPUT_ANALOG = 0x0, 7 DCB_OUTPUT_ANALOG = 0x0,
6 DCB_OUTPUT_TV = 0x1, 8 DCB_OUTPUT_TV = 0x1,
7 DCB_OUTPUT_TMDS = 0x2, 9 DCB_OUTPUT_TMDS = 0x2,
8 DCB_OUTPUT_LVDS = 0x3, 10 DCB_OUTPUT_LVDS = 0x3,
9 DCB_OUTPUT_DP = 0x4, 11 DCB_OUTPUT_DP = 0x6,
10 DCB_OUTPUT_EOL = 0xe, 12 DCB_OUTPUT_EOL = 0xe,
11 DCB_OUTPUT_UNUSED = 0xf, 13 DCB_OUTPUT_UNUSED = 0xf,
14 DCB_OUTPUT_ANY = -1,
15};
16
17struct dcb_output {
18 int index; /* may not be raw dcb index if merging has happened */
19 enum dcb_output_type type;
20 uint8_t i2c_index;
21 uint8_t heads;
22 uint8_t connector;
23 uint8_t bus;
24 uint8_t location;
25 uint8_t or;
26 bool duallink_possible;
27 union {
28 struct sor_conf {
29 int link;
30 } sorconf;
31 struct {
32 int maxfreq;
33 } crtconf;
34 struct {
35 struct sor_conf sor;
36 bool use_straps_for_mode;
37 bool use_acpi_for_edid;
38 bool use_power_scripts;
39 } lvdsconf;
40 struct {
41 bool has_component_output;
42 } tvconf;
43 struct {
44 struct sor_conf sor;
45 int link_nr;
46 int link_bw;
47 } dpconf;
48 struct {
49 struct sor_conf sor;
50 int slave_addr;
51 } tmdsconf;
52 };
53 bool i2c_upper_default;
12}; 54};
13 55
14u16 dcb_table(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *ent, u8 *len); 56u16 dcb_table(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *ent, u8 *len);
@@ -16,4 +58,33 @@ u16 dcb_outp(struct nouveau_bios *, u8 idx, u8 *ver, u8 *len);
16int dcb_outp_foreach(struct nouveau_bios *, void *data, int (*exec) 58int dcb_outp_foreach(struct nouveau_bios *, void *data, int (*exec)
17 (struct nouveau_bios *, void *, int index, u16 entry)); 59 (struct nouveau_bios *, void *, int index, u16 entry));
18 60
61
62/* BIT 'U'/'d' table encoder subtables have hashes matching them to
63 * a particular set of encoders.
64 *
65 * This function returns true if a particular DCB entry matches.
66 */
67static inline bool
68dcb_hash_match(struct dcb_output *dcb, u32 hash)
69{
70 if ((hash & 0x000000f0) != (dcb->location << 4))
71 return false;
72 if ((hash & 0x0000000f) != dcb->type)
73 return false;
74 if (!(hash & (dcb->or << 16)))
75 return false;
76
77 switch (dcb->type) {
78 case DCB_OUTPUT_TMDS:
79 case DCB_OUTPUT_LVDS:
80 case DCB_OUTPUT_DP:
81 if (hash & 0x00c00000) {
82 if (!(hash & (dcb->sorconf.link << 22)))
83 return false;
84 }
85 default:
86 return true;
87 }
88}
89
19#endif 90#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/dp.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/dp.h
new file mode 100644
index 00000000000..73b5e5d3e75
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/bios/dp.h
@@ -0,0 +1,8 @@
1#ifndef __NVBIOS_DP_H__
2#define __NVBIOS_DP_H__
3
4u16 dp_table(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
5u16 dp_outp(struct nouveau_bios *, u8 idx, u8 *ver, u8 *len);
6u16 dp_outp_match(struct nouveau_bios *, struct dcb_output *, u8 *ver, u8 *len);
7
8#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/init.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/init.h
new file mode 100644
index 00000000000..e69a8bdc6e9
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/bios/init.h
@@ -0,0 +1,21 @@
1#ifndef __NVBIOS_INIT_H__
2#define __NVBIOS_INIT_H__
3
4struct nvbios_init {
5 struct nouveau_subdev *subdev;
6 struct nouveau_bios *bios;
7 u16 offset;
8 struct dcb_output *outp;
9 int crtc;
10
11 /* internal state used during parsing */
12 u8 execute;
13 u32 nested;
14 u16 repeat;
15 u16 repend;
16};
17
18int nvbios_exec(struct nvbios_init *);
19int nvbios_init(struct nouveau_subdev *, bool execute);
20
21#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/devinit.h b/drivers/gpu/drm/nouveau/core/include/subdev/devinit.h
new file mode 100644
index 00000000000..29e4cc1f6cc
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/devinit.h
@@ -0,0 +1,40 @@
1#ifndef __NOUVEAU_DEVINIT_H__
2#define __NOUVEAU_DEVINIT_H__
3
4#include <core/subdev.h>
5#include <core/device.h>
6
7struct nouveau_devinit {
8 struct nouveau_subdev base;
9 bool post;
10 void (*meminit)(struct nouveau_devinit *);
11};
12
13static inline struct nouveau_devinit *
14nouveau_devinit(void *obj)
15{
16 return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_DEVINIT];
17}
18
19#define nouveau_devinit_create(p,e,o,d) \
20 nouveau_devinit_create_((p), (e), (o), sizeof(**d), (void **)d)
21#define nouveau_devinit_destroy(p) \
22 nouveau_subdev_destroy(&(p)->base)
23
24int nouveau_devinit_create_(struct nouveau_object *, struct nouveau_object *,
25 struct nouveau_oclass *, int, void **);
26int nouveau_devinit_init(struct nouveau_devinit *);
27int nouveau_devinit_fini(struct nouveau_devinit *, bool suspend);
28
29extern struct nouveau_oclass nv04_devinit_oclass;
30extern struct nouveau_oclass nv05_devinit_oclass;
31extern struct nouveau_oclass nv10_devinit_oclass;
32extern struct nouveau_oclass nv1a_devinit_oclass;
33extern struct nouveau_oclass nv20_devinit_oclass;
34extern struct nouveau_oclass nv50_devinit_oclass;
35
36void nv04_devinit_dtor(struct nouveau_object *);
37int nv04_devinit_init(struct nouveau_object *);
38int nv04_devinit_fini(struct nouveau_object *, bool);
39
40#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/conn.c b/drivers/gpu/drm/nouveau/core/subdev/bios/conn.c
new file mode 100644
index 00000000000..ac4026cd315
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/bios/conn.c
@@ -0,0 +1,55 @@
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include <core/device.h>
26
27#include <subdev/bios.h>
28#include <subdev/bios/dcb.h>
29
30u16
31dcb_conntab(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
32{
33 u16 dcb = dcb_table(bios, ver, hdr, cnt, len);
34 if (dcb && *ver >= 0x30 && *hdr >= 0x16) {
35 u16 data = nv_ro16(bios, dcb + 0x14);
36 if (data) {
37 *ver = nv_ro08(bios, data + 0);
38 *hdr = nv_ro08(bios, data + 1);
39 *cnt = nv_ro08(bios, data + 2);
40 *len = nv_ro08(bios, data + 3);
41 return data;
42 }
43 }
44 return 0x0000;
45}
46
47u16
48dcb_conn(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *len)
49{
50 u8 hdr, cnt;
51 u16 data = dcb_conntab(bios, ver, &hdr, &cnt, len);
52 if (data && idx < cnt)
53 return data + hdr + (idx * *len);
54 return 0x0000;
55}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/dp.c b/drivers/gpu/drm/nouveau/core/subdev/bios/dp.c
new file mode 100644
index 00000000000..3cbc0f3e8d5
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/bios/dp.c
@@ -0,0 +1,76 @@
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25
26#include "subdev/bios.h"
27#include "subdev/bios/bit.h"
28#include "subdev/bios/dcb.h"
29#include "subdev/bios/dp.h"
30
31u16
32dp_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
33{
34 struct bit_entry bit_d;
35
36 if (!bit_entry(bios, 'd', &bit_d)) {
37 if (bit_d.version == 1) {
38 u16 data = nv_ro16(bios, bit_d.offset);
39 if (data) {
40 *ver = nv_ro08(bios, data + 0);
41 *hdr = nv_ro08(bios, data + 1);
42 *len = nv_ro08(bios, data + 2);
43 *cnt = nv_ro08(bios, data + 3);
44 return data;
45 }
46 }
47 }
48
49 return 0x0000;
50}
51
52u16
53dp_outp(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *len)
54{
55 u8 hdr, cnt;
56 u16 table = dp_table(bios, ver, &hdr, &cnt, len);
57 if (table && idx < cnt)
58 return nv_ro16(bios, table + hdr + (idx * *len));
59 return 0xffff;
60}
61
62u16
63dp_outp_match(struct nouveau_bios *bios, struct dcb_output *outp,
64 u8 *ver, u8 *len)
65{
66 u8 idx = 0;
67 u16 data;
68 while ((data = dp_outp(bios, idx++, ver, len)) != 0xffff) {
69 if (data) {
70 u32 hash = nv_ro32(bios, data);
71 if (dcb_hash_match(outp, hash))
72 return data;
73 }
74 }
75 return 0x0000;
76}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/init.c b/drivers/gpu/drm/nouveau/core/subdev/bios/init.c
new file mode 100644
index 00000000000..6be8c32f6e4
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/bios/init.c
@@ -0,0 +1,2120 @@
1#include <core/engine.h>
2#include <core/device.h>
3
4#include <subdev/bios.h>
5#include <subdev/bios/conn.h>
6#include <subdev/bios/bmp.h>
7#include <subdev/bios/bit.h>
8#include <subdev/bios/dcb.h>
9#include <subdev/bios/dp.h>
10#include <subdev/bios/init.h>
11#include <subdev/devinit.h>
12#include <subdev/clock.h>
13#include <subdev/i2c.h>
14#include <subdev/vga.h>
15#include <subdev/gpio.h>
16
17#define bioslog(lvl, fmt, args...) do { \
18 nv_printk(init->bios, lvl, "0x%04x[%c]: "fmt, init->offset, \
19 init_exec(init) ? '0' + (init->nested - 1) : ' ', ##args); \
20} while(0)
21#define cont(fmt, args...) do { \
22 if (nv_subdev(init->bios)->debug >= NV_DBG_TRACE) \
23 printk(fmt, ##args); \
24} while(0)
25#define trace(fmt, args...) bioslog(TRACE, fmt, ##args)
26#define warn(fmt, args...) bioslog(WARN, fmt, ##args)
27#define error(fmt, args...) bioslog(ERROR, fmt, ##args)
28
29/******************************************************************************
30 * init parser control flow helpers
31 *****************************************************************************/
32
33static inline bool
34init_exec(struct nvbios_init *init)
35{
36 return (init->execute == 1) || ((init->execute & 5) == 5);
37}
38
39static inline void
40init_exec_set(struct nvbios_init *init, bool exec)
41{
42 if (exec) init->execute &= 0xfd;
43 else init->execute |= 0x02;
44}
45
46static inline void
47init_exec_inv(struct nvbios_init *init)
48{
49 init->execute ^= 0x02;
50}
51
52static inline void
53init_exec_force(struct nvbios_init *init, bool exec)
54{
55 if (exec) init->execute |= 0x04;
56 else init->execute &= 0xfb;
57}
58
59/******************************************************************************
60 * init parser wrappers for normal register/i2c/whatever accessors
61 *****************************************************************************/
62
63static inline int
64init_or(struct nvbios_init *init)
65{
66 if (init->outp)
67 return ffs(init->outp->or) - 1;
68 error("script needs OR!!\n");
69 return 0;
70}
71
72static inline int
73init_link(struct nvbios_init *init)
74{
75 if (init->outp)
76 return !(init->outp->sorconf.link & 1);
77 error("script needs OR link\n");
78 return 0;
79}
80
81static inline int
82init_crtc(struct nvbios_init *init)
83{
84 if (init->crtc >= 0)
85 return init->crtc;
86 error("script needs crtc\n");
87 return 0;
88}
89
90static u8
91init_conn(struct nvbios_init *init)
92{
93 struct nouveau_bios *bios = init->bios;
94
95 if (init->outp) {
96 u8 ver, len;
97 u16 conn = dcb_conn(bios, init->outp->connector, &ver, &len);
98 if (conn)
99 return nv_ro08(bios, conn);
100 }
101
102 error("script needs connector type\n");
103 return 0x00;
104}
105
106static inline u32
107init_nvreg(struct nvbios_init *init, u32 reg)
108{
109 /* C51 (at least) sometimes has the lower bits set which the VBIOS
110 * interprets to mean that access needs to go through certain IO
111 * ports instead. The NVIDIA binary driver has been seen to access
112 * these through the NV register address, so lets assume we can
113 * do the same
114 */
115 reg &= ~0x00000003;
116
117 /* GF8+ display scripts need register addresses mangled a bit to
118 * select a specific CRTC/OR
119 */
120 if (nv_device(init->bios)->card_type >= NV_50) {
121 if (reg & 0x80000000) {
122 reg += init_crtc(init) * 0x800;
123 reg &= ~0x80000000;
124 }
125
126 if (reg & 0x40000000) {
127 reg += init_or(init) * 0x800;
128 reg &= ~0x40000000;
129 if (reg & 0x20000000) {
130 reg += init_link(init) * 0x80;
131 reg &= ~0x20000000;
132 }
133 }
134 }
135
136 if (reg & ~0x00fffffc)
137 warn("unknown bits in register 0x%08x\n", reg);
138 return reg;
139}
140
141static u32
142init_rd32(struct nvbios_init *init, u32 reg)
143{
144 reg = init_nvreg(init, reg);
145 if (init_exec(init))
146 return nv_rd32(init->subdev, reg);
147 return 0x00000000;
148}
149
150static void
151init_wr32(struct nvbios_init *init, u32 reg, u32 val)
152{
153 reg = init_nvreg(init, reg);
154 if (init_exec(init))
155 nv_wr32(init->subdev, reg, val);
156}
157
158static u32
159init_mask(struct nvbios_init *init, u32 reg, u32 mask, u32 val)
160{
161 reg = init_nvreg(init, reg);
162 if (init_exec(init)) {
163 u32 tmp = nv_rd32(init->subdev, reg);
164 nv_wr32(init->subdev, reg, (tmp & ~mask) | val);
165 return tmp;
166 }
167 return 0x00000000;
168}
169
170static u8
171init_rdport(struct nvbios_init *init, u16 port)
172{
173 if (init_exec(init))
174 return nv_rdport(init->subdev, init->crtc, port);
175 return 0x00;
176}
177
178static void
179init_wrport(struct nvbios_init *init, u16 port, u8 value)
180{
181 if (init_exec(init))
182 nv_wrport(init->subdev, init->crtc, port, value);
183}
184
185static u8
186init_rdvgai(struct nvbios_init *init, u16 port, u8 index)
187{
188 struct nouveau_subdev *subdev = init->subdev;
189 if (init_exec(init)) {
190 int head = init->crtc < 0 ? 0 : init->crtc;
191 return nv_rdvgai(subdev, head, port, index);
192 }
193 return 0x00;
194}
195
196static void
197init_wrvgai(struct nvbios_init *init, u16 port, u8 index, u8 value)
198{
199 /* force head 0 for updates to cr44, it only exists on first head */
200 if (nv_device(init->subdev)->card_type < NV_50) {
201 if (port == 0x03d4 && index == 0x44)
202 init->crtc = 0;
203 }
204
205 if (init_exec(init)) {
206 int head = init->crtc < 0 ? 0 : init->crtc;
207 nv_wrvgai(init->subdev, head, port, index, value);
208 }
209
210 /* select head 1 if cr44 write selected it */
211 if (nv_device(init->subdev)->card_type < NV_50) {
212 if (port == 0x03d4 && index == 0x44 && value == 3)
213 init->crtc = 1;
214 }
215}
216
217static struct nouveau_i2c_port *
218init_i2c(struct nvbios_init *init, int index)
219{
220 struct nouveau_i2c *i2c = nouveau_i2c(init->bios);
221
222 if (index == 0xff) {
223 index = NV_I2C_DEFAULT(0);
224 if (init->outp && init->outp->i2c_upper_default)
225 index = NV_I2C_DEFAULT(1);
226 } else
227 if (index < 0) {
228 if (!init->outp) {
229 error("script needs output for i2c\n");
230 return NULL;
231 }
232
233 index = init->outp->i2c_index;
234 }
235
236 return i2c->find(i2c, index);
237}
238
239static int
240init_rdi2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg)
241{
242 struct nouveau_i2c_port *port = init_i2c(init, index);
243 if (port && init_exec(init))
244 return nv_rdi2cr(port, addr, reg);
245 return -ENODEV;
246}
247
248static int
249init_wri2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg, u8 val)
250{
251 struct nouveau_i2c_port *port = init_i2c(init, index);
252 if (port && init_exec(init))
253 return nv_wri2cr(port, addr, reg, val);
254 return -ENODEV;
255}
256
257static int
258init_rdauxr(struct nvbios_init *init, u32 addr)
259{
260 struct nouveau_i2c_port *port = init_i2c(init, -1);
261 u8 data;
262
263 if (port && init_exec(init)) {
264 int ret = nv_rdaux(port, addr, &data, 1);
265 if (ret)
266 return ret;
267 return data;
268 }
269
270 return -ENODEV;
271}
272
273static int
274init_wrauxr(struct nvbios_init *init, u32 addr, u8 data)
275{
276 struct nouveau_i2c_port *port = init_i2c(init, -1);
277 if (port && init_exec(init))
278 return nv_wraux(port, addr, &data, 1);
279 return -ENODEV;
280}
281
282static void
283init_prog_pll(struct nvbios_init *init, u32 id, u32 freq)
284{
285 struct nouveau_clock *clk = nouveau_clock(init->bios);
286 if (clk && clk->pll_set && init_exec(init)) {
287 int ret = clk->pll_set(clk, id, freq);
288 if (ret)
289 warn("failed to prog pll 0x%08x to %dkHz\n", id, freq);
290 }
291}
292
293/******************************************************************************
294 * parsing of bios structures that are required to execute init tables
295 *****************************************************************************/
296
297static u16
298init_table(struct nouveau_bios *bios, u16 *len)
299{
300 struct bit_entry bit_I;
301
302 if (!bit_entry(bios, 'I', &bit_I)) {
303 *len = bit_I.length;
304 return bit_I.offset;
305 }
306
307 if (bmp_version(bios) >= 0x0510) {
308 *len = 14;
309 return bios->bmp_offset + 75;
310 }
311
312 return 0x0000;
313}
314
315static u16
316init_table_(struct nvbios_init *init, u16 offset, const char *name)
317{
318 struct nouveau_bios *bios = init->bios;
319 u16 len, data = init_table(bios, &len);
320 if (data) {
321 if (len >= offset + 2) {
322 data = nv_ro16(bios, data + offset);
323 if (data)
324 return data;
325
326 warn("%s pointer invalid\n", name);
327 return 0x0000;
328 }
329
330 warn("init data too short for %s pointer", name);
331 return 0x0000;
332 }
333
334 warn("init data not found\n");
335 return 0x0000;
336}
337
338#define init_script_table(b) init_table_((b), 0x00, "script table")
339#define init_macro_index_table(b) init_table_((b), 0x02, "macro index table")
340#define init_macro_table(b) init_table_((b), 0x04, "macro table")
341#define init_condition_table(b) init_table_((b), 0x06, "condition table")
342#define init_io_condition_table(b) init_table_((b), 0x08, "io condition table")
343#define init_io_flag_condition_table(b) init_table_((b), 0x0a, "io flag conditon table")
344#define init_function_table(b) init_table_((b), 0x0c, "function table")
345#define init_xlat_table(b) init_table_((b), 0x10, "xlat table");
346
347static u16
348init_script(struct nouveau_bios *bios, int index)
349{
350 struct nvbios_init init = { .bios = bios };
351 u16 data;
352
353 if (bmp_version(bios) && bmp_version(bios) < 0x0510) {
354 if (index > 1)
355 return 0x0000;
356
357 data = bios->bmp_offset + (bios->version.major < 2 ? 14 : 18);
358 return nv_ro16(bios, data + (index * 2));
359 }
360
361 data = init_script_table(&init);
362 if (data)
363 return nv_ro16(bios, data + (index * 2));
364
365 return 0x0000;
366}
367
368static u16
369init_unknown_script(struct nouveau_bios *bios)
370{
371 u16 len, data = init_table(bios, &len);
372 if (data && len >= 16)
373 return nv_ro16(bios, data + 14);
374 return 0x0000;
375}
376
377static u16
378init_ram_restrict_table(struct nvbios_init *init)
379{
380 struct nouveau_bios *bios = init->bios;
381 struct bit_entry bit_M;
382 u16 data = 0x0000;
383
384 if (!bit_entry(bios, 'M', &bit_M)) {
385 if (bit_M.version == 1 && bit_M.length >= 5)
386 data = nv_ro16(bios, bit_M.offset + 3);
387 if (bit_M.version == 2 && bit_M.length >= 3)
388 data = nv_ro16(bios, bit_M.offset + 1);
389 }
390
391 if (data == 0x0000)
392 warn("ram restrict table not found\n");
393 return data;
394}
395
396static u8
397init_ram_restrict_group_count(struct nvbios_init *init)
398{
399 struct nouveau_bios *bios = init->bios;
400 struct bit_entry bit_M;
401
402 if (!bit_entry(bios, 'M', &bit_M)) {
403 if (bit_M.version == 1 && bit_M.length >= 5)
404 return nv_ro08(bios, bit_M.offset + 2);
405 if (bit_M.version == 2 && bit_M.length >= 3)
406 return nv_ro08(bios, bit_M.offset + 0);
407 }
408
409 return 0x00;
410}
411
412static u8
413init_ram_restrict(struct nvbios_init *init)
414{
415 u32 strap = (init_rd32(init, 0x101000) & 0x0000003c) >> 2;
416 u16 table = init_ram_restrict_table(init);
417 if (table)
418 return nv_ro08(init->bios, table + strap);
419 return 0x00;
420}
421
422static u8
423init_xlat_(struct nvbios_init *init, u8 index, u8 offset)
424{
425 struct nouveau_bios *bios = init->bios;
426 u16 table = init_xlat_table(init);
427 if (table) {
428 u16 data = nv_ro16(bios, table + (index * 2));
429 if (data)
430 return nv_ro08(bios, data + offset);
431 warn("xlat table pointer %d invalid\n", index);
432 }
433 return 0x00;
434}
435
436/******************************************************************************
437 * utility functions used by various init opcode handlers
438 *****************************************************************************/
439
440static bool
441init_condition_met(struct nvbios_init *init, u8 cond)
442{
443 struct nouveau_bios *bios = init->bios;
444 u16 table = init_condition_table(init);
445 if (table) {
446 u32 reg = nv_ro32(bios, table + (cond * 12) + 0);
447 u32 msk = nv_ro32(bios, table + (cond * 12) + 4);
448 u32 val = nv_ro32(bios, table + (cond * 12) + 8);
449 trace("\t[0x%02x] (R[0x%06x] & 0x%08x) == 0x%08x\n",
450 cond, reg, msk, val);
451 return (init_rd32(init, reg) & msk) == val;
452 }
453 return false;
454}
455
456static bool
457init_io_condition_met(struct nvbios_init *init, u8 cond)
458{
459 struct nouveau_bios *bios = init->bios;
460 u16 table = init_io_condition_table(init);
461 if (table) {
462 u16 port = nv_ro16(bios, table + (cond * 5) + 0);
463 u8 index = nv_ro08(bios, table + (cond * 5) + 2);
464 u8 mask = nv_ro08(bios, table + (cond * 5) + 3);
465 u8 value = nv_ro08(bios, table + (cond * 5) + 4);
466 trace("\t[0x%02x] (0x%04x[0x%02x] & 0x%02x) == 0x%02x\n",
467 cond, port, index, mask, value);
468 return (init_rdvgai(init, port, index) & mask) == value;
469 }
470 return false;
471}
472
473static bool
474init_io_flag_condition_met(struct nvbios_init *init, u8 cond)
475{
476 struct nouveau_bios *bios = init->bios;
477 u16 table = init_io_flag_condition_table(init);
478 if (table) {
479 u16 port = nv_ro16(bios, table + (cond * 9) + 0);
480 u8 index = nv_ro08(bios, table + (cond * 9) + 2);
481 u8 mask = nv_ro08(bios, table + (cond * 9) + 3);
482 u8 shift = nv_ro08(bios, table + (cond * 9) + 4);
483 u16 data = nv_ro16(bios, table + (cond * 9) + 5);
484 u8 dmask = nv_ro08(bios, table + (cond * 9) + 7);
485 u8 value = nv_ro08(bios, table + (cond * 9) + 8);
486 u8 ioval = (init_rdvgai(init, port, index) & mask) >> shift;
487 return (nv_ro08(bios, data + ioval) & dmask) == value;
488 }
489 return false;
490}
491
492static inline u32
493init_shift(u32 data, u8 shift)
494{
495 if (shift < 0x80)
496 return data >> shift;
497 return data << (0x100 - shift);
498}
499
500static u32
501init_tmds_reg(struct nvbios_init *init, u8 tmds)
502{
503 /* For mlv < 0x80, it is an index into a table of TMDS base addresses.
504 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
505 * CR58 for CR57 = 0 to index a table of offsets to the basic
506 * 0x6808b0 address.
507 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
508 * CR58 for CR57 = 0 to index a table of offsets to the basic
509 * 0x6808b0 address, and then flip the offset by 8.
510 */
511
512 const int pramdac_offset[13] = {
513 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
514 const u32 pramdac_table[4] = {
515 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
516
517 if (tmds >= 0x80) {
518 if (init->outp) {
519 u32 dacoffset = pramdac_offset[init->outp->or];
520 if (tmds == 0x81)
521 dacoffset ^= 8;
522 return 0x6808b0 + dacoffset;
523 }
524
525 error("tmds opcodes need dcb\n");
526 } else {
527 if (tmds < ARRAY_SIZE(pramdac_table))
528 return pramdac_table[tmds];
529
530 error("tmds selector 0x%02x unknown\n", tmds);
531 }
532
533 return 0;
534}
535
536/******************************************************************************
537 * init opcode handlers
538 *****************************************************************************/
539
540/**
541 * init_reserved - stub for various unknown/unused single-byte opcodes
542 *
543 */
544static void
545init_reserved(struct nvbios_init *init)
546{
547 u8 opcode = nv_ro08(init->bios, init->offset);
548 trace("RESERVED\t0x%02x\n", opcode);
549 init->offset += 1;
550}
551
552/**
553 * INIT_DONE - opcode 0x71
554 *
555 */
556static void
557init_done(struct nvbios_init *init)
558{
559 trace("DONE\n");
560 init->offset = 0x0000;
561}
562
563/**
564 * INIT_IO_RESTRICT_PROG - opcode 0x32
565 *
566 */
567static void
568init_io_restrict_prog(struct nvbios_init *init)
569{
570 struct nouveau_bios *bios = init->bios;
571 u16 port = nv_ro16(bios, init->offset + 1);
572 u8 index = nv_ro08(bios, init->offset + 3);
573 u8 mask = nv_ro08(bios, init->offset + 4);
574 u8 shift = nv_ro08(bios, init->offset + 5);
575 u8 count = nv_ro08(bios, init->offset + 6);
576 u32 reg = nv_ro32(bios, init->offset + 7);
577 u8 conf, i;
578
579 trace("IO_RESTRICT_PROG\tR[0x%06x] = "
580 "((0x%04x[0x%02x] & 0x%02x) >> %d) [{\n",
581 reg, port, index, mask, shift);
582 init->offset += 11;
583
584 conf = (init_rdvgai(init, port, index) & mask) >> shift;
585 for (i = 0; i < count; i++) {
586 u32 data = nv_ro32(bios, init->offset);
587
588 if (i == conf) {
589 trace("\t0x%08x *\n", data);
590 init_wr32(init, reg, data);
591 } else {
592 trace("\t0x%08x\n", data);
593 }
594
595 init->offset += 4;
596 }
597 trace("}]\n");
598}
599
600/**
601 * INIT_REPEAT - opcode 0x33
602 *
603 */
604static void
605init_repeat(struct nvbios_init *init)
606{
607 struct nouveau_bios *bios = init->bios;
608 u8 count = nv_ro08(bios, init->offset + 1);
609 u16 repeat = init->repeat;
610
611 trace("REPEAT\t0x%02x\n", count);
612 init->offset += 2;
613
614 init->repeat = init->offset;
615 init->repend = init->offset;
616 while (count--) {
617 init->offset = init->repeat;
618 nvbios_exec(init);
619 if (count)
620 trace("REPEAT\t0x%02x\n", count);
621 }
622 init->offset = init->repend;
623 init->repeat = repeat;
624}
625
626/**
627 * INIT_IO_RESTRICT_PLL - opcode 0x34
628 *
629 */
630static void
631init_io_restrict_pll(struct nvbios_init *init)
632{
633 struct nouveau_bios *bios = init->bios;
634 u16 port = nv_ro16(bios, init->offset + 1);
635 u8 index = nv_ro08(bios, init->offset + 3);
636 u8 mask = nv_ro08(bios, init->offset + 4);
637 u8 shift = nv_ro08(bios, init->offset + 5);
638 s8 iofc = nv_ro08(bios, init->offset + 6);
639 u8 count = nv_ro08(bios, init->offset + 7);
640 u32 reg = nv_ro32(bios, init->offset + 8);
641 u8 conf, i;
642
643 trace("IO_RESTRICT_PLL\tR[0x%06x] =PLL= "
644 "((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) IOFCOND 0x%02x [{\n",
645 reg, port, index, mask, shift, iofc);
646 init->offset += 12;
647
648 conf = (init_rdvgai(init, port, index) & mask) >> shift;
649 for (i = 0; i < count; i++) {
650 u32 freq = nv_ro16(bios, init->offset) * 10;
651
652 if (i == conf) {
653 trace("\t%dkHz *\n", freq);
654 if (iofc > 0 && init_io_flag_condition_met(init, iofc))
655 freq *= 2;
656 init_prog_pll(init, reg, freq);
657 } else {
658 trace("\t%dkHz\n", freq);
659 }
660
661 init->offset += 2;
662 }
663 trace("}]\n");
664}
665
666/**
667 * INIT_END_REPEAT - opcode 0x36
668 *
669 */
670static void
671init_end_repeat(struct nvbios_init *init)
672{
673 trace("END_REPEAT\n");
674 init->offset += 1;
675
676 if (init->repeat) {
677 init->repend = init->offset;
678 init->offset = 0;
679 }
680}
681
682/**
683 * INIT_COPY - opcode 0x37
684 *
685 */
686static void
687init_copy(struct nvbios_init *init)
688{
689 struct nouveau_bios *bios = init->bios;
690 u32 reg = nv_ro32(bios, init->offset + 1);
691 u8 shift = nv_ro08(bios, init->offset + 5);
692 u8 smask = nv_ro08(bios, init->offset + 6);
693 u16 port = nv_ro16(bios, init->offset + 7);
694 u8 index = nv_ro08(bios, init->offset + 9);
695 u8 mask = nv_ro08(bios, init->offset + 10);
696 u8 data;
697
698 trace("COPY\t0x%04x[0x%02x] &= 0x%02x |= "
699 "((R[0x%06x] %s 0x%02x) & 0x%02x)\n",
700 port, index, mask, reg, (shift & 0x80) ? "<<" : ">>",
701 (shift & 0x80) ? (0x100 - shift) : shift, smask);
702 init->offset += 11;
703
704 data = init_rdvgai(init, port, index) & mask;
705 data |= init_shift(init_rd32(init, reg), shift) & smask;
706 init_wrvgai(init, port, index, data);
707}
708
709/**
710 * INIT_NOT - opcode 0x38
711 *
712 */
713static void
714init_not(struct nvbios_init *init)
715{
716 trace("NOT\n");
717 init->offset += 1;
718 init_exec_inv(init);
719}
720
721/**
722 * INIT_IO_FLAG_CONDITION - opcode 0x39
723 *
724 */
725static void
726init_io_flag_condition(struct nvbios_init *init)
727{
728 struct nouveau_bios *bios = init->bios;
729 u8 cond = nv_ro08(bios, init->offset + 1);
730
731 trace("IO_FLAG_CONDITION\t0x%02x\n", cond);
732 init->offset += 2;
733
734 if (!init_io_flag_condition_met(init, cond))
735 init_exec_set(init, false);
736}
737
738/**
739 * INIT_DP_CONDITION - opcode 0x3a
740 *
741 */
742static void
743init_dp_condition(struct nvbios_init *init)
744{
745 struct nouveau_bios *bios = init->bios;
746 u8 cond = nv_ro08(bios, init->offset + 1);
747 u8 unkn = nv_ro08(bios, init->offset + 2);
748 u8 ver, len;
749 u16 data;
750
751 trace("DP_CONDITION\t0x%02x 0x%02x\n", cond, unkn);
752 init->offset += 3;
753
754 switch (cond) {
755 case 0:
756 if (init_conn(init) != DCB_CONNECTOR_eDP)
757 init_exec_set(init, false);
758 break;
759 case 1:
760 case 2:
761 if ( init->outp &&
762 (data = dp_outp_match(bios, init->outp, &ver, &len))) {
763 if (ver <= 0x40 && !(nv_ro08(bios, data + 5) & cond))
764 init_exec_set(init, false);
765 if (ver == 0x40 && !(nv_ro08(bios, data + 4) & cond))
766 init_exec_set(init, false);
767 break;
768 }
769
770 warn("script needs dp output table data\n");
771 break;
772 case 5:
773 if (!(init_rdauxr(init, 0x0d) & 1))
774 init_exec_set(init, false);
775 break;
776 default:
777 warn("unknown dp condition 0x%02x\n", cond);
778 break;
779 }
780}
781
782/**
783 * INIT_IO_MASK_OR - opcode 0x3b
784 *
785 */
786static void
787init_io_mask_or(struct nvbios_init *init)
788{
789 struct nouveau_bios *bios = init->bios;
790 u8 index = nv_ro08(bios, init->offset + 1);
791 u8 or = init_or(init);
792 u8 data;
793
794 trace("IO_MASK_OR\t0x03d4[0x%02x] &= ~(1 << 0x%02x)", index, or);
795 init->offset += 2;
796
797 data = init_rdvgai(init, 0x03d4, index);
798 init_wrvgai(init, 0x03d4, index, data &= ~(1 << or));
799}
800
801/**
802 * INIT_IO_OR - opcode 0x3c
803 *
804 */
805static void
806init_io_or(struct nvbios_init *init)
807{
808 struct nouveau_bios *bios = init->bios;
809 u8 index = nv_ro08(bios, init->offset + 1);
810 u8 or = init_or(init);
811 u8 data;
812
813 trace("IO_OR\t0x03d4[0x%02x] |= (1 << 0x%02x)", index, or);
814 init->offset += 2;
815
816 data = init_rdvgai(init, 0x03d4, index);
817 init_wrvgai(init, 0x03d4, index, data | (1 << or));
818}
819
820/**
821 * INIT_INDEX_ADDRESS_LATCHED - opcode 0x49
822 *
823 */
824static void
825init_idx_addr_latched(struct nvbios_init *init)
826{
827 struct nouveau_bios *bios = init->bios;
828 u32 creg = nv_ro32(bios, init->offset + 1);
829 u32 dreg = nv_ro32(bios, init->offset + 5);
830 u32 mask = nv_ro32(bios, init->offset + 9);
831 u32 data = nv_ro32(bios, init->offset + 13);
832 u8 count = nv_ro08(bios, init->offset + 17);
833
834 trace("INDEX_ADDRESS_LATCHED\t"
835 "R[0x%06x] : R[0x%06x]\n\tCTRL &= 0x%08x |= 0x%08x\n",
836 creg, dreg, mask, data);
837 init->offset += 18;
838
839 while (count--) {
840 u8 iaddr = nv_ro08(bios, init->offset + 0);
841 u8 idata = nv_ro08(bios, init->offset + 1);
842
843 trace("\t[0x%02x] = 0x%02x\n", iaddr, idata);
844 init->offset += 2;
845
846 init_wr32(init, dreg, idata);
847 init_mask(init, creg, ~mask, data | idata);
848 }
849}
850
851/**
852 * INIT_IO_RESTRICT_PLL2 - opcode 0x4a
853 *
854 */
855static void
856init_io_restrict_pll2(struct nvbios_init *init)
857{
858 struct nouveau_bios *bios = init->bios;
859 u16 port = nv_ro16(bios, init->offset + 1);
860 u8 index = nv_ro08(bios, init->offset + 3);
861 u8 mask = nv_ro08(bios, init->offset + 4);
862 u8 shift = nv_ro08(bios, init->offset + 5);
863 u8 count = nv_ro08(bios, init->offset + 6);
864 u32 reg = nv_ro32(bios, init->offset + 7);
865 u8 conf, i;
866
867 trace("IO_RESTRICT_PLL2\t"
868 "R[0x%06x] =PLL= ((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) [{\n",
869 reg, port, index, mask, shift);
870 init->offset += 11;
871
872 conf = (init_rdvgai(init, port, index) & mask) >> shift;
873 for (i = 0; i < count; i++) {
874 u32 freq = nv_ro32(bios, init->offset);
875 if (i == conf) {
876 trace("\t%dkHz *\n", freq);
877 init_prog_pll(init, reg, freq);
878 } else {
879 trace("\t%dkHz\n", freq);
880 }
881 init->offset += 4;
882 }
883 trace("}]\n");
884}
885
886/**
887 * INIT_PLL2 - opcode 0x4b
888 *
889 */
890static void
891init_pll2(struct nvbios_init *init)
892{
893 struct nouveau_bios *bios = init->bios;
894 u32 reg = nv_ro32(bios, init->offset + 1);
895 u32 freq = nv_ro32(bios, init->offset + 5);
896
897 trace("PLL2\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
898 init->offset += 9;
899
900 init_prog_pll(init, reg, freq);
901}
902
903/**
904 * INIT_I2C_BYTE - opcode 0x4c
905 *
906 */
907static void
908init_i2c_byte(struct nvbios_init *init)
909{
910 struct nouveau_bios *bios = init->bios;
911 u8 index = nv_ro08(bios, init->offset + 1);
912 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
913 u8 count = nv_ro08(bios, init->offset + 3);
914
915 trace("I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
916 init->offset += 4;
917
918 while (count--) {
919 u8 reg = nv_ro08(bios, init->offset + 0);
920 u8 mask = nv_ro08(bios, init->offset + 1);
921 u8 data = nv_ro08(bios, init->offset + 2);
922 int val;
923
924 trace("\t[0x%02x] &= 0x%02x |= 0x%02x\n", reg, mask, data);
925 init->offset += 3;
926
927 val = init_rdi2cr(init, index, addr, reg);
928 if (val < 0)
929 continue;
930 init_wri2cr(init, index, addr, reg, (val & mask) | data);
931 }
932}
933
934/**
935 * INIT_ZM_I2C_BYTE - opcode 0x4d
936 *
937 */
938static void
939init_zm_i2c_byte(struct nvbios_init *init)
940{
941 struct nouveau_bios *bios = init->bios;
942 u8 index = nv_ro08(bios, init->offset + 1);
943 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
944 u8 count = nv_ro08(bios, init->offset + 3);
945
946 trace("ZM_I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
947 init->offset += 4;
948
949 while (count--) {
950 u8 reg = nv_ro08(bios, init->offset + 0);
951 u8 data = nv_ro08(bios, init->offset + 1);
952
953 trace("\t[0x%02x] = 0x%02x\n", reg, data);
954 init->offset += 2;
955
956 init_wri2cr(init, index, addr, reg, data);
957 }
958
959}
960
961/**
962 * INIT_ZM_I2C - opcode 0x4e
963 *
964 */
965static void
966init_zm_i2c(struct nvbios_init *init)
967{
968 struct nouveau_bios *bios = init->bios;
969 u8 index = nv_ro08(bios, init->offset + 1);
970 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
971 u8 count = nv_ro08(bios, init->offset + 3);
972 u8 data[256], i;
973
974 trace("ZM_I2C\tI2C[0x%02x][0x%02x]\n", index, addr);
975 init->offset += 4;
976
977 for (i = 0; i < count; i++) {
978 data[i] = nv_ro08(bios, init->offset);
979 trace("\t0x%02x\n", data[i]);
980 init->offset++;
981 }
982
983 if (init_exec(init)) {
984 struct nouveau_i2c_port *port = init_i2c(init, index);
985 struct i2c_msg msg = {
986 .addr = addr, .flags = 0, .len = count, .buf = data,
987 };
988 int ret;
989
990 if (port && (ret = i2c_transfer(&port->adapter, &msg, 1)) != 1)
991 warn("i2c wr failed, %d\n", ret);
992 }
993}
994
995/**
996 * INIT_TMDS - opcode 0x4f
997 *
998 */
999static void
1000init_tmds(struct nvbios_init *init)
1001{
1002 struct nouveau_bios *bios = init->bios;
1003 u8 tmds = nv_ro08(bios, init->offset + 1);
1004 u8 addr = nv_ro08(bios, init->offset + 2);
1005 u8 mask = nv_ro08(bios, init->offset + 3);
1006 u8 data = nv_ro08(bios, init->offset + 4);
1007 u32 reg = init_tmds_reg(init, tmds);
1008
1009 trace("TMDS\tT[0x%02x][0x%02x] &= 0x%02x |= 0x%02x\n",
1010 tmds, addr, mask, data);
1011 init->offset += 5;
1012
1013 if (reg == 0)
1014 return;
1015
1016 init_wr32(init, reg + 0, addr | 0x00010000);
1017 init_wr32(init, reg + 4, data | (init_rd32(init, reg + 4) & mask));
1018 init_wr32(init, reg + 0, addr);
1019}
1020
1021/**
1022 * INIT_ZM_TMDS_GROUP - opcode 0x50
1023 *
1024 */
1025static void
1026init_zm_tmds_group(struct nvbios_init *init)
1027{
1028 struct nouveau_bios *bios = init->bios;
1029 u8 tmds = nv_ro08(bios, init->offset + 1);
1030 u8 count = nv_ro08(bios, init->offset + 2);
1031 u32 reg = init_tmds_reg(init, tmds);
1032
1033 trace("TMDS_ZM_GROUP\tT[0x%02x]\n", tmds);
1034 init->offset += 3;
1035
1036 while (count--) {
1037 u8 addr = nv_ro08(bios, init->offset + 0);
1038 u8 data = nv_ro08(bios, init->offset + 1);
1039
1040 trace("\t[0x%02x] = 0x%02x\n", addr, data);
1041 init->offset += 2;
1042
1043 init_wr32(init, reg + 4, data);
1044 init_wr32(init, reg + 0, addr);
1045 }
1046}
1047
1048/**
1049 * INIT_CR_INDEX_ADDRESS_LATCHED - opcode 0x51
1050 *
1051 */
1052static void
1053init_cr_idx_adr_latch(struct nvbios_init *init)
1054{
1055 struct nouveau_bios *bios = init->bios;
1056 u8 addr0 = nv_ro08(bios, init->offset + 1);
1057 u8 addr1 = nv_ro08(bios, init->offset + 2);
1058 u8 base = nv_ro08(bios, init->offset + 3);
1059 u8 count = nv_ro08(bios, init->offset + 4);
1060 u8 save0;
1061
1062 trace("CR_INDEX_ADDR C[%02x] C[%02x]\n", addr0, addr1);
1063 init->offset += 5;
1064
1065 save0 = init_rdvgai(init, 0x03d4, addr0);
1066 while (count--) {
1067 u8 data = nv_ro08(bios, init->offset);
1068
1069 trace("\t\t[0x%02x] = 0x%02x\n", base, data);
1070 init->offset += 1;
1071
1072 init_wrvgai(init, 0x03d4, addr0, base++);
1073 init_wrvgai(init, 0x03d4, addr1, data);
1074 }
1075 init_wrvgai(init, 0x03d4, addr0, save0);
1076}
1077
1078/**
1079 * INIT_CR - opcode 0x52
1080 *
1081 */
1082static void
1083init_cr(struct nvbios_init *init)
1084{
1085 struct nouveau_bios *bios = init->bios;
1086 u8 addr = nv_ro08(bios, init->offset + 1);
1087 u8 mask = nv_ro08(bios, init->offset + 2);
1088 u8 data = nv_ro08(bios, init->offset + 3);
1089 u8 val;
1090
1091 trace("CR\t\tC[0x%02x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
1092 init->offset += 4;
1093
1094 val = init_rdvgai(init, 0x03d4, addr) & mask;
1095 init_wrvgai(init, 0x03d4, addr, val | data);
1096}
1097
1098/**
1099 * INIT_ZM_CR - opcode 0x53
1100 *
1101 */
1102static void
1103init_zm_cr(struct nvbios_init *init)
1104{
1105 struct nouveau_bios *bios = init->bios;
1106 u8 addr = nv_ro08(bios, init->offset + 1);
1107 u8 data = nv_ro08(bios, init->offset + 2);
1108
1109 trace("ZM_CR\tC[0x%02x] = 0x%02x\n", addr, data);
1110 init->offset += 3;
1111
1112 init_wrvgai(init, 0x03d4, addr, data);
1113}
1114
1115/**
1116 * INIT_ZM_CR_GROUP - opcode 0x54
1117 *
1118 */
1119static void
1120init_zm_cr_group(struct nvbios_init *init)
1121{
1122 struct nouveau_bios *bios = init->bios;
1123 u8 count = nv_ro08(bios, init->offset + 1);
1124
1125 trace("ZM_CR_GROUP\n");
1126 init->offset += 2;
1127
1128 while (count--) {
1129 u8 addr = nv_ro08(bios, init->offset + 0);
1130 u8 data = nv_ro08(bios, init->offset + 1);
1131
1132 trace("\t\tC[0x%02x] = 0x%02x\n", addr, data);
1133 init->offset += 2;
1134
1135 init_wrvgai(init, 0x03d4, addr, data);
1136 }
1137}
1138
1139/**
1140 * INIT_CONDITION_TIME - opcode 0x56
1141 *
1142 */
1143static void
1144init_condition_time(struct nvbios_init *init)
1145{
1146 struct nouveau_bios *bios = init->bios;
1147 u8 cond = nv_ro08(bios, init->offset + 1);
1148 u8 retry = nv_ro08(bios, init->offset + 2);
1149 u8 wait = min((u16)retry * 50, 100);
1150
1151 trace("CONDITION_TIME\t0x%02x 0x%02x\n", cond, retry);
1152 init->offset += 3;
1153
1154 if (!init_exec(init))
1155 return;
1156
1157 while (wait--) {
1158 if (init_condition_met(init, cond))
1159 return;
1160 mdelay(20);
1161 }
1162
1163 init_exec_set(init, false);
1164}
1165
1166/**
1167 * INIT_LTIME - opcode 0x57
1168 *
1169 */
1170static void
1171init_ltime(struct nvbios_init *init)
1172{
1173 struct nouveau_bios *bios = init->bios;
1174 u16 msec = nv_ro16(bios, init->offset + 1);
1175
1176 trace("LTIME\t0x%04x\n", msec);
1177 init->offset += 3;
1178
1179 if (init_exec(init))
1180 mdelay(msec);
1181}
1182
1183/**
1184 * INIT_ZM_REG_SEQUENCE - opcode 0x58
1185 *
1186 */
1187static void
1188init_zm_reg_sequence(struct nvbios_init *init)
1189{
1190 struct nouveau_bios *bios = init->bios;
1191 u32 base = nv_ro32(bios, init->offset + 1);
1192 u8 count = nv_ro08(bios, init->offset + 5);
1193
1194 trace("ZM_REG_SEQUENCE\t0x%02x\n", count);
1195 init->offset += 6;
1196
1197 while (count--) {
1198 u32 data = nv_ro32(bios, init->offset);
1199
1200 trace("\t\tR[0x%06x] = 0x%08x\n", base, data);
1201 init->offset += 4;
1202
1203 init_wr32(init, base, data);
1204 base += 4;
1205 }
1206}
1207
1208/**
1209 * INIT_SUB_DIRECT - opcode 0x5b
1210 *
1211 */
1212static void
1213init_sub_direct(struct nvbios_init *init)
1214{
1215 struct nouveau_bios *bios = init->bios;
1216 u16 addr = nv_ro16(bios, init->offset + 1);
1217 u16 save;
1218
1219 trace("SUB_DIRECT\t0x%04x\n", addr);
1220
1221 if (init_exec(init)) {
1222 save = init->offset;
1223 init->offset = addr;
1224 if (nvbios_exec(init)) {
1225 error("error parsing sub-table\n");
1226 return;
1227 }
1228 init->offset = save;
1229 }
1230
1231 init->offset += 3;
1232}
1233
1234/**
1235 * INIT_JUMP - opcode 0x5c
1236 *
1237 */
1238static void
1239init_jump(struct nvbios_init *init)
1240{
1241 struct nouveau_bios *bios = init->bios;
1242 u16 offset = nv_ro16(bios, init->offset + 1);
1243
1244 trace("JUMP\t0x%04x\n", offset);
1245 init->offset = offset;
1246}
1247
1248/**
1249 * INIT_I2C_IF - opcode 0x5e
1250 *
1251 */
1252static void
1253init_i2c_if(struct nvbios_init *init)
1254{
1255 struct nouveau_bios *bios = init->bios;
1256 u8 index = nv_ro08(bios, init->offset + 1);
1257 u8 addr = nv_ro08(bios, init->offset + 2);
1258 u8 reg = nv_ro08(bios, init->offset + 3);
1259 u8 mask = nv_ro08(bios, init->offset + 4);
1260 u8 data = nv_ro08(bios, init->offset + 5);
1261 u8 value;
1262
1263 trace("I2C_IF\tI2C[0x%02x][0x%02x][0x%02x] & 0x%02x == 0x%02x\n",
1264 index, addr, reg, mask, data);
1265 init->offset += 6;
1266 init_exec_force(init, true);
1267
1268 value = init_rdi2cr(init, index, addr, reg);
1269 if ((value & mask) != data)
1270 init_exec_set(init, false);
1271
1272 init_exec_force(init, false);
1273}
1274
1275/**
1276 * INIT_COPY_NV_REG - opcode 0x5f
1277 *
1278 */
1279static void
1280init_copy_nv_reg(struct nvbios_init *init)
1281{
1282 struct nouveau_bios *bios = init->bios;
1283 u32 sreg = nv_ro32(bios, init->offset + 1);
1284 u8 shift = nv_ro08(bios, init->offset + 5);
1285 u32 smask = nv_ro32(bios, init->offset + 6);
1286 u32 sxor = nv_ro32(bios, init->offset + 10);
1287 u32 dreg = nv_ro32(bios, init->offset + 14);
1288 u32 dmask = nv_ro32(bios, init->offset + 18);
1289 u32 data;
1290
1291 trace("COPY_NV_REG\tR[0x%06x] &= 0x%08x |= "
1292 "((R[0x%06x] %s 0x%02x) & 0x%08x ^ 0x%08x)\n",
1293 dreg, dmask, sreg, (shift & 0x80) ? "<<" : ">>",
1294 (shift & 0x80) ? (0x100 - shift) : shift, smask, sxor);
1295 init->offset += 22;
1296
1297 data = init_shift(init_rd32(init, sreg), shift);
1298 init_mask(init, dreg, ~dmask, (data & smask) ^ sxor);
1299}
1300
1301/**
1302 * INIT_ZM_INDEX_IO - opcode 0x62
1303 *
1304 */
1305static void
1306init_zm_index_io(struct nvbios_init *init)
1307{
1308 struct nouveau_bios *bios = init->bios;
1309 u16 port = nv_ro16(bios, init->offset + 1);
1310 u8 index = nv_ro08(bios, init->offset + 3);
1311 u8 data = nv_ro08(bios, init->offset + 4);
1312
1313 trace("ZM_INDEX_IO\tI[0x%04x][0x%02x] = 0x%02x\n", port, index, data);
1314 init->offset += 5;
1315
1316 init_wrvgai(init, port, index, data);
1317}
1318
1319/**
1320 * INIT_COMPUTE_MEM - opcode 0x63
1321 *
1322 */
1323static void
1324init_compute_mem(struct nvbios_init *init)
1325{
1326 struct nouveau_devinit *devinit = nouveau_devinit(init->bios);
1327
1328 trace("COMPUTE_MEM\n");
1329 init->offset += 1;
1330
1331 init_exec_force(init, true);
1332 if (init_exec(init) && devinit->meminit)
1333 devinit->meminit(devinit);
1334 init_exec_force(init, false);
1335}
1336
1337/**
1338 * INIT_RESET - opcode 0x65
1339 *
1340 */
1341static void
1342init_reset(struct nvbios_init *init)
1343{
1344 struct nouveau_bios *bios = init->bios;
1345 u32 reg = nv_ro32(bios, init->offset + 1);
1346 u32 data1 = nv_ro32(bios, init->offset + 5);
1347 u32 data2 = nv_ro32(bios, init->offset + 9);
1348 u32 savepci19;
1349
1350 trace("RESET\tR[0x%08x] = 0x%08x, 0x%08x", reg, data1, data2);
1351 init->offset += 13;
1352 init_exec_force(init, true);
1353
1354 savepci19 = init_mask(init, 0x00184c, 0x00000f00, 0x00000000);
1355 init_wr32(init, reg, data1);
1356 udelay(10);
1357 init_wr32(init, reg, data2);
1358 init_wr32(init, 0x00184c, savepci19);
1359 init_mask(init, 0x001850, 0x00000001, 0x00000000);
1360
1361 init_exec_force(init, false);
1362}
1363
1364/**
1365 * INIT_CONFIGURE_MEM - opcode 0x66
1366 *
1367 */
1368static u16
1369init_configure_mem_clk(struct nvbios_init *init)
1370{
1371 u16 mdata = bmp_mem_init_table(init->bios);
1372 if (mdata)
1373 mdata += (init_rdvgai(init, 0x03d4, 0x3c) >> 4) * 66;
1374 return mdata;
1375}
1376
1377static void
1378init_configure_mem(struct nvbios_init *init)
1379{
1380 struct nouveau_bios *bios = init->bios;
1381 u16 mdata, sdata;
1382 u32 addr, data;
1383
1384 trace("CONFIGURE_MEM\n");
1385 init->offset += 1;
1386
1387 if (bios->version.major > 2) {
1388 init_done(init);
1389 return;
1390 }
1391 init_exec_force(init, true);
1392
1393 mdata = init_configure_mem_clk(init);
1394 sdata = bmp_sdr_seq_table(bios);
1395 if (nv_ro08(bios, mdata) & 0x01)
1396 sdata = bmp_ddr_seq_table(bios);
1397 mdata += 6; /* skip to data */
1398
1399 data = init_rdvgai(init, 0x03c4, 0x01);
1400 init_wrvgai(init, 0x03c4, 0x01, data | 0x20);
1401
1402 while ((addr = nv_ro32(bios, sdata)) != 0xffffffff) {
1403 switch (addr) {
1404 case 0x10021c: /* CKE_NORMAL */
1405 case 0x1002d0: /* CMD_REFRESH */
1406 case 0x1002d4: /* CMD_PRECHARGE */
1407 data = 0x00000001;
1408 break;
1409 default:
1410 data = nv_ro32(bios, mdata);
1411 mdata += 4;
1412 if (data == 0xffffffff)
1413 continue;
1414 break;
1415 }
1416
1417 init_wr32(init, addr, data);
1418 }
1419
1420 init_exec_force(init, false);
1421}
1422
1423/**
1424 * INIT_CONFIGURE_CLK - opcode 0x67
1425 *
1426 */
1427static void
1428init_configure_clk(struct nvbios_init *init)
1429{
1430 struct nouveau_bios *bios = init->bios;
1431 u16 mdata, clock;
1432
1433 trace("CONFIGURE_CLK\n");
1434 init->offset += 1;
1435
1436 if (bios->version.major > 2) {
1437 init_done(init);
1438 return;
1439 }
1440 init_exec_force(init, true);
1441
1442 mdata = init_configure_mem_clk(init);
1443
1444 /* NVPLL */
1445 clock = nv_ro16(bios, mdata + 4) * 10;
1446 init_prog_pll(init, 0x680500, clock);
1447
1448 /* MPLL */
1449 clock = nv_ro16(bios, mdata + 2) * 10;
1450 if (nv_ro08(bios, mdata) & 0x01)
1451 clock *= 2;
1452 init_prog_pll(init, 0x680504, clock);
1453
1454 init_exec_force(init, false);
1455}
1456
1457/**
1458 * INIT_CONFIGURE_PREINIT - opcode 0x68
1459 *
1460 */
1461static void
1462init_configure_preinit(struct nvbios_init *init)
1463{
1464 struct nouveau_bios *bios = init->bios;
1465 u32 strap;
1466
1467 trace("CONFIGURE_PREINIT\n");
1468 init->offset += 1;
1469
1470 if (bios->version.major > 2) {
1471 init_done(init);
1472 return;
1473 }
1474 init_exec_force(init, true);
1475
1476 strap = init_rd32(init, 0x101000);
1477 strap = ((strap << 2) & 0xf0) | ((strap & 0x40) >> 6);
1478 init_wrvgai(init, 0x03d4, 0x3c, strap);
1479
1480 init_exec_force(init, false);
1481}
1482
1483/**
1484 * INIT_IO - opcode 0x69
1485 *
1486 */
1487static void
1488init_io(struct nvbios_init *init)
1489{
1490 struct nouveau_bios *bios = init->bios;
1491 u16 port = nv_ro16(bios, init->offset + 1);
1492 u8 mask = nv_ro16(bios, init->offset + 3);
1493 u8 data = nv_ro16(bios, init->offset + 4);
1494 u8 value;
1495
1496 trace("IO\t\tI[0x%04x] &= 0x%02x |= 0x%02x\n", port, mask, data);
1497 init->offset += 5;
1498
1499 /* ummm.. yes.. should really figure out wtf this is and why it's
1500 * needed some day.. it's almost certainly wrong, but, it also
1501 * somehow makes things work...
1502 */
1503 if (nv_device(init->bios)->card_type >= NV_50 &&
1504 port == 0x03c3 && data == 0x01) {
1505 init_mask(init, 0x614100, 0xf0800000, 0x00800000);
1506 init_mask(init, 0x00e18c, 0x00020000, 0x00020000);
1507 init_mask(init, 0x614900, 0xf0800000, 0x00800000);
1508 init_mask(init, 0x000200, 0x40000000, 0x00000000);
1509 mdelay(10);
1510 init_mask(init, 0x00e18c, 0x00020000, 0x00000000);
1511 init_mask(init, 0x000200, 0x40000000, 0x40000000);
1512 init_wr32(init, 0x614100, 0x00800018);
1513 init_wr32(init, 0x614900, 0x00800018);
1514 mdelay(10);
1515 init_wr32(init, 0x614100, 0x10000018);
1516 init_wr32(init, 0x614900, 0x10000018);
1517 return;
1518 }
1519
1520 value = init_rdport(init, port) & mask;
1521 init_wrport(init, port, data | value);
1522}
1523
1524/**
1525 * INIT_SUB - opcode 0x6b
1526 *
1527 */
1528static void
1529init_sub(struct nvbios_init *init)
1530{
1531 struct nouveau_bios *bios = init->bios;
1532 u8 index = nv_ro08(bios, init->offset + 1);
1533 u16 addr, save;
1534
1535 trace("SUB\t0x%02x\n", index);
1536
1537 addr = init_script(bios, index);
1538 if (addr && init_exec(init)) {
1539 save = init->offset;
1540 init->offset = addr;
1541 if (nvbios_exec(init)) {
1542 error("error parsing sub-table\n");
1543 return;
1544 }
1545 init->offset = save;
1546 }
1547
1548 init->offset += 2;
1549}
1550
1551/**
1552 * INIT_RAM_CONDITION - opcode 0x6d
1553 *
1554 */
1555static void
1556init_ram_condition(struct nvbios_init *init)
1557{
1558 struct nouveau_bios *bios = init->bios;
1559 u8 mask = nv_ro08(bios, init->offset + 1);
1560 u8 value = nv_ro08(bios, init->offset + 2);
1561
1562 trace("RAM_CONDITION\t"
1563 "(R[0x100000] & 0x%02x) == 0x%02x\n", mask, value);
1564 init->offset += 3;
1565
1566 if ((init_rd32(init, 0x100000) & mask) != value)
1567 init_exec_set(init, false);
1568}
1569
1570/**
1571 * INIT_NV_REG - opcode 0x6e
1572 *
1573 */
1574static void
1575init_nv_reg(struct nvbios_init *init)
1576{
1577 struct nouveau_bios *bios = init->bios;
1578 u32 reg = nv_ro32(bios, init->offset + 1);
1579 u32 mask = nv_ro32(bios, init->offset + 5);
1580 u32 data = nv_ro32(bios, init->offset + 9);
1581
1582 trace("NV_REG\tR[0x%06x] &= 0x%08x |= 0x%08x\n", reg, mask, data);
1583 init->offset += 13;
1584
1585 init_mask(init, reg, ~mask, data);
1586}
1587
1588/**
1589 * INIT_MACRO - opcode 0x6f
1590 *
1591 */
1592static void
1593init_macro(struct nvbios_init *init)
1594{
1595 struct nouveau_bios *bios = init->bios;
1596 u8 macro = nv_ro08(bios, init->offset + 1);
1597 u16 table;
1598
1599 trace("MACRO\t0x%02x\n", macro);
1600
1601 table = init_macro_table(init);
1602 if (table) {
1603 u32 addr = nv_ro32(bios, table + (macro * 8) + 0);
1604 u32 data = nv_ro32(bios, table + (macro * 8) + 4);
1605 trace("\t\tR[0x%06x] = 0x%08x\n", addr, data);
1606 init_wr32(init, addr, data);
1607 }
1608
1609 init->offset += 2;
1610}
1611
1612/**
1613 * INIT_RESUME - opcode 0x72
1614 *
1615 */
1616static void
1617init_resume(struct nvbios_init *init)
1618{
1619 trace("RESUME\n");
1620 init->offset += 1;
1621 init_exec_set(init, true);
1622}
1623
1624/**
1625 * INIT_TIME - opcode 0x74
1626 *
1627 */
1628static void
1629init_time(struct nvbios_init *init)
1630{
1631 struct nouveau_bios *bios = init->bios;
1632 u16 usec = nv_ro16(bios, init->offset + 1);
1633
1634 trace("TIME\t0x%04x\n", usec);
1635 init->offset += 3;
1636
1637 if (init_exec(init)) {
1638 if (usec < 1000)
1639 udelay(usec);
1640 else
1641 mdelay((usec + 900) / 1000);
1642 }
1643}
1644
1645/**
1646 * INIT_CONDITION - opcode 0x75
1647 *
1648 */
1649static void
1650init_condition(struct nvbios_init *init)
1651{
1652 struct nouveau_bios *bios = init->bios;
1653 u8 cond = nv_ro08(bios, init->offset + 1);
1654
1655 trace("CONDITION\t0x%02x\n", cond);
1656 init->offset += 2;
1657
1658 if (!init_condition_met(init, cond))
1659 init_exec_set(init, false);
1660}
1661
1662/**
1663 * INIT_IO_CONDITION - opcode 0x76
1664 *
1665 */
1666static void
1667init_io_condition(struct nvbios_init *init)
1668{
1669 struct nouveau_bios *bios = init->bios;
1670 u8 cond = nv_ro08(bios, init->offset + 1);
1671
1672 trace("IO_CONDITION\t0x%02x\n", cond);
1673 init->offset += 2;
1674
1675 if (!init_io_condition_met(init, cond))
1676 init_exec_set(init, false);
1677}
1678
1679/**
1680 * INIT_INDEX_IO - opcode 0x78
1681 *
1682 */
1683static void
1684init_index_io(struct nvbios_init *init)
1685{
1686 struct nouveau_bios *bios = init->bios;
1687 u16 port = nv_ro16(bios, init->offset + 1);
1688 u8 index = nv_ro16(bios, init->offset + 3);
1689 u8 mask = nv_ro08(bios, init->offset + 4);
1690 u8 data = nv_ro08(bios, init->offset + 5);
1691 u8 value;
1692
1693 trace("INDEX_IO\tI[0x%04x][0x%02x] &= 0x%02x |= 0x%02x\n",
1694 port, index, mask, data);
1695 init->offset += 6;
1696
1697 value = init_rdvgai(init, port, index) & mask;
1698 init_wrvgai(init, port, index, data | value);
1699}
1700
1701/**
1702 * INIT_PLL - opcode 0x79
1703 *
1704 */
1705static void
1706init_pll(struct nvbios_init *init)
1707{
1708 struct nouveau_bios *bios = init->bios;
1709 u32 reg = nv_ro32(bios, init->offset + 1);
1710 u32 freq = nv_ro16(bios, init->offset + 5) * 10;
1711
1712 trace("PLL\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
1713 init->offset += 7;
1714
1715 init_prog_pll(init, reg, freq);
1716}
1717
1718/**
1719 * INIT_ZM_REG - opcode 0x7a
1720 *
1721 */
1722static void
1723init_zm_reg(struct nvbios_init *init)
1724{
1725 struct nouveau_bios *bios = init->bios;
1726 u32 addr = nv_ro32(bios, init->offset + 1);
1727 u32 data = nv_ro32(bios, init->offset + 5);
1728
1729 trace("ZM_REG\tR[0x%06x] = 0x%08x\n", addr, data);
1730 init->offset += 9;
1731
1732 if (addr == 0x000200)
1733 data |= 0x00000001;
1734
1735 init_wr32(init, addr, data);
1736}
1737
1738/**
1739 * INIT_RAM_RESTRICT_PLL - opcde 0x87
1740 *
1741 */
1742static void
1743init_ram_restrict_pll(struct nvbios_init *init)
1744{
1745 struct nouveau_bios *bios = init->bios;
1746 u8 type = nv_ro08(bios, init->offset + 1);
1747 u8 count = init_ram_restrict_group_count(init);
1748 u8 strap = init_ram_restrict(init);
1749 u8 cconf;
1750
1751 trace("RAM_RESTRICT_PLL\t0x%02x\n", type);
1752 init->offset += 2;
1753
1754 for (cconf = 0; cconf < count; cconf++) {
1755 u32 freq = nv_ro32(bios, init->offset);
1756
1757 if (cconf == strap) {
1758 trace("%dkHz *\n", freq);
1759 init_prog_pll(init, type, freq);
1760 } else {
1761 trace("%dkHz\n", freq);
1762 }
1763
1764 init->offset += 4;
1765 }
1766}
1767
1768/**
1769 * INIT_GPIO - opcode 0x8e
1770 *
1771 */
1772static void
1773init_gpio(struct nvbios_init *init)
1774{
1775 struct nouveau_gpio *gpio = nouveau_gpio(init->bios);
1776
1777 trace("GPIO\n");
1778 init->offset += 1;
1779
1780 if (init_exec(init) && gpio && gpio->reset)
1781 gpio->reset(gpio);
1782}
1783
1784/**
1785 * INIT_RAM_RESTRICT_ZM_GROUP - opcode 0x8f
1786 *
1787 */
1788static void
1789init_ram_restrict_zm_reg_group(struct nvbios_init *init)
1790{
1791 struct nouveau_bios *bios = init->bios;
1792 u32 addr = nv_ro32(bios, init->offset + 1);
1793 u8 incr = nv_ro08(bios, init->offset + 5);
1794 u8 num = nv_ro08(bios, init->offset + 6);
1795 u8 count = init_ram_restrict_group_count(init);
1796 u8 index = init_ram_restrict(init);
1797 u8 i, j;
1798
1799 trace("RAM_RESTRICT_ZM_REG_GROUP\t"
1800 "R[%08x] 0x%02x 0x%02x\n", addr, incr, num);
1801 init->offset += 7;
1802
1803 for (i = 0; i < num; i++) {
1804 trace("\tR[0x%06x] = {\n", addr);
1805 for (j = 0; j < count; j++) {
1806 u32 data = nv_ro32(bios, init->offset);
1807
1808 if (j == index) {
1809 trace("\t\t0x%08x *\n", data);
1810 init_wr32(init, addr, data);
1811 } else {
1812 trace("\t\t0x%08x\n", data);
1813 }
1814
1815 init->offset += 4;
1816 }
1817 trace("\t}\n");
1818 addr += incr;
1819 }
1820}
1821
1822/**
1823 * INIT_COPY_ZM_REG - opcode 0x90
1824 *
1825 */
1826static void
1827init_copy_zm_reg(struct nvbios_init *init)
1828{
1829 struct nouveau_bios *bios = init->bios;
1830 u32 sreg = nv_ro32(bios, init->offset + 1);
1831 u32 dreg = nv_ro32(bios, init->offset + 5);
1832
1833 trace("COPY_ZM_REG\tR[0x%06x] = R[0x%06x]\n", sreg, dreg);
1834 init->offset += 9;
1835
1836 init_wr32(init, dreg, init_rd32(init, sreg));
1837}
1838
1839/**
1840 * INIT_ZM_REG_GROUP - opcode 0x91
1841 *
1842 */
1843static void
1844init_zm_reg_group(struct nvbios_init *init)
1845{
1846 struct nouveau_bios *bios = init->bios;
1847 u32 addr = nv_ro32(bios, init->offset + 1);
1848 u8 count = nv_ro08(bios, init->offset + 5);
1849
1850 trace("ZM_REG_GROUP\tR[0x%06x] =\n");
1851 init->offset += 6;
1852
1853 while (count--) {
1854 u32 data = nv_ro32(bios, init->offset);
1855 trace("\t0x%08x\n", data);
1856 init_wr32(init, addr, data);
1857 init->offset += 4;
1858 }
1859}
1860
1861/**
1862 * INIT_XLAT - opcode 0x96
1863 *
1864 */
1865static void
1866init_xlat(struct nvbios_init *init)
1867{
1868 struct nouveau_bios *bios = init->bios;
1869 u32 saddr = nv_ro32(bios, init->offset + 1);
1870 u8 sshift = nv_ro08(bios, init->offset + 5);
1871 u8 smask = nv_ro08(bios, init->offset + 6);
1872 u8 index = nv_ro08(bios, init->offset + 7);
1873 u32 daddr = nv_ro32(bios, init->offset + 8);
1874 u32 dmask = nv_ro32(bios, init->offset + 12);
1875 u8 shift = nv_ro08(bios, init->offset + 16);
1876 u32 data;
1877
1878 trace("INIT_XLAT\tR[0x%06x] &= 0x%08x |= "
1879 "(X%02x((R[0x%06x] %s 0x%02x) & 0x%02x) << 0x%02x)\n",
1880 daddr, dmask, index, saddr, (sshift & 0x80) ? "<<" : ">>",
1881 (sshift & 0x80) ? (0x100 - sshift) : sshift, smask, shift);
1882 init->offset += 17;
1883
1884 data = init_shift(init_rd32(init, saddr), sshift) & smask;
1885 data = init_xlat_(init, index, data) << shift;
1886 init_mask(init, daddr, ~dmask, data);
1887}
1888
1889/**
1890 * INIT_ZM_MASK_ADD - opcode 0x97
1891 *
1892 */
1893static void
1894init_zm_mask_add(struct nvbios_init *init)
1895{
1896 struct nouveau_bios *bios = init->bios;
1897 u32 addr = nv_ro32(bios, init->offset + 1);
1898 u32 mask = nv_ro32(bios, init->offset + 5);
1899 u32 add = nv_ro32(bios, init->offset + 9);
1900 u32 data;
1901
1902 trace("ZM_MASK_ADD\tR[0x%06x] &= 0x%08x += 0x%08x\n", addr, mask, add);
1903 init->offset += 13;
1904
1905 data = init_rd32(init, addr) & mask;
1906 data |= ((data + add) & ~mask);
1907 init_wr32(init, addr, data);
1908}
1909
1910/**
1911 * INIT_AUXCH - opcode 0x98
1912 *
1913 */
1914static void
1915init_auxch(struct nvbios_init *init)
1916{
1917 struct nouveau_bios *bios = init->bios;
1918 u32 addr = nv_ro32(bios, init->offset + 1);
1919 u8 count = nv_ro08(bios, init->offset + 5);
1920
1921 trace("AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
1922 init->offset += 6;
1923
1924 while (count--) {
1925 u8 mask = nv_ro08(bios, init->offset + 0);
1926 u8 data = nv_ro08(bios, init->offset + 1);
1927 trace("\tAUX[0x%08x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
1928 mask = init_rdauxr(init, addr) & mask;
1929 init_wrauxr(init, addr, mask | data);
1930 init->offset += 2;
1931 }
1932}
1933
1934/**
1935 * INIT_AUXCH - opcode 0x99
1936 *
1937 */
1938static void
1939init_zm_auxch(struct nvbios_init *init)
1940{
1941 struct nouveau_bios *bios = init->bios;
1942 u32 addr = nv_ro32(bios, init->offset + 1);
1943 u8 count = nv_ro08(bios, init->offset + 5);
1944
1945 trace("ZM_AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
1946 init->offset += 6;
1947
1948 while (count--) {
1949 u8 data = nv_ro08(bios, init->offset + 0);
1950 trace("\tAUX[0x%08x] = 0x%02x\n", addr, data);
1951 init_wrauxr(init, addr, data);
1952 init->offset += 1;
1953 }
1954}
1955
1956/**
1957 * INIT_I2C_LONG_IF - opcode 0x9a
1958 *
1959 */
1960static void
1961init_i2c_long_if(struct nvbios_init *init)
1962{
1963 struct nouveau_bios *bios = init->bios;
1964 u8 index = nv_ro08(bios, init->offset + 1);
1965 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
1966 u8 reglo = nv_ro08(bios, init->offset + 3);
1967 u8 reghi = nv_ro08(bios, init->offset + 4);
1968 u8 mask = nv_ro08(bios, init->offset + 5);
1969 u8 data = nv_ro08(bios, init->offset + 6);
1970 struct nouveau_i2c_port *port;
1971
1972 trace("I2C_LONG_IF\t"
1973 "I2C[0x%02x][0x%02x][0x%02x%02x] & 0x%02x == 0x%02x\n",
1974 index, addr, reglo, reghi, mask, data);
1975 init->offset += 7;
1976
1977 port = init_i2c(init, index);
1978 if (port) {
1979 u8 i[2] = { reghi, reglo };
1980 u8 o[1] = {};
1981 struct i2c_msg msg[] = {
1982 { .addr = addr, .flags = 0, .len = 2, .buf = i },
1983 { .addr = addr, .flags = I2C_M_RD, .len = 1, .buf = o }
1984 };
1985 int ret;
1986
1987 ret = i2c_transfer(&port->adapter, msg, 2);
1988 if (ret == 2 && ((o[0] & mask) == data))
1989 return;
1990 }
1991
1992 init_exec_set(init, false);
1993}
1994
1995static struct nvbios_init_opcode {
1996 void (*exec)(struct nvbios_init *);
1997} init_opcode[] = {
1998 [0x32] = { init_io_restrict_prog },
1999 [0x33] = { init_repeat },
2000 [0x34] = { init_io_restrict_pll },
2001 [0x36] = { init_end_repeat },
2002 [0x37] = { init_copy },
2003 [0x38] = { init_not },
2004 [0x39] = { init_io_flag_condition },
2005 [0x3a] = { init_dp_condition },
2006 [0x3b] = { init_io_mask_or },
2007 [0x3c] = { init_io_or },
2008 [0x49] = { init_idx_addr_latched },
2009 [0x4a] = { init_io_restrict_pll2 },
2010 [0x4b] = { init_pll2 },
2011 [0x4c] = { init_i2c_byte },
2012 [0x4d] = { init_zm_i2c_byte },
2013 [0x4e] = { init_zm_i2c },
2014 [0x4f] = { init_tmds },
2015 [0x50] = { init_zm_tmds_group },
2016 [0x51] = { init_cr_idx_adr_latch },
2017 [0x52] = { init_cr },
2018 [0x53] = { init_zm_cr },
2019 [0x54] = { init_zm_cr_group },
2020 [0x56] = { init_condition_time },
2021 [0x57] = { init_ltime },
2022 [0x58] = { init_zm_reg_sequence },
2023 [0x5b] = { init_sub_direct },
2024 [0x5c] = { init_jump },
2025 [0x5e] = { init_i2c_if },
2026 [0x5f] = { init_copy_nv_reg },
2027 [0x62] = { init_zm_index_io },
2028 [0x63] = { init_compute_mem },
2029 [0x65] = { init_reset },
2030 [0x66] = { init_configure_mem },
2031 [0x67] = { init_configure_clk },
2032 [0x68] = { init_configure_preinit },
2033 [0x69] = { init_io },
2034 [0x6b] = { init_sub },
2035 [0x6d] = { init_ram_condition },
2036 [0x6e] = { init_nv_reg },
2037 [0x6f] = { init_macro },
2038 [0x71] = { init_done },
2039 [0x72] = { init_resume },
2040 [0x74] = { init_time },
2041 [0x75] = { init_condition },
2042 [0x76] = { init_io_condition },
2043 [0x78] = { init_index_io },
2044 [0x79] = { init_pll },
2045 [0x7a] = { init_zm_reg },
2046 [0x87] = { init_ram_restrict_pll },
2047 [0x8c] = { init_reserved },
2048 [0x8d] = { init_reserved },
2049 [0x8e] = { init_gpio },
2050 [0x8f] = { init_ram_restrict_zm_reg_group },
2051 [0x90] = { init_copy_zm_reg },
2052 [0x91] = { init_zm_reg_group },
2053 [0x92] = { init_reserved },
2054 [0x96] = { init_xlat },
2055 [0x97] = { init_zm_mask_add },
2056 [0x98] = { init_auxch },
2057 [0x99] = { init_zm_auxch },
2058 [0x9a] = { init_i2c_long_if },
2059};
2060
2061#define init_opcode_nr (sizeof(init_opcode) / sizeof(init_opcode[0]))
2062
2063int
2064nvbios_exec(struct nvbios_init *init)
2065{
2066 init->nested++;
2067 while (init->offset) {
2068 u8 opcode = nv_ro08(init->bios, init->offset);
2069 if (opcode >= init_opcode_nr || !init_opcode[opcode].exec) {
2070 error("unknown opcode 0x%02x\n", opcode);
2071 return -EINVAL;
2072 }
2073
2074 init_opcode[opcode].exec(init);
2075 }
2076 init->nested--;
2077 return 0;
2078}
2079
2080int
2081nvbios_init(struct nouveau_subdev *subdev, bool execute)
2082{
2083 struct nouveau_bios *bios = nouveau_bios(subdev);
2084 int ret = 0;
2085 int i = -1;
2086 u16 data;
2087
2088 if (execute)
2089 nv_info(bios, "running init tables\n");
2090 while (!ret && (data = (init_script(bios, ++i)))) {
2091 struct nvbios_init init = {
2092 .subdev = subdev,
2093 .bios = bios,
2094 .offset = data,
2095 .outp = NULL,
2096 .crtc = -1,
2097 .execute = execute ? 1 : 0,
2098 };
2099
2100 ret = nvbios_exec(&init);
2101 }
2102
2103 /* the vbios parser will run this right after the normal init
2104 * tables, whereas the binary driver appears to run it later.
2105 */
2106 if (!ret && (data = init_unknown_script(bios))) {
2107 struct nvbios_init init = {
2108 .subdev = subdev,
2109 .bios = bios,
2110 .offset = data,
2111 .outp = NULL,
2112 .crtc = -1,
2113 .execute = execute ? 1 : 0,
2114 };
2115
2116 ret = nvbios_exec(&init);
2117 }
2118
2119 return 0;
2120}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/device/nv04.c b/drivers/gpu/drm/nouveau/core/subdev/device/nv04.c
index e24e74b9c43..47f7841ecaa 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/device/nv04.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/device/nv04.c
@@ -26,6 +26,7 @@
26#include <subdev/bios.h> 26#include <subdev/bios.h>
27#include <subdev/i2c.h> 27#include <subdev/i2c.h>
28#include <subdev/clock.h> 28#include <subdev/clock.h>
29#include <subdev/devinit.h>
29 30
30int 31int
31nv04_identify(struct nouveau_device *device) 32nv04_identify(struct nouveau_device *device)
@@ -35,11 +36,13 @@ nv04_identify(struct nouveau_device *device)
35 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 36 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
36 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 37 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
37 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 38 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
39 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv04_devinit_oclass;
38 break; 40 break;
39 case 0x05: 41 case 0x05:
40 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 42 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
41 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 43 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
42 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 44 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
45 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv05_devinit_oclass;
43 break; 46 break;
44 default: 47 default:
45 nv_fatal(device, "unknown RIVA chipset\n"); 48 nv_fatal(device, "unknown RIVA chipset\n");
diff --git a/drivers/gpu/drm/nouveau/core/subdev/device/nv10.c b/drivers/gpu/drm/nouveau/core/subdev/device/nv10.c
index 0b8eb741686..ad481ebe7ea 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/device/nv10.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/device/nv10.c
@@ -27,6 +27,7 @@
27#include <subdev/gpio.h> 27#include <subdev/gpio.h>
28#include <subdev/i2c.h> 28#include <subdev/i2c.h>
29#include <subdev/clock.h> 29#include <subdev/clock.h>
30#include <subdev/devinit.h>
30 31
31int 32int
32nv10_identify(struct nouveau_device *device) 33nv10_identify(struct nouveau_device *device)
@@ -37,48 +38,56 @@ nv10_identify(struct nouveau_device *device)
37 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 38 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
38 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 39 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
39 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 40 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
41 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
40 break; 42 break;
41 case 0x15: 43 case 0x15:
42 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 44 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
43 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 45 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
44 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 46 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
45 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 47 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
48 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
46 break; 49 break;
47 case 0x16: 50 case 0x16:
48 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 51 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
49 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 52 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
50 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 53 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
51 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 54 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
55 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
52 break; 56 break;
53 case 0x1a: 57 case 0x1a:
54 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 58 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
55 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 59 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
56 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 60 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
57 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 61 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
62 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
58 break; 63 break;
59 case 0x11: 64 case 0x11:
60 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 65 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
61 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 66 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
62 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 67 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
63 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 68 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
69 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
64 break; 70 break;
65 case 0x17: 71 case 0x17:
66 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 72 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
67 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 73 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
68 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 74 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
69 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 75 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
76 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
70 break; 77 break;
71 case 0x1f: 78 case 0x1f:
72 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 79 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
73 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 80 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
74 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 81 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
75 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 82 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
83 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
76 break; 84 break;
77 case 0x18: 85 case 0x18:
78 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 86 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
79 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 87 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
80 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 88 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
81 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 89 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
90 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
82 break; 91 break;
83 default: 92 default:
84 nv_fatal(device, "unknown Celsius chipset\n"); 93 nv_fatal(device, "unknown Celsius chipset\n");
diff --git a/drivers/gpu/drm/nouveau/core/subdev/device/nv20.c b/drivers/gpu/drm/nouveau/core/subdev/device/nv20.c
index 1432ef046b7..51ef1f4b9a5 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/device/nv20.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/device/nv20.c
@@ -27,6 +27,7 @@
27#include <subdev/gpio.h> 27#include <subdev/gpio.h>
28#include <subdev/i2c.h> 28#include <subdev/i2c.h>
29#include <subdev/clock.h> 29#include <subdev/clock.h>
30#include <subdev/devinit.h>
30 31
31int 32int
32nv20_identify(struct nouveau_device *device) 33nv20_identify(struct nouveau_device *device)
@@ -37,24 +38,28 @@ nv20_identify(struct nouveau_device *device)
37 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 38 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
38 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 39 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
39 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 40 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
41 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
40 break; 42 break;
41 case 0x25: 43 case 0x25:
42 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 44 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
43 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 45 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
44 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 46 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
45 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 47 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
48 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
46 break; 49 break;
47 case 0x28: 50 case 0x28:
48 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 51 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
49 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 52 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
50 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 53 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
51 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 54 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
55 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
52 break; 56 break;
53 case 0x2a: 57 case 0x2a:
54 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 58 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
55 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 59 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
56 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 60 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
57 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 61 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
62 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
58 break; 63 break;
59 default: 64 default:
60 nv_fatal(device, "unknown Kelvin chipset\n"); 65 nv_fatal(device, "unknown Kelvin chipset\n");
diff --git a/drivers/gpu/drm/nouveau/core/subdev/device/nv30.c b/drivers/gpu/drm/nouveau/core/subdev/device/nv30.c
index 7eeab784179..e812f71a931 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/device/nv30.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/device/nv30.c
@@ -27,6 +27,7 @@
27#include <subdev/gpio.h> 27#include <subdev/gpio.h>
28#include <subdev/i2c.h> 28#include <subdev/i2c.h>
29#include <subdev/clock.h> 29#include <subdev/clock.h>
30#include <subdev/devinit.h>
30 31
31int 32int
32nv30_identify(struct nouveau_device *device) 33nv30_identify(struct nouveau_device *device)
@@ -37,30 +38,35 @@ nv30_identify(struct nouveau_device *device)
37 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 38 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
38 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 39 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
39 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 40 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
41 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
40 break; 42 break;
41 case 0x35: 43 case 0x35:
42 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 44 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
43 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 45 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
44 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 46 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
45 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 47 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
48 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
46 break; 49 break;
47 case 0x31: 50 case 0x31:
48 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 51 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
49 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 52 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
50 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 53 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
51 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 54 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
55 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
52 break; 56 break;
53 case 0x36: 57 case 0x36:
54 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 58 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
55 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 59 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
56 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 60 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
57 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 61 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
62 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
58 break; 63 break;
59 case 0x34: 64 case 0x34:
60 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 65 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
61 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 66 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
62 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 67 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
63 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; 68 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
69 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
64 break; 70 break;
65 default: 71 default:
66 nv_fatal(device, "unknown Rankine chipset\n"); 72 nv_fatal(device, "unknown Rankine chipset\n");
diff --git a/drivers/gpu/drm/nouveau/core/subdev/device/nv40.c b/drivers/gpu/drm/nouveau/core/subdev/device/nv40.c
index ec7c03f96d7..8d2b62cbdff 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/device/nv40.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/device/nv40.c
@@ -27,6 +27,7 @@
27#include <subdev/gpio.h> 27#include <subdev/gpio.h>
28#include <subdev/i2c.h> 28#include <subdev/i2c.h>
29#include <subdev/clock.h> 29#include <subdev/clock.h>
30#include <subdev/devinit.h>
30 31
31int 32int
32nv40_identify(struct nouveau_device *device) 33nv40_identify(struct nouveau_device *device)
@@ -37,96 +38,112 @@ nv40_identify(struct nouveau_device *device)
37 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 38 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
38 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 39 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
39 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 40 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
41 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
40 break; 42 break;
41 case 0x41: 43 case 0x41:
42 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 44 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
43 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 45 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
44 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 46 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
45 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 47 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
48 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
46 break; 49 break;
47 case 0x42: 50 case 0x42:
48 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 51 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
49 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 52 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
50 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 53 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
51 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 54 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
55 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
52 break; 56 break;
53 case 0x43: 57 case 0x43:
54 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 58 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
55 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 59 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
56 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 60 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
57 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 61 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
62 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
58 break; 63 break;
59 case 0x45: 64 case 0x45:
60 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 65 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
61 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 66 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
62 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 67 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
63 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 68 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
69 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
64 break; 70 break;
65 case 0x47: 71 case 0x47:
66 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 72 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
67 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 73 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
68 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 74 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
69 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 75 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
76 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
70 break; 77 break;
71 case 0x49: 78 case 0x49:
72 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 79 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
73 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 80 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
74 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 81 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
75 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 82 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
83 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
76 break; 84 break;
77 case 0x4b: 85 case 0x4b:
78 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 86 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
79 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 87 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
80 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 88 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
81 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 89 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
90 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
82 break; 91 break;
83 case 0x44: 92 case 0x44:
84 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 93 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
85 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 94 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
86 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 95 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
87 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 96 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
97 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
88 break; 98 break;
89 case 0x46: 99 case 0x46:
90 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 100 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
91 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 101 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
92 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 102 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
93 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 103 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
104 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
94 break; 105 break;
95 case 0x4a: 106 case 0x4a:
96 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 107 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
97 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 108 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
98 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 109 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
99 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 110 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
111 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
100 break; 112 break;
101 case 0x4c: 113 case 0x4c:
102 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 114 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
103 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 115 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
104 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 116 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
105 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 117 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
118 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
106 break; 119 break;
107 case 0x4e: 120 case 0x4e:
108 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 121 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
109 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 122 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
110 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 123 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
111 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 124 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
125 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
112 break; 126 break;
113 case 0x63: 127 case 0x63:
114 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 128 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
115 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 129 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
116 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 130 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
117 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 131 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
132 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
118 break; 133 break;
119 case 0x67: 134 case 0x67:
120 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 135 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
121 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 136 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
122 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 137 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
123 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 138 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
139 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
124 break; 140 break;
125 case 0x68: 141 case 0x68:
126 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 142 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
127 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; 143 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
128 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 144 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
129 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; 145 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
146 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
130 break; 147 break;
131 default: 148 default:
132 nv_fatal(device, "unknown Curie chipset\n"); 149 nv_fatal(device, "unknown Curie chipset\n");
diff --git a/drivers/gpu/drm/nouveau/core/subdev/device/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/device/nv50.c
index 0674163506c..cb50d8629bb 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/device/nv50.c
@@ -27,6 +27,7 @@
27#include <subdev/gpio.h> 27#include <subdev/gpio.h>
28#include <subdev/i2c.h> 28#include <subdev/i2c.h>
29#include <subdev/clock.h> 29#include <subdev/clock.h>
30#include <subdev/devinit.h>
30 31
31int 32int
32nv50_identify(struct nouveau_device *device) 33nv50_identify(struct nouveau_device *device)
@@ -37,84 +38,98 @@ nv50_identify(struct nouveau_device *device)
37 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; 38 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
38 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 39 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
39 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass; 40 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
41 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
40 break; 42 break;
41 case 0x84: 43 case 0x84:
42 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 44 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
43 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; 45 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
44 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 46 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
45 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass; 47 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
48 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
46 break; 49 break;
47 case 0x86: 50 case 0x86:
48 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 51 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
49 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; 52 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
50 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 53 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
51 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass; 54 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
55 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
52 break; 56 break;
53 case 0x92: 57 case 0x92:
54 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 58 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
55 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; 59 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
56 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 60 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
57 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass; 61 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
62 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
58 break; 63 break;
59 case 0x94: 64 case 0x94:
60 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 65 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
61 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; 66 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
62 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 67 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
63 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass; 68 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
69 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
64 break; 70 break;
65 case 0x96: 71 case 0x96:
66 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 72 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
67 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; 73 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
68 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 74 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
69 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass; 75 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
76 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
70 break; 77 break;
71 case 0x98: 78 case 0x98:
72 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 79 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
73 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; 80 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
74 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 81 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
75 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass; 82 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
83 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
76 break; 84 break;
77 case 0xa0: 85 case 0xa0:
78 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 86 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
79 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; 87 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
80 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 88 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
81 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass; 89 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
90 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
82 break; 91 break;
83 case 0xaa: 92 case 0xaa:
84 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 93 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
85 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; 94 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
86 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 95 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
87 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass; 96 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
97 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
88 break; 98 break;
89 case 0xac: 99 case 0xac:
90 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 100 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
91 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; 101 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
92 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 102 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
93 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass; 103 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
104 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
94 break; 105 break;
95 case 0xa3: 106 case 0xa3:
96 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 107 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
97 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; 108 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
98 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 109 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
99 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; 110 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
111 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
100 break; 112 break;
101 case 0xa5: 113 case 0xa5:
102 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 114 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
103 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; 115 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
104 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 116 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
105 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; 117 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
118 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
106 break; 119 break;
107 case 0xa8: 120 case 0xa8:
108 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 121 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
109 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; 122 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
110 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 123 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
111 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; 124 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
125 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
112 break; 126 break;
113 case 0xaf: 127 case 0xaf:
114 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 128 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
115 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; 129 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
116 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 130 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
117 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; 131 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
132 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
118 break; 133 break;
119 default: 134 default:
120 nv_fatal(device, "unknown Tesla chipset\n"); 135 nv_fatal(device, "unknown Tesla chipset\n");
diff --git a/drivers/gpu/drm/nouveau/core/subdev/device/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/device/nvc0.c
index 56aae6bfbf2..67c46fc15b8 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/device/nvc0.c
@@ -27,6 +27,7 @@
27#include <subdev/gpio.h> 27#include <subdev/gpio.h>
28#include <subdev/i2c.h> 28#include <subdev/i2c.h>
29#include <subdev/clock.h> 29#include <subdev/clock.h>
30#include <subdev/devinit.h>
30 31
31int 32int
32nvc0_identify(struct nouveau_device *device) 33nvc0_identify(struct nouveau_device *device)
@@ -37,48 +38,56 @@ nvc0_identify(struct nouveau_device *device)
37 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; 38 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
38 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 39 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
39 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; 40 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
41 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
40 break; 42 break;
41 case 0xc4: 43 case 0xc4:
42 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 44 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
43 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; 45 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
44 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 46 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
45 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; 47 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
48 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
46 break; 49 break;
47 case 0xc3: 50 case 0xc3:
48 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 51 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
49 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; 52 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
50 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 53 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
51 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; 54 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
55 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
52 break; 56 break;
53 case 0xce: 57 case 0xce:
54 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 58 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
55 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; 59 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
56 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 60 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
57 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; 61 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
62 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
58 break; 63 break;
59 case 0xcf: 64 case 0xcf:
60 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 65 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
61 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; 66 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
62 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 67 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
63 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; 68 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
69 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
64 break; 70 break;
65 case 0xc1: 71 case 0xc1:
66 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 72 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
67 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; 73 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
68 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 74 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
69 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; 75 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
76 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
70 break; 77 break;
71 case 0xc8: 78 case 0xc8:
72 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 79 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
73 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; 80 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
74 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 81 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
75 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; 82 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
83 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
76 break; 84 break;
77 case 0xd9: 85 case 0xd9:
78 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 86 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
79 device->oclass[NVDEV_SUBDEV_GPIO ] = &nvd0_gpio_oclass; 87 device->oclass[NVDEV_SUBDEV_GPIO ] = &nvd0_gpio_oclass;
80 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 88 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
81 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; 89 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
90 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
82 break; 91 break;
83 default: 92 default:
84 nv_fatal(device, "unknown Fermi chipset\n"); 93 nv_fatal(device, "unknown Fermi chipset\n");
diff --git a/drivers/gpu/drm/nouveau/core/subdev/device/nve0.c b/drivers/gpu/drm/nouveau/core/subdev/device/nve0.c
index 8ad51cc0543..a1e87dfccf6 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/device/nve0.c
@@ -27,6 +27,7 @@
27#include <subdev/gpio.h> 27#include <subdev/gpio.h>
28#include <subdev/i2c.h> 28#include <subdev/i2c.h>
29#include <subdev/clock.h> 29#include <subdev/clock.h>
30#include <subdev/devinit.h>
30 31
31int 32int
32nve0_identify(struct nouveau_device *device) 33nve0_identify(struct nouveau_device *device)
@@ -37,12 +38,14 @@ nve0_identify(struct nouveau_device *device)
37 device->oclass[NVDEV_SUBDEV_GPIO ] = &nvd0_gpio_oclass; 38 device->oclass[NVDEV_SUBDEV_GPIO ] = &nvd0_gpio_oclass;
38 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 39 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
39 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; 40 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
41 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
40 break; 42 break;
41 case 0xe7: 43 case 0xe7:
42 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 44 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
43 device->oclass[NVDEV_SUBDEV_GPIO ] = &nvd0_gpio_oclass; 45 device->oclass[NVDEV_SUBDEV_GPIO ] = &nvd0_gpio_oclass;
44 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; 46 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
45 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; 47 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
48 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
46 break; 49 break;
47 default: 50 default:
48 nv_fatal(device, "unknown Kepler chipset\n"); 51 nv_fatal(device, "unknown Kepler chipset\n");
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/base.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/base.c
new file mode 100644
index 00000000000..5a07a39c173
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/base.c
@@ -0,0 +1,69 @@
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include <core/option.h>
26
27#include <subdev/devinit.h>
28#include <subdev/bios.h>
29#include <subdev/bios/init.h>
30
31int
32nouveau_devinit_init(struct nouveau_devinit *devinit)
33{
34 int ret = nouveau_subdev_init(&devinit->base);
35 if (ret)
36 return ret;
37
38 return nvbios_init(&devinit->base, devinit->post);
39}
40
41int
42nouveau_devinit_fini(struct nouveau_devinit *devinit, bool suspend)
43{
44 /* force full reinit on resume */
45 if (suspend)
46 devinit->post = true;
47
48 return nouveau_subdev_fini(&devinit->base, suspend);
49}
50
51int
52nouveau_devinit_create_(struct nouveau_object *parent,
53 struct nouveau_object *engine,
54 struct nouveau_oclass *oclass,
55 int size, void **pobject)
56{
57 struct nouveau_device *device = nv_device(parent);
58 struct nouveau_devinit *devinit;
59 int ret;
60
61 ret = nouveau_subdev_create_(parent, engine, oclass, 0, "DEVINIT",
62 "init", size, pobject);
63 devinit = *pobject;
64 if (ret)
65 return ret;
66
67 devinit->post = nouveau_boolopt(device->cfgopt, "NvForcePost", false);
68 return 0;
69}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/fbmem.h b/drivers/gpu/drm/nouveau/core/subdev/devinit/fbmem.h
new file mode 100644
index 00000000000..6b56a0f4cb4
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/fbmem.h
@@ -0,0 +1,98 @@
1/*
2 * Copyright (C) 2010 Francisco Jerez.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27#define NV04_PFB_BOOT_0 0x00100000
28# define NV04_PFB_BOOT_0_RAM_AMOUNT 0x00000003
29# define NV04_PFB_BOOT_0_RAM_AMOUNT_32MB 0x00000000
30# define NV04_PFB_BOOT_0_RAM_AMOUNT_4MB 0x00000001
31# define NV04_PFB_BOOT_0_RAM_AMOUNT_8MB 0x00000002
32# define NV04_PFB_BOOT_0_RAM_AMOUNT_16MB 0x00000003
33# define NV04_PFB_BOOT_0_RAM_WIDTH_128 0x00000004
34# define NV04_PFB_BOOT_0_RAM_TYPE 0x00000028
35# define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT 0x00000000
36# define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT 0x00000008
37# define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT_4BANK 0x00000010
38# define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT 0x00000018
39# define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBIT 0x00000020
40# define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBITX16 0x00000028
41# define NV04_PFB_BOOT_0_UMA_ENABLE 0x00000100
42# define NV04_PFB_BOOT_0_UMA_SIZE 0x0000f000
43#define NV04_PFB_DEBUG_0 0x00100080
44# define NV04_PFB_DEBUG_0_PAGE_MODE 0x00000001
45# define NV04_PFB_DEBUG_0_REFRESH_OFF 0x00000010
46# define NV04_PFB_DEBUG_0_REFRESH_COUNTX64 0x00003f00
47# define NV04_PFB_DEBUG_0_REFRESH_SLOW_CLK 0x00004000
48# define NV04_PFB_DEBUG_0_SAFE_MODE 0x00008000
49# define NV04_PFB_DEBUG_0_ALOM_ENABLE 0x00010000
50# define NV04_PFB_DEBUG_0_CASOE 0x00100000
51# define NV04_PFB_DEBUG_0_CKE_INVERT 0x10000000
52# define NV04_PFB_DEBUG_0_REFINC 0x20000000
53# define NV04_PFB_DEBUG_0_SAVE_POWER_OFF 0x40000000
54#define NV04_PFB_CFG0 0x00100200
55# define NV04_PFB_CFG0_SCRAMBLE 0x20000000
56#define NV04_PFB_CFG1 0x00100204
57#define NV04_PFB_SCRAMBLE(i) (0x00100400 + 4 * (i))
58
59#define NV10_PFB_REFCTRL 0x00100210
60# define NV10_PFB_REFCTRL_VALID_1 (1 << 31)
61
62static inline struct io_mapping *
63fbmem_init(struct pci_dev *pdev)
64{
65 return io_mapping_create_wc(pci_resource_start(pdev, 1),
66 pci_resource_len(pdev, 1));
67}
68
69static inline void
70fbmem_fini(struct io_mapping *fb)
71{
72 io_mapping_free(fb);
73}
74
75static inline u32
76fbmem_peek(struct io_mapping *fb, u32 off)
77{
78 u8 __iomem *p = io_mapping_map_atomic_wc(fb, off & PAGE_MASK);
79 u32 val = ioread32(p + (off & ~PAGE_MASK));
80 io_mapping_unmap_atomic(p);
81 return val;
82}
83
84static inline void
85fbmem_poke(struct io_mapping *fb, u32 off, u32 val)
86{
87 u8 __iomem *p = io_mapping_map_atomic_wc(fb, off & PAGE_MASK);
88 iowrite32(val, p + (off & ~PAGE_MASK));
89 wmb();
90 io_mapping_unmap_atomic(p);
91}
92
93static inline bool
94fbmem_readback(struct io_mapping *fb, u32 off, u32 val)
95{
96 fbmem_poke(fb, off, val);
97 return val == fbmem_peek(fb, off);
98}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.c
new file mode 100644
index 00000000000..7a72d939434
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.c
@@ -0,0 +1,189 @@
1/*
2 * Copyright (C) 2010 Francisco Jerez.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27#include <subdev/devinit.h>
28#include <subdev/vga.h>
29
30#include "fbmem.h"
31
32struct nv04_devinit_priv {
33 struct nouveau_devinit base;
34 int owner;
35};
36
37static void
38nv04_devinit_meminit(struct nouveau_devinit *devinit)
39{
40 struct nv04_devinit_priv *priv = (void *)devinit;
41 u32 patt = 0xdeadbeef;
42 struct io_mapping *fb;
43 int i;
44
45 /* Map the framebuffer aperture */
46 fb = fbmem_init(nv_device(priv)->pdev);
47 if (!fb) {
48 nv_error(priv, "failed to map fb\n");
49 return;
50 }
51
52 /* Sequencer and refresh off */
53 nv_wrvgas(priv, 0, 1, nv_rdvgas(priv, 0, 1) | 0x20);
54 nv_mask(priv, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF);
55
56 nv_mask(priv, NV04_PFB_BOOT_0, ~0,
57 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB |
58 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
59 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT);
60
61 for (i = 0; i < 4; i++)
62 fbmem_poke(fb, 4 * i, patt);
63
64 fbmem_poke(fb, 0x400000, patt + 1);
65
66 if (fbmem_peek(fb, 0) == patt + 1) {
67 nv_mask(priv, NV04_PFB_BOOT_0,
68 NV04_PFB_BOOT_0_RAM_TYPE,
69 NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT);
70 nv_mask(priv, NV04_PFB_DEBUG_0,
71 NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
72
73 for (i = 0; i < 4; i++)
74 fbmem_poke(fb, 4 * i, patt);
75
76 if ((fbmem_peek(fb, 0xc) & 0xffff) != (patt & 0xffff))
77 nv_mask(priv, NV04_PFB_BOOT_0,
78 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
79 NV04_PFB_BOOT_0_RAM_AMOUNT,
80 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
81 } else
82 if ((fbmem_peek(fb, 0xc) & 0xffff0000) != (patt & 0xffff0000)) {
83 nv_mask(priv, NV04_PFB_BOOT_0,
84 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
85 NV04_PFB_BOOT_0_RAM_AMOUNT,
86 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
87 } else
88 if (fbmem_peek(fb, 0) != patt) {
89 if (fbmem_readback(fb, 0x800000, patt))
90 nv_mask(priv, NV04_PFB_BOOT_0,
91 NV04_PFB_BOOT_0_RAM_AMOUNT,
92 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
93 else
94 nv_mask(priv, NV04_PFB_BOOT_0,
95 NV04_PFB_BOOT_0_RAM_AMOUNT,
96 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
97
98 nv_mask(priv, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
99 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT);
100 } else
101 if (!fbmem_readback(fb, 0x800000, patt)) {
102 nv_mask(priv, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
103 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
104
105 }
106
107 /* Refresh on, sequencer on */
108 nv_mask(priv, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
109 nv_wrvgas(priv, 0, 1, nv_rdvgas(priv, 0, 1) & ~0x20);
110 fbmem_fini(fb);
111}
112
113static int
114nv04_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
115 struct nouveau_oclass *oclass, void *data, u32 size,
116 struct nouveau_object **pobject)
117{
118 struct nv04_devinit_priv *priv;
119 int ret;
120
121 ret = nouveau_devinit_create(parent, engine, oclass, &priv);
122 *pobject = nv_object(priv);
123 if (ret)
124 return ret;
125
126 priv->base.meminit = nv04_devinit_meminit;
127 priv->owner = -1;
128 return 0;
129}
130
131void
132nv04_devinit_dtor(struct nouveau_object *object)
133{
134 struct nv04_devinit_priv *priv = (void *)object;
135
136 /* restore vga owner saved at first init, and lock crtc regs */
137 nv_wrvgaowner(priv, priv->owner);
138 nv_lockvgac(priv, true);
139
140 nouveau_devinit_destroy(&priv->base);
141}
142
143int
144nv04_devinit_init(struct nouveau_object *object)
145{
146 struct nv04_devinit_priv *priv = (void *)object;
147
148 if (!priv->base.post) {
149 u32 htotal = nv_rdvgac(priv, 0, 0x06);
150 htotal |= (nv_rdvgac(priv, 0, 0x07) & 0x01) << 8;
151 htotal |= (nv_rdvgac(priv, 0, 0x07) & 0x20) << 4;
152 htotal |= (nv_rdvgac(priv, 0, 0x25) & 0x01) << 10;
153 htotal |= (nv_rdvgac(priv, 0, 0x41) & 0x01) << 11;
154 if (!htotal) {
155 nv_info(priv, "adaptor not initialised\n");
156 priv->base.post = true;
157 }
158 }
159
160 return nouveau_devinit_init(&priv->base);
161}
162
163int
164nv04_devinit_fini(struct nouveau_object *object, bool suspend)
165{
166 struct nv04_devinit_priv *priv = (void *)object;
167
168 /* make i2c busses accessible */
169 nv_mask(priv, 0x000200, 0x00000001, 0x00000001);
170
171 /* unlock extended vga crtc regs, and unslave crtcs */
172 nv_lockvgac(priv, false);
173 if (priv->owner < 0)
174 priv->owner = nv_rdvgaowner(priv);
175 nv_wrvgaowner(priv, 0);
176
177 return nouveau_devinit_fini(&priv->base, suspend);
178}
179
180struct nouveau_oclass
181nv04_devinit_oclass = {
182 .handle = NV_SUBDEV(DEVINIT, 0x04),
183 .ofuncs = &(struct nouveau_ofuncs) {
184 .ctor = nv04_devinit_ctor,
185 .dtor = nv04_devinit_dtor,
186 .init = nv04_devinit_init,
187 .fini = nv04_devinit_fini,
188 },
189};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv05.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv05.c
new file mode 100644
index 00000000000..191447d0d25
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv05.c
@@ -0,0 +1,159 @@
1/*
2 * Copyright (C) 2010 Francisco Jerez.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27#include <subdev/devinit.h>
28#include <subdev/bios.h>
29#include <subdev/bios/bmp.h>
30#include <subdev/vga.h>
31
32#include "fbmem.h"
33
34struct nv05_devinit_priv {
35 struct nouveau_devinit base;
36 u8 owner;
37};
38
39static void
40nv05_devinit_meminit(struct nouveau_devinit *devinit)
41{
42 static const u8 default_config_tab[][2] = {
43 { 0x24, 0x00 },
44 { 0x28, 0x00 },
45 { 0x24, 0x01 },
46 { 0x1f, 0x00 },
47 { 0x0f, 0x00 },
48 { 0x17, 0x00 },
49 { 0x06, 0x00 },
50 { 0x00, 0x00 }
51 };
52 struct nv05_devinit_priv *priv = (void *)devinit;
53 struct nouveau_bios *bios = nouveau_bios(priv);
54 struct io_mapping *fb;
55 u32 patt = 0xdeadbeef;
56 u16 data;
57 u8 strap, ramcfg[2];
58 int i, v;
59
60 /* Map the framebuffer aperture */
61 fb = fbmem_init(nv_device(priv)->pdev);
62 if (!fb) {
63 nv_error(priv, "failed to map fb\n");
64 return;
65 }
66
67 strap = (nv_rd32(priv, 0x101000) & 0x0000003c) >> 2;
68 if ((data = bmp_mem_init_table(bios))) {
69 ramcfg[0] = nv_ro08(bios, data + 2 * strap + 0);
70 ramcfg[1] = nv_ro08(bios, data + 2 * strap + 1);
71 } else {
72 ramcfg[0] = default_config_tab[strap][0];
73 ramcfg[1] = default_config_tab[strap][1];
74 }
75
76 /* Sequencer off */
77 nv_wrvgas(priv, 0, 1, nv_rdvgas(priv, 0, 1) | 0x20);
78
79 if (nv_rd32(priv, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_UMA_ENABLE)
80 goto out;
81
82 nv_mask(priv, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
83
84 /* If present load the hardcoded scrambling table */
85 if (data) {
86 for (i = 0, data += 0x10; i < 8; i++, data += 4) {
87 u32 scramble = nv_ro32(bios, data);
88 nv_wr32(priv, NV04_PFB_SCRAMBLE(i), scramble);
89 }
90 }
91
92 /* Set memory type/width/length defaults depending on the straps */
93 nv_mask(priv, NV04_PFB_BOOT_0, 0x3f, ramcfg[0]);
94
95 if (ramcfg[1] & 0x80)
96 nv_mask(priv, NV04_PFB_CFG0, 0, NV04_PFB_CFG0_SCRAMBLE);
97
98 nv_mask(priv, NV04_PFB_CFG1, 0x700001, (ramcfg[1] & 1) << 20);
99 nv_mask(priv, NV04_PFB_CFG1, 0, 1);
100
101 /* Probe memory bus width */
102 for (i = 0; i < 4; i++)
103 fbmem_poke(fb, 4 * i, patt);
104
105 if (fbmem_peek(fb, 0xc) != patt)
106 nv_mask(priv, NV04_PFB_BOOT_0,
107 NV04_PFB_BOOT_0_RAM_WIDTH_128, 0);
108
109 /* Probe memory length */
110 v = nv_rd32(priv, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_RAM_AMOUNT;
111
112 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_32MB &&
113 (!fbmem_readback(fb, 0x1000000, ++patt) ||
114 !fbmem_readback(fb, 0, ++patt)))
115 nv_mask(priv, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
116 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB);
117
118 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_16MB &&
119 !fbmem_readback(fb, 0x800000, ++patt))
120 nv_mask(priv, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
121 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
122
123 if (!fbmem_readback(fb, 0x400000, ++patt))
124 nv_mask(priv, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
125 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
126
127out:
128 /* Sequencer on */
129 nv_wrvgas(priv, 0, 1, nv_rdvgas(priv, 0, 1) & ~0x20);
130 fbmem_fini(fb);
131}
132
133static int
134nv05_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
135 struct nouveau_oclass *oclass, void *data, u32 size,
136 struct nouveau_object **pobject)
137{
138 struct nv05_devinit_priv *priv;
139 int ret;
140
141 ret = nouveau_devinit_create(parent, engine, oclass, &priv);
142 *pobject = nv_object(priv);
143 if (ret)
144 return ret;
145
146 priv->base.meminit = nv05_devinit_meminit;
147 return 0;
148}
149
150struct nouveau_oclass
151nv05_devinit_oclass = {
152 .handle = NV_SUBDEV(DEVINIT, 0x05),
153 .ofuncs = &(struct nouveau_ofuncs) {
154 .ctor = nv05_devinit_ctor,
155 .dtor = nv04_devinit_dtor,
156 .init = nv04_devinit_init,
157 .fini = nv04_devinit_fini,
158 },
159};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv10.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv10.c
new file mode 100644
index 00000000000..eb76ffab6b0
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv10.c
@@ -0,0 +1,124 @@
1/*
2 * Copyright (C) 2010 Francisco Jerez.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27#include <subdev/devinit.h>
28#include <subdev/vga.h>
29
30#include "fbmem.h"
31
32struct nv10_devinit_priv {
33 struct nouveau_devinit base;
34 u8 owner;
35};
36
37static void
38nv10_devinit_meminit(struct nouveau_devinit *devinit)
39{
40 struct nv10_devinit_priv *priv = (void *)devinit;
41 const int mem_width[] = { 0x10, 0x00, 0x20 };
42 const int mem_width_count = nv_device(priv)->chipset >= 0x17 ? 3 : 2;
43 uint32_t patt = 0xdeadbeef;
44 struct io_mapping *fb;
45 int i, j, k;
46
47 /* Map the framebuffer aperture */
48 fb = fbmem_init(nv_device(priv)->pdev);
49 if (!fb) {
50 nv_error(priv, "failed to map fb\n");
51 return;
52 }
53
54 nv_wr32(priv, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
55
56 /* Probe memory bus width */
57 for (i = 0; i < mem_width_count; i++) {
58 nv_mask(priv, NV04_PFB_CFG0, 0x30, mem_width[i]);
59
60 for (j = 0; j < 4; j++) {
61 for (k = 0; k < 4; k++)
62 fbmem_poke(fb, 0x1c, 0);
63
64 fbmem_poke(fb, 0x1c, patt);
65 fbmem_poke(fb, 0x3c, 0);
66
67 if (fbmem_peek(fb, 0x1c) == patt)
68 goto mem_width_found;
69 }
70 }
71
72mem_width_found:
73 patt <<= 1;
74
75 /* Probe amount of installed memory */
76 for (i = 0; i < 4; i++) {
77 int off = nv_rd32(priv, 0x10020c) - 0x100000;
78
79 fbmem_poke(fb, off, patt);
80 fbmem_poke(fb, 0, 0);
81
82 fbmem_peek(fb, 0);
83 fbmem_peek(fb, 0);
84 fbmem_peek(fb, 0);
85 fbmem_peek(fb, 0);
86
87 if (fbmem_peek(fb, off) == patt)
88 goto amount_found;
89 }
90
91 /* IC missing - disable the upper half memory space. */
92 nv_mask(priv, NV04_PFB_CFG0, 0x1000, 0);
93
94amount_found:
95 fbmem_fini(fb);
96}
97
98static int
99nv10_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
100 struct nouveau_oclass *oclass, void *data, u32 size,
101 struct nouveau_object **pobject)
102{
103 struct nv10_devinit_priv *priv;
104 int ret;
105
106 ret = nouveau_devinit_create(parent, engine, oclass, &priv);
107 *pobject = nv_object(priv);
108 if (ret)
109 return ret;
110
111 priv->base.meminit = nv10_devinit_meminit;
112 return 0;
113}
114
115struct nouveau_oclass
116nv10_devinit_oclass = {
117 .handle = NV_SUBDEV(DEVINIT, 0x10),
118 .ofuncs = &(struct nouveau_ofuncs) {
119 .ctor = nv10_devinit_ctor,
120 .dtor = nv04_devinit_dtor,
121 .init = nv04_devinit_init,
122 .fini = nv04_devinit_fini,
123 },
124};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv1a.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv1a.c
new file mode 100644
index 00000000000..5b2ba630d91
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv1a.c
@@ -0,0 +1,58 @@
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include <subdev/devinit.h>
26#include <subdev/vga.h>
27
28struct nv1a_devinit_priv {
29 struct nouveau_devinit base;
30 u8 owner;
31};
32
33static int
34nv1a_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
35 struct nouveau_oclass *oclass, void *data, u32 size,
36 struct nouveau_object **pobject)
37{
38 struct nv1a_devinit_priv *priv;
39 int ret;
40
41 ret = nouveau_devinit_create(parent, engine, oclass, &priv);
42 *pobject = nv_object(priv);
43 if (ret)
44 return ret;
45
46 return 0;
47}
48
49struct nouveau_oclass
50nv1a_devinit_oclass = {
51 .handle = NV_SUBDEV(DEVINIT, 0x1a),
52 .ofuncs = &(struct nouveau_ofuncs) {
53 .ctor = nv1a_devinit_ctor,
54 .dtor = nv04_devinit_dtor,
55 .init = nv04_devinit_init,
56 .fini = nv04_devinit_fini,
57 },
58};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv20.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv20.c
new file mode 100644
index 00000000000..eb32e99005e
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv20.c
@@ -0,0 +1,96 @@
1/*
2 * Copyright (C) 2010 Francisco Jerez.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27#include <subdev/devinit.h>
28#include <subdev/vga.h>
29
30#include "fbmem.h"
31
32struct nv20_devinit_priv {
33 struct nouveau_devinit base;
34 u8 owner;
35};
36
37static void
38nv20_devinit_meminit(struct nouveau_devinit *devinit)
39{
40 struct nv20_devinit_priv *priv = (void *)devinit;
41 struct nouveau_device *device = nv_device(priv);
42 uint32_t mask = (device->chipset >= 0x25 ? 0x300 : 0x900);
43 uint32_t amount, off;
44 struct io_mapping *fb;
45
46 /* Map the framebuffer aperture */
47 fb = fbmem_init(nv_device(priv)->pdev);
48 if (!fb) {
49 nv_error(priv, "failed to map fb\n");
50 return;
51 }
52
53 nv_wr32(priv, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
54
55 /* Allow full addressing */
56 nv_mask(priv, NV04_PFB_CFG0, 0, mask);
57
58 amount = nv_rd32(priv, 0x10020c);
59 for (off = amount; off > 0x2000000; off -= 0x2000000)
60 fbmem_poke(fb, off - 4, off);
61
62 amount = nv_rd32(priv, 0x10020c);
63 if (amount != fbmem_peek(fb, amount - 4))
64 /* IC missing - disable the upper half memory space. */
65 nv_mask(priv, NV04_PFB_CFG0, mask, 0);
66
67 fbmem_fini(fb);
68}
69
70static int
71nv20_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
72 struct nouveau_oclass *oclass, void *data, u32 size,
73 struct nouveau_object **pobject)
74{
75 struct nv20_devinit_priv *priv;
76 int ret;
77
78 ret = nouveau_devinit_create(parent, engine, oclass, &priv);
79 *pobject = nv_object(priv);
80 if (ret)
81 return ret;
82
83 priv->base.meminit = nv20_devinit_meminit;
84 return 0;
85}
86
87struct nouveau_oclass
88nv20_devinit_oclass = {
89 .handle = NV_SUBDEV(DEVINIT, 0x20),
90 .ofuncs = &(struct nouveau_ofuncs) {
91 .ctor = nv20_devinit_ctor,
92 .dtor = nv04_devinit_dtor,
93 .init = nv04_devinit_init,
94 .fini = nv04_devinit_fini,
95 },
96};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.c
new file mode 100644
index 00000000000..61becfa732e
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.c
@@ -0,0 +1,87 @@
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include <subdev/devinit.h>
26#include <subdev/vga.h>
27
28struct nv50_devinit_priv {
29 struct nouveau_devinit base;
30};
31
32static int
33nv50_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
34 struct nouveau_oclass *oclass, void *data, u32 size,
35 struct nouveau_object **pobject)
36{
37 struct nv50_devinit_priv *priv;
38 int ret;
39
40 ret = nouveau_devinit_create(parent, engine, oclass, &priv);
41 *pobject = nv_object(priv);
42 if (ret)
43 return ret;
44
45 return 0;
46}
47
48static void
49nv50_devinit_dtor(struct nouveau_object *object)
50{
51 struct nv50_devinit_priv *priv = (void *)object;
52 nouveau_devinit_destroy(&priv->base);
53}
54
55static int
56nv50_devinit_init(struct nouveau_object *object)
57{
58 struct nv50_devinit_priv *priv = (void *)object;
59
60 if (!priv->base.post) {
61 if (!nv_rdvgac(priv, 0, 0x00) &&
62 !nv_rdvgac(priv, 0, 0x1a)) {
63 nv_info(priv, "adaptor not initialised\n");
64 priv->base.post = true;
65 }
66 }
67
68 return nouveau_devinit_init(&priv->base);
69}
70
71static int
72nv50_devinit_fini(struct nouveau_object *object, bool suspend)
73{
74 struct nv50_devinit_priv *priv = (void *)object;
75 return nouveau_devinit_fini(&priv->base, suspend);
76}
77
78struct nouveau_oclass
79nv50_devinit_oclass = {
80 .handle = NV_SUBDEV(DEVINIT, 0x50),
81 .ofuncs = &(struct nouveau_ofuncs) {
82 .ctor = nv50_devinit_ctor,
83 .dtor = nv50_devinit_dtor,
84 .init = nv50_devinit_init,
85 .fini = nv50_devinit_fini,
86 },
87};
diff --git a/drivers/gpu/drm/nouveau/nouveau_agp.c b/drivers/gpu/drm/nouveau/nouveau_agp.c
index d33201c56aa..d28430cd2ba 100644
--- a/drivers/gpu/drm/nouveau/nouveau_agp.c
+++ b/drivers/gpu/drm/nouveau/nouveau_agp.c
@@ -1,10 +1,10 @@
1#include <linux/module.h> 1#include <linux/module.h>
2 2
3#include "drmP.h" 3#include <core/device.h>
4#include "drm.h"
5 4
6#include "nouveau_drv.h" 5#include "nouveau_drm.h"
7#include "nouveau_agp.h" 6#include "nouveau_agp.h"
7#include "nouveau_reg.h"
8 8
9#if __OS_HAS_AGP 9#if __OS_HAS_AGP
10MODULE_PARM_DESC(agpmode, "AGP mode (0 to disable AGP)"); 10MODULE_PARM_DESC(agpmode, "AGP mode (0 to disable AGP)");
@@ -12,15 +12,15 @@ static int nouveau_agpmode = -1;
12module_param_named(agpmode, nouveau_agpmode, int, 0400); 12module_param_named(agpmode, nouveau_agpmode, int, 0400);
13 13
14static unsigned long 14static unsigned long
15get_agp_mode(struct drm_device *dev, unsigned long mode) 15get_agp_mode(struct nouveau_drm *drm, unsigned long mode)
16{ 16{
17 struct drm_nouveau_private *dev_priv = dev->dev_private; 17 struct nouveau_device *device = nv_device(drm->device);
18 18
19 /* 19 /*
20 * FW seems to be broken on nv18, it makes the card lock up 20 * FW seems to be broken on nv18, it makes the card lock up
21 * randomly. 21 * randomly.
22 */ 22 */
23 if (dev_priv->chipset == 0x18) 23 if (device->chipset == 0x18)
24 mode &= ~PCI_AGP_COMMAND_FW; 24 mode &= ~PCI_AGP_COMMAND_FW;
25 25
26 /* 26 /*
@@ -37,42 +37,39 @@ get_agp_mode(struct drm_device *dev, unsigned long mode)
37} 37}
38 38
39static bool 39static bool
40nouveau_agp_enabled(struct drm_device *dev) 40nouveau_agp_enabled(struct nouveau_drm *drm)
41{ 41{
42 struct drm_nouveau_private *dev_priv = dev->dev_private; 42 struct drm_device *dev = drm->dev;
43 43
44 if (!drm_pci_device_is_agp(dev) || !dev->agp) 44 if (!drm_pci_device_is_agp(dev) || !dev->agp)
45 return false; 45 return false;
46 46
47 switch (dev_priv->gart_info.type) { 47 if (drm->agp.stat == UNKNOWN) {
48 case NOUVEAU_GART_NONE:
49 if (!nouveau_agpmode) 48 if (!nouveau_agpmode)
50 return false; 49 return false;
51 break; 50 return true;
52 case NOUVEAU_GART_AGP:
53 break;
54 default:
55 return false;
56 } 51 }
57 52
58 return true; 53 return (drm->agp.stat == ENABLED);
59} 54}
60#endif 55#endif
61 56
62void 57void
63nouveau_agp_reset(struct drm_device *dev) 58nouveau_agp_reset(struct nouveau_drm *drm)
64{ 59{
65#if __OS_HAS_AGP 60#if __OS_HAS_AGP
61 struct nouveau_device *device = nv_device(drm->device);
62 struct drm_device *dev = drm->dev;
66 u32 save[2]; 63 u32 save[2];
67 int ret; 64 int ret;
68 65
69 if (!nouveau_agp_enabled(dev)) 66 if (!nouveau_agp_enabled(drm))
70 return; 67 return;
71 68
72 /* First of all, disable fast writes, otherwise if it's 69 /* First of all, disable fast writes, otherwise if it's
73 * already enabled in the AGP bridge and we disable the card's 70 * already enabled in the AGP bridge and we disable the card's
74 * AGP controller we might be locking ourselves out of it. */ 71 * AGP controller we might be locking ourselves out of it. */
75 if ((nv_rd32(dev, NV04_PBUS_PCI_NV_19) | 72 if ((nv_rd32(device, NV04_PBUS_PCI_NV_19) |
76 dev->agp->mode) & PCI_AGP_COMMAND_FW) { 73 dev->agp->mode) & PCI_AGP_COMMAND_FW) {
77 struct drm_agp_info info; 74 struct drm_agp_info info;
78 struct drm_agp_mode mode; 75 struct drm_agp_mode mode;
@@ -81,7 +78,7 @@ nouveau_agp_reset(struct drm_device *dev)
81 if (ret) 78 if (ret)
82 return; 79 return;
83 80
84 mode.mode = get_agp_mode(dev, info.mode); 81 mode.mode = get_agp_mode(drm, info.mode);
85 mode.mode &= ~PCI_AGP_COMMAND_FW; 82 mode.mode &= ~PCI_AGP_COMMAND_FW;
86 83
87 ret = drm_agp_enable(dev, mode); 84 ret = drm_agp_enable(dev, mode);
@@ -91,61 +88,64 @@ nouveau_agp_reset(struct drm_device *dev)
91 88
92 89
93 /* clear busmaster bit, and disable AGP */ 90 /* clear busmaster bit, and disable AGP */
94 save[0] = nv_mask(dev, NV04_PBUS_PCI_NV_1, 0x00000004, 0x00000000); 91 save[0] = nv_mask(device, NV04_PBUS_PCI_NV_1, 0x00000004, 0x00000000);
95 nv_wr32(dev, NV04_PBUS_PCI_NV_19, 0); 92 nv_wr32(device, NV04_PBUS_PCI_NV_19, 0);
96 93
97 /* reset PGRAPH, PFIFO and PTIMER */ 94 /* reset PGRAPH, PFIFO and PTIMER */
98 save[1] = nv_mask(dev, 0x000200, 0x00011100, 0x00000000); 95 save[1] = nv_mask(device, 0x000200, 0x00011100, 0x00000000);
99 nv_mask(dev, 0x000200, 0x00011100, save[1]); 96 nv_mask(device, 0x000200, 0x00011100, save[1]);
100 97
101 /* and restore bustmaster bit (gives effect of resetting AGP) */ 98 /* and restore bustmaster bit (gives effect of resetting AGP) */
102 nv_wr32(dev, NV04_PBUS_PCI_NV_1, save[0]); 99 nv_wr32(device, NV04_PBUS_PCI_NV_1, save[0]);
103#endif 100#endif
104} 101}
105 102
106void 103void
107nouveau_agp_init(struct drm_device *dev) 104nouveau_agp_init(struct nouveau_drm *drm)
108{ 105{
109#if __OS_HAS_AGP 106#if __OS_HAS_AGP
110 struct drm_nouveau_private *dev_priv = dev->dev_private; 107 struct nouveau_device *device = nv_device(drm->device);
108 struct drm_device *dev = drm->dev;
111 struct drm_agp_info info; 109 struct drm_agp_info info;
112 struct drm_agp_mode mode; 110 struct drm_agp_mode mode;
113 int ret; 111 int ret;
114 112
115 if (!nouveau_agp_enabled(dev)) 113 if (!nouveau_agp_enabled(drm))
116 return; 114 return;
115 drm->agp.stat = DISABLE;
117 116
118 ret = drm_agp_acquire(dev); 117 ret = drm_agp_acquire(dev);
119 if (ret) { 118 if (ret) {
120 NV_ERROR(dev, "Unable to acquire AGP: %d\n", ret); 119 nv_error(device, "unable to acquire AGP: %d\n", ret);
121 return; 120 return;
122 } 121 }
123 122
124 ret = drm_agp_info(dev, &info); 123 ret = drm_agp_info(dev, &info);
125 if (ret) { 124 if (ret) {
126 NV_ERROR(dev, "Unable to get AGP info: %d\n", ret); 125 nv_error(device, "unable to get AGP info: %d\n", ret);
127 return; 126 return;
128 } 127 }
129 128
130 /* see agp.h for the AGPSTAT_* modes available */ 129 /* see agp.h for the AGPSTAT_* modes available */
131 mode.mode = get_agp_mode(dev, info.mode); 130 mode.mode = get_agp_mode(drm, info.mode);
132 131
133 ret = drm_agp_enable(dev, mode); 132 ret = drm_agp_enable(dev, mode);
134 if (ret) { 133 if (ret) {
135 NV_ERROR(dev, "Unable to enable AGP: %d\n", ret); 134 nv_error(device, "unable to enable AGP: %d\n", ret);
136 return; 135 return;
137 } 136 }
138 137
139 dev_priv->gart_info.type = NOUVEAU_GART_AGP; 138 drm->agp.stat = ENABLED;
140 dev_priv->gart_info.aper_base = info.aperture_base; 139 drm->agp.base = info.aperture_base;
141 dev_priv->gart_info.aper_size = info.aperture_size; 140 drm->agp.size = info.aperture_size;
142#endif 141#endif
143} 142}
144 143
145void 144void
146nouveau_agp_fini(struct drm_device *dev) 145nouveau_agp_fini(struct nouveau_drm *drm)
147{ 146{
148#if __OS_HAS_AGP 147#if __OS_HAS_AGP
148 struct drm_device *dev = drm->dev;
149 if (dev->agp && dev->agp->acquired) 149 if (dev->agp && dev->agp->acquired)
150 drm_agp_release(dev); 150 drm_agp_release(dev);
151#endif 151#endif
diff --git a/drivers/gpu/drm/nouveau/nouveau_agp.h b/drivers/gpu/drm/nouveau/nouveau_agp.h
index b23db55eb2c..b55c0865296 100644
--- a/drivers/gpu/drm/nouveau/nouveau_agp.h
+++ b/drivers/gpu/drm/nouveau/nouveau_agp.h
@@ -1,8 +1,10 @@
1#ifndef __NOUVEAU_AGP_H__ 1#ifndef __NOUVEAU_AGP_H__
2#define __NOUVEAU_AGP_H__ 2#define __NOUVEAU_AGP_H__
3 3
4void nouveau_agp_reset(struct drm_device *); 4struct nouveau_drm;
5void nouveau_agp_init(struct drm_device *); 5
6void nouveau_agp_fini(struct drm_device *); 6void nouveau_agp_reset(struct nouveau_drm *);
7void nouveau_agp_init(struct nouveau_drm *);
8void nouveau_agp_fini(struct nouveau_drm *);
7 9
8#endif 10#endif
diff --git a/drivers/gpu/drm/nouveau/nouveau_backlight.c b/drivers/gpu/drm/nouveau/nouveau_backlight.c
index 7266902a74e..d33e94a3451 100644
--- a/drivers/gpu/drm/nouveau/nouveau_backlight.c
+++ b/drivers/gpu/drm/nouveau/nouveau_backlight.c
@@ -181,9 +181,9 @@ nv50_backlight_init(struct drm_connector *connector)
181 struct backlight_device *bd; 181 struct backlight_device *bd;
182 const struct backlight_ops *ops; 182 const struct backlight_ops *ops;
183 183
184 nv_encoder = find_encoder(connector, OUTPUT_LVDS); 184 nv_encoder = find_encoder(connector, DCB_OUTPUT_LVDS);
185 if (!nv_encoder) { 185 if (!nv_encoder) {
186 nv_encoder = find_encoder(connector, OUTPUT_DP); 186 nv_encoder = find_encoder(connector, DCB_OUTPUT_DP);
187 if (!nv_encoder) 187 if (!nv_encoder)
188 return -ENODEV; 188 return -ENODEV;
189 } 189 }
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c
index 98eaac9da30..e7abde138e2 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.c
@@ -64,3372 +64,6 @@ static bool nv_cksum(const uint8_t *data, unsigned int length)
64 return false; 64 return false;
65} 65}
66 66
67struct init_tbl_entry {
68 char *name;
69 uint8_t id;
70 /* Return:
71 * > 0: success, length of opcode
72 * 0: success, but abort further parsing of table (INIT_DONE etc)
73 * < 0: failure, table parsing will be aborted
74 */
75 int (*handler)(struct nvbios *, uint16_t, struct init_exec *);
76};
77
78static int parse_init_table(struct nvbios *, uint16_t, struct init_exec *);
79
80#define MACRO_INDEX_SIZE 2
81#define MACRO_SIZE 8
82#define CONDITION_SIZE 12
83#define IO_FLAG_CONDITION_SIZE 9
84#define IO_CONDITION_SIZE 5
85#define MEM_INIT_SIZE 66
86
87static void still_alive(void)
88{
89#if 0
90 sync();
91 mdelay(2);
92#endif
93}
94
95static uint32_t
96munge_reg(struct nvbios *bios, uint32_t reg)
97{
98 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
99 struct dcb_entry *dcbent = bios->display.output;
100
101 if (dev_priv->card_type < NV_50)
102 return reg;
103
104 if (reg & 0x80000000) {
105 BUG_ON(bios->display.crtc < 0);
106 reg += bios->display.crtc * 0x800;
107 }
108
109 if (reg & 0x40000000) {
110 BUG_ON(!dcbent);
111
112 reg += (ffs(dcbent->or) - 1) * 0x800;
113 if ((reg & 0x20000000) && !(dcbent->sorconf.link & 1))
114 reg += 0x00000080;
115 }
116
117 reg &= ~0xe0000000;
118 return reg;
119}
120
121static int
122valid_reg(struct nvbios *bios, uint32_t reg)
123{
124 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
125 struct drm_device *dev = bios->dev;
126
127 /* C51 has misaligned regs on purpose. Marvellous */
128 if (reg & 0x2 ||
129 (reg & 0x1 && dev_priv->vbios.chip_version != 0x51))
130 NV_ERROR(dev, "======= misaligned reg 0x%08X =======\n", reg);
131
132 /* warn on C51 regs that haven't been verified accessible in tracing */
133 if (reg & 0x1 && dev_priv->vbios.chip_version == 0x51 &&
134 reg != 0x130d && reg != 0x1311 && reg != 0x60081d)
135 NV_WARN(dev, "=== C51 misaligned reg 0x%08X not verified ===\n",
136 reg);
137
138 if (reg >= (8*1024*1024)) {
139 NV_ERROR(dev, "=== reg 0x%08x out of mapped bounds ===\n", reg);
140 return 0;
141 }
142
143 return 1;
144}
145
146static bool
147valid_idx_port(struct nvbios *bios, uint16_t port)
148{
149 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
150 struct drm_device *dev = bios->dev;
151
152 /*
153 * If adding more ports here, the read/write functions below will need
154 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
155 * used for the port in question
156 */
157 if (dev_priv->card_type < NV_50) {
158 if (port == NV_CIO_CRX__COLOR)
159 return true;
160 if (port == NV_VIO_SRX)
161 return true;
162 } else {
163 if (port == NV_CIO_CRX__COLOR)
164 return true;
165 }
166
167 NV_ERROR(dev, "========== unknown indexed io port 0x%04X ==========\n",
168 port);
169
170 return false;
171}
172
173static bool
174valid_port(struct nvbios *bios, uint16_t port)
175{
176 struct drm_device *dev = bios->dev;
177
178 /*
179 * If adding more ports here, the read/write functions below will need
180 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
181 * used for the port in question
182 */
183 if (port == NV_VIO_VSE2)
184 return true;
185
186 NV_ERROR(dev, "========== unknown io port 0x%04X ==========\n", port);
187
188 return false;
189}
190
191static uint32_t
192bios_rd32(struct nvbios *bios, uint32_t reg)
193{
194 uint32_t data;
195
196 reg = munge_reg(bios, reg);
197 if (!valid_reg(bios, reg))
198 return 0;
199
200 /*
201 * C51 sometimes uses regs with bit0 set in the address. For these
202 * cases there should exist a translation in a BIOS table to an IO
203 * port address which the BIOS uses for accessing the reg
204 *
205 * These only seem to appear for the power control regs to a flat panel,
206 * and the GPIO regs at 0x60081*. In C51 mmio traces the normal regs
207 * for 0x1308 and 0x1310 are used - hence the mask below. An S3
208 * suspend-resume mmio trace from a C51 will be required to see if this
209 * is true for the power microcode in 0x14.., or whether the direct IO
210 * port access method is needed
211 */
212 if (reg & 0x1)
213 reg &= ~0x1;
214
215 data = nv_rd32(bios->dev, reg);
216
217 BIOSLOG(bios, " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
218
219 return data;
220}
221
222static void
223bios_wr32(struct nvbios *bios, uint32_t reg, uint32_t data)
224{
225 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
226
227 reg = munge_reg(bios, reg);
228 if (!valid_reg(bios, reg))
229 return;
230
231 /* see note in bios_rd32 */
232 if (reg & 0x1)
233 reg &= 0xfffffffe;
234
235 LOG_OLD_VALUE(bios_rd32(bios, reg));
236 BIOSLOG(bios, " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
237
238 if (dev_priv->vbios.execute) {
239 still_alive();
240 nv_wr32(bios->dev, reg, data);
241 }
242}
243
244static uint8_t
245bios_idxprt_rd(struct nvbios *bios, uint16_t port, uint8_t index)
246{
247 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
248 struct drm_device *dev = bios->dev;
249 uint8_t data;
250
251 if (!valid_idx_port(bios, port))
252 return 0;
253
254 if (dev_priv->card_type < NV_50) {
255 if (port == NV_VIO_SRX)
256 data = NVReadVgaSeq(dev, bios->state.crtchead, index);
257 else /* assume NV_CIO_CRX__COLOR */
258 data = NVReadVgaCrtc(dev, bios->state.crtchead, index);
259 } else {
260 uint32_t data32;
261
262 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
263 data = (data32 >> ((index & 3) << 3)) & 0xff;
264 }
265
266 BIOSLOG(bios, " Indexed IO read: Port: 0x%04X, Index: 0x%02X, "
267 "Head: 0x%02X, Data: 0x%02X\n",
268 port, index, bios->state.crtchead, data);
269 return data;
270}
271
272static void
273bios_idxprt_wr(struct nvbios *bios, uint16_t port, uint8_t index, uint8_t data)
274{
275 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
276 struct drm_device *dev = bios->dev;
277
278 if (!valid_idx_port(bios, port))
279 return;
280
281 /*
282 * The current head is maintained in the nvbios member state.crtchead.
283 * We trap changes to CR44 and update the head variable and hence the
284 * register set written.
285 * As CR44 only exists on CRTC0, we update crtchead to head0 in advance
286 * of the write, and to head1 after the write
287 */
288 if (port == NV_CIO_CRX__COLOR && index == NV_CIO_CRE_44 &&
289 data != NV_CIO_CRE_44_HEADB)
290 bios->state.crtchead = 0;
291
292 LOG_OLD_VALUE(bios_idxprt_rd(bios, port, index));
293 BIOSLOG(bios, " Indexed IO write: Port: 0x%04X, Index: 0x%02X, "
294 "Head: 0x%02X, Data: 0x%02X\n",
295 port, index, bios->state.crtchead, data);
296
297 if (bios->execute && dev_priv->card_type < NV_50) {
298 still_alive();
299 if (port == NV_VIO_SRX)
300 NVWriteVgaSeq(dev, bios->state.crtchead, index, data);
301 else /* assume NV_CIO_CRX__COLOR */
302 NVWriteVgaCrtc(dev, bios->state.crtchead, index, data);
303 } else
304 if (bios->execute) {
305 uint32_t data32, shift = (index & 3) << 3;
306
307 still_alive();
308
309 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
310 data32 &= ~(0xff << shift);
311 data32 |= (data << shift);
312 bios_wr32(bios, NV50_PDISPLAY_VGACRTC(index & ~3), data32);
313 }
314
315 if (port == NV_CIO_CRX__COLOR &&
316 index == NV_CIO_CRE_44 && data == NV_CIO_CRE_44_HEADB)
317 bios->state.crtchead = 1;
318}
319
320static uint8_t
321bios_port_rd(struct nvbios *bios, uint16_t port)
322{
323 uint8_t data, head = bios->state.crtchead;
324
325 if (!valid_port(bios, port))
326 return 0;
327
328 data = NVReadPRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port);
329
330 BIOSLOG(bios, " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
331 port, head, data);
332
333 return data;
334}
335
336static void
337bios_port_wr(struct nvbios *bios, uint16_t port, uint8_t data)
338{
339 int head = bios->state.crtchead;
340
341 if (!valid_port(bios, port))
342 return;
343
344 LOG_OLD_VALUE(bios_port_rd(bios, port));
345 BIOSLOG(bios, " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
346 port, head, data);
347
348 if (!bios->execute)
349 return;
350
351 still_alive();
352 NVWritePRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port, data);
353}
354
355static bool
356io_flag_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
357{
358 /*
359 * The IO flag condition entry has 2 bytes for the CRTC port; 1 byte
360 * for the CRTC index; 1 byte for the mask to apply to the value
361 * retrieved from the CRTC; 1 byte for the shift right to apply to the
362 * masked CRTC value; 2 bytes for the offset to the flag array, to
363 * which the shifted value is added; 1 byte for the mask applied to the
364 * value read from the flag array; and 1 byte for the value to compare
365 * against the masked byte from the flag table.
366 */
367
368 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE;
369 uint16_t crtcport = ROM16(bios->data[condptr]);
370 uint8_t crtcindex = bios->data[condptr + 2];
371 uint8_t mask = bios->data[condptr + 3];
372 uint8_t shift = bios->data[condptr + 4];
373 uint16_t flagarray = ROM16(bios->data[condptr + 5]);
374 uint8_t flagarraymask = bios->data[condptr + 7];
375 uint8_t cmpval = bios->data[condptr + 8];
376 uint8_t data;
377
378 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
379 "Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, "
380 "Cmpval: 0x%02X\n",
381 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval);
382
383 data = bios_idxprt_rd(bios, crtcport, crtcindex);
384
385 data = bios->data[flagarray + ((data & mask) >> shift)];
386 data &= flagarraymask;
387
388 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
389 offset, data, cmpval);
390
391 return (data == cmpval);
392}
393
394static bool
395bios_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
396{
397 /*
398 * The condition table entry has 4 bytes for the address of the
399 * register to check, 4 bytes for a mask to apply to the register and
400 * 4 for a test comparison value
401 */
402
403 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
404 uint32_t reg = ROM32(bios->data[condptr]);
405 uint32_t mask = ROM32(bios->data[condptr + 4]);
406 uint32_t cmpval = ROM32(bios->data[condptr + 8]);
407 uint32_t data;
408
409 BIOSLOG(bios, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X\n",
410 offset, cond, reg, mask);
411
412 data = bios_rd32(bios, reg) & mask;
413
414 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
415 offset, data, cmpval);
416
417 return (data == cmpval);
418}
419
420static bool
421io_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
422{
423 /*
424 * The IO condition entry has 2 bytes for the IO port address; 1 byte
425 * for the index to write to io_port; 1 byte for the mask to apply to
426 * the byte read from io_port+1; and 1 byte for the value to compare
427 * against the masked byte.
428 */
429
430 uint16_t condptr = bios->io_condition_tbl_ptr + cond * IO_CONDITION_SIZE;
431 uint16_t io_port = ROM16(bios->data[condptr]);
432 uint8_t port_index = bios->data[condptr + 2];
433 uint8_t mask = bios->data[condptr + 3];
434 uint8_t cmpval = bios->data[condptr + 4];
435
436 uint8_t data = bios_idxprt_rd(bios, io_port, port_index) & mask;
437
438 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
439 offset, data, cmpval);
440
441 return (data == cmpval);
442}
443
444static int dcb_entry_idx_from_crtchead(struct drm_device *dev)
445{
446 struct drm_nouveau_private *dev_priv = dev->dev_private;
447 struct nvbios *bios = &dev_priv->vbios;
448
449 /*
450 * For the results of this function to be correct, CR44 must have been
451 * set (using bios_idxprt_wr to set crtchead), CR58 set for CR57 = 0,
452 * and the DCB table parsed, before the script calling the function is
453 * run. run_digital_op_script is example of how to do such setup
454 */
455
456 uint8_t dcb_entry = NVReadVgaCrtc5758(dev, bios->state.crtchead, 0);
457
458 if (dcb_entry > bios->dcb.entries) {
459 NV_ERROR(dev, "CR58 doesn't have a valid DCB entry currently "
460 "(%02X)\n", dcb_entry);
461 dcb_entry = 0x7f; /* unused / invalid marker */
462 }
463
464 return dcb_entry;
465}
466
467static struct nouveau_i2c_port *
468init_i2c_device_find(struct drm_device *dev, int i2c_index)
469{
470 if (i2c_index == 0xff) {
471 struct drm_nouveau_private *dev_priv = dev->dev_private;
472 struct dcb_table *dcb = &dev_priv->vbios.dcb;
473 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
474 int idx = dcb_entry_idx_from_crtchead(dev);
475
476 i2c_index = 0x80; //NV_I2C_DEFAULT(0);
477 if (idx != 0x7f && dcb->entry[idx].i2c_upper_default)
478 i2c_index = 0x81; //NV_I2C_DEFAULT(1);
479 }
480
481 return nouveau_i2c_find(dev, i2c_index);
482}
483
484static uint32_t
485get_tmds_index_reg(struct drm_device *dev, uint8_t mlv)
486{
487 /*
488 * For mlv < 0x80, it is an index into a table of TMDS base addresses.
489 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
490 * CR58 for CR57 = 0 to index a table of offsets to the basic
491 * 0x6808b0 address.
492 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
493 * CR58 for CR57 = 0 to index a table of offsets to the basic
494 * 0x6808b0 address, and then flip the offset by 8.
495 */
496
497 struct drm_nouveau_private *dev_priv = dev->dev_private;
498 struct nvbios *bios = &dev_priv->vbios;
499 const int pramdac_offset[13] = {
500 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
501 const uint32_t pramdac_table[4] = {
502 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
503
504 if (mlv >= 0x80) {
505 int dcb_entry, dacoffset;
506
507 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
508 dcb_entry = dcb_entry_idx_from_crtchead(dev);
509 if (dcb_entry == 0x7f)
510 return 0;
511 dacoffset = pramdac_offset[bios->dcb.entry[dcb_entry].or];
512 if (mlv == 0x81)
513 dacoffset ^= 8;
514 return 0x6808b0 + dacoffset;
515 } else {
516 if (mlv >= ARRAY_SIZE(pramdac_table)) {
517 NV_ERROR(dev, "Magic Lookup Value too big (%02X)\n",
518 mlv);
519 return 0;
520 }
521 return pramdac_table[mlv];
522 }
523}
524
525static int
526init_io_restrict_prog(struct nvbios *bios, uint16_t offset,
527 struct init_exec *iexec)
528{
529 /*
530 * INIT_IO_RESTRICT_PROG opcode: 0x32 ('2')
531 *
532 * offset (8 bit): opcode
533 * offset + 1 (16 bit): CRTC port
534 * offset + 3 (8 bit): CRTC index
535 * offset + 4 (8 bit): mask
536 * offset + 5 (8 bit): shift
537 * offset + 6 (8 bit): count
538 * offset + 7 (32 bit): register
539 * offset + 11 (32 bit): configuration 1
540 * ...
541 *
542 * Starting at offset + 11 there are "count" 32 bit values.
543 * To find out which value to use read index "CRTC index" on "CRTC
544 * port", AND this value with "mask" and then bit shift right "shift"
545 * bits. Read the appropriate value using this index and write to
546 * "register"
547 */
548
549 uint16_t crtcport = ROM16(bios->data[offset + 1]);
550 uint8_t crtcindex = bios->data[offset + 3];
551 uint8_t mask = bios->data[offset + 4];
552 uint8_t shift = bios->data[offset + 5];
553 uint8_t count = bios->data[offset + 6];
554 uint32_t reg = ROM32(bios->data[offset + 7]);
555 uint8_t config;
556 uint32_t configval;
557 int len = 11 + count * 4;
558
559 if (!iexec->execute)
560 return len;
561
562 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
563 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
564 offset, crtcport, crtcindex, mask, shift, count, reg);
565
566 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
567 if (config > count) {
568 NV_ERROR(bios->dev,
569 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
570 offset, config, count);
571 return len;
572 }
573
574 configval = ROM32(bios->data[offset + 11 + config * 4]);
575
576 BIOSLOG(bios, "0x%04X: Writing config %02X\n", offset, config);
577
578 bios_wr32(bios, reg, configval);
579
580 return len;
581}
582
583static int
584init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
585{
586 /*
587 * INIT_REPEAT opcode: 0x33 ('3')
588 *
589 * offset (8 bit): opcode
590 * offset + 1 (8 bit): count
591 *
592 * Execute script following this opcode up to INIT_REPEAT_END
593 * "count" times
594 */
595
596 uint8_t count = bios->data[offset + 1];
597 uint8_t i;
598
599 /* no iexec->execute check by design */
600
601 BIOSLOG(bios, "0x%04X: Repeating following segment %d times\n",
602 offset, count);
603
604 iexec->repeat = true;
605
606 /*
607 * count - 1, as the script block will execute once when we leave this
608 * opcode -- this is compatible with bios behaviour as:
609 * a) the block is always executed at least once, even if count == 0
610 * b) the bios interpreter skips to the op following INIT_END_REPEAT,
611 * while we don't
612 */
613 for (i = 0; i < count - 1; i++)
614 parse_init_table(bios, offset + 2, iexec);
615
616 iexec->repeat = false;
617
618 return 2;
619}
620
621static int
622init_io_restrict_pll(struct nvbios *bios, uint16_t offset,
623 struct init_exec *iexec)
624{
625 /*
626 * INIT_IO_RESTRICT_PLL opcode: 0x34 ('4')
627 *
628 * offset (8 bit): opcode
629 * offset + 1 (16 bit): CRTC port
630 * offset + 3 (8 bit): CRTC index
631 * offset + 4 (8 bit): mask
632 * offset + 5 (8 bit): shift
633 * offset + 6 (8 bit): IO flag condition index
634 * offset + 7 (8 bit): count
635 * offset + 8 (32 bit): register
636 * offset + 12 (16 bit): frequency 1
637 * ...
638 *
639 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz).
640 * Set PLL register "register" to coefficients for frequency n,
641 * selected by reading index "CRTC index" of "CRTC port" ANDed with
642 * "mask" and shifted right by "shift".
643 *
644 * If "IO flag condition index" > 0, and condition met, double
645 * frequency before setting it.
646 */
647
648 uint16_t crtcport = ROM16(bios->data[offset + 1]);
649 uint8_t crtcindex = bios->data[offset + 3];
650 uint8_t mask = bios->data[offset + 4];
651 uint8_t shift = bios->data[offset + 5];
652 int8_t io_flag_condition_idx = bios->data[offset + 6];
653 uint8_t count = bios->data[offset + 7];
654 uint32_t reg = ROM32(bios->data[offset + 8]);
655 uint8_t config;
656 uint16_t freq;
657 int len = 12 + count * 2;
658
659 if (!iexec->execute)
660 return len;
661
662 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
663 "Shift: 0x%02X, IO Flag Condition: 0x%02X, "
664 "Count: 0x%02X, Reg: 0x%08X\n",
665 offset, crtcport, crtcindex, mask, shift,
666 io_flag_condition_idx, count, reg);
667
668 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
669 if (config > count) {
670 NV_ERROR(bios->dev,
671 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
672 offset, config, count);
673 return len;
674 }
675
676 freq = ROM16(bios->data[offset + 12 + config * 2]);
677
678 if (io_flag_condition_idx > 0) {
679 if (io_flag_condition_met(bios, offset, io_flag_condition_idx)) {
680 BIOSLOG(bios, "0x%04X: Condition fulfilled -- "
681 "frequency doubled\n", offset);
682 freq *= 2;
683 } else
684 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- "
685 "frequency unchanged\n", offset);
686 }
687
688 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n",
689 offset, reg, config, freq);
690
691 setPLL(bios->dev, reg, freq * 10);
692
693 return len;
694}
695
696static int
697init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
698{
699 /*
700 * INIT_END_REPEAT opcode: 0x36 ('6')
701 *
702 * offset (8 bit): opcode
703 *
704 * Marks the end of the block for INIT_REPEAT to repeat
705 */
706
707 /* no iexec->execute check by design */
708
709 /*
710 * iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when
711 * we're not in repeat mode
712 */
713 if (iexec->repeat)
714 return 0;
715
716 return 1;
717}
718
719static int
720init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
721{
722 /*
723 * INIT_COPY opcode: 0x37 ('7')
724 *
725 * offset (8 bit): opcode
726 * offset + 1 (32 bit): register
727 * offset + 5 (8 bit): shift
728 * offset + 6 (8 bit): srcmask
729 * offset + 7 (16 bit): CRTC port
730 * offset + 9 (8 bit): CRTC index
731 * offset + 10 (8 bit): mask
732 *
733 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with
734 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC
735 * port
736 */
737
738 uint32_t reg = ROM32(bios->data[offset + 1]);
739 uint8_t shift = bios->data[offset + 5];
740 uint8_t srcmask = bios->data[offset + 6];
741 uint16_t crtcport = ROM16(bios->data[offset + 7]);
742 uint8_t crtcindex = bios->data[offset + 9];
743 uint8_t mask = bios->data[offset + 10];
744 uint32_t data;
745 uint8_t crtcdata;
746
747 if (!iexec->execute)
748 return 11;
749
750 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, "
751 "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n",
752 offset, reg, shift, srcmask, crtcport, crtcindex, mask);
753
754 data = bios_rd32(bios, reg);
755
756 if (shift < 0x80)
757 data >>= shift;
758 else
759 data <<= (0x100 - shift);
760
761 data &= srcmask;
762
763 crtcdata = bios_idxprt_rd(bios, crtcport, crtcindex) & mask;
764 crtcdata |= (uint8_t)data;
765 bios_idxprt_wr(bios, crtcport, crtcindex, crtcdata);
766
767 return 11;
768}
769
770static int
771init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
772{
773 /*
774 * INIT_NOT opcode: 0x38 ('8')
775 *
776 * offset (8 bit): opcode
777 *
778 * Invert the current execute / no-execute condition (i.e. "else")
779 */
780 if (iexec->execute)
781 BIOSLOG(bios, "0x%04X: ------ Skipping following commands ------\n", offset);
782 else
783 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", offset);
784
785 iexec->execute = !iexec->execute;
786 return 1;
787}
788
789static int
790init_io_flag_condition(struct nvbios *bios, uint16_t offset,
791 struct init_exec *iexec)
792{
793 /*
794 * INIT_IO_FLAG_CONDITION opcode: 0x39 ('9')
795 *
796 * offset (8 bit): opcode
797 * offset + 1 (8 bit): condition number
798 *
799 * Check condition "condition number" in the IO flag condition table.
800 * If condition not met skip subsequent opcodes until condition is
801 * inverted (INIT_NOT), or we hit INIT_RESUME
802 */
803
804 uint8_t cond = bios->data[offset + 1];
805
806 if (!iexec->execute)
807 return 2;
808
809 if (io_flag_condition_met(bios, offset, cond))
810 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
811 else {
812 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
813 iexec->execute = false;
814 }
815
816 return 2;
817}
818
819static int
820init_dp_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
821{
822 /*
823 * INIT_DP_CONDITION opcode: 0x3A ('')
824 *
825 * offset (8 bit): opcode
826 * offset + 1 (8 bit): "sub" opcode
827 * offset + 2 (8 bit): unknown
828 *
829 */
830
831 struct dcb_entry *dcb = bios->display.output;
832 struct drm_device *dev = bios->dev;
833 uint8_t cond = bios->data[offset + 1];
834 uint8_t *table, *entry;
835
836 BIOSLOG(bios, "0x%04X: subop 0x%02X\n", offset, cond);
837
838 if (!iexec->execute)
839 return 3;
840
841 table = nouveau_dp_bios_data(dev, dcb, &entry);
842 if (!table)
843 return 3;
844
845 switch (cond) {
846 case 0:
847 entry = dcb_conn(dev, dcb->connector);
848 if (!entry || entry[0] != DCB_CONNECTOR_eDP)
849 iexec->execute = false;
850 break;
851 case 1:
852 case 2:
853 if ((table[0] < 0x40 && !(entry[5] & cond)) ||
854 (table[0] == 0x40 && !(entry[4] & cond)))
855 iexec->execute = false;
856 break;
857 case 5:
858 {
859 struct nouveau_i2c_port *auxch;
860 int ret;
861
862 auxch = nouveau_i2c_find(dev, bios->display.output->i2c_index);
863 if (!auxch) {
864 NV_ERROR(dev, "0x%04X: couldn't get auxch\n", offset);
865 return 3;
866 }
867
868 ret = auxch_rd(dev, auxch, 0xd, &cond, 1);
869 if (ret) {
870 NV_ERROR(dev, "0x%04X: auxch rd fail: %d\n", offset, ret);
871 return 3;
872 }
873
874 if (!(cond & 1))
875 iexec->execute = false;
876 }
877 break;
878 default:
879 NV_WARN(dev, "0x%04X: unknown INIT_3A op: %d\n", offset, cond);
880 break;
881 }
882
883 if (iexec->execute)
884 BIOSLOG(bios, "0x%04X: continuing to execute\n", offset);
885 else
886 BIOSLOG(bios, "0x%04X: skipping following commands\n", offset);
887
888 return 3;
889}
890
891static int
892init_op_3b(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
893{
894 /*
895 * INIT_3B opcode: 0x3B ('')
896 *
897 * offset (8 bit): opcode
898 * offset + 1 (8 bit): crtc index
899 *
900 */
901
902 uint8_t or = ffs(bios->display.output->or) - 1;
903 uint8_t index = bios->data[offset + 1];
904 uint8_t data;
905
906 if (!iexec->execute)
907 return 2;
908
909 data = bios_idxprt_rd(bios, 0x3d4, index);
910 bios_idxprt_wr(bios, 0x3d4, index, data & ~(1 << or));
911 return 2;
912}
913
914static int
915init_op_3c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
916{
917 /*
918 * INIT_3C opcode: 0x3C ('')
919 *
920 * offset (8 bit): opcode
921 * offset + 1 (8 bit): crtc index
922 *
923 */
924
925 uint8_t or = ffs(bios->display.output->or) - 1;
926 uint8_t index = bios->data[offset + 1];
927 uint8_t data;
928
929 if (!iexec->execute)
930 return 2;
931
932 data = bios_idxprt_rd(bios, 0x3d4, index);
933 bios_idxprt_wr(bios, 0x3d4, index, data | (1 << or));
934 return 2;
935}
936
937static int
938init_idx_addr_latched(struct nvbios *bios, uint16_t offset,
939 struct init_exec *iexec)
940{
941 /*
942 * INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I')
943 *
944 * offset (8 bit): opcode
945 * offset + 1 (32 bit): control register
946 * offset + 5 (32 bit): data register
947 * offset + 9 (32 bit): mask
948 * offset + 13 (32 bit): data
949 * offset + 17 (8 bit): count
950 * offset + 18 (8 bit): address 1
951 * offset + 19 (8 bit): data 1
952 * ...
953 *
954 * For each of "count" address and data pairs, write "data n" to
955 * "data register", read the current value of "control register",
956 * and write it back once ANDed with "mask", ORed with "data",
957 * and ORed with "address n"
958 */
959
960 uint32_t controlreg = ROM32(bios->data[offset + 1]);
961 uint32_t datareg = ROM32(bios->data[offset + 5]);
962 uint32_t mask = ROM32(bios->data[offset + 9]);
963 uint32_t data = ROM32(bios->data[offset + 13]);
964 uint8_t count = bios->data[offset + 17];
965 int len = 18 + count * 2;
966 uint32_t value;
967 int i;
968
969 if (!iexec->execute)
970 return len;
971
972 BIOSLOG(bios, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, "
973 "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n",
974 offset, controlreg, datareg, mask, data, count);
975
976 for (i = 0; i < count; i++) {
977 uint8_t instaddress = bios->data[offset + 18 + i * 2];
978 uint8_t instdata = bios->data[offset + 19 + i * 2];
979
980 BIOSLOG(bios, "0x%04X: Address: 0x%02X, Data: 0x%02X\n",
981 offset, instaddress, instdata);
982
983 bios_wr32(bios, datareg, instdata);
984 value = bios_rd32(bios, controlreg) & mask;
985 value |= data;
986 value |= instaddress;
987 bios_wr32(bios, controlreg, value);
988 }
989
990 return len;
991}
992
993static int
994init_io_restrict_pll2(struct nvbios *bios, uint16_t offset,
995 struct init_exec *iexec)
996{
997 /*
998 * INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J')
999 *
1000 * offset (8 bit): opcode
1001 * offset + 1 (16 bit): CRTC port
1002 * offset + 3 (8 bit): CRTC index
1003 * offset + 4 (8 bit): mask
1004 * offset + 5 (8 bit): shift
1005 * offset + 6 (8 bit): count
1006 * offset + 7 (32 bit): register
1007 * offset + 11 (32 bit): frequency 1
1008 * ...
1009 *
1010 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz).
1011 * Set PLL register "register" to coefficients for frequency n,
1012 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1013 * "mask" and shifted right by "shift".
1014 */
1015
1016 uint16_t crtcport = ROM16(bios->data[offset + 1]);
1017 uint8_t crtcindex = bios->data[offset + 3];
1018 uint8_t mask = bios->data[offset + 4];
1019 uint8_t shift = bios->data[offset + 5];
1020 uint8_t count = bios->data[offset + 6];
1021 uint32_t reg = ROM32(bios->data[offset + 7]);
1022 int len = 11 + count * 4;
1023 uint8_t config;
1024 uint32_t freq;
1025
1026 if (!iexec->execute)
1027 return len;
1028
1029 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
1030 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1031 offset, crtcport, crtcindex, mask, shift, count, reg);
1032
1033 if (!reg)
1034 return len;
1035
1036 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
1037 if (config > count) {
1038 NV_ERROR(bios->dev,
1039 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1040 offset, config, count);
1041 return len;
1042 }
1043
1044 freq = ROM32(bios->data[offset + 11 + config * 4]);
1045
1046 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n",
1047 offset, reg, config, freq);
1048
1049 setPLL(bios->dev, reg, freq);
1050
1051 return len;
1052}
1053
1054static int
1055init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1056{
1057 /*
1058 * INIT_PLL2 opcode: 0x4B ('K')
1059 *
1060 * offset (8 bit): opcode
1061 * offset + 1 (32 bit): register
1062 * offset + 5 (32 bit): freq
1063 *
1064 * Set PLL register "register" to coefficients for frequency "freq"
1065 */
1066
1067 uint32_t reg = ROM32(bios->data[offset + 1]);
1068 uint32_t freq = ROM32(bios->data[offset + 5]);
1069
1070 if (!iexec->execute)
1071 return 9;
1072
1073 BIOSLOG(bios, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n",
1074 offset, reg, freq);
1075
1076 setPLL(bios->dev, reg, freq);
1077 return 9;
1078}
1079
1080static int
1081init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1082{
1083 /*
1084 * INIT_I2C_BYTE opcode: 0x4C ('L')
1085 *
1086 * offset (8 bit): opcode
1087 * offset + 1 (8 bit): DCB I2C table entry index
1088 * offset + 2 (8 bit): I2C slave address
1089 * offset + 3 (8 bit): count
1090 * offset + 4 (8 bit): I2C register 1
1091 * offset + 5 (8 bit): mask 1
1092 * offset + 6 (8 bit): data 1
1093 * ...
1094 *
1095 * For each of "count" registers given by "I2C register n" on the device
1096 * addressed by "I2C slave address" on the I2C bus given by
1097 * "DCB I2C table entry index", read the register, AND the result with
1098 * "mask n" and OR it with "data n" before writing it back to the device
1099 */
1100
1101 struct drm_device *dev = bios->dev;
1102 uint8_t i2c_index = bios->data[offset + 1];
1103 uint8_t i2c_address = bios->data[offset + 2] >> 1;
1104 uint8_t count = bios->data[offset + 3];
1105 struct nouveau_i2c_port *chan;
1106 int len = 4 + count * 3;
1107 int ret, i;
1108
1109 if (!iexec->execute)
1110 return len;
1111
1112 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1113 "Count: 0x%02X\n",
1114 offset, i2c_index, i2c_address, count);
1115
1116 chan = init_i2c_device_find(dev, i2c_index);
1117 if (!chan) {
1118 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1119 return len;
1120 }
1121
1122 for (i = 0; i < count; i++) {
1123 uint8_t reg = bios->data[offset + 4 + i * 3];
1124 uint8_t mask = bios->data[offset + 5 + i * 3];
1125 uint8_t data = bios->data[offset + 6 + i * 3];
1126 union i2c_smbus_data val;
1127
1128 ret = i2c_smbus_xfer(nouveau_i2c_adapter(chan), i2c_address, 0,
1129 I2C_SMBUS_READ, reg,
1130 I2C_SMBUS_BYTE_DATA, &val);
1131 if (ret < 0) {
1132 NV_ERROR(dev, "0x%04X: i2c rd fail: %d\n", offset, ret);
1133 return len;
1134 }
1135
1136 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
1137 "Mask: 0x%02X, Data: 0x%02X\n",
1138 offset, reg, val.byte, mask, data);
1139
1140 if (!bios->execute)
1141 continue;
1142
1143 val.byte &= mask;
1144 val.byte |= data;
1145 ret = i2c_smbus_xfer(nouveau_i2c_adapter(chan), i2c_address, 0,
1146 I2C_SMBUS_WRITE, reg,
1147 I2C_SMBUS_BYTE_DATA, &val);
1148 if (ret < 0) {
1149 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1150 return len;
1151 }
1152 }
1153
1154 return len;
1155}
1156
1157static int
1158init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1159{
1160 /*
1161 * INIT_ZM_I2C_BYTE opcode: 0x4D ('M')
1162 *
1163 * offset (8 bit): opcode
1164 * offset + 1 (8 bit): DCB I2C table entry index
1165 * offset + 2 (8 bit): I2C slave address
1166 * offset + 3 (8 bit): count
1167 * offset + 4 (8 bit): I2C register 1
1168 * offset + 5 (8 bit): data 1
1169 * ...
1170 *
1171 * For each of "count" registers given by "I2C register n" on the device
1172 * addressed by "I2C slave address" on the I2C bus given by
1173 * "DCB I2C table entry index", set the register to "data n"
1174 */
1175
1176 struct drm_device *dev = bios->dev;
1177 uint8_t i2c_index = bios->data[offset + 1];
1178 uint8_t i2c_address = bios->data[offset + 2] >> 1;
1179 uint8_t count = bios->data[offset + 3];
1180 struct nouveau_i2c_port *chan;
1181 int len = 4 + count * 2;
1182 int ret, i;
1183
1184 if (!iexec->execute)
1185 return len;
1186
1187 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1188 "Count: 0x%02X\n",
1189 offset, i2c_index, i2c_address, count);
1190
1191 chan = init_i2c_device_find(dev, i2c_index);
1192 if (!chan) {
1193 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1194 return len;
1195 }
1196
1197 for (i = 0; i < count; i++) {
1198 uint8_t reg = bios->data[offset + 4 + i * 2];
1199 union i2c_smbus_data val;
1200
1201 val.byte = bios->data[offset + 5 + i * 2];
1202
1203 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Data: 0x%02X\n",
1204 offset, reg, val.byte);
1205
1206 if (!bios->execute)
1207 continue;
1208
1209 ret = i2c_smbus_xfer(nouveau_i2c_adapter(chan), i2c_address, 0,
1210 I2C_SMBUS_WRITE, reg,
1211 I2C_SMBUS_BYTE_DATA, &val);
1212 if (ret < 0) {
1213 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1214 return len;
1215 }
1216 }
1217
1218 return len;
1219}
1220
1221static int
1222init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1223{
1224 /*
1225 * INIT_ZM_I2C opcode: 0x4E ('N')
1226 *
1227 * offset (8 bit): opcode
1228 * offset + 1 (8 bit): DCB I2C table entry index
1229 * offset + 2 (8 bit): I2C slave address
1230 * offset + 3 (8 bit): count
1231 * offset + 4 (8 bit): data 1
1232 * ...
1233 *
1234 * Send "count" bytes ("data n") to the device addressed by "I2C slave
1235 * address" on the I2C bus given by "DCB I2C table entry index"
1236 */
1237
1238 struct drm_device *dev = bios->dev;
1239 uint8_t i2c_index = bios->data[offset + 1];
1240 uint8_t i2c_address = bios->data[offset + 2] >> 1;
1241 uint8_t count = bios->data[offset + 3];
1242 int len = 4 + count;
1243 struct nouveau_i2c_port *chan;
1244 struct i2c_msg msg;
1245 uint8_t data[256];
1246 int ret, i;
1247
1248 if (!iexec->execute)
1249 return len;
1250
1251 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1252 "Count: 0x%02X\n",
1253 offset, i2c_index, i2c_address, count);
1254
1255 chan = init_i2c_device_find(dev, i2c_index);
1256 if (!chan) {
1257 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1258 return len;
1259 }
1260
1261 for (i = 0; i < count; i++) {
1262 data[i] = bios->data[offset + 4 + i];
1263
1264 BIOSLOG(bios, "0x%04X: Data: 0x%02X\n", offset, data[i]);
1265 }
1266
1267 if (bios->execute) {
1268 msg.addr = i2c_address;
1269 msg.flags = 0;
1270 msg.len = count;
1271 msg.buf = data;
1272 ret = i2c_transfer(nouveau_i2c_adapter(chan), &msg, 1);
1273 if (ret != 1) {
1274 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1275 return len;
1276 }
1277 }
1278
1279 return len;
1280}
1281
1282static int
1283init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1284{
1285 /*
1286 * INIT_TMDS opcode: 0x4F ('O') (non-canon name)
1287 *
1288 * offset (8 bit): opcode
1289 * offset + 1 (8 bit): magic lookup value
1290 * offset + 2 (8 bit): TMDS address
1291 * offset + 3 (8 bit): mask
1292 * offset + 4 (8 bit): data
1293 *
1294 * Read the data reg for TMDS address "TMDS address", AND it with mask
1295 * and OR it with data, then write it back
1296 * "magic lookup value" determines which TMDS base address register is
1297 * used -- see get_tmds_index_reg()
1298 */
1299
1300 struct drm_device *dev = bios->dev;
1301 uint8_t mlv = bios->data[offset + 1];
1302 uint32_t tmdsaddr = bios->data[offset + 2];
1303 uint8_t mask = bios->data[offset + 3];
1304 uint8_t data = bios->data[offset + 4];
1305 uint32_t reg, value;
1306
1307 if (!iexec->execute)
1308 return 5;
1309
1310 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, "
1311 "Mask: 0x%02X, Data: 0x%02X\n",
1312 offset, mlv, tmdsaddr, mask, data);
1313
1314 reg = get_tmds_index_reg(bios->dev, mlv);
1315 if (!reg) {
1316 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset);
1317 return 5;
1318 }
1319
1320 bios_wr32(bios, reg,
1321 tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE);
1322 value = (bios_rd32(bios, reg + 4) & mask) | data;
1323 bios_wr32(bios, reg + 4, value);
1324 bios_wr32(bios, reg, tmdsaddr);
1325
1326 return 5;
1327}
1328
1329static int
1330init_zm_tmds_group(struct nvbios *bios, uint16_t offset,
1331 struct init_exec *iexec)
1332{
1333 /*
1334 * INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name)
1335 *
1336 * offset (8 bit): opcode
1337 * offset + 1 (8 bit): magic lookup value
1338 * offset + 2 (8 bit): count
1339 * offset + 3 (8 bit): addr 1
1340 * offset + 4 (8 bit): data 1
1341 * ...
1342 *
1343 * For each of "count" TMDS address and data pairs write "data n" to
1344 * "addr n". "magic lookup value" determines which TMDS base address
1345 * register is used -- see get_tmds_index_reg()
1346 */
1347
1348 struct drm_device *dev = bios->dev;
1349 uint8_t mlv = bios->data[offset + 1];
1350 uint8_t count = bios->data[offset + 2];
1351 int len = 3 + count * 2;
1352 uint32_t reg;
1353 int i;
1354
1355 if (!iexec->execute)
1356 return len;
1357
1358 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n",
1359 offset, mlv, count);
1360
1361 reg = get_tmds_index_reg(bios->dev, mlv);
1362 if (!reg) {
1363 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset);
1364 return len;
1365 }
1366
1367 for (i = 0; i < count; i++) {
1368 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2];
1369 uint8_t tmdsdata = bios->data[offset + 4 + i * 2];
1370
1371 bios_wr32(bios, reg + 4, tmdsdata);
1372 bios_wr32(bios, reg, tmdsaddr);
1373 }
1374
1375 return len;
1376}
1377
1378static int
1379init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset,
1380 struct init_exec *iexec)
1381{
1382 /*
1383 * INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q')
1384 *
1385 * offset (8 bit): opcode
1386 * offset + 1 (8 bit): CRTC index1
1387 * offset + 2 (8 bit): CRTC index2
1388 * offset + 3 (8 bit): baseaddr
1389 * offset + 4 (8 bit): count
1390 * offset + 5 (8 bit): data 1
1391 * ...
1392 *
1393 * For each of "count" address and data pairs, write "baseaddr + n" to
1394 * "CRTC index1" and "data n" to "CRTC index2"
1395 * Once complete, restore initial value read from "CRTC index1"
1396 */
1397 uint8_t crtcindex1 = bios->data[offset + 1];
1398 uint8_t crtcindex2 = bios->data[offset + 2];
1399 uint8_t baseaddr = bios->data[offset + 3];
1400 uint8_t count = bios->data[offset + 4];
1401 int len = 5 + count;
1402 uint8_t oldaddr, data;
1403 int i;
1404
1405 if (!iexec->execute)
1406 return len;
1407
1408 BIOSLOG(bios, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, "
1409 "BaseAddr: 0x%02X, Count: 0x%02X\n",
1410 offset, crtcindex1, crtcindex2, baseaddr, count);
1411
1412 oldaddr = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex1);
1413
1414 for (i = 0; i < count; i++) {
1415 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1,
1416 baseaddr + i);
1417 data = bios->data[offset + 5 + i];
1418 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex2, data);
1419 }
1420
1421 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, oldaddr);
1422
1423 return len;
1424}
1425
1426static int
1427init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1428{
1429 /*
1430 * INIT_CR opcode: 0x52 ('R')
1431 *
1432 * offset (8 bit): opcode
1433 * offset + 1 (8 bit): CRTC index
1434 * offset + 2 (8 bit): mask
1435 * offset + 3 (8 bit): data
1436 *
1437 * Assign the value of at "CRTC index" ANDed with mask and ORed with
1438 * data back to "CRTC index"
1439 */
1440
1441 uint8_t crtcindex = bios->data[offset + 1];
1442 uint8_t mask = bios->data[offset + 2];
1443 uint8_t data = bios->data[offset + 3];
1444 uint8_t value;
1445
1446 if (!iexec->execute)
1447 return 4;
1448
1449 BIOSLOG(bios, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1450 offset, crtcindex, mask, data);
1451
1452 value = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex) & mask;
1453 value |= data;
1454 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, value);
1455
1456 return 4;
1457}
1458
1459static int
1460init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1461{
1462 /*
1463 * INIT_ZM_CR opcode: 0x53 ('S')
1464 *
1465 * offset (8 bit): opcode
1466 * offset + 1 (8 bit): CRTC index
1467 * offset + 2 (8 bit): value
1468 *
1469 * Assign "value" to CRTC register with index "CRTC index".
1470 */
1471
1472 uint8_t crtcindex = ROM32(bios->data[offset + 1]);
1473 uint8_t data = bios->data[offset + 2];
1474
1475 if (!iexec->execute)
1476 return 3;
1477
1478 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, data);
1479
1480 return 3;
1481}
1482
1483static int
1484init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1485{
1486 /*
1487 * INIT_ZM_CR_GROUP opcode: 0x54 ('T')
1488 *
1489 * offset (8 bit): opcode
1490 * offset + 1 (8 bit): count
1491 * offset + 2 (8 bit): CRTC index 1
1492 * offset + 3 (8 bit): value 1
1493 * ...
1494 *
1495 * For "count", assign "value n" to CRTC register with index
1496 * "CRTC index n".
1497 */
1498
1499 uint8_t count = bios->data[offset + 1];
1500 int len = 2 + count * 2;
1501 int i;
1502
1503 if (!iexec->execute)
1504 return len;
1505
1506 for (i = 0; i < count; i++)
1507 init_zm_cr(bios, offset + 2 + 2 * i - 1, iexec);
1508
1509 return len;
1510}
1511
1512static int
1513init_condition_time(struct nvbios *bios, uint16_t offset,
1514 struct init_exec *iexec)
1515{
1516 /*
1517 * INIT_CONDITION_TIME opcode: 0x56 ('V')
1518 *
1519 * offset (8 bit): opcode
1520 * offset + 1 (8 bit): condition number
1521 * offset + 2 (8 bit): retries / 50
1522 *
1523 * Check condition "condition number" in the condition table.
1524 * Bios code then sleeps for 2ms if the condition is not met, and
1525 * repeats up to "retries" times, but on one C51 this has proved
1526 * insufficient. In mmiotraces the driver sleeps for 20ms, so we do
1527 * this, and bail after "retries" times, or 2s, whichever is less.
1528 * If still not met after retries, clear execution flag for this table.
1529 */
1530
1531 uint8_t cond = bios->data[offset + 1];
1532 uint16_t retries = bios->data[offset + 2] * 50;
1533 unsigned cnt;
1534
1535 if (!iexec->execute)
1536 return 3;
1537
1538 if (retries > 100)
1539 retries = 100;
1540
1541 BIOSLOG(bios, "0x%04X: Condition: 0x%02X, Retries: 0x%02X\n",
1542 offset, cond, retries);
1543
1544 if (!bios->execute) /* avoid 2s delays when "faking" execution */
1545 retries = 1;
1546
1547 for (cnt = 0; cnt < retries; cnt++) {
1548 if (bios_condition_met(bios, offset, cond)) {
1549 BIOSLOG(bios, "0x%04X: Condition met, continuing\n",
1550 offset);
1551 break;
1552 } else {
1553 BIOSLOG(bios, "0x%04X: "
1554 "Condition not met, sleeping for 20ms\n",
1555 offset);
1556 mdelay(20);
1557 }
1558 }
1559
1560 if (!bios_condition_met(bios, offset, cond)) {
1561 NV_WARN(bios->dev,
1562 "0x%04X: Condition still not met after %dms, "
1563 "skipping following opcodes\n", offset, 20 * retries);
1564 iexec->execute = false;
1565 }
1566
1567 return 3;
1568}
1569
1570static int
1571init_ltime(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1572{
1573 /*
1574 * INIT_LTIME opcode: 0x57 ('V')
1575 *
1576 * offset (8 bit): opcode
1577 * offset + 1 (16 bit): time
1578 *
1579 * Sleep for "time" milliseconds.
1580 */
1581
1582 unsigned time = ROM16(bios->data[offset + 1]);
1583
1584 if (!iexec->execute)
1585 return 3;
1586
1587 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X milliseconds\n",
1588 offset, time);
1589
1590 mdelay(time);
1591
1592 return 3;
1593}
1594
1595static int
1596init_zm_reg_sequence(struct nvbios *bios, uint16_t offset,
1597 struct init_exec *iexec)
1598{
1599 /*
1600 * INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X')
1601 *
1602 * offset (8 bit): opcode
1603 * offset + 1 (32 bit): base register
1604 * offset + 5 (8 bit): count
1605 * offset + 6 (32 bit): value 1
1606 * ...
1607 *
1608 * Starting at offset + 6 there are "count" 32 bit values.
1609 * For "count" iterations set "base register" + 4 * current_iteration
1610 * to "value current_iteration"
1611 */
1612
1613 uint32_t basereg = ROM32(bios->data[offset + 1]);
1614 uint32_t count = bios->data[offset + 5];
1615 int len = 6 + count * 4;
1616 int i;
1617
1618 if (!iexec->execute)
1619 return len;
1620
1621 BIOSLOG(bios, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n",
1622 offset, basereg, count);
1623
1624 for (i = 0; i < count; i++) {
1625 uint32_t reg = basereg + i * 4;
1626 uint32_t data = ROM32(bios->data[offset + 6 + i * 4]);
1627
1628 bios_wr32(bios, reg, data);
1629 }
1630
1631 return len;
1632}
1633
1634static int
1635init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1636{
1637 /*
1638 * INIT_SUB_DIRECT opcode: 0x5B ('[')
1639 *
1640 * offset (8 bit): opcode
1641 * offset + 1 (16 bit): subroutine offset (in bios)
1642 *
1643 * Calls a subroutine that will execute commands until INIT_DONE
1644 * is found.
1645 */
1646
1647 uint16_t sub_offset = ROM16(bios->data[offset + 1]);
1648
1649 if (!iexec->execute)
1650 return 3;
1651
1652 BIOSLOG(bios, "0x%04X: Executing subroutine at 0x%04X\n",
1653 offset, sub_offset);
1654
1655 parse_init_table(bios, sub_offset, iexec);
1656
1657 BIOSLOG(bios, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset);
1658
1659 return 3;
1660}
1661
1662static int
1663init_jump(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1664{
1665 /*
1666 * INIT_JUMP opcode: 0x5C ('\')
1667 *
1668 * offset (8 bit): opcode
1669 * offset + 1 (16 bit): offset (in bios)
1670 *
1671 * Continue execution of init table from 'offset'
1672 */
1673
1674 uint16_t jmp_offset = ROM16(bios->data[offset + 1]);
1675
1676 if (!iexec->execute)
1677 return 3;
1678
1679 BIOSLOG(bios, "0x%04X: Jump to 0x%04X\n", offset, jmp_offset);
1680 return jmp_offset - offset;
1681}
1682
1683static int
1684init_i2c_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1685{
1686 /*
1687 * INIT_I2C_IF opcode: 0x5E ('^')
1688 *
1689 * offset (8 bit): opcode
1690 * offset + 1 (8 bit): DCB I2C table entry index
1691 * offset + 2 (8 bit): I2C slave address
1692 * offset + 3 (8 bit): I2C register
1693 * offset + 4 (8 bit): mask
1694 * offset + 5 (8 bit): data
1695 *
1696 * Read the register given by "I2C register" on the device addressed
1697 * by "I2C slave address" on the I2C bus given by "DCB I2C table
1698 * entry index". Compare the result AND "mask" to "data".
1699 * If they're not equal, skip subsequent opcodes until condition is
1700 * inverted (INIT_NOT), or we hit INIT_RESUME
1701 */
1702
1703 uint8_t i2c_index = bios->data[offset + 1];
1704 uint8_t i2c_address = bios->data[offset + 2] >> 1;
1705 uint8_t reg = bios->data[offset + 3];
1706 uint8_t mask = bios->data[offset + 4];
1707 uint8_t data = bios->data[offset + 5];
1708 struct nouveau_i2c_port *chan;
1709 union i2c_smbus_data val;
1710 int ret;
1711
1712 /* no execute check by design */
1713
1714 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X\n",
1715 offset, i2c_index, i2c_address);
1716
1717 chan = init_i2c_device_find(bios->dev, i2c_index);
1718 if (!chan)
1719 return -ENODEV;
1720
1721 ret = i2c_smbus_xfer(nouveau_i2c_adapter(chan), i2c_address, 0,
1722 I2C_SMBUS_READ, reg,
1723 I2C_SMBUS_BYTE_DATA, &val);
1724 if (ret < 0) {
1725 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: [no device], "
1726 "Mask: 0x%02X, Data: 0x%02X\n",
1727 offset, reg, mask, data);
1728 iexec->execute = 0;
1729 return 6;
1730 }
1731
1732 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
1733 "Mask: 0x%02X, Data: 0x%02X\n",
1734 offset, reg, val.byte, mask, data);
1735
1736 iexec->execute = ((val.byte & mask) == data);
1737
1738 return 6;
1739}
1740
1741static int
1742init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1743{
1744 /*
1745 * INIT_COPY_NV_REG opcode: 0x5F ('_')
1746 *
1747 * offset (8 bit): opcode
1748 * offset + 1 (32 bit): src reg
1749 * offset + 5 (8 bit): shift
1750 * offset + 6 (32 bit): src mask
1751 * offset + 10 (32 bit): xor
1752 * offset + 14 (32 bit): dst reg
1753 * offset + 18 (32 bit): dst mask
1754 *
1755 * Shift REGVAL("src reg") right by (signed) "shift", AND result with
1756 * "src mask", then XOR with "xor". Write this OR'd with
1757 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg"
1758 */
1759
1760 uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1]));
1761 uint8_t shift = bios->data[offset + 5];
1762 uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6]));
1763 uint32_t xor = *((uint32_t *)(&bios->data[offset + 10]));
1764 uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14]));
1765 uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18]));
1766 uint32_t srcvalue, dstvalue;
1767
1768 if (!iexec->execute)
1769 return 22;
1770
1771 BIOSLOG(bios, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, "
1772 "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n",
1773 offset, srcreg, shift, srcmask, xor, dstreg, dstmask);
1774
1775 srcvalue = bios_rd32(bios, srcreg);
1776
1777 if (shift < 0x80)
1778 srcvalue >>= shift;
1779 else
1780 srcvalue <<= (0x100 - shift);
1781
1782 srcvalue = (srcvalue & srcmask) ^ xor;
1783
1784 dstvalue = bios_rd32(bios, dstreg) & dstmask;
1785
1786 bios_wr32(bios, dstreg, dstvalue | srcvalue);
1787
1788 return 22;
1789}
1790
1791static int
1792init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1793{
1794 /*
1795 * INIT_ZM_INDEX_IO opcode: 0x62 ('b')
1796 *
1797 * offset (8 bit): opcode
1798 * offset + 1 (16 bit): CRTC port
1799 * offset + 3 (8 bit): CRTC index
1800 * offset + 4 (8 bit): data
1801 *
1802 * Write "data" to index "CRTC index" of "CRTC port"
1803 */
1804 uint16_t crtcport = ROM16(bios->data[offset + 1]);
1805 uint8_t crtcindex = bios->data[offset + 3];
1806 uint8_t data = bios->data[offset + 4];
1807
1808 if (!iexec->execute)
1809 return 5;
1810
1811 bios_idxprt_wr(bios, crtcport, crtcindex, data);
1812
1813 return 5;
1814}
1815
1816static inline void
1817bios_md32(struct nvbios *bios, uint32_t reg,
1818 uint32_t mask, uint32_t val)
1819{
1820 bios_wr32(bios, reg, (bios_rd32(bios, reg) & ~mask) | val);
1821}
1822
1823static uint32_t
1824peek_fb(struct drm_device *dev, struct io_mapping *fb,
1825 uint32_t off)
1826{
1827 uint32_t val = 0;
1828
1829 if (off < pci_resource_len(dev->pdev, 1)) {
1830 uint8_t __iomem *p =
1831 io_mapping_map_atomic_wc(fb, off & PAGE_MASK);
1832
1833 val = ioread32(p + (off & ~PAGE_MASK));
1834
1835 io_mapping_unmap_atomic(p);
1836 }
1837
1838 return val;
1839}
1840
1841static void
1842poke_fb(struct drm_device *dev, struct io_mapping *fb,
1843 uint32_t off, uint32_t val)
1844{
1845 if (off < pci_resource_len(dev->pdev, 1)) {
1846 uint8_t __iomem *p =
1847 io_mapping_map_atomic_wc(fb, off & PAGE_MASK);
1848
1849 iowrite32(val, p + (off & ~PAGE_MASK));
1850 wmb();
1851
1852 io_mapping_unmap_atomic(p);
1853 }
1854}
1855
1856static inline bool
1857read_back_fb(struct drm_device *dev, struct io_mapping *fb,
1858 uint32_t off, uint32_t val)
1859{
1860 poke_fb(dev, fb, off, val);
1861 return val == peek_fb(dev, fb, off);
1862}
1863
1864static int
1865nv04_init_compute_mem(struct nvbios *bios)
1866{
1867 struct drm_device *dev = bios->dev;
1868 uint32_t patt = 0xdeadbeef;
1869 struct io_mapping *fb;
1870 int i;
1871
1872 /* Map the framebuffer aperture */
1873 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
1874 pci_resource_len(dev->pdev, 1));
1875 if (!fb)
1876 return -ENOMEM;
1877
1878 /* Sequencer and refresh off */
1879 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20);
1880 bios_md32(bios, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF);
1881
1882 bios_md32(bios, NV04_PFB_BOOT_0, ~0,
1883 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB |
1884 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
1885 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT);
1886
1887 for (i = 0; i < 4; i++)
1888 poke_fb(dev, fb, 4 * i, patt);
1889
1890 poke_fb(dev, fb, 0x400000, patt + 1);
1891
1892 if (peek_fb(dev, fb, 0) == patt + 1) {
1893 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
1894 NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT);
1895 bios_md32(bios, NV04_PFB_DEBUG_0,
1896 NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
1897
1898 for (i = 0; i < 4; i++)
1899 poke_fb(dev, fb, 4 * i, patt);
1900
1901 if ((peek_fb(dev, fb, 0xc) & 0xffff) != (patt & 0xffff))
1902 bios_md32(bios, NV04_PFB_BOOT_0,
1903 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
1904 NV04_PFB_BOOT_0_RAM_AMOUNT,
1905 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
1906
1907 } else if ((peek_fb(dev, fb, 0xc) & 0xffff0000) !=
1908 (patt & 0xffff0000)) {
1909 bios_md32(bios, NV04_PFB_BOOT_0,
1910 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
1911 NV04_PFB_BOOT_0_RAM_AMOUNT,
1912 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
1913
1914 } else if (peek_fb(dev, fb, 0) != patt) {
1915 if (read_back_fb(dev, fb, 0x800000, patt))
1916 bios_md32(bios, NV04_PFB_BOOT_0,
1917 NV04_PFB_BOOT_0_RAM_AMOUNT,
1918 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
1919 else
1920 bios_md32(bios, NV04_PFB_BOOT_0,
1921 NV04_PFB_BOOT_0_RAM_AMOUNT,
1922 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
1923
1924 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
1925 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT);
1926
1927 } else if (!read_back_fb(dev, fb, 0x800000, patt)) {
1928 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
1929 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
1930
1931 }
1932
1933 /* Refresh on, sequencer on */
1934 bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
1935 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20);
1936
1937 io_mapping_free(fb);
1938 return 0;
1939}
1940
1941static const uint8_t *
1942nv05_memory_config(struct nvbios *bios)
1943{
1944 /* Defaults for BIOSes lacking a memory config table */
1945 static const uint8_t default_config_tab[][2] = {
1946 { 0x24, 0x00 },
1947 { 0x28, 0x00 },
1948 { 0x24, 0x01 },
1949 { 0x1f, 0x00 },
1950 { 0x0f, 0x00 },
1951 { 0x17, 0x00 },
1952 { 0x06, 0x00 },
1953 { 0x00, 0x00 }
1954 };
1955 int i = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) &
1956 NV_PEXTDEV_BOOT_0_RAMCFG) >> 2;
1957
1958 if (bios->legacy.mem_init_tbl_ptr)
1959 return &bios->data[bios->legacy.mem_init_tbl_ptr + 2 * i];
1960 else
1961 return default_config_tab[i];
1962}
1963
1964static int
1965nv05_init_compute_mem(struct nvbios *bios)
1966{
1967 struct drm_device *dev = bios->dev;
1968 const uint8_t *ramcfg = nv05_memory_config(bios);
1969 uint32_t patt = 0xdeadbeef;
1970 struct io_mapping *fb;
1971 int i, v;
1972
1973 /* Map the framebuffer aperture */
1974 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
1975 pci_resource_len(dev->pdev, 1));
1976 if (!fb)
1977 return -ENOMEM;
1978
1979 /* Sequencer off */
1980 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20);
1981
1982 if (bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_UMA_ENABLE)
1983 goto out;
1984
1985 bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
1986
1987 /* If present load the hardcoded scrambling table */
1988 if (bios->legacy.mem_init_tbl_ptr) {
1989 uint32_t *scramble_tab = (uint32_t *)&bios->data[
1990 bios->legacy.mem_init_tbl_ptr + 0x10];
1991
1992 for (i = 0; i < 8; i++)
1993 bios_wr32(bios, NV04_PFB_SCRAMBLE(i),
1994 ROM32(scramble_tab[i]));
1995 }
1996
1997 /* Set memory type/width/length defaults depending on the straps */
1998 bios_md32(bios, NV04_PFB_BOOT_0, 0x3f, ramcfg[0]);
1999
2000 if (ramcfg[1] & 0x80)
2001 bios_md32(bios, NV04_PFB_CFG0, 0, NV04_PFB_CFG0_SCRAMBLE);
2002
2003 bios_md32(bios, NV04_PFB_CFG1, 0x700001, (ramcfg[1] & 1) << 20);
2004 bios_md32(bios, NV04_PFB_CFG1, 0, 1);
2005
2006 /* Probe memory bus width */
2007 for (i = 0; i < 4; i++)
2008 poke_fb(dev, fb, 4 * i, patt);
2009
2010 if (peek_fb(dev, fb, 0xc) != patt)
2011 bios_md32(bios, NV04_PFB_BOOT_0,
2012 NV04_PFB_BOOT_0_RAM_WIDTH_128, 0);
2013
2014 /* Probe memory length */
2015 v = bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_RAM_AMOUNT;
2016
2017 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_32MB &&
2018 (!read_back_fb(dev, fb, 0x1000000, ++patt) ||
2019 !read_back_fb(dev, fb, 0, ++patt)))
2020 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2021 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB);
2022
2023 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_16MB &&
2024 !read_back_fb(dev, fb, 0x800000, ++patt))
2025 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2026 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2027
2028 if (!read_back_fb(dev, fb, 0x400000, ++patt))
2029 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2030 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
2031
2032out:
2033 /* Sequencer on */
2034 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20);
2035
2036 io_mapping_free(fb);
2037 return 0;
2038}
2039
2040static int
2041nv10_init_compute_mem(struct nvbios *bios)
2042{
2043 struct drm_device *dev = bios->dev;
2044 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2045 const int mem_width[] = { 0x10, 0x00, 0x20 };
2046 const int mem_width_count = (dev_priv->chipset >= 0x17 ? 3 : 2);
2047 uint32_t patt = 0xdeadbeef;
2048 struct io_mapping *fb;
2049 int i, j, k;
2050
2051 /* Map the framebuffer aperture */
2052 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2053 pci_resource_len(dev->pdev, 1));
2054 if (!fb)
2055 return -ENOMEM;
2056
2057 bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
2058
2059 /* Probe memory bus width */
2060 for (i = 0; i < mem_width_count; i++) {
2061 bios_md32(bios, NV04_PFB_CFG0, 0x30, mem_width[i]);
2062
2063 for (j = 0; j < 4; j++) {
2064 for (k = 0; k < 4; k++)
2065 poke_fb(dev, fb, 0x1c, 0);
2066
2067 poke_fb(dev, fb, 0x1c, patt);
2068 poke_fb(dev, fb, 0x3c, 0);
2069
2070 if (peek_fb(dev, fb, 0x1c) == patt)
2071 goto mem_width_found;
2072 }
2073 }
2074
2075mem_width_found:
2076 patt <<= 1;
2077
2078 /* Probe amount of installed memory */
2079 for (i = 0; i < 4; i++) {
2080 int off = bios_rd32(bios, NV04_PFB_FIFO_DATA) - 0x100000;
2081
2082 poke_fb(dev, fb, off, patt);
2083 poke_fb(dev, fb, 0, 0);
2084
2085 peek_fb(dev, fb, 0);
2086 peek_fb(dev, fb, 0);
2087 peek_fb(dev, fb, 0);
2088 peek_fb(dev, fb, 0);
2089
2090 if (peek_fb(dev, fb, off) == patt)
2091 goto amount_found;
2092 }
2093
2094 /* IC missing - disable the upper half memory space. */
2095 bios_md32(bios, NV04_PFB_CFG0, 0x1000, 0);
2096
2097amount_found:
2098 io_mapping_free(fb);
2099 return 0;
2100}
2101
2102static int
2103nv20_init_compute_mem(struct nvbios *bios)
2104{
2105 struct drm_device *dev = bios->dev;
2106 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2107 uint32_t mask = (dev_priv->chipset >= 0x25 ? 0x300 : 0x900);
2108 uint32_t amount, off;
2109 struct io_mapping *fb;
2110
2111 /* Map the framebuffer aperture */
2112 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2113 pci_resource_len(dev->pdev, 1));
2114 if (!fb)
2115 return -ENOMEM;
2116
2117 bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
2118
2119 /* Allow full addressing */
2120 bios_md32(bios, NV04_PFB_CFG0, 0, mask);
2121
2122 amount = bios_rd32(bios, NV04_PFB_FIFO_DATA);
2123 for (off = amount; off > 0x2000000; off -= 0x2000000)
2124 poke_fb(dev, fb, off - 4, off);
2125
2126 amount = bios_rd32(bios, NV04_PFB_FIFO_DATA);
2127 if (amount != peek_fb(dev, fb, amount - 4))
2128 /* IC missing - disable the upper half memory space. */
2129 bios_md32(bios, NV04_PFB_CFG0, mask, 0);
2130
2131 io_mapping_free(fb);
2132 return 0;
2133}
2134
2135static int
2136init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2137{
2138 /*
2139 * INIT_COMPUTE_MEM opcode: 0x63 ('c')
2140 *
2141 * offset (8 bit): opcode
2142 *
2143 * This opcode is meant to set the PFB memory config registers
2144 * appropriately so that we can correctly calculate how much VRAM it
2145 * has (on nv10 and better chipsets the amount of installed VRAM is
2146 * subsequently reported in NV_PFB_CSTATUS (0x10020C)).
2147 *
2148 * The implementation of this opcode in general consists of several
2149 * parts:
2150 *
2151 * 1) Determination of memory type and density. Only necessary for
2152 * really old chipsets, the memory type reported by the strap bits
2153 * (0x101000) is assumed to be accurate on nv05 and newer.
2154 *
2155 * 2) Determination of the memory bus width. Usually done by a cunning
2156 * combination of writes to offsets 0x1c and 0x3c in the fb, and
2157 * seeing whether the written values are read back correctly.
2158 *
2159 * Only necessary on nv0x-nv1x and nv34, on the other cards we can
2160 * trust the straps.
2161 *
2162 * 3) Determination of how many of the card's RAM pads have ICs
2163 * attached, usually done by a cunning combination of writes to an
2164 * offset slightly less than the maximum memory reported by
2165 * NV_PFB_CSTATUS, then seeing if the test pattern can be read back.
2166 *
2167 * This appears to be a NOP on IGPs and NV4x or newer chipsets, both io
2168 * logs of the VBIOS and kmmio traces of the binary driver POSTing the
2169 * card show nothing being done for this opcode. Why is it still listed
2170 * in the table?!
2171 */
2172
2173 /* no iexec->execute check by design */
2174
2175 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2176 int ret;
2177
2178 if (dev_priv->chipset >= 0x40 ||
2179 dev_priv->chipset == 0x1a ||
2180 dev_priv->chipset == 0x1f)
2181 ret = 0;
2182 else if (dev_priv->chipset >= 0x20 &&
2183 dev_priv->chipset != 0x34)
2184 ret = nv20_init_compute_mem(bios);
2185 else if (dev_priv->chipset >= 0x10)
2186 ret = nv10_init_compute_mem(bios);
2187 else if (dev_priv->chipset >= 0x5)
2188 ret = nv05_init_compute_mem(bios);
2189 else
2190 ret = nv04_init_compute_mem(bios);
2191
2192 if (ret)
2193 return ret;
2194
2195 return 1;
2196}
2197
2198static int
2199init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2200{
2201 /*
2202 * INIT_RESET opcode: 0x65 ('e')
2203 *
2204 * offset (8 bit): opcode
2205 * offset + 1 (32 bit): register
2206 * offset + 5 (32 bit): value1
2207 * offset + 9 (32 bit): value2
2208 *
2209 * Assign "value1" to "register", then assign "value2" to "register"
2210 */
2211
2212 uint32_t reg = ROM32(bios->data[offset + 1]);
2213 uint32_t value1 = ROM32(bios->data[offset + 5]);
2214 uint32_t value2 = ROM32(bios->data[offset + 9]);
2215 uint32_t pci_nv_19, pci_nv_20;
2216
2217 /* no iexec->execute check by design */
2218
2219 pci_nv_19 = bios_rd32(bios, NV_PBUS_PCI_NV_19);
2220 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19 & ~0xf00);
2221
2222 bios_wr32(bios, reg, value1);
2223
2224 udelay(10);
2225
2226 bios_wr32(bios, reg, value2);
2227 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19);
2228
2229 pci_nv_20 = bios_rd32(bios, NV_PBUS_PCI_NV_20);
2230 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */
2231 bios_wr32(bios, NV_PBUS_PCI_NV_20, pci_nv_20);
2232
2233 return 13;
2234}
2235
2236static int
2237init_configure_mem(struct nvbios *bios, uint16_t offset,
2238 struct init_exec *iexec)
2239{
2240 /*
2241 * INIT_CONFIGURE_MEM opcode: 0x66 ('f')
2242 *
2243 * offset (8 bit): opcode
2244 *
2245 * Equivalent to INIT_DONE on bios version 3 or greater.
2246 * For early bios versions, sets up the memory registers, using values
2247 * taken from the memory init table
2248 */
2249
2250 /* no iexec->execute check by design */
2251
2252 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2253 uint16_t seqtbloffs = bios->legacy.sdr_seq_tbl_ptr, meminitdata = meminitoffs + 6;
2254 uint32_t reg, data;
2255
2256 if (bios->major_version > 2)
2257 return 0;
2258
2259 bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd(
2260 bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20);
2261
2262 if (bios->data[meminitoffs] & 1)
2263 seqtbloffs = bios->legacy.ddr_seq_tbl_ptr;
2264
2265 for (reg = ROM32(bios->data[seqtbloffs]);
2266 reg != 0xffffffff;
2267 reg = ROM32(bios->data[seqtbloffs += 4])) {
2268
2269 switch (reg) {
2270 case NV04_PFB_PRE:
2271 data = NV04_PFB_PRE_CMD_PRECHARGE;
2272 break;
2273 case NV04_PFB_PAD:
2274 data = NV04_PFB_PAD_CKE_NORMAL;
2275 break;
2276 case NV04_PFB_REF:
2277 data = NV04_PFB_REF_CMD_REFRESH;
2278 break;
2279 default:
2280 data = ROM32(bios->data[meminitdata]);
2281 meminitdata += 4;
2282 if (data == 0xffffffff)
2283 continue;
2284 }
2285
2286 bios_wr32(bios, reg, data);
2287 }
2288
2289 return 1;
2290}
2291
2292static int
2293init_configure_clk(struct nvbios *bios, uint16_t offset,
2294 struct init_exec *iexec)
2295{
2296 /*
2297 * INIT_CONFIGURE_CLK opcode: 0x67 ('g')
2298 *
2299 * offset (8 bit): opcode
2300 *
2301 * Equivalent to INIT_DONE on bios version 3 or greater.
2302 * For early bios versions, sets up the NVClk and MClk PLLs, using
2303 * values taken from the memory init table
2304 */
2305
2306 /* no iexec->execute check by design */
2307
2308 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2309 int clock;
2310
2311 if (bios->major_version > 2)
2312 return 0;
2313
2314 clock = ROM16(bios->data[meminitoffs + 4]) * 10;
2315 setPLL(bios->dev, NV_PRAMDAC_NVPLL_COEFF, clock);
2316
2317 clock = ROM16(bios->data[meminitoffs + 2]) * 10;
2318 if (bios->data[meminitoffs] & 1) /* DDR */
2319 clock *= 2;
2320 setPLL(bios->dev, NV_PRAMDAC_MPLL_COEFF, clock);
2321
2322 return 1;
2323}
2324
2325static int
2326init_configure_preinit(struct nvbios *bios, uint16_t offset,
2327 struct init_exec *iexec)
2328{
2329 /*
2330 * INIT_CONFIGURE_PREINIT opcode: 0x68 ('h')
2331 *
2332 * offset (8 bit): opcode
2333 *
2334 * Equivalent to INIT_DONE on bios version 3 or greater.
2335 * For early bios versions, does early init, loading ram and crystal
2336 * configuration from straps into CR3C
2337 */
2338
2339 /* no iexec->execute check by design */
2340
2341 uint32_t straps = bios_rd32(bios, NV_PEXTDEV_BOOT_0);
2342 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & 0x40) >> 6;
2343
2344 if (bios->major_version > 2)
2345 return 0;
2346
2347 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR,
2348 NV_CIO_CRE_SCRATCH4__INDEX, cr3c);
2349
2350 return 1;
2351}
2352
2353static int
2354init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2355{
2356 /*
2357 * INIT_IO opcode: 0x69 ('i')
2358 *
2359 * offset (8 bit): opcode
2360 * offset + 1 (16 bit): CRTC port
2361 * offset + 3 (8 bit): mask
2362 * offset + 4 (8 bit): data
2363 *
2364 * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port"
2365 */
2366
2367 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2368 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2369 uint8_t mask = bios->data[offset + 3];
2370 uint8_t data = bios->data[offset + 4];
2371
2372 if (!iexec->execute)
2373 return 5;
2374
2375 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n",
2376 offset, crtcport, mask, data);
2377
2378 /*
2379 * I have no idea what this does, but NVIDIA do this magic sequence
2380 * in the places where this INIT_IO happens..
2381 */
2382 if (dev_priv->card_type >= NV_50 && crtcport == 0x3c3 && data == 1) {
2383 int i;
2384
2385 bios_wr32(bios, 0x614100, (bios_rd32(
2386 bios, 0x614100) & 0x0fffffff) | 0x00800000);
2387
2388 bios_wr32(bios, 0x00e18c, bios_rd32(
2389 bios, 0x00e18c) | 0x00020000);
2390
2391 bios_wr32(bios, 0x614900, (bios_rd32(
2392 bios, 0x614900) & 0x0fffffff) | 0x00800000);
2393
2394 bios_wr32(bios, 0x000200, bios_rd32(
2395 bios, 0x000200) & ~0x40000000);
2396
2397 mdelay(10);
2398
2399 bios_wr32(bios, 0x00e18c, bios_rd32(
2400 bios, 0x00e18c) & ~0x00020000);
2401
2402 bios_wr32(bios, 0x000200, bios_rd32(
2403 bios, 0x000200) | 0x40000000);
2404
2405 bios_wr32(bios, 0x614100, 0x00800018);
2406 bios_wr32(bios, 0x614900, 0x00800018);
2407
2408 mdelay(10);
2409
2410 bios_wr32(bios, 0x614100, 0x10000018);
2411 bios_wr32(bios, 0x614900, 0x10000018);
2412
2413 for (i = 0; i < 3; i++)
2414 bios_wr32(bios, 0x614280 + (i*0x800), bios_rd32(
2415 bios, 0x614280 + (i*0x800)) & 0xf0f0f0f0);
2416
2417 for (i = 0; i < 2; i++)
2418 bios_wr32(bios, 0x614300 + (i*0x800), bios_rd32(
2419 bios, 0x614300 + (i*0x800)) & 0xfffff0f0);
2420
2421 for (i = 0; i < 3; i++)
2422 bios_wr32(bios, 0x614380 + (i*0x800), bios_rd32(
2423 bios, 0x614380 + (i*0x800)) & 0xfffff0f0);
2424
2425 for (i = 0; i < 2; i++)
2426 bios_wr32(bios, 0x614200 + (i*0x800), bios_rd32(
2427 bios, 0x614200 + (i*0x800)) & 0xfffffff0);
2428
2429 for (i = 0; i < 2; i++)
2430 bios_wr32(bios, 0x614108 + (i*0x800), bios_rd32(
2431 bios, 0x614108 + (i*0x800)) & 0x0fffffff);
2432 return 5;
2433 }
2434
2435 bios_port_wr(bios, crtcport, (bios_port_rd(bios, crtcport) & mask) |
2436 data);
2437 return 5;
2438}
2439
2440static int
2441init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2442{
2443 /*
2444 * INIT_SUB opcode: 0x6B ('k')
2445 *
2446 * offset (8 bit): opcode
2447 * offset + 1 (8 bit): script number
2448 *
2449 * Execute script number "script number", as a subroutine
2450 */
2451
2452 uint8_t sub = bios->data[offset + 1];
2453
2454 if (!iexec->execute)
2455 return 2;
2456
2457 BIOSLOG(bios, "0x%04X: Calling script %d\n", offset, sub);
2458
2459 parse_init_table(bios,
2460 ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]),
2461 iexec);
2462
2463 BIOSLOG(bios, "0x%04X: End of script %d\n", offset, sub);
2464
2465 return 2;
2466}
2467
2468static int
2469init_ram_condition(struct nvbios *bios, uint16_t offset,
2470 struct init_exec *iexec)
2471{
2472 /*
2473 * INIT_RAM_CONDITION opcode: 0x6D ('m')
2474 *
2475 * offset (8 bit): opcode
2476 * offset + 1 (8 bit): mask
2477 * offset + 2 (8 bit): cmpval
2478 *
2479 * Test if (NV04_PFB_BOOT_0 & "mask") equals "cmpval".
2480 * If condition not met skip subsequent opcodes until condition is
2481 * inverted (INIT_NOT), or we hit INIT_RESUME
2482 */
2483
2484 uint8_t mask = bios->data[offset + 1];
2485 uint8_t cmpval = bios->data[offset + 2];
2486 uint8_t data;
2487
2488 if (!iexec->execute)
2489 return 3;
2490
2491 data = bios_rd32(bios, NV04_PFB_BOOT_0) & mask;
2492
2493 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
2494 offset, data, cmpval);
2495
2496 if (data == cmpval)
2497 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2498 else {
2499 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2500 iexec->execute = false;
2501 }
2502
2503 return 3;
2504}
2505
2506static int
2507init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2508{
2509 /*
2510 * INIT_NV_REG opcode: 0x6E ('n')
2511 *
2512 * offset (8 bit): opcode
2513 * offset + 1 (32 bit): register
2514 * offset + 5 (32 bit): mask
2515 * offset + 9 (32 bit): data
2516 *
2517 * Assign ((REGVAL("register") & "mask") | "data") to "register"
2518 */
2519
2520 uint32_t reg = ROM32(bios->data[offset + 1]);
2521 uint32_t mask = ROM32(bios->data[offset + 5]);
2522 uint32_t data = ROM32(bios->data[offset + 9]);
2523
2524 if (!iexec->execute)
2525 return 13;
2526
2527 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n",
2528 offset, reg, mask, data);
2529
2530 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | data);
2531
2532 return 13;
2533}
2534
2535static int
2536init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2537{
2538 /*
2539 * INIT_MACRO opcode: 0x6F ('o')
2540 *
2541 * offset (8 bit): opcode
2542 * offset + 1 (8 bit): macro number
2543 *
2544 * Look up macro index "macro number" in the macro index table.
2545 * The macro index table entry has 1 byte for the index in the macro
2546 * table, and 1 byte for the number of times to repeat the macro.
2547 * The macro table entry has 4 bytes for the register address and
2548 * 4 bytes for the value to write to that register
2549 */
2550
2551 uint8_t macro_index_tbl_idx = bios->data[offset + 1];
2552 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE);
2553 uint8_t macro_tbl_idx = bios->data[tmp];
2554 uint8_t count = bios->data[tmp + 1];
2555 uint32_t reg, data;
2556 int i;
2557
2558 if (!iexec->execute)
2559 return 2;
2560
2561 BIOSLOG(bios, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, "
2562 "Count: 0x%02X\n",
2563 offset, macro_index_tbl_idx, macro_tbl_idx, count);
2564
2565 for (i = 0; i < count; i++) {
2566 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE;
2567
2568 reg = ROM32(bios->data[macroentryptr]);
2569 data = ROM32(bios->data[macroentryptr + 4]);
2570
2571 bios_wr32(bios, reg, data);
2572 }
2573
2574 return 2;
2575}
2576
2577static int
2578init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2579{
2580 /*
2581 * INIT_DONE opcode: 0x71 ('q')
2582 *
2583 * offset (8 bit): opcode
2584 *
2585 * End the current script
2586 */
2587
2588 /* mild retval abuse to stop parsing this table */
2589 return 0;
2590}
2591
2592static int
2593init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2594{
2595 /*
2596 * INIT_RESUME opcode: 0x72 ('r')
2597 *
2598 * offset (8 bit): opcode
2599 *
2600 * End the current execute / no-execute condition
2601 */
2602
2603 if (iexec->execute)
2604 return 1;
2605
2606 iexec->execute = true;
2607 BIOSLOG(bios, "0x%04X: ---- Executing following commands ----\n", offset);
2608
2609 return 1;
2610}
2611
2612static int
2613init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2614{
2615 /*
2616 * INIT_TIME opcode: 0x74 ('t')
2617 *
2618 * offset (8 bit): opcode
2619 * offset + 1 (16 bit): time
2620 *
2621 * Sleep for "time" microseconds.
2622 */
2623
2624 unsigned time = ROM16(bios->data[offset + 1]);
2625
2626 if (!iexec->execute)
2627 return 3;
2628
2629 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X microseconds\n",
2630 offset, time);
2631
2632 if (time < 1000)
2633 udelay(time);
2634 else
2635 mdelay((time + 900) / 1000);
2636
2637 return 3;
2638}
2639
2640static int
2641init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2642{
2643 /*
2644 * INIT_CONDITION opcode: 0x75 ('u')
2645 *
2646 * offset (8 bit): opcode
2647 * offset + 1 (8 bit): condition number
2648 *
2649 * Check condition "condition number" in the condition table.
2650 * If condition not met skip subsequent opcodes until condition is
2651 * inverted (INIT_NOT), or we hit INIT_RESUME
2652 */
2653
2654 uint8_t cond = bios->data[offset + 1];
2655
2656 if (!iexec->execute)
2657 return 2;
2658
2659 BIOSLOG(bios, "0x%04X: Condition: 0x%02X\n", offset, cond);
2660
2661 if (bios_condition_met(bios, offset, cond))
2662 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2663 else {
2664 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2665 iexec->execute = false;
2666 }
2667
2668 return 2;
2669}
2670
2671static int
2672init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2673{
2674 /*
2675 * INIT_IO_CONDITION opcode: 0x76
2676 *
2677 * offset (8 bit): opcode
2678 * offset + 1 (8 bit): condition number
2679 *
2680 * Check condition "condition number" in the io condition table.
2681 * If condition not met skip subsequent opcodes until condition is
2682 * inverted (INIT_NOT), or we hit INIT_RESUME
2683 */
2684
2685 uint8_t cond = bios->data[offset + 1];
2686
2687 if (!iexec->execute)
2688 return 2;
2689
2690 BIOSLOG(bios, "0x%04X: IO condition: 0x%02X\n", offset, cond);
2691
2692 if (io_condition_met(bios, offset, cond))
2693 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2694 else {
2695 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2696 iexec->execute = false;
2697 }
2698
2699 return 2;
2700}
2701
2702static int
2703init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2704{
2705 /*
2706 * INIT_INDEX_IO opcode: 0x78 ('x')
2707 *
2708 * offset (8 bit): opcode
2709 * offset + 1 (16 bit): CRTC port
2710 * offset + 3 (8 bit): CRTC index
2711 * offset + 4 (8 bit): mask
2712 * offset + 5 (8 bit): data
2713 *
2714 * Read value at index "CRTC index" on "CRTC port", AND with "mask",
2715 * OR with "data", write-back
2716 */
2717
2718 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2719 uint8_t crtcindex = bios->data[offset + 3];
2720 uint8_t mask = bios->data[offset + 4];
2721 uint8_t data = bios->data[offset + 5];
2722 uint8_t value;
2723
2724 if (!iexec->execute)
2725 return 6;
2726
2727 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
2728 "Data: 0x%02X\n",
2729 offset, crtcport, crtcindex, mask, data);
2730
2731 value = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) | data;
2732 bios_idxprt_wr(bios, crtcport, crtcindex, value);
2733
2734 return 6;
2735}
2736
2737static int
2738init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2739{
2740 /*
2741 * INIT_PLL opcode: 0x79 ('y')
2742 *
2743 * offset (8 bit): opcode
2744 * offset + 1 (32 bit): register
2745 * offset + 5 (16 bit): freq
2746 *
2747 * Set PLL register "register" to coefficients for frequency (10kHz)
2748 * "freq"
2749 */
2750
2751 uint32_t reg = ROM32(bios->data[offset + 1]);
2752 uint16_t freq = ROM16(bios->data[offset + 5]);
2753
2754 if (!iexec->execute)
2755 return 7;
2756
2757 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset, reg, freq);
2758
2759 setPLL(bios->dev, reg, freq * 10);
2760
2761 return 7;
2762}
2763
2764static int
2765init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2766{
2767 /*
2768 * INIT_ZM_REG opcode: 0x7A ('z')
2769 *
2770 * offset (8 bit): opcode
2771 * offset + 1 (32 bit): register
2772 * offset + 5 (32 bit): value
2773 *
2774 * Assign "value" to "register"
2775 */
2776
2777 uint32_t reg = ROM32(bios->data[offset + 1]);
2778 uint32_t value = ROM32(bios->data[offset + 5]);
2779
2780 if (!iexec->execute)
2781 return 9;
2782
2783 if (reg == 0x000200)
2784 value |= 1;
2785
2786 bios_wr32(bios, reg, value);
2787
2788 return 9;
2789}
2790
2791static int
2792init_ram_restrict_pll(struct nvbios *bios, uint16_t offset,
2793 struct init_exec *iexec)
2794{
2795 /*
2796 * INIT_RAM_RESTRICT_PLL opcode: 0x87 ('')
2797 *
2798 * offset (8 bit): opcode
2799 * offset + 1 (8 bit): PLL type
2800 * offset + 2 (32 bit): frequency 0
2801 *
2802 * Uses the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
2803 * ram_restrict_table_ptr. The value read from there is used to select
2804 * a frequency from the table starting at 'frequency 0' to be
2805 * programmed into the PLL corresponding to 'type'.
2806 *
2807 * The PLL limits table on cards using this opcode has a mapping of
2808 * 'type' to the relevant registers.
2809 */
2810
2811 struct drm_device *dev = bios->dev;
2812 uint32_t strap = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) & 0x0000003c) >> 2;
2813 uint8_t index = bios->data[bios->ram_restrict_tbl_ptr + strap];
2814 uint8_t type = bios->data[offset + 1];
2815 uint32_t freq = ROM32(bios->data[offset + 2 + (index * 4)]);
2816 uint8_t *pll_limits = &bios->data[bios->pll_limit_tbl_ptr], *entry;
2817 int len = 2 + bios->ram_restrict_group_count * 4;
2818 int i;
2819
2820 if (!iexec->execute)
2821 return len;
2822
2823 if (!bios->pll_limit_tbl_ptr || (pll_limits[0] & 0xf0) != 0x30) {
2824 NV_ERROR(dev, "PLL limits table not version 3.x\n");
2825 return len; /* deliberate, allow default clocks to remain */
2826 }
2827
2828 entry = pll_limits + pll_limits[1];
2829 for (i = 0; i < pll_limits[3]; i++, entry += pll_limits[2]) {
2830 if (entry[0] == type) {
2831 uint32_t reg = ROM32(entry[3]);
2832
2833 BIOSLOG(bios, "0x%04X: "
2834 "Type %02x Reg 0x%08x Freq %dKHz\n",
2835 offset, type, reg, freq);
2836
2837 setPLL(bios->dev, reg, freq);
2838 return len;
2839 }
2840 }
2841
2842 NV_ERROR(dev, "PLL type 0x%02x not found in PLL limits table", type);
2843 return len;
2844}
2845
2846static int
2847init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2848{
2849 /*
2850 * INIT_8C opcode: 0x8C ('')
2851 *
2852 * NOP so far....
2853 *
2854 */
2855
2856 return 1;
2857}
2858
2859static int
2860init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2861{
2862 /*
2863 * INIT_8D opcode: 0x8D ('')
2864 *
2865 * NOP so far....
2866 *
2867 */
2868
2869 return 1;
2870}
2871
2872static int
2873init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2874{
2875 /*
2876 * INIT_GPIO opcode: 0x8E ('')
2877 *
2878 * offset (8 bit): opcode
2879 *
2880 * Loop over all entries in the DCB GPIO table, and initialise
2881 * each GPIO according to various values listed in each entry
2882 */
2883
2884 if (iexec->execute && bios->execute)
2885 nouveau_gpio_reset(bios->dev);
2886
2887 return 1;
2888}
2889
2890static int
2891init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset,
2892 struct init_exec *iexec)
2893{
2894 /*
2895 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('')
2896 *
2897 * offset (8 bit): opcode
2898 * offset + 1 (32 bit): reg
2899 * offset + 5 (8 bit): regincrement
2900 * offset + 6 (8 bit): count
2901 * offset + 7 (32 bit): value 1,1
2902 * ...
2903 *
2904 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
2905 * ram_restrict_table_ptr. The value read from here is 'n', and
2906 * "value 1,n" gets written to "reg". This repeats "count" times and on
2907 * each iteration 'm', "reg" increases by "regincrement" and
2908 * "value m,n" is used. The extent of n is limited by a number read
2909 * from the 'M' BIT table, herein called "blocklen"
2910 */
2911
2912 uint32_t reg = ROM32(bios->data[offset + 1]);
2913 uint8_t regincrement = bios->data[offset + 5];
2914 uint8_t count = bios->data[offset + 6];
2915 uint32_t strap_ramcfg, data;
2916 /* previously set by 'M' BIT table */
2917 uint16_t blocklen = bios->ram_restrict_group_count * 4;
2918 int len = 7 + count * blocklen;
2919 uint8_t index;
2920 int i;
2921
2922 /* critical! to know the length of the opcode */;
2923 if (!blocklen) {
2924 NV_ERROR(bios->dev,
2925 "0x%04X: Zero block length - has the M table "
2926 "been parsed?\n", offset);
2927 return -EINVAL;
2928 }
2929
2930 if (!iexec->execute)
2931 return len;
2932
2933 strap_ramcfg = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 2) & 0xf;
2934 index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg];
2935
2936 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, "
2937 "Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n",
2938 offset, reg, regincrement, count, strap_ramcfg, index);
2939
2940 for (i = 0; i < count; i++) {
2941 data = ROM32(bios->data[offset + 7 + index * 4 + blocklen * i]);
2942
2943 bios_wr32(bios, reg, data);
2944
2945 reg += regincrement;
2946 }
2947
2948 return len;
2949}
2950
2951static int
2952init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2953{
2954 /*
2955 * INIT_COPY_ZM_REG opcode: 0x90 ('')
2956 *
2957 * offset (8 bit): opcode
2958 * offset + 1 (32 bit): src reg
2959 * offset + 5 (32 bit): dst reg
2960 *
2961 * Put contents of "src reg" into "dst reg"
2962 */
2963
2964 uint32_t srcreg = ROM32(bios->data[offset + 1]);
2965 uint32_t dstreg = ROM32(bios->data[offset + 5]);
2966
2967 if (!iexec->execute)
2968 return 9;
2969
2970 bios_wr32(bios, dstreg, bios_rd32(bios, srcreg));
2971
2972 return 9;
2973}
2974
2975static int
2976init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset,
2977 struct init_exec *iexec)
2978{
2979 /*
2980 * INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('')
2981 *
2982 * offset (8 bit): opcode
2983 * offset + 1 (32 bit): dst reg
2984 * offset + 5 (8 bit): count
2985 * offset + 6 (32 bit): data 1
2986 * ...
2987 *
2988 * For each of "count" values write "data n" to "dst reg"
2989 */
2990
2991 uint32_t reg = ROM32(bios->data[offset + 1]);
2992 uint8_t count = bios->data[offset + 5];
2993 int len = 6 + count * 4;
2994 int i;
2995
2996 if (!iexec->execute)
2997 return len;
2998
2999 for (i = 0; i < count; i++) {
3000 uint32_t data = ROM32(bios->data[offset + 6 + 4 * i]);
3001 bios_wr32(bios, reg, data);
3002 }
3003
3004 return len;
3005}
3006
3007static int
3008init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3009{
3010 /*
3011 * INIT_RESERVED opcode: 0x92 ('')
3012 *
3013 * offset (8 bit): opcode
3014 *
3015 * Seemingly does nothing
3016 */
3017
3018 return 1;
3019}
3020
3021static int
3022init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3023{
3024 /*
3025 * INIT_96 opcode: 0x96 ('')
3026 *
3027 * offset (8 bit): opcode
3028 * offset + 1 (32 bit): sreg
3029 * offset + 5 (8 bit): sshift
3030 * offset + 6 (8 bit): smask
3031 * offset + 7 (8 bit): index
3032 * offset + 8 (32 bit): reg
3033 * offset + 12 (32 bit): mask
3034 * offset + 16 (8 bit): shift
3035 *
3036 */
3037
3038 uint16_t xlatptr = bios->init96_tbl_ptr + (bios->data[offset + 7] * 2);
3039 uint32_t reg = ROM32(bios->data[offset + 8]);
3040 uint32_t mask = ROM32(bios->data[offset + 12]);
3041 uint32_t val;
3042
3043 val = bios_rd32(bios, ROM32(bios->data[offset + 1]));
3044 if (bios->data[offset + 5] < 0x80)
3045 val >>= bios->data[offset + 5];
3046 else
3047 val <<= (0x100 - bios->data[offset + 5]);
3048 val &= bios->data[offset + 6];
3049
3050 val = bios->data[ROM16(bios->data[xlatptr]) + val];
3051 val <<= bios->data[offset + 16];
3052
3053 if (!iexec->execute)
3054 return 17;
3055
3056 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | val);
3057 return 17;
3058}
3059
3060static int
3061init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3062{
3063 /*
3064 * INIT_97 opcode: 0x97 ('')
3065 *
3066 * offset (8 bit): opcode
3067 * offset + 1 (32 bit): register
3068 * offset + 5 (32 bit): mask
3069 * offset + 9 (32 bit): value
3070 *
3071 * Adds "value" to "register" preserving the fields specified
3072 * by "mask"
3073 */
3074
3075 uint32_t reg = ROM32(bios->data[offset + 1]);
3076 uint32_t mask = ROM32(bios->data[offset + 5]);
3077 uint32_t add = ROM32(bios->data[offset + 9]);
3078 uint32_t val;
3079
3080 val = bios_rd32(bios, reg);
3081 val = (val & mask) | ((val + add) & ~mask);
3082
3083 if (!iexec->execute)
3084 return 13;
3085
3086 bios_wr32(bios, reg, val);
3087 return 13;
3088}
3089
3090static int
3091init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3092{
3093 /*
3094 * INIT_AUXCH opcode: 0x98 ('')
3095 *
3096 * offset (8 bit): opcode
3097 * offset + 1 (32 bit): address
3098 * offset + 5 (8 bit): count
3099 * offset + 6 (8 bit): mask 0
3100 * offset + 7 (8 bit): data 0
3101 * ...
3102 *
3103 */
3104
3105 struct drm_device *dev = bios->dev;
3106 struct nouveau_i2c_port *auxch;
3107 uint32_t addr = ROM32(bios->data[offset + 1]);
3108 uint8_t count = bios->data[offset + 5];
3109 int len = 6 + count * 2;
3110 int ret, i;
3111
3112 if (!bios->display.output) {
3113 NV_ERROR(dev, "INIT_AUXCH: no active output\n");
3114 return len;
3115 }
3116
3117 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
3118 if (!auxch) {
3119 NV_ERROR(dev, "INIT_AUXCH: couldn't get auxch %d\n",
3120 bios->display.output->i2c_index);
3121 return len;
3122 }
3123
3124 if (!iexec->execute)
3125 return len;
3126
3127 offset += 6;
3128 for (i = 0; i < count; i++, offset += 2) {
3129 uint8_t data;
3130
3131 ret = auxch_rd(dev, auxch, addr, &data, 1);
3132 if (ret) {
3133 NV_ERROR(dev, "INIT_AUXCH: rd auxch fail %d\n", ret);
3134 return len;
3135 }
3136
3137 data &= bios->data[offset + 0];
3138 data |= bios->data[offset + 1];
3139
3140 ret = auxch_wr(dev, auxch, addr, &data, 1);
3141 if (ret) {
3142 NV_ERROR(dev, "INIT_AUXCH: wr auxch fail %d\n", ret);
3143 return len;
3144 }
3145 }
3146
3147 return len;
3148}
3149
3150static int
3151init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3152{
3153 /*
3154 * INIT_ZM_AUXCH opcode: 0x99 ('')
3155 *
3156 * offset (8 bit): opcode
3157 * offset + 1 (32 bit): address
3158 * offset + 5 (8 bit): count
3159 * offset + 6 (8 bit): data 0
3160 * ...
3161 *
3162 */
3163
3164 struct drm_device *dev = bios->dev;
3165 struct nouveau_i2c_port *auxch;
3166 uint32_t addr = ROM32(bios->data[offset + 1]);
3167 uint8_t count = bios->data[offset + 5];
3168 int len = 6 + count;
3169 int ret, i;
3170
3171 if (!bios->display.output) {
3172 NV_ERROR(dev, "INIT_ZM_AUXCH: no active output\n");
3173 return len;
3174 }
3175
3176 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
3177 if (!auxch) {
3178 NV_ERROR(dev, "INIT_ZM_AUXCH: couldn't get auxch %d\n",
3179 bios->display.output->i2c_index);
3180 return len;
3181 }
3182
3183 if (!iexec->execute)
3184 return len;
3185
3186 offset += 6;
3187 for (i = 0; i < count; i++, offset++) {
3188 ret = auxch_wr(dev, auxch, addr, &bios->data[offset], 1);
3189 if (ret) {
3190 NV_ERROR(dev, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret);
3191 return len;
3192 }
3193 }
3194
3195 return len;
3196}
3197
3198static int
3199init_i2c_long_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3200{
3201 /*
3202 * INIT_I2C_LONG_IF opcode: 0x9A ('')
3203 *
3204 * offset (8 bit): opcode
3205 * offset + 1 (8 bit): DCB I2C table entry index
3206 * offset + 2 (8 bit): I2C slave address
3207 * offset + 3 (16 bit): I2C register
3208 * offset + 5 (8 bit): mask
3209 * offset + 6 (8 bit): data
3210 *
3211 * Read the register given by "I2C register" on the device addressed
3212 * by "I2C slave address" on the I2C bus given by "DCB I2C table
3213 * entry index". Compare the result AND "mask" to "data".
3214 * If they're not equal, skip subsequent opcodes until condition is
3215 * inverted (INIT_NOT), or we hit INIT_RESUME
3216 */
3217
3218 uint8_t i2c_index = bios->data[offset + 1];
3219 uint8_t i2c_address = bios->data[offset + 2] >> 1;
3220 uint8_t reglo = bios->data[offset + 3];
3221 uint8_t reghi = bios->data[offset + 4];
3222 uint8_t mask = bios->data[offset + 5];
3223 uint8_t data = bios->data[offset + 6];
3224 struct nouveau_i2c_port *chan;
3225 uint8_t buf0[2] = { reghi, reglo };
3226 uint8_t buf1[1];
3227 struct i2c_msg msg[2] = {
3228 { i2c_address, 0, 1, buf0 },
3229 { i2c_address, I2C_M_RD, 1, buf1 },
3230 };
3231 int ret;
3232
3233 /* no execute check by design */
3234
3235 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X\n",
3236 offset, i2c_index, i2c_address);
3237
3238 chan = init_i2c_device_find(bios->dev, i2c_index);
3239 if (!chan)
3240 return -ENODEV;
3241
3242
3243 ret = i2c_transfer(nouveau_i2c_adapter(chan), msg, 2);
3244 if (ret < 0) {
3245 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X:0x%02X, Value: [no device], "
3246 "Mask: 0x%02X, Data: 0x%02X\n",
3247 offset, reghi, reglo, mask, data);
3248 iexec->execute = 0;
3249 return 7;
3250 }
3251
3252 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X:0x%02X, Value: 0x%02X, "
3253 "Mask: 0x%02X, Data: 0x%02X\n",
3254 offset, reghi, reglo, buf1[0], mask, data);
3255
3256 iexec->execute = ((buf1[0] & mask) == data);
3257
3258 return 7;
3259}
3260
3261static struct init_tbl_entry itbl_entry[] = {
3262 /* command name , id , length , offset , mult , command handler */
3263 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */
3264 { "INIT_IO_RESTRICT_PROG" , 0x32, init_io_restrict_prog },
3265 { "INIT_REPEAT" , 0x33, init_repeat },
3266 { "INIT_IO_RESTRICT_PLL" , 0x34, init_io_restrict_pll },
3267 { "INIT_END_REPEAT" , 0x36, init_end_repeat },
3268 { "INIT_COPY" , 0x37, init_copy },
3269 { "INIT_NOT" , 0x38, init_not },
3270 { "INIT_IO_FLAG_CONDITION" , 0x39, init_io_flag_condition },
3271 { "INIT_DP_CONDITION" , 0x3A, init_dp_condition },
3272 { "INIT_OP_3B" , 0x3B, init_op_3b },
3273 { "INIT_OP_3C" , 0x3C, init_op_3c },
3274 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, init_idx_addr_latched },
3275 { "INIT_IO_RESTRICT_PLL2" , 0x4A, init_io_restrict_pll2 },
3276 { "INIT_PLL2" , 0x4B, init_pll2 },
3277 { "INIT_I2C_BYTE" , 0x4C, init_i2c_byte },
3278 { "INIT_ZM_I2C_BYTE" , 0x4D, init_zm_i2c_byte },
3279 { "INIT_ZM_I2C" , 0x4E, init_zm_i2c },
3280 { "INIT_TMDS" , 0x4F, init_tmds },
3281 { "INIT_ZM_TMDS_GROUP" , 0x50, init_zm_tmds_group },
3282 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, init_cr_idx_adr_latch },
3283 { "INIT_CR" , 0x52, init_cr },
3284 { "INIT_ZM_CR" , 0x53, init_zm_cr },
3285 { "INIT_ZM_CR_GROUP" , 0x54, init_zm_cr_group },
3286 { "INIT_CONDITION_TIME" , 0x56, init_condition_time },
3287 { "INIT_LTIME" , 0x57, init_ltime },
3288 { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence },
3289 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */
3290 { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct },
3291 { "INIT_JUMP" , 0x5C, init_jump },
3292 { "INIT_I2C_IF" , 0x5E, init_i2c_if },
3293 { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg },
3294 { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io },
3295 { "INIT_COMPUTE_MEM" , 0x63, init_compute_mem },
3296 { "INIT_RESET" , 0x65, init_reset },
3297 { "INIT_CONFIGURE_MEM" , 0x66, init_configure_mem },
3298 { "INIT_CONFIGURE_CLK" , 0x67, init_configure_clk },
3299 { "INIT_CONFIGURE_PREINIT" , 0x68, init_configure_preinit },
3300 { "INIT_IO" , 0x69, init_io },
3301 { "INIT_SUB" , 0x6B, init_sub },
3302 { "INIT_RAM_CONDITION" , 0x6D, init_ram_condition },
3303 { "INIT_NV_REG" , 0x6E, init_nv_reg },
3304 { "INIT_MACRO" , 0x6F, init_macro },
3305 { "INIT_DONE" , 0x71, init_done },
3306 { "INIT_RESUME" , 0x72, init_resume },
3307 /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */
3308 { "INIT_TIME" , 0x74, init_time },
3309 { "INIT_CONDITION" , 0x75, init_condition },
3310 { "INIT_IO_CONDITION" , 0x76, init_io_condition },
3311 { "INIT_INDEX_IO" , 0x78, init_index_io },
3312 { "INIT_PLL" , 0x79, init_pll },
3313 { "INIT_ZM_REG" , 0x7A, init_zm_reg },
3314 { "INIT_RAM_RESTRICT_PLL" , 0x87, init_ram_restrict_pll },
3315 { "INIT_8C" , 0x8C, init_8c },
3316 { "INIT_8D" , 0x8D, init_8d },
3317 { "INIT_GPIO" , 0x8E, init_gpio },
3318 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, init_ram_restrict_zm_reg_group },
3319 { "INIT_COPY_ZM_REG" , 0x90, init_copy_zm_reg },
3320 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, init_zm_reg_group_addr_latched },
3321 { "INIT_RESERVED" , 0x92, init_reserved },
3322 { "INIT_96" , 0x96, init_96 },
3323 { "INIT_97" , 0x97, init_97 },
3324 { "INIT_AUXCH" , 0x98, init_auxch },
3325 { "INIT_ZM_AUXCH" , 0x99, init_zm_auxch },
3326 { "INIT_I2C_LONG_IF" , 0x9A, init_i2c_long_if },
3327 { NULL , 0 , NULL }
3328};
3329
3330#define MAX_TABLE_OPS 1000
3331
3332static int
3333parse_init_table(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3334{
3335 /*
3336 * Parses all commands in an init table.
3337 *
3338 * We start out executing all commands found in the init table. Some
3339 * opcodes may change the status of iexec->execute to SKIP, which will
3340 * cause the following opcodes to perform no operation until the value
3341 * is changed back to EXECUTE.
3342 */
3343
3344 int count = 0, i, ret;
3345 uint8_t id;
3346
3347 /* catch NULL script pointers */
3348 if (offset == 0)
3349 return 0;
3350
3351 /*
3352 * Loop until INIT_DONE causes us to break out of the loop
3353 * (or until offset > bios length just in case... )
3354 * (and no more than MAX_TABLE_OPS iterations, just in case... )
3355 */
3356 while ((offset < bios->length) && (count++ < MAX_TABLE_OPS)) {
3357 id = bios->data[offset];
3358
3359 /* Find matching id in itbl_entry */
3360 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++)
3361 ;
3362
3363 if (!itbl_entry[i].name) {
3364 NV_ERROR(bios->dev,
3365 "0x%04X: Init table command not found: "
3366 "0x%02X\n", offset, id);
3367 return -ENOENT;
3368 }
3369
3370 BIOSLOG(bios, "0x%04X: [ (0x%02X) - %s ]\n", offset,
3371 itbl_entry[i].id, itbl_entry[i].name);
3372
3373 /* execute eventual command handler */
3374 ret = (*itbl_entry[i].handler)(bios, offset, iexec);
3375 if (ret < 0) {
3376 NV_ERROR(bios->dev, "0x%04X: Failed parsing init "
3377 "table opcode: %s %d\n", offset,
3378 itbl_entry[i].name, ret);
3379 }
3380
3381 if (ret <= 0)
3382 break;
3383
3384 /*
3385 * Add the offset of the current command including all data
3386 * of that command. The offset will then be pointing on the
3387 * next op code.
3388 */
3389 offset += ret;
3390 }
3391
3392 if (offset >= bios->length)
3393 NV_WARN(bios->dev,
3394 "Offset 0x%04X greater than known bios image length. "
3395 "Corrupt image?\n", offset);
3396 if (count >= MAX_TABLE_OPS)
3397 NV_WARN(bios->dev,
3398 "More than %d opcodes to a table is unlikely, "
3399 "is the bios image corrupt?\n", MAX_TABLE_OPS);
3400
3401 return 0;
3402}
3403
3404static void
3405parse_init_tables(struct nvbios *bios)
3406{
3407 /* Loops and calls parse_init_table() for each present table. */
3408
3409 int i = 0;
3410 uint16_t table;
3411 struct init_exec iexec = {true, false};
3412
3413 if (bios->old_style_init) {
3414 if (bios->init_script_tbls_ptr)
3415 parse_init_table(bios, bios->init_script_tbls_ptr, &iexec);
3416 if (bios->extra_init_script_tbl_ptr)
3417 parse_init_table(bios, bios->extra_init_script_tbl_ptr, &iexec);
3418
3419 return;
3420 }
3421
3422 while ((table = ROM16(bios->data[bios->init_script_tbls_ptr + i]))) {
3423 NV_INFO(bios->dev,
3424 "Parsing VBIOS init table %d at offset 0x%04X\n",
3425 i / 2, table);
3426 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", table);
3427
3428 parse_init_table(bios, table, &iexec);
3429 i += 2;
3430 }
3431}
3432
3433static uint16_t clkcmptable(struct nvbios *bios, uint16_t clktable, int pxclk) 67static uint16_t clkcmptable(struct nvbios *bios, uint16_t clktable, int pxclk)
3434{ 68{
3435 int compare_record_len, i = 0; 69 int compare_record_len, i = 0;
@@ -3458,28 +92,22 @@ static uint16_t clkcmptable(struct nvbios *bios, uint16_t clktable, int pxclk)
3458 92
3459static void 93static void
3460run_digital_op_script(struct drm_device *dev, uint16_t scriptptr, 94run_digital_op_script(struct drm_device *dev, uint16_t scriptptr,
3461 struct dcb_entry *dcbent, int head, bool dl) 95 struct dcb_output *dcbent, int head, bool dl)
3462{ 96{
3463 struct drm_nouveau_private *dev_priv = dev->dev_private;
3464 struct nvbios *bios = &dev_priv->vbios;
3465 struct init_exec iexec = {true, false};
3466
3467 NV_TRACE(dev, "0x%04X: Parsing digital output script table\n", 97 NV_TRACE(dev, "0x%04X: Parsing digital output script table\n",
3468 scriptptr); 98 scriptptr);
3469 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_44, 99 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_44, head ? NV_CIO_CRE_44_HEADB :
3470 head ? NV_CIO_CRE_44_HEADB : NV_CIO_CRE_44_HEADA); 100 NV_CIO_CRE_44_HEADA);
3471 /* note: if dcb entries have been merged, index may be misleading */ 101 nouveau_bios_run_init_table(dev, scriptptr, dcbent, head);
3472 NVWriteVgaCrtc5758(dev, head, 0, dcbent->index);
3473 parse_init_table(bios, scriptptr, &iexec);
3474 102
3475 nv04_dfp_bind_head(dev, dcbent, head, dl); 103 nv04_dfp_bind_head(dev, dcbent, head, dl);
3476} 104}
3477 105
3478static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script) 106static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_output *dcbent, int head, enum LVDS_script script)
3479{ 107{
3480 struct drm_nouveau_private *dev_priv = dev->dev_private; 108 struct drm_nouveau_private *dev_priv = dev->dev_private;
3481 struct nvbios *bios = &dev_priv->vbios; 109 struct nvbios *bios = &dev_priv->vbios;
3482 uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & OUTPUT_C ? 1 : 0); 110 uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & DCB_OUTPUT_C ? 1 : 0);
3483 uint16_t scriptofs = ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]); 111 uint16_t scriptofs = ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]);
3484 112
3485 if (!bios->fp.xlated_entry || !sub || !scriptofs) 113 if (!bios->fp.xlated_entry || !sub || !scriptofs)
@@ -3502,7 +130,7 @@ static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_entr
3502 return 0; 130 return 0;
3503} 131}
3504 132
3505static int run_lvds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk) 133static int run_lvds_table(struct drm_device *dev, struct dcb_output *dcbent, int head, enum LVDS_script script, int pxclk)
3506{ 134{
3507 /* 135 /*
3508 * The BIT LVDS table's header has the information to setup the 136 * The BIT LVDS table's header has the information to setup the
@@ -3575,7 +203,7 @@ static int run_lvds_table(struct drm_device *dev, struct dcb_entry *dcbent, int
3575 return 0; 203 return 0;
3576} 204}
3577 205
3578int call_lvds_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk) 206int call_lvds_script(struct drm_device *dev, struct dcb_output *dcbent, int head, enum LVDS_script script, int pxclk)
3579{ 207{
3580 /* 208 /*
3581 * LVDS operations are multiplexed in an effort to present a single API 209 * LVDS operations are multiplexed in an effort to present a single API
@@ -3606,7 +234,7 @@ int call_lvds_script(struct drm_device *dev, struct dcb_entry *dcbent, int head,
3606 NV_TRACE(dev, "Calling LVDS script %d:\n", script); 234 NV_TRACE(dev, "Calling LVDS script %d:\n", script);
3607 235
3608 /* don't let script change pll->head binding */ 236 /* don't let script change pll->head binding */
3609 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000; 237 sel_clk_binding = nv_rd32(dev, NV_PRAMDAC_SEL_CLK) & 0x50000;
3610 238
3611 if (lvds_ver < 0x30) 239 if (lvds_ver < 0x30)
3612 ret = call_lvds_manufacturer_script(dev, dcbent, head, script); 240 ret = call_lvds_manufacturer_script(dev, dcbent, head, script);
@@ -3700,9 +328,9 @@ get_fp_strap(struct drm_device *dev, struct nvbios *bios)
3700 return NVReadVgaCrtc5758(dev, 0, 0xf) & 0xf; 328 return NVReadVgaCrtc5758(dev, 0, 0xf) & 0xf;
3701 329
3702 if (dev_priv->card_type >= NV_50) 330 if (dev_priv->card_type >= NV_50)
3703 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 24) & 0xf; 331 return (nv_rd32(dev, NV_PEXTDEV_BOOT_0) >> 24) & 0xf;
3704 else 332 else
3705 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 16) & 0xf; 333 return (nv_rd32(dev, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;
3706} 334}
3707 335
3708static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios) 336static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios)
@@ -3994,7 +622,7 @@ int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, b
3994 * This function returns true if a particular DCB entry matches. 622 * This function returns true if a particular DCB entry matches.
3995 */ 623 */
3996bool 624bool
3997bios_encoder_match(struct dcb_entry *dcb, u32 hash) 625bios_encoder_match(struct dcb_output *dcb, u32 hash)
3998{ 626{
3999 if ((hash & 0x000000f0) != (dcb->location << 4)) 627 if ((hash & 0x000000f0) != (dcb->location << 4))
4000 return false; 628 return false;
@@ -4004,9 +632,9 @@ bios_encoder_match(struct dcb_entry *dcb, u32 hash)
4004 return false; 632 return false;
4005 633
4006 switch (dcb->type) { 634 switch (dcb->type) {
4007 case OUTPUT_TMDS: 635 case DCB_OUTPUT_TMDS:
4008 case OUTPUT_LVDS: 636 case DCB_OUTPUT_LVDS:
4009 case OUTPUT_DP: 637 case DCB_OUTPUT_DP:
4010 if (hash & 0x00c00000) { 638 if (hash & 0x00c00000) {
4011 if (!(hash & (dcb->sorconf.link << 22))) 639 if (!(hash & (dcb->sorconf.link << 22)))
4012 return false; 640 return false;
@@ -4018,7 +646,7 @@ bios_encoder_match(struct dcb_entry *dcb, u32 hash)
4018 646
4019int 647int
4020nouveau_bios_run_display_table(struct drm_device *dev, u16 type, int pclk, 648nouveau_bios_run_display_table(struct drm_device *dev, u16 type, int pclk,
4021 struct dcb_entry *dcbent, int crtc) 649 struct dcb_output *dcbent, int crtc)
4022{ 650{
4023 /* 651 /*
4024 * The display script table is located by the BIT 'U' table. 652 * The display script table is located by the BIT 'U' table.
@@ -4188,7 +816,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, u16 type, int pclk,
4188} 816}
4189 817
4190 818
4191int run_tmds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, int pxclk) 819int run_tmds_table(struct drm_device *dev, struct dcb_output *dcbent, int head, int pxclk)
4192{ 820{
4193 /* 821 /*
4194 * the pxclk parameter is in kHz 822 * the pxclk parameter is in kHz
@@ -4233,7 +861,7 @@ int run_tmds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, i
4233 } 861 }
4234 862
4235 /* don't let script change pll->head binding */ 863 /* don't let script change pll->head binding */
4236 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000; 864 sel_clk_binding = nv_rd32(dev, NV_PRAMDAC_SEL_CLK) & 0x50000;
4237 run_digital_op_script(dev, scriptptr, dcbent, head, pxclk >= 165000); 865 run_digital_op_script(dev, scriptptr, dcbent, head, pxclk >= 165000);
4238 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000; 866 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
4239 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding); 867 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
@@ -4967,9 +1595,9 @@ olddcb_outp_foreach(struct drm_device *dev, void *data,
4967 if (ROM32(outp[0]) == 0xffffffff) 1595 if (ROM32(outp[0]) == 0xffffffff)
4968 break; /* seen on an NV17 with DCB v2.0 */ 1596 break; /* seen on an NV17 with DCB v2.0 */
4969 1597
4970 if ((outp[0] & 0x0f) == OUTPUT_UNUSED) 1598 if ((outp[0] & 0x0f) == DCB_OUTPUT_UNUSED)
4971 continue; 1599 continue;
4972 if ((outp[0] & 0x0f) == OUTPUT_EOL) 1600 if ((outp[0] & 0x0f) == DCB_OUTPUT_EOL)
4973 break; 1601 break;
4974 1602
4975 ret = exec(dev, data, idx, outp); 1603 ret = exec(dev, data, idx, outp);
@@ -4981,7 +1609,7 @@ olddcb_outp_foreach(struct drm_device *dev, void *data,
4981} 1609}
4982 1610
4983u8 * 1611u8 *
4984dcb_conntab(struct drm_device *dev) 1612olddcb_conntab(struct drm_device *dev)
4985{ 1613{
4986 u8 *dcb = olddcb_table(dev); 1614 u8 *dcb = olddcb_table(dev);
4987 if (dcb && dcb[0] >= 0x30 && dcb[1] >= 0x16) { 1615 if (dcb && dcb[0] >= 0x30 && dcb[1] >= 0x16) {
@@ -4993,19 +1621,19 @@ dcb_conntab(struct drm_device *dev)
4993} 1621}
4994 1622
4995u8 * 1623u8 *
4996dcb_conn(struct drm_device *dev, u8 idx) 1624olddcb_conn(struct drm_device *dev, u8 idx)
4997{ 1625{
4998 u8 *conntab = dcb_conntab(dev); 1626 u8 *conntab = olddcb_conntab(dev);
4999 if (conntab && idx < conntab[2]) 1627 if (conntab && idx < conntab[2])
5000 return conntab + conntab[1] + (idx * conntab[3]); 1628 return conntab + conntab[1] + (idx * conntab[3]);
5001 return NULL; 1629 return NULL;
5002} 1630}
5003 1631
5004static struct dcb_entry *new_dcb_entry(struct dcb_table *dcb) 1632static struct dcb_output *new_dcb_entry(struct dcb_table *dcb)
5005{ 1633{
5006 struct dcb_entry *entry = &dcb->entry[dcb->entries]; 1634 struct dcb_output *entry = &dcb->entry[dcb->entries];
5007 1635
5008 memset(entry, 0, sizeof(struct dcb_entry)); 1636 memset(entry, 0, sizeof(struct dcb_output));
5009 entry->index = dcb->entries++; 1637 entry->index = dcb->entries++;
5010 1638
5011 return entry; 1639 return entry;
@@ -5014,19 +1642,19 @@ static struct dcb_entry *new_dcb_entry(struct dcb_table *dcb)
5014static void fabricate_dcb_output(struct dcb_table *dcb, int type, int i2c, 1642static void fabricate_dcb_output(struct dcb_table *dcb, int type, int i2c,
5015 int heads, int or) 1643 int heads, int or)
5016{ 1644{
5017 struct dcb_entry *entry = new_dcb_entry(dcb); 1645 struct dcb_output *entry = new_dcb_entry(dcb);
5018 1646
5019 entry->type = type; 1647 entry->type = type;
5020 entry->i2c_index = i2c; 1648 entry->i2c_index = i2c;
5021 entry->heads = heads; 1649 entry->heads = heads;
5022 if (type != OUTPUT_ANALOG) 1650 if (type != DCB_OUTPUT_ANALOG)
5023 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */ 1651 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */
5024 entry->or = or; 1652 entry->or = or;
5025} 1653}
5026 1654
5027static bool 1655static bool
5028parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb, 1656parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb,
5029 uint32_t conn, uint32_t conf, struct dcb_entry *entry) 1657 uint32_t conn, uint32_t conf, struct dcb_output *entry)
5030{ 1658{
5031 entry->type = conn & 0xf; 1659 entry->type = conn & 0xf;
5032 entry->i2c_index = (conn >> 4) & 0xf; 1660 entry->i2c_index = (conn >> 4) & 0xf;
@@ -5037,7 +1665,7 @@ parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb,
5037 entry->or = (conn >> 24) & 0xf; 1665 entry->or = (conn >> 24) & 0xf;
5038 1666
5039 switch (entry->type) { 1667 switch (entry->type) {
5040 case OUTPUT_ANALOG: 1668 case DCB_OUTPUT_ANALOG:
5041 /* 1669 /*
5042 * Although the rest of a CRT conf dword is usually 1670 * Although the rest of a CRT conf dword is usually
5043 * zeros, mac biosen have stuff there so we must mask 1671 * zeros, mac biosen have stuff there so we must mask
@@ -5046,7 +1674,7 @@ parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb,
5046 (conf & 0xffff) * 10 : 1674 (conf & 0xffff) * 10 :
5047 (conf & 0xff) * 10000; 1675 (conf & 0xff) * 10000;
5048 break; 1676 break;
5049 case OUTPUT_LVDS: 1677 case DCB_OUTPUT_LVDS:
5050 { 1678 {
5051 uint32_t mask; 1679 uint32_t mask;
5052 if (conf & 0x1) 1680 if (conf & 0x1)
@@ -5086,7 +1714,7 @@ parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb,
5086 } 1714 }
5087 break; 1715 break;
5088 } 1716 }
5089 case OUTPUT_TV: 1717 case DCB_OUTPUT_TV:
5090 { 1718 {
5091 if (dcb->version >= 0x30) 1719 if (dcb->version >= 0x30)
5092 entry->tvconf.has_component_output = conf & (0x8 << 4); 1720 entry->tvconf.has_component_output = conf & (0x8 << 4);
@@ -5095,7 +1723,7 @@ parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb,
5095 1723
5096 break; 1724 break;
5097 } 1725 }
5098 case OUTPUT_DP: 1726 case DCB_OUTPUT_DP:
5099 entry->dpconf.sor.link = (conf & 0x00000030) >> 4; 1727 entry->dpconf.sor.link = (conf & 0x00000030) >> 4;
5100 switch ((conf & 0x00e00000) >> 21) { 1728 switch ((conf & 0x00e00000) >> 21) {
5101 case 0: 1729 case 0:
@@ -5117,7 +1745,7 @@ parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb,
5117 break; 1745 break;
5118 } 1746 }
5119 break; 1747 break;
5120 case OUTPUT_TMDS: 1748 case DCB_OUTPUT_TMDS:
5121 if (dcb->version >= 0x40) 1749 if (dcb->version >= 0x40)
5122 entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4; 1750 entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4;
5123 else if (dcb->version >= 0x30) 1751 else if (dcb->version >= 0x30)
@@ -5126,7 +1754,7 @@ parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb,
5126 entry->tmdsconf.slave_addr = (conf & 0x00000070) >> 4; 1754 entry->tmdsconf.slave_addr = (conf & 0x00000070) >> 4;
5127 1755
5128 break; 1756 break;
5129 case OUTPUT_EOL: 1757 case DCB_OUTPUT_EOL:
5130 /* weird g80 mobile type that "nv" treats as a terminator */ 1758 /* weird g80 mobile type that "nv" treats as a terminator */
5131 dcb->entries--; 1759 dcb->entries--;
5132 return false; 1760 return false;
@@ -5153,24 +1781,24 @@ parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb,
5153 1781
5154static bool 1782static bool
5155parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb, 1783parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb,
5156 uint32_t conn, uint32_t conf, struct dcb_entry *entry) 1784 uint32_t conn, uint32_t conf, struct dcb_output *entry)
5157{ 1785{
5158 switch (conn & 0x0000000f) { 1786 switch (conn & 0x0000000f) {
5159 case 0: 1787 case 0:
5160 entry->type = OUTPUT_ANALOG; 1788 entry->type = DCB_OUTPUT_ANALOG;
5161 break; 1789 break;
5162 case 1: 1790 case 1:
5163 entry->type = OUTPUT_TV; 1791 entry->type = DCB_OUTPUT_TV;
5164 break; 1792 break;
5165 case 2: 1793 case 2:
5166 case 4: 1794 case 4:
5167 if (conn & 0x10) 1795 if (conn & 0x10)
5168 entry->type = OUTPUT_LVDS; 1796 entry->type = DCB_OUTPUT_LVDS;
5169 else 1797 else
5170 entry->type = OUTPUT_TMDS; 1798 entry->type = DCB_OUTPUT_TMDS;
5171 break; 1799 break;
5172 case 3: 1800 case 3:
5173 entry->type = OUTPUT_LVDS; 1801 entry->type = DCB_OUTPUT_LVDS;
5174 break; 1802 break;
5175 default: 1803 default:
5176 NV_ERROR(dev, "Unknown DCB type %d\n", conn & 0x0000000f); 1804 NV_ERROR(dev, "Unknown DCB type %d\n", conn & 0x0000000f);
@@ -5185,13 +1813,13 @@ parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb,
5185 entry->duallink_possible = false; 1813 entry->duallink_possible = false;
5186 1814
5187 switch (entry->type) { 1815 switch (entry->type) {
5188 case OUTPUT_ANALOG: 1816 case DCB_OUTPUT_ANALOG:
5189 entry->crtconf.maxfreq = (conf & 0xffff) * 10; 1817 entry->crtconf.maxfreq = (conf & 0xffff) * 10;
5190 break; 1818 break;
5191 case OUTPUT_TV: 1819 case DCB_OUTPUT_TV:
5192 entry->tvconf.has_component_output = false; 1820 entry->tvconf.has_component_output = false;
5193 break; 1821 break;
5194 case OUTPUT_LVDS: 1822 case DCB_OUTPUT_LVDS:
5195 if ((conn & 0x00003f00) >> 8 != 0x10) 1823 if ((conn & 0x00003f00) >> 8 != 0x10)
5196 entry->lvdsconf.use_straps_for_mode = true; 1824 entry->lvdsconf.use_straps_for_mode = true;
5197 entry->lvdsconf.use_power_scripts = true; 1825 entry->lvdsconf.use_power_scripts = true;
@@ -5215,11 +1843,11 @@ void merge_like_dcb_entries(struct drm_device *dev, struct dcb_table *dcb)
5215 int i, newentries = 0; 1843 int i, newentries = 0;
5216 1844
5217 for (i = 0; i < dcb->entries; i++) { 1845 for (i = 0; i < dcb->entries; i++) {
5218 struct dcb_entry *ient = &dcb->entry[i]; 1846 struct dcb_output *ient = &dcb->entry[i];
5219 int j; 1847 int j;
5220 1848
5221 for (j = i + 1; j < dcb->entries; j++) { 1849 for (j = i + 1; j < dcb->entries; j++) {
5222 struct dcb_entry *jent = &dcb->entry[j]; 1850 struct dcb_output *jent = &dcb->entry[j];
5223 1851
5224 if (jent->type == 100) /* already merged entry */ 1852 if (jent->type == 100) /* already merged entry */
5225 continue; 1853 continue;
@@ -5282,7 +1910,7 @@ apply_dcb_encoder_quirks(struct drm_device *dev, int idx, u32 *conn, u32 *conf)
5282 */ 1910 */
5283 if (nv_match_device(dev, 0x0201, 0x1462, 0x8851)) { 1911 if (nv_match_device(dev, 0x0201, 0x1462, 0x8851)) {
5284 if (*conn == 0xf2005014 && *conf == 0xffffffff) { 1912 if (*conn == 0xf2005014 && *conf == 0xffffffff) {
5285 fabricate_dcb_output(dcb, OUTPUT_TMDS, 1, 1, 1); 1913 fabricate_dcb_output(dcb, DCB_OUTPUT_TMDS, 1, 1, 1);
5286 return false; 1914 return false;
5287 } 1915 }
5288 } 1916 }
@@ -5368,24 +1996,24 @@ fabricate_dcb_encoder_table(struct drm_device *dev, struct nvbios *bios)
5368#ifdef __powerpc__ 1996#ifdef __powerpc__
5369 /* Apple iMac G4 NV17 */ 1997 /* Apple iMac G4 NV17 */
5370 if (of_machine_is_compatible("PowerMac4,5")) { 1998 if (of_machine_is_compatible("PowerMac4,5")) {
5371 fabricate_dcb_output(dcb, OUTPUT_TMDS, 0, all_heads, 1); 1999 fabricate_dcb_output(dcb, DCB_OUTPUT_TMDS, 0, all_heads, 1);
5372 fabricate_dcb_output(dcb, OUTPUT_ANALOG, 1, all_heads, 2); 2000 fabricate_dcb_output(dcb, DCB_OUTPUT_ANALOG, 1, all_heads, 2);
5373 return; 2001 return;
5374 } 2002 }
5375#endif 2003#endif
5376 2004
5377 /* Make up some sane defaults */ 2005 /* Make up some sane defaults */
5378 fabricate_dcb_output(dcb, OUTPUT_ANALOG, 2006 fabricate_dcb_output(dcb, DCB_OUTPUT_ANALOG,
5379 bios->legacy.i2c_indices.crt, 1, 1); 2007 bios->legacy.i2c_indices.crt, 1, 1);
5380 2008
5381 if (nv04_tv_identify(dev, bios->legacy.i2c_indices.tv) >= 0) 2009 if (nv04_tv_identify(dev, bios->legacy.i2c_indices.tv) >= 0)
5382 fabricate_dcb_output(dcb, OUTPUT_TV, 2010 fabricate_dcb_output(dcb, DCB_OUTPUT_TV,
5383 bios->legacy.i2c_indices.tv, 2011 bios->legacy.i2c_indices.tv,
5384 all_heads, 0); 2012 all_heads, 0);
5385 2013
5386 else if (bios->tmds.output0_script_ptr || 2014 else if (bios->tmds.output0_script_ptr ||
5387 bios->tmds.output1_script_ptr) 2015 bios->tmds.output1_script_ptr)
5388 fabricate_dcb_output(dcb, OUTPUT_TMDS, 2016 fabricate_dcb_output(dcb, DCB_OUTPUT_TMDS,
5389 bios->legacy.i2c_indices.panel, 2017 bios->legacy.i2c_indices.panel,
5390 all_heads, 1); 2018 all_heads, 1);
5391} 2019}
@@ -5400,7 +2028,7 @@ parse_dcb_entry(struct drm_device *dev, void *data, int idx, u8 *outp)
5400 bool ret; 2028 bool ret;
5401 2029
5402 if (apply_dcb_encoder_quirks(dev, idx, &conn, &conf)) { 2030 if (apply_dcb_encoder_quirks(dev, idx, &conn, &conf)) {
5403 struct dcb_entry *entry = new_dcb_entry(dcb); 2031 struct dcb_output *entry = new_dcb_entry(dcb);
5404 2032
5405 NV_TRACEWARN(dev, "DCB outp %02d: %08x %08x\n", idx, conn, conf); 2033 NV_TRACEWARN(dev, "DCB outp %02d: %08x %08x\n", idx, conn, conf);
5406 2034
@@ -5415,7 +2043,7 @@ parse_dcb_entry(struct drm_device *dev, void *data, int idx, u8 *outp)
5415 * are cards with bogus values (nv31m in bug 23212), 2043 * are cards with bogus values (nv31m in bug 23212),
5416 * and it's otherwise useless. 2044 * and it's otherwise useless.
5417 */ 2045 */
5418 if (entry->type == OUTPUT_TV && 2046 if (entry->type == DCB_OUTPUT_TV &&
5419 entry->location == DCB_LOC_ON_CHIP) 2047 entry->location == DCB_LOC_ON_CHIP)
5420 entry->i2c_index = 0x0f; 2048 entry->i2c_index = 0x0f;
5421 } 2049 }
@@ -5463,7 +2091,7 @@ dcb_fake_connectors(struct nvbios *bios)
5463 * table - just in case it has random, rather than stub, entries. 2091 * table - just in case it has random, rather than stub, entries.
5464 */ 2092 */
5465 if (i > 1) { 2093 if (i > 1) {
5466 u8 *conntab = dcb_conntab(bios->dev); 2094 u8 *conntab = olddcb_conntab(bios->dev);
5467 if (conntab) 2095 if (conntab)
5468 conntab[0] = 0x00; 2096 conntab[0] = 0x00;
5469 } 2097 }
@@ -5504,10 +2132,10 @@ parse_dcb_table(struct drm_device *dev, struct nvbios *bios)
5504 2132
5505 /* dump connector table entries to log, if any exist */ 2133 /* dump connector table entries to log, if any exist */
5506 idx = -1; 2134 idx = -1;
5507 while ((conn = dcb_conn(dev, ++idx))) { 2135 while ((conn = olddcb_conn(dev, ++idx))) {
5508 if (conn[0] != 0xff) { 2136 if (conn[0] != 0xff) {
5509 NV_TRACE(dev, "DCB conn %02d: ", idx); 2137 NV_TRACE(dev, "DCB conn %02d: ", idx);
5510 if (dcb_conntab(dev)[3] < 4) 2138 if (olddcb_conntab(dev)[3] < 4)
5511 printk("%04x\n", ROM16(conn[0])); 2139 printk("%04x\n", ROM16(conn[0]));
5512 else 2140 else
5513 printk("%08x\n", ROM32(conn[0])); 2141 printk("%08x\n", ROM32(conn[0]));
@@ -5550,15 +2178,15 @@ static int load_nv17_hwsq_ucode_entry(struct drm_device *dev, struct nvbios *bio
5550 hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write; 2178 hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write;
5551 2179
5552 /* set sequencer control */ 2180 /* set sequencer control */
5553 bios_wr32(bios, 0x00001304, ROM32(bios->data[hwsq_entry_offset])); 2181 nv_wr32(dev, 0x00001304, ROM32(bios->data[hwsq_entry_offset]));
5554 bytes_to_write -= 4; 2182 bytes_to_write -= 4;
5555 2183
5556 /* write ucode */ 2184 /* write ucode */
5557 for (i = 0; i < bytes_to_write; i += 4) 2185 for (i = 0; i < bytes_to_write; i += 4)
5558 bios_wr32(bios, 0x00001400 + i, ROM32(bios->data[hwsq_entry_offset + i + 4])); 2186 nv_wr32(dev, 0x00001400 + i, ROM32(bios->data[hwsq_entry_offset + i + 4]));
5559 2187
5560 /* twiddle NV_PBUS_DEBUG_4 */ 2188 /* twiddle NV_PBUS_DEBUG_4 */
5561 bios_wr32(bios, NV_PBUS_DEBUG_4, bios_rd32(bios, NV_PBUS_DEBUG_4) | 0x18); 2189 nv_wr32(dev, NV_PBUS_DEBUG_4, nv_rd32(dev, NV_PBUS_DEBUG_4) | 0x18);
5562 2190
5563 return 0; 2191 return 0;
5564} 2192}
@@ -5618,32 +2246,6 @@ uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev)
5618 return bios->fp.edid = &bios->data[offset]; 2246 return bios->fp.edid = &bios->data[offset];
5619} 2247}
5620 2248
5621void
5622nouveau_bios_run_init_table(struct drm_device *dev, uint16_t table,
5623 struct dcb_entry *dcbent, int crtc)
5624{
5625 struct drm_nouveau_private *dev_priv = dev->dev_private;
5626 struct nvbios *bios = &dev_priv->vbios;
5627 struct init_exec iexec = { true, false };
5628
5629 spin_lock_bh(&bios->lock);
5630 bios->display.output = dcbent;
5631 bios->display.crtc = crtc;
5632 parse_init_table(bios, table, &iexec);
5633 bios->display.output = NULL;
5634 spin_unlock_bh(&bios->lock);
5635}
5636
5637void
5638nouveau_bios_init_exec(struct drm_device *dev, uint16_t table)
5639{
5640 struct drm_nouveau_private *dev_priv = dev->dev_private;
5641 struct nvbios *bios = &dev_priv->vbios;
5642 struct init_exec iexec = { true, false };
5643
5644 parse_init_table(bios, table, &iexec);
5645}
5646
5647static bool NVInitVBIOS(struct drm_device *dev) 2249static bool NVInitVBIOS(struct drm_device *dev)
5648{ 2250{
5649 struct drm_nouveau_private *dev_priv = dev->dev_private; 2251 struct drm_nouveau_private *dev_priv = dev->dev_private;
@@ -5704,23 +2306,8 @@ nouveau_run_vbios_init(struct drm_device *dev)
5704 bios->fp.lvds_init_run = false; 2306 bios->fp.lvds_init_run = false;
5705 } 2307 }
5706 2308
5707 parse_init_tables(bios);
5708
5709 /*
5710 * Runs some additional script seen on G8x VBIOSen. The VBIOS'
5711 * parser will run this right after the init tables, the binary
5712 * driver appears to run it at some point later.
5713 */
5714 if (bios->some_script_ptr) {
5715 struct init_exec iexec = {true, false};
5716
5717 NV_INFO(dev, "Parsing VBIOS init table at offset 0x%04X\n",
5718 bios->some_script_ptr);
5719 parse_init_table(bios, bios->some_script_ptr, &iexec);
5720 }
5721
5722 if (dev_priv->card_type >= NV_50) { 2309 if (dev_priv->card_type >= NV_50) {
5723 for (i = 0; i < bios->dcb.entries; i++) { 2310 for (i = 0; bios->execute && i < bios->dcb.entries; i++) {
5724 nouveau_bios_run_display_table(dev, 0, 0, 2311 nouveau_bios_run_display_table(dev, 0, 0,
5725 &bios->dcb.entry[i], -1); 2312 &bios->dcb.entry[i], -1);
5726 } 2313 }
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.h b/drivers/gpu/drm/nouveau/nouveau_bios.h
index e9bb14ec8c3..13a7e127080 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.h
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.h
@@ -72,66 +72,18 @@ enum dcb_connector_type {
72 DCB_CONNECTOR_NONE = 0xff 72 DCB_CONNECTOR_NONE = 0xff
73}; 73};
74 74
75enum dcb_type { 75#include <subdev/bios/dcb.h>
76 OUTPUT_ANALOG = 0,
77 OUTPUT_TV = 1,
78 OUTPUT_TMDS = 2,
79 OUTPUT_LVDS = 3,
80 OUTPUT_DP = 6,
81 OUTPUT_EOL = 14, /* DCB 4.0+, appears to be end-of-list */
82 OUTPUT_UNUSED = 15,
83 OUTPUT_ANY = -1
84};
85
86struct dcb_entry {
87 int index; /* may not be raw dcb index if merging has happened */
88 enum dcb_type type;
89 uint8_t i2c_index;
90 uint8_t heads;
91 uint8_t connector;
92 uint8_t bus;
93 uint8_t location;
94 uint8_t or;
95 bool duallink_possible;
96 union {
97 struct sor_conf {
98 int link;
99 } sorconf;
100 struct {
101 int maxfreq;
102 } crtconf;
103 struct {
104 struct sor_conf sor;
105 bool use_straps_for_mode;
106 bool use_acpi_for_edid;
107 bool use_power_scripts;
108 } lvdsconf;
109 struct {
110 bool has_component_output;
111 } tvconf;
112 struct {
113 struct sor_conf sor;
114 int link_nr;
115 int link_bw;
116 } dpconf;
117 struct {
118 struct sor_conf sor;
119 int slave_addr;
120 } tmdsconf;
121 };
122 bool i2c_upper_default;
123};
124 76
125struct dcb_table { 77struct dcb_table {
126 uint8_t version; 78 uint8_t version;
127 int entries; 79 int entries;
128 struct dcb_entry entry[DCB_MAX_NUM_ENTRIES]; 80 struct dcb_output entry[DCB_MAX_NUM_ENTRIES];
129}; 81};
130 82
131enum nouveau_or { 83enum nouveau_or {
132 OUTPUT_A = (1 << 0), 84 DCB_OUTPUT_A = (1 << 0),
133 OUTPUT_B = (1 << 1), 85 DCB_OUTPUT_B = (1 << 1),
134 OUTPUT_C = (1 << 2) 86 DCB_OUTPUT_C = (1 << 2)
135}; 87};
136 88
137enum LVDS_script { 89enum LVDS_script {
@@ -195,7 +147,7 @@ struct nvbios {
195 } state; 147 } state;
196 148
197 struct { 149 struct {
198 struct dcb_entry *output; 150 struct dcb_output *output;
199 int crtc; 151 int crtc;
200 uint16_t script_table_ptr; 152 uint16_t script_table_ptr;
201 } display; 153 } display;
@@ -244,7 +196,7 @@ void *olddcb_table(struct drm_device *);
244void *olddcb_outp(struct drm_device *, u8 idx); 196void *olddcb_outp(struct drm_device *, u8 idx);
245int olddcb_outp_foreach(struct drm_device *, void *data, 197int olddcb_outp_foreach(struct drm_device *, void *data,
246 int (*)(struct drm_device *, void *, int idx, u8 *outp)); 198 int (*)(struct drm_device *, void *, int idx, u8 *outp));
247u8 *dcb_conntab(struct drm_device *); 199u8 *olddcb_conntab(struct drm_device *);
248u8 *dcb_conn(struct drm_device *, u8 idx); 200u8 *olddcb_conn(struct drm_device *, u8 idx);
249 201
250#endif 202#endif
diff --git a/drivers/gpu/drm/nouveau/nouveau_compat.c b/drivers/gpu/drm/nouveau/nouveau_compat.c
index 30431c820bb..3fc7d5785c6 100644
--- a/drivers/gpu/drm/nouveau/nouveau_compat.c
+++ b/drivers/gpu/drm/nouveau/nouveau_compat.c
@@ -2,6 +2,8 @@
2#include "nouveau_compat.h" 2#include "nouveau_compat.h"
3 3
4#include <subdev/bios.h> 4#include <subdev/bios.h>
5#include <subdev/bios/dcb.h>
6#include <subdev/bios/init.h>
5#include <subdev/bios/pll.h> 7#include <subdev/bios/pll.h>
6#include <subdev/gpio.h> 8#include <subdev/gpio.h>
7#include <subdev/i2c.h> 9#include <subdev/i2c.h>
@@ -9,6 +11,18 @@
9 11
10void *nouveau_newpriv(struct drm_device *); 12void *nouveau_newpriv(struct drm_device *);
11 13
14int
15nvdrm_gart_init(struct drm_device *dev, u64 *base, u64 *size)
16{
17 struct nouveau_drm *drm = nouveau_newpriv(dev);
18 if (drm->agp.stat == ENABLED) {
19 *base = drm->agp.base;
20 *size = drm->agp.base;
21 return 0;
22 }
23 return -ENODEV;
24}
25
12u8 26u8
13_nv_rd08(struct drm_device *dev, u32 reg) 27_nv_rd08(struct drm_device *dev, u32 reg)
14{ 28{
@@ -255,3 +269,27 @@ nva3_calc_pll(struct drm_device *dev, struct nvbios_pll *info, u32 freq,
255 269
256 return nva3_pll_calc(clk, info, freq, N, fN, M, P); 270 return nva3_pll_calc(clk, info, freq, N, fN, M, P);
257} 271}
272
273void
274nouveau_bios_run_init_table(struct drm_device *dev, uint16_t table,
275 struct dcb_output *dcbent, int crtc)
276{
277 struct nouveau_drm *drm = nouveau_newpriv(dev);
278 struct nouveau_bios *bios = nouveau_bios(drm->device);
279 struct nvbios_init init = {
280 .subdev = nv_subdev(bios),
281 .bios = bios,
282 .offset = table,
283 .outp = dcbent,
284 .crtc = crtc,
285 .execute = 1
286 };
287
288 nvbios_exec(&init);
289}
290
291void
292nouveau_bios_init_exec(struct drm_device *dev, uint16_t table)
293{
294 nouveau_bios_run_init_table(dev, table, NULL, 0);
295}
diff --git a/drivers/gpu/drm/nouveau/nouveau_compat.h b/drivers/gpu/drm/nouveau/nouveau_compat.h
index 8bf5bec8171..7ffad0a7a30 100644
--- a/drivers/gpu/drm/nouveau/nouveau_compat.h
+++ b/drivers/gpu/drm/nouveau/nouveau_compat.h
@@ -1,6 +1,8 @@
1#ifndef __NOUVEAU_COMPAT_H__ 1#ifndef __NOUVEAU_COMPAT_H__
2#define __NOUVEAU_COMPAT_H__ 2#define __NOUVEAU_COMPAT_H__
3 3
4int nvdrm_gart_init(struct drm_device *, u64 *, u64 *);
5
4u8 _nv_rd08(struct drm_device *, u32); 6u8 _nv_rd08(struct drm_device *, u32);
5void _nv_wr08(struct drm_device *, u32, u8); 7void _nv_wr08(struct drm_device *, u32, u8);
6u32 _nv_rd32(struct drm_device *, u32); 8u32 _nv_rd32(struct drm_device *, u32);
@@ -45,4 +47,8 @@ int nva3_calc_pll(struct drm_device *dev, struct nvbios_pll *info, u32 freq,
45 int *N, int *fN, int *M, int *P); 47 int *N, int *fN, int *M, int *P);
46int nouveau_hw_setpll(struct drm_device *, u32, struct nouveau_pll_vals *); 48int nouveau_hw_setpll(struct drm_device *, u32, struct nouveau_pll_vals *);
47 49
50struct dcb_output;
51void nouveau_bios_run_init_table(struct drm_device *, u16, struct dcb_output *, int);
52void nouveau_bios_init_exec(struct drm_device *, u16);
53
48#endif 54#endif
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c
index f9cc3b38606..bd0985a4ff6 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.c
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
@@ -59,7 +59,7 @@ find_encoder(struct drm_connector *connector, int type)
59 continue; 59 continue;
60 nv_encoder = nouveau_encoder(obj_to_encoder(obj)); 60 nv_encoder = nouveau_encoder(obj_to_encoder(obj));
61 61
62 if (type == OUTPUT_ANY || nv_encoder->dcb->type == type) 62 if (type == DCB_OUTPUT_ANY || nv_encoder->dcb->type == type)
63 return nv_encoder; 63 return nv_encoder;
64 } 64 }
65 65
@@ -149,8 +149,8 @@ nouveau_connector_of_detect(struct drm_connector *connector)
149 struct device_node *cn, *dn = pci_device_to_OF_node(dev->pdev); 149 struct device_node *cn, *dn = pci_device_to_OF_node(dev->pdev);
150 150
151 if (!dn || 151 if (!dn ||
152 !((nv_encoder = find_encoder(connector, OUTPUT_TMDS)) || 152 !((nv_encoder = find_encoder(connector, DCB_OUTPUT_TMDS)) ||
153 (nv_encoder = find_encoder(connector, OUTPUT_ANALOG)))) 153 (nv_encoder = find_encoder(connector, DCB_OUTPUT_ANALOG))))
154 return NULL; 154 return NULL;
155 155
156 for_each_child_of_node(dn, cn) { 156 for_each_child_of_node(dn, cn) {
@@ -185,8 +185,8 @@ nouveau_connector_set_encoder(struct drm_connector *connector,
185 connector->interlace_allowed = true; 185 connector->interlace_allowed = true;
186 connector->doublescan_allowed = true; 186 connector->doublescan_allowed = true;
187 } else 187 } else
188 if (nv_encoder->dcb->type == OUTPUT_LVDS || 188 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS ||
189 nv_encoder->dcb->type == OUTPUT_TMDS) { 189 nv_encoder->dcb->type == DCB_OUTPUT_TMDS) {
190 connector->doublescan_allowed = false; 190 connector->doublescan_allowed = false;
191 connector->interlace_allowed = false; 191 connector->interlace_allowed = false;
192 } else { 192 } else {
@@ -204,7 +204,7 @@ nouveau_connector_set_encoder(struct drm_connector *connector,
204 if (nv_connector->type == DCB_CONNECTOR_DVI_I) { 204 if (nv_connector->type == DCB_CONNECTOR_DVI_I) {
205 drm_connector_property_set_value(connector, 205 drm_connector_property_set_value(connector,
206 dev->mode_config.dvi_i_subconnector_property, 206 dev->mode_config.dvi_i_subconnector_property,
207 nv_encoder->dcb->type == OUTPUT_TMDS ? 207 nv_encoder->dcb->type == DCB_OUTPUT_TMDS ?
208 DRM_MODE_SUBCONNECTOR_DVID : 208 DRM_MODE_SUBCONNECTOR_DVID :
209 DRM_MODE_SUBCONNECTOR_DVIA); 209 DRM_MODE_SUBCONNECTOR_DVIA);
210 } 210 }
@@ -238,7 +238,7 @@ nouveau_connector_detect(struct drm_connector *connector, bool force)
238 goto detect_analog; 238 goto detect_analog;
239 } 239 }
240 240
241 if (nv_encoder->dcb->type == OUTPUT_DP && 241 if (nv_encoder->dcb->type == DCB_OUTPUT_DP &&
242 !nouveau_dp_detect(to_drm_encoder(nv_encoder))) { 242 !nouveau_dp_detect(to_drm_encoder(nv_encoder))) {
243 NV_ERROR(dev, "Detected %s, but failed init\n", 243 NV_ERROR(dev, "Detected %s, but failed init\n",
244 drm_get_connector_name(connector)); 244 drm_get_connector_name(connector));
@@ -251,19 +251,19 @@ nouveau_connector_detect(struct drm_connector *connector, bool force)
251 * isn't necessarily correct. 251 * isn't necessarily correct.
252 */ 252 */
253 nv_partner = NULL; 253 nv_partner = NULL;
254 if (nv_encoder->dcb->type == OUTPUT_TMDS) 254 if (nv_encoder->dcb->type == DCB_OUTPUT_TMDS)
255 nv_partner = find_encoder(connector, OUTPUT_ANALOG); 255 nv_partner = find_encoder(connector, DCB_OUTPUT_ANALOG);
256 if (nv_encoder->dcb->type == OUTPUT_ANALOG) 256 if (nv_encoder->dcb->type == DCB_OUTPUT_ANALOG)
257 nv_partner = find_encoder(connector, OUTPUT_TMDS); 257 nv_partner = find_encoder(connector, DCB_OUTPUT_TMDS);
258 258
259 if (nv_partner && ((nv_encoder->dcb->type == OUTPUT_ANALOG && 259 if (nv_partner && ((nv_encoder->dcb->type == DCB_OUTPUT_ANALOG &&
260 nv_partner->dcb->type == OUTPUT_TMDS) || 260 nv_partner->dcb->type == DCB_OUTPUT_TMDS) ||
261 (nv_encoder->dcb->type == OUTPUT_TMDS && 261 (nv_encoder->dcb->type == DCB_OUTPUT_TMDS &&
262 nv_partner->dcb->type == OUTPUT_ANALOG))) { 262 nv_partner->dcb->type == DCB_OUTPUT_ANALOG))) {
263 if (nv_connector->edid->input & DRM_EDID_INPUT_DIGITAL) 263 if (nv_connector->edid->input & DRM_EDID_INPUT_DIGITAL)
264 type = OUTPUT_TMDS; 264 type = DCB_OUTPUT_TMDS;
265 else 265 else
266 type = OUTPUT_ANALOG; 266 type = DCB_OUTPUT_ANALOG;
267 267
268 nv_encoder = find_encoder(connector, type); 268 nv_encoder = find_encoder(connector, type);
269 } 269 }
@@ -279,9 +279,9 @@ nouveau_connector_detect(struct drm_connector *connector, bool force)
279 } 279 }
280 280
281detect_analog: 281detect_analog:
282 nv_encoder = find_encoder(connector, OUTPUT_ANALOG); 282 nv_encoder = find_encoder(connector, DCB_OUTPUT_ANALOG);
283 if (!nv_encoder && !nouveau_tv_disable) 283 if (!nv_encoder && !nouveau_tv_disable)
284 nv_encoder = find_encoder(connector, OUTPUT_TV); 284 nv_encoder = find_encoder(connector, DCB_OUTPUT_TV);
285 if (nv_encoder && force) { 285 if (nv_encoder && force) {
286 struct drm_encoder *encoder = to_drm_encoder(nv_encoder); 286 struct drm_encoder *encoder = to_drm_encoder(nv_encoder);
287 struct drm_encoder_helper_funcs *helper = 287 struct drm_encoder_helper_funcs *helper =
@@ -314,7 +314,7 @@ nouveau_connector_detect_lvds(struct drm_connector *connector, bool force)
314 nv_connector->edid = NULL; 314 nv_connector->edid = NULL;
315 } 315 }
316 316
317 nv_encoder = find_encoder(connector, OUTPUT_LVDS); 317 nv_encoder = find_encoder(connector, DCB_OUTPUT_LVDS);
318 if (!nv_encoder) 318 if (!nv_encoder)
319 return connector_status_disconnected; 319 return connector_status_disconnected;
320 320
@@ -386,11 +386,11 @@ nouveau_connector_force(struct drm_connector *connector)
386 386
387 if (nv_connector->type == DCB_CONNECTOR_DVI_I) { 387 if (nv_connector->type == DCB_CONNECTOR_DVI_I) {
388 if (connector->force == DRM_FORCE_ON_DIGITAL) 388 if (connector->force == DRM_FORCE_ON_DIGITAL)
389 type = OUTPUT_TMDS; 389 type = DCB_OUTPUT_TMDS;
390 else 390 else
391 type = OUTPUT_ANALOG; 391 type = DCB_OUTPUT_ANALOG;
392 } else 392 } else
393 type = OUTPUT_ANY; 393 type = DCB_OUTPUT_ANY;
394 394
395 nv_encoder = find_encoder(connector, type); 395 nv_encoder = find_encoder(connector, type);
396 if (!nv_encoder) { 396 if (!nv_encoder) {
@@ -533,7 +533,7 @@ nouveau_connector_set_property(struct drm_connector *connector,
533 } 533 }
534 } 534 }
535 535
536 if (nv_encoder && nv_encoder->dcb->type == OUTPUT_TV) 536 if (nv_encoder && nv_encoder->dcb->type == DCB_OUTPUT_TV)
537 return get_slave_funcs(encoder)->set_property( 537 return get_slave_funcs(encoder)->set_property(
538 encoder, connector, property, value); 538 encoder, connector, property, value);
539 539
@@ -662,7 +662,7 @@ nouveau_connector_detect_depth(struct drm_connector *connector)
662 } 662 }
663 663
664 /* we're out of options unless we're LVDS, default to 8bpc */ 664 /* we're out of options unless we're LVDS, default to 8bpc */
665 if (nv_encoder->dcb->type != OUTPUT_LVDS) { 665 if (nv_encoder->dcb->type != DCB_OUTPUT_LVDS) {
666 connector->display_info.bpc = 8; 666 connector->display_info.bpc = 8;
667 return; 667 return;
668 } 668 }
@@ -710,7 +710,7 @@ nouveau_connector_get_modes(struct drm_connector *connector)
710 if (nv_connector->edid) 710 if (nv_connector->edid)
711 ret = drm_add_edid_modes(connector, nv_connector->edid); 711 ret = drm_add_edid_modes(connector, nv_connector->edid);
712 else 712 else
713 if (nv_encoder->dcb->type == OUTPUT_LVDS && 713 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS &&
714 (nv_encoder->dcb->lvdsconf.use_straps_for_mode || 714 (nv_encoder->dcb->lvdsconf.use_straps_for_mode ||
715 dev_priv->vbios.fp_no_ddc) && nouveau_bios_fp_mode(dev, NULL)) { 715 dev_priv->vbios.fp_no_ddc) && nouveau_bios_fp_mode(dev, NULL)) {
716 struct drm_display_mode mode; 716 struct drm_display_mode mode;
@@ -747,7 +747,7 @@ nouveau_connector_get_modes(struct drm_connector *connector)
747 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) 747 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
748 nouveau_connector_detect_depth(connector); 748 nouveau_connector_detect_depth(connector);
749 749
750 if (nv_encoder->dcb->type == OUTPUT_TV) 750 if (nv_encoder->dcb->type == DCB_OUTPUT_TV)
751 ret = get_slave_funcs(encoder)->get_modes(encoder, connector); 751 ret = get_slave_funcs(encoder)->get_modes(encoder, connector);
752 752
753 if (nv_connector->type == DCB_CONNECTOR_LVDS || 753 if (nv_connector->type == DCB_CONNECTOR_LVDS ||
@@ -763,7 +763,7 @@ get_tmds_link_bandwidth(struct drm_connector *connector)
763{ 763{
764 struct nouveau_connector *nv_connector = nouveau_connector(connector); 764 struct nouveau_connector *nv_connector = nouveau_connector(connector);
765 struct drm_nouveau_private *dev_priv = connector->dev->dev_private; 765 struct drm_nouveau_private *dev_priv = connector->dev->dev_private;
766 struct dcb_entry *dcb = nv_connector->detected_encoder->dcb; 766 struct dcb_output *dcb = nv_connector->detected_encoder->dcb;
767 767
768 if (dcb->location != DCB_LOC_ON_CHIP || 768 if (dcb->location != DCB_LOC_ON_CHIP ||
769 dev_priv->chipset >= 0x46) 769 dev_priv->chipset >= 0x46)
@@ -787,7 +787,7 @@ nouveau_connector_mode_valid(struct drm_connector *connector,
787 unsigned clock = mode->clock; 787 unsigned clock = mode->clock;
788 788
789 switch (nv_encoder->dcb->type) { 789 switch (nv_encoder->dcb->type) {
790 case OUTPUT_LVDS: 790 case DCB_OUTPUT_LVDS:
791 if (nv_connector->native_mode && 791 if (nv_connector->native_mode &&
792 (mode->hdisplay > nv_connector->native_mode->hdisplay || 792 (mode->hdisplay > nv_connector->native_mode->hdisplay ||
793 mode->vdisplay > nv_connector->native_mode->vdisplay)) 793 mode->vdisplay > nv_connector->native_mode->vdisplay))
@@ -796,19 +796,19 @@ nouveau_connector_mode_valid(struct drm_connector *connector,
796 min_clock = 0; 796 min_clock = 0;
797 max_clock = 400000; 797 max_clock = 400000;
798 break; 798 break;
799 case OUTPUT_TMDS: 799 case DCB_OUTPUT_TMDS:
800 max_clock = get_tmds_link_bandwidth(connector); 800 max_clock = get_tmds_link_bandwidth(connector);
801 if (nouveau_duallink && nv_encoder->dcb->duallink_possible) 801 if (nouveau_duallink && nv_encoder->dcb->duallink_possible)
802 max_clock *= 2; 802 max_clock *= 2;
803 break; 803 break;
804 case OUTPUT_ANALOG: 804 case DCB_OUTPUT_ANALOG:
805 max_clock = nv_encoder->dcb->crtconf.maxfreq; 805 max_clock = nv_encoder->dcb->crtconf.maxfreq;
806 if (!max_clock) 806 if (!max_clock)
807 max_clock = 350000; 807 max_clock = 350000;
808 break; 808 break;
809 case OUTPUT_TV: 809 case DCB_OUTPUT_TV:
810 return get_slave_funcs(encoder)->mode_valid(encoder, mode); 810 return get_slave_funcs(encoder)->mode_valid(encoder, mode);
811 case OUTPUT_DP: 811 case DCB_OUTPUT_DP:
812 max_clock = nv_encoder->dp.link_nr; 812 max_clock = nv_encoder->dp.link_nr;
813 max_clock *= nv_encoder->dp.link_bw; 813 max_clock *= nv_encoder->dp.link_bw;
814 clock = clock * (connector->display_info.bpc * 3) / 10; 814 clock = clock * (connector->display_info.bpc * 3) / 10;
@@ -923,7 +923,7 @@ nouveau_connector_create(struct drm_device *dev, int index)
923 nv_connector->index = index; 923 nv_connector->index = index;
924 924
925 /* attempt to parse vbios connector type and hotplug gpio */ 925 /* attempt to parse vbios connector type and hotplug gpio */
926 nv_connector->dcb = dcb_conn(dev, index); 926 nv_connector->dcb = olddcb_conn(dev, index);
927 if (nv_connector->dcb) { 927 if (nv_connector->dcb) {
928 static const u8 hpd[16] = { 928 static const u8 hpd[16] = {
929 0xff, 0x07, 0x08, 0xff, 0xff, 0x51, 0x52, 0xff, 929 0xff, 0x07, 0x08, 0xff, 0xff, 0x51, 0x52, 0xff,
@@ -931,7 +931,7 @@ nouveau_connector_create(struct drm_device *dev, int index)
931 }; 931 };
932 932
933 u32 entry = ROM16(nv_connector->dcb[0]); 933 u32 entry = ROM16(nv_connector->dcb[0]);
934 if (dcb_conntab(dev)[3] >= 4) 934 if (olddcb_conntab(dev)[3] >= 4)
935 entry |= (u32)ROM16(nv_connector->dcb[2]) << 16; 935 entry |= (u32)ROM16(nv_connector->dcb[2]) << 16;
936 936
937 nv_connector->hpd = ffs((entry & 0x07033000) >> 12); 937 nv_connector->hpd = ffs((entry & 0x07033000) >> 12);
@@ -975,25 +975,25 @@ nouveau_connector_create(struct drm_device *dev, int index)
975 encoders |= (1 << dcbt->entry[i].type); 975 encoders |= (1 << dcbt->entry[i].type);
976 } 976 }
977 977
978 if (encoders & (1 << OUTPUT_DP)) { 978 if (encoders & (1 << DCB_OUTPUT_DP)) {
979 if (encoders & (1 << OUTPUT_TMDS)) 979 if (encoders & (1 << DCB_OUTPUT_TMDS))
980 nv_connector->type = DCB_CONNECTOR_DP; 980 nv_connector->type = DCB_CONNECTOR_DP;
981 else 981 else
982 nv_connector->type = DCB_CONNECTOR_eDP; 982 nv_connector->type = DCB_CONNECTOR_eDP;
983 } else 983 } else
984 if (encoders & (1 << OUTPUT_TMDS)) { 984 if (encoders & (1 << DCB_OUTPUT_TMDS)) {
985 if (encoders & (1 << OUTPUT_ANALOG)) 985 if (encoders & (1 << DCB_OUTPUT_ANALOG))
986 nv_connector->type = DCB_CONNECTOR_DVI_I; 986 nv_connector->type = DCB_CONNECTOR_DVI_I;
987 else 987 else
988 nv_connector->type = DCB_CONNECTOR_DVI_D; 988 nv_connector->type = DCB_CONNECTOR_DVI_D;
989 } else 989 } else
990 if (encoders & (1 << OUTPUT_ANALOG)) { 990 if (encoders & (1 << DCB_OUTPUT_ANALOG)) {
991 nv_connector->type = DCB_CONNECTOR_VGA; 991 nv_connector->type = DCB_CONNECTOR_VGA;
992 } else 992 } else
993 if (encoders & (1 << OUTPUT_LVDS)) { 993 if (encoders & (1 << DCB_OUTPUT_LVDS)) {
994 nv_connector->type = DCB_CONNECTOR_LVDS; 994 nv_connector->type = DCB_CONNECTOR_LVDS;
995 } else 995 } else
996 if (encoders & (1 << OUTPUT_TV)) { 996 if (encoders & (1 << DCB_OUTPUT_TV)) {
997 nv_connector->type = DCB_CONNECTOR_TV_0; 997 nv_connector->type = DCB_CONNECTOR_TV_0;
998 } 998 }
999 } 999 }
diff --git a/drivers/gpu/drm/nouveau/nouveau_dp.c b/drivers/gpu/drm/nouveau/nouveau_dp.c
index 9e18b35803a..6fe11f8c5f6 100644
--- a/drivers/gpu/drm/nouveau/nouveau_dp.c
+++ b/drivers/gpu/drm/nouveau/nouveau_dp.c
@@ -31,7 +31,7 @@
31#include "nouveau_crtc.h" 31#include "nouveau_crtc.h"
32 32
33u8 * 33u8 *
34nouveau_dp_bios_data(struct drm_device *dev, struct dcb_entry *dcb, u8 **entry) 34nouveau_dp_bios_data(struct drm_device *dev, struct dcb_output *dcb, u8 **entry)
35{ 35{
36 struct bit_entry d; 36 struct bit_entry d;
37 u8 *table; 37 u8 *table;
@@ -80,7 +80,7 @@ nouveau_dp_bios_data(struct drm_device *dev, struct dcb_entry *dcb, u8 **entry)
80struct dp_state { 80struct dp_state {
81 struct nouveau_i2c_port *auxch; 81 struct nouveau_i2c_port *auxch;
82 struct dp_train_func *func; 82 struct dp_train_func *func;
83 struct dcb_entry *dcb; 83 struct dcb_output *dcb;
84 int crtc; 84 int crtc;
85 u8 *dpcd; 85 u8 *dpcd;
86 int link_nr; 86 int link_nr;
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c
index c72d42636c8..3b4e65d5122 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@ -32,6 +32,7 @@
32#include <subdev/device.h> 32#include <subdev/device.h>
33 33
34#include "nouveau_drm.h" 34#include "nouveau_drm.h"
35#include "nouveau_agp.h"
35 36
36int __devinit nouveau_pci_probe(struct pci_dev *, const struct pci_device_id *); 37int __devinit nouveau_pci_probe(struct pci_dev *, const struct pci_device_id *);
37void nouveau_pci_remove(struct pci_dev *); 38void nouveau_pci_remove(struct pci_dev *);
@@ -123,6 +124,30 @@ nouveau_drm_load(struct drm_device *dev, unsigned long flags)
123 INIT_LIST_HEAD(&drm->clients); 124 INIT_LIST_HEAD(&drm->clients);
124 drm->dev = dev; 125 drm->dev = dev;
125 126
127 /* make sure AGP controller is in a consistent state before we
128 * (possibly) execute vbios init tables (see nouveau_agp.h)
129 */
130 if (drm_pci_device_is_agp(dev) && dev->agp) {
131 /* dummy device object, doesn't init anything, but allows
132 * agp code access to registers
133 */
134 ret = nouveau_object_new(nv_object(drm), NVDRM_CLIENT,
135 NVDRM_DEVICE, 0x0080,
136 &(struct nv_device_class) {
137 .device = ~0,
138 .disable =
139 ~(NV_DEVICE_DISABLE_MMIO |
140 NV_DEVICE_DISABLE_IDENTIFY),
141 .debug0 = ~0,
142 }, sizeof(struct nv_device_class),
143 &drm->device);
144 if (ret)
145 return ret;
146
147 nouveau_agp_reset(drm);
148 nouveau_object_del(nv_object(drm), NVDRM_CLIENT, NVDRM_DEVICE);
149 }
150
126 ret = nouveau_object_new(nv_object(drm), NVDRM_CLIENT, NVDRM_DEVICE, 151 ret = nouveau_object_new(nv_object(drm), NVDRM_CLIENT, NVDRM_DEVICE,
127 0x0080, &(struct nv_device_class) { 152 0x0080, &(struct nv_device_class) {
128 .device = ~0, 153 .device = ~0,
@@ -133,6 +158,9 @@ nouveau_drm_load(struct drm_device *dev, unsigned long flags)
133 if (ret) 158 if (ret)
134 goto fail_device; 159 goto fail_device;
135 160
161 /* initialise AGP */
162 nouveau_agp_init(drm);
163
136 ret = nouveau_load(dev, flags); 164 ret = nouveau_load(dev, flags);
137 if (ret) 165 if (ret)
138 goto fail_device; 166 goto fail_device;
@@ -155,6 +183,8 @@ nouveau_drm_unload(struct drm_device *dev)
155 if (ret) 183 if (ret)
156 return ret; 184 return ret;
157 185
186 nouveau_agp_fini(drm);
187
158 pci_set_drvdata(pdev, drm->client.base.device); 188 pci_set_drvdata(pdev, drm->client.base.device);
159 nouveau_cli_destroy(&drm->client); 189 nouveau_cli_destroy(&drm->client);
160 return 0; 190 return 0;
@@ -195,6 +225,8 @@ nouveau_drm_suspend(struct pci_dev *pdev, pm_message_t pm_state)
195 if (ret) 225 if (ret)
196 goto fail_client; 226 goto fail_client;
197 227
228 nouveau_agp_fini(drm);
229
198 pci_save_state(pdev); 230 pci_save_state(pdev);
199 if (pm_state.event == PM_EVENT_SUSPEND) { 231 if (pm_state.event == PM_EVENT_SUSPEND) {
200 pci_disable_device(pdev); 232 pci_disable_device(pdev);
@@ -230,12 +262,16 @@ nouveau_drm_resume(struct pci_dev *pdev)
230 return ret; 262 return ret;
231 pci_set_master(pdev); 263 pci_set_master(pdev);
232 264
265 nouveau_agp_reset(drm);
266
233 nouveau_client_init(&drm->client.base); 267 nouveau_client_init(&drm->client.base);
234 268
235 list_for_each_entry(cli, &drm->clients, head) { 269 list_for_each_entry(cli, &drm->clients, head) {
236 nouveau_client_init(&cli->base); 270 nouveau_client_init(&cli->base);
237 } 271 }
238 272
273 nouveau_agp_init(drm);
274
239 return nouveau_pci_resume(pdev); 275 return nouveau_pci_resume(pdev);
240} 276}
241 277
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.h b/drivers/gpu/drm/nouveau/nouveau_drm.h
index ef5500f5686..87698067244 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.h
@@ -23,6 +23,16 @@ struct nouveau_drm {
23 23
24 struct nouveau_object *device; 24 struct nouveau_object *device;
25 struct list_head clients; 25 struct list_head clients;
26
27 struct {
28 enum {
29 UNKNOWN = 0,
30 DISABLE = 1,
31 ENABLED = 2
32 } stat;
33 u32 base;
34 u32 size;
35 } agp;
26}; 36};
27 37
28int nouveau_drm_suspend(struct pci_dev *, pm_message_t); 38int nouveau_drm_suspend(struct pci_dev *, pm_message_t);
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.c b/drivers/gpu/drm/nouveau/nouveau_drv.c
index cea947beb35..25487c148e4 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.c
@@ -29,7 +29,6 @@
29#include "drm.h" 29#include "drm.h"
30#include "drm_crtc_helper.h" 30#include "drm_crtc_helper.h"
31#include "nouveau_drv.h" 31#include "nouveau_drv.h"
32#include "nouveau_agp.h"
33#include "nouveau_abi16.h" 32#include "nouveau_abi16.h"
34#include "nouveau_hw.h" 33#include "nouveau_hw.h"
35#include "nouveau_fb.h" 34#include "nouveau_fb.h"
@@ -219,7 +218,6 @@ nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state)
219 goto out_abort; 218 goto out_abort;
220 } 219 }
221 220
222 nouveau_agp_fini(dev);
223 return 0; 221 return 0;
224 222
225out_abort: 223out_abort:
@@ -241,9 +239,6 @@ nouveau_pci_resume(struct pci_dev *pdev)
241 struct drm_crtc *crtc; 239 struct drm_crtc *crtc;
242 int ret, i; 240 int ret, i;
243 241
244 /* Make sure the AGP controller is in a consistent state */
245 nouveau_agp_reset(dev);
246
247 /* Make the CRTCs accessible */ 242 /* Make the CRTCs accessible */
248 engine->display.early_init(dev); 243 engine->display.early_init(dev);
249 244
@@ -252,8 +247,6 @@ nouveau_pci_resume(struct pci_dev *pdev)
252 if (ret) 247 if (ret)
253 return ret; 248 return ret;
254 249
255 nouveau_agp_init(dev);
256
257 NV_INFO(dev, "Restoring GPU objects...\n"); 250 NV_INFO(dev, "Restoring GPU objects...\n");
258 nouveau_gpuobj_resume(dev); 251 nouveau_gpuobj_resume(dev);
259 252
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
index 2b519b5cfac..f6be94d323f 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@ -1040,22 +1040,19 @@ static inline void nouveau_backlight_exit(struct drm_device *dev) { }
1040extern int nouveau_bios_init(struct drm_device *); 1040extern int nouveau_bios_init(struct drm_device *);
1041extern void nouveau_bios_takedown(struct drm_device *dev); 1041extern void nouveau_bios_takedown(struct drm_device *dev);
1042extern int nouveau_run_vbios_init(struct drm_device *); 1042extern int nouveau_run_vbios_init(struct drm_device *);
1043extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
1044 struct dcb_entry *, int crtc);
1045extern void nouveau_bios_init_exec(struct drm_device *, uint16_t table);
1046extern struct dcb_connector_table_entry * 1043extern struct dcb_connector_table_entry *
1047nouveau_bios_connector_entry(struct drm_device *, int index); 1044nouveau_bios_connector_entry(struct drm_device *, int index);
1048extern int nouveau_bios_run_display_table(struct drm_device *, u16 id, int clk, 1045extern int nouveau_bios_run_display_table(struct drm_device *, u16 id, int clk,
1049 struct dcb_entry *, int crtc); 1046 struct dcb_output *, int crtc);
1050extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1047extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
1051extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1048extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
1052extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1049extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
1053 bool *dl, bool *if_is_24bit); 1050 bool *dl, bool *if_is_24bit);
1054extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1051extern int run_tmds_table(struct drm_device *, struct dcb_output *,
1055 int head, int pxclk); 1052 int head, int pxclk);
1056extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1053extern int call_lvds_script(struct drm_device *, struct dcb_output *, int head,
1057 enum LVDS_script, int pxclk); 1054 enum LVDS_script, int pxclk);
1058bool bios_encoder_match(struct dcb_entry *, u32 hash); 1055bool bios_encoder_match(struct dcb_output *, u32 hash);
1059 1056
1060/* nouveau_mxm.c */ 1057/* nouveau_mxm.c */
1061int nouveau_mxm_init(struct drm_device *dev); 1058int nouveau_mxm_init(struct drm_device *dev);
@@ -1234,26 +1231,26 @@ extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1234 unsigned long arg); 1231 unsigned long arg);
1235 1232
1236/* nv04_dac.c */ 1233/* nv04_dac.c */
1237extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1234extern int nv04_dac_create(struct drm_connector *, struct dcb_output *);
1238extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1235extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
1239extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1236extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1240extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1237extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1241extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1238extern bool nv04_dac_in_use(struct drm_encoder *encoder);
1242 1239
1243/* nv04_dfp.c */ 1240/* nv04_dfp.c */
1244extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1241extern int nv04_dfp_create(struct drm_connector *, struct dcb_output *);
1245extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1242extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_output *dcbent);
1246extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1243extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_output *dcbent,
1247 int head, bool dl); 1244 int head, bool dl);
1248extern void nv04_dfp_disable(struct drm_device *dev, int head); 1245extern void nv04_dfp_disable(struct drm_device *dev, int head);
1249extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1246extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1250 1247
1251/* nv04_tv.c */ 1248/* nv04_tv.c */
1252extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1249extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
1253extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1250extern int nv04_tv_create(struct drm_connector *, struct dcb_output *);
1254 1251
1255/* nv17_tv.c */ 1252/* nv17_tv.c */
1256extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1253extern int nv17_tv_create(struct drm_connector *, struct dcb_output *);
1257 1254
1258/* nv04_display.c */ 1255/* nv04_display.c */
1259extern int nv04_display_early_init(struct drm_device *); 1256extern int nv04_display_early_init(struct drm_device *);
diff --git a/drivers/gpu/drm/nouveau/nouveau_encoder.h b/drivers/gpu/drm/nouveau/nouveau_encoder.h
index 1e79ee5fb89..789221d86c4 100644
--- a/drivers/gpu/drm/nouveau/nouveau_encoder.h
+++ b/drivers/gpu/drm/nouveau/nouveau_encoder.h
@@ -35,17 +35,17 @@
35struct nouveau_i2c_port; 35struct nouveau_i2c_port;
36 36
37struct dp_train_func { 37struct dp_train_func {
38 void (*link_set)(struct drm_device *, struct dcb_entry *, int crtc, 38 void (*link_set)(struct drm_device *, struct dcb_output *, int crtc,
39 int nr, u32 bw, bool enhframe); 39 int nr, u32 bw, bool enhframe);
40 void (*train_set)(struct drm_device *, struct dcb_entry *, u8 pattern); 40 void (*train_set)(struct drm_device *, struct dcb_output *, u8 pattern);
41 void (*train_adj)(struct drm_device *, struct dcb_entry *, 41 void (*train_adj)(struct drm_device *, struct dcb_output *,
42 u8 lane, u8 swing, u8 preem); 42 u8 lane, u8 swing, u8 preem);
43}; 43};
44 44
45struct nouveau_encoder { 45struct nouveau_encoder {
46 struct drm_encoder_slave base; 46 struct drm_encoder_slave base;
47 47
48 struct dcb_entry *dcb; 48 struct dcb_output *dcb;
49 int or; 49 int or;
50 50
51 /* different to drm_encoder.crtc, this reflects what's 51 /* different to drm_encoder.crtc, this reflects what's
@@ -92,13 +92,13 @@ get_slave_funcs(struct drm_encoder *enc)
92bool nouveau_dp_detect(struct drm_encoder *); 92bool nouveau_dp_detect(struct drm_encoder *);
93void nouveau_dp_dpms(struct drm_encoder *, int mode, u32 datarate, 93void nouveau_dp_dpms(struct drm_encoder *, int mode, u32 datarate,
94 struct dp_train_func *); 94 struct dp_train_func *);
95u8 *nouveau_dp_bios_data(struct drm_device *, struct dcb_entry *, u8 **); 95u8 *nouveau_dp_bios_data(struct drm_device *, struct dcb_output *, u8 **);
96 96
97struct nouveau_connector * 97struct nouveau_connector *
98nouveau_encoder_connector_get(struct nouveau_encoder *encoder); 98nouveau_encoder_connector_get(struct nouveau_encoder *encoder);
99int nv50_sor_create(struct drm_connector *, struct dcb_entry *); 99int nv50_sor_create(struct drm_connector *, struct dcb_output *);
100void nv50_sor_dp_calc_tu(struct drm_device *, int, int, u32, u32); 100void nv50_sor_dp_calc_tu(struct drm_device *, int, int, u32, u32);
101int nv50_dac_create(struct drm_connector *, struct dcb_entry *); 101int nv50_dac_create(struct drm_connector *, struct dcb_output *);
102 102
103 103
104#endif /* __NOUVEAU_ENCODER_H__ */ 104#endif /* __NOUVEAU_ENCODER_H__ */
diff --git a/drivers/gpu/drm/nouveau/nouveau_hw.h b/drivers/gpu/drm/nouveau/nouveau_hw.h
index ff7f31c279d..24c45921361 100644
--- a/drivers/gpu/drm/nouveau/nouveau_hw.h
+++ b/drivers/gpu/drm/nouveau/nouveau_hw.h
@@ -161,7 +161,7 @@ static inline void NVWriteRAMDAC(struct drm_device *dev,
161static inline uint8_t nv_read_tmds(struct drm_device *dev, 161static inline uint8_t nv_read_tmds(struct drm_device *dev,
162 int or, int dl, uint8_t address) 162 int or, int dl, uint8_t address)
163{ 163{
164 int ramdac = (or & OUTPUT_C) >> 2; 164 int ramdac = (or & DCB_OUTPUT_C) >> 2;
165 165
166 NVWriteRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_CONTROL + dl * 8, 166 NVWriteRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_CONTROL + dl * 8,
167 NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE | address); 167 NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE | address);
@@ -172,7 +172,7 @@ static inline void nv_write_tmds(struct drm_device *dev,
172 int or, int dl, uint8_t address, 172 int or, int dl, uint8_t address,
173 uint8_t data) 173 uint8_t data)
174{ 174{
175 int ramdac = (or & OUTPUT_C) >> 2; 175 int ramdac = (or & DCB_OUTPUT_C) >> 2;
176 176
177 NVWriteRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_DATA + dl * 8, data); 177 NVWriteRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_DATA + dl * 8, data);
178 NVWriteRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_CONTROL + dl * 8, address); 178 NVWriteRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_CONTROL + dl * 8, address);
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c
index c816e03c15d..689d3e70805 100644
--- a/drivers/gpu/drm/nouveau/nouveau_mem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_mem.c
@@ -36,7 +36,6 @@
36#include "drm_sarea.h" 36#include "drm_sarea.h"
37 37
38#include "nouveau_drv.h" 38#include "nouveau_drv.h"
39#include "nouveau_agp.h"
40#include "nouveau_pm.h" 39#include "nouveau_pm.h"
41#include <core/mm.h> 40#include <core/mm.h>
42#include <subdev/vm.h> 41#include <subdev/vm.h>
@@ -173,7 +172,6 @@ void
173nouveau_mem_gart_fini(struct drm_device *dev) 172nouveau_mem_gart_fini(struct drm_device *dev)
174{ 173{
175 nouveau_sgdma_takedown(dev); 174 nouveau_sgdma_takedown(dev);
176 nouveau_agp_fini(dev);
177} 175}
178 176
179bool 177bool
@@ -308,7 +306,9 @@ nouveau_mem_gart_init(struct drm_device *dev)
308 struct ttm_bo_device *bdev = &dev_priv->ttm.bdev; 306 struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
309 int ret; 307 int ret;
310 308
311 nouveau_agp_init(dev); 309 if (!nvdrm_gart_init(dev, &dev_priv->gart_info.aper_base,
310 &dev_priv->gart_info.aper_size))
311 dev_priv->gart_info.type = NOUVEAU_GART_AGP;
312 312
313 if (dev_priv->gart_info.type == NOUVEAU_GART_NONE) { 313 if (dev_priv->gart_info.type == NOUVEAU_GART_NONE) {
314 ret = nouveau_sgdma_init(dev); 314 ret = nouveau_sgdma_init(dev);
diff --git a/drivers/gpu/drm/nouveau/nouveau_mxm.c b/drivers/gpu/drm/nouveau/nouveau_mxm.c
index 7ca129d5583..670ef087d3d 100644
--- a/drivers/gpu/drm/nouveau/nouveau_mxm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_mxm.c
@@ -390,7 +390,7 @@ mxm_dcb_sanitise_entry(struct drm_device *dev, void *data, int idx, u8 *dcbe)
390 * vbios mxm table 390 * vbios mxm table
391 */ 391 */
392 i2cidx = mxm_ddc_map(dev, ctx.desc.ddc_port); 392 i2cidx = mxm_ddc_map(dev, ctx.desc.ddc_port);
393 if ((ctx.outp[0] & 0x0000000f) != OUTPUT_DP) 393 if ((ctx.outp[0] & 0x0000000f) != DCB_OUTPUT_DP)
394 i2cidx = (i2cidx & 0x0f) << 4; 394 i2cidx = (i2cidx & 0x0f) << 4;
395 else 395 else
396 i2cidx = (i2cidx & 0xf0); 396 i2cidx = (i2cidx & 0xf0);
@@ -419,7 +419,7 @@ mxm_dcb_sanitise_entry(struct drm_device *dev, void *data, int idx, u8 *dcbe)
419 * and the mxm data says the connector is really HDMI. another 419 * and the mxm data says the connector is really HDMI. another
420 * common example is DP->eDP. 420 * common example is DP->eDP.
421 */ 421 */
422 conn = dcb_conn(dev, (ctx.outp[0] & 0x0000f000) >> 12); 422 conn = olddcb_conn(dev, (ctx.outp[0] & 0x0000f000) >> 12);
423 type = conn[0]; 423 type = conn[0];
424 switch (ctx.desc.conn_type) { 424 switch (ctx.desc.conn_type) {
425 case 0x01: /* LVDS */ 425 case 0x01: /* LVDS */
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c
index 84e03797bec..1a07655d1e9 100644
--- a/drivers/gpu/drm/nouveau/nouveau_state.c
+++ b/drivers/gpu/drm/nouveau/nouveau_state.c
@@ -34,7 +34,6 @@
34 34
35#include "nouveau_drv.h" 35#include "nouveau_drv.h"
36#include <nouveau_drm.h> 36#include <nouveau_drm.h>
37#include "nouveau_agp.h"
38#include "nouveau_fbcon.h" 37#include "nouveau_fbcon.h"
39#include <core/ramht.h> 38#include <core/ramht.h>
40#include "nouveau_pm.h" 39#include "nouveau_pm.h"
@@ -516,9 +515,6 @@ nouveau_card_init(struct drm_device *dev)
516 spin_lock_init(&dev_priv->context_switch_lock); 515 spin_lock_init(&dev_priv->context_switch_lock);
517 spin_lock_init(&dev_priv->vm_lock); 516 spin_lock_init(&dev_priv->vm_lock);
518 517
519 /* Make sure the AGP controller is in a consistent state */
520 nouveau_agp_reset(dev);
521
522 /* Make the CRTCs and I2C buses accessible */ 518 /* Make the CRTCs and I2C buses accessible */
523 ret = engine->display.early_init(dev); 519 ret = engine->display.early_init(dev);
524 if (ret) 520 if (ret)
diff --git a/drivers/gpu/drm/nouveau/nv04_crtc.c b/drivers/gpu/drm/nouveau/nv04_crtc.c
index 93ca09b90da..1d38968abcf 100644
--- a/drivers/gpu/drm/nouveau/nv04_crtc.c
+++ b/drivers/gpu/drm/nouveau/nv04_crtc.c
@@ -251,8 +251,8 @@ nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode)
251 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 251 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
252 252
253 if (encoder->crtc == crtc && 253 if (encoder->crtc == crtc &&
254 (nv_encoder->dcb->type == OUTPUT_LVDS || 254 (nv_encoder->dcb->type == DCB_OUTPUT_LVDS ||
255 nv_encoder->dcb->type == OUTPUT_TMDS)) 255 nv_encoder->dcb->type == DCB_OUTPUT_TMDS))
256 fp_output = true; 256 fp_output = true;
257 } 257 }
258 258
@@ -467,11 +467,11 @@ nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode)
467 if (encoder->crtc != crtc) 467 if (encoder->crtc != crtc)
468 continue; 468 continue;
469 469
470 if (nv_encoder->dcb->type == OUTPUT_LVDS) 470 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS)
471 digital = lvds_output = true; 471 digital = lvds_output = true;
472 if (nv_encoder->dcb->type == OUTPUT_TV) 472 if (nv_encoder->dcb->type == DCB_OUTPUT_TV)
473 tv_output = true; 473 tv_output = true;
474 if (nv_encoder->dcb->type == OUTPUT_TMDS) 474 if (nv_encoder->dcb->type == DCB_OUTPUT_TMDS)
475 digital = tmds_output = true; 475 digital = tmds_output = true;
476 if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP && digital) 476 if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP && digital)
477 off_chip_digital = true; 477 off_chip_digital = true;
diff --git a/drivers/gpu/drm/nouveau/nv04_dac.c b/drivers/gpu/drm/nouveau/nv04_dac.c
index 54deb2779f8..a1a2c2f33d5 100644
--- a/drivers/gpu/drm/nouveau/nv04_dac.c
+++ b/drivers/gpu/drm/nouveau/nv04_dac.c
@@ -38,12 +38,12 @@
38 38
39int nv04_dac_output_offset(struct drm_encoder *encoder) 39int nv04_dac_output_offset(struct drm_encoder *encoder)
40{ 40{
41 struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb; 41 struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
42 int offset = 0; 42 int offset = 0;
43 43
44 if (dcb->or & (8 | OUTPUT_C)) 44 if (dcb->or & (8 | DCB_OUTPUT_C))
45 offset += 0x68; 45 offset += 0x68;
46 if (dcb->or & (8 | OUTPUT_B)) 46 if (dcb->or & (8 | DCB_OUTPUT_B))
47 offset += 0x2000; 47 offset += 0x2000;
48 48
49 return offset; 49 return offset;
@@ -222,14 +222,14 @@ uint32_t nv17_dac_sample_load(struct drm_encoder *encoder)
222{ 222{
223 struct drm_device *dev = encoder->dev; 223 struct drm_device *dev = encoder->dev;
224 struct drm_nouveau_private *dev_priv = dev->dev_private; 224 struct drm_nouveau_private *dev_priv = dev->dev_private;
225 struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb; 225 struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
226 uint32_t sample, testval, regoffset = nv04_dac_output_offset(encoder); 226 uint32_t sample, testval, regoffset = nv04_dac_output_offset(encoder);
227 uint32_t saved_powerctrl_2 = 0, saved_powerctrl_4 = 0, saved_routput, 227 uint32_t saved_powerctrl_2 = 0, saved_powerctrl_4 = 0, saved_routput,
228 saved_rtest_ctrl, saved_gpio0, saved_gpio1, temp, routput; 228 saved_rtest_ctrl, saved_gpio0, saved_gpio1, temp, routput;
229 int head; 229 int head;
230 230
231#define RGB_TEST_DATA(r, g, b) (r << 0 | g << 10 | b << 20) 231#define RGB_TEST_DATA(r, g, b) (r << 0 | g << 10 | b << 20)
232 if (dcb->type == OUTPUT_TV) { 232 if (dcb->type == DCB_OUTPUT_TV) {
233 testval = RGB_TEST_DATA(0xa0, 0xa0, 0xa0); 233 testval = RGB_TEST_DATA(0xa0, 0xa0, 0xa0);
234 234
235 if (dev_priv->vbios.tvdactestval) 235 if (dev_priv->vbios.tvdactestval)
@@ -256,8 +256,8 @@ uint32_t nv17_dac_sample_load(struct drm_encoder *encoder)
256 saved_gpio1 = nouveau_gpio_func_get(dev, DCB_GPIO_TVDAC1); 256 saved_gpio1 = nouveau_gpio_func_get(dev, DCB_GPIO_TVDAC1);
257 saved_gpio0 = nouveau_gpio_func_get(dev, DCB_GPIO_TVDAC0); 257 saved_gpio0 = nouveau_gpio_func_get(dev, DCB_GPIO_TVDAC0);
258 258
259 nouveau_gpio_func_set(dev, DCB_GPIO_TVDAC1, dcb->type == OUTPUT_TV); 259 nouveau_gpio_func_set(dev, DCB_GPIO_TVDAC1, dcb->type == DCB_OUTPUT_TV);
260 nouveau_gpio_func_set(dev, DCB_GPIO_TVDAC0, dcb->type == OUTPUT_TV); 260 nouveau_gpio_func_set(dev, DCB_GPIO_TVDAC0, dcb->type == DCB_OUTPUT_TV);
261 261
262 msleep(4); 262 msleep(4);
263 263
@@ -272,7 +272,7 @@ uint32_t nv17_dac_sample_load(struct drm_encoder *encoder)
272 routput = (saved_routput & 0xfffffece) | head << 8; 272 routput = (saved_routput & 0xfffffece) | head << 8;
273 273
274 if (dev_priv->card_type >= NV_40) { 274 if (dev_priv->card_type >= NV_40) {
275 if (dcb->type == OUTPUT_TV) 275 if (dcb->type == DCB_OUTPUT_TV)
276 routput |= 0x1a << 16; 276 routput |= 0x1a << 16;
277 else 277 else
278 routput &= ~(0x1a << 16); 278 routput &= ~(0x1a << 16);
@@ -317,7 +317,7 @@ static enum drm_connector_status
317nv17_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 317nv17_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
318{ 318{
319 struct drm_device *dev = encoder->dev; 319 struct drm_device *dev = encoder->dev;
320 struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb; 320 struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
321 321
322 if (nv04_dac_in_use(encoder)) 322 if (nv04_dac_in_use(encoder))
323 return connector_status_disconnected; 323 return connector_status_disconnected;
@@ -373,7 +373,7 @@ static void nv04_dac_mode_set(struct drm_encoder *encoder,
373 /* force any other vga encoders to bind to the other crtc */ 373 /* force any other vga encoders to bind to the other crtc */
374 list_for_each_entry(rebind, &dev->mode_config.encoder_list, head) { 374 list_for_each_entry(rebind, &dev->mode_config.encoder_list, head) {
375 if (rebind == encoder 375 if (rebind == encoder
376 || nouveau_encoder(rebind)->dcb->type != OUTPUT_ANALOG) 376 || nouveau_encoder(rebind)->dcb->type != DCB_OUTPUT_ANALOG)
377 continue; 377 continue;
378 378
379 dac_offset = nv04_dac_output_offset(rebind); 379 dac_offset = nv04_dac_output_offset(rebind);
@@ -408,7 +408,7 @@ void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable)
408{ 408{
409 struct drm_device *dev = encoder->dev; 409 struct drm_device *dev = encoder->dev;
410 struct drm_nouveau_private *dev_priv = dev->dev_private; 410 struct drm_nouveau_private *dev_priv = dev->dev_private;
411 struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb; 411 struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
412 412
413 if (nv_gf4_disp_arch(dev)) { 413 if (nv_gf4_disp_arch(dev)) {
414 uint32_t *dac_users = &dev_priv->dac_users[ffs(dcb->or) - 1]; 414 uint32_t *dac_users = &dev_priv->dac_users[ffs(dcb->or) - 1];
@@ -433,7 +433,7 @@ void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable)
433bool nv04_dac_in_use(struct drm_encoder *encoder) 433bool nv04_dac_in_use(struct drm_encoder *encoder)
434{ 434{
435 struct drm_nouveau_private *dev_priv = encoder->dev->dev_private; 435 struct drm_nouveau_private *dev_priv = encoder->dev->dev_private;
436 struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb; 436 struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
437 437
438 return nv_gf4_disp_arch(encoder->dev) && 438 return nv_gf4_disp_arch(encoder->dev) &&
439 (dev_priv->dac_users[ffs(dcb->or) - 1] & ~(1 << dcb->index)); 439 (dev_priv->dac_users[ffs(dcb->or) - 1] & ~(1 << dcb->index));
@@ -513,7 +513,7 @@ static const struct drm_encoder_funcs nv04_dac_funcs = {
513}; 513};
514 514
515int 515int
516nv04_dac_create(struct drm_connector *connector, struct dcb_entry *entry) 516nv04_dac_create(struct drm_connector *connector, struct dcb_output *entry)
517{ 517{
518 const struct drm_encoder_helper_funcs *helper; 518 const struct drm_encoder_helper_funcs *helper;
519 struct nouveau_encoder *nv_encoder = NULL; 519 struct nouveau_encoder *nv_encoder = NULL;
diff --git a/drivers/gpu/drm/nouveau/nv04_dfp.c b/drivers/gpu/drm/nouveau/nv04_dfp.c
index c9835b9bd63..823a1c5c075 100644
--- a/drivers/gpu/drm/nouveau/nv04_dfp.c
+++ b/drivers/gpu/drm/nouveau/nv04_dfp.c
@@ -49,20 +49,20 @@ static inline bool is_fpc_off(uint32_t fpc)
49 FP_TG_CONTROL_OFF); 49 FP_TG_CONTROL_OFF);
50} 50}
51 51
52int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent) 52int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_output *dcbent)
53{ 53{
54 /* special case of nv_read_tmds to find crtc associated with an output. 54 /* special case of nv_read_tmds to find crtc associated with an output.
55 * this does not give a correct answer for off-chip dvi, but there's no 55 * this does not give a correct answer for off-chip dvi, but there's no
56 * use for such an answer anyway 56 * use for such an answer anyway
57 */ 57 */
58 int ramdac = (dcbent->or & OUTPUT_C) >> 2; 58 int ramdac = (dcbent->or & DCB_OUTPUT_C) >> 2;
59 59
60 NVWriteRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_CONTROL, 60 NVWriteRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_CONTROL,
61 NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE | 0x4); 61 NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE | 0x4);
62 return ((NVReadRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_DATA) & 0x8) >> 3) ^ ramdac; 62 return ((NVReadRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_DATA) & 0x8) >> 3) ^ ramdac;
63} 63}
64 64
65void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 65void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_output *dcbent,
66 int head, bool dl) 66 int head, bool dl)
67{ 67{
68 /* The BIOS scripts don't do this for us, sadly 68 /* The BIOS scripts don't do this for us, sadly
@@ -72,13 +72,13 @@ void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
72 * (for VT restore etc.) 72 * (for VT restore etc.)
73 */ 73 */
74 74
75 int ramdac = (dcbent->or & OUTPUT_C) >> 2; 75 int ramdac = (dcbent->or & DCB_OUTPUT_C) >> 2;
76 uint8_t tmds04 = 0x80; 76 uint8_t tmds04 = 0x80;
77 77
78 if (head != ramdac) 78 if (head != ramdac)
79 tmds04 = 0x88; 79 tmds04 = 0x88;
80 80
81 if (dcbent->type == OUTPUT_LVDS) 81 if (dcbent->type == DCB_OUTPUT_LVDS)
82 tmds04 |= 0x01; 82 tmds04 |= 0x01;
83 83
84 nv_write_tmds(dev, dcbent->or, 0, 0x04, tmds04); 84 nv_write_tmds(dev, dcbent->or, 0, 0x04, tmds04);
@@ -151,10 +151,10 @@ void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode)
151static struct drm_encoder *get_tmds_slave(struct drm_encoder *encoder) 151static struct drm_encoder *get_tmds_slave(struct drm_encoder *encoder)
152{ 152{
153 struct drm_device *dev = encoder->dev; 153 struct drm_device *dev = encoder->dev;
154 struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb; 154 struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
155 struct drm_encoder *slave; 155 struct drm_encoder *slave;
156 156
157 if (dcb->type != OUTPUT_TMDS || dcb->location == DCB_LOC_ON_CHIP) 157 if (dcb->type != DCB_OUTPUT_TMDS || dcb->location == DCB_LOC_ON_CHIP)
158 return NULL; 158 return NULL;
159 159
160 /* Some BIOSes (e.g. the one in a Quadro FX1000) report several 160 /* Some BIOSes (e.g. the one in a Quadro FX1000) report several
@@ -168,9 +168,9 @@ static struct drm_encoder *get_tmds_slave(struct drm_encoder *encoder)
168 * let's do the same. 168 * let's do the same.
169 */ 169 */
170 list_for_each_entry(slave, &dev->mode_config.encoder_list, head) { 170 list_for_each_entry(slave, &dev->mode_config.encoder_list, head) {
171 struct dcb_entry *slave_dcb = nouveau_encoder(slave)->dcb; 171 struct dcb_output *slave_dcb = nouveau_encoder(slave)->dcb;
172 172
173 if (slave_dcb->type == OUTPUT_TMDS && get_slave_funcs(slave) && 173 if (slave_dcb->type == DCB_OUTPUT_TMDS && get_slave_funcs(slave) &&
174 slave_dcb->tmdsconf.slave_addr == dcb->tmdsconf.slave_addr) 174 slave_dcb->tmdsconf.slave_addr == dcb->tmdsconf.slave_addr)
175 return slave; 175 return slave;
176 } 176 }
@@ -204,7 +204,7 @@ static void nv04_dfp_prepare_sel_clk(struct drm_device *dev,
204{ 204{
205 struct drm_nouveau_private *dev_priv = dev->dev_private; 205 struct drm_nouveau_private *dev_priv = dev->dev_private;
206 struct nv04_mode_state *state = &dev_priv->mode_reg; 206 struct nv04_mode_state *state = &dev_priv->mode_reg;
207 uint32_t bits1618 = nv_encoder->dcb->or & OUTPUT_A ? 0x10000 : 0x40000; 207 uint32_t bits1618 = nv_encoder->dcb->or & DCB_OUTPUT_A ? 0x10000 : 0x40000;
208 208
209 if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP) 209 if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP)
210 return; 210 return;
@@ -233,7 +233,7 @@ static void nv04_dfp_prepare_sel_clk(struct drm_device *dev,
233 * and which bit-pair to use, is unclear on nv40 (for earlier cards, the fp table 233 * and which bit-pair to use, is unclear on nv40 (for earlier cards, the fp table
234 * entry has the necessary info) 234 * entry has the necessary info)
235 */ 235 */
236 if (nv_encoder->dcb->type == OUTPUT_LVDS && dev_priv->saved_reg.sel_clk & 0xf0) { 236 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS && dev_priv->saved_reg.sel_clk & 0xf0) {
237 int shift = (dev_priv->saved_reg.sel_clk & 0x50) ? 0 : 1; 237 int shift = (dev_priv->saved_reg.sel_clk & 0x50) ? 0 : 1;
238 238
239 state->sel_clk &= ~0xf0; 239 state->sel_clk &= ~0xf0;
@@ -263,7 +263,7 @@ static void nv04_dfp_prepare(struct drm_encoder *encoder)
263 *cr_lcd |= head ? 0x0 : 0x8; 263 *cr_lcd |= head ? 0x0 : 0x8;
264 else { 264 else {
265 *cr_lcd |= (nv_encoder->dcb->or << 4) & 0x30; 265 *cr_lcd |= (nv_encoder->dcb->or << 4) & 0x30;
266 if (nv_encoder->dcb->type == OUTPUT_LVDS) 266 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS)
267 *cr_lcd |= 0x30; 267 *cr_lcd |= 0x30;
268 if ((*cr_lcd & 0x30) == (*cr_lcd_oth & 0x30)) { 268 if ((*cr_lcd & 0x30) == (*cr_lcd_oth & 0x30)) {
269 /* avoid being connected to both crtcs */ 269 /* avoid being connected to both crtcs */
@@ -340,7 +340,7 @@ static void nv04_dfp_mode_set(struct drm_encoder *encoder,
340 if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP && 340 if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP &&
341 output_mode->clock > 165000) 341 output_mode->clock > 165000)
342 regp->fp_control |= (2 << 24); 342 regp->fp_control |= (2 << 24);
343 if (nv_encoder->dcb->type == OUTPUT_LVDS) { 343 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS) {
344 bool duallink = false, dummy; 344 bool duallink = false, dummy;
345 if (nv_connector->edid && 345 if (nv_connector->edid &&
346 nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) { 346 nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
@@ -448,13 +448,13 @@ static void nv04_dfp_commit(struct drm_encoder *encoder)
448 struct drm_encoder_helper_funcs *helper = encoder->helper_private; 448 struct drm_encoder_helper_funcs *helper = encoder->helper_private;
449 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 449 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
450 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 450 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
451 struct dcb_entry *dcbe = nv_encoder->dcb; 451 struct dcb_output *dcbe = nv_encoder->dcb;
452 int head = nouveau_crtc(encoder->crtc)->index; 452 int head = nouveau_crtc(encoder->crtc)->index;
453 struct drm_encoder *slave_encoder; 453 struct drm_encoder *slave_encoder;
454 454
455 if (dcbe->type == OUTPUT_TMDS) 455 if (dcbe->type == DCB_OUTPUT_TMDS)
456 run_tmds_table(dev, dcbe, head, nv_encoder->mode.clock); 456 run_tmds_table(dev, dcbe, head, nv_encoder->mode.clock);
457 else if (dcbe->type == OUTPUT_LVDS) 457 else if (dcbe->type == DCB_OUTPUT_LVDS)
458 call_lvds_script(dev, dcbe, head, LVDS_RESET, nv_encoder->mode.clock); 458 call_lvds_script(dev, dcbe, head, LVDS_RESET, nv_encoder->mode.clock);
459 459
460 /* update fp_control state for any changes made by scripts, 460 /* update fp_control state for any changes made by scripts,
@@ -588,7 +588,7 @@ static void nv04_dfp_restore(struct drm_encoder *encoder)
588 struct drm_nouveau_private *dev_priv = dev->dev_private; 588 struct drm_nouveau_private *dev_priv = dev->dev_private;
589 int head = nv_encoder->restore.head; 589 int head = nv_encoder->restore.head;
590 590
591 if (nv_encoder->dcb->type == OUTPUT_LVDS) { 591 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS) {
592 struct nouveau_connector *connector = 592 struct nouveau_connector *connector =
593 nouveau_encoder_connector_get(nv_encoder); 593 nouveau_encoder_connector_get(nv_encoder);
594 594
@@ -597,7 +597,7 @@ static void nv04_dfp_restore(struct drm_encoder *encoder)
597 LVDS_PANEL_ON, 597 LVDS_PANEL_ON,
598 connector->native_mode->clock); 598 connector->native_mode->clock);
599 599
600 } else if (nv_encoder->dcb->type == OUTPUT_TMDS) { 600 } else if (nv_encoder->dcb->type == DCB_OUTPUT_TMDS) {
601 int clock = nouveau_hw_pllvals_to_clk 601 int clock = nouveau_hw_pllvals_to_clk
602 (&dev_priv->saved_reg.crtc_reg[head].pllvals); 602 (&dev_priv->saved_reg.crtc_reg[head].pllvals);
603 603
@@ -623,7 +623,7 @@ static void nv04_dfp_destroy(struct drm_encoder *encoder)
623static void nv04_tmds_slave_init(struct drm_encoder *encoder) 623static void nv04_tmds_slave_init(struct drm_encoder *encoder)
624{ 624{
625 struct drm_device *dev = encoder->dev; 625 struct drm_device *dev = encoder->dev;
626 struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb; 626 struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
627 struct nouveau_i2c_port *i2c = nouveau_i2c_find(dev, 2); 627 struct nouveau_i2c_port *i2c = nouveau_i2c_find(dev, 2);
628 struct i2c_board_info info[] = { 628 struct i2c_board_info info[] = {
629 { 629 {
@@ -676,7 +676,7 @@ static const struct drm_encoder_funcs nv04_dfp_funcs = {
676}; 676};
677 677
678int 678int
679nv04_dfp_create(struct drm_connector *connector, struct dcb_entry *entry) 679nv04_dfp_create(struct drm_connector *connector, struct dcb_output *entry)
680{ 680{
681 const struct drm_encoder_helper_funcs *helper; 681 const struct drm_encoder_helper_funcs *helper;
682 struct nouveau_encoder *nv_encoder = NULL; 682 struct nouveau_encoder *nv_encoder = NULL;
@@ -684,11 +684,11 @@ nv04_dfp_create(struct drm_connector *connector, struct dcb_entry *entry)
684 int type; 684 int type;
685 685
686 switch (entry->type) { 686 switch (entry->type) {
687 case OUTPUT_TMDS: 687 case DCB_OUTPUT_TMDS:
688 type = DRM_MODE_ENCODER_TMDS; 688 type = DRM_MODE_ENCODER_TMDS;
689 helper = &nv04_tmds_helper_funcs; 689 helper = &nv04_tmds_helper_funcs;
690 break; 690 break;
691 case OUTPUT_LVDS: 691 case DCB_OUTPUT_LVDS:
692 type = DRM_MODE_ENCODER_LVDS; 692 type = DRM_MODE_ENCODER_LVDS;
693 helper = &nv04_lvds_helper_funcs; 693 helper = &nv04_lvds_helper_funcs;
694 break; 694 break;
@@ -711,7 +711,7 @@ nv04_dfp_create(struct drm_connector *connector, struct dcb_entry *entry)
711 encoder->possible_crtcs = entry->heads; 711 encoder->possible_crtcs = entry->heads;
712 encoder->possible_clones = 0; 712 encoder->possible_clones = 0;
713 713
714 if (entry->type == OUTPUT_TMDS && 714 if (entry->type == DCB_OUTPUT_TMDS &&
715 entry->location != DCB_LOC_ON_CHIP) 715 entry->location != DCB_LOC_ON_CHIP)
716 nv04_tmds_slave_init(encoder); 716 nv04_tmds_slave_init(encoder);
717 717
diff --git a/drivers/gpu/drm/nouveau/nv04_display.c b/drivers/gpu/drm/nouveau/nv04_display.c
index 44488e3a257..2b7d23e8f27 100644
--- a/drivers/gpu/drm/nouveau/nv04_display.c
+++ b/drivers/gpu/drm/nouveau/nv04_display.c
@@ -35,69 +35,9 @@
35static void nv04_vblank_crtc0_isr(struct drm_device *); 35static void nv04_vblank_crtc0_isr(struct drm_device *);
36static void nv04_vblank_crtc1_isr(struct drm_device *); 36static void nv04_vblank_crtc1_isr(struct drm_device *);
37 37
38static void
39nv04_display_store_initial_head_owner(struct drm_device *dev)
40{
41 struct drm_nouveau_private *dev_priv = dev->dev_private;
42
43 if (dev_priv->chipset != 0x11) {
44 dev_priv->crtc_owner = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_44);
45 return;
46 }
47
48 /* reading CR44 is broken on nv11, so we attempt to infer it */
49 if (nvReadMC(dev, NV_PBUS_DEBUG_1) & (1 << 28)) /* heads tied, restore both */
50 dev_priv->crtc_owner = 0x4;
51 else {
52 uint8_t slaved_on_A, slaved_on_B;
53 bool tvA = false;
54 bool tvB = false;
55
56 slaved_on_B = NVReadVgaCrtc(dev, 1, NV_CIO_CRE_PIXEL_INDEX) &
57 0x80;
58 if (slaved_on_B)
59 tvB = !(NVReadVgaCrtc(dev, 1, NV_CIO_CRE_LCD__INDEX) &
60 MASK(NV_CIO_CRE_LCD_LCD_SELECT));
61
62 slaved_on_A = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_PIXEL_INDEX) &
63 0x80;
64 if (slaved_on_A)
65 tvA = !(NVReadVgaCrtc(dev, 0, NV_CIO_CRE_LCD__INDEX) &
66 MASK(NV_CIO_CRE_LCD_LCD_SELECT));
67
68 if (slaved_on_A && !tvA)
69 dev_priv->crtc_owner = 0x0;
70 else if (slaved_on_B && !tvB)
71 dev_priv->crtc_owner = 0x3;
72 else if (slaved_on_A)
73 dev_priv->crtc_owner = 0x0;
74 else if (slaved_on_B)
75 dev_priv->crtc_owner = 0x3;
76 else
77 dev_priv->crtc_owner = 0x0;
78 }
79}
80
81int 38int
82nv04_display_early_init(struct drm_device *dev) 39nv04_display_early_init(struct drm_device *dev)
83{ 40{
84 /* Make the I2C buses accessible. */
85 if (!nv_gf4_disp_arch(dev)) {
86 uint32_t pmc_enable = nv_rd32(dev, NV03_PMC_ENABLE);
87
88 if (!(pmc_enable & 1))
89 nv_wr32(dev, NV03_PMC_ENABLE, pmc_enable | 1);
90 }
91
92 /* Unlock the VGA CRTCs. */
93 NVLockVgaCrtcs(dev, false);
94
95 /* Make sure the CRTCs aren't in slaved mode. */
96 if (nv_two_heads(dev)) {
97 nv04_display_store_initial_head_owner(dev);
98 NVSetOwner(dev, 0);
99 }
100
101 /* ensure vblank interrupts are off, they can't be enabled until 41 /* ensure vblank interrupts are off, they can't be enabled until
102 * drm_vblank has been initialised 42 * drm_vblank has been initialised
103 */ 43 */
@@ -111,12 +51,6 @@ nv04_display_early_init(struct drm_device *dev)
111void 51void
112nv04_display_late_takedown(struct drm_device *dev) 52nv04_display_late_takedown(struct drm_device *dev)
113{ 53{
114 struct drm_nouveau_private *dev_priv = dev->dev_private;
115
116 if (nv_two_heads(dev))
117 NVSetOwner(dev, dev_priv->crtc_owner);
118
119 NVLockVgaCrtcs(dev, true);
120} 54}
121 55
122int 56int
@@ -138,21 +72,21 @@ nv04_display_create(struct drm_device *dev)
138 nv04_crtc_create(dev, 1); 72 nv04_crtc_create(dev, 1);
139 73
140 for (i = 0; i < dcb->entries; i++) { 74 for (i = 0; i < dcb->entries; i++) {
141 struct dcb_entry *dcbent = &dcb->entry[i]; 75 struct dcb_output *dcbent = &dcb->entry[i];
142 76
143 connector = nouveau_connector_create(dev, dcbent->connector); 77 connector = nouveau_connector_create(dev, dcbent->connector);
144 if (IS_ERR(connector)) 78 if (IS_ERR(connector))
145 continue; 79 continue;
146 80
147 switch (dcbent->type) { 81 switch (dcbent->type) {
148 case OUTPUT_ANALOG: 82 case DCB_OUTPUT_ANALOG:
149 ret = nv04_dac_create(connector, dcbent); 83 ret = nv04_dac_create(connector, dcbent);
150 break; 84 break;
151 case OUTPUT_LVDS: 85 case DCB_OUTPUT_LVDS:
152 case OUTPUT_TMDS: 86 case DCB_OUTPUT_TMDS:
153 ret = nv04_dfp_create(connector, dcbent); 87 ret = nv04_dfp_create(connector, dcbent);
154 break; 88 break;
155 case OUTPUT_TV: 89 case DCB_OUTPUT_TV:
156 if (dcbent->location == DCB_LOC_ON_CHIP) 90 if (dcbent->location == DCB_LOC_ON_CHIP)
157 ret = nv17_tv_create(connector, dcbent); 91 ret = nv17_tv_create(connector, dcbent);
158 else 92 else
diff --git a/drivers/gpu/drm/nouveau/nv04_tv.c b/drivers/gpu/drm/nouveau/nv04_tv.c
index 3d7dd22879b..5927391373e 100644
--- a/drivers/gpu/drm/nouveau/nv04_tv.c
+++ b/drivers/gpu/drm/nouveau/nv04_tv.c
@@ -181,7 +181,7 @@ static const struct drm_encoder_funcs nv04_tv_funcs = {
181}; 181};
182 182
183int 183int
184nv04_tv_create(struct drm_connector *connector, struct dcb_entry *entry) 184nv04_tv_create(struct drm_connector *connector, struct dcb_output *entry)
185{ 185{
186 struct nouveau_encoder *nv_encoder; 186 struct nouveau_encoder *nv_encoder;
187 struct drm_encoder *encoder; 187 struct drm_encoder *encoder;
diff --git a/drivers/gpu/drm/nouveau/nv17_tv.c b/drivers/gpu/drm/nouveau/nv17_tv.c
index a66a348d7f2..54ff394e005 100644
--- a/drivers/gpu/drm/nouveau/nv17_tv.c
+++ b/drivers/gpu/drm/nouveau/nv17_tv.c
@@ -144,7 +144,7 @@ nv17_tv_detect(struct drm_encoder *encoder, struct drm_connector *connector)
144 struct drm_nouveau_private *dev_priv = dev->dev_private; 144 struct drm_nouveau_private *dev_priv = dev->dev_private;
145 struct drm_mode_config *conf = &dev->mode_config; 145 struct drm_mode_config *conf = &dev->mode_config;
146 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder); 146 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
147 struct dcb_entry *dcb = tv_enc->base.dcb; 147 struct dcb_output *dcb = tv_enc->base.dcb;
148 bool reliable = get_tv_detect_quirks(dev, &tv_enc->pin_mask); 148 bool reliable = get_tv_detect_quirks(dev, &tv_enc->pin_mask);
149 149
150 if (nv04_dac_in_use(encoder)) 150 if (nv04_dac_in_use(encoder))
@@ -411,10 +411,10 @@ static void nv17_tv_prepare(struct drm_encoder *encoder)
411 struct drm_encoder *enc; 411 struct drm_encoder *enc;
412 412
413 list_for_each_entry(enc, &dev->mode_config.encoder_list, head) { 413 list_for_each_entry(enc, &dev->mode_config.encoder_list, head) {
414 struct dcb_entry *dcb = nouveau_encoder(enc)->dcb; 414 struct dcb_output *dcb = nouveau_encoder(enc)->dcb;
415 415
416 if ((dcb->type == OUTPUT_TMDS || 416 if ((dcb->type == DCB_OUTPUT_TMDS ||
417 dcb->type == OUTPUT_LVDS) && 417 dcb->type == DCB_OUTPUT_LVDS) &&
418 !enc->crtc && 418 !enc->crtc &&
419 nv04_dfp_get_bound_head(dev, dcb) == head) { 419 nv04_dfp_get_bound_head(dev, dcb) == head) {
420 nv04_dfp_bind_head(dev, dcb, head ^ 1, 420 nv04_dfp_bind_head(dev, dcb, head ^ 1,
@@ -633,7 +633,7 @@ static int nv17_tv_create_resources(struct drm_encoder *encoder,
633 struct drm_device *dev = encoder->dev; 633 struct drm_device *dev = encoder->dev;
634 struct drm_mode_config *conf = &dev->mode_config; 634 struct drm_mode_config *conf = &dev->mode_config;
635 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder); 635 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
636 struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb; 636 struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
637 int num_tv_norms = dcb->tvconf.has_component_output ? NUM_TV_NORMS : 637 int num_tv_norms = dcb->tvconf.has_component_output ? NUM_TV_NORMS :
638 NUM_LD_TV_NORMS; 638 NUM_LD_TV_NORMS;
639 int i; 639 int i;
@@ -789,7 +789,7 @@ static struct drm_encoder_funcs nv17_tv_funcs = {
789}; 789};
790 790
791int 791int
792nv17_tv_create(struct drm_connector *connector, struct dcb_entry *entry) 792nv17_tv_create(struct drm_connector *connector, struct dcb_output *entry)
793{ 793{
794 struct drm_device *dev = connector->dev; 794 struct drm_device *dev = connector->dev;
795 struct drm_encoder *encoder; 795 struct drm_encoder *encoder;
diff --git a/drivers/gpu/drm/nouveau/nv50_dac.c b/drivers/gpu/drm/nouveau/nv50_dac.c
index 2c36a6b92c5..dd3b8f2a396 100644
--- a/drivers/gpu/drm/nouveau/nv50_dac.c
+++ b/drivers/gpu/drm/nouveau/nv50_dac.c
@@ -224,10 +224,10 @@ nv50_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
224 mode_ctl |= NV50_EVO_DAC_MODE_CTRL_CRTC0; 224 mode_ctl |= NV50_EVO_DAC_MODE_CTRL_CRTC0;
225 225
226 /* Lacking a working tv-out, this is not a 100% sure. */ 226 /* Lacking a working tv-out, this is not a 100% sure. */
227 if (nv_encoder->dcb->type == OUTPUT_ANALOG) 227 if (nv_encoder->dcb->type == DCB_OUTPUT_ANALOG)
228 mode_ctl |= 0x40; 228 mode_ctl |= 0x40;
229 else 229 else
230 if (nv_encoder->dcb->type == OUTPUT_TV) 230 if (nv_encoder->dcb->type == DCB_OUTPUT_TV)
231 mode_ctl |= 0x100; 231 mode_ctl |= 0x100;
232 232
233 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) 233 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
@@ -286,7 +286,7 @@ static const struct drm_encoder_funcs nv50_dac_encoder_funcs = {
286}; 286};
287 287
288int 288int
289nv50_dac_create(struct drm_connector *connector, struct dcb_entry *entry) 289nv50_dac_create(struct drm_connector *connector, struct dcb_output *entry)
290{ 290{
291 struct nouveau_encoder *nv_encoder; 291 struct nouveau_encoder *nv_encoder;
292 struct drm_encoder *encoder; 292 struct drm_encoder *encoder;
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index 66abff11d1b..e7cd8216d11 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -74,53 +74,9 @@ nv50_display_active_crtcs(struct drm_device *dev)
74 return mask & 3; 74 return mask & 3;
75} 75}
76 76
77static int
78evo_icmd(struct drm_device *dev, int ch, u32 mthd, u32 data)
79{
80 int ret = 0;
81 nv_mask(dev, 0x610300 + (ch * 0x08), 0x00000001, 0x00000001);
82 nv_wr32(dev, 0x610304 + (ch * 0x08), data);
83 nv_wr32(dev, 0x610300 + (ch * 0x08), 0x80000001 | mthd);
84 if (!nv_wait(dev, 0x610300 + (ch * 0x08), 0x80000000, 0x00000000))
85 ret = -EBUSY;
86 if (ret || (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO))
87 NV_INFO(dev, "EvoPIO: %d 0x%04x 0x%08x\n", ch, mthd, data);
88 nv_mask(dev, 0x610300 + (ch * 0x08), 0x00000001, 0x00000000);
89 return ret;
90}
91
92int 77int
93nv50_display_early_init(struct drm_device *dev) 78nv50_display_early_init(struct drm_device *dev)
94{ 79{
95 u32 ctrl = nv_rd32(dev, 0x610200);
96 int i;
97
98 /* check if master evo channel is already active, a good a sign as any
99 * that the display engine is in a weird state (hibernate/kexec), if
100 * it is, do our best to reset the display engine...
101 */
102 if ((ctrl & 0x00000003) == 0x00000003) {
103 NV_INFO(dev, "PDISP: EVO(0) 0x%08x, resetting...\n", ctrl);
104
105 /* deactivate both heads first, PDISP will disappear forever
106 * (well, until you power cycle) on some boards as soon as
107 * PMC_ENABLE is hit unless they are..
108 */
109 for (i = 0; i < 2; i++) {
110 evo_icmd(dev, 0, 0x0880 + (i * 0x400), 0x05000000);
111 evo_icmd(dev, 0, 0x089c + (i * 0x400), 0);
112 evo_icmd(dev, 0, 0x0840 + (i * 0x400), 0);
113 evo_icmd(dev, 0, 0x0844 + (i * 0x400), 0);
114 evo_icmd(dev, 0, 0x085c + (i * 0x400), 0);
115 evo_icmd(dev, 0, 0x0874 + (i * 0x400), 0);
116 }
117 evo_icmd(dev, 0, 0x0080, 0);
118
119 /* reset PDISP */
120 nv_mask(dev, 0x000200, 0x40000000, 0x00000000);
121 nv_mask(dev, 0x000200, 0x40000000, 0x40000000);
122 }
123
124 return 0; 80 return 0;
125} 81}
126 82
@@ -367,7 +323,7 @@ nv50_display_create(struct drm_device *dev)
367 323
368 /* We setup the encoders from the BIOS table */ 324 /* We setup the encoders from the BIOS table */
369 for (i = 0 ; i < dcb->entries; i++) { 325 for (i = 0 ; i < dcb->entries; i++) {
370 struct dcb_entry *entry = &dcb->entry[i]; 326 struct dcb_output *entry = &dcb->entry[i];
371 327
372 if (entry->location != DCB_LOC_ON_CHIP) { 328 if (entry->location != DCB_LOC_ON_CHIP) {
373 NV_WARN(dev, "Off-chip encoder %d/%d unsupported\n", 329 NV_WARN(dev, "Off-chip encoder %d/%d unsupported\n",
@@ -380,12 +336,12 @@ nv50_display_create(struct drm_device *dev)
380 continue; 336 continue;
381 337
382 switch (entry->type) { 338 switch (entry->type) {
383 case OUTPUT_TMDS: 339 case DCB_OUTPUT_TMDS:
384 case OUTPUT_LVDS: 340 case DCB_OUTPUT_LVDS:
385 case OUTPUT_DP: 341 case DCB_OUTPUT_DP:
386 nv50_sor_create(connector, entry); 342 nv50_sor_create(connector, entry);
387 break; 343 break;
388 case OUTPUT_ANALOG: 344 case DCB_OUTPUT_ANALOG:
389 nv50_dac_create(connector, entry); 345 nv50_dac_create(connector, entry);
390 break; 346 break;
391 default: 347 default:
@@ -555,7 +511,7 @@ nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
555} 511}
556 512
557static u16 513static u16
558nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcb, 514nv50_display_script_select(struct drm_device *dev, struct dcb_output *dcb,
559 u32 mc, int pxclk) 515 u32 mc, int pxclk)
560{ 516{
561 struct drm_nouveau_private *dev_priv = dev->dev_private; 517 struct drm_nouveau_private *dev_priv = dev->dev_private;
@@ -576,7 +532,7 @@ nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcb,
576 532
577 or = ffs(dcb->or) - 1; 533 or = ffs(dcb->or) - 1;
578 switch (dcb->type) { 534 switch (dcb->type) {
579 case OUTPUT_LVDS: 535 case DCB_OUTPUT_LVDS:
580 script = (mc >> 8) & 0xf; 536 script = (mc >> 8) & 0xf;
581 if (bios->fp_no_ddc) { 537 if (bios->fp_no_ddc) {
582 if (bios->fp.dual_link) 538 if (bios->fp.dual_link)
@@ -617,7 +573,7 @@ nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcb,
617 script = nouveau_uscript_lvds; 573 script = nouveau_uscript_lvds;
618 } 574 }
619 break; 575 break;
620 case OUTPUT_TMDS: 576 case DCB_OUTPUT_TMDS:
621 script = (mc >> 8) & 0xf; 577 script = (mc >> 8) & 0xf;
622 if (pxclk >= 165000) 578 if (pxclk >= 165000)
623 script |= 0x0100; 579 script |= 0x0100;
@@ -629,10 +585,10 @@ nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcb,
629 script = nouveau_uscript_tmds; 585 script = nouveau_uscript_tmds;
630 } 586 }
631 break; 587 break;
632 case OUTPUT_DP: 588 case DCB_OUTPUT_DP:
633 script = (mc >> 8) & 0xf; 589 script = (mc >> 8) & 0xf;
634 break; 590 break;
635 case OUTPUT_ANALOG: 591 case DCB_OUTPUT_ANALOG:
636 script = 0xff; 592 script = 0xff;
637 break; 593 break;
638 default: 594 default:
@@ -691,7 +647,7 @@ nv50_display_unk10_handler(struct drm_device *dev)
691 struct drm_nouveau_private *dev_priv = dev->dev_private; 647 struct drm_nouveau_private *dev_priv = dev->dev_private;
692 struct nv50_display *disp = nv50_display(dev); 648 struct nv50_display *disp = nv50_display(dev);
693 u32 unk30 = nv_rd32(dev, 0x610030), mc; 649 u32 unk30 = nv_rd32(dev, 0x610030), mc;
694 int i, crtc, or = 0, type = OUTPUT_ANY; 650 int i, crtc, or = 0, type = DCB_OUTPUT_ANY;
695 651
696 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30); 652 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
697 disp->irq.dcb = NULL; 653 disp->irq.dcb = NULL;
@@ -711,15 +667,15 @@ nv50_display_unk10_handler(struct drm_device *dev)
711 goto ack; 667 goto ack;
712 668
713 /* Find which encoder was connected to the CRTC */ 669 /* Find which encoder was connected to the CRTC */
714 for (i = 0; type == OUTPUT_ANY && i < 3; i++) { 670 for (i = 0; type == DCB_OUTPUT_ANY && i < 3; i++) {
715 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_C(i)); 671 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_C(i));
716 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc); 672 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
717 if (!(mc & (1 << crtc))) 673 if (!(mc & (1 << crtc)))
718 continue; 674 continue;
719 675
720 switch ((mc & 0x00000f00) >> 8) { 676 switch ((mc & 0x00000f00) >> 8) {
721 case 0: type = OUTPUT_ANALOG; break; 677 case 0: type = DCB_OUTPUT_ANALOG; break;
722 case 1: type = OUTPUT_TV; break; 678 case 1: type = DCB_OUTPUT_TV; break;
723 default: 679 default:
724 NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc); 680 NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
725 goto ack; 681 goto ack;
@@ -728,7 +684,7 @@ nv50_display_unk10_handler(struct drm_device *dev)
728 or = i; 684 or = i;
729 } 685 }
730 686
731 for (i = 0; type == OUTPUT_ANY && i < nv50_sor_nr(dev); i++) { 687 for (i = 0; type == DCB_OUTPUT_ANY && i < nv50_sor_nr(dev); i++) {
732 if (dev_priv->chipset < 0x90 || 688 if (dev_priv->chipset < 0x90 ||
733 dev_priv->chipset == 0x92 || 689 dev_priv->chipset == 0x92 ||
734 dev_priv->chipset == 0xa0) 690 dev_priv->chipset == 0xa0)
@@ -741,12 +697,12 @@ nv50_display_unk10_handler(struct drm_device *dev)
741 continue; 697 continue;
742 698
743 switch ((mc & 0x00000f00) >> 8) { 699 switch ((mc & 0x00000f00) >> 8) {
744 case 0: type = OUTPUT_LVDS; break; 700 case 0: type = DCB_OUTPUT_LVDS; break;
745 case 1: type = OUTPUT_TMDS; break; 701 case 1: type = DCB_OUTPUT_TMDS; break;
746 case 2: type = OUTPUT_TMDS; break; 702 case 2: type = DCB_OUTPUT_TMDS; break;
747 case 5: type = OUTPUT_TMDS; break; 703 case 5: type = DCB_OUTPUT_TMDS; break;
748 case 8: type = OUTPUT_DP; break; 704 case 8: type = DCB_OUTPUT_DP; break;
749 case 9: type = OUTPUT_DP; break; 705 case 9: type = DCB_OUTPUT_DP; break;
750 default: 706 default:
751 NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc); 707 NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
752 goto ack; 708 goto ack;
@@ -756,12 +712,12 @@ nv50_display_unk10_handler(struct drm_device *dev)
756 } 712 }
757 713
758 /* There was no encoder to disable */ 714 /* There was no encoder to disable */
759 if (type == OUTPUT_ANY) 715 if (type == DCB_OUTPUT_ANY)
760 goto ack; 716 goto ack;
761 717
762 /* Disable the encoder */ 718 /* Disable the encoder */
763 for (i = 0; i < dev_priv->vbios.dcb.entries; i++) { 719 for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
764 struct dcb_entry *dcb = &dev_priv->vbios.dcb.entry[i]; 720 struct dcb_output *dcb = &dev_priv->vbios.dcb.entry[i];
765 721
766 if (dcb->type == type && (dcb->or & (1 << or))) { 722 if (dcb->type == type && (dcb->or & (1 << or))) {
767 nouveau_bios_run_display_table(dev, 0, -1, dcb, -1); 723 nouveau_bios_run_display_table(dev, 0, -1, dcb, -1);
@@ -782,8 +738,8 @@ nv50_display_unk20_handler(struct drm_device *dev)
782 struct drm_nouveau_private *dev_priv = dev->dev_private; 738 struct drm_nouveau_private *dev_priv = dev->dev_private;
783 struct nv50_display *disp = nv50_display(dev); 739 struct nv50_display *disp = nv50_display(dev);
784 u32 unk30 = nv_rd32(dev, 0x610030), tmp, pclk, script, mc = 0; 740 u32 unk30 = nv_rd32(dev, 0x610030), tmp, pclk, script, mc = 0;
785 struct dcb_entry *dcb; 741 struct dcb_output *dcb;
786 int i, crtc, or = 0, type = OUTPUT_ANY; 742 int i, crtc, or = 0, type = DCB_OUTPUT_ANY;
787 743
788 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30); 744 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
789 dcb = disp->irq.dcb; 745 dcb = disp->irq.dcb;
@@ -812,15 +768,15 @@ nv50_display_unk20_handler(struct drm_device *dev)
812 pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK)) & 0x003fffff; 768 pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK)) & 0x003fffff;
813 769
814 /* Find which encoder is connected to the CRTC */ 770 /* Find which encoder is connected to the CRTC */
815 for (i = 0; type == OUTPUT_ANY && i < 3; i++) { 771 for (i = 0; type == DCB_OUTPUT_ANY && i < 3; i++) {
816 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_P(i)); 772 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_P(i));
817 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc); 773 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
818 if (!(mc & (1 << crtc))) 774 if (!(mc & (1 << crtc)))
819 continue; 775 continue;
820 776
821 switch ((mc & 0x00000f00) >> 8) { 777 switch ((mc & 0x00000f00) >> 8) {
822 case 0: type = OUTPUT_ANALOG; break; 778 case 0: type = DCB_OUTPUT_ANALOG; break;
823 case 1: type = OUTPUT_TV; break; 779 case 1: type = DCB_OUTPUT_TV; break;
824 default: 780 default:
825 NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc); 781 NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
826 goto ack; 782 goto ack;
@@ -829,7 +785,7 @@ nv50_display_unk20_handler(struct drm_device *dev)
829 or = i; 785 or = i;
830 } 786 }
831 787
832 for (i = 0; type == OUTPUT_ANY && i < nv50_sor_nr(dev); i++) { 788 for (i = 0; type == DCB_OUTPUT_ANY && i < nv50_sor_nr(dev); i++) {
833 if (dev_priv->chipset < 0x90 || 789 if (dev_priv->chipset < 0x90 ||
834 dev_priv->chipset == 0x92 || 790 dev_priv->chipset == 0x92 ||
835 dev_priv->chipset == 0xa0) 791 dev_priv->chipset == 0xa0)
@@ -842,12 +798,12 @@ nv50_display_unk20_handler(struct drm_device *dev)
842 continue; 798 continue;
843 799
844 switch ((mc & 0x00000f00) >> 8) { 800 switch ((mc & 0x00000f00) >> 8) {
845 case 0: type = OUTPUT_LVDS; break; 801 case 0: type = DCB_OUTPUT_LVDS; break;
846 case 1: type = OUTPUT_TMDS; break; 802 case 1: type = DCB_OUTPUT_TMDS; break;
847 case 2: type = OUTPUT_TMDS; break; 803 case 2: type = DCB_OUTPUT_TMDS; break;
848 case 5: type = OUTPUT_TMDS; break; 804 case 5: type = DCB_OUTPUT_TMDS; break;
849 case 8: type = OUTPUT_DP; break; 805 case 8: type = DCB_OUTPUT_DP; break;
850 case 9: type = OUTPUT_DP; break; 806 case 9: type = DCB_OUTPUT_DP; break;
851 default: 807 default:
852 NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc); 808 NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
853 goto ack; 809 goto ack;
@@ -856,7 +812,7 @@ nv50_display_unk20_handler(struct drm_device *dev)
856 or = i; 812 or = i;
857 } 813 }
858 814
859 if (type == OUTPUT_ANY) 815 if (type == DCB_OUTPUT_ANY)
860 goto ack; 816 goto ack;
861 817
862 /* Enable the encoder */ 818 /* Enable the encoder */
@@ -874,7 +830,7 @@ nv50_display_unk20_handler(struct drm_device *dev)
874 script = nv50_display_script_select(dev, dcb, mc, pclk); 830 script = nv50_display_script_select(dev, dcb, mc, pclk);
875 nouveau_bios_run_display_table(dev, script, pclk, dcb, -1); 831 nouveau_bios_run_display_table(dev, script, pclk, dcb, -1);
876 832
877 if (type == OUTPUT_DP) { 833 if (type == DCB_OUTPUT_DP) {
878 int link = !(dcb->dpconf.sor.link & 1); 834 int link = !(dcb->dpconf.sor.link & 1);
879 if ((mc & 0x000f0000) == 0x00020000) 835 if ((mc & 0x000f0000) == 0x00020000)
880 nv50_sor_dp_calc_tu(dev, or, link, pclk, 18); 836 nv50_sor_dp_calc_tu(dev, or, link, pclk, 18);
@@ -882,7 +838,7 @@ nv50_display_unk20_handler(struct drm_device *dev)
882 nv50_sor_dp_calc_tu(dev, or, link, pclk, 24); 838 nv50_sor_dp_calc_tu(dev, or, link, pclk, 24);
883 } 839 }
884 840
885 if (dcb->type != OUTPUT_ANALOG) { 841 if (dcb->type != DCB_OUTPUT_ANALOG) {
886 tmp = nv_rd32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or)); 842 tmp = nv_rd32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or));
887 tmp &= ~0x00000f0f; 843 tmp &= ~0x00000f0f;
888 if (script & 0x0100) 844 if (script & 0x0100)
@@ -910,19 +866,19 @@ ack:
910 * programmed for DisplayPort. 866 * programmed for DisplayPort.
911 */ 867 */
912static void 868static void
913nv50_display_unk40_dp_set_tmds(struct drm_device *dev, struct dcb_entry *dcb) 869nv50_display_unk40_dp_set_tmds(struct drm_device *dev, struct dcb_output *dcb)
914{ 870{
915 int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1); 871 int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
916 struct drm_encoder *encoder; 872 struct drm_encoder *encoder;
917 u32 tmp; 873 u32 tmp;
918 874
919 if (dcb->type != OUTPUT_TMDS) 875 if (dcb->type != DCB_OUTPUT_TMDS)
920 return; 876 return;
921 877
922 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 878 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
923 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 879 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
924 880
925 if (nv_encoder->dcb->type == OUTPUT_DP && 881 if (nv_encoder->dcb->type == DCB_OUTPUT_DP &&
926 nv_encoder->dcb->or & (1 << or)) { 882 nv_encoder->dcb->or & (1 << or)) {
927 tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link)); 883 tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
928 tmp &= ~NV50_SOR_DP_CTRL_ENABLED; 884 tmp &= ~NV50_SOR_DP_CTRL_ENABLED;
@@ -936,7 +892,7 @@ static void
936nv50_display_unk40_handler(struct drm_device *dev) 892nv50_display_unk40_handler(struct drm_device *dev)
937{ 893{
938 struct nv50_display *disp = nv50_display(dev); 894 struct nv50_display *disp = nv50_display(dev);
939 struct dcb_entry *dcb = disp->irq.dcb; 895 struct dcb_output *dcb = disp->irq.dcb;
940 u16 script = disp->irq.script; 896 u16 script = disp->irq.script;
941 u32 unk30 = nv_rd32(dev, 0x610030), pclk = disp->irq.pclk; 897 u32 unk30 = nv_rd32(dev, 0x610030), pclk = disp->irq.pclk;
942 898
diff --git a/drivers/gpu/drm/nouveau/nv50_display.h b/drivers/gpu/drm/nouveau/nv50_display.h
index e9db9b97f04..25c30139172 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.h
+++ b/drivers/gpu/drm/nouveau/nv50_display.h
@@ -53,7 +53,7 @@ struct nv50_display {
53 53
54 struct tasklet_struct tasklet; 54 struct tasklet_struct tasklet;
55 struct { 55 struct {
56 struct dcb_entry *dcb; 56 struct dcb_output *dcb;
57 u16 script; 57 u16 script;
58 u32 pclk; 58 u32 pclk;
59 } irq; 59 } irq;
diff --git a/drivers/gpu/drm/nouveau/nv50_sor.c b/drivers/gpu/drm/nouveau/nv50_sor.c
index 93240bde891..2e6d83b37a0 100644
--- a/drivers/gpu/drm/nouveau/nv50_sor.c
+++ b/drivers/gpu/drm/nouveau/nv50_sor.c
@@ -37,7 +37,7 @@
37#include "nv50_display.h" 37#include "nv50_display.h"
38 38
39static u32 39static u32
40nv50_sor_dp_lane_map(struct drm_device *dev, struct dcb_entry *dcb, u8 lane) 40nv50_sor_dp_lane_map(struct drm_device *dev, struct dcb_output *dcb, u8 lane)
41{ 41{
42 struct drm_nouveau_private *dev_priv = dev->dev_private; 42 struct drm_nouveau_private *dev_priv = dev->dev_private;
43 static const u8 nvaf[] = { 24, 16, 8, 0 }; /* thanks, apple.. */ 43 static const u8 nvaf[] = { 24, 16, 8, 0 }; /* thanks, apple.. */
@@ -48,14 +48,14 @@ nv50_sor_dp_lane_map(struct drm_device *dev, struct dcb_entry *dcb, u8 lane)
48} 48}
49 49
50static void 50static void
51nv50_sor_dp_train_set(struct drm_device *dev, struct dcb_entry *dcb, u8 pattern) 51nv50_sor_dp_train_set(struct drm_device *dev, struct dcb_output *dcb, u8 pattern)
52{ 52{
53 u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1); 53 u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
54 nv_mask(dev, NV50_SOR_DP_CTRL(or, link), 0x0f000000, pattern << 24); 54 nv_mask(dev, NV50_SOR_DP_CTRL(or, link), 0x0f000000, pattern << 24);
55} 55}
56 56
57static void 57static void
58nv50_sor_dp_train_adj(struct drm_device *dev, struct dcb_entry *dcb, 58nv50_sor_dp_train_adj(struct drm_device *dev, struct dcb_output *dcb,
59 u8 lane, u8 swing, u8 preem) 59 u8 lane, u8 swing, u8 preem)
60{ 60{
61 u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1); 61 u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
@@ -82,7 +82,7 @@ nv50_sor_dp_train_adj(struct drm_device *dev, struct dcb_entry *dcb,
82} 82}
83 83
84static void 84static void
85nv50_sor_dp_link_set(struct drm_device *dev, struct dcb_entry *dcb, int crtc, 85nv50_sor_dp_link_set(struct drm_device *dev, struct dcb_output *dcb, int crtc,
86 int link_nr, u32 link_bw, bool enhframe) 86 int link_nr, u32 link_bw, bool enhframe)
87{ 87{
88 u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1); 88 u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
@@ -269,9 +269,9 @@ nv50_sor_dpms(struct drm_encoder *encoder, int mode)
269 struct nouveau_encoder *nvenc = nouveau_encoder(enc); 269 struct nouveau_encoder *nvenc = nouveau_encoder(enc);
270 270
271 if (nvenc == nv_encoder || 271 if (nvenc == nv_encoder ||
272 (nvenc->dcb->type != OUTPUT_TMDS && 272 (nvenc->dcb->type != DCB_OUTPUT_TMDS &&
273 nvenc->dcb->type != OUTPUT_LVDS && 273 nvenc->dcb->type != DCB_OUTPUT_LVDS &&
274 nvenc->dcb->type != OUTPUT_DP) || 274 nvenc->dcb->type != DCB_OUTPUT_DP) ||
275 nvenc->dcb->or != nv_encoder->dcb->or) 275 nvenc->dcb->or != nv_encoder->dcb->or)
276 continue; 276 continue;
277 277
@@ -303,7 +303,7 @@ nv50_sor_dpms(struct drm_encoder *encoder, int mode)
303 nv_rd32(dev, NV50_PDISPLAY_SOR_DPMS_STATE(or))); 303 nv_rd32(dev, NV50_PDISPLAY_SOR_DPMS_STATE(or)));
304 } 304 }
305 305
306 if (nv_encoder->dcb->type == OUTPUT_DP) { 306 if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
307 struct dp_train_func func = { 307 struct dp_train_func func = {
308 .link_set = nv50_sor_dp_link_set, 308 .link_set = nv50_sor_dp_link_set,
309 .train_set = nv50_sor_dp_train_set, 309 .train_set = nv50_sor_dp_train_set,
@@ -354,7 +354,7 @@ nv50_sor_prepare(struct drm_encoder *encoder)
354{ 354{
355 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 355 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
356 nv50_sor_disconnect(encoder); 356 nv50_sor_disconnect(encoder);
357 if (nv_encoder->dcb->type == OUTPUT_DP) { 357 if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
358 /* avoid race between link training and supervisor intr */ 358 /* avoid race between link training and supervisor intr */
359 nv50_display_sync(encoder->dev); 359 nv50_display_sync(encoder->dev);
360 } 360 }
@@ -382,7 +382,7 @@ nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
382 nv_encoder->crtc = encoder->crtc; 382 nv_encoder->crtc = encoder->crtc;
383 383
384 switch (nv_encoder->dcb->type) { 384 switch (nv_encoder->dcb->type) {
385 case OUTPUT_TMDS: 385 case DCB_OUTPUT_TMDS:
386 if (nv_encoder->dcb->sorconf.link & 1) { 386 if (nv_encoder->dcb->sorconf.link & 1) {
387 if (mode->clock < 165000) 387 if (mode->clock < 165000)
388 mode_ctl = 0x0100; 388 mode_ctl = 0x0100;
@@ -393,7 +393,7 @@ nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
393 393
394 nouveau_hdmi_mode_set(encoder, mode); 394 nouveau_hdmi_mode_set(encoder, mode);
395 break; 395 break;
396 case OUTPUT_DP: 396 case DCB_OUTPUT_DP:
397 nv_connector = nouveau_encoder_connector_get(nv_encoder); 397 nv_connector = nouveau_encoder_connector_get(nv_encoder);
398 if (nv_connector && nv_connector->base.display_info.bpc == 6) { 398 if (nv_connector && nv_connector->base.display_info.bpc == 6) {
399 nv_encoder->dp.datarate = mode->clock * 18 / 8; 399 nv_encoder->dp.datarate = mode->clock * 18 / 8;
@@ -474,7 +474,7 @@ static const struct drm_encoder_funcs nv50_sor_encoder_funcs = {
474}; 474};
475 475
476int 476int
477nv50_sor_create(struct drm_connector *connector, struct dcb_entry *entry) 477nv50_sor_create(struct drm_connector *connector, struct dcb_output *entry)
478{ 478{
479 struct nouveau_encoder *nv_encoder = NULL; 479 struct nouveau_encoder *nv_encoder = NULL;
480 struct drm_device *dev = connector->dev; 480 struct drm_device *dev = connector->dev;
@@ -484,11 +484,11 @@ nv50_sor_create(struct drm_connector *connector, struct dcb_entry *entry)
484 NV_DEBUG_KMS(dev, "\n"); 484 NV_DEBUG_KMS(dev, "\n");
485 485
486 switch (entry->type) { 486 switch (entry->type) {
487 case OUTPUT_TMDS: 487 case DCB_OUTPUT_TMDS:
488 case OUTPUT_DP: 488 case DCB_OUTPUT_DP:
489 type = DRM_MODE_ENCODER_TMDS; 489 type = DRM_MODE_ENCODER_TMDS;
490 break; 490 break;
491 case OUTPUT_LVDS: 491 case DCB_OUTPUT_LVDS:
492 type = DRM_MODE_ENCODER_LVDS; 492 type = DRM_MODE_ENCODER_LVDS;
493 break; 493 break;
494 default: 494 default:
diff --git a/drivers/gpu/drm/nouveau/nvd0_display.c b/drivers/gpu/drm/nouveau/nvd0_display.c
index 8a2fc89b776..d26dd02f3d1 100644
--- a/drivers/gpu/drm/nouveau/nvd0_display.c
+++ b/drivers/gpu/drm/nouveau/nvd0_display.c
@@ -1063,7 +1063,7 @@ static const struct drm_encoder_funcs nvd0_dac_func = {
1063}; 1063};
1064 1064
1065static int 1065static int
1066nvd0_dac_create(struct drm_connector *connector, struct dcb_entry *dcbe) 1066nvd0_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
1067{ 1067{
1068 struct drm_device *dev = connector->dev; 1068 struct drm_device *dev = connector->dev;
1069 struct nouveau_encoder *nv_encoder; 1069 struct nouveau_encoder *nv_encoder;
@@ -1191,14 +1191,14 @@ nvd0_hdmi_disconnect(struct drm_encoder *encoder)
1191 * SOR 1191 * SOR
1192 *****************************************************************************/ 1192 *****************************************************************************/
1193static inline u32 1193static inline u32
1194nvd0_sor_dp_lane_map(struct drm_device *dev, struct dcb_entry *dcb, u8 lane) 1194nvd0_sor_dp_lane_map(struct drm_device *dev, struct dcb_output *dcb, u8 lane)
1195{ 1195{
1196 static const u8 nvd0[] = { 16, 8, 0, 24 }; 1196 static const u8 nvd0[] = { 16, 8, 0, 24 };
1197 return nvd0[lane]; 1197 return nvd0[lane];
1198} 1198}
1199 1199
1200static void 1200static void
1201nvd0_sor_dp_train_set(struct drm_device *dev, struct dcb_entry *dcb, u8 pattern) 1201nvd0_sor_dp_train_set(struct drm_device *dev, struct dcb_output *dcb, u8 pattern)
1202{ 1202{
1203 const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1); 1203 const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
1204 const u32 loff = (or * 0x800) + (link * 0x80); 1204 const u32 loff = (or * 0x800) + (link * 0x80);
@@ -1206,7 +1206,7 @@ nvd0_sor_dp_train_set(struct drm_device *dev, struct dcb_entry *dcb, u8 pattern)
1206} 1206}
1207 1207
1208static void 1208static void
1209nvd0_sor_dp_train_adj(struct drm_device *dev, struct dcb_entry *dcb, 1209nvd0_sor_dp_train_adj(struct drm_device *dev, struct dcb_output *dcb,
1210 u8 lane, u8 swing, u8 preem) 1210 u8 lane, u8 swing, u8 preem)
1211{ 1211{
1212 const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1); 1212 const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
@@ -1247,7 +1247,7 @@ nvd0_sor_dp_train_adj(struct drm_device *dev, struct dcb_entry *dcb,
1247} 1247}
1248 1248
1249static void 1249static void
1250nvd0_sor_dp_link_set(struct drm_device *dev, struct dcb_entry *dcb, int crtc, 1250nvd0_sor_dp_link_set(struct drm_device *dev, struct dcb_output *dcb, int crtc,
1251 int link_nr, u32 link_bw, bool enhframe) 1251 int link_nr, u32 link_bw, bool enhframe)
1252{ 1252{
1253 const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1); 1253 const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
@@ -1290,7 +1290,7 @@ nvd0_sor_dp_link_set(struct drm_device *dev, struct dcb_entry *dcb, int crtc,
1290} 1290}
1291 1291
1292static void 1292static void
1293nvd0_sor_dp_link_get(struct drm_device *dev, struct dcb_entry *dcb, 1293nvd0_sor_dp_link_get(struct drm_device *dev, struct dcb_output *dcb,
1294 u32 *link_nr, u32 *link_bw) 1294 u32 *link_nr, u32 *link_bw)
1295{ 1295{
1296 const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1); 1296 const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
@@ -1308,7 +1308,7 @@ nvd0_sor_dp_link_get(struct drm_device *dev, struct dcb_entry *dcb,
1308} 1308}
1309 1309
1310static void 1310static void
1311nvd0_sor_dp_calc_tu(struct drm_device *dev, struct dcb_entry *dcb, 1311nvd0_sor_dp_calc_tu(struct drm_device *dev, struct dcb_output *dcb,
1312 u32 crtc, u32 datarate) 1312 u32 crtc, u32 datarate)
1313{ 1313{
1314 const u32 symbol = 100000; 1314 const u32 symbol = 100000;
@@ -1366,7 +1366,7 @@ nvd0_sor_dpms(struct drm_encoder *encoder, int mode)
1366 nv_wait(dev, 0x61c004 + (or * 0x0800), 0x80000000, 0x00000000); 1366 nv_wait(dev, 0x61c004 + (or * 0x0800), 0x80000000, 0x00000000);
1367 nv_wait(dev, 0x61c030 + (or * 0x0800), 0x10000000, 0x00000000); 1367 nv_wait(dev, 0x61c030 + (or * 0x0800), 0x10000000, 0x00000000);
1368 1368
1369 if (nv_encoder->dcb->type == OUTPUT_DP) { 1369 if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
1370 struct dp_train_func func = { 1370 struct dp_train_func func = {
1371 .link_set = nvd0_sor_dp_link_set, 1371 .link_set = nvd0_sor_dp_link_set,
1372 .train_set = nvd0_sor_dp_train_set, 1372 .train_set = nvd0_sor_dp_train_set,
@@ -1427,7 +1427,7 @@ static void
1427nvd0_sor_prepare(struct drm_encoder *encoder) 1427nvd0_sor_prepare(struct drm_encoder *encoder)
1428{ 1428{
1429 nvd0_sor_disconnect(encoder); 1429 nvd0_sor_disconnect(encoder);
1430 if (nouveau_encoder(encoder)->dcb->type == OUTPUT_DP) 1430 if (nouveau_encoder(encoder)->dcb->type == DCB_OUTPUT_DP)
1431 evo_sync(encoder->dev, EVO_MASTER); 1431 evo_sync(encoder->dev, EVO_MASTER);
1432} 1432}
1433 1433
@@ -1462,7 +1462,7 @@ nvd0_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
1462 1462
1463 nv_connector = nouveau_encoder_connector_get(nv_encoder); 1463 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1464 switch (nv_encoder->dcb->type) { 1464 switch (nv_encoder->dcb->type) {
1465 case OUTPUT_TMDS: 1465 case DCB_OUTPUT_TMDS:
1466 if (nv_encoder->dcb->sorconf.link & 1) { 1466 if (nv_encoder->dcb->sorconf.link & 1) {
1467 if (mode->clock < 165000) 1467 if (mode->clock < 165000)
1468 mode_ctrl |= 0x00000100; 1468 mode_ctrl |= 0x00000100;
@@ -1478,7 +1478,7 @@ nvd0_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
1478 1478
1479 nvd0_hdmi_mode_set(encoder, mode); 1479 nvd0_hdmi_mode_set(encoder, mode);
1480 break; 1480 break;
1481 case OUTPUT_LVDS: 1481 case DCB_OUTPUT_LVDS:
1482 or_config = (mode_ctrl & 0x00000f00) >> 8; 1482 or_config = (mode_ctrl & 0x00000f00) >> 8;
1483 if (bios->fp_no_ddc) { 1483 if (bios->fp_no_ddc) {
1484 if (bios->fp.dual_link) 1484 if (bios->fp.dual_link)
@@ -1507,7 +1507,7 @@ nvd0_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
1507 1507
1508 } 1508 }
1509 break; 1509 break;
1510 case OUTPUT_DP: 1510 case DCB_OUTPUT_DP:
1511 if (nv_connector->base.display_info.bpc == 6) { 1511 if (nv_connector->base.display_info.bpc == 6) {
1512 nv_encoder->dp.datarate = mode->clock * 18 / 8; 1512 nv_encoder->dp.datarate = mode->clock * 18 / 8;
1513 syncs |= 0x00000002 << 6; 1513 syncs |= 0x00000002 << 6;
@@ -1530,7 +1530,7 @@ nvd0_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
1530 1530
1531 nvd0_sor_dpms(encoder, DRM_MODE_DPMS_ON); 1531 nvd0_sor_dpms(encoder, DRM_MODE_DPMS_ON);
1532 1532
1533 if (nv_encoder->dcb->type == OUTPUT_DP) { 1533 if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
1534 nvd0_sor_dp_calc_tu(dev, nv_encoder->dcb, nv_crtc->index, 1534 nvd0_sor_dp_calc_tu(dev, nv_encoder->dcb, nv_crtc->index,
1535 nv_encoder->dp.datarate); 1535 nv_encoder->dp.datarate);
1536 } 1536 }
@@ -1571,7 +1571,7 @@ static const struct drm_encoder_funcs nvd0_sor_func = {
1571}; 1571};
1572 1572
1573static int 1573static int
1574nvd0_sor_create(struct drm_connector *connector, struct dcb_entry *dcbe) 1574nvd0_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
1575{ 1575{
1576 struct drm_device *dev = connector->dev; 1576 struct drm_device *dev = connector->dev;
1577 struct nouveau_encoder *nv_encoder; 1577 struct nouveau_encoder *nv_encoder;
@@ -1597,23 +1597,23 @@ nvd0_sor_create(struct drm_connector *connector, struct dcb_entry *dcbe)
1597/****************************************************************************** 1597/******************************************************************************
1598 * IRQ 1598 * IRQ
1599 *****************************************************************************/ 1599 *****************************************************************************/
1600static struct dcb_entry * 1600static struct dcb_output *
1601lookup_dcb(struct drm_device *dev, int id, u32 mc) 1601lookup_dcb(struct drm_device *dev, int id, u32 mc)
1602{ 1602{
1603 struct drm_nouveau_private *dev_priv = dev->dev_private; 1603 struct drm_nouveau_private *dev_priv = dev->dev_private;
1604 int type, or, i, link = -1; 1604 int type, or, i, link = -1;
1605 1605
1606 if (id < 4) { 1606 if (id < 4) {
1607 type = OUTPUT_ANALOG; 1607 type = DCB_OUTPUT_ANALOG;
1608 or = id; 1608 or = id;
1609 } else { 1609 } else {
1610 switch (mc & 0x00000f00) { 1610 switch (mc & 0x00000f00) {
1611 case 0x00000000: link = 0; type = OUTPUT_LVDS; break; 1611 case 0x00000000: link = 0; type = DCB_OUTPUT_LVDS; break;
1612 case 0x00000100: link = 0; type = OUTPUT_TMDS; break; 1612 case 0x00000100: link = 0; type = DCB_OUTPUT_TMDS; break;
1613 case 0x00000200: link = 1; type = OUTPUT_TMDS; break; 1613 case 0x00000200: link = 1; type = DCB_OUTPUT_TMDS; break;
1614 case 0x00000500: link = 0; type = OUTPUT_TMDS; break; 1614 case 0x00000500: link = 0; type = DCB_OUTPUT_TMDS; break;
1615 case 0x00000800: link = 0; type = OUTPUT_DP; break; 1615 case 0x00000800: link = 0; type = DCB_OUTPUT_DP; break;
1616 case 0x00000900: link = 1; type = OUTPUT_DP; break; 1616 case 0x00000900: link = 1; type = DCB_OUTPUT_DP; break;
1617 default: 1617 default:
1618 NV_ERROR(dev, "PDISP: unknown SOR mc 0x%08x\n", mc); 1618 NV_ERROR(dev, "PDISP: unknown SOR mc 0x%08x\n", mc);
1619 return NULL; 1619 return NULL;
@@ -1623,7 +1623,7 @@ lookup_dcb(struct drm_device *dev, int id, u32 mc)
1623 } 1623 }
1624 1624
1625 for (i = 0; i < dev_priv->vbios.dcb.entries; i++) { 1625 for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
1626 struct dcb_entry *dcb = &dev_priv->vbios.dcb.entry[i]; 1626 struct dcb_output *dcb = &dev_priv->vbios.dcb.entry[i];
1627 if (dcb->type == type && (dcb->or & (1 << or)) && 1627 if (dcb->type == type && (dcb->or & (1 << or)) &&
1628 (link < 0 || link == !(dcb->sorconf.link & 1))) 1628 (link < 0 || link == !(dcb->sorconf.link & 1)))
1629 return dcb; 1629 return dcb;
@@ -1636,7 +1636,7 @@ lookup_dcb(struct drm_device *dev, int id, u32 mc)
1636static void 1636static void
1637nvd0_display_unk1_handler(struct drm_device *dev, u32 crtc, u32 mask) 1637nvd0_display_unk1_handler(struct drm_device *dev, u32 crtc, u32 mask)
1638{ 1638{
1639 struct dcb_entry *dcb; 1639 struct dcb_output *dcb;
1640 int i; 1640 int i;
1641 1641
1642 for (i = 0; mask && i < 8; i++) { 1642 for (i = 0; mask && i < 8; i++) {
@@ -1659,7 +1659,7 @@ nvd0_display_unk1_handler(struct drm_device *dev, u32 crtc, u32 mask)
1659static void 1659static void
1660nvd0_display_unk2_handler(struct drm_device *dev, u32 crtc, u32 mask) 1660nvd0_display_unk2_handler(struct drm_device *dev, u32 crtc, u32 mask)
1661{ 1661{
1662 struct dcb_entry *dcb; 1662 struct dcb_output *dcb;
1663 u32 or, tmp, pclk; 1663 u32 or, tmp, pclk;
1664 int i; 1664 int i;
1665 1665
@@ -1697,12 +1697,12 @@ nvd0_display_unk2_handler(struct drm_device *dev, u32 crtc, u32 mask)
1697 1697
1698 nv_wr32(dev, 0x612200 + (crtc * 0x800), 0x00000000); 1698 nv_wr32(dev, 0x612200 + (crtc * 0x800), 0x00000000);
1699 switch (dcb->type) { 1699 switch (dcb->type) {
1700 case OUTPUT_ANALOG: 1700 case DCB_OUTPUT_ANALOG:
1701 nv_wr32(dev, 0x612280 + (or * 0x800), 0x00000000); 1701 nv_wr32(dev, 0x612280 + (or * 0x800), 0x00000000);
1702 break; 1702 break;
1703 case OUTPUT_TMDS: 1703 case DCB_OUTPUT_TMDS:
1704 case OUTPUT_LVDS: 1704 case DCB_OUTPUT_LVDS:
1705 case OUTPUT_DP: 1705 case DCB_OUTPUT_DP:
1706 if (cfg & 0x00000100) 1706 if (cfg & 0x00000100)
1707 tmp = 0x00000101; 1707 tmp = 0x00000101;
1708 else 1708 else
@@ -1725,7 +1725,7 @@ nvd0_display_unk2_handler(struct drm_device *dev, u32 crtc, u32 mask)
1725static void 1725static void
1726nvd0_display_unk4_handler(struct drm_device *dev, u32 crtc, u32 mask) 1726nvd0_display_unk4_handler(struct drm_device *dev, u32 crtc, u32 mask)
1727{ 1727{
1728 struct dcb_entry *dcb; 1728 struct dcb_output *dcb;
1729 int pclk, i; 1729 int pclk, i;
1730 1730
1731 pclk = nv_rd32(dev, 0x660450 + (crtc * 0x300)) / 1000; 1731 pclk = nv_rd32(dev, 0x660450 + (crtc * 0x300)) / 1000;
@@ -1972,7 +1972,7 @@ nvd0_display_create(struct drm_device *dev)
1972 struct drm_connector *connector, *tmp; 1972 struct drm_connector *connector, *tmp;
1973 struct pci_dev *pdev = dev->pdev; 1973 struct pci_dev *pdev = dev->pdev;
1974 struct nvd0_display *disp; 1974 struct nvd0_display *disp;
1975 struct dcb_entry *dcbe; 1975 struct dcb_output *dcbe;
1976 int crtcs, ret, i; 1976 int crtcs, ret, i;
1977 1977
1978 disp = kzalloc(sizeof(*disp), GFP_KERNEL); 1978 disp = kzalloc(sizeof(*disp), GFP_KERNEL);
@@ -2001,12 +2001,12 @@ nvd0_display_create(struct drm_device *dev)
2001 } 2001 }
2002 2002
2003 switch (dcbe->type) { 2003 switch (dcbe->type) {
2004 case OUTPUT_TMDS: 2004 case DCB_OUTPUT_TMDS:
2005 case OUTPUT_LVDS: 2005 case DCB_OUTPUT_LVDS:
2006 case OUTPUT_DP: 2006 case DCB_OUTPUT_DP:
2007 nvd0_sor_create(connector, dcbe); 2007 nvd0_sor_create(connector, dcbe);
2008 break; 2008 break;
2009 case OUTPUT_ANALOG: 2009 case DCB_OUTPUT_ANALOG:
2010 nvd0_dac_create(connector, dcbe); 2010 nvd0_dac_create(connector, dcbe);
2011 break; 2011 break;
2012 default: 2012 default:
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-03 23:39:40 -0500