ARM: mmci: add dmaengine-based DMA support

Based on a patch from Linus Walleij.

Add dmaengine based support for DMA to the MMCI driver, using the
Primecell DMA engine interface.  The changes over Linus' driver are:

- rename txsize_threshold to dmasize_threshold, as this reflects the
  purpose more.
- use 'mmci_dma_' as the function prefix rather than 'dma_mmci_'.
- clean up requesting of dma channels.
- don't release a single channel twice when it's shared between tx and rx.
- get rid of 'dma_enable' bool - instead check whether the channel is NULL.
- detect incomplete DMA at the end of a transfer.  Some DMA controllers
  (eg, PL08x) are unable to be configured for scatter DMA and also listen
  to all four DMA request signals [BREQ,SREQ,LBREQ,LSREQ] from the MMCI.
  They can do one or other but not both.  As MMCI uses LBREQ/LSREQ for the
  final burst/words, PL08x does not transfer the last few words.
- map and unmap DMA buffers using the DMA engine struct device, not the
  MMCI struct device - the DMA engine is doing the DMA transfer, not us.
- avoid double-unmapping of the DMA buffers on MMCI data errors.
- don't check for negative values from the dmaengine tx submission
  function - Dan says this must never fail.
- use new dmaengine helper functions rather than using the ugly function
  pointers directly.
- allow DMA code to be fully optimized away using dma_inprogress() which
  is defined to constant 0 if DMA engine support is disabled.
- request maximum segment size from the DMA engine struct device and
  set this appropriately.
- removed checking of buffer alignment - the DMA engine should deal with
  its own restrictions on buffer alignment, not the individual DMA engine
  users.
- removed setting DMAREQCTL - this confuses some DMA controllers as it
  causes LBREQ to be asserted for the last seven transfers, rather than
  six SREQ and one LSREQ.
- removed burst setting - the DMA controller should not burst past the
  transfer size required to complete the DMA operation.

Tested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

3 files changed, 304 insertions, 8 deletions

diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index db2a358143d..8a29c9f4a81 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -2,7 +2,7 @@
  *  linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
  *
  *  Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
- *  Copyright (C) 2010 ST-Ericsson AB.
+ *  Copyright (C) 2010 ST-Ericsson SA
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -25,8 +25,10 @@
 #include <linux/clk.h>
 #include <linux/scatterlist.h>
 #include <linux/gpio.h>
-#include <linux/amba/mmci.h>
 #include <linux/regulator/consumer.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+#include <linux/amba/mmci.h>
 
 #include <asm/div64.h>
 #include <asm/io.h>
@@ -186,6 +188,248 @@ static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
         sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 }
 
+/*
+ * All the DMA operation mode stuff goes inside this ifdef.
+ * This assumes that you have a generic DMA device interface,
+ * no custom DMA interfaces are supported.
+ */
+#ifdef CONFIG_DMA_ENGINE
+static void __devinit mmci_dma_setup(struct mmci_host *host)
+{
+        struct mmci_platform_data *plat = host->plat;
+        const char *rxname, *txname;
+        dma_cap_mask_t mask;
+
+        if (!plat || !plat->dma_filter) {
+                dev_info(mmc_dev(host->mmc), "no DMA platform data\n");
+                return;
+        }
+
+        /* Try to acquire a generic DMA engine slave channel */
+        dma_cap_zero(mask);
+        dma_cap_set(DMA_SLAVE, mask);
+
+        /*
+         * If only an RX channel is specified, the driver will
+         * attempt to use it bidirectionally, however if it is
+         * is specified but cannot be located, DMA will be disabled.
+         */
+        if (plat->dma_rx_param) {
+                host->dma_rx_channel = dma_request_channel(mask,
+                                                           plat->dma_filter,
+                                                           plat->dma_rx_param);
+                /* E.g if no DMA hardware is present */
+                if (!host->dma_rx_channel)
+                        dev_err(mmc_dev(host->mmc), "no RX DMA channel\n");
+        }
+
+        if (plat->dma_tx_param) {
+                host->dma_tx_channel = dma_request_channel(mask,
+                                                           plat->dma_filter,
+                                                           plat->dma_tx_param);
+                if (!host->dma_tx_channel)
+                        dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n");
+        } else {
+                host->dma_tx_channel = host->dma_rx_channel;
+        }
+
+        if (host->dma_rx_channel)
+                rxname = dma_chan_name(host->dma_rx_channel);
+        else
+                rxname = "none";
+
+        if (host->dma_tx_channel)
+                txname = dma_chan_name(host->dma_tx_channel);
+        else
+                txname = "none";
+
+        dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n",
+                 rxname, txname);
+
+        /*
+         * Limit the maximum segment size in any SG entry according to
+         * the parameters of the DMA engine device.
+         */
+        if (host->dma_tx_channel) {
+                struct device *dev = host->dma_tx_channel->device->dev;
+                unsigned int max_seg_size = dma_get_max_seg_size(dev);
+
+                if (max_seg_size < host->mmc->max_seg_size)
+                        host->mmc->max_seg_size = max_seg_size;
+        }
+        if (host->dma_rx_channel) {
+                struct device *dev = host->dma_rx_channel->device->dev;
+                unsigned int max_seg_size = dma_get_max_seg_size(dev);
+
+                if (max_seg_size < host->mmc->max_seg_size)
+                        host->mmc->max_seg_size = max_seg_size;
+        }
+}
+
+/*
+ * This is used in __devinit or __devexit so inline it
+ * so it can be discarded.
+ */
+static inline void mmci_dma_release(struct mmci_host *host)
+{
+        struct mmci_platform_data *plat = host->plat;
+
+        if (host->dma_rx_channel)
+                dma_release_channel(host->dma_rx_channel);
+        if (host->dma_tx_channel && plat->dma_tx_param)
+                dma_release_channel(host->dma_tx_channel);
+        host->dma_rx_channel = host->dma_tx_channel = NULL;
+}
+
+static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
+{
+        struct dma_chan *chan = host->dma_current;
+        enum dma_data_direction dir;
+        u32 status;
+        int i;
+
+        /* Wait up to 1ms for the DMA to complete */
+        for (i = 0; ; i++) {
+                status = readl(host->base + MMCISTATUS);
+                if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100)
+                        break;
+                udelay(10);
+        }
+
+        /*
+         * Check to see whether we still have some data left in the FIFO -
+         * this catches DMA controllers which are unable to monitor the
+         * DMALBREQ and DMALSREQ signals while allowing us to DMA to non-
+         * contiguous buffers.  On TX, we'll get a FIFO underrun error.
+         */
+        if (status & MCI_RXDATAAVLBLMASK) {
+                dmaengine_terminate_all(chan);
+                if (!data->error)
+                        data->error = -EIO;
+        }
+
+        if (data->flags & MMC_DATA_WRITE) {
+                dir = DMA_TO_DEVICE;
+        } else {
+                dir = DMA_FROM_DEVICE;
+        }
+
+        dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir);
+
+        /*
+         * Use of DMA with scatter-gather is impossible.
+         * Give up with DMA and switch back to PIO mode.
+         */
+        if (status & MCI_RXDATAAVLBLMASK) {
+                dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n");
+                mmci_dma_release(host);
+        }
+}
+
+static void mmci_dma_data_error(struct mmci_host *host)
+{
+        dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n");
+        dmaengine_terminate_all(host->dma_current);
+}
+
+static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
+{
+        struct variant_data *variant = host->variant;
+        struct dma_slave_config conf = {
+                .src_addr = host->phybase + MMCIFIFO,
+                .dst_addr = host->phybase + MMCIFIFO,
+                .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
+                .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
+                .src_maxburst = variant->fifohalfsize >> 2, /* # of words */
+                .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */
+        };
+        struct mmc_data *data = host->data;
+        struct dma_chan *chan;
+        struct dma_device *device;
+        struct dma_async_tx_descriptor *desc;
+        int nr_sg;
+
+        host->dma_current = NULL;
+
+        if (data->flags & MMC_DATA_READ) {
+                conf.direction = DMA_FROM_DEVICE;
+                chan = host->dma_rx_channel;
+        } else {
+                conf.direction = DMA_TO_DEVICE;
+                chan = host->dma_tx_channel;
+        }
+
+        /* If there's no DMA channel, fall back to PIO */