diff options
author | Paul Walmsley <paul@pwsan.com> | 2012-04-19 15:33:52 -0400 |
---|---|---|
committer | Paul Walmsley <paul@pwsan.com> | 2012-04-19 15:33:52 -0400 |
commit | bf30f950ac6b3ba904b90afa0fe12de78f2cf5a1 (patch) | |
tree | 1fae53cacb30ea32bd40b04b6590ad1224301e84 | |
parent | eb42b5d3997c3a7d0da6c3bb56c1a0055ba3b2be (diff) |
ARM: OMAP4: hwmod data: add EMIF1 and 2
Add the EMIF1 and 2 hwmods and associated interconnect data. The EMIFs
are SDRAM interface IP blocks.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: BenoƮt Cousson <b-cousson@ti.com>
-rw-r--r-- | arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 98 |
1 files changed, 96 insertions, 2 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index c31ae9aa9fd..476e98ac170 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c | |||
@@ -261,8 +261,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = { | |||
261 | * efuse_ctrl_cust | 261 | * efuse_ctrl_cust |
262 | * efuse_ctrl_std | 262 | * efuse_ctrl_std |
263 | * elm | 263 | * elm |
264 | * emif1 | ||
265 | * emif2 | ||
266 | * gpu | 264 | * gpu |
267 | * mcasp | 265 | * mcasp |
268 | * mpu_c0 | 266 | * mpu_c0 |
@@ -813,6 +811,64 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = { | |||
813 | }; | 811 | }; |
814 | 812 | ||
815 | /* | 813 | /* |
814 | * 'emif' class | ||
815 | * external memory interface no1 | ||
816 | */ | ||
817 | |||
818 | static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = { | ||
819 | .rev_offs = 0x0000, | ||
820 | }; | ||
821 | |||
822 | static struct omap_hwmod_class omap44xx_emif_hwmod_class = { | ||
823 | .name = "emif", | ||
824 | .sysc = &omap44xx_emif_sysc, | ||
825 | }; | ||
826 | |||
827 | /* emif1 */ | ||
828 | static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = { | ||
829 | { .irq = 110 + OMAP44XX_IRQ_GIC_START }, | ||
830 | { .irq = -1 } | ||
831 | }; | ||
832 | |||
833 | static struct omap_hwmod omap44xx_emif1_hwmod = { | ||
834 | .name = "emif1", | ||
835 | .class = &omap44xx_emif_hwmod_class, | ||
836 | .clkdm_name = "l3_emif_clkdm", | ||
837 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, | ||
838 | .mpu_irqs = omap44xx_emif1_irqs, | ||
839 | .main_clk = "ddrphy_ck", | ||
840 | .prcm = { | ||
841 | .omap4 = { | ||
842 | .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET, | ||
843 | .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET, | ||
844 | .modulemode = MODULEMODE_HWCTRL, | ||
845 | }, | ||
846 | }, | ||
847 | }; | ||
848 | |||
849 | /* emif2 */ | ||
850 | static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = { | ||
851 | { .irq = 111 + OMAP44XX_IRQ_GIC_START }, | ||
852 | { .irq = -1 } | ||
853 | }; | ||
854 | |||
855 | static struct omap_hwmod omap44xx_emif2_hwmod = { | ||
856 | .name = "emif2", | ||
857 | .class = &omap44xx_emif_hwmod_class, | ||
858 | .clkdm_name = "l3_emif_clkdm", | ||
859 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, | ||
860 | .mpu_irqs = omap44xx_emif2_irqs, | ||
861 | .main_clk = "ddrphy_ck", | ||
862 | .prcm = { | ||
863 | .omap4 = { | ||
864 | .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET, | ||
865 | .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET, | ||
866 | .modulemode = MODULEMODE_HWCTRL, | ||
867 | }, | ||
868 | }, | ||
869 | }; | ||
870 | |||
871 | /* | ||
816 | * 'fdif' class | 872 | * 'fdif' class |
817 | * face detection hw accelerator module | 873 | * face detection hw accelerator module |
818 | */ | 874 | */ |
@@ -3673,6 +3729,42 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = { | |||
3673 | .user = OCP_USER_MPU, | 3729 | .user = OCP_USER_MPU, |
3674 | }; | 3730 | }; |
3675 | 3731 | ||
3732 | static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = { | ||
3733 | { | ||
3734 | .pa_start = 0x4c000000, | ||
3735 | .pa_end = 0x4c0000ff, | ||
3736 | .flags = ADDR_TYPE_RT | ||
3737 | }, | ||
3738 | { } | ||
3739 | }; | ||
3740 | |||
3741 | /* emif_fw -> emif1 */ | ||
3742 | static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = { | ||
3743 | .master = &omap44xx_emif_fw_hwmod, | ||
3744 | .slave = &omap44xx_emif1_hwmod, | ||
3745 | .clk = "l3_div_ck", | ||
3746 | .addr = omap44xx_emif1_addrs, | ||
3747 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
3748 | }; | ||
3749 | |||
3750 | static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = { | ||
3751 | { | ||
3752 | .pa_start = 0x4d000000, | ||
3753 | .pa_end = 0x4d0000ff, | ||
3754 | .flags = ADDR_TYPE_RT | ||
3755 | }, | ||
3756 | { } | ||
3757 | }; | ||
3758 | |||
3759 | /* emif_fw -> emif2 */ | ||
3760 | static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = { | ||
3761 | .master = &omap44xx_emif_fw_hwmod, | ||
3762 | .slave = &omap44xx_emif2_hwmod, | ||
3763 | .clk = "l3_div_ck", | ||
3764 | .addr = omap44xx_emif2_addrs, | ||
3765 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
3766 | }; | ||
3767 | |||
3676 | static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = { | 3768 | static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = { |
3677 | { | 3769 | { |
3678 | .pa_start = 0x4a10a000, | 3770 | .pa_start = 0x4a10a000, |
@@ -4926,6 +5018,8 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { | |||
4926 | &omap44xx_l4_per__dss_rfbi, | 5018 | &omap44xx_l4_per__dss_rfbi, |
4927 | &omap44xx_l3_main_2__dss_venc, | 5019 | &omap44xx_l3_main_2__dss_venc, |
4928 | &omap44xx_l4_per__dss_venc, | 5020 | &omap44xx_l4_per__dss_venc, |
5021 | &omap44xx_emif_fw__emif1, | ||
5022 | &omap44xx_emif_fw__emif2, | ||
4929 | &omap44xx_l4_cfg__fdif, | 5023 | &omap44xx_l4_cfg__fdif, |
4930 | &omap44xx_l4_wkup__gpio1, | 5024 | &omap44xx_l4_wkup__gpio1, |
4931 | &omap44xx_l4_per__gpio2, | 5025 | &omap44xx_l4_per__gpio2, |