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authorRalf Baechle <ralf@linux-mips.org>2012-12-11 15:02:55 -0500
committerRalf Baechle <ralf@linux-mips.org>2012-12-13 12:15:30 -0500
commitbdf20507da11a9a5b32ef04fa09f352828189aef (patch)
tree5fe9541a1b0dfe9628cd3fff26d6ac43de1206a9
parentfa4dbbc602a1fb020b627ca8d5a265ad7f3d0c48 (diff)
MIPS: PMC-Sierra Yosemite: Remove support.
Nobody seems to be interested anymore and upstream also never had an ethernet driver. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat
-rw-r--r--arch/mips/Kconfig44
-rw-r--r--arch/mips/Makefile2
-rw-r--r--arch/mips/configs/yosemite_defconfig94
-rw-r--r--arch/mips/include/asm/hazards.h25
-rw-r--r--arch/mips/include/asm/mach-ar7/war.h1
-rw-r--r--arch/mips/include/asm/mach-ath79/war.h1
-rw-r--r--arch/mips/include/asm/mach-au1x00/war.h1
-rw-r--r--arch/mips/include/asm/mach-bcm47xx/war.h1
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/war.h1
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/war.h1
-rw-r--r--arch/mips/include/asm/mach-cobalt/war.h1
-rw-r--r--arch/mips/include/asm/mach-dec/war.h1
-rw-r--r--arch/mips/include/asm/mach-emma2rh/war.h1
-rw-r--r--arch/mips/include/asm/mach-generic/irq.h6
-rw-r--r--arch/mips/include/asm/mach-ip22/war.h1
-rw-r--r--arch/mips/include/asm/mach-ip27/war.h1
-rw-r--r--arch/mips/include/asm/mach-ip28/war.h1
-rw-r--r--arch/mips/include/asm/mach-ip32/war.h1
-rw-r--r--arch/mips/include/asm/mach-jazz/war.h1
-rw-r--r--arch/mips/include/asm/mach-jz4740/war.h1
-rw-r--r--arch/mips/include/asm/mach-lantiq/war.h1
-rw-r--r--arch/mips/include/asm/mach-lasat/war.h1
-rw-r--r--arch/mips/include/asm/mach-loongson/war.h1
-rw-r--r--arch/mips/include/asm/mach-loongson1/war.h1
-rw-r--r--arch/mips/include/asm/mach-malta/war.h1
-rw-r--r--arch/mips/include/asm/mach-netlogic/war.h1
-rw-r--r--arch/mips/include/asm/mach-pnx833x/war.h1
-rw-r--r--arch/mips/include/asm/mach-pnx8550/war.h1
-rw-r--r--arch/mips/include/asm/mach-powertv/war.h1
-rw-r--r--arch/mips/include/asm/mach-rc32434/war.h1
-rw-r--r--arch/mips/include/asm/mach-rm/war.h1
-rw-r--r--arch/mips/include/asm/mach-sead3/war.h1
-rw-r--r--arch/mips/include/asm/mach-sibyte/war.h1
-rw-r--r--arch/mips/include/asm/mach-tx39xx/war.h1
-rw-r--r--arch/mips/include/asm/mach-tx49xx/war.h1
-rw-r--r--arch/mips/include/asm/mach-vr41xx/war.h1
-rw-r--r--arch/mips/include/asm/mach-wrppmc/war.h1
-rw-r--r--arch/mips/include/asm/mach-yosemite/cpu-feature-overrides.h48
-rw-r--r--arch/mips/include/asm/mach-yosemite/war.h25
-rw-r--r--arch/mips/include/asm/mipsregs.h8
-rw-r--r--arch/mips/include/asm/mmu_context.h6
-rw-r--r--arch/mips/include/asm/module.h2
-rw-r--r--arch/mips/include/asm/pgtable-bits.h14
-rw-r--r--arch/mips/include/asm/pmc-sierra/msp71xx/war.h1
-rw-r--r--arch/mips/include/asm/titan_dep.h231
-rw-r--r--arch/mips/include/asm/war.h8
-rw-r--r--arch/mips/kernel/Makefile1
-rw-r--r--arch/mips/kernel/irq-rm9000.c106
-rw-r--r--arch/mips/mm/c-r4k.c4
-rw-r--r--arch/mips/mm/page.c9
-rw-r--r--arch/mips/mm/tlbex.c18
-rw-r--r--arch/mips/oprofile/Makefile1
-rw-r--r--arch/mips/oprofile/common.c4
-rw-r--r--arch/mips/oprofile/op_model_rm9000.c138
-rw-r--r--arch/mips/pci/Makefile2
-rw-r--r--arch/mips/pci/fixup-yosemite.c41
-rw-r--r--arch/mips/pci/ops-titan-ht.c124
-rw-r--r--arch/mips/pci/ops-titan.c111
-rw-r--r--arch/mips/pci/pci-yosemite.c67
-rw-r--r--arch/mips/pmc-sierra/Kconfig4
-rw-r--r--arch/mips/pmc-sierra/Platform7
-rw-r--r--arch/mips/pmc-sierra/yosemite/Makefile7
-rw-r--r--arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c169
-rw-r--r--arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h67
-rw-r--r--arch/mips/pmc-sierra/yosemite/ht-irq.c41
-rw-r--r--arch/mips/pmc-sierra/yosemite/ht.c404
-rw-r--r--arch/mips/pmc-sierra/yosemite/irq.c152
-rw-r--r--arch/mips/pmc-sierra/yosemite/prom.c142
-rw-r--r--arch/mips/pmc-sierra/yosemite/py-console.c109
-rw-r--r--arch/mips/pmc-sierra/yosemite/setup.c224
-rw-r--r--arch/mips/pmc-sierra/yosemite/setup.h32
-rw-r--r--arch/mips/pmc-sierra/yosemite/smp.c185
72 files changed, 0 insertions, 2715 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 53470f0437c..9806a5ae50b 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -416,27 +416,6 @@ config PMC_MSP
416 of integrated peripherals, interfaces and DSPs in addition to 416 of integrated peripherals, interfaces and DSPs in addition to
417 a variety of MIPS cores. 417 a variety of MIPS cores.
418 418
419config PMC_YOSEMITE
420 bool "PMC-Sierra Yosemite eval board"
421 select CEVT_R4K
422 select CSRC_R4K
423 select DMA_COHERENT
424 select HW_HAS_PCI
425 select IRQ_CPU
426 select IRQ_CPU_RM7K
427 select IRQ_CPU_RM9K
428 select SWAP_IO_SPACE
429 select SYS_HAS_CPU_RM9000
430 select SYS_HAS_EARLY_PRINTK
431 select SYS_SUPPORTS_32BIT_KERNEL
432 select SYS_SUPPORTS_64BIT_KERNEL
433 select SYS_SUPPORTS_BIG_ENDIAN
434 select SYS_SUPPORTS_HIGHMEM
435 select SYS_SUPPORTS_SMP
436 help
437 Yosemite is an evaluation board for the RM9000x2 processor
438 manufactured by PMC-Sierra.
439
440config POWERTV 419config POWERTV
441 bool "Cisco PowerTV" 420 bool "Cisco PowerTV"
442 select BOOT_ELF32 421 select BOOT_ELF32
@@ -1080,9 +1059,6 @@ config IRQ_CPU
1080config IRQ_CPU_RM7K 1059config IRQ_CPU_RM7K
1081 bool 1060 bool
1082 1061
1083config IRQ_CPU_RM9K
1084 bool
1085
1086config IRQ_MSP_SLP 1062config IRQ_MSP_SLP
1087 bool 1063 bool
1088 1064
@@ -1107,10 +1083,6 @@ config PCI_GT64XXX_PCI0
1107config NO_EXCEPT_FILL 1083config NO_EXCEPT_FILL
1108 bool 1084 bool
1109 1085
1110config MIPS_RM9122
1111 bool
1112 select SERIAL_RM9000
1113
1114config SOC_EMMA2RH 1086config SOC_EMMA2RH
1115 bool 1087 bool
1116 select CEVT_R4K 1088 select CEVT_R4K
@@ -1156,9 +1128,6 @@ config SOC_PNX8550
1156config SWAP_IO_SPACE 1128config SWAP_IO_SPACE
1157 bool 1129 bool
1158 1130
1159config SERIAL_RM9000
1160 bool
1161
1162config SGI_HAS_INDYDOG 1131config SGI_HAS_INDYDOG
1163 bool 1132 bool
1164 1133
@@ -1452,16 +1421,6 @@ config CPU_RM7000
1452 select CPU_SUPPORTS_HIGHMEM 1421 select CPU_SUPPORTS_HIGHMEM
1453 select CPU_SUPPORTS_HUGEPAGES 1422 select CPU_SUPPORTS_HUGEPAGES
1454 1423
1455config CPU_RM9000
1456 bool "RM9000"
1457 depends on SYS_HAS_CPU_RM9000
1458 select CPU_HAS_PREFETCH
1459 select CPU_SUPPORTS_32BIT_KERNEL
1460 select CPU_SUPPORTS_64BIT_KERNEL
1461 select CPU_SUPPORTS_HIGHMEM
1462 select CPU_SUPPORTS_HUGEPAGES
1463 select WEAK_ORDERING
1464
1465config CPU_SB1 1424config CPU_SB1
1466 bool "SB1" 1425 bool "SB1"
1467 depends on SYS_HAS_CPU_SB1 1426 depends on SYS_HAS_CPU_SB1
@@ -1680,9 +1639,6 @@ config SYS_HAS_CPU_R10000
1680config SYS_HAS_CPU_RM7000 1639config SYS_HAS_CPU_RM7000
1681 bool 1640 bool
1682 1641
1683config SYS_HAS_CPU_RM9000
1684 bool
1685
1686config SYS_HAS_CPU_SB1 1642config SYS_HAS_CPU_SB1
1687 bool 1643 bool
1688 1644
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index f5f873eed8b..f2dfd404550 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -145,8 +145,6 @@ cflags-$(CONFIG_CPU_NEVADA) += $(call cc-option,-march=rm5200,-march=r5000) \
145 -Wa,--trap 145 -Wa,--trap
146cflags-$(CONFIG_CPU_RM7000) += $(call cc-option,-march=rm7000,-march=r5000) \ 146cflags-$(CONFIG_CPU_RM7000) += $(call cc-option,-march=rm7000,-march=r5000) \
147 -Wa,--trap 147 -Wa,--trap
148cflags-$(CONFIG_CPU_RM9000) += $(call cc-option,-march=rm9000,-march=r5000) \
149 -Wa,--trap
150cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-march=sb1,-march=r5000) \ 148cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-march=sb1,-march=r5000) \
151 -Wa,--trap 149 -Wa,--trap
152cflags-$(CONFIG_CPU_R8000) += -march=r8000 -Wa,--trap 150cflags-$(CONFIG_CPU_R8000) += -march=r8000 -Wa,--trap
diff --git a/arch/mips/configs/yosemite_defconfig b/arch/mips/configs/yosemite_defconfig
deleted file mode 100644
index f72d305a3f0..00000000000
--- a/arch/mips/configs/yosemite_defconfig
+++ /dev/null
@@ -1,94 +0,0 @@
1CONFIG_PMC_YOSEMITE=y
2CONFIG_HIGHMEM=y
3CONFIG_SMP=y
4CONFIG_NR_CPUS=2
5CONFIG_HZ_1000=y
6CONFIG_SYSVIPC=y
7CONFIG_IKCONFIG=y
8CONFIG_IKCONFIG_PROC=y
9CONFIG_LOG_BUF_SHIFT=14
10CONFIG_RELAY=y
11CONFIG_EXPERT=y
12CONFIG_SLAB=y
13CONFIG_MODULES=y
14CONFIG_MODULE_UNLOAD=y
15CONFIG_PCI=y
16CONFIG_PM=y
17CONFIG_NET=y
18CONFIG_PACKET=m
19CONFIG_UNIX=y
20CONFIG_XFRM_USER=m
21CONFIG_INET=y
22CONFIG_IP_PNP=y
23CONFIG_IP_PNP_BOOTP=y
24CONFIG_INET_XFRM_MODE_TRANSPORT=m
25CONFIG_INET_XFRM_MODE_TUNNEL=m
26CONFIG_INET_XFRM_MODE_BEET=m
27CONFIG_IPV6_PRIVACY=y
28CONFIG_IPV6_ROUTER_PREF=y
29CONFIG_INET6_AH=m
30CONFIG_INET6_ESP=m
31CONFIG_INET6_IPCOMP=m
32CONFIG_IPV6_TUNNEL=m
33CONFIG_NETWORK_SECMARK=y
34CONFIG_FW_LOADER=m
35CONFIG_CONNECTOR=m
36CONFIG_CDROM_PKTCDVD=m
37CONFIG_ATA_OVER_ETH=m
38CONFIG_SGI_IOC4=m
39CONFIG_RAID_ATTRS=m
40CONFIG_NETDEVICES=y
41CONFIG_PHYLIB=m
42CONFIG_MARVELL_PHY=m
43CONFIG_DAVICOM_PHY=m
44CONFIG_QSEMI_PHY=m
45CONFIG_LXT_PHY=m
46CONFIG_CICADA_PHY=m
47CONFIG_VITESSE_PHY=m
48CONFIG_SMSC_PHY=m
49CONFIG_NET_ETHERNET=y
50CONFIG_MII=y
51CONFIG_QLA3XXX=m
52CONFIG_CHELSIO_T3=m
53CONFIG_NETXEN_NIC=m
54# CONFIG_INPUT is not set
55# CONFIG_SERIO is not set
56# CONFIG_VT is not set
57CONFIG_SERIAL_8250=y
58CONFIG_SERIAL_8250_CONSOLE=y
59# CONFIG_HW_RANDOM is not set
60# CONFIG_HWMON is not set
61CONFIG_FUSE_FS=m
62CONFIG_PROC_KCORE=y
63CONFIG_TMPFS=y
64CONFIG_TMPFS_POSIX_ACL=y
65CONFIG_NFS_FS=y
66CONFIG_ROOT_NFS=y
67CONFIG_DEBUG_KERNEL=y
68CONFIG_DEBUG_MUTEXES=y
69CONFIG_KEYS=y
70CONFIG_KEYS_DEBUG_PROC_KEYS=y
71CONFIG_CRYPTO_NULL=m
72CONFIG_CRYPTO_ECB=m
73CONFIG_CRYPTO_PCBC=m
74CONFIG_CRYPTO_HMAC=y
75CONFIG_CRYPTO_MD4=m
76CONFIG_CRYPTO_MICHAEL_MIC=m
77CONFIG_CRYPTO_SHA256=m
78CONFIG_CRYPTO_SHA512=m
79CONFIG_CRYPTO_TGR192=m
80CONFIG_CRYPTO_WP512=m
81CONFIG_CRYPTO_ANUBIS=m
82CONFIG_CRYPTO_ARC4=m
83CONFIG_CRYPTO_BLOWFISH=m
84CONFIG_CRYPTO_CAMELLIA=m
85CONFIG_CRYPTO_CAST5=m
86CONFIG_CRYPTO_CAST6=m
87CONFIG_CRYPTO_FCRYPT=m
88CONFIG_CRYPTO_KHAZAD=m
89CONFIG_CRYPTO_SERPENT=m
90CONFIG_CRYPTO_TEA=m
91CONFIG_CRYPTO_TWOFISH=m
92CONFIG_CRC16=m
93CONFIG_CRC32=m
94CONFIG_LIBCRC32C=m
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
index b4c20e4f87c..f0324e92d08 100644
--- a/arch/mips/include/asm/hazards.h
+++ b/arch/mips/include/asm/hazards.h
@@ -161,31 +161,6 @@ ASMMACRO(back_to_back_c0_hazard,
161 ) 161 )
162#define instruction_hazard() do { } while (0) 162#define instruction_hazard() do { } while (0)
163 163
164#elif defined(CONFIG_CPU_RM9000)
165
166/*
167 * RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent
168 * use of the JTLB for instructions should not occur for 4 cpu cycles and use
169 * for data translations should not occur for 3 cpu cycles.
170 */
171
172ASMMACRO(mtc0_tlbw_hazard,
173 _ssnop; _ssnop; _ssnop; _ssnop
174 )
175ASMMACRO(tlbw_use_hazard,
176 _ssnop; _ssnop; _ssnop; _ssnop
177 )
178ASMMACRO(tlb_probe_hazard,
179 _ssnop; _ssnop; _ssnop; _ssnop
180 )
181ASMMACRO(irq_enable_hazard,
182 )
183ASMMACRO(irq_disable_hazard,
184 )
185ASMMACRO(back_to_back_c0_hazard,
186 )
187#define instruction_hazard() do { } while (0)
188
189#elif defined(CONFIG_CPU_SB1) 164#elif defined(CONFIG_CPU_SB1)
190 165
191/* 166/*
diff --git a/arch/mips/include/asm/mach-ar7/war.h b/arch/mips/include/asm/mach-ar7/war.h
index f4862b56308..99071e50faa 100644
--- a/arch/mips/include/asm/mach-ar7/war.h
+++ b/arch/mips/include/asm/mach-ar7/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-ath79/war.h b/arch/mips/include/asm/mach-ath79/war.h
index 323d9f1d8c4..0bb30905fd5 100644
--- a/arch/mips/include/asm/mach-ath79/war.h
+++ b/arch/mips/include/asm/mach-ath79/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-au1x00/war.h b/arch/mips/include/asm/mach-au1x00/war.h
index dd57d03d68b..72e260d24e5 100644
--- a/arch/mips/include/asm/mach-au1x00/war.h
+++ b/arch/mips/include/asm/mach-au1x00/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-bcm47xx/war.h b/arch/mips/include/asm/mach-bcm47xx/war.h
index 87cd4651dda..a3d2f448b10 100644
--- a/arch/mips/include/asm/mach-bcm47xx/war.h
+++ b/arch/mips/include/asm/mach-bcm47xx/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-bcm63xx/war.h b/arch/mips/include/asm/mach-bcm63xx/war.h
index 8e3f3fdf320..05ee8671bef 100644
--- a/arch/mips/include/asm/mach-bcm63xx/war.h
+++ b/arch/mips/include/asm/mach-bcm63xx/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-cavium-octeon/war.h b/arch/mips/include/asm/mach-cavium-octeon/war.h
index c4712d7cc81..eb72b35cf04 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/war.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/war.h
@@ -18,7 +18,6 @@
18#define MIPS4K_ICACHE_REFILL_WAR 0 18#define MIPS4K_ICACHE_REFILL_WAR 0
19#define MIPS_CACHE_SYNC_WAR 0 19#define MIPS_CACHE_SYNC_WAR 0
20#define TX49XX_ICACHE_INDEX_INV_WAR 0 20#define TX49XX_ICACHE_INDEX_INV_WAR 0
21#define RM9000_CDEX_SMP_WAR 0
22#define ICACHE_REFILLS_WORKAROUND_WAR 0 21#define ICACHE_REFILLS_WORKAROUND_WAR 0
23#define R10000_LLSC_WAR 0 22#define R10000_LLSC_WAR 0
24#define MIPS34K_MISSED_ITLB_WAR 0 23#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-cobalt/war.h b/arch/mips/include/asm/mach-cobalt/war.h
index 97884fd18ac..34ae4046541 100644
--- a/arch/mips/include/asm/mach-cobalt/war.h
+++ b/arch/mips/include/asm/mach-cobalt/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-dec/war.h b/arch/mips/include/asm/mach-dec/war.h
index ca5e2ef909a..d29996feb3e 100644
--- a/arch/mips/include/asm/mach-dec/war.h
+++ b/arch/mips/include/asm/mach-dec/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-emma2rh/war.h b/arch/mips/include/asm/mach-emma2rh/war.h
index b660a4c30e6..79ae82da3ec 100644
--- a/arch/mips/include/asm/mach-emma2rh/war.h
+++ b/arch/mips/include/asm/mach-emma2rh/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-generic/irq.h b/arch/mips/include/asm/mach-generic/irq.h
index 70d9a25132c..e014264b2be 100644
--- a/arch/mips/include/asm/mach-generic/irq.h
+++ b/arch/mips/include/asm/mach-generic/irq.h
@@ -34,12 +34,6 @@
34#endif 34#endif
35#endif 35#endif
36 36
37#ifdef CONFIG_IRQ_CPU_RM9K
38#ifndef RM9K_CPU_IRQ_BASE
39#define RM9K_CPU_IRQ_BASE (MIPS_CPU_IRQ_BASE+12)
40#endif
41#endif
42
43#endif /* CONFIG_IRQ_CPU */ 37#endif /* CONFIG_IRQ_CPU */
44 38
45#endif /* __ASM_MACH_GENERIC_IRQ_H */ 39#endif /* __ASM_MACH_GENERIC_IRQ_H */
diff --git a/arch/mips/include/asm/mach-ip22/war.h b/arch/mips/include/asm/mach-ip22/war.h
index a44fa9656a8..fba640517f4 100644
--- a/arch/mips/include/asm/mach-ip22/war.h
+++ b/arch/mips/include/asm/mach-ip22/war.h
@@ -21,7 +21,6 @@
21#define MIPS4K_ICACHE_REFILL_WAR 0 21#define MIPS4K_ICACHE_REFILL_WAR 0
22#define MIPS_CACHE_SYNC_WAR 0 22#define MIPS_CACHE_SYNC_WAR 0
23#define TX49XX_ICACHE_INDEX_INV_WAR 0 23#define TX49XX_ICACHE_INDEX_INV_WAR 0
24#define RM9000_CDEX_SMP_WAR 0
25#define ICACHE_REFILLS_WORKAROUND_WAR 0 24#define ICACHE_REFILLS_WORKAROUND_WAR 0
26#define R10000_LLSC_WAR 0 25#define R10000_LLSC_WAR 0
27#define MIPS34K_MISSED_ITLB_WAR 0 26#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-ip27/war.h b/arch/mips/include/asm/mach-ip27/war.h
index e2ddcc9b1ff..4ee0e4bdf4f 100644
--- a/arch/mips/include/asm/mach-ip27/war.h
+++ b/arch/mips/include/asm/mach-ip27/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 1 21#define R10000_LLSC_WAR 1
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-ip28/war.h b/arch/mips/include/asm/mach-ip28/war.h
index a1baafab486..4821c7b7a38 100644
--- a/arch/mips/include/asm/mach-ip28/war.h
+++ b/arch/mips/include/asm/mach-ip28/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 1 21#define R10000_LLSC_WAR 1
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-ip32/war.h b/arch/mips/include/asm/mach-ip32/war.h
index d194056dcd7..7237a935a13 100644
--- a/arch/mips/include/asm/mach-ip32/war.h
+++ b/arch/mips/include/asm/mach-ip32/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 1 20#define ICACHE_REFILLS_WORKAROUND_WAR 1
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-jazz/war.h b/arch/mips/include/asm/mach-jazz/war.h
index 6158ee861bf..5b18b9a3d0e 100644
--- a/arch/mips/include/asm/mach-jazz/war.h
+++ b/arch/mips/include/asm/mach-jazz/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-jz4740/war.h b/arch/mips/include/asm/mach-jz4740/war.h
index 3a5bc17e28f..9b511d32383 100644
--- a/arch/mips/include/asm/mach-jz4740/war.h
+++ b/arch/mips/include/asm/mach-jz4740/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-lantiq/war.h b/arch/mips/include/asm/mach-lantiq/war.h
index 01b08ef368d..b6c568c280e 100644
--- a/arch/mips/include/asm/mach-lantiq/war.h
+++ b/arch/mips/include/asm/mach-lantiq/war.h
@@ -16,7 +16,6 @@
16#define MIPS4K_ICACHE_REFILL_WAR 0 16#define MIPS4K_ICACHE_REFILL_WAR 0
17#define MIPS_CACHE_SYNC_WAR 0 17#define MIPS_CACHE_SYNC_WAR 0
18#define TX49XX_ICACHE_INDEX_INV_WAR 0 18#define TX49XX_ICACHE_INDEX_INV_WAR 0
19#define RM9000_CDEX_SMP_WAR 0
20#define ICACHE_REFILLS_WORKAROUND_WAR 0 19#define ICACHE_REFILLS_WORKAROUND_WAR 0
21#define R10000_LLSC_WAR 0 20#define R10000_LLSC_WAR 0
22#define MIPS34K_MISSED_ITLB_WAR 0 21#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-lasat/war.h b/arch/mips/include/asm/mach-lasat/war.h
index bb1e0325c9b..741ae724adc 100644
--- a/arch/mips/include/asm/mach-lasat/war.h
+++ b/arch/mips/include/asm/mach-lasat/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-loongson/war.h b/arch/mips/include/asm/mach-loongson/war.h
index 4b971c3ffd8..f2570df66bb 100644
--- a/arch/mips/include/asm/mach-loongson/war.h
+++ b/arch/mips/include/asm/mach-loongson/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-loongson1/war.h b/arch/mips/include/asm/mach-loongson1/war.h
index e3680a8fb34..8fb50d00813 100644
--- a/arch/mips/include/asm/mach-loongson1/war.h
+++ b/arch/mips/include/asm/mach-loongson1/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-malta/war.h b/arch/mips/include/asm/mach-malta/war.h
index 7c6931d5f45..d068fc411f4 100644
--- a/arch/mips/include/asm/mach-malta/war.h
+++ b/arch/mips/include/asm/mach-malta/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 1 17#define MIPS4K_ICACHE_REFILL_WAR 1
18#define MIPS_CACHE_SYNC_WAR 1 18#define MIPS_CACHE_SYNC_WAR 1
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 1 20#define ICACHE_REFILLS_WORKAROUND_WAR 1
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-netlogic/war.h b/arch/mips/include/asm/mach-netlogic/war.h
index 22da8932735..2c7216840e1 100644
--- a/arch/mips/include/asm/mach-netlogic/war.h
+++ b/arch/mips/include/asm/mach-netlogic/war.h
@@ -18,7 +18,6 @@
18#define MIPS4K_ICACHE_REFILL_WAR 0 18#define MIPS4K_ICACHE_REFILL_WAR 0
19#define MIPS_CACHE_SYNC_WAR 0 19#define MIPS_CACHE_SYNC_WAR 0
20#define TX49XX_ICACHE_INDEX_INV_WAR 0 20#define TX49XX_ICACHE_INDEX_INV_WAR 0
21#define RM9000_CDEX_SMP_WAR 0
22#define ICACHE_REFILLS_WORKAROUND_WAR 0 21#define ICACHE_REFILLS_WORKAROUND_WAR 0
23#define R10000_LLSC_WAR 0 22#define R10000_LLSC_WAR 0
24#define MIPS34K_MISSED_ITLB_WAR 0 23#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-pnx833x/war.h b/arch/mips/include/asm/mach-pnx833x/war.h
index 82cd1e97bc2..edaa06d9d49 100644
--- a/arch/mips/include/asm/mach-pnx833x/war.h
+++ b/arch/mips/include/asm/mach-pnx833x/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-pnx8550/war.h b/arch/mips/include/asm/mach-pnx8550/war.h
index d0458dd082f..de8894c4668 100644
--- a/arch/mips/include/asm/mach-pnx8550/war.h
+++ b/arch/mips/include/asm/mach-pnx8550/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-powertv/war.h b/arch/mips/include/asm/mach-powertv/war.h
index 7ac05ecc512..c5651c8e58d 100644
--- a/arch/mips/include/asm/mach-powertv/war.h
+++ b/arch/mips/include/asm/mach-powertv/war.h
@@ -20,7 +20,6 @@
20#define MIPS4K_ICACHE_REFILL_WAR 1 20#define MIPS4K_ICACHE_REFILL_WAR 1
21#define MIPS_CACHE_SYNC_WAR 1 21#define MIPS_CACHE_SYNC_WAR 1
22#define TX49XX_ICACHE_INDEX_INV_WAR 0 22#define TX49XX_ICACHE_INDEX_INV_WAR 0
23#define RM9000_CDEX_SMP_WAR 0
24#define ICACHE_REFILLS_WORKAROUND_WAR 1 23#define ICACHE_REFILLS_WORKAROUND_WAR 1
25#define R10000_LLSC_WAR 0 24#define R10000_LLSC_WAR 0
26#define MIPS34K_MISSED_ITLB_WAR 0 25#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-rc32434/war.h b/arch/mips/include/asm/mach-rc32434/war.h
index 3ddf187e98a..1bfd489a370 100644
--- a/arch/mips/include/asm/mach-rc32434/war.h
+++ b/arch/mips/include/asm/mach-rc32434/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 1 17#define MIPS4K_ICACHE_REFILL_WAR 1
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-rm/war.h b/arch/mips/include/asm/mach-rm/war.h
index 948d3129a11..a3dde98549b 100644
--- a/arch/mips/include/asm/mach-rm/war.h
+++ b/arch/mips/include/asm/mach-rm/war.h
@@ -21,7 +21,6 @@
21#define MIPS4K_ICACHE_REFILL_WAR 0 21#define MIPS4K_ICACHE_REFILL_WAR 0
22#define MIPS_CACHE_SYNC_WAR 0 22#define MIPS_CACHE_SYNC_WAR 0
23#define TX49XX_ICACHE_INDEX_INV_WAR 0 23#define TX49XX_ICACHE_INDEX_INV_WAR 0
24#define RM9000_CDEX_SMP_WAR 0
25#define ICACHE_REFILLS_WORKAROUND_WAR 0 24#define ICACHE_REFILLS_WORKAROUND_WAR 0
26#define R10000_LLSC_WAR 0 25#define R10000_LLSC_WAR 0
27#define MIPS34K_MISSED_ITLB_WAR 0 26#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-sead3/war.h b/arch/mips/include/asm/mach-sead3/war.h
index 7c6931d5f45..d068fc411f4 100644
--- a/arch/mips/include/asm/mach-sead3/war.h
+++ b/arch/mips/include/asm/mach-sead3/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 1 17#define MIPS4K_ICACHE_REFILL_WAR 1
18#define MIPS_CACHE_SYNC_WAR 1 18#define MIPS_CACHE_SYNC_WAR 1
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 1 20#define ICACHE_REFILLS_WORKAROUND_WAR 1
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-sibyte/war.h b/arch/mips/include/asm/mach-sibyte/war.h
index 743385d7b5f..176f5b32dc6 100644
--- a/arch/mips/include/asm/mach-sibyte/war.h
+++ b/arch/mips/include/asm/mach-sibyte/war.h
@@ -33,7 +33,6 @@ extern int sb1250_m3_workaround_needed(void);
33#define MIPS4K_ICACHE_REFILL_WAR 0 33#define MIPS4K_ICACHE_REFILL_WAR 0
34#define MIPS_CACHE_SYNC_WAR 0 34#define MIPS_CACHE_SYNC_WAR 0
35#define TX49XX_ICACHE_INDEX_INV_WAR 0 35#define TX49XX_ICACHE_INDEX_INV_WAR 0
36#define RM9000_CDEX_SMP_WAR 0
37#define ICACHE_REFILLS_WORKAROUND_WAR 0 36#define ICACHE_REFILLS_WORKAROUND_WAR 0
38#define R10000_LLSC_WAR 0 37#define R10000_LLSC_WAR 0
39#define MIPS34K_MISSED_ITLB_WAR 0 38#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-tx39xx/war.h b/arch/mips/include/asm/mach-tx39xx/war.h
index 43381461635..6a52e653477 100644
--- a/arch/mips/include/asm/mach-tx39xx/war.h
+++ b/arch/mips/include/asm/mach-tx39xx/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-tx49xx/war.h b/arch/mips/include/asm/mach-tx49xx/war.h
index 39b5d1177c5..a8e2c586a18 100644
--- a/arch/mips/include/asm/mach-tx49xx/war.h
+++ b/arch/mips/include/asm/mach-tx49xx/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 1 19#define TX49XX_ICACHE_INDEX_INV_WAR 1
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-vr41xx/war.h b/arch/mips/include/asm/mach-vr41xx/war.h
index 56a38926412..ffe31e73600 100644
--- a/arch/mips/include/asm/mach-vr41xx/war.h
+++ b/arch/mips/include/asm/mach-vr41xx/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-wrppmc/war.h b/arch/mips/include/asm/mach-wrppmc/war.h
index ac48629bb1c..e86084c0bd6 100644
--- a/arch/mips/include/asm/mach-wrppmc/war.h
+++ b/arch/mips/include/asm/mach-wrppmc/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 1 20#define ICACHE_REFILLS_WORKAROUND_WAR 1
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-yosemite/cpu-feature-overrides.h b/arch/mips/include/asm/mach-yosemite/cpu-feature-overrides.h
deleted file mode 100644
index 56bdd329860..00000000000
--- a/arch/mips/include/asm/mach-yosemite/cpu-feature-overrides.h
+++ /dev/null
@@ -1,48 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 04, 07 Ralf Baechle (ralf@linux-mips.org)
7 */
8#ifndef __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H
9#define __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H
10
11/*
12 * Momentum Jaguar ATX always has the RM9000 processor.
13 */
14#define cpu_has_watch 1
15#define cpu_has_mips16 0
16#define cpu_has_divec 0
17#define cpu_has_vce 0
18#define cpu_has_cache_cdex_p 0
19#define cpu_has_cache_cdex_s 0
20#define cpu_has_prefetch 1
21#define cpu_has_mcheck 0
22#define cpu_has_ejtag 0
23
24#define cpu_has_llsc 1
25#define cpu_has_vtag_icache 0
26#define cpu_has_dc_aliases 0
27#define cpu_has_ic_fills_f_dc 0
28#define cpu_has_dsp 0
29#define cpu_has_dsp2 0
30#define cpu_has_mipsmt 0
31#define cpu_has_userlocal 0
32#define cpu_icache_snoops_remote_store 0
33
34#define cpu_has_nofpuex 0
35#define cpu_has_64bits 1
36
37#define cpu_has_inclusive_pcaches 0
38
39#define cpu_dcache_line_size() 32
40#define cpu_icache_line_size() 32
41#define cpu_scache_line_size() 32
42
43#define cpu_has_mips32r1 0
44#define cpu_has_mips32r2 0
45#define cpu_has_mips64r1 0
46#define cpu_has_mips64r2 0
47
48#endif /* __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-yosemite/war.h b/arch/mips/include/asm/mach-yosemite/war.h
deleted file mode 100644
index e5c6d53efc8..00000000000
--- a/arch/mips/include/asm/mach-yosemite/war.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_YOSEMITE_WAR_H
9#define __ASM_MIPS_MACH_YOSEMITE_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 1
21#define ICACHE_REFILLS_WORKAROUND_WAR 1
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_YOSEMITE_WAR_H */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 881b980c72d..7e4e6f8fab3 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -977,10 +977,6 @@ do { \
977#define read_c0_framemask() __read_32bit_c0_register($21, 0) 977#define read_c0_framemask() __read_32bit_c0_register($21, 0)
978#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) 978#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
979 979
980/* RM9000 PerfControl performance counter control register */
981#define read_c0_perfcontrol() __read_32bit_c0_register($22, 0)
982#define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val)
983
984#define read_c0_diag() __read_32bit_c0_register($22, 0) 980#define read_c0_diag() __read_32bit_c0_register($22, 0)
985#define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) 981#define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
986 982
@@ -1033,10 +1029,6 @@ do { \
1033#define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7) 1029#define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
1034#define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val) 1030#define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1035 1031
1036/* RM9000 PerfCount performance counter register */
1037#define read_c0_perfcount() __read_64bit_c0_register($25, 0)
1038#define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val)
1039
1040#define read_c0_ecc() __read_32bit_c0_register($26, 0) 1032#define read_c0_ecc() __read_32bit_c0_register($26, 0)
1041#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) 1033#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
1042 1034
diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h
index 9b02cfba744..45cfa1ad86a 100644
--- a/arch/mips/include/asm/mmu_context.h
+++ b/arch/mips/include/asm/mmu_context.h
@@ -72,12 +72,6 @@ extern unsigned long pgd_current[];
72#define ASID_INC 0x10 72#define ASID_INC 0x10
73#define ASID_MASK 0xff0 73#define ASID_MASK 0xff0
74 74
75#elif defined(CONFIG_CPU_RM9000)
76
77#define ASID_INC 0x1
78#define ASID_MASK 0xfff
79
80/* SMTC/34K debug hack - but maybe we'll keep it */
81#elif defined(CONFIG_MIPS_MT_SMTC) 75#elif defined(CONFIG_MIPS_MT_SMTC)
82 76
83#define ASID_INC 0x1 77#define ASID_INC 0x1
diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h
index 26137da1c71..44b705d0826 100644
--- a/arch/mips/include/asm/module.h
+++ b/arch/mips/include/asm/module.h
@@ -120,8 +120,6 @@ search_module_dbetables(unsigned long addr)
120#define MODULE_PROC_FAMILY "R10000 " 120#define MODULE_PROC_FAMILY "R10000 "
121#elif defined CONFIG_CPU_RM7000 121#elif defined CONFIG_CPU_RM7000
122#define MODULE_PROC_FAMILY "RM7000 " 122#define MODULE_PROC_FAMILY "RM7000 "
123#elif defined CONFIG_CPU_RM9000
124#define MODULE_PROC_FAMILY "RM9000 "
125#elif defined CONFIG_CPU_SB1 123#elif defined CONFIG_CPU_SB1
126#define MODULE_PROC_FAMILY "SB1 " 124#define MODULE_PROC_FAMILY "SB1 "
127#elif defined CONFIG_CPU_LOONGSON1 125#elif defined CONFIG_CPU_LOONGSON1
diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
index 9ce1ac78244..f6a0439a408 100644
--- a/arch/mips/include/asm/pgtable-bits.h
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -235,20 +235,6 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
235#define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT) 235#define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
236#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) 236#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
237 237
238#elif defined(CONFIG_CPU_RM9000)
239
240#define _CACHE_WT (0<<_CACHE_SHIFT)
241#define _CACHE_WTWA (1<<_CACHE_SHIFT)
242#define _CACHE_UC_B (2<<_CACHE_SHIFT)
243#define _CACHE_WB (3<<_CACHE_SHIFT)
244#define _CACHE_CWBEA (4<<_CACHE_SHIFT)
245#define _CACHE_CWB (5<<_CACHE_SHIFT)
246#define _CACHE_UCNB (6<<_CACHE_SHIFT)
247#define _CACHE_FPC (7<<_CACHE_SHIFT)
248
249#define _CACHE_UNCACHED _CACHE_UC_B
250#define _CACHE_CACHABLE_NONCOHERENT _CACHE_WB
251
252#else 238#else
253 239
254#define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT) /* R4600 only */ 240#define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT) /* R4600 only */
diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/war.h b/arch/mips/include/asm/pmc-sierra/msp71xx/war.h
index 9e2ee429c52..c74eb1657f5 100644
--- a/arch/mips/include/asm/pmc-sierra/msp71xx/war.h
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/war.h
@@ -17,7 +17,6 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 20#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
23#if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \ 22#if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \
diff --git a/arch/mips/include/asm/titan_dep.h b/arch/mips/include/asm/titan_dep.h
deleted file mode 100644
index fee1908c65d..00000000000
--- a/arch/mips/include/asm/titan_dep.h
+++ /dev/null
@@ -1,231 +0,0 @@
1/*
2 * Copyright 2003 PMC-Sierra
3 * Author: Manish Lachwani (lachwani@pmc-sierra.com)
4 *
5 * Board specific definititions for the PMC-Sierra Yosemite
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#ifndef __TITAN_DEP_H__
14#define __TITAN_DEP_H__
15
16#include <asm/addrspace.h> /* for KSEG1ADDR() */
17#include <asm/byteorder.h> /* for cpu_to_le32() */
18
19#define TITAN_READ(ofs) \
20 (*(volatile u32 *)(ocd_base+(ofs)))
21#define TITAN_READ_16(ofs) \
22 (*(volatile u16 *)(ocd_base+(ofs)))
23#define TITAN_READ_8(ofs) \
24 (*(volatile u8 *)(ocd_base+(ofs)))
25
26#define TITAN_WRITE(ofs, data) \
27 do { *(volatile u32 *)(ocd_base+(ofs)) = (data); } while (0)
28#define TITAN_WRITE_16(ofs, data) \
29 do { *(volatile u16 *)(ocd_base+(ofs)) = (data); } while (0)
30#define TITAN_WRITE_8(ofs, data) \
31 do { *(volatile u8 *)(ocd_base+(ofs)) = (data); } while (0)
32
33/*
34 * PCI specific defines
35 */
36#define TITAN_PCI_0_CONFIG_ADDRESS 0x780
37#define TITAN_PCI_0_CONFIG_DATA 0x784
38
39/*
40 * HT specific defines
41 */
42#define RM9000x2_HTLINK_REG 0xbb000644
43#define RM9000x2_BASE_ADDR 0xbb000000
44
45#define OCD_BASE 0xfb000000UL
46#define OCD_SIZE 0x3000UL
47
48extern unsigned long ocd_base;
49
50/*
51 * OCD Registers
52 */
53#define RM9000x2_OCD_LKB5 0x0128 /* Ethernet */
54#define RM9000x2_OCD_LKM5 0x012c
55
56#define RM9000x2_OCD_LKB7 0x0138 /* HT Region 0 */
57#define RM9000x2_OCD_LKM7 0x013c
58#define RM9000x2_OCD_LKB8 0x0140 /* HT Region 1 */
59#define RM9000x2_OCD_LKM8 0x0144
60
61#define RM9000x2_OCD_LKB9 0x0148 /* Local Bus */
62#define RM9000x2_OCD_LKM9 0x014c
63#define RM9000x2_OCD_LKB10 0x0150
64#define RM9000x2_OCD_LKM10 0x0154
65#define RM9000x2_OCD_LKB11 0x0158
66#define RM9000x2_OCD_LKM11 0x015c
67#define RM9000x2_OCD_LKB12 0x0160
68#define RM9000x2_OCD_LKM12 0x0164
69
70#define RM9000x2_OCD_LKB13 0x0168 /* Scratch RAM */
71#define RM9000x2_OCD_LKM13 0x016c
72
73#define RM9000x2_OCD_LPD0 0x0200 /* Local Bus */
74#define RM9000x2_OCD_LPD1 0x0210
75#define RM9000x2_OCD_LPD2 0x0220
76#define RM9000x2_OCD_LPD3 0x0230
77
78#define RM9000x2_OCD_HTDVID 0x0600 /* HT Device Header */
79#define RM9000x2_OCD_HTSC 0x0604
80#define RM9000x2_OCD_HTCCR 0x0608
81#define RM9000x2_OCD_HTBHL 0x060c
82#define RM9000x2_OCD_HTBAR0 0x0610
83#define RM9000x2_OCD_HTBAR1 0x0614
84#define RM9000x2_OCD_HTBAR2 0x0618
85#define RM9000x2_OCD_HTBAR3 0x061c
86#define RM9000x2_OCD_HTBAR4 0x0620
87#define RM9000x2_OCD_HTBAR5 0x0624
88#define RM9000x2_OCD_HTCBCPT 0x0628
89#define RM9000x2_OCD_HTSDVID 0x062c
90#define RM9000x2_OCD_HTXRA 0x0630
91#define RM9000x2_OCD_HTCAP1 0x0634
92#define RM9000x2_OCD_HTIL 0x063c
93
94#define RM9000x2_OCD_HTLCC 0x0640 /* HT Capability Block */
95#define RM9000x2_OCD_HTLINK 0x0644
96#define RM9000x2_OCD_HTFQREV 0x0648
97
98#define RM9000x2_OCD_HTERCTL 0x0668 /* HT Controller */
99#define RM9000x2_OCD_HTRXDB 0x066c
100#define RM9000x2_OCD_HTIMPED 0x0670
101#define RM9000x2_OCD_HTSWIMP 0x0674
102#define RM9000x2_OCD_HTCAL 0x0678
103
104#define RM9000x2_OCD_HTBAA30 0x0680
105#define RM9000x2_OCD_HTBAA54 0x0684
106#define RM9000x2_OCD_HTMASK0 0x0688
107#define RM9000x2_OCD_HTMASK1 0x068c
108#define RM9000x2_OCD_HTMASK2 0x0690
109#define RM9000x2_OCD_HTMASK3 0x0694
110#define RM9000x2_OCD_HTMASK4 0x0698
111#define RM9000x2_OCD_HTMASK5 0x069c
112
113#define RM9000x2_OCD_HTIFCTL 0x06a0
114#define RM9000x2_OCD_HTPLL 0x06a4
115
116#define RM9000x2_OCD_HTSRI 0x06b0
117#define RM9000x2_OCD_HTRXNUM 0x06b4
118#define RM9000x2_OCD_HTTXNUM 0x06b8
119
120#define RM9000x2_OCD_HTTXCNT 0x06c8
121
122#define RM9000x2_OCD_HTERROR 0x06d8
123#define RM9000x2_OCD_HTRCRCE 0x06dc
124#define RM9000x2_OCD_HTEOI 0x06e0
125
126#define RM9000x2_OCD_CRCR 0x06f0
127
128#define RM9000x2_OCD_HTCFGA 0x06f8
129#define RM9000x2_OCD_HTCFGD 0x06fc
130
131#define RM9000x2_OCD_INTMSG 0x0a00
132
133#define RM9000x2_OCD_INTPIN0 0x0a40
134#define RM9000x2_OCD_INTPIN1 0x0a44
135#define RM9000x2_OCD_INTPIN2 0x0a48
136#define RM9000x2_OCD_INTPIN3 0x0a4c
137#define RM9000x2_OCD_INTPIN4 0x0a50
138#define RM9000x2_OCD_INTPIN5 0x0a54
139#define RM9000x2_OCD_INTPIN6 0x0a58
140#define RM9000x2_OCD_INTPIN7 0x0a5c
141#define RM9000x2_OCD_SEM 0x0a60
142#define RM9000x2_OCD_SEMSET 0x0a64
143#define RM9000x2_OCD_SEMCLR 0x0a68
144
145#define RM9000x2_OCD_TKT 0x0a70
146#define RM9000x2_OCD_TKTINC 0x0a74
147
148#define RM9000x2_OCD_NMICONFIG 0x0ac0 /* Interrupts */
149#define RM9000x2_OCD_INTP0PRI 0x1a80
150#define RM9000x2_OCD_INTP1PRI 0x1a80
151#define RM9000x2_OCD_INTP0STATUS0 0x1b00
152#define RM9000x2_OCD_INTP0MASK0 0x1b04
153#define RM9000x2_OCD_INTP0SET0 0x1b08
154#define RM9000x2_OCD_INTP0CLEAR0 0x1b0c
155#define RM9000x2_OCD_INTP0STATUS1 0x1b10
156#define RM9000x2_OCD_INTP0MASK1 0x1b14
157#define RM9000x2_OCD_INTP0SET1 0x1b18
158#define RM9000x2_OCD_INTP0CLEAR1 0x1b1c
159#define RM9000x2_OCD_INTP0STATUS2 0x1b20
160#define RM9000x2_OCD_INTP0MASK2 0x1b24
161#define RM9000x2_OCD_INTP0SET2 0x1b28
162#define RM9000x2_OCD_INTP0CLEAR2 0x1b2c
163#define RM9000x2_OCD_INTP0STATUS3 0x1b30
164#define RM9000x2_OCD_INTP0MASK3 0x1b34
165#define RM9000x2_OCD_INTP0SET3 0x1b38
166#define RM9000x2_OCD_INTP0CLEAR3 0x1b3c
167#define RM9000x2_OCD_INTP0STATUS4 0x1b40
168#define RM9000x2_OCD_INTP0MASK4 0x1b44
169#define RM9000x2_OCD_INTP0SET4 0x1b48
170#define RM9000x2_OCD_INTP0CLEAR4 0x1b4c
171#define RM9000x2_OCD_INTP0STATUS5 0x1b50
172#define RM9000x2_OCD_INTP0MASK5 0x1b54
173#define RM9000x2_OCD_INTP0SET5 0x1b58
174#define RM9000x2_OCD_INTP0CLEAR5 0x1b5c
175#define RM9000x2_OCD_INTP0STATUS6 0x1b60
176#define RM9000x2_OCD_INTP0MASK6 0x1b64
177#define RM9000x2_OCD_INTP0SET6 0x1b68
178#define RM9000x2_OCD_INTP0CLEAR6 0x1b6c
179#define RM9000x2_OCD_INTP0STATUS7 0x1b70
180#define RM9000x2_OCD_INTP0MASK7 0x1b74
181#define RM9000x2_OCD_INTP0SET7 0x1b78
182#define RM9000x2_OCD_INTP0CLEAR7 0x1b7c
183#define RM9000x2_OCD_INTP1STATUS0 0x2b00
184#define RM9000x2_OCD_INTP1MASK0 0x2b04
185#define RM9000x2_OCD_INTP1SET0 0x2b08
186#define RM9000x2_OCD_INTP1CLEAR0 0x2b0c
187#define RM9000x2_OCD_INTP1STATUS1 0x2b10
188#define RM9000x2_OCD_INTP1MASK1 0x2b14
189#define RM9000x2_OCD_INTP1SET1 0x2b18
190#define RM9000x2_OCD_INTP1CLEAR1 0x2b1c
191#define RM9000x2_OCD_INTP1STATUS2 0x2b20
192#define RM9000x2_OCD_INTP1MASK2 0x2b24
193#define RM9000x2_OCD_INTP1SET2 0x2b28
194#define RM9000x2_OCD_INTP1CLEAR2 0x2b2c
195#define RM9000x2_OCD_INTP1STATUS3 0x2b30
196#define RM9000x2_OCD_INTP1MASK3 0x2b34
197#define RM9000x2_OCD_INTP1SET3 0x2b38
198#define RM9000x2_OCD_INTP1CLEAR3 0x2b3c
199#define RM9000x2_OCD_INTP1STATUS4 0x2b40
200#define RM9000x2_OCD_INTP1MASK4 0x2b44
201#define RM9000x2_OCD_INTP1SET4 0x2b48
202#define RM9000x2_OCD_INTP1CLEAR4 0x2b4c
203#define RM9000x2_OCD_INTP1STATUS5 0x2b50
204#define RM9000x2_OCD_INTP1MASK5 0x2b54
205#define RM9000x2_OCD_INTP1SET5 0x2b58
206#define RM9000x2_OCD_INTP1CLEAR5 0x2b5c
207#define RM9000x2_OCD_INTP1STATUS6 0x2b60
208#define RM9000x2_OCD_INTP1MASK6 0x2b64
209#define RM9000x2_OCD_INTP1SET6 0x2b68
210#define RM9000x2_OCD_INTP1CLEAR6 0x2b6c
211#define RM9000x2_OCD_INTP1STATUS7 0x2b70
212#define RM9000x2_OCD_INTP1MASK7 0x2b74
213#define RM9000x2_OCD_INTP1SET7 0x2b78
214#define RM9000x2_OCD_INTP1CLEAR7 0x2b7c
215
216#define OCD_READ(reg) (*(volatile unsigned int *)(ocd_base + (reg)))
217#define OCD_WRITE(reg, val) \
218 do { *(volatile unsigned int *)(ocd_base + (reg)) = (val); } while (0)
219
220/*
221 * Hypertransport specific macros
222 */
223#define RM9K_WRITE(ofs, data) *(volatile u_int32_t *)(RM9000x2_BASE_ADDR+ofs) = data
224#define RM9K_WRITE_8(ofs, data) *(volatile u8 *)(RM9000x2_BASE_ADDR+ofs) = data
225#define RM9K_WRITE_16(ofs, data) *(volatile u16 *)(RM9000x2_BASE_ADDR+ofs) = data
226
227#define RM9K_READ(ofs, val) *(val) = *(volatile u_int32_t *)(RM9000x2_BASE_ADDR+ofs)
228#define RM9K_READ_8(ofs, val) *(val) = *(volatile u8 *)(RM9000x2_BASE_ADDR+ofs)
229#define RM9K_READ_16(ofs, val) *(val) = *(volatile u16 *)(RM9000x2_BASE_ADDR+ofs)
230
231#endif
diff --git a/arch/mips/include/asm/war.h b/arch/mips/include/asm/war.h
index fa133c1bc1f..65e344532de 100644
--- a/arch/mips/include/asm/war.h
+++ b/arch/mips/include/asm/war.h
@@ -209,14 +209,6 @@
209#endif 209#endif
210 210
211/* 211/*
212 * On the RM9000 there is a problem which makes the CreateDirtyExclusive
213 * eache operation unusable on SMP systems.
214 */
215#ifndef RM9000_CDEX_SMP_WAR
216#error Check setting of RM9000_CDEX_SMP_WAR for your platform
217#endif
218
219/*
220 * The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra 212 * The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
221 * opposes it being called that) where invalid instructions in the same 213 * opposes it being called that) where invalid instructions in the same
222 * I-cache line worth of instructions being fetched may case spurious 214 * I-cache line worth of instructions being fetched may case spurious
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 540dff8c721..007c33d7371 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -58,7 +58,6 @@ obj-$(CONFIG_MIPS_VPE_APSP_API) += rtlx.o
58obj-$(CONFIG_I8259) += i8259.o 58obj-$(CONFIG_I8259) += i8259.o
59obj-$(CONFIG_IRQ_CPU) += irq_cpu.o 59obj-$(CONFIG_IRQ_CPU) += irq_cpu.o
60obj-$(CONFIG_IRQ_CPU_RM7K) += irq-rm7000.o 60obj-$(CONFIG_IRQ_CPU_RM7K) += irq-rm7000.o
61obj-$(CONFIG_IRQ_CPU_RM9K) += irq-rm9000.o
62obj-$(CONFIG_MIPS_MSC) += irq-msc01.o 61obj-$(CONFIG_MIPS_MSC) += irq-msc01.o
63obj-$(CONFIG_IRQ_TXX9) += irq_txx9.o 62obj-$(CONFIG_IRQ_TXX9) += irq_txx9.o
64obj-$(CONFIG_IRQ_GT641XX) += irq-gt641xx.o 63obj-$(CONFIG_IRQ_GT641XX) += irq-gt641xx.o
diff --git a/arch/mips/kernel/irq-rm9000.c b/arch/mips/kernel/irq-rm9000.c
deleted file mode 100644
index 1282b9ae81c..00000000000
--- a/arch/mips/kernel/irq-rm9000.c
+++ /dev/null
@@ -1,106 +0,0 @@
1/*
2 * Copyright (C) 2003 Ralf Baechle
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * Handler for RM9000 extended interrupts. These are a non-standard
10 * feature so we handle them separately from standard interrupts.
11 */
12#include <linux/init.h>
13#include <linux/interrupt.h>
14#include <linux/irq.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17
18#include <asm/irq_cpu.h>
19#include <asm/mipsregs.h>
20
21static inline void unmask_rm9k_irq(struct irq_data *d)
22{
23 set_c0_intcontrol(0x1000 << (d->irq - RM9K_CPU_IRQ_BASE));
24}
25
26static inline void mask_rm9k_irq(struct irq_data *d)
27{
28 clear_c0_intcontrol(0x1000 << (d->irq - RM9K_CPU_IRQ_BASE));
29}
30
31static inline void rm9k_cpu_irq_enable(struct irq_data *d)
32{
33 unsigned long flags;
34
35 local_irq_save(flags);
36 unmask_rm9k_irq(d);
37 local_irq_restore(flags);
38}
39
40/*
41 * Performance counter interrupts are global on all processors.
42 */
43static void local_rm9k_perfcounter_irq_startup(void *args)
44{
45 rm9k_cpu_irq_enable(args);
46}
47
48static unsigned int rm9k_perfcounter_irq_startup(struct irq_data *d)
49{
50 on_each_cpu(local_rm9k_perfcounter_irq_startup, d, 1);
51
52 return 0;
53}
54
55static void local_rm9k_perfcounter_irq_shutdown(void *args)
56{
57 unsigned long flags;
58
59 local_irq_save(flags);
60 mask_rm9k_irq(args);
61 local_irq_restore(flags);
62}
63
64static void rm9k_perfcounter_irq_shutdown(struct irq_data *d)
65{
66 on_each_cpu(local_rm9k_perfcounter_irq_shutdown, d, 1);
67}
68
69static struct irq_chip rm9k_irq_controller = {
70 .name = "RM9000",
71 .irq_ack = mask_rm9k_irq,
72 .irq_mask = mask_rm9k_irq,
73 .irq_mask_ack = mask_rm9k_irq,
74 .irq_unmask = unmask_rm9k_irq,
75 .irq_eoi = unmask_rm9k_irq
76};
77
78static struct irq_chip rm9k_perfcounter_irq = {
79 .name = "RM9000",
80 .irq_startup = rm9k_perfcounter_irq_startup,
81 .irq_shutdown = rm9k_perfcounter_irq_shutdown,
82 .irq_ack = mask_rm9k_irq,
83 .irq_mask = mask_rm9k_irq,
84 .irq_mask_ack = mask_rm9k_irq,
85 .irq_unmask = unmask_rm9k_irq,
86};
87
88unsigned int rm9000_perfcount_irq;
89
90EXPORT_SYMBOL(rm9000_perfcount_irq);
91
92void __init rm9k_cpu_irq_init(void)
93{
94 int base = RM9K_CPU_IRQ_BASE;
95 int i;
96
97 clear_c0_intcontrol(0x0000f000); /* Mask all */
98
99 for (i = base; i < base + 4; i++)
100 irq_set_chip_and_handler(i, &rm9k_irq_controller,
101 handle_level_irq);
102
103 rm9000_perfcount_irq = base + 1;
104 irq_set_chip_and_handler(rm9000_perfcount_irq, &rm9k_perfcounter_irq,
105 handle_percpu_irq);
106}
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 2b6146241bd..d2b5b0c7afa 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -936,7 +936,6 @@ static void __cpuinit probe_pcache(void)
936 case CPU_RM7000: 936 case CPU_RM7000:
937 rm7k_erratum31(); 937 rm7k_erratum31();
938 938
939 case CPU_RM9000:
940 icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); 939 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
941 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 940 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
942 c->icache.ways = 4; 941 c->icache.ways = 4;
@@ -947,9 +946,7 @@ static void __cpuinit probe_pcache(void)
947 c->dcache.ways = 4; 946 c->dcache.ways = 4;
948 c->dcache.waybit = __ffs(dcache_size / c->dcache.ways); 947 c->dcache.waybit = __ffs(dcache_size / c->dcache.ways);
949 948
950#if !defined(CONFIG_SMP) || !defined(RM9000_CDEX_SMP_WAR)
951 c->options |= MIPS_CPU_CACHE_CDEX_P; 949 c->options |= MIPS_CPU_CACHE_CDEX_P;
952#endif
953 c->options |= MIPS_CPU_PREFETCH; 950 c->options |= MIPS_CPU_PREFETCH;
954 break; 951 break;
955 952
@@ -1234,7 +1231,6 @@ static void __cpuinit setup_scache(void)
1234 return; 1231 return;
1235 1232
1236 case CPU_RM7000: 1233 case CPU_RM7000:
1237 case CPU_RM9000:
1238#ifdef CONFIG_RM7000_CPU_SCACHE 1234#ifdef CONFIG_RM7000_CPU_SCACHE
1239 rm7k_sc_init(); 1235 rm7k_sc_init();
1240#endif 1236#endif
diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c
index 98f530e1821..8e666c55f4d 100644
--- a/arch/mips/mm/page.c
+++ b/arch/mips/mm/page.c
@@ -140,15 +140,6 @@ static void __cpuinit set_prefetch_parameters(void)
140 pref_bias_copy_load = 256; 140 pref_bias_copy_load = 256;
141 break; 141 break;
142 142
143 case CPU_RM9000:
144 /*
145 * As a workaround for erratum G105 which make the
146 * PrepareForStore hint unusable we fall back to
147 * StoreRetained on the RM9000. Once it is known which
148 * versions of the RM9000 we'll be able to condition-
149 * alize this.
150 */
151
152 case CPU_R10000: 143 case CPU_R10000:
153 case CPU_R12000: 144 case CPU_R12000:
154 case CPU_R14000: 145 case CPU_R14000:
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 6af62a2fec2..69a357254e4 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -603,24 +603,6 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
603 tlbw(p); 603 tlbw(p);
604 break; 604 break;
605 605
606 case CPU_RM9000:
607 /*
608 * When the JTLB is updated by tlbwi or tlbwr, a subsequent
609 * use of the JTLB for instructions should not occur for 4
610 * cpu cycles and use for data translations should not occur
611 * for 3 cpu cycles.
612 */
613 uasm_i_ssnop(p);
614 uasm_i_ssnop(p);
615 uasm_i_ssnop(p);
616 uasm_i_ssnop(p);
617 tlbw(p);
618 uasm_i_ssnop(p);
619 uasm_i_ssnop(p);
620 uasm_i_ssnop(p);
621 uasm_i_ssnop(p);
622 break;
623
624 case CPU_VR4111: 606 case CPU_VR4111:
625 case CPU_VR4121: 607 case CPU_VR4121:
626 case CPU_VR4122: 608 case CPU_VR4122:
diff --git a/arch/mips/oprofile/Makefile b/arch/mips/oprofile/Makefile
index 1208c280f77..8232dbd1228 100644
--- a/arch/mips/oprofile/Makefile
+++ b/arch/mips/oprofile/Makefile
@@ -12,5 +12,4 @@ oprofile-$(CONFIG_CPU_MIPS32) += op_model_mipsxx.o
12oprofile-$(CONFIG_CPU_MIPS64) += op_model_mipsxx.o 12oprofile-$(CONFIG_CPU_MIPS64) += op_model_mipsxx.o
13oprofile-$(CONFIG_CPU_R10000) += op_model_mipsxx.o 13oprofile-$(CONFIG_CPU_R10000) += op_model_mipsxx.o
14oprofile-$(CONFIG_CPU_SB1) += op_model_mipsxx.o 14oprofile-$(CONFIG_CPU_SB1) += op_model_mipsxx.o
15oprofile-$(CONFIG_CPU_RM9000) += op_model_rm9000.o
16oprofile-$(CONFIG_CPU_LOONGSON2) += op_model_loongson2.o 15oprofile-$(CONFIG_CPU_LOONGSON2) += op_model_loongson2.o
diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c
index f80480a5a03..be387faef87 100644
--- a/arch/mips/oprofile/common.c
+++ b/arch/mips/oprofile/common.c
@@ -16,7 +16,6 @@
16#include "op_impl.h" 16#include "op_impl.h"
17 17
18extern struct op_mips_model op_model_mipsxx_ops __weak; 18extern struct op_mips_model op_model_mipsxx_ops __weak;
19extern struct op_mips_model op_model_rm9000_ops __weak;
20extern struct op_mips_model op_model_loongson2_ops __weak; 19extern struct op_mips_model op_model_loongson2_ops __weak;
21 20
22static struct op_mips_model *model; 21static struct op_mips_model *model;
@@ -94,9 +93,6 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
94 lmodel = &op_model_mipsxx_ops; 93 lmodel = &op_model_mipsxx_ops;
95 break; 94 break;
96 95
97 case CPU_RM9000:
98 lmodel = &op_model_rm9000_ops;
99 break;
100 case CPU_LOONGSON2: 96 case CPU_LOONGSON2:
101 lmodel = &op_model_loongson2_ops; 97 lmodel = &op_model_loongson2_ops;
102 break; 98 break;
diff --git a/arch/mips/oprofile/op_model_rm9000.c b/arch/mips/oprofile/op_model_rm9000.c
deleted file mode 100644
index 3aa81384966..00000000000
--- a/arch/mips/oprofile/op_model_rm9000.c
+++ /dev/null
@@ -1,138 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004 by Ralf Baechle
7 */
8#include <linux/init.h>
9#include <linux/oprofile.h>
10#include <linux/interrupt.h>
11#include <linux/smp.h>
12
13#include "op_impl.h"
14
15#define RM9K_COUNTER1_EVENT(event) ((event) << 0)
16#define RM9K_COUNTER1_SUPERVISOR (1ULL << 7)
17#define RM9K_COUNTER1_KERNEL (1ULL << 8)
18#define RM9K_COUNTER1_USER (1ULL << 9)
19#define RM9K_COUNTER1_ENABLE (1ULL << 10)
20#define RM9K_COUNTER1_OVERFLOW (1ULL << 15)
21
22#define RM9K_COUNTER2_EVENT(event) ((event) << 16)
23#define RM9K_COUNTER2_SUPERVISOR (1ULL << 23)
24#define RM9K_COUNTER2_KERNEL (1ULL << 24)
25#define RM9K_COUNTER2_USER (1ULL << 25)
26#define RM9K_COUNTER2_ENABLE (1ULL << 26)
27#define RM9K_COUNTER2_OVERFLOW (1ULL << 31)
28
29extern unsigned int rm9000_perfcount_irq;
30
31static struct rm9k_register_config {
32 unsigned int control;
33 unsigned int reset_counter1;
34 unsigned int reset_counter2;
35} reg;
36
37/* Compute all of the registers in preparation for enabling profiling. */
38
39static void rm9000_reg_setup(struct op_counter_config *ctr)
40{
41 unsigned int control = 0;
42
43 /* Compute the performance counter control word. */
44 /* For now count kernel and user mode */
45 if (ctr[0].enabled)
46 control |= RM9K_COUNTER1_EVENT(ctr[0].event) |
47 RM9K_COUNTER1_KERNEL |
48 RM9K_COUNTER1_USER |
49 RM9K_COUNTER1_ENABLE;
50 if (ctr[1].enabled)
51 control |= RM9K_COUNTER2_EVENT(ctr[1].event) |
52 RM9K_COUNTER2_KERNEL |
53 RM9K_COUNTER2_USER |
54 RM9K_COUNTER2_ENABLE;
55 reg.control = control;
56
57 reg.reset_counter1 = 0x80000000 - ctr[0].count;
58 reg.reset_counter2 = 0x80000000 - ctr[1].count;
59}
60
61/* Program all of the registers in preparation for enabling profiling. */
62
63static void rm9000_cpu_setup(void *args)
64{
65 uint64_t perfcount;
66
67 perfcount = ((uint64_t) reg.reset_counter2 << 32) | reg.reset_counter1;
68 write_c0_perfcount(perfcount);
69}
70
71static void rm9000_cpu_start(void *args)
72{
73 /* Start all counters on current CPU */
74 write_c0_perfcontrol(reg.control);
75}
76
77static void rm9000_cpu_stop(void *args)
78{
79 /* Stop all counters on current CPU */
80 write_c0_perfcontrol(0);
81}
82
83static irqreturn_t rm9000_perfcount_handler(int irq, void *dev_id)
84{
85 unsigned int control = read_c0_perfcontrol();
86 struct pt_regs *regs = get_irq_regs();
87 uint32_t counter1, counter2;
88 uint64_t counters;
89
90 /*
91 * RM9000 combines two 32-bit performance counters into a single
92 * 64-bit coprocessor zero register. To avoid a race updating the
93 * registers we need to stop the counters while we're messing with
94 * them ...
95 */
96 write_c0_perfcontrol(0);
97
98 counters = read_c0_perfcount();
99 counter1 = counters;
100 counter2 = counters >> 32;
101
102 if (control & RM9K_COUNTER1_OVERFLOW) {
103 oprofile_add_sample(regs, 0);
104 counter1 = reg.reset_counter1;
105 }
106 if (control & RM9K_COUNTER2_OVERFLOW) {
107 oprofile_add_sample(regs, 1);
108 counter2 = reg.reset_counter2;
109 }
110
111 counters = ((uint64_t)counter2 << 32) | counter1;
112 write_c0_perfcount(counters);
113 write_c0_perfcontrol(reg.control);
114
115 return IRQ_HANDLED;
116}
117
118static int __init rm9000_init(void)
119{
120 return request_irq(rm9000_perfcount_irq, rm9000_perfcount_handler,
121 0, "Perfcounter", NULL);
122}
123
124static void rm9000_exit(void)
125{
126 free_irq(rm9000_perfcount_irq, NULL);
127}
128
129struct op_mips_model op_model_rm9000_ops = {
130 .reg_setup = rm9000_reg_setup,
131 .cpu_setup = rm9000_cpu_setup,
132 .init = rm9000_init,
133 .exit = rm9000_exit,
134 .cpu_start = rm9000_cpu_start,
135 .cpu_stop = rm9000_cpu_stop,
136 .cpu_type = "mips/rm9000",
137 .num_counters = 2
138};
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index e13a71cbc3c..ce995d3d944 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -34,8 +34,6 @@ obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o
34obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o 34obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o
35obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o 35obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o
36obj-$(CONFIG_PMC_MSP7120_FPGA) += fixup-pmcmsp.o ops-pmcmsp.o 36obj-$(CONFIG_PMC_MSP7120_FPGA) += fixup-pmcmsp.o ops-pmcmsp.o
37obj-$(CONFIG_PMC_YOSEMITE) += fixup-yosemite.o ops-titan.o ops-titan-ht.o \
38 pci-yosemite.o
39obj-$(CONFIG_SGI_IP27) += ops-bridge.o pci-ip27.o 37obj-$(CONFIG_SGI_IP27) += ops-bridge.o pci-ip27.o
40obj-$(CONFIG_SGI_IP32) += fixup-ip32.o ops-mace.o pci-ip32.o 38obj-$(CONFIG_SGI_IP32) += fixup-ip32.o ops-mace.o pci-ip32.o
41obj-$(CONFIG_SIBYTE_SB1250) += fixup-sb1250.o pci-sb1250.o 39obj-$(CONFIG_SIBYTE_SB1250) += fixup-sb1250.o pci-sb1250.o
diff --git a/arch/mips/pci/fixup-yosemite.c b/arch/mips/pci/fixup-yosemite.c
deleted file mode 100644
index fdafb13a793..00000000000
--- a/arch/mips/pci/fixup-yosemite.c
+++ /dev/null
@@ -1,41 +0,0 @@
1/*
2 * Copyright 2003 PMC-Sierra
3 * Author: Manish Lachwani (lachwani@pmc-sierra.com)
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25#include <linux/kernel.h>
26#include <linux/init.h>
27#include <linux/pci.h>
28
29int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
30{
31 if (pin == 0)
32 return -1;
33
34 return 3; /* Everything goes to one irq bit */
35}
36
37/* Do platform specific device initialization at pci_enable_device() time */
38int pcibios_plat_dev_init(struct pci_dev *dev)
39{
40 return 0;
41}
diff --git a/arch/mips/pci/ops-titan-ht.c b/arch/mips/pci/ops-titan-ht.c
deleted file mode 100644
index 57d54adc9e2..00000000000
--- a/arch/mips/pci/ops-titan-ht.c
+++ /dev/null
@@ -1,124 +0,0 @@
1/*
2 * Copyright 2003 PMC-Sierra
3 * Author: Manish Lachwani (lachwani@pmc-sierra.com)
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26#include <linux/types.h>
27#include <linux/pci.h>
28#include <linux/kernel.h>
29#include <linux/delay.h>
30#include <asm/io.h>
31
32#include <asm/titan_dep.h>
33
34static int titan_ht_config_read_dword(struct pci_bus *bus, unsigned int devfn,
35 int offset, u32 *val)
36{
37 volatile uint32_t address;
38 int busno;
39
40 busno = bus->number;
41
42 address = (busno << 16) | (devfn << 8) | (offset & 0xfc) | 0x80000000;
43 if (busno != 0)
44 address |= 1;
45
46 /*
47 * RM9000 HT Errata: Issue back to back HT config
48 * transcations. Issue a BIU sync before and
49 * after the HT cycle
50 */
51
52 *(volatile int32_t *) 0xfb0000f0 |= 0x2;
53
54 udelay(30);
55
56 *(volatile int32_t *) 0xfb0006f8 = address;
57 *(val) = *(volatile int32_t *) 0xfb0006fc;
58
59 udelay(30);
60
61 * (volatile int32_t *) 0xfb0000f0 |= 0x2;
62
63 return PCIBIOS_SUCCESSFUL;
64}
65
66static int titan_ht_config_read(struct pci_bus *bus, unsigned int devfn,
67 int offset, int size, u32 *val)
68{
69 uint32_t dword;
70
71 titan_ht_config_read_dword(bus, devfn, offset, &dword);
72
73 dword >>= ((offset & 3) << 3);
74 dword &= (0xffffffffU >> ((4 - size) << 8));
75
76 return PCIBIOS_SUCCESSFUL;
77}
78
79static inline int titan_ht_config_write_dword(struct pci_bus *bus,
80 unsigned int devfn, int offset, u32 val)
81{
82 volatile uint32_t address;
83 int busno;
84
85 busno = bus->number;
86
87 address = (busno << 16) | (devfn << 8) | (offset & 0xfc) | 0x80000000;
88 if (busno != 0)
89 address |= 1;
90
91 *(volatile int32_t *) 0xfb0000f0 |= 0x2;
92
93 udelay(30);
94
95 *(volatile int32_t *) 0xfb0006f8 = address;
96 *(volatile int32_t *) 0xfb0006fc = val;
97
98 udelay(30);
99
100 *(volatile int32_t *) 0xfb0000f0 |= 0x2;
101
102 return PCIBIOS_SUCCESSFUL;
103}
104
105static int titan_ht_config_write(struct pci_bus *bus, unsigned int devfn,
106 int offset, int size, u32 val)
107{
108 uint32_t val1, val2, mask;
109
110 titan_ht_config_read_dword(bus, devfn, offset, &val2);
111
112 val1 = val << ((offset & 3) << 3);
113 mask = ~(0xffffffffU >> ((4 - size) << 8));
114 val2 &= ~(mask << ((offset & 3) << 8));
115
116 titan_ht_config_write_dword(bus, devfn, offset, val1 | val2);
117
118 return PCIBIOS_SUCCESSFUL;
119}
120
121struct pci_ops titan_ht_pci_ops = {
122 .read = titan_ht_config_read,
123 .write = titan_ht_config_write,
124};
diff --git a/arch/mips/pci/ops-titan.c b/arch/mips/pci/ops-titan.c
deleted file mode 100644
index ebf8fc40e9b..00000000000
--- a/arch/mips/pci/ops-titan.c
+++ /dev/null
@@ -1,111 +0,0 @@
1/*
2 * Copyright 2003 PMC-Sierra
3 * Author: Manish Lachwani (lachwani@pmc-sierra.com)
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25#include <linux/types.h>
26#include <linux/pci.h>
27#include <linux/kernel.h>
28
29#include <asm/pci.h>
30#include <asm/io.h>
31#include <asm/rm9k-ocd.h>
32
33/*
34 * PCI specific defines
35 */
36#define TITAN_PCI_0_CONFIG_ADDRESS 0x780
37#define TITAN_PCI_0_CONFIG_DATA 0x784
38
39/*
40 * Titan PCI Config Read Byte
41 */
42static int titan_read_config(struct pci_bus *bus, unsigned int devfn, int reg,
43 int size, u32 * val)
44{
45 uint32_t address, tmp;
46 int dev, busno, func;
47
48 busno = bus->number;
49 dev = PCI_SLOT(devfn);
50 func = PCI_FUNC(devfn);
51
52 address = (busno << 16) | (dev << 11) | (func << 8) |
53 (reg & 0xfc) | 0x80000000;
54
55
56 /* start the configuration cycle */
57 ocd_writel(address, TITAN_PCI_0_CONFIG_ADDRESS);
58 tmp = ocd_readl(TITAN_PCI_0_CONFIG_DATA) >> ((reg & 3) << 3);
59
60 switch (size) {
61 case 1:
62 tmp &= 0xff;
63 case 2:
64 tmp &= 0xffff;
65 }
66 *val = tmp;
67
68 return PCIBIOS_SUCCESSFUL;
69}
70
71static int titan_write_config(struct pci_bus *bus, unsigned int devfn, int reg,
72 int size, u32 val)
73{
74 uint32_t address;
75 int dev, busno, func;
76
77 busno = bus->number;
78 dev = PCI_SLOT(devfn);
79 func = PCI_FUNC(devfn);
80
81 address = (busno << 16) | (dev << 11) | (func << 8) |
82 (reg & 0xfc) | 0x80000000;
83
84 /* start the configuration cycle */
85 ocd_writel(address, TITAN_PCI_0_CONFIG_ADDRESS);
86
87 /* write the data */
88 switch (size) {
89 case 1:
90 ocd_writeb(val, TITAN_PCI_0_CONFIG_DATA + (~reg & 0x3));
91 break;
92
93 case 2:
94 ocd_writew(val, TITAN_PCI_0_CONFIG_DATA + (~reg & 0x2));
95 break;
96
97 case 4:
98 ocd_writel(val, TITAN_PCI_0_CONFIG_DATA);
99 break;
100 }
101
102 return PCIBIOS_SUCCESSFUL;
103}
104
105/*
106 * Titan PCI structure
107 */
108struct pci_ops titan_pci_ops = {
109 titan_read_config,
110 titan_write_config,
111};
diff --git a/arch/mips/pci/pci-yosemite.c b/arch/mips/pci/pci-yosemite.c
deleted file mode 100644
index cf5e1a25cb7..00000000000
--- a/arch/mips/pci/pci-yosemite.c
+++ /dev/null
@@ -1,67 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
7 */
8#include <linux/init.h>
9#include <linux/kernel.h>
10#include <linux/types.h>
11#include <linux/pci.h>
12#include <asm/titan_dep.h>
13
14extern struct pci_ops titan_pci_ops;
15
16static struct resource py_mem_resource = {
17 .start = 0xe0000000UL,
18 .end = 0xe3ffffffUL,
19 .name = "Titan PCI MEM",
20 .flags = IORESOURCE_MEM
21};
22
23/*
24 * PMON really reserves 16MB of I/O port space but that's stupid, nothing
25 * needs that much since allocations are limited to 256 bytes per device
26 * anyway. So we just claim 64kB here.
27 */
28#define TITAN_IO_SIZE 0x0000ffffUL
29#define TITAN_IO_BASE 0xe8000000UL
30
31static struct resource py_io_resource = {
32 .start = 0x00001000UL,
33 .end = TITAN_IO_SIZE - 1,
34 .name = "Titan IO MEM",
35 .flags = IORESOURCE_IO,
36};
37
38static struct pci_controller py_controller = {
39 .pci_ops = &titan_pci_ops,
40 .mem_resource = &py_mem_resource,
41 .mem_offset = 0x00000000UL,
42 .io_resource = &py_io_resource,
43 .io_offset = 0x00000000UL
44};
45
46static char ioremap_failed[] __initdata = "Could not ioremap I/O port range";
47
48static int __init pmc_yosemite_setup(void)
49{
50 unsigned long io_v_base;
51
52 io_v_base = (unsigned long) ioremap(TITAN_IO_BASE, TITAN_IO_SIZE);
53 if (!io_v_base)
54 panic(ioremap_failed);
55
56 set_io_port_base(io_v_base);
57 py_controller.io_map_base = io_v_base;
58 TITAN_WRITE(RM9000x2_OCD_LKM7, TITAN_READ(RM9000x2_OCD_LKM7) | 1);
59
60 ioport_resource.end = TITAN_IO_SIZE - 1;
61
62 register_pci_controller(&py_controller);
63
64 return 0;
65}
66
67arch_initcall(pmc_yosemite_setup);
diff --git a/arch/mips/pmc-sierra/Kconfig b/arch/mips/pmc-sierra/Kconfig
index bbd76082fa8..3482b8c8640 100644
--- a/arch/mips/pmc-sierra/Kconfig
+++ b/arch/mips/pmc-sierra/Kconfig
@@ -34,10 +34,6 @@ config PMC_MSP7120_FPGA
34 34
35endchoice 35endchoice
36 36
37config HYPERTRANSPORT
38 bool "Hypertransport Support for PMC-Sierra Yosemite"
39 depends on PMC_YOSEMITE
40
41config MSP_HAS_USB 37config MSP_HAS_USB
42 boolean 38 boolean
43 depends on PMC_MSP 39 depends on PMC_MSP
diff --git a/arch/mips/pmc-sierra/Platform b/arch/mips/pmc-sierra/Platform
index f092f2524c5..387fda6c28c 100644
--- a/arch/mips/pmc-sierra/Platform
+++ b/arch/mips/pmc-sierra/Platform
@@ -5,10 +5,3 @@ platform-$(CONFIG_PMC_MSP) += pmc-sierra/msp71xx/
5cflags-$(CONFIG_PMC_MSP) += -I$(srctree)/arch/mips/include/asm/pmc-sierra/msp71xx \ 5cflags-$(CONFIG_PMC_MSP) += -I$(srctree)/arch/mips/include/asm/pmc-sierra/msp71xx \
6 -mno-branch-likely 6 -mno-branch-likely
7load-$(CONFIG_PMC_MSP) += 0xffffffff80100000 7load-$(CONFIG_PMC_MSP) += 0xffffffff80100000
8
9#
10# PMC-Sierra Yosemite
11#
12platform-$(CONFIG_PMC_YOSEMITE) += pmc-sierra/yosemite/
13cflags-$(CONFIG_PMC_YOSEMITE) += -I$(srctree)/arch/mips/include/asm/mach-yosemite
14load-$(CONFIG_PMC_YOSEMITE) += 0xffffffff80100000
diff --git a/arch/mips/pmc-sierra/yosemite/Makefile b/arch/mips/pmc-sierra/yosemite/Makefile
deleted file mode 100644
index 5af95ec3319..00000000000
--- a/arch/mips/pmc-sierra/yosemite/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
1#
2# Makefile for the PMC-Sierra Titan
3#
4
5obj-y += irq.o prom.o py-console.o setup.o
6
7obj-$(CONFIG_SMP) += smp.o
diff --git a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c
deleted file mode 100644
index d6f8bdff8cb..00000000000
--- a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c
+++ /dev/null
@@ -1,169 +0,0 @@
1/*
2 * Copyright (C) 2003 PMC-Sierra Inc.
3 * Author: Manish Lachwani (lachwani@pmc-sierra.com)
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26/*
27 * Description:
28 *
29 * This code reads the ATMEL 24CXX EEPROM. The PMC-Sierra Yosemite board uses the ATMEL
30 * 24C32/24C64 which uses two byte addressing as compared to 24C16. Note that this program
31 * uses the serial port like /dev/ttyS0, to communicate with the EEPROM. Hence, you are
32 * expected to have a connectivity from the EEPROM to the serial port. This program does
33 * __not__ communicate using the I2C protocol
34 */
35
36#include "atmel_read_eeprom.h"
37
38static void delay(int delay)
39{
40 while (delay--);
41}
42
43static void send_bit(unsigned char bit)
44{
45 scl_lo;
46 delay(TXX);
47 if (bit)
48 sda_hi;
49 else
50 sda_lo;
51
52 delay(TXX);
53 scl_hi;
54 delay(TXX);
55}
56
57static void send_ack(void)
58{
59 send_bit(0);
60}
61
62static void send_byte(unsigned char byte)
63{
64 int i = 0;
65
66 for (i = 7; i >= 0; i--)
67 send_bit((byte >> i) & 0x01);
68}
69
70static void send_start(void)
71{
72 sda_hi;
73 delay(TXX);
74 scl_hi;
75 delay(TXX);
76 sda_lo;
77 delay(TXX);
78}
79
80static void send_stop(void)
81{
82 sda_lo;
83 delay(TXX);
84 scl_hi;
85 delay(TXX);
86 sda_hi;
87 delay(TXX);
88}
89
90static void do_idle(void)
91{
92 sda_hi;
93 scl_hi;
94 vcc_off;
95}
96
97static int recv_bit(void)
98{
99 int status;
100
101 scl_lo;
102 delay(TXX);
103 sda_hi;
104 delay(TXX);
105 scl_hi;
106 delay(TXX);
107
108 return 1;
109}
110
111static unsigned char recv_byte(void) {
112 int i;
113 unsigned char byte=0;
114
115 for (i=7;i>=0;i--)
116 byte |= (recv_bit() << i);
117
118 return byte;
119}
120
121static int recv_ack(void)
122{
123 unsigned int ack;
124
125 ack = (unsigned int)recv_bit();
126 scl_lo;
127
128 if (ack) {
129 do_idle();
130 printk(KERN_ERR "Error reading the Atmel 24C32/24C64 EEPROM\n");
131 return -1;
132 }
133
134 return ack;
135}
136
137/*
138 * This function does the actual read of the EEPROM. It needs the buffer into which the
139 * read data is copied, the size of the EEPROM being read and the buffer size
140 */
141int read_eeprom(char *buffer, int eeprom_size, int size)
142{
143 int i = 0, err;
144
145 send_start();
146 send_byte(W_HEADER);
147 recv_ack();
148
149 /* EEPROM with size of more than 2K need two byte addressing */
150 if (eeprom_size > 2048) {
151 send_byte(0x00);
152 recv_ack();
153 }
154
155 send_start();
156 send_byte(R_HEADER);
157 err = recv_ack();
158 if (err == -1)
159 return err;
160
161 for (i = 0; i < size; i++) {
162 *buffer++ = recv_byte();
163 send_ack();
164 }
165
166 /* Note : We should do some check if the buffer contains correct information */
167
168 send_stop();
169}
diff --git a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h
deleted file mode 100644
index d6c7ec469fa..00000000000
--- a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h
+++ /dev/null
@@ -1,67 +0,0 @@
1/*
2 * arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c
3 *
4 * Copyright (C) 2003 PMC-Sierra Inc.
5 * Author: Manish Lachwani (lachwani@pmc-sierra.com)
6 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29/*
30 * Header file for atmel_read_eeprom.c
31 */
32
33#include <linux/types.h>
34#include <linux/pci.h>
35#include <linux/kernel.h>
36#include <linux/slab.h>
37#include <asm/pci.h>
38#include <asm/io.h>
39#include <linux/init.h>
40#include <asm/termios.h>
41#include <asm/ioctls.h>
42#include <linux/ioctl.h>
43#include <linux/fcntl.h>
44
45#define DEFAULT_PORT "/dev/ttyS0" /* Port to open */
46#define TXX 0 /* Dummy loop for spinning */
47
48#define BLOCK_SEL 0x00
49#define SLAVE_ADDR 0xa0
50#define READ_BIT 0x01
51#define WRITE_BIT 0x00
52#define R_HEADER SLAVE_ADDR + BLOCK_SEL + READ_BIT
53#define W_HEADER SLAVE_ADDR + BLOCK_SEL + WRITE_BIT
54
55/*
56 * Clock, Voltages and Data
57 */
58#define vcc_off (ioctl(fd, TIOCSBRK, 0))
59#define vcc_on (ioctl(fd, TIOCCBRK, 0))
60#define sda_hi (ioctl(fd, TIOCMBIS, &dtr))
61#define sda_lo (ioctl(fd, TIOCMBIC, &dtr))
62#define scl_lo (ioctl(fd, TIOCMBIC, &rts))
63#define scl_hi (ioctl(fd, TIOCMBIS, &rts))
64
65const char rts = TIOCM_RTS;
66const char dtr = TIOCM_DTR;
67int fd;
diff --git a/arch/mips/pmc-sierra/yosemite/ht-irq.c b/arch/mips/pmc-sierra/yosemite/ht-irq.c
deleted file mode 100644
index 62ead6601c6..00000000000
--- a/arch/mips/pmc-sierra/yosemite/ht-irq.c
+++ /dev/null
@@ -1,41 +0,0 @@
1/*
2 * Copyright 2003 PMC-Sierra
3 * Author: Manish Lachwani (lachwani@pmc-sierra.com)
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26#include <linux/types.h>
27#include <linux/pci.h>
28#include <linux/kernel.h>
29#include <linux/init.h>
30#include <asm/pci.h>
31
32/*
33 * HT Bus fixup for the Titan
34 * XXX IRQ values need to change based on the board layout
35 */
36void __init titan_ht_pcibios_fixup_bus(struct pci_bus *bus)
37{
38 /*
39 * PLX and SPKT related changes go here
40 */
41}
diff --git a/arch/mips/pmc-sierra/yosemite/ht.c b/arch/mips/pmc-sierra/yosemite/ht.c
deleted file mode 100644
index 14dc9c8fff0..00000000000
--- a/arch/mips/pmc-sierra/yosemite/ht.c
+++ /dev/null
@@ -1,404 +0,0 @@
1/*
2 * Copyright 2003 PMC-Sierra
3 * Author: Manish Lachwani (lachwani@pmc-sierra.com)
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26#include <linux/types.h>
27#include <linux/pci.h>
28#include <linux/kernel.h>
29#include <asm/pci.h>
30#include <asm/io.h>
31
32#include <linux/init.h>
33#include <asm/titan_dep.h>
34
35#ifdef CONFIG_HYPERTRANSPORT
36
37
38/*
39 * This function check if the Hypertransport Link Initialization completed. If
40 * it did, then proceed further with scanning bus #2
41 */
42static __inline__ int check_titan_htlink(void)
43{
44 u32 val;
45
46 val = *(volatile uint32_t *)(RM9000x2_HTLINK_REG);
47 if (val & 0x00000020)
48 /* HT Link Initialization completed */
49 return 1;
50 else
51 return 0;
52}
53
54static int titan_ht_config_read_dword(struct pci_dev *device,
55 int offset, u32* val)
56{
57 int dev, bus, func;
58 uint32_t address_reg, data_reg;
59 uint32_t address;
60
61 bus = device->bus->number;
62 dev = PCI_SLOT(device->devfn);
63 func = PCI_FUNC(device->devfn);
64
65 /* XXX Need to change the Bus # */
66 if (bus > 2)
67 address = (bus << 16) | (dev << 11) | (func << 8) | (offset & 0xfc) |
68 0x80000000 | 0x1;
69 else
70 address = (dev << 11) | (func << 8) | (offset & 0xfc) | 0x80000000;
71
72 address_reg = RM9000x2_OCD_HTCFGA;
73 data_reg = RM9000x2_OCD_HTCFGD;
74
75 RM9K_WRITE(address_reg, address);
76 RM9K_READ(data_reg, val);
77
78 return PCIBIOS_SUCCESSFUL;
79}
80
81
82static int titan_ht_config_read_word(struct pci_dev *device,
83 int offset, u16* val)
84{
85 int dev, bus, func;
86 uint32_t address_reg, data_reg;
87 uint32_t address;
88
89 bus = device->bus->number;
90 dev = PCI_SLOT(device->devfn);
91 func = PCI_FUNC(device->devfn);
92
93 /* XXX Need to change the Bus # */
94 if (bus > 2)
95 address = (bus << 16) | (dev << 11) | (func << 8) | (offset & 0xfc) |
96 0x80000000 | 0x1;
97 else
98 address = (dev << 11) | (func << 8) | (offset & 0xfc) | 0x80000000;
99
100 address_reg = RM9000x2_OCD_HTCFGA;
101 data_reg = RM9000x2_OCD_HTCFGD;
102
103 if ((offset & 0x3) == 0)
104 offset = 0x2;
105 else
106 offset = 0x0;
107
108 RM9K_WRITE(address_reg, address);
109 RM9K_READ_16(data_reg + offset, val);
110
111 return PCIBIOS_SUCCESSFUL;
112}
113
114
115u32 longswap(unsigned long l)
116{
117 unsigned char b1, b2, b3, b4;
118
119 b1 = l&255;
120 b2 = (l>>8)&255;
121 b3 = (l>>16)&255;
122 b4 = (l>>24)&255;
123
124 return ((b1<<24) + (b2<<16) + (b3<<8) + b4);
125}
126
127
128static int titan_ht_config_read_byte(struct pci_dev *device,
129 int offset, u8* val)
130{
131 int dev, bus, func;
132 uint32_t address_reg, data_reg;
133 uint32_t address;
134 int offset1;
135
136 bus = device->bus->number;
137 dev = PCI_SLOT(device->devfn);
138 func = PCI_FUNC(device->devfn);
139
140 /* XXX Need to change the Bus # */
141 if (bus > 2)
142 address = (bus << 16) | (dev << 11) | (func << 8) | (offset & 0xfc) |
143 0x80000000 | 0x1;
144 else
145 address = (dev << 11) | (func << 8) | (offset & 0xfc) | 0x80000000;
146
147 address_reg = RM9000x2_OCD_HTCFGA;
148 data_reg = RM9000x2_OCD_HTCFGD;
149
150 RM9K_WRITE(address_reg, address);
151
152 if ((offset & 0x3) == 0) {
153 offset1 = 0x3;
154 }
155 if ((offset & 0x3) == 1) {
156 offset1 = 0x2;
157 }
158 if ((offset & 0x3) == 2) {
159 offset1 = 0x1;
160 }
161 if ((offset & 0x3) == 3) {
162 offset1 = 0x0;
163 }
164 RM9K_READ_8(data_reg + offset1, val);
165
166 return PCIBIOS_SUCCESSFUL;
167}
168
169
170static int titan_ht_config_write_dword(struct pci_dev *device,
171 int offset, u8 val)
172{
173 int dev, bus, func;
174 uint32_t address_reg, data_reg;
175 uint32_t address;
176
177 bus = device->bus->number;
178 dev = PCI_SLOT(device->devfn);
179 func = PCI_FUNC(device->devfn);
180
181 /* XXX Need to change the Bus # */
182 if (bus > 2)
183 address = (bus << 16) | (dev << 11) | (func << 8) | (offset & 0xfc) |
184 0x80000000 | 0x1;
185 else
186 address = (dev << 11) | (func << 8) | (offset & 0xfc) | 0x80000000;
187
188 address_reg = RM9000x2_OCD_HTCFGA;
189 data_reg = RM9000x2_OCD_HTCFGD;
190
191 RM9K_WRITE(address_reg, address);
192 RM9K_WRITE(data_reg, val);
193
194 return PCIBIOS_SUCCESSFUL;
195}
196
197static int titan_ht_config_write_word(struct pci_dev *device,
198 int offset, u8 val)
199{
200 int dev, bus, func;
201 uint32_t address_reg, data_reg;
202 uint32_t address;
203
204 bus = device->bus->number;
205 dev = PCI_SLOT(device->devfn);
206 func = PCI_FUNC(device->devfn);
207
208 /* XXX Need to change the Bus # */
209 if (bus > 2)
210 address = (bus << 16) | (dev << 11) | (func << 8) | (offset & 0xfc) |
211 0x80000000 | 0x1;
212 else
213 address = (dev << 11) | (func << 8) | (offset & 0xfc) | 0x80000000;
214
215 address_reg = RM9000x2_OCD_HTCFGA;
216 data_reg = RM9000x2_OCD_HTCFGD;
217
218 if ((offset & 0x3) == 0)
219 offset = 0x2;
220 else
221 offset = 0x0;
222
223 RM9K_WRITE(address_reg, address);
224 RM9K_WRITE_16(data_reg + offset, val);
225
226 return PCIBIOS_SUCCESSFUL;
227}
228
229static int titan_ht_config_write_byte(struct pci_dev *device,
230 int offset, u8 val)
231{
232 int dev, bus, func;
233 uint32_t address_reg, data_reg;
234 uint32_t address;
235 int offset1;
236
237 bus = device->bus->number;
238 dev = PCI_SLOT(device->devfn);
239 func = PCI_FUNC(device->devfn);
240
241 /* XXX Need to change the Bus # */
242 if (bus > 2)
243 address = (bus << 16) | (dev << 11) | (func << 8) | (offset & 0xfc) |
244 0x80000000 | 0x1;
245 else
246 address = (dev << 11) | (func << 8) | (offset & 0xfc) | 0x80000000;
247
248 address_reg = RM9000x2_OCD_HTCFGA;
249 data_reg = RM9000x2_OCD_HTCFGD;
250
251 RM9K_WRITE(address_reg, address);
252
253 if ((offset & 0x3) == 0) {
254 offset1 = 0x3;
255 }
256 if ((offset & 0x3) == 1) {
257 offset1 = 0x2;
258 }
259 if ((offset & 0x3) == 2) {
260 offset1 = 0x1;
261 }
262 if ((offset & 0x3) == 3) {
263 offset1 = 0x0;
264 }
265
266 RM9K_WRITE_8(data_reg + offset1, val);
267 return PCIBIOS_SUCCESSFUL;
268}
269
270
271static void titan_pcibios_set_master(struct pci_dev *dev)
272{
273 u16 cmd;
274 int bus = dev->bus->number;
275
276 if (check_titan_htlink())
277 titan_ht_config_read_word(dev, PCI_COMMAND, &cmd);
278
279 cmd |= PCI_COMMAND_MASTER;
280
281 if (check_titan_htlink())
282 titan_ht_config_write_word(dev, PCI_COMMAND, cmd);
283}
284
285
286int pcibios_enable_resources(struct pci_dev *dev)
287{
288 u16 cmd, old_cmd;
289 u8 tmp1;
290 int idx;
291 struct resource *r;
292 int bus = dev->bus->number;
293
294 if (check_titan_htlink())
295 titan_ht_config_read_word(dev, PCI_COMMAND, &cmd);
296
297 old_cmd = cmd;
298 for (idx = 0; idx < 6; idx++) {
299 r = &dev->resource[idx];
300 if (!r->start && r->end) {
301 printk(KERN_ERR
302 "PCI: Device %s not available because of "
303 "resource collisions\n", pci_name(dev));
304 return -EINVAL;
305 }
306 if (r->flags & IORESOURCE_IO)
307 cmd |= PCI_COMMAND_IO;
308 if (r->flags & IORESOURCE_MEM)
309 cmd |= PCI_COMMAND_MEMORY;
310 }
311 if (cmd != old_cmd) {
312 if (check_titan_htlink())
313 titan_ht_config_write_word(dev, PCI_COMMAND, cmd);
314 }
315
316 if (check_titan_htlink())
317 titan_ht_config_read_byte(dev, PCI_CACHE_LINE_SIZE, &tmp1);
318
319 if (tmp1 != 8) {
320 printk(KERN_WARNING "PCI setting cache line size to 8 from "
321 "%d\n", tmp1);
322 }
323
324 if (check_titan_htlink())
325 titan_ht_config_write_byte(dev, PCI_CACHE_LINE_SIZE, 8);
326
327 if (check_titan_htlink())
328 titan_ht_config_read_byte(dev, PCI_LATENCY_TIMER, &tmp1);
329
330 if (tmp1 < 32 || tmp1 == 0xff) {
331 printk(KERN_WARNING "PCI setting latency timer to 32 from %d\n",
332 tmp1);
333 }
334
335 if (check_titan_htlink())
336 titan_ht_config_write_byte(dev, PCI_LATENCY_TIMER, 32);
337
338 return 0;
339}
340
341
342int pcibios_enable_device(struct pci_dev *dev, int mask)
343{
344 return pcibios_enable_resources(dev);
345}
346
347resource_size_t pcibios_align_resource(void *data, const struct resource *res,
348 resource_size_t size, resource_size_t align)
349{
350 struct pci_dev *dev = data;
351 resource_size_t start = res->start;
352
353 if (res->flags & IORESOURCE_IO) {
354 /* We need to avoid collisions with `mirrored' VGA ports
355 and other strange ISA hardware, so we always want the
356 addresses kilobyte aligned. */
357 if (size > 0x100) {
358 printk(KERN_ERR "PCI: I/O Region %s/%d too large"
359 " (%ld bytes)\n", pci_name(dev),
360 dev->resource - res, size);
361 }
362
363 start = (start + 1024 - 1) & ~(1024 - 1);
364 }
365
366 return start;
367}
368
369struct pci_ops titan_pci_ops = {
370 titan_ht_config_read_byte,
371 titan_ht_config_read_word,
372 titan_ht_config_read_dword,
373 titan_ht_config_write_byte,
374 titan_ht_config_write_word,
375 titan_ht_config_write_dword
376};
377
378void __init pcibios_fixup_bus(struct pci_bus *c)
379{
380 titan_ht_pcibios_fixup_bus(c);
381}
382
383void __init pcibios_init(void)
384{
385
386 /* Reset PCI I/O and PCI MEM values */
387 /* XXX Need to add the proper values here */
388 ioport_resource.start = 0xe0000000;
389 ioport_resource.end = 0xe0000000 + 0x20000000 - 1;
390 iomem_resource.start = 0xc0000000;
391 iomem_resource.end = 0xc0000000 + 0x20000000 - 1;
392
393 /* XXX Need to add bus values */
394 pci_scan_bus(2, &titan_pci_ops, NULL);
395 pci_scan_bus(3, &titan_pci_ops, NULL);
396}
397
398unsigned __init int pcibios_assign_all_busses(void)
399{
400 /* We want to use the PCI bus detection done by PMON */
401 return 0;
402}
403
404#endif /* CONFIG_HYPERTRANSPORT */
diff --git a/arch/mips/pmc-sierra/yosemite/irq.c b/arch/mips/pmc-sierra/yosemite/irq.c
deleted file mode 100644
index 6590812daa5..00000000000
--- a/arch/mips/pmc-sierra/yosemite/irq.c
+++ /dev/null
@@ -1,152 +0,0 @@
1/*
2 * Copyright (C) 2003 PMC-Sierra Inc.
3 * Author: Manish Lachwani (lachwani@pmc-sierra.com)
4 *
5 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 *
27 * Second level Interrupt handlers for the PMC-Sierra Titan/Yosemite board
28 */
29#include <linux/errno.h>
30#include <linux/init.h>
31#include <linux/kernel_stat.h>
32#include <linux/module.h>
33#include <linux/signal.h>
34#include <linux/sched.h>
35#include <linux/types.h>
36#include <linux/interrupt.h>
37#include <linux/ioport.h>
38#include <linux/irq.h>
39#include <linux/timex.h>
40#include <linux/random.h>
41#include <linux/bitops.h>
42#include <asm/bootinfo.h>
43#include <asm/io.h>
44#include <asm/irq.h>
45#include <asm/irq_cpu.h>
46#include <asm/mipsregs.h>
47#include <asm/titan_dep.h>
48
49/* Hypertransport specific */
50#define IRQ_ACK_BITS 0x00000000 /* Ack bits */
51
52#define HYPERTRANSPORT_INTA 0x78 /* INTA# */
53#define HYPERTRANSPORT_INTB 0x79 /* INTB# */
54#define HYPERTRANSPORT_INTC 0x7a /* INTC# */
55#define HYPERTRANSPORT_INTD 0x7b /* INTD# */
56
57extern void titan_mailbox_irq(void);
58
59#ifdef CONFIG_HYPERTRANSPORT
60/*
61 * Handle hypertransport & SMP interrupts. The interrupt lines are scarce.
62 * For interprocessor interrupts, the best thing to do is to use the INTMSG
63 * register. We use the same external interrupt line, i.e. INTB3 and monitor
64 * another status bit
65 */
66static void ll_ht_smp_irq_handler(int irq)
67{
68 u32 status = OCD_READ(RM9000x2_OCD_INTP0STATUS4);
69
70 /* Ack all the bits that correspond to the interrupt sources */
71 if (status != 0)
72 OCD_WRITE(RM9000x2_OCD_INTP0STATUS4, IRQ_ACK_BITS);
73
74 status = OCD_READ(RM9000x2_OCD_INTP1STATUS4);
75 if (status != 0)
76 OCD_WRITE(RM9000x2_OCD_INTP1STATUS4, IRQ_ACK_BITS);
77
78#ifdef CONFIG_HT_LEVEL_TRIGGER
79 /*
80 * Level Trigger Mode only. Send the HT EOI message back to the source.
81 */
82 switch (status) {
83 case 0x1000000:
84 OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTA);
85 break;
86 case 0x2000000:
87 OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTB);
88 break;
89 case 0x4000000:
90 OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTC);
91 break;
92 case 0x8000000:
93 OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTD);
94 break;
95 case 0x0000001:
96 /* PLX */
97 OCD_WRITE(RM9000x2_OCD_HTEOI, 0x20);
98 OCD_WRITE(IRQ_CLEAR_REG, IRQ_ACK_BITS);
99 break;
100 case 0xf000000:
101 OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTA);
102 OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTB);
103 OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTC);
104 OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTD);
105 break;
106 }
107#endif /* CONFIG_HT_LEVEL_TRIGGER */
108
109 do_IRQ(irq);
110}
111#endif
112
113asmlinkage void plat_irq_dispatch(void)
114{
115 unsigned int cause = read_c0_cause();
116 unsigned int status = read_c0_status();
117 unsigned int pending = cause & status;
118
119 if (pending & STATUSF_IP7) {
120 do_IRQ(7);
121 } else if (pending & STATUSF_IP2) {
122#ifdef CONFIG_HYPERTRANSPORT
123 ll_ht_smp_irq_handler(2);
124#else
125 do_IRQ(2);
126#endif
127 } else if (pending & STATUSF_IP3) {
128 do_IRQ(3);
129 } else if (pending & STATUSF_IP4) {
130 do_IRQ(4);
131 } else if (pending & STATUSF_IP5) {
132#ifdef CONFIG_SMP
133 titan_mailbox_irq();
134#else
135 do_IRQ(5);
136#endif
137 } else if (pending & STATUSF_IP6) {
138 do_IRQ(4);
139 }
140}
141
142/*
143 * Initialize the next level interrupt handler
144 */
145void __init arch_init_irq(void)
146{
147 clear_c0_status(ST0_IM);
148
149 mips_cpu_irq_init();
150 rm7k_cpu_irq_init();
151 rm9k_cpu_irq_init();
152}
diff --git a/arch/mips/pmc-sierra/yosemite/prom.c b/arch/mips/pmc-sierra/yosemite/prom.c
deleted file mode 100644
index 6a2754c4f10..00000000000
--- a/arch/mips/pmc-sierra/yosemite/prom.c
+++ /dev/null
@@ -1,142 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * Copyright (C) 2003, 2004 PMC-Sierra Inc.
8 * Author: Manish Lachwani (lachwani@pmc-sierra.com)
9 * Copyright (C) 2004 Ralf Baechle
10 */
11#include <linux/init.h>
12#include <linux/sched.h>
13#include <linux/mm.h>
14#include <linux/delay.h>
15#include <linux/pm.h>
16#include <linux/smp.h>
17
18#include <asm/io.h>
19#include <asm/pgtable.h>
20#include <asm/processor.h>
21#include <asm/reboot.h>
22#include <asm/smp-ops.h>
23#include <asm/bootinfo.h>
24#include <asm/pmon.h>
25
26#ifdef CONFIG_SMP
27extern void prom_grab_secondary(void);
28#else
29#define prom_grab_secondary() do { } while (0)
30#endif
31
32#include "setup.h"
33
34struct callvectors *debug_vectors;
35
36extern unsigned long yosemite_base;
37extern unsigned long cpu_clock_freq;
38
39const char *get_system_type(void)
40{
41 return "PMC-Sierra Yosemite";
42}
43
44static void prom_cpu0_exit(void *arg)
45{
46 void *nvram = (void *) YOSEMITE_RTC_BASE;
47
48 /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */
49 writeb(0x84, nvram + 0xff7);
50
51 /* wait for the watchdog to go off */
52 mdelay(100 + (1000 / 16));
53
54 /* if the watchdog fails for some reason, let people know */
55 printk(KERN_NOTICE "Watchdog reset failed\n");
56}
57
58/*
59 * Reset the NVRAM over the local bus
60 */
61static void prom_exit(void)
62{
63#ifdef CONFIG_SMP
64 if (smp_processor_id())
65 /* CPU 1 */
66 smp_call_function(prom_cpu0_exit, NULL, 1);
67#endif
68 prom_cpu0_exit(NULL);
69}
70
71/*
72 * Halt the system
73 */
74static void prom_halt(void)
75{
76 printk(KERN_NOTICE "\n** You can safely turn off the power\n");
77 while (1)
78 __asm__(".set\tmips3\n\t" "wait\n\t" ".set\tmips0");
79}
80
81extern struct plat_smp_ops yos_smp_ops;
82
83/*
84 * Init routine which accepts the variables from PMON
85 */
86void __init prom_init(void)
87{
88 int argc = fw_arg0;
89 char **arg = (char **) fw_arg1;
90 char **env = (char **) fw_arg2;
91 struct callvectors *cv = (struct callvectors *) fw_arg3;
92 int i = 0;
93
94 /* Callbacks for halt, restart */
95 _machine_restart = (void (*)(char *)) prom_exit;
96 _machine_halt = prom_halt;
97 pm_power_off = prom_halt;
98
99 debug_vectors = cv;
100 arcs_cmdline[0] = '\0';
101
102 /* Get the boot parameters */
103 for (i = 1; i < argc; i++) {
104 if (strlen(arcs_cmdline) + strlen(arg[i]) + 1 >=
105 sizeof(arcs_cmdline))
106 break;
107
108 strcat(arcs_cmdline, arg[i]);
109 strcat(arcs_cmdline, " ");
110 }
111
112#ifdef CONFIG_SERIAL_8250_CONSOLE
113 if ((strstr(arcs_cmdline, "console=ttyS")) == NULL)
114 strcat(arcs_cmdline, "console=ttyS0,115200");
115#endif
116
117 while (*env) {
118 if (strncmp("ocd_base", *env, strlen("ocd_base")) == 0)
119 yosemite_base =
120 simple_strtol(*env + strlen("ocd_base="), NULL,
121 16);
122
123 if (strncmp("cpuclock", *env, strlen("cpuclock")) == 0)
124 cpu_clock_freq =
125 simple_strtol(*env + strlen("cpuclock="), NULL,
126 10);
127
128 env++;
129 }
130
131 prom_grab_secondary();
132
133 register_smp_ops(&yos_smp_ops);
134}
135
136void __init prom_free_prom_memory(void)
137{
138}
139
140void __init prom_fixup_mem_map(unsigned long start, unsigned long end)
141{
142}
diff --git a/arch/mips/pmc-sierra/yosemite/py-console.c b/arch/mips/pmc-sierra/yosemite/py-console.c
deleted file mode 100644
index b7f1d9c4a8a..00000000000
--- a/arch/mips/pmc-sierra/yosemite/py-console.c
+++ /dev/null
@@ -1,109 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2001, 2002, 2004 Ralf Baechle
7 */
8#include <linux/init.h>
9#include <linux/console.h>
10#include <linux/kdev_t.h>
11#include <linux/major.h>
12#include <linux/termios.h>
13#include <linux/sched.h>
14#include <linux/tty.h>
15
16#include <linux/serial.h>
17#include <linux/serial_core.h>
18#include <asm/serial.h>
19#include <asm/io.h>
20
21/* SUPERIO uart register map */
22struct yo_uartregs {
23 union {
24 volatile u8 rbr; /* read only, DLAB == 0 */
25 volatile u8 thr; /* write only, DLAB == 0 */
26 volatile u8 dll; /* DLAB == 1 */
27 } u1;
28 union {
29 volatile u8 ier; /* DLAB == 0 */
30 volatile u8 dlm; /* DLAB == 1 */
31 } u2;
32 union {
33 volatile u8 iir; /* read only */
34 volatile u8 fcr; /* write only */
35 } u3;
36 volatile u8 iu_lcr;
37 volatile u8 iu_mcr;
38 volatile u8 iu_lsr;
39 volatile u8 iu_msr;
40 volatile u8 iu_scr;
41} yo_uregs_t;
42
43#define iu_rbr u1.rbr
44#define iu_thr u1.thr
45#define iu_dll u1.dll
46#define iu_ier u2.ier
47#define iu_dlm u2.dlm
48#define iu_iir u3.iir
49#define iu_fcr u3.fcr
50
51#define ssnop() __asm__ __volatile__("sll $0, $0, 1\n");
52#define ssnop_4() do { ssnop(); ssnop(); ssnop(); ssnop(); } while (0)
53
54#define IO_BASE_64 0x9000000000000000ULL
55
56static unsigned char readb_outer_space(unsigned long long phys)
57{
58 unsigned long long vaddr = IO_BASE_64 | phys;
59 unsigned char res;
60 unsigned int sr;
61
62 sr = read_c0_status();
63 write_c0_status((sr | ST0_KX) & ~ ST0_IE);
64 ssnop_4();
65
66 __asm__ __volatile__ (
67 " .set mips3 \n"
68 " ld %0, %1 \n"
69 " lbu %0, (%0) \n"
70 " .set mips0 \n"
71 : "=r" (res)
72 : "m" (vaddr));
73
74 write_c0_status(sr);
75 ssnop_4();
76
77 return res;
78}
79
80static void writeb_outer_space(unsigned long long phys, unsigned char c)
81{
82 unsigned long long vaddr = IO_BASE_64 | phys;
83 unsigned long tmp;
84 unsigned int sr;
85
86 sr = read_c0_status();
87 write_c0_status((sr | ST0_KX) & ~ ST0_IE);
88 ssnop_4();
89
90 __asm__ __volatile__ (
91 " .set mips3 \n"
92 " ld %0, %1 \n"
93 " sb %2, (%0) \n"
94 " .set mips0 \n"
95 : "=&r" (tmp)
96 : "m" (vaddr), "r" (c));
97
98 write_c0_status(sr);
99 ssnop_4();
100}
101
102void prom_putchar(char c)
103{
104 unsigned long lsr = 0xfd000008ULL + offsetof(struct yo_uartregs, iu_lsr);
105 unsigned long thr = 0xfd000008ULL + offsetof(struct yo_uartregs, iu_thr);
106
107 while ((readb_outer_space(lsr) & 0x20) == 0);
108 writeb_outer_space(thr, c);
109}
diff --git a/arch/mips/pmc-sierra/yosemite/setup.c b/arch/mips/pmc-sierra/yosemite/setup.c
deleted file mode 100644
index b6472fc88a9..00000000000
--- a/arch/mips/pmc-sierra/yosemite/setup.c
+++ /dev/null
@@ -1,224 +0,0 @@
1/*
2 * Copyright (C) 2003 PMC-Sierra Inc.
3 * Author: Manish Lachwani (lachwani@pmc-sierra.com)
4 *
5 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27#include <linux/bcd.h>
28#include <linux/init.h>
29#include <linux/kernel.h>
30#include <linux/export.h>
31#include <linux/types.h>
32#include <linux/mm.h>
33#include <linux/bootmem.h>
34#include <linux/swap.h>
35#include <linux/ioport.h>
36#include <linux/sched.h>
37#include <linux/interrupt.h>
38#include <linux/timex.h>
39#include <linux/termios.h>
40#include <linux/tty.h>
41#include <linux/serial.h>
42#include <linux/serial_core.h>
43#include <linux/serial_8250.h>
44
45#include <asm/time.h>
46#include <asm/bootinfo.h>
47#include <asm/page.h>
48#include <asm/io.h>
49#include <asm/irq.h>
50#include <asm/processor.h>
51#include <asm/reboot.h>
52#include <asm/serial.h>
53#include <asm/titan_dep.h>
54#include <asm/m48t37.h>
55
56#include "setup.h"
57
58unsigned char titan_ge_mac_addr_base[6] = {
59 // 0x00, 0x03, 0xcc, 0x1d, 0x22, 0x00
60 0x00, 0xe0, 0x04, 0x00, 0x00, 0x21
61};
62
63unsigned long cpu_clock_freq;
64unsigned long yosemite_base;
65
66static struct m48t37_rtc *m48t37_base;
67
68void __init bus_error_init(void)
69{
70 /* Do nothing */
71}
72
73
74void read_persistent_clock(struct timespec *ts)
75{
76 unsigned int year, month, day, hour, min, sec;
77 unsigned long flags;
78
79 spin_lock_irqsave(&rtc_lock, flags);
80 /* Stop the update to the time */
81 m48t37_base->control = 0x40;
82
83 year = bcd2bin(m48t37_base->year);
84 year += bcd2bin(m48t37_base->century) * 100;
85
86 month = bcd2bin(m48t37_base->month);
87 day = bcd2bin(m48t37_base->date);
88 hour = bcd2bin(m48t37_base->hour);
89 min = bcd2bin(m48t37_base->min);
90 sec = bcd2bin(m48t37_base->sec);
91
92 /* Start the update to the time again */
93 m48t37_base->control = 0x00;
94 spin_unlock_irqrestore(&rtc_lock, flags);
95
96 ts->tv_sec = mktime(year, month, day, hour, min, sec);
97 ts->tv_nsec = 0;
98}
99
100int rtc_mips_set_time(unsigned long tim)
101{
102 struct rtc_time tm;
103 unsigned long flags;
104
105 /*
106 * Convert to a more useful format -- note months count from 0
107 * and years from 1900
108 */
109 rtc_time_to_tm(tim, &tm);
110 tm.tm_year += 1900;
111 tm.tm_mon += 1;
112
113 spin_lock_irqsave(&rtc_lock, flags);
114 /* enable writing */
115 m48t37_base->control = 0x80;
116
117 /* year */
118 m48t37_base->year = bin2bcd(tm.tm_year % 100);
119 m48t37_base->century = bin2bcd(tm.tm_year / 100);
120
121 /* month */
122 m48t37_base->month = bin2bcd(tm.tm_mon);
123
124 /* day */
125 m48t37_base->date = bin2bcd(tm.tm_mday);
126
127 /* hour/min/sec */
128 m48t37_base->hour = bin2bcd(tm.tm_hour);
129 m48t37_base->min = bin2bcd(tm.tm_min);
130 m48t37_base->sec = bin2bcd(tm.tm_sec);
131
132 /* day of week -- not really used, but let's keep it up-to-date */
133 m48t37_base->day = bin2bcd(tm.tm_wday + 1);
134
135 /* disable writing */
136 m48t37_base->control = 0x00;
137 spin_unlock_irqrestore(&rtc_lock, flags);
138
139 return 0;
140}
141
142void __init plat_time_init(void)
143{
144 mips_hpt_frequency = cpu_clock_freq / 2;
145mips_hpt_frequency = 33000000 * 3 * 5;
146}
147
148unsigned long ocd_base;
149
150EXPORT_SYMBOL(ocd_base);
151
152/*
153 * Common setup before any secondaries are started
154 */
155
156#define TITAN_UART_CLK 3686400
157#define TITAN_SERIAL_BASE_BAUD (TITAN_UART_CLK / 16)
158#define TITAN_SERIAL_IRQ 4
159#define TITAN_SERIAL_BASE 0xfd000008UL
160
161static void __init py_map_ocd(void)
162{
163 ocd_base = (unsigned long) ioremap(OCD_BASE, OCD_SIZE);
164 if (!ocd_base)
165 panic("Mapping OCD failed - game over. Your score is 0.");
166
167 /* Kludge for PMON bug ... */
168 OCD_WRITE(0x0710, 0x0ffff029);
169}
170
171static void __init py_uart_setup(void)
172{
173#ifdef CONFIG_SERIAL_8250
174 struct uart_port up;
175
176 /*
177 * Register to interrupt zero because we share the interrupt with
178 * the serial driver which we don't properly support yet.
179 */
180 memset(&up, 0, sizeof(up));
181 up.membase = (unsigned char *) ioremap(TITAN_SERIAL_BASE, 8);
182 up.irq = TITAN_SERIAL_IRQ;
183 up.uartclk = TITAN_UART_CLK;
184 up.regshift = 0;
185 up.iotype = UPIO_MEM;
186 up.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
187 up.line = 0;
188
189 if (early_serial_setup(&up))
190 printk(KERN_ERR "Early serial init of port 0 failed\n");
191#endif /* CONFIG_SERIAL_8250 */
192}
193
194static void __init py_rtc_setup(void)
195{
196 m48t37_base = ioremap(YOSEMITE_RTC_BASE, YOSEMITE_RTC_SIZE);
197 if (!m48t37_base)
198 printk(KERN_ERR "Mapping the RTC failed\n");
199}
200
201/* Not only time init but that's what the hook it's called through is named */
202static void __init py_late_time_init(void)
203{
204 py_map_ocd();
205 py_uart_setup();
206 py_rtc_setup();
207}
208
209void __init plat_mem_setup(void)
210{
211 late_time_init = py_late_time_init;
212
213 /* Add memory regions */
214 add_memory_region(0x00000000, 0x10000000, BOOT_MEM_RAM);
215
216#if 0 /* XXX Crash ... */
217 OCD_WRITE(RM9000x2_OCD_HTSC,
218 OCD_READ(RM9000x2_OCD_HTSC) | HYPERTRANSPORT_ENABLE);
219
220 /* Set the BAR. Shifted mode */
221 OCD_WRITE(RM9000x2_OCD_HTBAR0, HYPERTRANSPORT_BAR0_ADDR);
222 OCD_WRITE(RM9000x2_OCD_HTMASK0, HYPERTRANSPORT_SIZE0);
223#endif
224}
diff --git a/arch/mips/pmc-sierra/yosemite/setup.h b/arch/mips/pmc-sierra/yosemite/setup.h
deleted file mode 100644
index 1a01abfc7d3..00000000000
--- a/arch/mips/pmc-sierra/yosemite/setup.h
+++ /dev/null
@@ -1,32 +0,0 @@
1/*
2 * Copyright 2003, 04 PMC-Sierra
3 * Author: Manish Lachwani (lachwani@pmc-sierra.com)
4 * Copyright 2004 Ralf Baechle <ralf@linux-mips.org>
5 *
6 * Board specific definititions for the PMC-Sierra Yosemite
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13#ifndef __SETUP_H__
14#define __SETUP_H__
15
16/* M48T37 RTC + NVRAM */
17#define YOSEMITE_RTC_BASE 0xfc800000
18#define YOSEMITE_RTC_SIZE 0x00800000
19
20#define HYPERTRANSPORT_BAR0_ADDR 0x00000006
21#define HYPERTRANSPORT_SIZE0 0x0fffffff
22#define HYPERTRANSPORT_BAR0_ATTR 0x00002000
23
24#define HYPERTRANSPORT_ENABLE 0x6
25
26/*
27 * EEPROM Size
28 */
29#define TITAN_ATMEL_24C32_SIZE 32768
30#define TITAN_ATMEL_24C64_SIZE 65536
31
32#endif /* __SETUP_H__ */
diff --git a/arch/mips/pmc-sierra/yosemite/smp.c b/arch/mips/pmc-sierra/yosemite/smp.c
deleted file mode 100644
index 5edab2bc6fc..00000000000
--- a/arch/mips/pmc-sierra/yosemite/smp.c
+++ /dev/null
@@ -1,185 +0,0 @@
1#include <linux/linkage.h>
2#include <linux/sched.h>
3#include <linux/smp.h>
4
5#include <asm/pmon.h>
6#include <asm/titan_dep.h>
7#include <asm/time.h>
8
9#define LAUNCHSTACK_SIZE 256
10
11static __cpuinitdata arch_spinlock_t launch_lock = __ARCH_SPIN_LOCK_UNLOCKED;
12
13static unsigned long secondary_sp __cpuinitdata;
14static unsigned long secondary_gp __cpuinitdata;
15
16static unsigned char launchstack[LAUNCHSTACK_SIZE] __initdata
17 __attribute__((aligned(2 * sizeof(long))));
18
19static void __init prom_smp_bootstrap(void)
20{
21 local_irq_disable();
22
23 while (arch_spin_is_locked(&launch_lock));
24
25 __asm__ __volatile__(
26 " move $sp, %0 \n"
27 " move $gp, %1 \n"
28 " j smp_bootstrap \n"
29 :
30 : "r" (secondary_sp), "r" (secondary_gp));
31}
32
33/*
34 * PMON is a fragile beast. It'll blow up once the mappings it's littering
35 * right into the middle of KSEG3 are blown away so we have to grab the slave
36 * core early and keep it in a waiting loop.
37 */
38void __init prom_grab_secondary(void)
39{
40 arch_spin_lock(&launch_lock);
41
42 pmon_cpustart(1, &prom_smp_bootstrap,
43 launchstack + LAUNCHSTACK_SIZE, 0);
44}
45
46void titan_mailbox_irq(void)
47{
48 int cpu = smp_processor_id();
49 unsigned long status;
50
51 switch (cpu) {
52 case 0:
53 status = OCD_READ(RM9000x2_OCD_INTP0STATUS3);
54 OCD_WRITE(RM9000x2_OCD_INTP0CLEAR3, status);
55
56 if (status & 0x2)
57 smp_call_function_interrupt();
58 if (status & 0x4)
59 scheduler_ipi();
60 break;
61
62 case 1:
63 status = OCD_READ(RM9000x2_OCD_INTP1STATUS3);
64 OCD_WRITE(RM9000x2_OCD_INTP1CLEAR3, status);
65
66 if (status & 0x2)
67 smp_call_function_interrupt();
68 if (status & 0x4)
69 scheduler_ipi();
70 break;
71 }
72}
73
74/*
75 * Send inter-processor interrupt
76 */
77static void yos_send_ipi_single(int cpu, unsigned int action)
78{
79 /*
80 * Generate an INTMSG so that it can be sent over to the
81 * destination CPU. The INTMSG will put the STATUS bits
82 * based on the action desired. An alternative strategy
83 * is to write to the Interrupt Set register, read the
84 * Interrupt Status register and clear the Interrupt
85 * Clear register. The latter is preffered.
86 */
87 switch (action) {
88 case SMP_RESCHEDULE_YOURSELF:
89 if (cpu == 1)
90 OCD_WRITE(RM9000x2_OCD_INTP1SET3, 4);
91 else
92 OCD_WRITE(RM9000x2_OCD_INTP0SET3, 4);
93 break;
94
95 case SMP_CALL_FUNCTION:
96 if (cpu == 1)
97 OCD_WRITE(RM9000x2_OCD_INTP1SET3, 2);
98 else
99 OCD_WRITE(RM9000x2_OCD_INTP0SET3, 2);
100 break;
101 }
102}
103
104static void yos_send_ipi_mask(const struct cpumask *mask, unsigned int action)
105{
106 unsigned int i;
107
108 for_each_cpu(i, mask)
109 yos_send_ipi_single(i, action);
110}
111
112/*
113 * After we've done initial boot, this function is called to allow the
114 * board code to clean up state, if needed
115 */
116static void __cpuinit yos_init_secondary(void)
117{
118}
119
120static void __cpuinit yos_smp_finish(void)
121{
122 set_c0_status(ST0_CO | ST0_IM | ST0_IE);
123}
124
125/* Hook for after all CPUs are online */
126static void yos_cpus_done(void)
127{
128}
129
130/*
131 * Firmware CPU startup hook
132 * Complicated by PMON's weird interface which tries to minimic the UNIX fork.
133 * It launches the next * available CPU and copies some information on the
134 * stack so the first thing we do is throw away that stuff and load useful
135 * values into the registers ...
136 */
137static void __cpuinit yos_boot_secondary(int cpu, struct task_struct *idle)
138{
139 unsigned long gp = (unsigned long) task_thread_info(idle);
140 unsigned long sp = __KSTK_TOS(idle);
141
142 secondary_sp = sp;
143 secondary_gp = gp;
144
145 arch_spin_unlock(&launch_lock);
146}
147
148/*
149 * Detect available CPUs, populate cpu_possible_mask before smp_init
150 *
151 * We don't want to start the secondary CPU yet nor do we have a nice probing
152 * feature in PMON so we just assume presence of the secondary core.
153 */
154static void __init yos_smp_setup(void)
155{
156 int i;
157
158 init_cpu_possible(cpu_none_mask);
159
160 for (i = 0; i < 2; i++) {
161 set_cpu_possible(i, true);
162 __cpu_number_map[i] = i;
163 __cpu_logical_map[i] = i;
164 }
165}
166
167static void __init yos_prepare_cpus(unsigned int max_cpus)
168{
169 /*
170 * Be paranoid. Enable the IPI only if we're really about to go SMP.
171 */
172 if (num_possible_cpus())
173 set_c0_status(STATUSF_IP5);
174}
175
176struct plat_smp_ops yos_smp_ops = {
177 .send_ipi_single = yos_send_ipi_single,
178 .send_ipi_mask = yos_send_ipi_mask,
179 .init_secondary = yos_init_secondary,
180 .smp_finish = yos_smp_finish,
181 .cpus_done = yos_cpus_done,
182 .boot_secondary = yos_boot_secondary,
183 .smp_setup = yos_smp_setup,
184 .prepare_cpus = yos_prepare_cpus,
185};
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-31 23:35:31 -0500