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authorAaro Koskinen <aaro.koskinen@iki.fi>2011-03-13 06:26:06 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2011-03-14 14:52:24 -0400
commitb9ebf5e5913307e67d226e61d953c3c4fd48de99 (patch)
treef36acafb515005c2f2e810e00cac7bae5717a2c4
parent3f8214c33f3b9997f3351feef77eb32d213ef94d (diff)
staging: xgifb: vb_init: move functions to avoid forward declarations
Move functions to avoid forward declarations. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat
-rw-r--r--drivers/staging/xgifb/vb_init.c875
1 files changed, 428 insertions, 447 deletions
diff --git a/drivers/staging/xgifb/vb_init.c b/drivers/staging/xgifb/vb_init.c
index 4bbcff6aedf..7b8e00defd5 100644
--- a/drivers/staging/xgifb/vb_init.c
+++ b/drivers/staging/xgifb/vb_init.c
@@ -37,389 +37,13 @@ static unsigned short XGINew_DDRDRAM_TYPE20[12][5] = {
37 { 2, 12, 9, 8, 0x35}, 37 { 2, 12, 9, 8, 0x35},
38 { 2, 12, 8, 4, 0x31} }; 38 { 2, 12, 8, 4, 0x31} };
39 39
40static void XGINew_SetDRAMSize_340(struct xgi_hw_device_info *, struct vb_device_info *); 40static int XGINew_RAMType;
41static void XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *);
42static void XGINew_SetDRAMDefaultRegister340(struct xgi_hw_device_info *HwDeviceExtension,
43 unsigned long, struct vb_device_info *);
44static unsigned char XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
45 struct vb_device_info *pVBInfo);
46
47static int XGINew_DDRSizing340(struct xgi_hw_device_info *, struct vb_device_info *);
48static int XGINew_RAMType; /*int ModeIDOffset,StandTable,CRT1Table,ScreenOffset,REFIndex;*/
49static void ReadVBIOSTablData(unsigned char ChipType, struct vb_device_info *pVBInfo);
50static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4, struct vb_device_info *pVBInfo);
51static void XGINew_ChkSenseStatus(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo) ;
52static void XGINew_GetXG21Sense(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo) ;
53static unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo);
54static void XGINew_GetXG27Sense(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo) ;
55static unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo);
56static void XGINew_SetModeScratch(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo) ;
57 41
58static void DelayUS(unsigned long MicroSeconds) 42static void DelayUS(unsigned long MicroSeconds)
59{ 43{
60 udelay(MicroSeconds); 44 udelay(MicroSeconds);
61} 45}
62 46
63unsigned char XGIInitNew(struct xgi_hw_device_info *HwDeviceExtension)
64{
65 struct vb_device_info VBINF;
66 struct vb_device_info *pVBInfo = &VBINF;
67 unsigned char i, temp = 0, temp1;
68 /* VBIOSVersion[5]; */
69 volatile unsigned char *pVideoMemory;
70
71 /* unsigned long j, k; */
72
73 unsigned long Temp;
74
75 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase;
76
77 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
78
79 pVBInfo->BaseAddr = (unsigned long) HwDeviceExtension->pjIOAddress;
80
81 pVideoMemory = (unsigned char *) pVBInfo->ROMAddr;
82
83 /* Newdebugcode(0x99); */
84
85
86 /* if (pVBInfo->ROMAddr == 0) */
87 /* return(0); */
88
89 if (pVBInfo->FBAddr == NULL) {
90 printk("\n pVBInfo->FBAddr == 0 ");
91 return 0;
92 }
93 printk("1");
94 if (pVBInfo->BaseAddr == 0) {
95 printk("\npVBInfo->BaseAddr == 0 ");
96 return 0;
97 }
98 printk("2");
99
100 XGINew_SetReg3((pVBInfo->BaseAddr + 0x12), 0x67); /* 3c2 <- 67 ,ynlai */
101
102 pVBInfo->ISXPDOS = 0;
103 printk("3");
104
105 printk("4");
106
107 /* VBIOSVersion[4] = 0x0; */
108
109 /* 09/07/99 modify by domao */
110
111 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14;
112 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24;
113 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10;
114 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e;
115 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12;
116 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a;
117 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16;
118 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17;
119 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18;
120 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19;
121 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A;
122 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00;
123 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04;
124 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10;
125 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12;
126 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14;
127 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2;
128 printk("5");
129
130 if (HwDeviceExtension->jChipType < XG20) /* kuku 2004/06/25 */
131 XGI_GetVBType(pVBInfo); /* Run XGI_GetVBType before InitTo330Pointer */
132
133 InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
134
135 /* ReadVBIOSData */
136 ReadVBIOSTablData(HwDeviceExtension->jChipType, pVBInfo);
137
138 /* 1.Openkey */
139 XGINew_SetReg1(pVBInfo->P3c4, 0x05, 0x86);
140 printk("6");
141
142 /* GetXG21Sense (GPIO) */
143 if (HwDeviceExtension->jChipType == XG21)
144 XGINew_GetXG21Sense(HwDeviceExtension, pVBInfo);
145
146 if (HwDeviceExtension->jChipType == XG27)
147 XGINew_GetXG27Sense(HwDeviceExtension, pVBInfo);
148
149 printk("7");
150
151 /* 2.Reset Extended register */
152
153 for (i = 0x06; i < 0x20; i++)
154 XGINew_SetReg1(pVBInfo->P3c4, i, 0);
155
156 for (i = 0x21; i <= 0x27; i++)
157 XGINew_SetReg1(pVBInfo->P3c4, i, 0);
158
159 /* for(i = 0x06; i <= 0x27; i++) */
160 /* XGINew_SetReg1(pVBInfo->P3c4, i, 0); */
161
162 printk("8");
163
164 if ((HwDeviceExtension->jChipType >= XG20) || (HwDeviceExtension->jChipType >= XG40)) {
165 for (i = 0x31; i <= 0x3B; i++)
166 XGINew_SetReg1(pVBInfo->P3c4, i, 0);
167 } else {
168 for (i = 0x31; i <= 0x3D; i++)
169 XGINew_SetReg1(pVBInfo->P3c4, i, 0);
170 }
171 printk("9");
172
173 if (HwDeviceExtension->jChipType == XG42) /* [Hsuan] 2004/08/20 Auto over driver for XG42 */
174 XGINew_SetReg1(pVBInfo->P3c4, 0x3B, 0xC0);
175
176 /* for (i = 0x30; i <= 0x3F; i++) */
177 /* XGINew_SetReg1(pVBInfo->P3d4, i, 0); */
178
179 for (i = 0x79; i <= 0x7C; i++)
180 XGINew_SetReg1(pVBInfo->P3d4, i, 0); /* shampoo 0208 */
181
182 printk("10");
183
184 if (HwDeviceExtension->jChipType >= XG20)
185 XGINew_SetReg1(pVBInfo->P3d4, 0x97, *pVBInfo->pXGINew_CR97);
186
187 /* 3.SetMemoryClock
188
189 if (HwDeviceExtension->jChipType >= XG40)
190 XGINew_RAMType = (int)XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
191
192 if (HwDeviceExtension->jChipType < XG40)
193 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo); */
194
195 printk("11");
196
197 /* 4.SetDefExt1Regs begin */
198 XGINew_SetReg1(pVBInfo->P3c4, 0x07, *pVBInfo->pSR07);
199 if (HwDeviceExtension->jChipType == XG27) {
200 XGINew_SetReg1(pVBInfo->P3c4, 0x40, *pVBInfo->pSR40);
201 XGINew_SetReg1(pVBInfo->P3c4, 0x41, *pVBInfo->pSR41);
202 }
203 XGINew_SetReg1(pVBInfo->P3c4, 0x11, 0x0F);
204 XGINew_SetReg1(pVBInfo->P3c4, 0x1F, *pVBInfo->pSR1F);
205 /* XGINew_SetReg1(pVBInfo->P3c4, 0x20, 0x20); */
206 XGINew_SetReg1(pVBInfo->P3c4, 0x20, 0xA0); /* alan, 2001/6/26 Frame buffer can read/write SR20 */
207 XGINew_SetReg1(pVBInfo->P3c4, 0x36, 0x70); /* Hsuan, 2006/01/01 H/W request for slow corner chip */
208 if (HwDeviceExtension->jChipType == XG27) /* Alan 12/07/2006 */
209 XGINew_SetReg1(pVBInfo->P3c4, 0x36, *pVBInfo->pSR36);
210
211 /* SR11 = 0x0F; */
212 /* XGINew_SetReg1(pVBInfo->P3c4, 0x11, SR11); */
213
214 printk("12");
215
216 if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
217 /* Set AGP Rate */
218 /*
219 temp1 = XGINew_GetReg1(pVBInfo->P3c4, 0x3B);
220 temp1 &= 0x02;
221 if (temp1 == 0x02) {
222 XGINew_SetReg4(0xcf8, 0x80000000);
223 ChipsetID = XGINew_GetReg3(0x0cfc);
224 XGINew_SetReg4(0xcf8, 0x8000002C);
225 VendorID = XGINew_GetReg3(0x0cfc);
226 VendorID &= 0x0000FFFF;
227 XGINew_SetReg4(0xcf8, 0x8001002C);
228 GraphicVendorID = XGINew_GetReg3(0x0cfc);
229 GraphicVendorID &= 0x0000FFFF;
230
231 if (ChipsetID == 0x7301039)
232 XGINew_SetReg1(pVBInfo->P3d4, 0x5F, 0x09);
233
234 ChipsetID &= 0x0000FFFF;
235
236 if ((ChipsetID == 0x700E) || (ChipsetID == 0x1022) || (ChipsetID == 0x1106) || (ChipsetID == 0x10DE)) {
237 if (ChipsetID == 0x1106) {
238 if ((VendorID == 0x1019) && (GraphicVendorID == 0x1019))
239 XGINew_SetReg1(pVBInfo->P3d4, 0x5F, 0x0D);
240 else
241 XGINew_SetReg1(pVBInfo->P3d4, 0x5F, 0x0B);
242 } else {
243 XGINew_SetReg1(pVBInfo->P3d4, 0x5F, 0x0B);
244 }
245 }
246 }
247 */
248
249 printk("13");
250
251 if (HwDeviceExtension->jChipType >= XG40) {
252 /* Set AGP customize registers (in SetDefAGPRegs) Start */
253 for (i = 0x47; i <= 0x4C; i++)
254 XGINew_SetReg1(pVBInfo->P3d4, i, pVBInfo->AGPReg[i - 0x47]);
255
256 for (i = 0x70; i <= 0x71; i++)
257 XGINew_SetReg1(pVBInfo->P3d4, i, pVBInfo->AGPReg[6 + i - 0x70]);
258
259 for (i = 0x74; i <= 0x77; i++)
260 XGINew_SetReg1(pVBInfo->P3d4, i, pVBInfo->AGPReg[8 + i - 0x74]);
261 /* Set AGP customize registers (in SetDefAGPRegs) End */
262 /* [Hsuan]2004/12/14 AGP Input Delay Adjustment on 850 */
263 /* XGINew_SetReg4(0xcf8 , 0x80000000); */
264 /* ChipsetID = XGINew_GetReg3(0x0cfc); */
265 /* if (ChipsetID == 0x25308086) */
266 /* XGINew_SetReg1(pVBInfo->P3d4, 0x77, 0xF0); */
267
268 HwDeviceExtension->pQueryVGAConfigSpace(HwDeviceExtension, 0x50, 0, &Temp); /* Get */
269 Temp >>= 20;
270 Temp &= 0xF;
271
272 if (Temp == 1)
273 XGINew_SetReg1(pVBInfo->P3d4, 0x48, 0x20); /* CR48 */
274 }
275 printk("14");
276
277 if (HwDeviceExtension->jChipType < XG40)
278 XGINew_SetReg1(pVBInfo->P3d4, 0x49, pVBInfo->CR49[0]);
279 } /* != XG20 */
280
281 /* Set PCI */
282 XGINew_SetReg1(pVBInfo->P3c4, 0x23, *pVBInfo->pSR23);
283 XGINew_SetReg1(pVBInfo->P3c4, 0x24, *pVBInfo->pSR24);
284 XGINew_SetReg1(pVBInfo->P3c4, 0x25, pVBInfo->SR25[0]);
285 printk("15");
286
287 if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
288 /* Set VB */
289 XGI_UnLockCRT2(HwDeviceExtension, pVBInfo);
290 XGINew_SetRegANDOR(pVBInfo->Part0Port, 0x3F, 0xEF, 0x00); /* alan, disable VideoCapture */
291 XGINew_SetReg1(pVBInfo->Part1Port, 0x00, 0x00);
292 temp1 = (unsigned char) XGINew_GetReg1(pVBInfo->P3d4, 0x7B); /* chk if BCLK>=100MHz */
293 temp = (unsigned char) ((temp1 >> 4) & 0x0F);
294
295 XGINew_SetReg1(pVBInfo->Part1Port, 0x02, (*pVBInfo->pCRT2Data_1_2));
296
297 printk("16");
298
299 XGINew_SetReg1(pVBInfo->Part1Port, 0x2E, 0x08); /* use VB */
300 } /* != XG20 */
301
302 XGINew_SetReg1(pVBInfo->P3c4, 0x27, 0x1F);
303
304 if ((HwDeviceExtension->jChipType == XG42)
305 && XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) != 0) { /* Not DDR */
306 XGINew_SetReg1(pVBInfo->P3c4, 0x31, (*pVBInfo->pSR31 & 0x3F) | 0x40);
307 XGINew_SetReg1(pVBInfo->P3c4, 0x32, (*pVBInfo->pSR32 & 0xFC) | 0x01);
308 } else {
309 XGINew_SetReg1(pVBInfo->P3c4, 0x31, *pVBInfo->pSR31);
310 XGINew_SetReg1(pVBInfo->P3c4, 0x32, *pVBInfo->pSR32);
311 }
312 XGINew_SetReg1(pVBInfo->P3c4, 0x33, *pVBInfo->pSR33);
313 printk("17");
314
315 /*
316 if (HwDeviceExtension->jChipType >= XG40)
317 SetPowerConsume (HwDeviceExtension, pVBInfo->P3c4); */
318
319 if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
320 if (XGI_BridgeIsOn(pVBInfo) == 1) {
321 if (pVBInfo->IF_DEF_LVDS == 0) {
322 XGINew_SetReg1(pVBInfo->Part2Port, 0x00, 0x1C);
323 XGINew_SetReg1(pVBInfo->Part4Port, 0x0D, *pVBInfo->pCRT2Data_4_D);
324 XGINew_SetReg1(pVBInfo->Part4Port, 0x0E, *pVBInfo->pCRT2Data_4_E);
325 XGINew_SetReg1(pVBInfo->Part4Port, 0x10, *pVBInfo->pCRT2Data_4_10);
326 XGINew_SetReg1(pVBInfo->Part4Port, 0x0F, 0x3F);
327 }
328
329 XGI_LockCRT2(HwDeviceExtension, pVBInfo);
330 }
331 } /* != XG20 */
332 printk("18");
333
334 if (HwDeviceExtension->jChipType < XG40)
335 XGINew_SetReg1(pVBInfo->P3d4, 0x83, 0x00);
336 printk("181");
337
338 printk("182");
339
340 XGI_SenseCRT1(pVBInfo);
341
342 printk("183");
343 /* XGINew_DetectMonitor(HwDeviceExtension); */
344 pVBInfo->IF_DEF_CH7007 = 0;
345 if ((HwDeviceExtension->jChipType == XG21) && (pVBInfo->IF_DEF_CH7007)) {
346 printk("184");
347 XGI_GetSenseStatus(HwDeviceExtension, pVBInfo); /* sense CRT2 */
348 printk("185");
349
350 }
351 if (HwDeviceExtension->jChipType == XG21) {
352 printk("186");
353
354 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x32, ~Monitor1Sense, Monitor1Sense); /* Z9 default has CRT */
355 temp = GetXG21FPBits(pVBInfo);
356 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x37, ~0x01, temp);
357 printk("187");
358
359 }
360 if (HwDeviceExtension->jChipType == XG27) {
361 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x32, ~Monitor1Sense, Monitor1Sense); /* Z9 default has CRT */
362 temp = GetXG27FPBits(pVBInfo);
363 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x37, ~0x03, temp);
364 }
365 printk("19");
366
367 if (HwDeviceExtension->jChipType >= XG40) {
368 if (HwDeviceExtension->jChipType >= XG40)
369 XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
370
371 XGINew_SetDRAMDefaultRegister340(HwDeviceExtension, pVBInfo->P3d4, pVBInfo);
372
373 printk("20");
374 XGINew_SetDRAMSize_340(HwDeviceExtension, pVBInfo);
375 printk("21");
376 } /* XG40 */
377
378 printk("22");
379
380 /* SetDefExt2Regs begin */
381 /*
382 AGP = 1;
383 temp = (unsigned char) XGINew_GetReg1(pVBInfo->P3c4, 0x3A);
384 temp &= 0x30;
385 if (temp == 0x30)
386 AGP = 0;
387
388 if (AGP == 0)
389 *pVBInfo->pSR21 &= 0xEF;
390
391 XGINew_SetReg1(pVBInfo->P3c4, 0x21, *pVBInfo->pSR21);
392 if (AGP == 1)
393 *pVBInfo->pSR22 &= 0x20;
394 XGINew_SetReg1(pVBInfo->P3c4, 0x22, *pVBInfo->pSR22);
395 */
396 /* base = 0x80000000; */
397 /* OutPortLong(0xcf8, base); */
398 /* Temp = (InPortLong(0xcfc) & 0xFFFF); */
399 /* if (Temp == 0x1039) { */
400 XGINew_SetReg1(pVBInfo->P3c4, 0x22, (unsigned char) ((*pVBInfo->pSR22) & 0xFE));
401 /* } else { */
402 /* XGINew_SetReg1(pVBInfo->P3c4, 0x22, *pVBInfo->pSR22); */
403 /* } */
404
405 XGINew_SetReg1(pVBInfo->P3c4, 0x21, *pVBInfo->pSR21);
406
407 printk("23");
408
409 XGINew_ChkSenseStatus(HwDeviceExtension, pVBInfo);
410 XGINew_SetModeScratch(HwDeviceExtension, pVBInfo);
411
412 printk("24");
413
414 XGINew_SetReg1(pVBInfo->P3d4, 0x8c, 0x87);
415 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x31);
416 printk("25");
417
418 return 1;
419} /* end of init */
420
421/* ============== alan ====================== */
422
423static unsigned char XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension, 47static unsigned char XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
424 struct vb_device_info *pVBInfo) 48 struct vb_device_info *pVBInfo)
425{ 49{
@@ -503,6 +127,31 @@ static void XGINew_DDR1x_MRS_340(unsigned long P3c4, struct vb_device_info *pVBI
503 XGINew_SetReg1(P3c4, 0x1B, 0x00); 127 XGINew_SetReg1(P3c4, 0x1B, 0x00);
504} 128}
505 129
130static void XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension,
131 struct vb_device_info *pVBInfo)
132{
133
134 XGINew_SetReg1(pVBInfo->P3c4, 0x28, pVBInfo->MCLKData[XGINew_RAMType].SR28);
135 XGINew_SetReg1(pVBInfo->P3c4, 0x29, pVBInfo->MCLKData[XGINew_RAMType].SR29);
136 XGINew_SetReg1(pVBInfo->P3c4, 0x2A, pVBInfo->MCLKData[XGINew_RAMType].SR2A);
137
138 XGINew_SetReg1(pVBInfo->P3c4, 0x2E, pVBInfo->ECLKData[XGINew_RAMType].SR2E);
139 XGINew_SetReg1(pVBInfo->P3c4, 0x2F, pVBInfo->ECLKData[XGINew_RAMType].SR2F);
140 XGINew_SetReg1(pVBInfo->P3c4, 0x30, pVBInfo->ECLKData[XGINew_RAMType].SR30);
141
142 /* [Vicent] 2004/07/07, When XG42 ECLK = MCLK = 207MHz, Set SR32 D[1:0] = 10b */
143 /* [Hsuan] 2004/08/20, Modify SR32 value, when MCLK=207MHZ, ELCK=250MHz, Set SR32 D[1:0] = 10b */
144 if (HwDeviceExtension->jChipType == XG42) {
145 if ((pVBInfo->MCLKData[XGINew_RAMType].SR28 == 0x1C)
146 && (pVBInfo->MCLKData[XGINew_RAMType].SR29 == 0x01)
147 && (((pVBInfo->ECLKData[XGINew_RAMType].SR2E == 0x1C)
148 && (pVBInfo->ECLKData[XGINew_RAMType].SR2F == 0x01))
149 || ((pVBInfo->ECLKData[XGINew_RAMType].SR2E == 0x22)
150 && (pVBInfo->ECLKData[XGINew_RAMType].SR2F == 0x01))))
151 XGINew_SetReg1(pVBInfo->P3c4, 0x32, ((unsigned char) XGINew_GetReg1(pVBInfo->P3c4, 0x32) & 0xFC) | 0x02);
152 }
153}
154
506static void XGINew_DDRII_Bootup_XG27( 155static void XGINew_DDRII_Bootup_XG27(
507 struct xgi_hw_device_info *HwDeviceExtension, 156 struct xgi_hw_device_info *HwDeviceExtension,
508 unsigned long P3c4, struct vb_device_info *pVBInfo) 157 unsigned long P3c4, struct vb_device_info *pVBInfo)
@@ -624,6 +273,36 @@ static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension,
624 DelayUS(200); 273 DelayUS(200);
625} 274}
626 275
276static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4, struct vb_device_info *pVBInfo)
277{
278
279 XGINew_SetReg1(P3c4, 0x18, 0x01);
280 XGINew_SetReg1(P3c4, 0x19, 0x40);
281 XGINew_SetReg1(P3c4, 0x16, 0x00);
282 XGINew_SetReg1(P3c4, 0x16, 0x80);
283 DelayUS(60);
284
285 XGINew_SetReg1(P3c4, 0x18, 0x00);
286 XGINew_SetReg1(P3c4, 0x19, 0x40);
287 XGINew_SetReg1(P3c4, 0x16, 0x00);
288 XGINew_SetReg1(P3c4, 0x16, 0x80);
289 DelayUS(60);
290 XGINew_SetReg1(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
291 /* XGINew_SetReg1(P3c4, 0x18, 0x31); */
292 XGINew_SetReg1(P3c4, 0x19, 0x01);
293 XGINew_SetReg1(P3c4, 0x16, 0x03);
294 XGINew_SetReg1(P3c4, 0x16, 0x83);
295 DelayUS(1000);
296 XGINew_SetReg1(P3c4, 0x1B, 0x03);
297 DelayUS(500);
298 /* XGINew_SetReg1(P3c4, 0x18, 0x31); */
299 XGINew_SetReg1(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
300 XGINew_SetReg1(P3c4, 0x19, 0x00);
301 XGINew_SetReg1(P3c4, 0x16, 0x03);
302 XGINew_SetReg1(P3c4, 0x16, 0x83);
303 XGINew_SetReg1(P3c4, 0x1B, 0x00);
304}
305
627static void XGINew_DDR1x_DefaultRegister( 306static void XGINew_DDR1x_DefaultRegister(
628 struct xgi_hw_device_info *HwDeviceExtension, 307 struct xgi_hw_device_info *HwDeviceExtension,
629 unsigned long Port, struct vb_device_info *pVBInfo) 308 unsigned long Port, struct vb_device_info *pVBInfo)
@@ -835,28 +514,6 @@ static void XGINew_SetDRAMDefaultRegister340(
835 XGINew_SetReg1(P3c4, 0x1B, pVBInfo->SR15[3][XGINew_RAMType]); /* SR1B */ 514 XGINew_SetReg1(P3c4, 0x1B, pVBInfo->SR15[3][XGINew_RAMType]); /* SR1B */
836} 515}
837 516
838static void XGINew_SetDRAMSize_340(struct xgi_hw_device_info *HwDeviceExtension,
839 struct vb_device_info *pVBInfo)
840{
841 unsigned short data;
842
843 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase;
844 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
845
846 XGISetModeNew(HwDeviceExtension, 0x2e);
847
848 data = XGINew_GetReg1(pVBInfo->P3c4, 0x21);
849 XGINew_SetReg1(pVBInfo->P3c4, 0x21, (unsigned short) (data & 0xDF)); /* disable read cache */
850 XGI_DisplayOff(HwDeviceExtension, pVBInfo);
851
852 /* data = XGINew_GetReg1(pVBInfo->P3c4, 0x1); */
853 /* data |= 0x20 ; */
854 /* XGINew_SetReg1(pVBInfo->P3c4, 0x01, data); *//* Turn OFF Display */
855 XGINew_DDRSizing340(HwDeviceExtension, pVBInfo);
856 data = XGINew_GetReg1(pVBInfo->P3c4, 0x21);
857 XGINew_SetReg1(pVBInfo->P3c4, 0x21, (unsigned short) (data | 0x20)); /* enable read cache */
858}
859
860static void XGINew_SetDRAMSizingType(int index, 517static void XGINew_SetDRAMSizingType(int index,
861 unsigned short DRAMTYPE_TABLE[][5], 518 unsigned short DRAMTYPE_TABLE[][5],
862 struct vb_device_info *pVBInfo) 519 struct vb_device_info *pVBInfo)
@@ -1290,29 +947,26 @@ static int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension,
1290 return 0; 947 return 0;
1291} 948}
1292 949
1293static void XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension, 950static void XGINew_SetDRAMSize_340(struct xgi_hw_device_info *HwDeviceExtension,
1294 struct vb_device_info *pVBInfo) 951 struct vb_device_info *pVBInfo)
1295{ 952{
953 unsigned short data;
1296 954
1297 XGINew_SetReg1(pVBInfo->P3c4, 0x28, pVBInfo->MCLKData[XGINew_RAMType].SR28); 955 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase;
1298 XGINew_SetReg1(pVBInfo->P3c4, 0x29, pVBInfo->MCLKData[XGINew_RAMType].SR29); 956 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
1299 XGINew_SetReg1(pVBInfo->P3c4, 0x2A, pVBInfo->MCLKData[XGINew_RAMType].SR2A);
1300 957
1301 XGINew_SetReg1(pVBInfo->P3c4, 0x2E, pVBInfo->ECLKData[XGINew_RAMType].SR2E); 958 XGISetModeNew(HwDeviceExtension, 0x2e);
1302 XGINew_SetReg1(pVBInfo->P3c4, 0x2F, pVBInfo->ECLKData[XGINew_RAMType].SR2F);
1303 XGINew_SetReg1(pVBInfo->P3c4, 0x30, pVBInfo->ECLKData[XGINew_RAMType].SR30);
1304 959
1305 /* [Vicent] 2004/07/07, When XG42 ECLK = MCLK = 207MHz, Set SR32 D[1:0] = 10b */ 960 data = XGINew_GetReg1(pVBInfo->P3c4, 0x21);
1306 /* [Hsuan] 2004/08/20, Modify SR32 value, when MCLK=207MHZ, ELCK=250MHz, Set SR32 D[1:0] = 10b */ 961 XGINew_SetReg1(pVBInfo->P3c4, 0x21, (unsigned short) (data & 0xDF)); /* disable read cache */
1307 if (HwDeviceExtension->jChipType == XG42) { 962 XGI_DisplayOff(HwDeviceExtension, pVBInfo);
1308 if ((pVBInfo->MCLKData[XGINew_RAMType].SR28 == 0x1C) 963
1309 && (pVBInfo->MCLKData[XGINew_RAMType].SR29 == 0x01) 964 /* data = XGINew_GetReg1(pVBInfo->P3c4, 0x1); */
1310 && (((pVBInfo->ECLKData[XGINew_RAMType].SR2E == 0x1C) 965 /* data |= 0x20 ; */
1311 && (pVBInfo->ECLKData[XGINew_RAMType].SR2F == 0x01)) 966 /* XGINew_SetReg1(pVBInfo->P3c4, 0x01, data); *//* Turn OFF Display */
1312 || ((pVBInfo->ECLKData[XGINew_RAMType].SR2E == 0x22) 967 XGINew_DDRSizing340(HwDeviceExtension, pVBInfo);
1313 && (pVBInfo->ECLKData[XGINew_RAMType].SR2F == 0x01)))) 968 data = XGINew_GetReg1(pVBInfo->P3c4, 0x21);
1314 XGINew_SetReg1(pVBInfo->P3c4, 0x32, ((unsigned char) XGINew_GetReg1(pVBInfo->P3c4, 0x32) & 0xFC) | 0x02); 969 XGINew_SetReg1(pVBInfo->P3c4, 0x21, (unsigned short) (data | 0x20)); /* enable read cache */
1315 }
1316} 970}
1317 971
1318static void ReadVBIOSTablData(unsigned char ChipType, struct vb_device_info *pVBInfo) 972static void ReadVBIOSTablData(unsigned char ChipType, struct vb_device_info *pVBInfo)
@@ -1405,36 +1059,6 @@ static void ReadVBIOSTablData(unsigned char ChipType, struct vb_device_info *pVB
1405 } 1059 }
1406} 1060}
1407 1061
1408static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4, struct vb_device_info *pVBInfo)
1409{
1410
1411 XGINew_SetReg1(P3c4, 0x18, 0x01);
1412 XGINew_SetReg1(P3c4, 0x19, 0x40);
1413 XGINew_SetReg1(P3c4, 0x16, 0x00);
1414 XGINew_SetReg1(P3c4, 0x16, 0x80);
1415 DelayUS(60);
1416
1417 XGINew_SetReg1(P3c4, 0x18, 0x00);
1418 XGINew_SetReg1(P3c4, 0x19, 0x40);
1419 XGINew_SetReg1(P3c4, 0x16, 0x00);
1420 XGINew_SetReg1(P3c4, 0x16, 0x80);
1421 DelayUS(60);
1422 XGINew_SetReg1(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
1423 /* XGINew_SetReg1(P3c4, 0x18, 0x31); */
1424 XGINew_SetReg1(P3c4, 0x19, 0x01);
1425 XGINew_SetReg1(P3c4, 0x16, 0x03);
1426 XGINew_SetReg1(P3c4, 0x16, 0x83);
1427 DelayUS(1000);
1428 XGINew_SetReg1(P3c4, 0x1B, 0x03);
1429 DelayUS(500);
1430 /* XGINew_SetReg1(P3c4, 0x18, 0x31); */
1431 XGINew_SetReg1(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
1432 XGINew_SetReg1(P3c4, 0x19, 0x00);
1433 XGINew_SetReg1(P3c4, 0x16, 0x03);
1434 XGINew_SetReg1(P3c4, 0x16, 0x83);
1435 XGINew_SetReg1(P3c4, 0x1B, 0x00);
1436}
1437
1438static void XGINew_ChkSenseStatus(struct xgi_hw_device_info *HwDeviceExtension, 1062static void XGINew_ChkSenseStatus(struct xgi_hw_device_info *HwDeviceExtension,
1439 struct vb_device_info *pVBInfo) 1063 struct vb_device_info *pVBInfo)
1440{ 1064{
@@ -1657,3 +1281,360 @@ static unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo)
1657 return temp; 1281 return temp;
1658} 1282}
1659 1283
1284unsigned char XGIInitNew(struct xgi_hw_device_info *HwDeviceExtension)
1285{
1286 struct vb_device_info VBINF;
1287 struct vb_device_info *pVBInfo = &VBINF;
1288 unsigned char i, temp = 0, temp1;
1289 /* VBIOSVersion[5]; */
1290 volatile unsigned char *pVideoMemory;
1291
1292 /* unsigned long j, k; */
1293
1294 unsigned long Temp;
1295
1296 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase;
1297
1298 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
1299
1300 pVBInfo->BaseAddr = (unsigned long) HwDeviceExtension->pjIOAddress;
1301
1302 pVideoMemory = (unsigned char *) pVBInfo->ROMAddr;
1303
1304 /* Newdebugcode(0x99); */
1305
1306
1307 /* if (pVBInfo->ROMAddr == 0) */
1308 /* return(0); */
1309
1310 if (pVBInfo->FBAddr == NULL) {
1311 printk("\n pVBInfo->FBAddr == 0 ");
1312 return 0;
1313 }
1314 printk("1");
1315 if (pVBInfo->BaseAddr == 0) {
1316 printk("\npVBInfo->BaseAddr == 0 ");
1317 return 0;
1318 }
1319 printk("2");
1320
1321 XGINew_SetReg3((pVBInfo->BaseAddr + 0x12), 0x67); /* 3c2 <- 67 ,ynlai */
1322
1323 pVBInfo->ISXPDOS = 0;
1324 printk("3");
1325
1326 printk("4");
1327
1328 /* VBIOSVersion[4] = 0x0; */
1329
1330 /* 09/07/99 modify by domao */
1331
1332 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14;
1333 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24;
1334 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10;
1335 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e;
1336 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12;
1337 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a;
1338 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16;
1339 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17;
1340 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18;
1341 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19;
1342 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A;
1343 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00;
1344 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04;
1345 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10;
1346 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12;
1347 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14;
1348 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2;
1349 printk("5");
1350
1351 if (HwDeviceExtension->jChipType < XG20) /* kuku 2004/06/25 */
1352 XGI_GetVBType(pVBInfo); /* Run XGI_GetVBType before InitTo330Pointer */
1353
1354 InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
1355
1356 /* ReadVBIOSData */
1357 ReadVBIOSTablData(HwDeviceExtension->jChipType, pVBInfo);
1358
1359 /* 1.Openkey */
1360 XGINew_SetReg1(pVBInfo->P3c4, 0x05, 0x86);
1361 printk("6");
1362
1363 /* GetXG21Sense (GPIO) */
1364 if (HwDeviceExtension->jChipType == XG21)
1365 XGINew_GetXG21Sense(HwDeviceExtension, pVBInfo);
1366
1367 if (HwDeviceExtension->jChipType == XG27)
1368 XGINew_GetXG27Sense(HwDeviceExtension, pVBInfo);
1369
1370 printk("7");
1371
1372 /* 2.Reset Extended register */
1373
1374 for (i = 0x06; i < 0x20; i++)
1375 XGINew_SetReg1(pVBInfo->P3c4, i, 0);
1376
1377 for (i = 0x21; i <= 0x27; i++)
1378 XGINew_SetReg1(pVBInfo->P3c4, i, 0);
1379
1380 /* for(i = 0x06; i <= 0x27; i++) */
1381 /* XGINew_SetReg1(pVBInfo->P3c4, i, 0); */
1382
1383 printk("8");
1384
1385 if ((HwDeviceExtension->jChipType >= XG20) || (HwDeviceExtension->jChipType >= XG40)) {
1386 for (i = 0x31; i <= 0x3B; i++)
1387 XGINew_SetReg1(pVBInfo->P3c4, i, 0);
1388 } else {
1389 for (i = 0x31; i <= 0x3D; i++)
1390 XGINew_SetReg1(pVBInfo->P3c4, i, 0);
1391 }
1392 printk("9");
1393
1394 if (HwDeviceExtension->jChipType == XG42) /* [Hsuan] 2004/08/20 Auto over driver for XG42 */
1395 XGINew_SetReg1(pVBInfo->P3c4, 0x3B, 0xC0);
1396
1397 /* for (i = 0x30; i <= 0x3F; i++) */
1398 /* XGINew_SetReg1(pVBInfo->P3d4, i, 0); */
1399
1400 for (i = 0x79; i <= 0x7C; i++)
1401 XGINew_SetReg1(pVBInfo->P3d4, i, 0); /* shampoo 0208 */
1402
1403 printk("10");
1404
1405 if (HwDeviceExtension->jChipType >= XG20)
1406 XGINew_SetReg1(pVBInfo->P3d4, 0x97, *pVBInfo->pXGINew_CR97);
1407
1408 /* 3.SetMemoryClock
1409
1410 if (HwDeviceExtension->jChipType >= XG40)
1411 XGINew_RAMType = (int)XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
1412
1413 if (HwDeviceExtension->jChipType < XG40)
1414 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo); */
1415
1416 printk("11");
1417
1418 /* 4.SetDefExt1Regs begin */
1419 XGINew_SetReg1(pVBInfo->P3c4, 0x07, *pVBInfo->pSR07);
1420 if (HwDeviceExtension->jChipType == XG27) {
1421 XGINew_SetReg1(pVBInfo->P3c4, 0x40, *pVBInfo->pSR40);
1422 XGINew_SetReg1(pVBInfo->P3c4, 0x41, *pVBInfo->pSR41);
1423 }
1424 XGINew_SetReg1(pVBInfo->P3c4, 0x11, 0x0F);
1425 XGINew_SetReg1(pVBInfo->P3c4, 0x1F, *pVBInfo->pSR1F);
1426 /* XGINew_SetReg1(pVBInfo->P3c4, 0x20, 0x20); */
1427 XGINew_SetReg1(pVBInfo->P3c4, 0x20, 0xA0); /* alan, 2001/6/26 Frame buffer can read/write SR20 */
1428 XGINew_SetReg1(pVBInfo->P3c4, 0x36, 0x70); /* Hsuan, 2006/01/01 H/W request for slow corner chip */
1429 if (HwDeviceExtension->jChipType == XG27) /* Alan 12/07/2006 */
1430 XGINew_SetReg1(pVBInfo->P3c4, 0x36, *pVBInfo->pSR36);
1431
1432 /* SR11 = 0x0F; */
1433 /* XGINew_SetReg1(pVBInfo->P3c4, 0x11, SR11); */
1434
1435 printk("12");
1436
1437 if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
1438 /* Set AGP Rate */
1439 /*
1440 temp1 = XGINew_GetReg1(pVBInfo->P3c4, 0x3B);
1441 temp1 &= 0x02;
1442 if (temp1 == 0x02) {
1443 XGINew_SetReg4(0xcf8, 0x80000000);
1444 ChipsetID = XGINew_GetReg3(0x0cfc);
1445 XGINew_SetReg4(0xcf8, 0x8000002C);
1446 VendorID = XGINew_GetReg3(0x0cfc);
1447 VendorID &= 0x0000FFFF;
1448 XGINew_SetReg4(0xcf8, 0x8001002C);
1449 GraphicVendorID = XGINew_GetReg3(0x0cfc);
1450 GraphicVendorID &= 0x0000FFFF;
1451
1452 if (ChipsetID == 0x7301039)
1453 XGINew_SetReg1(pVBInfo->P3d4, 0x5F, 0x09);
1454
1455 ChipsetID &= 0x0000FFFF;
1456
1457 if ((ChipsetID == 0x700E) || (ChipsetID == 0x1022) || (ChipsetID == 0x1106) || (ChipsetID == 0x10DE)) {
1458 if (ChipsetID == 0x1106) {
1459 if ((VendorID == 0x1019) && (GraphicVendorID == 0x1019))
1460 XGINew_SetReg1(pVBInfo->P3d4, 0x5F, 0x0D);
1461 else
1462 XGINew_SetReg1(pVBInfo->P3d4, 0x5F, 0x0B);
1463 } else {
1464 XGINew_SetReg1(pVBInfo->P3d4, 0x5F, 0x0B);
1465 }
1466 }
1467 }
1468 */
1469
1470 printk("13");
1471
1472 if (HwDeviceExtension->jChipType >= XG40) {
1473 /* Set AGP customize registers (in SetDefAGPRegs) Start */
1474 for (i = 0x47; i <= 0x4C; i++)
1475 XGINew_SetReg1(pVBInfo->P3d4, i, pVBInfo->AGPReg[i - 0x47]);
1476
1477 for (i = 0x70; i <= 0x71; i++)
1478 XGINew_SetReg1(pVBInfo->P3d4, i, pVBInfo->AGPReg[6 + i - 0x70]);
1479
1480 for (i = 0x74; i <= 0x77; i++)
1481 XGINew_SetReg1(pVBInfo->P3d4, i, pVBInfo->AGPReg[8 + i - 0x74]);
1482 /* Set AGP customize registers (in SetDefAGPRegs) End */
1483 /* [Hsuan]2004/12/14 AGP Input Delay Adjustment on 850 */
1484 /* XGINew_SetReg4(0xcf8 , 0x80000000); */
1485 /* ChipsetID = XGINew_GetReg3(0x0cfc); */
1486 /* if (ChipsetID == 0x25308086) */
1487 /* XGINew_SetReg1(pVBInfo->P3d4, 0x77, 0xF0); */
1488
1489 HwDeviceExtension->pQueryVGAConfigSpace(HwDeviceExtension, 0x50, 0, &Temp); /* Get */
1490 Temp >>= 20;
1491 Temp &= 0xF;
1492
1493 if (Temp == 1)
1494 XGINew_SetReg1(pVBInfo->P3d4, 0x48, 0x20); /* CR48 */
1495 }
1496 printk("14");
1497
1498 if (HwDeviceExtension->jChipType < XG40)
1499 XGINew_SetReg1(pVBInfo->P3d4, 0x49, pVBInfo->CR49[0]);
1500 } /* != XG20 */
1501
1502 /* Set PCI */
1503 XGINew_SetReg1(pVBInfo->P3c4, 0x23, *pVBInfo->pSR23);
1504 XGINew_SetReg1(pVBInfo->P3c4, 0x24, *pVBInfo->pSR24);
1505 XGINew_SetReg1(pVBInfo->P3c4, 0x25, pVBInfo->SR25[0]);
1506 printk("15");
1507
1508 if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
1509 /* Set VB */
1510 XGI_UnLockCRT2(HwDeviceExtension, pVBInfo);
1511 XGINew_SetRegANDOR(pVBInfo->Part0Port, 0x3F, 0xEF, 0x00); /* alan, disable VideoCapture */
1512 XGINew_SetReg1(pVBInfo->Part1Port, 0x00, 0x00);
1513 temp1 = (unsigned char) XGINew_GetReg1(pVBInfo->P3d4, 0x7B); /* chk if BCLK>=100MHz */
1514 temp = (unsigned char) ((temp1 >> 4) & 0x0F);
1515
1516 XGINew_SetReg1(pVBInfo->Part1Port, 0x02, (*pVBInfo->pCRT2Data_1_2));
1517
1518 printk("16");
1519
1520 XGINew_SetReg1(pVBInfo->Part1Port, 0x2E, 0x08); /* use VB */
1521 } /* != XG20 */
1522
1523 XGINew_SetReg1(pVBInfo->P3c4, 0x27, 0x1F);
1524
1525 if ((HwDeviceExtension->jChipType == XG42)
1526 && XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) != 0) { /* Not DDR */
1527 XGINew_SetReg1(pVBInfo->P3c4, 0x31, (*pVBInfo->pSR31 & 0x3F) | 0x40);
1528 XGINew_SetReg1(pVBInfo->P3c4, 0x32, (*pVBInfo->pSR32 & 0xFC) | 0x01);
1529 } else {
1530 XGINew_SetReg1(pVBInfo->P3c4, 0x31, *pVBInfo->pSR31);
1531 XGINew_SetReg1(pVBInfo->P3c4, 0x32, *pVBInfo->pSR32);
1532 }
1533 XGINew_SetReg1(pVBInfo->P3c4, 0x33, *pVBInfo->pSR33);
1534 printk("17");
1535
1536 /*
1537 if (HwDeviceExtension->jChipType >= XG40)
1538 SetPowerConsume (HwDeviceExtension, pVBInfo->P3c4); */
1539
1540 if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
1541 if (XGI_BridgeIsOn(pVBInfo) == 1) {
1542 if (pVBInfo->IF_DEF_LVDS == 0) {
1543 XGINew_SetReg1(pVBInfo->Part2Port, 0x00, 0x1C);
1544 XGINew_SetReg1(pVBInfo->Part4Port, 0x0D, *pVBInfo->pCRT2Data_4_D);
1545 XGINew_SetReg1(pVBInfo->Part4Port, 0x0E, *pVBInfo->pCRT2Data_4_E);
1546 XGINew_SetReg1(pVBInfo->Part4Port, 0x10, *pVBInfo->pCRT2Data_4_10);
1547 XGINew_SetReg1(pVBInfo->Part4Port, 0x0F, 0x3F);
1548 }
1549
1550 XGI_LockCRT2(HwDeviceExtension, pVBInfo);
1551 }
1552 } /* != XG20 */
1553 printk("18");
1554
1555 if (HwDeviceExtension->jChipType < XG40)
1556 XGINew_SetReg1(pVBInfo->P3d4, 0x83, 0x00);
1557 printk("181");
1558
1559 printk("182");
1560
1561 XGI_SenseCRT1(pVBInfo);
1562
1563 printk("183");
1564 /* XGINew_DetectMonitor(HwDeviceExtension); */
1565 pVBInfo->IF_DEF_CH7007 = 0;
1566 if ((HwDeviceExtension->jChipType == XG21) && (pVBInfo->IF_DEF_CH7007)) {
1567 printk("184");
1568 XGI_GetSenseStatus(HwDeviceExtension, pVBInfo); /* sense CRT2 */
1569 printk("185");
1570
1571 }
1572 if (HwDeviceExtension->jChipType == XG21) {
1573 printk("186");
1574
1575 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x32, ~Monitor1Sense, Monitor1Sense); /* Z9 default has CRT */
1576 temp = GetXG21FPBits(pVBInfo);
1577 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x37, ~0x01, temp);
1578 printk("187");
1579
1580 }
1581 if (HwDeviceExtension->jChipType == XG27) {
1582 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x32, ~Monitor1Sense, Monitor1Sense); /* Z9 default has CRT */
1583 temp = GetXG27FPBits(pVBInfo);
1584 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x37, ~0x03, temp);
1585 }
1586 printk("19");
1587
1588 if (HwDeviceExtension->jChipType >= XG40) {
1589 if (HwDeviceExtension->jChipType >= XG40)
1590 XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
1591
1592 XGINew_SetDRAMDefaultRegister340(HwDeviceExtension, pVBInfo->P3d4, pVBInfo);
1593
1594 printk("20");
1595 XGINew_SetDRAMSize_340(HwDeviceExtension, pVBInfo);
1596 printk("21");
1597 } /* XG40 */
1598
1599 printk("22");
1600
1601 /* SetDefExt2Regs begin */
1602 /*
1603 AGP = 1;
1604 temp = (unsigned char) XGINew_GetReg1(pVBInfo->P3c4, 0x3A);
1605 temp &= 0x30;
1606 if (temp == 0x30)
1607 AGP = 0;
1608
1609 if (AGP == 0)
1610 *pVBInfo->pSR21 &= 0xEF;
1611
1612 XGINew_SetReg1(pVBInfo->P3c4, 0x21, *pVBInfo->pSR21);
1613 if (AGP == 1)
1614 *pVBInfo->pSR22 &= 0x20;
1615 XGINew_SetReg1(pVBInfo->P3c4, 0x22, *pVBInfo->pSR22);
1616 */
1617 /* base = 0x80000000; */
1618 /* OutPortLong(0xcf8, base); */
1619 /* Temp = (InPortLong(0xcfc) & 0xFFFF); */
1620 /* if (Temp == 0x1039) { */
1621 XGINew_SetReg1(pVBInfo->P3c4, 0x22, (unsigned char) ((*pVBInfo->pSR22) & 0xFE));
1622 /* } else { */
1623 /* XGINew_SetReg1(pVBInfo->P3c4, 0x22, *pVBInfo->pSR22); */
1624 /* } */
1625
1626 XGINew_SetReg1(pVBInfo->P3c4, 0x21, *pVBInfo->pSR21);
1627
1628 printk("23");
1629
1630 XGINew_ChkSenseStatus(HwDeviceExtension, pVBInfo);
1631 XGINew_SetModeScratch(HwDeviceExtension, pVBInfo);
1632
1633 printk("24");
1634
1635 XGINew_SetReg1(pVBInfo->P3d4, 0x8c, 0x87);
1636 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x31);
1637 printk("25");
1638
1639 return 1;
1640} /* end of init */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-22 08:32:38 -0400