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authorHaojian Zhuang <haojian.zhuang@marvell.com>2010-11-23 22:54:19 -0500
committerEric Miao <eric.y.miao@gmail.com>2010-12-18 08:02:14 -0500
commita4553358d94b4a1f3e6f24aacfd076022ac14855 (patch)
tree7d6d7909730801a6f512aa2a7f637353ce0931bf
parentaae8224ddd72e045bb92eaf6b73b89282c771c69 (diff)
ARM: pxa: support pxa95x
The core of PXA955 is PJ4. Add new PJ4 support. And add new macro CONFIG_PXA95x. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Diffstat
-rw-r--r--arch/arm/mach-pxa/Kconfig12
-rw-r--r--arch/arm/mach-pxa/Makefile1
-rw-r--r--arch/arm/mach-pxa/clock-pxa3xx.c2
-rw-r--r--arch/arm/mach-pxa/clock.h2
-rw-r--r--arch/arm/mach-pxa/devices.c247
-rw-r--r--arch/arm/mach-pxa/generic.c8
-rw-r--r--arch/arm/mach-pxa/generic.h3
-rw-r--r--arch/arm/mach-pxa/include/mach/hardware.h34
-rw-r--r--arch/arm/mach-pxa/include/mach/irqs.h1
-rw-r--r--arch/arm/mach-pxa/pxa3xx.c6
-rw-r--r--arch/arm/mach-pxa/pxa930.c2
-rw-r--r--arch/arm/mach-pxa/pxa95x.c308
-rw-r--r--arch/arm/mm/Kconfig6
-rw-r--r--arch/arm/plat-pxa/Makefile1
-rw-r--r--arch/arm/plat-pxa/include/plat/mfp.h4
15 files changed, 486 insertions, 151 deletions
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index dd235ecc9d6..d4076594af4 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -651,11 +651,17 @@ config CPU_PXA935
651 help 651 help
652 PXA935 (codename Tavor-P65) 652 PXA935 (codename Tavor-P65)
653 653
654config CPU_PXA950 654config PXA95x
655 bool 655 bool
656 select CPU_PXA930 656 select CPU_PJ4
657 help
658 Select code specific to PXA95x variants
659
660config CPU_PXA955
661 bool
662 select PXA95x
657 help 663 help
658 PXA950 (codename Tavor-PV2) 664 PXA950 (codename MG1)
659 665
660config PXA_SHARP_C7xx 666config PXA_SHARP_C7xx
661 bool 667 bool
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index c90789e3db1..d7f359240d2 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -19,6 +19,7 @@ endif
19obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o clock-pxa2xx.o pxa2xx.o pxa25x.o 19obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o clock-pxa2xx.o pxa2xx.o pxa25x.o
20obj-$(CONFIG_PXA27x) += mfp-pxa2xx.o clock-pxa2xx.o pxa2xx.o pxa27x.o 20obj-$(CONFIG_PXA27x) += mfp-pxa2xx.o clock-pxa2xx.o pxa2xx.o pxa27x.o
21obj-$(CONFIG_PXA3xx) += mfp-pxa3xx.o clock-pxa3xx.o pxa3xx.o smemc.o pxa3xx-ulpi.o 21obj-$(CONFIG_PXA3xx) += mfp-pxa3xx.o clock-pxa3xx.o pxa3xx.o smemc.o pxa3xx-ulpi.o
22obj-$(CONFIG_PXA95x) += mfp-pxa3xx.o clock-pxa3xx.o pxa95x.o smemc.o
22obj-$(CONFIG_CPU_PXA300) += pxa300.o 23obj-$(CONFIG_CPU_PXA300) += pxa300.o
23obj-$(CONFIG_CPU_PXA320) += pxa320.o 24obj-$(CONFIG_CPU_PXA320) += pxa320.o
24obj-$(CONFIG_CPU_PXA930) += pxa930.o 25obj-$(CONFIG_CPU_PXA930) += pxa930.o
diff --git a/arch/arm/mach-pxa/clock-pxa3xx.c b/arch/arm/mach-pxa/clock-pxa3xx.c
index dd122d98175..25be4adf6f4 100644
--- a/arch/arm/mach-pxa/clock-pxa3xx.c
+++ b/arch/arm/mach-pxa/clock-pxa3xx.c
@@ -192,7 +192,7 @@ struct sysdev_class pxa3xx_clock_sysclass = {
192 192
193static int __init pxa3xx_clock_init(void) 193static int __init pxa3xx_clock_init(void)
194{ 194{
195 if (cpu_is_pxa3xx()) 195 if (cpu_is_pxa3xx() || cpu_is_pxa95x())
196 return sysdev_class_register(&pxa3xx_clock_sysclass); 196 return sysdev_class_register(&pxa3xx_clock_sysclass);
197 return 0; 197 return 0;
198} 198}
diff --git a/arch/arm/mach-pxa/clock.h b/arch/arm/mach-pxa/clock.h
index cf2cbd0b4ea..3a607521dc2 100644
--- a/arch/arm/mach-pxa/clock.h
+++ b/arch/arm/mach-pxa/clock.h
@@ -56,7 +56,7 @@ void clk_pxa2xx_cken_disable(struct clk *clk);
56 56
57extern struct sysdev_class pxa2xx_clock_sysclass; 57extern struct sysdev_class pxa2xx_clock_sysclass;
58 58
59#ifdef CONFIG_PXA3xx 59#if defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x)
60#define DEFINE_PXA3_CKEN(_name, _cken, _rate, _delay) \ 60#define DEFINE_PXA3_CKEN(_name, _cken, _rate, _delay) \
61struct clk clk_##_name = { \ 61struct clk clk_##_name = { \
62 .ops = &clk_pxa3xx_cken_ops, \ 62 .ops = &clk_pxa3xx_cken_ops, \
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index aaa1166df96..022c2fa4af0 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -342,27 +342,6 @@ struct platform_device pxa27x_device_i2c_power = {
342}; 342};
343#endif 343#endif
344 344
345#ifdef CONFIG_PXA3xx
346static struct resource pxa3xx_resources_i2c_power[] = {
347 {
348 .start = 0x40f500c0,
349 .end = 0x40f500d3,
350 .flags = IORESOURCE_MEM,
351 }, {
352 .start = IRQ_PWRI2C,
353 .end = IRQ_PWRI2C,
354 .flags = IORESOURCE_IRQ,
355 },
356};
357
358struct platform_device pxa3xx_device_i2c_power = {
359 .name = "pxa3xx-pwri2c",
360 .id = 1,
361 .resource = pxa3xx_resources_i2c_power,
362 .num_resources = ARRAY_SIZE(pxa3xx_resources_i2c_power),
363};
364#endif
365
366static struct resource pxai2s_resources[] = { 345static struct resource pxai2s_resources[] = {
367 { 346 {
368 .start = 0x40400000, 347 .start = 0x40400000,
@@ -633,30 +612,35 @@ struct platform_device pxa25x_device_assp = {
633#endif /* CONFIG_PXA25x */ 612#endif /* CONFIG_PXA25x */
634 613
635#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) 614#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
636 615static struct resource pxa27x_resource_camera[] = {
637static struct resource pxa27x_resource_keypad[] = {
638 [0] = { 616 [0] = {
639 .start = 0x41500000, 617 .start = 0x50000000,
640 .end = 0x4150004c, 618 .end = 0x50000fff,
641 .flags = IORESOURCE_MEM, 619 .flags = IORESOURCE_MEM,
642 }, 620 },
643 [1] = { 621 [1] = {
644 .start = IRQ_KEYPAD, 622 .start = IRQ_CAMERA,
645 .end = IRQ_KEYPAD, 623 .end = IRQ_CAMERA,
646 .flags = IORESOURCE_IRQ, 624 .flags = IORESOURCE_IRQ,
647 }, 625 },
648}; 626};
649 627
650struct platform_device pxa27x_device_keypad = { 628static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
651 .name = "pxa27x-keypad", 629
652 .id = -1, 630static struct platform_device pxa27x_device_camera = {
653 .resource = pxa27x_resource_keypad, 631 .name = "pxa27x-camera",
654 .num_resources = ARRAY_SIZE(pxa27x_resource_keypad), 632 .id = 0, /* This is used to put cameras on this interface */
633 .dev = {
634 .dma_mask = &pxa27x_dma_mask_camera,
635 .coherent_dma_mask = 0xffffffff,
636 },
637 .num_resources = ARRAY_SIZE(pxa27x_resource_camera),
638 .resource = pxa27x_resource_camera,
655}; 639};
656 640
657void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info) 641void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
658{ 642{
659 pxa_register_device(&pxa27x_device_keypad, info); 643 pxa_register_device(&pxa27x_device_camera, info);
660} 644}
661 645
662static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32); 646static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
@@ -689,6 +673,33 @@ void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
689{ 673{
690 pxa_register_device(&pxa27x_device_ohci, info); 674 pxa_register_device(&pxa27x_device_ohci, info);
691} 675}
676#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
677
678#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x)
679static struct resource pxa27x_resource_keypad[] = {
680 [0] = {
681 .start = 0x41500000,
682 .end = 0x4150004c,
683 .flags = IORESOURCE_MEM,
684 },
685 [1] = {
686 .start = IRQ_KEYPAD,
687 .end = IRQ_KEYPAD,
688 .flags = IORESOURCE_IRQ,
689 },
690};
691
692struct platform_device pxa27x_device_keypad = {
693 .name = "pxa27x-keypad",
694 .id = -1,
695 .resource = pxa27x_resource_keypad,
696 .num_resources = ARRAY_SIZE(pxa27x_resource_keypad),
697};
698
699void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
700{
701 pxa_register_device(&pxa27x_device_keypad, info);
702}
692 703
693static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32); 704static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
694 705
@@ -833,79 +844,9 @@ struct platform_device pxa27x_device_pwm1 = {
833 .resource = pxa27x_resource_pwm1, 844 .resource = pxa27x_resource_pwm1,
834 .num_resources = ARRAY_SIZE(pxa27x_resource_pwm1), 845 .num_resources = ARRAY_SIZE(pxa27x_resource_pwm1),
835}; 846};
836 847#endif /* CONFIG_PXA27x || CONFIG_PXA3xx || CONFIG_PXA95x*/
837static struct resource pxa27x_resource_camera[] = {
838 [0] = {
839 .start = 0x50000000,
840 .end = 0x50000fff,
841 .flags = IORESOURCE_MEM,
842 },
843 [1] = {
844 .start = IRQ_CAMERA,
845 .end = IRQ_CAMERA,
846 .flags = IORESOURCE_IRQ,
847 },
848};
849
850static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
851
852static struct platform_device pxa27x_device_camera = {
853 .name = "pxa27x-camera",
854 .id = 0, /* This is used to put cameras on this interface */
855 .dev = {
856 .dma_mask = &pxa27x_dma_mask_camera,
857 .coherent_dma_mask = 0xffffffff,
858 },
859 .num_resources = ARRAY_SIZE(pxa27x_resource_camera),
860 .resource = pxa27x_resource_camera,
861};
862
863void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
864{
865 pxa_register_device(&pxa27x_device_camera, info);
866}
867#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
868 848
869#ifdef CONFIG_PXA3xx 849#ifdef CONFIG_PXA3xx
870static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
871
872static struct resource pxa3xx_resource_ssp4[] = {
873 [0] = {
874 .start = 0x41a00000,
875 .end = 0x41a0003f,
876 .flags = IORESOURCE_MEM,
877 },
878 [1] = {
879 .start = IRQ_SSP4,
880 .end = IRQ_SSP4,
881 .flags = IORESOURCE_IRQ,
882 },
883 [2] = {
884 /* DRCMR for RX */
885 .start = 2,
886 .end = 2,
887 .flags = IORESOURCE_DMA,
888 },
889 [3] = {
890 /* DRCMR for TX */
891 .start = 3,
892 .end = 3,
893 .flags = IORESOURCE_DMA,
894 },
895};
896
897struct platform_device pxa3xx_device_ssp4 = {
898 /* PXA3xx SSP is basically equivalent to PXA27x */
899 .name = "pxa27x-ssp",
900 .id = 3,
901 .dev = {
902 .dma_mask = &pxa3xx_ssp4_dma_mask,
903 .coherent_dma_mask = DMA_BIT_MASK(32),
904 },
905 .resource = pxa3xx_resource_ssp4,
906 .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4),
907};
908
909static struct resource pxa3xx_resources_mci2[] = { 850static struct resource pxa3xx_resources_mci2[] = {
910 [0] = { 851 [0] = {
911 .start = 0x42000000, 852 .start = 0x42000000,
@@ -984,6 +925,54 @@ void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
984 pxa_register_device(&pxa3xx_device_mci3, info); 925 pxa_register_device(&pxa3xx_device_mci3, info);
985} 926}
986 927
928static struct resource pxa3xx_resources_gcu[] = {
929 {
930 .start = 0x54000000,
931 .end = 0x54000fff,
932 .flags = IORESOURCE_MEM,
933 },
934 {
935 .start = IRQ_GCU,
936 .end = IRQ_GCU,
937 .flags = IORESOURCE_IRQ,
938 },
939};
940
941static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32);
942
943struct platform_device pxa3xx_device_gcu = {
944 .name = "pxa3xx-gcu",
945 .id = -1,
946 .num_resources = ARRAY_SIZE(pxa3xx_resources_gcu),
947 .resource = pxa3xx_resources_gcu,
948 .dev = {
949 .dma_mask = &pxa3xx_gcu_dmamask,
950 .coherent_dma_mask = 0xffffffff,
951 },
952};
953
954#endif /* CONFIG_PXA3xx */
955
956#if defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x)
957static struct resource pxa3xx_resources_i2c_power[] = {
958 {
959 .start = 0x40f500c0,
960 .end = 0x40f500d3,
961 .flags = IORESOURCE_MEM,
962 }, {
963 .start = IRQ_PWRI2C,
964 .end = IRQ_PWRI2C,
965 .flags = IORESOURCE_IRQ,
966 },
967};
968
969struct platform_device pxa3xx_device_i2c_power = {
970 .name = "pxa3xx-pwri2c",
971 .id = 1,
972 .resource = pxa3xx_resources_i2c_power,
973 .num_resources = ARRAY_SIZE(pxa3xx_resources_i2c_power),
974};
975
987static struct resource pxa3xx_resources_nand[] = { 976static struct resource pxa3xx_resources_nand[] = {
988 [0] = { 977 [0] = {
989 .start = 0x43100000, 978 .start = 0x43100000,
@@ -1027,33 +1016,45 @@ void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info)
1027 pxa_register_device(&pxa3xx_device_nand, info); 1016 pxa_register_device(&pxa3xx_device_nand, info);
1028} 1017}
1029 1018
1030static struct resource pxa3xx_resources_gcu[] = { 1019static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
1031 { 1020
1032 .start = 0x54000000, 1021static struct resource pxa3xx_resource_ssp4[] = {
1033 .end = 0x54000fff, 1022 [0] = {
1023 .start = 0x41a00000,
1024 .end = 0x41a0003f,
1034 .flags = IORESOURCE_MEM, 1025 .flags = IORESOURCE_MEM,
1035 }, 1026 },
1036 { 1027 [1] = {
1037 .start = IRQ_GCU, 1028 .start = IRQ_SSP4,
1038 .end = IRQ_GCU, 1029 .end = IRQ_SSP4,
1039 .flags = IORESOURCE_IRQ, 1030 .flags = IORESOURCE_IRQ,
1040 }, 1031 },
1032 [2] = {
1033 /* DRCMR for RX */
1034 .start = 2,
1035 .end = 2,
1036 .flags = IORESOURCE_DMA,
1037 },
1038 [3] = {
1039 /* DRCMR for TX */
1040 .start = 3,
1041 .end = 3,
1042 .flags = IORESOURCE_DMA,
1043 },
1041}; 1044};
1042 1045
1043static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32); 1046struct platform_device pxa3xx_device_ssp4 = {
1044 1047 /* PXA3xx SSP is basically equivalent to PXA27x */
1045struct platform_device pxa3xx_device_gcu = { 1048 .name = "pxa27x-ssp",
1046 .name = "pxa3xx-gcu", 1049 .id = 3,
1047 .id = -1,
1048 .num_resources = ARRAY_SIZE(pxa3xx_resources_gcu),
1049 .resource = pxa3xx_resources_gcu,
1050 .dev = { 1050 .dev = {
1051 .dma_mask = &pxa3xx_gcu_dmamask, 1051 .dma_mask = &pxa3xx_ssp4_dma_mask,
1052 .coherent_dma_mask = 0xffffffff, 1052 .coherent_dma_mask = DMA_BIT_MASK(32),
1053 }, 1053 },
1054 .resource = pxa3xx_resource_ssp4,
1055 .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4),
1054}; 1056};
1055 1057#endif /* CONFIG_PXA3xx || CONFIG_PXA95x */
1056#endif /* CONFIG_PXA3xx */
1057 1058
1058/* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1. 1059/* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1.
1059 * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */ 1060 * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */
diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c
index d2bb071b0af..d6e15f71fc0 100644
--- a/arch/arm/mach-pxa/generic.c
+++ b/arch/arm/mach-pxa/generic.c
@@ -29,6 +29,7 @@
29#include <mach/reset.h> 29#include <mach/reset.h>
30#include <mach/gpio.h> 30#include <mach/gpio.h>
31#include <mach/smemc.h> 31#include <mach/smemc.h>
32#include <mach/pxa3xx-regs.h>
32 33
33#include "generic.h" 34#include "generic.h"
34 35
@@ -36,9 +37,10 @@ void clear_reset_status(unsigned int mask)
36{ 37{
37 if (cpu_is_pxa2xx()) 38 if (cpu_is_pxa2xx())
38 pxa2xx_clear_reset_status(mask); 39 pxa2xx_clear_reset_status(mask);
39 40 else {
40 if (cpu_is_pxa3xx()) 41 /* RESET_STATUS_* has a 1:1 mapping with ARSR */
41 pxa3xx_clear_reset_status(mask); 42 ARSR = mask;
43 }
42} 44}
43 45
44unsigned long get_clock_tick_rate(void) 46unsigned long get_clock_tick_rate(void)
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h
index 0569d82d259..6205dc9a2b9 100644
--- a/arch/arm/mach-pxa/generic.h
+++ b/arch/arm/mach-pxa/generic.h
@@ -20,6 +20,7 @@ extern void __init pxa26x_init_irq(void);
20#endif 20#endif
21extern void __init pxa27x_init_irq(void); 21extern void __init pxa27x_init_irq(void);
22extern void __init pxa3xx_init_irq(void); 22extern void __init pxa3xx_init_irq(void);
23extern void __init pxa95x_init_irq(void);
23 24
24extern void __init pxa_map_io(void); 25extern void __init pxa_map_io(void);
25extern void __init pxa25x_map_io(void); 26extern void __init pxa25x_map_io(void);
@@ -54,10 +55,8 @@ static inline void pxa2xx_clear_reset_status(unsigned int mask) {}
54 55
55#ifdef CONFIG_PXA3xx 56#ifdef CONFIG_PXA3xx
56extern unsigned pxa3xx_get_clk_frequency_khz(int); 57extern unsigned pxa3xx_get_clk_frequency_khz(int);
57extern void pxa3xx_clear_reset_status(unsigned int);
58#else 58#else
59#define pxa3xx_get_clk_frequency_khz(x) (0) 59#define pxa3xx_get_clk_frequency_khz(x) (0)
60static inline void pxa3xx_clear_reset_status(unsigned int mask) {}
61#endif 60#endif
62 61
63extern struct sysdev_class pxa_irq_sysclass; 62extern struct sysdev_class pxa_irq_sysclass;
diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h
index e480d1e4813..6957ba56025 100644
--- a/arch/arm/mach-pxa/include/mach/hardware.h
+++ b/arch/arm/mach-pxa/include/mach/hardware.h
@@ -195,14 +195,15 @@
195#define __cpu_is_pxa935(id) (0) 195#define __cpu_is_pxa935(id) (0)
196#endif 196#endif
197 197
198#ifdef CONFIG_CPU_PXA950 198#ifdef CONFIG_CPU_PXA955
199#define __cpu_is_pxa950(id) \ 199#define __cpu_is_pxa955(id) \
200 ({ \ 200 ({ \
201 unsigned int _id = (id) >> 4 & 0xfff; \ 201 unsigned int _id = (id) >> 4 & 0xfff; \
202 _id == 0x697; \ 202 _id == 0x581 || _id == 0xc08 \
203 }) 203 || _id == 0xb76; \
204 })
204#else 205#else
205#define __cpu_is_pxa950(id) (0) 206#define __cpu_is_pxa955(id) (0)
206#endif 207#endif
207 208
208#define cpu_is_pxa210() \ 209#define cpu_is_pxa210() \
@@ -255,10 +256,10 @@
255 __cpu_is_pxa935(read_cpuid_id()); \ 256 __cpu_is_pxa935(read_cpuid_id()); \
256 }) 257 })
257 258
258#define cpu_is_pxa950() \ 259#define cpu_is_pxa955() \
259 ({ \ 260 ({ \
260 __cpu_is_pxa950(read_cpuid_id()); \ 261 __cpu_is_pxa955(read_cpuid_id()); \
261 }) 262 })
262 263
263 264
264/* 265/*
@@ -297,6 +298,15 @@
297#define __cpu_is_pxa93x(id) (0) 298#define __cpu_is_pxa93x(id) (0)
298#endif 299#endif
299 300
301#ifdef CONFIG_PXA95x
302#define __cpu_is_pxa95x(id) \
303 ({ \
304 __cpu_is_pxa955(id); \
305 })
306#else
307#define __cpu_is_pxa95x(id) (0)
308#endif
309
300#define cpu_is_pxa2xx() \ 310#define cpu_is_pxa2xx() \
301 ({ \ 311 ({ \
302 __cpu_is_pxa2xx(read_cpuid_id()); \ 312 __cpu_is_pxa2xx(read_cpuid_id()); \
@@ -311,6 +321,12 @@
311 ({ \ 321 ({ \
312 __cpu_is_pxa93x(read_cpuid_id()); \ 322 __cpu_is_pxa93x(read_cpuid_id()); \
313 }) 323 })
324
325#define cpu_is_pxa95x() \
326 ({ \
327 __cpu_is_pxa95x(read_cpuid_id()); \
328 })
329
314/* 330/*
315 * return current memory and LCD clock frequency in units of 10kHz 331 * return current memory and LCD clock frequency in units of 10kHz
316 */ 332 */
diff --git a/arch/arm/mach-pxa/include/mach/irqs.h b/arch/arm/mach-pxa/include/mach/irqs.h
index cb7ee2665b2..a4285fc0087 100644
--- a/arch/arm/mach-pxa/include/mach/irqs.h
+++ b/arch/arm/mach-pxa/include/mach/irqs.h
@@ -84,6 +84,7 @@
84#define IRQ_PXA935_MMC0 PXA_IRQ(72) /* MMC0 Controller (PXA935) */ 84#define IRQ_PXA935_MMC0 PXA_IRQ(72) /* MMC0 Controller (PXA935) */
85#define IRQ_PXA935_MMC1 PXA_IRQ(73) /* MMC1 Controller (PXA935) */ 85#define IRQ_PXA935_MMC1 PXA_IRQ(73) /* MMC1 Controller (PXA935) */
86#define IRQ_PXA935_MMC2 PXA_IRQ(74) /* MMC2 Controller (PXA935) */ 86#define IRQ_PXA935_MMC2 PXA_IRQ(74) /* MMC2 Controller (PXA935) */
87#define IRQ_PXA955_MMC3 PXA_IRQ(75) /* MMC3 Controller (PXA955) */
87#define IRQ_U2P PXA_IRQ(93) /* USB PHY D+/D- Lines (PXA935) */ 88#define IRQ_U2P PXA_IRQ(93) /* USB PHY D+/D- Lines (PXA935) */
88 89
89#define PXA_GPIO_IRQ_BASE PXA_IRQ(96) 90#define PXA_GPIO_IRQ_BASE PXA_IRQ(96)
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index a1c3ab26ce6..da3edcc9ac7 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -41,12 +41,6 @@
41#define PECR_IE(n) ((1 << ((n) * 2)) << 28) 41#define PECR_IE(n) ((1 << ((n) * 2)) << 28)
42#define PECR_IS(n) ((1 << ((n) * 2)) << 29) 42#define PECR_IS(n) ((1 << ((n) * 2)) << 29)
43 43
44void pxa3xx_clear_reset_status(unsigned int mask)
45{
46 /* RESET_STATUS_* has a 1:1 mapping with ARSR */
47 ARSR = mask;
48}
49
50static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1); 44static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
51static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1); 45static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
52static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1); 46static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
diff --git a/arch/arm/mach-pxa/pxa930.c b/arch/arm/mach-pxa/pxa930.c
index 7d29dd3af79..8aeacf90878 100644
--- a/arch/arm/mach-pxa/pxa930.c
+++ b/arch/arm/mach-pxa/pxa930.c
@@ -192,7 +192,7 @@ static struct mfp_addr_map pxa935_mfp_addr_map[] __initdata = {
192 192
193static int __init pxa930_init(void) 193static int __init pxa930_init(void)
194{ 194{
195 if (cpu_is_pxa930() || cpu_is_pxa935() || cpu_is_pxa950()) { 195 if (cpu_is_pxa93x()) {
196 mfp_init_base(io_p2v(MFPR_BASE)); 196 mfp_init_base(io_p2v(MFPR_BASE));
197 mfp_init_addr(pxa930_mfp_addr_map); 197 mfp_init_addr(pxa930_mfp_addr_map);
198 } 198 }
diff --git a/arch/arm/mach-pxa/pxa95x.c b/arch/arm/mach-pxa/pxa95x.c
new file mode 100644
index 00000000000..437980f7271
--- /dev/null
+++ b/arch/arm/mach-pxa/pxa95x.c
@@ -0,0 +1,308 @@
1/*
2 * linux/arch/arm/mach-pxa/pxa95x.c
3 *
4 * code specific to PXA95x aka MGx
5 *
6 * Copyright (C) 2009-2010 Marvell International Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/pm.h>
17#include <linux/platform_device.h>
18#include <linux/irq.h>
19#include <linux/io.h>
20#include <linux/sysdev.h>
21
22#include <mach/hardware.h>
23#include <mach/gpio.h>
24#include <mach/pxa3xx-regs.h>
25#include <mach/pxa930.h>
26#include <mach/reset.h>
27#include <mach/pm.h>
28#include <mach/dma.h>
29#include <mach/regs-intc.h>
30#include <plat/i2c.h>
31
32#include "generic.h"
33#include "devices.h"
34#include "clock.h"
35
36static struct mfp_addr_map pxa95x_mfp_addr_map[] __initdata = {
37
38 MFP_ADDR(GPIO0, 0x02e0),
39 MFP_ADDR(GPIO1, 0x02dc),
40 MFP_ADDR(GPIO2, 0x02e8),
41 MFP_ADDR(GPIO3, 0x02d8),
42 MFP_ADDR(GPIO4, 0x02e4),
43 MFP_ADDR(GPIO5, 0x02ec),
44 MFP_ADDR(GPIO6, 0x02f8),
45 MFP_ADDR(GPIO7, 0x02fc),
46 MFP_ADDR(GPIO8, 0x0300),
47 MFP_ADDR(GPIO9, 0x02d4),
48 MFP_ADDR(GPIO10, 0x02f4),
49 MFP_ADDR(GPIO11, 0x02f0),
50 MFP_ADDR(GPIO12, 0x0304),
51 MFP_ADDR(GPIO13, 0x0310),
52 MFP_ADDR(GPIO14, 0x0308),
53 MFP_ADDR(GPIO15, 0x030c),
54 MFP_ADDR(GPIO16, 0x04e8),
55 MFP_ADDR(GPIO17, 0x04f4),
56 MFP_ADDR(GPIO18, 0x04f8),
57 MFP_ADDR(GPIO19, 0x04fc),
58 MFP_ADDR(GPIO20, 0x0518),
59 MFP_ADDR(GPIO21, 0x051c),
60 MFP_ADDR(GPIO22, 0x04ec),
61 MFP_ADDR(GPIO23, 0x0500),
62 MFP_ADDR(GPIO24, 0x04f0),
63 MFP_ADDR(GPIO25, 0x0504),
64 MFP_ADDR(GPIO26, 0x0510),
65 MFP_ADDR(GPIO27, 0x0514),
66 MFP_ADDR(GPIO28, 0x0520),
67 MFP_ADDR(GPIO29, 0x0600),
68 MFP_ADDR(GPIO30, 0x0618),
69 MFP_ADDR(GPIO31, 0x0610),
70 MFP_ADDR(GPIO32, 0x060c),
71 MFP_ADDR(GPIO33, 0x061c),
72 MFP_ADDR(GPIO34, 0x0620),
73 MFP_ADDR(GPIO35, 0x0628),
74 MFP_ADDR(GPIO36, 0x062c),
75 MFP_ADDR(GPIO37, 0x0630),
76 MFP_ADDR(GPIO38, 0x0634),
77 MFP_ADDR(GPIO39, 0x0638),
78 MFP_ADDR(GPIO40, 0x063c),
79 MFP_ADDR(GPIO41, 0x0614),
80 MFP_ADDR(GPIO42, 0x0624),
81 MFP_ADDR(GPIO43, 0x0608),
82 MFP_ADDR(GPIO44, 0x0604),
83 MFP_ADDR(GPIO45, 0x050c),
84 MFP_ADDR(GPIO46, 0x0508),
85 MFP_ADDR(GPIO47, 0x02bc),
86 MFP_ADDR(GPIO48, 0x02b4),
87 MFP_ADDR(GPIO49, 0x02b8),
88 MFP_ADDR(GPIO50, 0x02c8),
89 MFP_ADDR(GPIO51, 0x02c0),
90 MFP_ADDR(GPIO52, 0x02c4),
91 MFP_ADDR(GPIO53, 0x02d0),
92 MFP_ADDR(GPIO54, 0x02cc),
93 MFP_ADDR(GPIO55, 0x029c),
94 MFP_ADDR(GPIO56, 0x02a0),
95 MFP_ADDR(GPIO57, 0x0294),
96 MFP_ADDR(GPIO58, 0x0298),
97 MFP_ADDR(GPIO59, 0x02a4),
98 MFP_ADDR(GPIO60, 0x02a8),
99 MFP_ADDR(GPIO61, 0x02b0),
100 MFP_ADDR(GPIO62, 0x02ac),
101 MFP_ADDR(GPIO63, 0x0640),
102 MFP_ADDR(GPIO64, 0x065c),
103 MFP_ADDR(GPIO65, 0x0648),
104 MFP_ADDR(GPIO66, 0x0644),
105 MFP_ADDR(GPIO67, 0x0674),
106 MFP_ADDR(GPIO68, 0x0658),
107 MFP_ADDR(GPIO69, 0x0654),
108 MFP_ADDR(GPIO70, 0x0660),
109 MFP_ADDR(GPIO71, 0x0668),
110 MFP_ADDR(GPIO72, 0x0664),
111 MFP_ADDR(GPIO73, 0x0650),
112 MFP_ADDR(GPIO74, 0x066c),
113 MFP_ADDR(GPIO75, 0x064c),
114 MFP_ADDR(GPIO76, 0x0670),
115 MFP_ADDR(GPIO77, 0x0678),
116 MFP_ADDR(GPIO78, 0x067c),
117 MFP_ADDR(GPIO79, 0x0694),
118 MFP_ADDR(GPIO80, 0x069c),
119 MFP_ADDR(GPIO81, 0x06a0),
120 MFP_ADDR(GPIO82, 0x06a4),
121 MFP_ADDR(GPIO83, 0x0698),
122 MFP_ADDR(GPIO84, 0x06bc),
123 MFP_ADDR(GPIO85, 0x06b4),
124 MFP_ADDR(GPIO86, 0x06b0),
125 MFP_ADDR(GPIO87, 0x06c0),
126 MFP_ADDR(GPIO88, 0x06c4),
127 MFP_ADDR(GPIO89, 0x06ac),
128 MFP_ADDR(GPIO90, 0x0680),
129 MFP_ADDR(GPIO91, 0x0684),
130 MFP_ADDR(GPIO92, 0x0688),
131 MFP_ADDR(GPIO93, 0x0690),
132 MFP_ADDR(GPIO94, 0x068c),
133 MFP_ADDR(GPIO95, 0x06a8),
134 MFP_ADDR(GPIO96, 0x06b8),
135 MFP_ADDR(GPIO97, 0x0410),
136 MFP_ADDR(GPIO98, 0x0418),
137 MFP_ADDR(GPIO99, 0x041c),
138 MFP_ADDR(GPIO100, 0x0414),
139 MFP_ADDR(GPIO101, 0x0408),
140 MFP_ADDR(GPIO102, 0x0324),
141 MFP_ADDR(GPIO103, 0x040c),
142 MFP_ADDR(GPIO104, 0x0400),
143 MFP_ADDR(GPIO105, 0x0328),
144 MFP_ADDR(GPIO106, 0x0404),
145
146 MFP_ADDR(GPIO159, 0x0524),
147 MFP_ADDR(GPIO163, 0x0534),
148 MFP_ADDR(GPIO167, 0x0544),
149 MFP_ADDR(GPIO168, 0x0548),
150 MFP_ADDR(GPIO169, 0x054c),
151 MFP_ADDR(GPIO170, 0x0550),
152 MFP_ADDR(GPIO171, 0x0554),
153 MFP_ADDR(GPIO172, 0x0558),
154 MFP_ADDR(GPIO173, 0x055c),
155
156 MFP_ADDR(nXCVREN, 0x0204),
157 MFP_ADDR(DF_CLE_nOE, 0x020c),
158 MFP_ADDR(DF_nADV1_ALE, 0x0218),
159 MFP_ADDR(DF_SCLK_E, 0x0214),
160 MFP_ADDR(DF_SCLK_S, 0x0210),
161 MFP_ADDR(nBE0, 0x021c),
162 MFP_ADDR(nBE1, 0x0220),
163 MFP_ADDR(DF_nADV2_ALE, 0x0224),
164 MFP_ADDR(DF_INT_RnB, 0x0228),
165 MFP_ADDR(DF_nCS0, 0x022c),
166 MFP_ADDR(DF_nCS1, 0x0230),
167 MFP_ADDR(nLUA, 0x0254),
168 MFP_ADDR(nLLA, 0x0258),
169 MFP_ADDR(DF_nWE, 0x0234),
170 MFP_ADDR(DF_nRE_nOE, 0x0238),
171 MFP_ADDR(DF_ADDR0, 0x024c),
172 MFP_ADDR(DF_ADDR1, 0x0250),
173 MFP_ADDR(DF_ADDR2, 0x025c),
174 MFP_ADDR(DF_ADDR3, 0x0260),
175 MFP_ADDR(DF_IO0, 0x023c),
176 MFP_ADDR(DF_IO1, 0x0240),
177 MFP_ADDR(DF_IO2, 0x0244),
178 MFP_ADDR(DF_IO3, 0x0248),
179 MFP_ADDR(DF_IO4, 0x0264),
180 MFP_ADDR(DF_IO5, 0x0268),
181 MFP_ADDR(DF_IO6, 0x026c),
182 MFP_ADDR(DF_IO7, 0x0270),
183 MFP_ADDR(DF_IO8, 0x0274),
184 MFP_ADDR(DF_IO9, 0x0278),
185 MFP_ADDR(DF_IO10, 0x027c),
186 MFP_ADDR(DF_IO11, 0x0280),
187 MFP_ADDR(DF_IO12, 0x0284),
188 MFP_ADDR(DF_IO13, 0x0288),
189 MFP_ADDR(DF_IO14, 0x028c),
190 MFP_ADDR(DF_IO15, 0x0290),
191
192 MFP_ADDR(GSIM_UIO, 0x0314),
193 MFP_ADDR(GSIM_UCLK, 0x0318),
194 MFP_ADDR(GSIM_UDET, 0x031c),
195 MFP_ADDR(GSIM_nURST, 0x0320),
196
197 MFP_ADDR(PMIC_INT, 0x06c8),
198
199 MFP_ADDR(RDY, 0x0200),
200
201 MFP_ADDR_END,
202};
203
204static DEFINE_CK(pxa95x_lcd, LCD, &clk_pxa3xx_hsio_ops);
205static DEFINE_CLK(pxa95x_pout, &clk_pxa3xx_pout_ops, 13000000, 70);
206static DEFINE_PXA3_CKEN(pxa95x_ffuart, FFUART, 14857000, 1);
207static DEFINE_PXA3_CKEN(pxa95x_btuart, BTUART, 14857000, 1);
208static DEFINE_PXA3_CKEN(pxa95x_stuart, STUART, 14857000, 1);
209static DEFINE_PXA3_CKEN(pxa95x_i2c, I2C, 32842000, 0);
210static DEFINE_PXA3_CKEN(pxa95x_keypad, KEYPAD, 32768, 0);
211static DEFINE_PXA3_CKEN(pxa95x_ssp1, SSP1, 13000000, 0);
212static DEFINE_PXA3_CKEN(pxa95x_ssp2, SSP2, 13000000, 0);
213static DEFINE_PXA3_CKEN(pxa95x_ssp3, SSP3, 13000000, 0);
214static DEFINE_PXA3_CKEN(pxa95x_ssp4, SSP4, 13000000, 0);
215static DEFINE_PXA3_CKEN(pxa95x_pwm0, PWM0, 13000000, 0);
216static DEFINE_PXA3_CKEN(pxa95x_pwm1, PWM1, 13000000, 0);
217
218static struct clk_lookup pxa95x_clkregs[] = {
219 INIT_CLKREG(&clk_pxa95x_pout, NULL, "CLK_POUT"),
220 /* Power I2C clock is always on */
221 INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
222 INIT_CLKREG(&clk_pxa95x_lcd, "pxa2xx-fb", NULL),
223 INIT_CLKREG(&clk_pxa95x_ffuart, "pxa2xx-uart.0", NULL),
224 INIT_CLKREG(&clk_pxa95x_btuart, "pxa2xx-uart.1", NULL),
225 INIT_CLKREG(&clk_pxa95x_stuart, "pxa2xx-uart.2", NULL),
226 INIT_CLKREG(&clk_pxa95x_stuart, "pxa2xx-ir", "UARTCLK"),
227 INIT_CLKREG(&clk_pxa95x_i2c, "pxa2xx-i2c.0", NULL),
228 INIT_CLKREG(&clk_pxa95x_keypad, "pxa27x-keypad", NULL),
229 INIT_CLKREG(&clk_pxa95x_ssp1, "pxa27x-ssp.0", NULL),
230 INIT_CLKREG(&clk_pxa95x_ssp2, "pxa27x-ssp.1", NULL),
231 INIT_CLKREG(&clk_pxa95x_ssp3, "pxa27x-ssp.2", NULL),
232 INIT_CLKREG(&clk_pxa95x_ssp4, "pxa27x-ssp.3", NULL),
233 INIT_CLKREG(&clk_pxa95x_pwm0, "pxa27x-pwm.0", NULL),
234 INIT_CLKREG(&clk_pxa95x_pwm1, "pxa27x-pwm.1", NULL),
235};
236
237void __init pxa95x_init_irq(void)
238{
239 pxa_init_irq(96, NULL);
240 pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL);
241}
242
243/*
244 * device registration specific to PXA93x.
245 */
246
247void __init pxa95x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
248{
249 pxa_register_device(&pxa3xx_device_i2c_power, info);
250}
251
252static struct platform_device *devices[] __initdata = {
253 &sa1100_device_rtc,
254 &pxa_device_rtc,
255 &pxa27x_device_ssp1,
256 &pxa27x_device_ssp2,
257 &pxa27x_device_ssp3,
258 &pxa3xx_device_ssp4,
259 &pxa27x_device_pwm0,
260 &pxa27x_device_pwm1,
261};
262
263static struct sys_device pxa95x_sysdev[] = {
264 {
265 .cls = &pxa_irq_sysclass,
266 }, {
267 .cls = &pxa_gpio_sysclass,
268 }, {
269 .cls = &pxa3xx_clock_sysclass,
270 }
271};
272
273static int __init pxa95x_init(void)
274{
275 int ret = 0, i;
276
277 if (cpu_is_pxa95x()) {
278 mfp_init_base(io_p2v(MFPR_BASE));
279 mfp_init_addr(pxa95x_mfp_addr_map);
280
281 reset_status = ARSR;
282
283 /*
284 * clear RDH bit every time after reset
285 *
286 * Note: the last 3 bits DxS are write-1-to-clear so carefully
287 * preserve them here in case they will be referenced later
288 */
289 ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
290
291 clkdev_add_table(pxa95x_clkregs, ARRAY_SIZE(pxa95x_clkregs));
292
293 if ((ret = pxa_init_dma(IRQ_DMA, 32)))
294 return ret;
295
296 for (i = 0; i < ARRAY_SIZE(pxa95x_sysdev); i++) {
297 ret = sysdev_register(&pxa95x_sysdev[i]);
298 if (ret)
299 pr_err("failed to register sysdev[%d]\n", i);
300 }
301
302 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
303 }
304
305 return ret;
306}
307
308postcore_initcall(pxa95x_init);
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 4414a01e1e8..ede1763429a 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -382,6 +382,12 @@ config CPU_FEROCEON_OLD_ID
382 for which the CPU ID is equal to the ARM926 ID. 382 for which the CPU ID is equal to the ARM926 ID.
383 Relevant for Feroceon-1850 and early Feroceon-2850. 383 Relevant for Feroceon-1850 and early Feroceon-2850.
384 384
385# Marvell PJ4
386config CPU_PJ4
387 bool
388 select CPU_V7
389 select ARM_THUMBEE
390
385# ARMv6 391# ARMv6
386config CPU_V6 392config CPU_V6
387 bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || ARCH_DOVE 393 bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || ARCH_DOVE
diff --git a/arch/arm/plat-pxa/Makefile b/arch/arm/plat-pxa/Makefile
index 4aacdd12c9c..3aca5ba0f87 100644
--- a/arch/arm/plat-pxa/Makefile
+++ b/arch/arm/plat-pxa/Makefile
@@ -6,6 +6,7 @@ obj-y := dma.o
6 6
7obj-$(CONFIG_GENERIC_GPIO) += gpio.o 7obj-$(CONFIG_GENERIC_GPIO) += gpio.o
8obj-$(CONFIG_PXA3xx) += mfp.o 8obj-$(CONFIG_PXA3xx) += mfp.o
9obj-$(CONFIG_PXA95x) += mfp.o
9obj-$(CONFIG_ARCH_MMP) += mfp.o 10obj-$(CONFIG_ARCH_MMP) += mfp.o
10 11
11obj-$(CONFIG_HAVE_PWM) += pwm.o 12obj-$(CONFIG_HAVE_PWM) += pwm.o
diff --git a/arch/arm/plat-pxa/include/plat/mfp.h b/arch/arm/plat-pxa/include/plat/mfp.h
index 9e604c80618..75f65647124 100644
--- a/arch/arm/plat-pxa/include/plat/mfp.h
+++ b/arch/arm/plat-pxa/include/plat/mfp.h
@@ -423,7 +423,7 @@ typedef unsigned long mfp_cfg_t;
423 ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK | MFP_LPM_STATE_MASK)) |\ 423 ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK | MFP_LPM_STATE_MASK)) |\
424 (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv | MFP_LPM_##lpm)) 424 (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv | MFP_LPM_##lpm))
425 425
426#if defined(CONFIG_PXA3xx) || defined(CONFIG_ARCH_MMP) 426#if defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x) || defined(CONFIG_ARCH_MMP)
427/* 427/*
428 * each MFP pin will have a MFPR register, since the offset of the 428 * each MFP pin will have a MFPR register, since the offset of the
429 * register varies between processors, the processor specific code 429 * register varies between processors, the processor specific code
@@ -470,6 +470,6 @@ void mfp_write(int mfp, unsigned long mfpr_val);
470void mfp_config(unsigned long *mfp_cfgs, int num); 470void mfp_config(unsigned long *mfp_cfgs, int num);
471void mfp_config_run(void); 471void mfp_config_run(void);
472void mfp_config_lpm(void); 472void mfp_config_lpm(void);
473#endif /* CONFIG_PXA3xx || CONFIG_ARCH_MMP */ 473#endif /* CONFIG_PXA3xx || CONFIG_PXA95x || CONFIG_ARCH_MMP */
474 474
475#endif /* __ASM_PLAT_MFP_H */ 475#endif /* __ASM_PLAT_MFP_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 06:31:24 -0500