diff options
| author | Benoit Cousson <b-cousson@ti.com> | 2011-07-09 21:15:06 -0400 |
|---|---|---|
| committer | Paul Walmsley <paul@pwsan.com> | 2011-07-09 21:15:06 -0400 |
| commit | a3b90ad8d1fb0ddaa6964d83886283ae3e338cea (patch) | |
| tree | dca688419889321cf46a6715a1f891f2634e1721 | |
| parent | 7b342a8d4c310b5cc153b35ea80aab03ddf2e6da (diff) | |
OMAP4: prcm_mpu: Fix indent in few macros
Some maros were not well aligned. Re-align them.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
| -rw-r--r-- | arch/arm/mach-omap2/prcm_mpu44xx.h | 69 |
1 files changed, 34 insertions, 35 deletions
diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.h b/arch/arm/mach-omap2/prcm_mpu44xx.h index d22d1b43bcc..8a6e250f04b 100644 --- a/arch/arm/mach-omap2/prcm_mpu44xx.h +++ b/arch/arm/mach-omap2/prcm_mpu44xx.h | |||
| @@ -31,7 +31,6 @@ | |||
| 31 | OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (inst) + (reg)) | 31 | OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (inst) + (reg)) |
| 32 | 32 | ||
| 33 | /* PRCM_MPU instances */ | 33 | /* PRCM_MPU instances */ |
| 34 | |||
| 35 | #define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST 0x0000 | 34 | #define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST 0x0000 |
| 36 | #define OMAP4430_PRCM_MPU_DEVICE_PRM_INST 0x0200 | 35 | #define OMAP4430_PRCM_MPU_DEVICE_PRM_INST 0x0200 |
| 37 | #define OMAP4430_PRCM_MPU_CPU0_INST 0x0400 | 36 | #define OMAP4430_PRCM_MPU_CPU0_INST 0x0400 |
| @@ -52,46 +51,46 @@ | |||
| 52 | */ | 51 | */ |
| 53 | 52 | ||
| 54 | /* PRCM_MPU.OCP_SOCKET_PRCM register offsets */ | 53 | /* PRCM_MPU.OCP_SOCKET_PRCM register offsets */ |
| 55 | #define OMAP4_REVISION_PRCM_OFFSET 0x0000 | 54 | #define OMAP4_REVISION_PRCM_OFFSET 0x0000 |
| 56 | #define OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000) | 55 | #define OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000) |
| 57 | 56 | ||
| 58 | /* PRCM_MPU.DEVICE_PRM register offsets */ | 57 | /* PRCM_MPU.DEVICE_PRM register offsets */ |
| 59 | #define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000 | 58 | #define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000 |
| 60 | #define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0000) | 59 | #define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0000) |
| 61 | #define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004 | 60 | #define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004 |
| 62 | #define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0004) | 61 | #define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0004) |
| 63 | 62 | ||
| 64 | /* PRCM_MPU.CPU0 register offsets */ | 63 | /* PRCM_MPU.CPU0 register offsets */ |
| 65 | #define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000 | 64 | #define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000 |
| 66 | #define OMAP4430_PM_CPU0_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0000) | 65 | #define OMAP4430_PM_CPU0_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0000) |
| 67 | #define OMAP4_PM_CPU0_PWRSTST_OFFSET 0x0004 | 66 | #define OMAP4_PM_CPU0_PWRSTST_OFFSET 0x0004 |
| 68 | #define OMAP4430_PM_CPU0_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0004) | 67 | #define OMAP4430_PM_CPU0_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0004) |
| 69 | #define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0008 | 68 | #define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0008 |
| 70 | #define OMAP4430_RM_CPU0_CPU0_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0008) | 69 | #define OMAP4430_RM_CPU0_CPU0_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0008) |
| 71 | #define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x000c | 70 | #define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x000c |
| 72 | #define OMAP4430_RM_CPU0_CPU0_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x000c) | 71 | #define OMAP4430_RM_CPU0_CPU0_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x000c) |
| 73 | #define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET 0x0010 | 72 | #define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET 0x0010 |
| 74 | #define OMAP4430_RM_CPU0_CPU0_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0010) | 73 | #define OMAP4430_RM_CPU0_CPU0_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0010) |
| 75 | #define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0014 | 74 | #define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0014 |
| 76 | #define OMAP4430_CM_CPU0_CPU0_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0014) | 75 | #define OMAP4430_CM_CPU0_CPU0_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0014) |
| 77 | #define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET 0x0018 | 76 | #define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET 0x0018 |
| 78 | #define OMAP4430_CM_CPU0_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0018) | 77 | #define OMAP4430_CM_CPU0_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0018) |
| 79 | 78 | ||
| 80 | /* PRCM_MPU.CPU1 register offsets */ | 79 | /* PRCM_MPU.CPU1 register offsets */ |
| 81 | #define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET 0x0000 | 80 | #define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET 0x0000 |
| 82 | #define OMAP4430_PM_CPU1_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0000) | 81 | #define OMAP4430_PM_CPU1_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0000) |
| 83 | #define OMAP4_PM_CPU1_PWRSTST_OFFSET 0x0004 | 82 | #define OMAP4_PM_CPU1_PWRSTST_OFFSET 0x0004 |
| 84 | #define OMAP4430_PM_CPU1_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0004) | 83 | #define OMAP4430_PM_CPU1_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0004) |
| 85 | #define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0008 | 84 | #define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0008 |
| 86 | #define OMAP4430_RM_CPU1_CPU1_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0008) | 85 | #define OMAP4430_RM_CPU1_CPU1_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0008) |
| 87 | #define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x000c | 86 | #define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x000c |
| 88 | #define OMAP4430_RM_CPU1_CPU1_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x000c) | 87 | #define OMAP4430_RM_CPU1_CPU1_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x000c) |
| 89 | #define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET 0x0010 | 88 | #define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET 0x0010 |
| 90 | #define OMAP4430_RM_CPU1_CPU1_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0010) | 89 | #define OMAP4430_RM_CPU1_CPU1_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0010) |
| 91 | #define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0014 | 90 | #define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0014 |
| 92 | #define OMAP4430_CM_CPU1_CPU1_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0014) | 91 | #define OMAP4430_CM_CPU1_CPU1_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0014) |
| 93 | #define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018 | 92 | #define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018 |
| 94 | #define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018) | 93 | #define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018) |
| 95 | 94 | ||
| 96 | /* Function prototypes */ | 95 | /* Function prototypes */ |
| 97 | # ifndef __ASSEMBLER__ | 96 | # ifndef __ASSEMBLER__ |