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authorRussell King <rmk+kernel@arm.linux.org.uk>2010-05-17 03:49:25 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-05-17 03:49:25 -0400
commita3685f00652af83f12b63e3b4ef48f29581ba48b (patch)
tree18ec9eed3deabf3c6b9bec206765a4dd0d8cf9ec
parentb12f3cbd7a9a869eae1eb108da02526b132ba80b (diff)
parent63b1f51b2405573d47bf5b9ab6e7cd5c697d3dcc (diff)
Merge branch 'for-rmk/2635' of git://git.fluff.org/bjdooks/linux into devel-stable
Diffstat
-rw-r--r--arch/arm/Kconfig7
-rw-r--r--arch/arm/Makefile2
-rw-r--r--arch/arm/mach-s3c2410/Kconfig1
-rw-r--r--arch/arm/mach-s3c2410/h1940-bluetooth.c32
-rw-r--r--arch/arm/mach-s3c2410/include/mach/dma.h2
-rw-r--r--arch/arm/mach-s3c2410/include/mach/gpio-fns.h47
-rw-r--r--arch/arm/mach-s3c2410/include/mach/gpio-nrs.h12
-rw-r--r--arch/arm/mach-s3c2410/include/mach/irqs.h25
-rw-r--r--arch/arm/mach-s3c2410/include/mach/map.h5
-rw-r--r--arch/arm/mach-s3c2410/include/mach/regs-clock.h2
-rw-r--r--arch/arm/mach-s3c2410/include/mach/regs-dsc.h36
-rw-r--r--arch/arm/mach-s3c2410/include/mach/regs-gpio.h45
-rw-r--r--arch/arm/mach-s3c2410/include/mach/regs-gpioj.h36
-rw-r--r--arch/arm/mach-s3c2410/include/mach/regs-irq.h10
-rw-r--r--arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h30
-rw-r--r--arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h24
-rw-r--r--arch/arm/mach-s3c2410/include/mach/uncompress.h4
-rw-r--r--arch/arm/mach-s3c2410/mach-amlm5900.c5
-rw-r--r--arch/arm/mach-s3c2410/mach-bast.c9
-rw-r--r--arch/arm/mach-s3c2410/mach-h1940.c20
-rw-r--r--arch/arm/mach-s3c2410/mach-n30.c7
-rw-r--r--arch/arm/mach-s3c2410/mach-qt2410.c10
-rw-r--r--arch/arm/mach-s3c2410/mach-vr1000.c5
-rw-r--r--arch/arm/mach-s3c2410/s3c2410.c8
-rw-r--r--arch/arm/mach-s3c2412/Kconfig3
-rw-r--r--arch/arm/mach-s3c2412/mach-jive.c26
-rw-r--r--arch/arm/mach-s3c2412/mach-smdk2413.c8
-rw-r--r--arch/arm/mach-s3c2416/Kconfig38
-rw-r--r--arch/arm/mach-s3c2416/Makefile19
-rw-r--r--arch/arm/mach-s3c2416/clock.c135
-rw-r--r--arch/arm/mach-s3c2416/irq.c254
-rw-r--r--arch/arm/mach-s3c2416/mach-smdk2416.c150
-rw-r--r--arch/arm/mach-s3c2416/s3c2416.c128
-rw-r--r--arch/arm/mach-s3c2440/Kconfig1
-rw-r--r--arch/arm/mach-s3c2440/mach-mini2440.c23
-rw-r--r--arch/arm/mach-s3c2440/mach-nexcoder.c9
-rw-r--r--arch/arm/mach-s3c2440/mach-osiris.c5
-rw-r--r--arch/arm/mach-s3c2440/s3c2440.c8
-rw-r--r--arch/arm/mach-s3c2443/Kconfig1
-rw-r--r--arch/arm/mach-s3c2443/clock.c479
-rw-r--r--arch/arm/mach-s3c64xx/gpiolib.c6
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/pll.h35
-rw-r--r--arch/arm/mach-s5p6440/gpio.c5
-rw-r--r--arch/arm/plat-s3c24xx/Kconfig7
-rw-r--r--arch/arm/plat-s3c24xx/Makefile1
-rw-r--r--arch/arm/plat-s3c24xx/common-smdk.c9
-rw-r--r--arch/arm/plat-s3c24xx/cpu.c21
-rw-r--r--arch/arm/plat-s3c24xx/gpio.c144
-rw-r--r--arch/arm/plat-s3c24xx/gpiolib.c60
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/pll.h25
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/s3c2416.h31
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/s3c2443.h19
-rw-r--r--arch/arm/plat-s3c24xx/pm.c9
-rw-r--r--arch/arm/plat-s3c24xx/s3c2410-clock.c15
-rw-r--r--arch/arm/plat-s3c24xx/s3c2443-clock.c472
-rw-r--r--arch/arm/plat-s3c24xx/setup-i2c.c5
-rw-r--r--arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c16
-rw-r--r--arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c16
-rw-r--r--arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c16
-rw-r--r--arch/arm/plat-samsung/clock.c15
-rw-r--r--arch/arm/plat-samsung/gpio-config.c103
-rw-r--r--arch/arm/plat-samsung/include/plat/clock.h1
-rw-r--r--arch/arm/plat-samsung/include/plat/cpu.h1
-rw-r--r--arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h58
-rw-r--r--arch/arm/plat-samsung/include/plat/gpio-cfg.h11
-rw-r--r--arch/arm/plat-samsung/include/plat/gpio-core.h3
-rw-r--r--arch/arm/plat-samsung/include/plat/pll6553x.h51
-rw-r--r--drivers/serial/Kconfig7
68 files changed, 2016 insertions, 817 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 3806d636a40..ae0ecdaf353 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -657,7 +657,7 @@ config ARCH_SA1100
657 Support for StrongARM 11x0 based boards. 657 Support for StrongARM 11x0 based boards.
658 658
659config ARCH_S3C2410 659config ARCH_S3C2410
660 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2440, S3C2442, S3C2443" 660 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
661 select GENERIC_GPIO 661 select GENERIC_GPIO
662 select ARCH_HAS_CPUFREQ 662 select ARCH_HAS_CPUFREQ
663 select HAVE_CLK 663 select HAVE_CLK
@@ -666,6 +666,10 @@ config ARCH_S3C2410
666 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or 666 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
667 the Samsung SMDK2410 development board (and derivatives). 667 the Samsung SMDK2410 development board (and derivatives).
668 668
669 Note, the S3C2416 and the S3C2450 are so close that they even share
670 the same SoC ID code. This means that there is no seperate machine
671 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
672
669config ARCH_S3C64XX 673config ARCH_S3C64XX
670 bool "Samsung S3C64XX" 674 bool "Samsung S3C64XX"
671 select PLAT_SAMSUNG 675 select PLAT_SAMSUNG
@@ -904,6 +908,7 @@ if ARCH_S3C2410
904source "arch/arm/mach-s3c2400/Kconfig" 908source "arch/arm/mach-s3c2400/Kconfig"
905source "arch/arm/mach-s3c2410/Kconfig" 909source "arch/arm/mach-s3c2410/Kconfig"
906source "arch/arm/mach-s3c2412/Kconfig" 910source "arch/arm/mach-s3c2412/Kconfig"
911source "arch/arm/mach-s3c2416/Kconfig"
907source "arch/arm/mach-s3c2440/Kconfig" 912source "arch/arm/mach-s3c2440/Kconfig"
908source "arch/arm/mach-s3c2443/Kconfig" 913source "arch/arm/mach-s3c2443/Kconfig"
909endif 914endif
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 3e312ec8e62..7cdaf5afcee 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -161,7 +161,7 @@ machine-$(CONFIG_ARCH_PNX4008) := pnx4008
161machine-$(CONFIG_ARCH_PXA) := pxa 161machine-$(CONFIG_ARCH_PXA) := pxa
162machine-$(CONFIG_ARCH_REALVIEW) := realview 162machine-$(CONFIG_ARCH_REALVIEW) := realview
163machine-$(CONFIG_ARCH_RPC) := rpc 163machine-$(CONFIG_ARCH_RPC) := rpc
164machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2440 s3c2443 164machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2416 s3c2440 s3c2443
165machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0 165machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0
166machine-$(CONFIG_ARCH_S3C64XX) := s3c64xx 166machine-$(CONFIG_ARCH_S3C64XX) := s3c64xx
167machine-$(CONFIG_ARCH_S5P6440) := s5p6440 167machine-$(CONFIG_ARCH_S5P6440) := s5p6440
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig
index 554731868b0..9e5e96f12d8 100644
--- a/arch/arm/mach-s3c2410/Kconfig
+++ b/arch/arm/mach-s3c2410/Kconfig
@@ -6,6 +6,7 @@ config CPU_S3C2410
6 bool 6 bool
7 depends on ARCH_S3C2410 7 depends on ARCH_S3C2410
8 select CPU_ARM920T 8 select CPU_ARM920T
9 select S3C_GPIO_PULL_UP
9 select S3C2410_CLOCK 10 select S3C2410_CLOCK
10 select S3C2410_GPIO 11 select S3C2410_GPIO
11 select CPU_LLSERIAL_S3C2410 12 select CPU_LLSERIAL_S3C2410
diff --git a/arch/arm/mach-s3c2410/h1940-bluetooth.c b/arch/arm/mach-s3c2410/h1940-bluetooth.c
index a3f3c7b1ca3..8cdeb14af59 100644
--- a/arch/arm/mach-s3c2410/h1940-bluetooth.c
+++ b/arch/arm/mach-s3c2410/h1940-bluetooth.c
@@ -33,14 +33,15 @@ static void h1940bt_enable(int on)
33 h1940_latch_control(0, H1940_LATCH_BLUETOOTH_POWER); 33 h1940_latch_control(0, H1940_LATCH_BLUETOOTH_POWER);
34 /* Reset the chip */ 34 /* Reset the chip */
35 mdelay(10); 35 mdelay(10);
36 s3c2410_gpio_setpin(S3C2410_GPH(1), 1); 36
37 gpio_set_value(S3C2410_GPH(1), 1);
37 mdelay(10); 38 mdelay(10);
38 s3c2410_gpio_setpin(S3C2410_GPH(1), 0); 39 gpio_set_value(S3C2410_GPH(1), 0);
39 } 40 }
40 else { 41 else {
41 s3c2410_gpio_setpin(S3C2410_GPH(1), 1); 42 gpio_set_value(S3C2410_GPH(1), 1);
42 mdelay(10); 43 mdelay(10);
43 s3c2410_gpio_setpin(S3C2410_GPH(1), 0); 44 gpio_set_value(S3C2410_GPH(1), 0);
44 mdelay(10); 45 mdelay(10);
45 h1940_latch_control(H1940_LATCH_BLUETOOTH_POWER, 0); 46 h1940_latch_control(H1940_LATCH_BLUETOOTH_POWER, 0);
46 } 47 }
@@ -61,15 +62,21 @@ static int __devinit h1940bt_probe(struct platform_device *pdev)
61 struct rfkill *rfk; 62 struct rfkill *rfk;
62 int ret = 0; 63 int ret = 0;
63 64
65 ret = gpio_request(S3C2410_GPH(1), dev_name(&pdev->dev));
66 if (ret) {
67 dev_err(&pdev->dev, "could not get GPH1\n");\
68 return ret;
69 }
70
64 /* Configures BT serial port GPIOs */ 71 /* Configures BT serial port GPIOs */
65 s3c2410_gpio_cfgpin(S3C2410_GPH(0), S3C2410_GPH0_nCTS0); 72 s3c_gpio_cfgpin(S3C2410_GPH(0), S3C2410_GPH0_nCTS0);
66 s3c2410_gpio_pullup(S3C2410_GPH(0), 1); 73 s3c_gpio_cfgpull(S3C2410_GPH(0), S3C_GPIO_PULL_NONE);
67 s3c2410_gpio_cfgpin(S3C2410_GPH(1), S3C2410_GPIO_OUTPUT); 74 s3c_gpio_cfgpin(S3C2410_GPH(1), S3C2410_GPIO_OUTPUT);
68 s3c2410_gpio_pullup(S3C2410_GPH(1), 1); 75 s3c_gpio_cfgpull(S3C2410_GPH(1), S3C_GPIO_PULL_NONE);
69 s3c2410_gpio_cfgpin(S3C2410_GPH(2), S3C2410_GPH2_TXD0); 76 s3c_gpio_cfgpin(S3C2410_GPH(2), S3C2410_GPH2_TXD0);
70 s3c2410_gpio_pullup(S3C2410_GPH(2), 1); 77 s3c_gpio_cfgpull(S3C2410_GPH(2), S3C_GPIO_PULL_NONE);
71 s3c2410_gpio_cfgpin(S3C2410_GPH(3), S3C2410_GPH3_RXD0); 78 s3c_gpio_cfgpin(S3C2410_GPH(3), S3C2410_GPH3_RXD0);
72 s3c2410_gpio_pullup(S3C2410_GPH(3), 1); 79 s3c_gpio_cfgpull(S3C2410_GPH(3), S3C_GPIO_PULL_NONE);
73 80
74 81
75 rfk = rfkill_alloc(DRV_NAME, &pdev->dev, RFKILL_TYPE_BLUETOOTH, 82 rfk = rfkill_alloc(DRV_NAME, &pdev->dev, RFKILL_TYPE_BLUETOOTH,
@@ -100,6 +107,7 @@ static int h1940bt_remove(struct platform_device *pdev)
100 struct rfkill *rfk = platform_get_drvdata(pdev); 107 struct rfkill *rfk = platform_get_drvdata(pdev);
101 108
102 platform_set_drvdata(pdev, NULL); 109 platform_set_drvdata(pdev, NULL);
110 gpio_free(S3C2410_GPH(1));
103 111
104 if (rfk) { 112 if (rfk) {
105 rfkill_unregister(rfk); 113 rfkill_unregister(rfk);
diff --git a/arch/arm/mach-s3c2410/include/mach/dma.h b/arch/arm/mach-s3c2410/include/mach/dma.h
index 08ac5f96c01..cf68136cc66 100644
--- a/arch/arm/mach-s3c2410/include/mach/dma.h
+++ b/arch/arm/mach-s3c2410/include/mach/dma.h
@@ -54,7 +54,7 @@ enum dma_ch {
54#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */ 54#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
55 55
56/* we have 4 dma channels */ 56/* we have 4 dma channels */
57#ifndef CONFIG_CPU_S3C2443 57#if !defined(CONFIG_CPU_S3C2443) && !defined(CONFIG_CPU_S3C2416)
58#define S3C_DMA_CHANNELS (4) 58#define S3C_DMA_CHANNELS (4)
59#else 59#else
60#define S3C_DMA_CHANNELS (6) 60#define S3C_DMA_CHANNELS (6)
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h
index 035a493952d..f453c4f2cb8 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h
@@ -10,14 +10,28 @@
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11*/ 11*/
12 12
13#ifndef __MACH_GPIO_FNS_H
14#define __MACH_GPIO_FNS_H __FILE__
15
13/* These functions are in the to-be-removed category and it is strongly 16/* These functions are in the to-be-removed category and it is strongly
14 * encouraged not to use these in new code. They will be marked deprecated 17 * encouraged not to use these in new code. They will be marked deprecated
15 * very soon. 18 * very soon.
16 * 19 *
17 * Most of the functionality can be either replaced by the gpiocfg calls 20 * Most of the functionality can be either replaced by the gpiocfg calls
18 * for the s3c platform or by the generic GPIOlib API. 21 * for the s3c platform or by the generic GPIOlib API.
22 *
23 * As of 2.6.35-rc, these will be removed, with the few drivers using them
24 * either replaced or given a wrapper until the calls can be removed.
19*/ 25*/
20 26
27#include <plat/gpio-cfg.h>
28
29static inline void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int cfg)
30{
31 /* 1:1 mapping between cfgpin and setcfg calls at the moment */
32 s3c_gpio_cfgpin(pin, cfg);
33}
34
21/* external functions for GPIO support 35/* external functions for GPIO support
22 * 36 *
23 * These allow various different clients to access the same GPIO 37 * These allow various different clients to access the same GPIO
@@ -25,17 +39,6 @@
25 * GPIO register, then it is safe to ioremap/__raw_{read|write} to it. 39 * GPIO register, then it is safe to ioremap/__raw_{read|write} to it.
26*/ 40*/
27 41
28/* s3c2410_gpio_cfgpin
29 *
30 * set the configuration of the given pin to the value passed.
31 *
32 * eg:
33 * s3c2410_gpio_cfgpin(S3C2410_GPA(0), S3C2410_GPA0_ADDR0);
34 * s3c2410_gpio_cfgpin(S3C2410_GPE(8), S3C2410_GPE8_SDDAT1);
35*/
36
37extern void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function);
38
39extern unsigned int s3c2410_gpio_getcfg(unsigned int pin); 42extern unsigned int s3c2410_gpio_getcfg(unsigned int pin);
40 43
41/* s3c2410_gpio_getirq 44/* s3c2410_gpio_getirq
@@ -73,6 +76,14 @@ extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
73 76
74/* s3c2410_gpio_pullup 77/* s3c2410_gpio_pullup
75 * 78 *
79 * This call should be replaced with s3c_gpio_setpull().
80 *
81 * As a note, there is currently no distinction between pull-up and pull-down
82 * in the s3c24xx series devices with only an on/off configuration.
83 */
84
85/* s3c2410_gpio_pullup
86 *
76 * configure the pull-up control on the given pin 87 * configure the pull-up control on the given pin
77 * 88 *
78 * to = 1 => disable the pull-up 89 * to = 1 => disable the pull-up
@@ -86,18 +97,8 @@ extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
86 97
87extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to); 98extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to);
88 99
89/* s3c2410_gpio_getpull
90 *
91 * Read the state of the pull-up on a given pin
92 *
93 * return:
94 * < 0 => error code
95 * 0 => enabled
96 * 1 => disabled
97*/
98
99extern int s3c2410_gpio_getpull(unsigned int pin);
100
101extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to); 100extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to);
102 101
103extern unsigned int s3c2410_gpio_getpin(unsigned int pin); 102extern unsigned int s3c2410_gpio_getpin(unsigned int pin);
103
104#endif /* __MACH_GPIO_FNS_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
index 2edbb9c88ab..f3182ff847c 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
@@ -34,6 +34,10 @@
34#define S3C2410_GPIO_F_NR (32) 34#define S3C2410_GPIO_F_NR (32)
35#define S3C2410_GPIO_G_NR (32) 35#define S3C2410_GPIO_G_NR (32)
36#define S3C2410_GPIO_H_NR (32) 36#define S3C2410_GPIO_H_NR (32)
37#define S3C2410_GPIO_J_NR (32) /* technically 16. */
38#define S3C2410_GPIO_K_NR (32) /* technically 16. */
39#define S3C2410_GPIO_L_NR (32) /* technically 15. */
40#define S3C2410_GPIO_M_NR (32) /* technically 2. */
37 41
38#if CONFIG_S3C_GPIO_SPACE != 0 42#if CONFIG_S3C_GPIO_SPACE != 0
39#error CONFIG_S3C_GPIO_SPACE cannot be zero at the moment 43#error CONFIG_S3C_GPIO_SPACE cannot be zero at the moment
@@ -53,6 +57,10 @@ enum s3c_gpio_number {
53 S3C2410_GPIO_F_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_E), 57 S3C2410_GPIO_F_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_E),
54 S3C2410_GPIO_G_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_F), 58 S3C2410_GPIO_G_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_F),
55 S3C2410_GPIO_H_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_G), 59 S3C2410_GPIO_H_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_G),
60 S3C2410_GPIO_J_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_H),
61 S3C2410_GPIO_K_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_J),
62 S3C2410_GPIO_L_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_K),
63 S3C2410_GPIO_M_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_L),
56}; 64};
57 65
58#endif /* __ASSEMBLY__ */ 66#endif /* __ASSEMBLY__ */
@@ -67,6 +75,10 @@ enum s3c_gpio_number {
67#define S3C2410_GPF(_nr) (S3C2410_GPIO_F_START + (_nr)) 75#define S3C2410_GPF(_nr) (S3C2410_GPIO_F_START + (_nr))
68#define S3C2410_GPG(_nr) (S3C2410_GPIO_G_START + (_nr)) 76#define S3C2410_GPG(_nr) (S3C2410_GPIO_G_START + (_nr))
69#define S3C2410_GPH(_nr) (S3C2410_GPIO_H_START + (_nr)) 77#define S3C2410_GPH(_nr) (S3C2410_GPIO_H_START + (_nr))
78#define S3C2410_GPJ(_nr) (S3C2410_GPIO_J_START + (_nr))
79#define S3C2410_GPK(_nr) (S3C2410_GPIO_K_START + (_nr))
80#define S3C2410_GPL(_nr) (S3C2410_GPIO_L_START + (_nr))
81#define S3C2410_GPM(_nr) (S3C2410_GPIO_M_START + (_nr))
70 82
71/* compatibility until drivers can be modified */ 83/* compatibility until drivers can be modified */
72 84
diff --git a/arch/arm/mach-s3c2410/include/mach/irqs.h b/arch/arm/mach-s3c2410/include/mach/irqs.h
index 6c12c6312ad..877c15e1b15 100644
--- a/arch/arm/mach-s3c2410/include/mach/irqs.h
+++ b/arch/arm/mach-s3c2410/include/mach/irqs.h
@@ -115,6 +115,26 @@
115#define IRQ_S3C2412_SDI S3C2410_IRQSUB(13) 115#define IRQ_S3C2412_SDI S3C2410_IRQSUB(13)
116#define IRQ_S3C2412_CF S3C2410_IRQSUB(14) 116#define IRQ_S3C2412_CF S3C2410_IRQSUB(14)
117 117
118
119#define IRQ_S3C2416_EINT8t15 S3C2410_IRQ(5)
120#define IRQ_S3C2416_DMA S3C2410_IRQ(17)
121#define IRQ_S3C2416_UART3 S3C2410_IRQ(18)
122#define IRQ_S3C2416_SDI1 S3C2410_IRQ(20)
123#define IRQ_S3C2416_SDI0 S3C2410_IRQ(21)
124
125#define IRQ_S3C2416_LCD2 S3C2410_IRQSUB(15)
126#define IRQ_S3C2416_LCD3 S3C2410_IRQSUB(16)
127#define IRQ_S3C2416_LCD4 S3C2410_IRQSUB(17)
128#define IRQ_S3C2416_DMA0 S3C2410_IRQSUB(18)
129#define IRQ_S3C2416_DMA1 S3C2410_IRQSUB(19)
130#define IRQ_S3C2416_DMA2 S3C2410_IRQSUB(20)
131#define IRQ_S3C2416_DMA3 S3C2410_IRQSUB(21)
132#define IRQ_S3C2416_DMA4 S3C2410_IRQSUB(22)
133#define IRQ_S3C2416_DMA5 S3C2410_IRQSUB(23)
134#define IRQ_S32416_WDT S3C2410_IRQSUB(27)
135#define IRQ_S32416_AC97 S3C2410_IRQSUB(28)
136
137
118/* extra irqs for s3c2440 */ 138/* extra irqs for s3c2440 */
119 139
120#define IRQ_S3C2440_CAM_C S3C2410_IRQSUB(11) /* S3C2443 too */ 140#define IRQ_S3C2440_CAM_C S3C2410_IRQSUB(11) /* S3C2443 too */
@@ -130,7 +150,10 @@
130#define IRQ_S3C2443_HSMMC S3C2410_IRQ(20) /* IRQ_SDI */ 150#define IRQ_S3C2443_HSMMC S3C2410_IRQ(20) /* IRQ_SDI */
131#define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */ 151#define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */
132 152
153#define IRQ_S3C2416_HSMMC0 S3C2410_IRQ(21) /* S3C2416/S3C2450 */
154
133#define IRQ_HSMMC0 IRQ_S3C2443_HSMMC 155#define IRQ_HSMMC0 IRQ_S3C2443_HSMMC
156#define IRQ_HSMMC1 IRQ_S3C2416_HSMMC0
134 157
135#define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14) 158#define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14)
136#define IRQ_S3C2443_LCD2 S3C2410_IRQSUB(15) 159#define IRQ_S3C2443_LCD2 S3C2410_IRQSUB(15)
@@ -152,7 +175,7 @@
152#define IRQ_S3C2443_WDT S3C2410_IRQSUB(27) 175#define IRQ_S3C2443_WDT S3C2410_IRQSUB(27)
153#define IRQ_S3C2443_AC97 S3C2410_IRQSUB(28) 176#define IRQ_S3C2443_AC97 S3C2410_IRQSUB(28)
154 177
155#ifdef CONFIG_CPU_S3C2443 178#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
156#define NR_IRQS (IRQ_S3C2443_AC97+1) 179#define NR_IRQS (IRQ_S3C2443_AC97+1)
157#else 180#else
158#define NR_IRQS (IRQ_S3C2440_AC97+1) 181#define NR_IRQS (IRQ_S3C2440_AC97+1)
diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h
index b049e61460b..f07d68066d7 100644
--- a/arch/arm/mach-s3c2410/include/mach/map.h
+++ b/arch/arm/mach-s3c2410/include/mach/map.h
@@ -63,9 +63,9 @@
63#define S3C2440_PA_AC97 (0x5B000000) 63#define S3C2440_PA_AC97 (0x5B000000)
64#define S3C2440_SZ_AC97 SZ_1M 64#define S3C2440_SZ_AC97 SZ_1M
65 65
66/* S3C2443 High-speed SD/MMC */ 66/* S3C2443/S3C2416 High-speed SD/MMC */
67#define S3C2443_PA_HSMMC (0x4A800000) 67#define S3C2443_PA_HSMMC (0x4A800000)
68#define S3C2443_SZ_HSMMC (256) 68#define S3C2416_PA_HSMMC0 (0x4AC00000)
69 69
70/* S3C2412 memory and IO controls */ 70/* S3C2412 memory and IO controls */
71#define S3C2412_PA_SSMC (0x4F000000) 71#define S3C2412_PA_SSMC (0x4F000000)
@@ -110,6 +110,7 @@
110#define S3C_PA_UART S3C24XX_PA_UART 110#define S3C_PA_UART S3C24XX_PA_UART
111#define S3C_PA_USBHOST S3C2410_PA_USBHOST 111#define S3C_PA_USBHOST S3C2410_PA_USBHOST
112#define S3C_PA_HSMMC0 S3C2443_PA_HSMMC 112#define S3C_PA_HSMMC0 S3C2443_PA_HSMMC
113#define S3C_PA_HSMMC1 S3C2416_PA_HSMMC0
113#define S3C_PA_NAND S3C24XX_PA_NAND 114#define S3C_PA_NAND S3C24XX_PA_NAND
114 115
115#endif /* __ASM_ARCH_MAP_H */ 116#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-clock.h b/arch/arm/mach-s3c2410/include/mach/regs-clock.h
index 9a0d169be13..3415b60082d 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-clock.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-clock.h
@@ -161,4 +161,6 @@
161 161
162#endif /* CONFIG_CPU_S3C2412 | CONFIG_CPU_S3C2413 */ 162#endif /* CONFIG_CPU_S3C2412 | CONFIG_CPU_S3C2413 */
163 163
164#define S3C2416_CLKDIV2 S3C2410_CLKREG(0x28)
165
164#endif /* __ASM_ARM_REGS_CLOCK */ 166#endif /* __ASM_ARM_REGS_CLOCK */
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-dsc.h b/arch/arm/mach-s3c2410/include/mach/regs-dsc.h
index 3c3853cd3cf..98fd4a05587 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-dsc.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-dsc.h
@@ -19,6 +19,42 @@
19#define S3C2412_DSC1 S3C2410_GPIOREG(0xe0) 19#define S3C2412_DSC1 S3C2410_GPIOREG(0xe0)
20#endif 20#endif
21 21
22#if defined(CONFIG_CPU_S3C2416)
23#define S3C2416_DSC0 S3C2410_GPIOREG(0xc0)
24#define S3C2416_DSC1 S3C2410_GPIOREG(0xc4)
25#define S3C2416_DSC2 S3C2410_GPIOREG(0xc8)
26#define S3C2416_DSC3 S3C2410_GPIOREG(0x110)
27
28#define S3C2416_SELECT_DSC0 (0 << 30)
29#define S3C2416_SELECT_DSC1 (1 << 30)
30#define S3C2416_SELECT_DSC2 (2 << 30)
31#define S3C2416_SELECT_DSC3 (3 << 30)
32
33#define S3C2416_DSC_GETSHIFT(x) (x & 30)
34
35#define S3C2416_DSC0_CF (S3C2416_SELECT_DSC0 | 28)
36#define S3C2416_DSC0_CF_5mA (0 << 28)
37#define S3C2416_DSC0_CF_10mA (1 << 28)
38#define S3C2416_DSC0_CF_15mA (2 << 28)
39#define S3C2416_DSC0_CF_21mA (3 << 28)
40#define S3C2416_DSC0_CF_MASK (3 << 28)
41
42#define S3C2416_DSC0_nRBE (S3C2416_SELECT_DSC0 | 26)
43#define S3C2416_DSC0_nRBE_5mA (0 << 26)
44#define S3C2416_DSC0_nRBE_10mA (1 << 26)
45#define S3C2416_DSC0_nRBE_15mA (2 << 26)
46#define S3C2416_DSC0_nRBE_21mA (3 << 26)
47#define S3C2416_DSC0_nRBE_MASK (3 << 26)
48
49#define S3C2416_DSC0_nROE (S3C2416_SELECT_DSC0 | 24)
50#define S3C2416_DSC0_nROE_5mA (0 << 24)
51#define S3C2416_DSC0_nROE_10mA (1 << 24)
52#define S3C2416_DSC0_nROE_15mA (2 << 24)
53#define S3C2416_DSC0_nROE_21mA (3 << 24)
54#define S3C2416_DSC0_nROE_MASK (3 << 24)
55
56#endif
57
22#if defined(CONFIG_CPU_S3C244X) 58#if defined(CONFIG_CPU_S3C244X)
23 59
24#define S3C2440_DSC0 S3C2410_GPIOREG(0xc4) 60#define S3C2440_DSC0 S3C2410_GPIOREG(0xc4)
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
index fd672f330bf..a6384239edd 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
@@ -610,35 +610,73 @@
610#define S3C2410_GPHUP S3C2410_GPIOREG(0x78) 610#define S3C2410_GPHUP S3C2410_GPIOREG(0x78)
611 611
612#define S3C2410_GPH0_nCTS0 (0x02 << 0) 612#define S3C2410_GPH0_nCTS0 (0x02 << 0)
613#define S3C2416_GPH0_TXD0 (0x02 << 0)
613 614
614#define S3C2410_GPH1_nRTS0 (0x02 << 2) 615#define S3C2410_GPH1_nRTS0 (0x02 << 2)
616#define S3C2416_GPH1_RXD0 (0x02 << 2)
615 617
616#define S3C2410_GPH2_TXD0 (0x02 << 4) 618#define S3C2410_GPH2_TXD0 (0x02 << 4)
619#define S3C2416_GPH2_TXD1 (0x02 << 4)
617 620
618#define S3C2410_GPH3_RXD0 (0x02 << 6) 621#define S3C2410_GPH3_RXD0 (0x02 << 6)
622#define S3C2416_GPH3_RXD1 (0x02 << 6)
619 623
620#define S3C2410_GPH4_TXD1 (0x02 << 8) 624#define S3C2410_GPH4_TXD1 (0x02 << 8)
625#define S3C2416_GPH4_TXD2 (0x02 << 8)
621 626
622#define S3C2410_GPH5_RXD1 (0x02 << 10) 627#define S3C2410_GPH5_RXD1 (0x02 << 10)
628#define S3C2416_GPH5_RXD2 (0x02 << 10)
623 629
624#define S3C2410_GPH6_TXD2 (0x02 << 12) 630#define S3C2410_GPH6_TXD2 (0x02 << 12)
631#define S3C2416_GPH6_TXD3 (0x02 << 12)
625#define S3C2410_GPH6_nRTS1 (0x03 << 12) 632#define S3C2410_GPH6_nRTS1 (0x03 << 12)
633#define S3C2416_GPH6_nRTS2 (0x03 << 12)
626 634
627#define S3C2410_GPH7_RXD2 (0x02 << 14) 635#define S3C2410_GPH7_RXD2 (0x02 << 14)
636#define S3C2416_GPH7_RXD3 (0x02 << 14)
628#define S3C2410_GPH7_nCTS1 (0x03 << 14) 637#define S3C2410_GPH7_nCTS1 (0x03 << 14)
638#define S3C2416_GPH7_nCTS2 (0x03 << 14)
629 639
630#define S3C2410_GPH8_UCLK (0x02 << 16) 640#define S3C2410_GPH8_UCLK (0x02 << 16)
641#define S3C2416_GPH8_nCTS0 (0x02 << 16)
631 642
632#define S3C2410_GPH9_CLKOUT0 (0x02 << 18) 643#define S3C2410_GPH9_CLKOUT0 (0x02 << 18)
633#define S3C2442_GPH9_nSPICS0 (0x03 << 18) 644#define S3C2442_GPH9_nSPICS0 (0x03 << 18)
645#define S3C2416_GPH9_nRTS0 (0x02 << 18)
634 646
635#define S3C2410_GPH10_CLKOUT1 (0x02 << 20) 647#define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
648#define S3C2416_GPH10_nCTS1 (0x02 << 20)
649
650#define S3C2416_GPH11_nRTS1 (0x02 << 22)
651
652#define S3C2416_GPH12_EXTUARTCLK (0x02 << 24)
653
654#define S3C2416_GPH13_CLKOUT0 (0x02 << 26)
655
656#define S3C2416_GPH14_CLKOUT1 (0x02 << 28)
636 657
637/* The S3C2412 and S3C2413 move the GPJ register set to after 658/* The S3C2412 and S3C2413 move the GPJ register set to after
638 * GPH, which means all registers after 0x80 are now offset by 0x10 659 * GPH, which means all registers after 0x80 are now offset by 0x10
639 * for the 2412/2413 from the 2410/2440/2442 660 * for the 2412/2413 from the 2410/2440/2442
640*/ 661*/
641 662
663/* S3C2443 and above */
664#define S3C2440_GPJCON S3C2410_GPIOREG(0xD0)
665#define S3C2440_GPJDAT S3C2410_GPIOREG(0xD4)
666#define S3C2440_GPJUP S3C2410_GPIOREG(0xD8)
667
668#define S3C2443_GPKCON S3C2410_GPIOREG(0xE0)
669#define S3C2443_GPKDAT S3C2410_GPIOREG(0xE4)
670#define S3C2443_GPKUP S3C2410_GPIOREG(0xE8)
671
672#define S3C2443_GPLCON S3C2410_GPIOREG(0xF0)
673#define S3C2443_GPLDAT S3C2410_GPIOREG(0xF4)
674#define S3C2443_GPLUP S3C2410_GPIOREG(0xF8)
675
676#define S3C2443_GPMCON S3C2410_GPIOREG(0x100)
677#define S3C2443_GPMDAT S3C2410_GPIOREG(0x104)
678#define S3C2443_GPMUP S3C2410_GPIOREG(0x108)
679
642/* miscellaneous control */ 680/* miscellaneous control */
643#define S3C2400_MISCCR S3C2410_GPIOREG(0x54) 681#define S3C2400_MISCCR S3C2410_GPIOREG(0x54)
644#define S3C2410_MISCCR S3C2410_GPIOREG(0x80) 682#define S3C2410_MISCCR S3C2410_GPIOREG(0x80)
@@ -686,6 +724,7 @@
686#define S3C2412_MISCCR_CLK1_CLKsrc (0<<8) 724#define S3C2412_MISCCR_CLK1_CLKsrc (0<<8)
687 725
688#define S3C2410_MISCCR_USBSUSPND0 (1<<12) 726#define S3C2410_MISCCR_USBSUSPND0 (1<<12)
727#define S3C2416_MISCCR_SEL_SUSPND (1<<12)
689#define S3C2410_MISCCR_USBSUSPND1 (1<<13) 728#define S3C2410_MISCCR_USBSUSPND1 (1<<13)
690 729
691#define S3C2410_MISCCR_nRSTCON (1<<16) 730#define S3C2410_MISCCR_nRSTCON (1<<16)
@@ -695,6 +734,9 @@
695#define S3C2410_MISCCR_nEN_SCLKE (1<<19) /* not 2412 */ 734#define S3C2410_MISCCR_nEN_SCLKE (1<<19) /* not 2412 */
696#define S3C2410_MISCCR_SDSLEEP (7<<17) 735#define S3C2410_MISCCR_SDSLEEP (7<<17)
697 736
737#define S3C2416_MISCCR_FLT_I2C (1<<24)
738#define S3C2416_MISCCR_HSSPI_EN2 (1<<31)
739
698/* external interrupt control... */ 740/* external interrupt control... */
699/* S3C2410_EXTINT0 -> irq sense control for EINT0..EINT7 741/* S3C2410_EXTINT0 -> irq sense control for EINT0..EINT7
700 * S3C2410_EXTINT1 -> irq sense control for EINT8..EINT15 742 * S3C2410_EXTINT1 -> irq sense control for EINT8..EINT15
@@ -762,8 +804,11 @@
762#define S3C2410_GSTATUS1_IDMASK (0xffff0000) 804#define S3C2410_GSTATUS1_IDMASK (0xffff0000)
763#define S3C2410_GSTATUS1_2410 (0x32410000) 805#define S3C2410_GSTATUS1_2410 (0x32410000)
764#define S3C2410_GSTATUS1_2412 (0x32412001) 806#define S3C2410_GSTATUS1_2412 (0x32412001)
807#define S3C2410_GSTATUS1_2416 (0x32416003)
765#define S3C2410_GSTATUS1_2440 (0x32440000) 808#define S3C2410_GSTATUS1_2440 (0x32440000)
766#define S3C2410_GSTATUS1_2442 (0x32440aaa) 809#define S3C2410_GSTATUS1_2442 (0x32440aaa)
810/* some 2416 CPUs report this value also */
811#define S3C2410_GSTATUS1_2450 (0x32450003)
767 812
768#define S3C2410_GSTATUS2_WTRESET (1<<2) 813#define S3C2410_GSTATUS2_WTRESET (1<<2)
769#define S3C2410_GSTATUS2_OFFRESET (1<<1) 814#define S3C2410_GSTATUS2_OFFRESET (1<<1)
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpioj.h b/arch/arm/mach-s3c2410/include/mach/regs-gpioj.h
index 1202ca5e99f..19575e06111 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-gpioj.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-gpioj.h
@@ -22,85 +22,49 @@
22 * pull up works like all other ports. 22 * pull up works like all other ports.
23*/ 23*/
24 24
25#define S3C2440_GPIO_BANKJ (416)
26
27#define S3C2440_GPJCON S3C2410_GPIOREG(0xd0)
28#define S3C2440_GPJDAT S3C2410_GPIOREG(0xd4)
29#define S3C2440_GPJUP S3C2410_GPIOREG(0xd8)
30
31#define S3C2413_GPJCON S3C2410_GPIOREG(0x80) 25#define S3C2413_GPJCON S3C2410_GPIOREG(0x80)
32#define S3C2413_GPJDAT S3C2410_GPIOREG(0x84) 26#define S3C2413_GPJDAT S3C2410_GPIOREG(0x84)
33#define S3C2413_GPJUP S3C2410_GPIOREG(0x88) 27#define S3C2413_GPJUP S3C2410_GPIOREG(0x88)
34#define S3C2413_GPJSLPCON S3C2410_GPIOREG(0x8C) 28#define S3C2413_GPJSLPCON S3C2410_GPIOREG(0x8C)
35 29
36#define S3C2440_GPJ0 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 0)
37#define S3C2440_GPJ0_INP (0x00 << 0)
38#define S3C2440_GPJ0_OUTP (0x01 << 0) 30#define S3C2440_GPJ0_OUTP (0x01 << 0)
39#define S3C2440_GPJ0_CAMDATA0 (0x02 << 0) 31#define S3C2440_GPJ0_CAMDATA0 (0x02 << 0)
40 32
41#define S3C2440_GPJ1 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 1)
42#define S3C2440_GPJ1_INP (0x00 << 2)
43#define S3C2440_GPJ1_OUTP (0x01 << 2) 33#define S3C2440_GPJ1_OUTP (0x01 << 2)
44#define S3C2440_GPJ1_CAMDATA1 (0x02 << 2) 34#define S3C2440_GPJ1_CAMDATA1 (0x02 << 2)
45 35
46#define S3C2440_GPJ2 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 2)
47#define S3C2440_GPJ2_INP (0x00 << 4)
48#define S3C2440_GPJ2_OUTP (0x01 << 4) 36#define S3C2440_GPJ2_OUTP (0x01 << 4)
49#define S3C2440_GPJ2_CAMDATA2 (0x02 << 4) 37#define S3C2440_GPJ2_CAMDATA2 (0x02 << 4)
50 38
51#define S3C2440_GPJ3 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 3)
52#define S3C2440_GPJ3_INP (0x00 << 6)
53#define S3C2440_GPJ3_OUTP (0x01 << 6) 39#define S3C2440_GPJ3_OUTP (0x01 << 6)
54#define S3C2440_GPJ3_CAMDATA3 (0x02 << 6) 40#define S3C2440_GPJ3_CAMDATA3 (0x02 << 6)
55 41
56#define S3C2440_GPJ4 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 4)
57#define S3C2440_GPJ4_INP (0x00 << 8)
58#define S3C2440_GPJ4_OUTP (0x01 << 8) 42#define S3C2440_GPJ4_OUTP (0x01 << 8)
59#define S3C2440_GPJ4_CAMDATA4 (0x02 << 8) 43#define S3C2440_GPJ4_CAMDATA4 (0x02 << 8)
60 44
61#define S3C2440_GPJ5 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 5)
62#define S3C2440_GPJ5_INP (0x00 << 10)
63#define S3C2440_GPJ5_OUTP (0x01 << 10) 45#define S3C2440_GPJ5_OUTP (0x01 << 10)
64#define S3C2440_GPJ5_CAMDATA5 (0x02 << 10) 46#define S3C2440_GPJ5_CAMDATA5 (0x02 << 10)
65 47
66#define S3C2440_GPJ6 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 6)
67#define S3C2440_GPJ6_INP (0x00 << 12)
68#define S3C2440_GPJ6_OUTP (0x01 << 12) 48#define S3C2440_GPJ6_OUTP (0x01 << 12)
69#define S3C2440_GPJ6_CAMDATA6 (0x02 << 12) 49#define S3C2440_GPJ6_CAMDATA6 (0x02 << 12)
70 50
71#define S3C2440_GPJ7 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 7)
72#define S3C2440_GPJ7_INP (0x00 << 14)
73#define S3C2440_GPJ7_OUTP (0x01 << 14) 51#define S3C2440_GPJ7_OUTP (0x01 << 14)
74#define S3C2440_GPJ7_CAMDATA7 (0x02 << 14) 52#define S3C2440_GPJ7_CAMDATA7 (0x02 << 14)
75 53
76#define S3C2440_GPJ8 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 8)
77#define S3C2440_GPJ8_INP (0x00 << 16)
78#define S3C2440_GPJ8_OUTP (0x01 << 16) 54#define S3C2440_GPJ8_OUTP (0x01 << 16)
79#define S3C2440_GPJ8_CAMPCLK (0x02 << 16) 55#define S3C2440_GPJ8_CAMPCLK (0x02 << 16)
80 56
81#define S3C2440_GPJ9 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 9)
82#define S3C2440_GPJ9_INP (0x00 << 18)
83#define S3C2440_GPJ9_OUTP (0x01 << 18) 57#define S3C2440_GPJ9_OUTP (0x01 << 18)
84#define S3C2440_GPJ9_CAMVSYNC (0x02 << 18) 58#define S3C2440_GPJ9_CAMVSYNC (0x02 << 18)
85 59
86#define S3C2440_GPJ10 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 10)
87#define S3C2440_GPJ10_INP (0x00 << 20)
88#define S3C2440_GPJ10_OUTP (0x01 << 20) 60#define S3C2440_GPJ10_OUTP (0x01 << 20)
89#define S3C2440_GPJ10_CAMHREF (0x02 << 20) 61#define S3C2440_GPJ10_CAMHREF (0x02 << 20)
90 62
91#define S3C2440_GPJ11 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 11)
92#define S3C2440_GPJ11_INP (0x00 << 22)
93#define S3C2440_GPJ11_OUTP (0x01 << 22) 63#define S3C2440_GPJ11_OUTP (0x01 << 22)
94#define S3C2440_GPJ11_CAMCLKOUT (0x02 << 22) 64#define S3C2440_GPJ11_CAMCLKOUT (0x02 << 22)
95 65
96#define S3C2440_GPJ12 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 12)
97#define S3C2440_GPJ12_INP (0x00 << 24)
98#define S3C2440_GPJ12_OUTP (0x01 << 24) 66#define S3C2440_GPJ12_OUTP (0x01 << 24)
99#define S3C2440_GPJ12_CAMRESET (0x02 << 24) 67#define S3C2440_GPJ12_CAMRESET (0x02 << 24)
100 68
101#define S3C2443_GPJ13 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 13)
102#define S3C2443_GPJ14 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 14)
103#define S3C2443_GPJ15 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 15)
104
105#endif /* __ASM_ARCH_REGS_GPIOJ_H */ 69#endif /* __ASM_ARCH_REGS_GPIOJ_H */
106 70
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-irq.h b/arch/arm/mach-s3c2410/include/mach/regs-irq.h
index de86ee8812b..0f07ba30b1f 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-irq.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-irq.h
@@ -27,6 +27,16 @@
27#define S3C2410_SUBSRCPND S3C2410_IRQREG(0x018) 27#define S3C2410_SUBSRCPND S3C2410_IRQREG(0x018)
28#define S3C2410_INTSUBMSK S3C2410_IRQREG(0x01C) 28#define S3C2410_INTSUBMSK S3C2410_IRQREG(0x01C)
29 29
30#define S3C2416_PRIORITY_MODE1 S3C2410_IRQREG(0x030)
31#define S3C2416_PRIORITY_UPDATE1 S3C2410_IRQREG(0x034)
32#define S3C2416_SRCPND2 S3C2410_IRQREG(0x040)
33#define S3C2416_INTMOD2 S3C2410_IRQREG(0x044)
34#define S3C2416_INTMSK2 S3C2410_IRQREG(0x048)
35#define S3C2416_INTPND2 S3C2410_IRQREG(0x050)
36#define S3C2416_INTOFFSET2 S3C2410_IRQREG(0x054)
37#define S3C2416_PRIORITY_MODE2 S3C2410_IRQREG(0x070)
38#define S3C2416_PRIORITY_UPDATE2 S3C2410_IRQREG(0x074)
39
30/* mask: 0=enable, 1=disable 40/* mask: 0=enable, 1=disable
31 * 1 bit EINT, 4=EINT4, 23=EINT23 41 * 1 bit EINT, 4=EINT4, 23=EINT23
32 * EINT0,1,2,3 are not handled here. 42 * EINT0,1,2,3 are not handled here.
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h
new file mode 100644
index 00000000000..2f31b74974a
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h
@@ -0,0 +1,30 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h
2 *
3 * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
4 * as part of OpenInkpot project
5 * Copyright (c) 2009 Promwad Innovation Company
6 * Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * S3C2416 memory register definitions
13*/
14
15#ifndef __ASM_ARM_REGS_S3C2416_MEM
16#define __ASM_ARM_REGS_S3C2416_MEM
17
18#ifndef S3C2416_MEMREG
19#define S3C2416_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
20#endif
21
22#define S3C2416_BANKCFG S3C2416_MEMREG(0x00)
23#define S3C2416_BANKCON1 S3C2416_MEMREG(0x04)
24#define S3C2416_BANKCON2 S3C2416_MEMREG(0x08)
25#define S3C2416_BANKCON3 S3C2416_MEMREG(0x0C)
26
27#define S3C2416_REFRESH S3C2416_MEMREG(0x10)
28#define S3C2416_TIMEOUT S3C2416_MEMREG(0x14)
29
30#endif /* __ASM_ARM_REGS_S3C2416_MEM */
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h
new file mode 100644
index 00000000000..e443167efb8
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h
@@ -0,0 +1,24 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h
2 *
3 * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
4 * as part of OpenInkpot project
5 * Copyright (c) 2009 Promwad Innovation Company
6 * Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * S3C2416 specific register definitions
13*/
14
15#ifndef __ASM_ARCH_REGS_S3C2416_H
16#define __ASM_ARCH_REGS_S3C2416_H "s3c2416"
17
18#define S3C2416_SWRST (S3C24XX_VA_CLKPWR + 0x44)
19#define S3C2416_SWRST_RESET (0x533C2416)
20
21/* see regs-power.h for the other registers in the power block. */
22
23#endif /* __ASM_ARCH_REGS_S3C2416_H */
24
diff --git a/arch/arm/mach-s3c2410/include/mach/uncompress.h b/arch/arm/mach-s3c2410/include/mach/uncompress.h
index 72f756c5e50..8b283f847da 100644
--- a/arch/arm/mach-s3c2410/include/mach/uncompress.h
+++ b/arch/arm/mach-s3c2410/include/mach/uncompress.h
@@ -40,7 +40,9 @@ static void arch_detect_cpu(void)
40 cpuid &= S3C2410_GSTATUS1_IDMASK; 40 cpuid &= S3C2410_GSTATUS1_IDMASK;
41 41
42 if (is_arm926() || cpuid == S3C2410_GSTATUS1_2440 || 42 if (is_arm926() || cpuid == S3C2410_GSTATUS1_2440 ||
43 cpuid == S3C2410_GSTATUS1_2442) { 43 cpuid == S3C2410_GSTATUS1_2442 ||
44 cpuid == S3C2410_GSTATUS1_2416 ||
45 cpuid == S3C2410_GSTATUS1_2450) {
44 fifo_mask = S3C2440_UFSTAT_TXMASK; 46 fifo_mask = S3C2440_UFSTAT_TXMASK;
45 fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT; 47 fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
46 } else { 48 } else {
diff --git a/arch/arm/mach-s3c2410/mach-amlm5900.c b/arch/arm/mach-s3c2410/mach-amlm5900.c
index 7047317ed7f..34fc05a4244 100644
--- a/arch/arm/mach-s3c2410/mach-amlm5900.c
+++ b/arch/arm/mach-s3c2410/mach-amlm5900.c
@@ -56,6 +56,7 @@
56#include <plat/iic.h> 56#include <plat/iic.h>
57#include <plat/devs.h> 57#include <plat/devs.h>
58#include <plat/cpu.h> 58#include <plat/cpu.h>
59#include <plat/gpio-cfg.h>
59 60
60#ifdef CONFIG_MTD_PARTITIONS 61#ifdef CONFIG_MTD_PARTITIONS
61 62
@@ -225,8 +226,8 @@ static void amlm5900_init_pm(void)
225 } else { 226 } else {
226 enable_irq_wake(IRQ_EINT9); 227 enable_irq_wake(IRQ_EINT9);
227 /* configure the suspend/resume status pin */ 228 /* configure the suspend/resume status pin */
228 s3c2410_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT); 229 s3c_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT);
229 s3c2410_gpio_pullup(S3C2410_GPF(2), 0); 230 s3c_gpio_setpull(S3C2410_GPF(2), S3C_GPIO_PULL_UP);
230 } 231 }
231} 232}
232static void __init amlm5900_init(void) 233static void __init amlm5900_init(void)
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index 02b1b6220cb..b061ddcf306 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -61,6 +61,7 @@
61#include <plat/devs.h> 61#include <plat/devs.h>
62#include <plat/cpu.h> 62#include <plat/cpu.h>
63#include <plat/cpu-freq.h> 63#include <plat/cpu-freq.h>
64#include <plat/gpio-cfg.h>
64#include <plat/audio-simtec.h> 65#include <plat/audio-simtec.h>
65 66
66#include "usb-simtec.h" 67#include "usb-simtec.h"
@@ -216,15 +217,13 @@ static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
216static int bast_pm_suspend(struct sys_device *sd, pm_message_t state) 217static int bast_pm_suspend(struct sys_device *sd, pm_message_t state)
217{ 218{
218 /* ensure that an nRESET is not generated on resume. */ 219 /* ensure that an nRESET is not generated on resume. */
219 s3c2410_gpio_setpin(S3C2410_GPA(21), 1); 220 gpio_direction_output(S3C2410_GPA(21), 1);
220 s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);
221
222 return 0; 221 return 0;
223} 222}
224 223
225static int bast_pm_resume(struct sys_device *sd) 224static int bast_pm_resume(struct sys_device *sd)
226{ 225{
227 s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT); 226 s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
228 return 0; 227 return 0;
229} 228}
230 229
@@ -658,6 +657,8 @@ static void __init bast_init(void)
658 nor_simtec_init(); 657 nor_simtec_init();
659 simtec_audio_add(NULL, true, &bast_audio); 658 simtec_audio_add(NULL, true, &bast_audio);
660 659
660 WARN_ON(gpio_request(S3C2410_GPA(21), "bast nreset"));
661
661 s3c_cpufreq_setboard(&bast_cpufreq); 662 s3c_cpufreq_setboard(&bast_cpufreq);
662} 663}
663 664
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index fbedd076094..9531b4c41de 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -50,6 +50,7 @@
50#include <plat/udc.h> 50#include <plat/udc.h>
51#include <plat/iic.h> 51#include <plat/iic.h>
52 52
53#include <plat/gpio-cfg.h>
53#include <plat/clock.h> 54#include <plat/clock.h>
54#include <plat/devs.h> 55#include <plat/devs.h>
55#include <plat/cpu.h> 56#include <plat/cpu.h>
@@ -207,16 +208,16 @@ static int h1940_backlight_init(struct device *dev)
207{ 208{
208 gpio_request(S3C2410_GPB(0), "Backlight"); 209 gpio_request(S3C2410_GPB(0), "Backlight");
209 210
210 s3c2410_gpio_setpin(S3C2410_GPB(0), 0); 211 gpio_direction_output(S3C2410_GPB(0), 0);
211 s3c2410_gpio_pullup(S3C2410_GPB(0), 0); 212 s3c_gpio_setpull(S3C2410_GPB(0), S3C_GPIO_PULL_NONE);
212 s3c2410_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPB0_TOUT0); 213 s3c_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPB0_TOUT0);
213 214
214 return 0; 215 return 0;
215} 216}
216 217
217static void h1940_backlight_exit(struct device *dev) 218static void h1940_backlight_exit(struct device *dev)
218{ 219{
219 s3c2410_gpio_cfgpin(S3C2410_GPB(0), 1/*S3C2410_GPB0_OUTP*/); 220 gpio_direction_output(S3C2410_GPB(0), 1);
220} 221}
221 222
222static struct platform_pwm_backlight_data backlight_data = { 223static struct platform_pwm_backlight_data backlight_data = {
@@ -245,18 +246,18 @@ static void h1940_lcd_power_set(struct plat_lcd_data *pd,
245 246
246 if (!power) { 247 if (!power) {
247 /* set to 3ec */ 248 /* set to 3ec */
248 s3c2410_gpio_setpin(S3C2410_GPC(0), 0); 249 gpio_direction_output(S3C2410_GPC(0), 0);
249 /* wait for 3ac */ 250 /* wait for 3ac */
250 do { 251 do {
251 value = s3c2410_gpio_getpin(S3C2410_GPC(6)); 252 value = gpio_get_value(S3C2410_GPC(6));
252 } while (value); 253 } while (value);
253 /* set to 38c */ 254 /* set to 38c */
254 s3c2410_gpio_setpin(S3C2410_GPC(5), 0); 255 gpio_direction_output(S3C2410_GPC(5), 0);
255 } else { 256 } else {
256 /* Set to 3ac */ 257 /* Set to 3ac */
257 s3c2410_gpio_setpin(S3C2410_GPC(5), 1); 258 gpio_direction_output(S3C2410_GPC(5), 1);
258 /* Set to 3ad */ 259 /* Set to 3ad */
259 s3c2410_gpio_setpin(S3C2410_GPC(0), 1); 260 gpio_direction_output(S3C2410_GPC(0), 1);
260 } 261 }
261} 262}
262 263
@@ -332,6 +333,7 @@ static void __init h1940_init(void)
332 gpio_request(S3C2410_GPC(5), "LCD power"); 333 gpio_request(S3C2410_GPC(5), "LCD power");
333 gpio_request(S3C2410_GPC(6), "LCD power"); 334 gpio_request(S3C2410_GPC(6), "LCD power");
334 335
336 gpio_direction_input(S3C2410_GPC(6));
335 337
336 platform_add_devices(h1940_devices, ARRAY_SIZE(h1940_devices)); 338 platform_add_devices(h1940_devices, ARRAY_SIZE(h1940_devices));
337} 339}
diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c
index 684710f8814..75a9fd37a46 100644
--- a/arch/arm/mach-s3c2410/mach-n30.c
+++ b/arch/arm/mach-s3c2410/mach-n30.c
@@ -86,10 +86,10 @@ static void n30_udc_pullup(enum s3c2410_udc_cmd_e cmd)
86{ 86{
87 switch (cmd) { 87 switch (cmd) {
88 case S3C2410_UDC_P_ENABLE : 88 case S3C2410_UDC_P_ENABLE :
89 s3c2410_gpio_setpin(S3C2410_GPB(3), 1); 89 gpio_set_value(S3C2410_GPB(3), 1);
90 break; 90 break;
91 case S3C2410_UDC_P_DISABLE : 91 case S3C2410_UDC_P_DISABLE :
92 s3c2410_gpio_setpin(S3C2410_GPB(3), 0); 92 gpio_set_value(S3C2410_GPB(3), 0);
93 break; 93 break;
94 case S3C2410_UDC_P_RESET : 94 case S3C2410_UDC_P_RESET :
95 break; 95 break;
@@ -536,6 +536,9 @@ static void __init n30_init(void)
536 536
537 platform_add_devices(n35_devices, ARRAY_SIZE(n35_devices)); 537 platform_add_devices(n35_devices, ARRAY_SIZE(n35_devices));
538 } 538 }
539
540 WARN_ON(gpio_request(S3C2410_GPB(3), "udc pup"));
541 gpio_direction_output(S3C2410_GPB(3), 0);
539} 542}
540 543
541MACHINE_START(N30, "Acer-N30") 544MACHINE_START(N30, "Acer-N30")
diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c
index 92a4ec375d8..d0e87b6e2e0 100644
--- a/arch/arm/mach-s3c2410/mach-qt2410.c
+++ b/arch/arm/mach-s3c2410/mach-qt2410.c
@@ -58,6 +58,7 @@
58#include <plat/iic.h> 58#include <plat/iic.h>
59 59
60#include <plat/common-smdk.h> 60#include <plat/common-smdk.h>
61#include <plat/gpio-cfg.h>
61#include <plat/devs.h> 62#include <plat/devs.h>
62#include <plat/cpu.h> 63#include <plat/cpu.h>
63#include <plat/pm.h> 64#include <plat/pm.h>
@@ -219,10 +220,10 @@ static void spi_gpio_cs(struct s3c2410_spigpio_info *spi, int cs)
219{ 220{
220 switch (cs) { 221 switch (cs) {
221 case BITBANG_CS_ACTIVE: 222 case BITBANG_CS_ACTIVE:
222 s3c2410_gpio_setpin(S3C2410_GPB(5), 0); 223 gpio_set_value(S3C2410_GPB(5), 0);
223 break; 224 break;
224 case BITBANG_CS_INACTIVE: 225 case BITBANG_CS_INACTIVE:
225 s3c2410_gpio_setpin(S3C2410_GPB(5), 1); 226 gpio_set_value(S3C2410_GPB(5), 1);
226 break; 227 break;
227 } 228 }
228} 229}
@@ -347,13 +348,14 @@ static void __init qt2410_machine_init(void)
347 } 348 }
348 s3c24xx_fb_set_platdata(&qt2410_fb_info); 349 s3c24xx_fb_set_platdata(&qt2410_fb_info);
349 350
350 s3c2410_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPIO_OUTPUT); 351 s3c_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPIO_OUTPUT);
351 s3c2410_gpio_setpin(S3C2410_GPB(0), 1); 352 s3c2410_gpio_setpin(S3C2410_GPB(0), 1);
352 353
353 s3c24xx_udc_set_platdata(&qt2410_udc_cfg); 354 s3c24xx_udc_set_platdata(&qt2410_udc_cfg);
354 s3c_i2c0_set_platdata(NULL); 355 s3c_i2c0_set_platdata(NULL);
355 356
356 s3c2410_gpio_cfgpin(S3C2410_GPB(5), S3C2410_GPIO_OUTPUT); 357 WARN_ON(gpio_request(S3C2410_GPB(5), "spi cs"));
358 gpio_direction_output(S3C2410_GPB(5), 1);
357 359
358 platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices)); 360 platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices));
359 s3c_pm_init(); 361 s3c_pm_init();
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c
index 9051f0d3112..d540d79dd26 100644
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c2410/mach-vr1000.c
@@ -357,8 +357,7 @@ static struct clk *vr1000_clocks[] __initdata = {
357 357
358static void vr1000_power_off(void) 358static void vr1000_power_off(void)
359{ 359{
360 s3c2410_gpio_cfgpin(S3C2410_GPB(9), S3C2410_GPIO_OUTPUT); 360 gpio_direction_output(S3C2410_GPB(9), 1);
361 s3c2410_gpio_setpin(S3C2410_GPB(9), 1);
362} 361}
363 362
364static void __init vr1000_map_io(void) 363static void __init vr1000_map_io(void)
@@ -395,6 +394,8 @@ static void __init vr1000_init(void)
395 394
396 nor_simtec_init(); 395 nor_simtec_init();
397 simtec_audio_add(NULL, true, NULL); 396 simtec_audio_add(NULL, true, NULL);
397
398 WARN_ON(gpio_request(S3C2410_GPB(9), "power off"));
398} 399}
399 400
400MACHINE_START(VR1000, "Thorcom-VR1000") 401MACHINE_START(VR1000, "Thorcom-VR1000")
diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c
index 91ba42f688a..adc90a3c589 100644
--- a/arch/arm/mach-s3c2410/s3c2410.c
+++ b/arch/arm/mach-s3c2410/s3c2410.c
@@ -16,6 +16,7 @@
16#include <linux/list.h> 16#include <linux/list.h>
17#include <linux/timer.h> 17#include <linux/timer.h>
18#include <linux/init.h> 18#include <linux/init.h>
19#include <linux/gpio.h>
19#include <linux/clk.h> 20#include <linux/clk.h>
20#include <linux/sysdev.h> 21#include <linux/sysdev.h>
21#include <linux/serial_core.h> 22#include <linux/serial_core.h>
@@ -40,6 +41,10 @@
40#include <plat/clock.h> 41#include <plat/clock.h>
41#include <plat/pll.h> 42#include <plat/pll.h>
42 43
44#include <plat/gpio-core.h>
45#include <plat/gpio-cfg.h>
46#include <plat/gpio-cfg-helpers.h>
47
43/* Initial IO mappings */ 48/* Initial IO mappings */
44 49
45static struct map_desc s3c2410_iodesc[] __initdata = { 50static struct map_desc s3c2410_iodesc[] __initdata = {
@@ -65,6 +70,9 @@ void __init s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no)
65 70
66void __init s3c2410_map_io(void) 71void __init s3c2410_map_io(void)
67{ 72{
73 s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_1up;
74 s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_1up;
75
68 iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc)); 76 iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc));
69} 77}
70 78
diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig
index 9a8c0657ae5..cef6a65637b 100644
--- a/arch/arm/mach-s3c2412/Kconfig
+++ b/arch/arm/mach-s3c2412/Kconfig
@@ -16,7 +16,8 @@ config CPU_S3C2412
16config CPU_S3C2412_ONLY 16config CPU_S3C2412_ONLY
17 bool 17 bool
18 depends on ARCH_S3C2410 && !CPU_S3C2400 && !CPU_S3C2410 && \ 18 depends on ARCH_S3C2410 && !CPU_S3C2400 && !CPU_S3C2410 && \
19 !CPU_S3C2440 && !CPU_S3C2442 && !CPU_S3C2443 && CPU_S3C2412 19 !CPU_2416 && !CPU_S3C2440 && !CPU_S3C2442 && \
20 !CPU_S3C2443 && CPU_S3C2412
20 default y if CPU_S3C2412 21 default y if CPU_S3C2412
21 22
22config S3C2412_DMA 23config S3C2412_DMA
diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c
index 14f4798291a..43160183571 100644
--- a/arch/arm/mach-s3c2412/mach-jive.c
+++ b/arch/arm/mach-s3c2412/mach-jive.c
@@ -48,6 +48,7 @@
48#include <linux/mtd/nand_ecc.h> 48#include <linux/mtd/nand_ecc.h>
49#include <linux/mtd/partitions.h> 49#include <linux/mtd/partitions.h>
50 50
51#include <plat/gpio-cfg.h>
51#include <plat/clock.h> 52#include <plat/clock.h>
52#include <plat/devs.h> 53#include <plat/devs.h>
53#include <plat/cpu.h> 54#include <plat/cpu.h>
@@ -357,8 +358,7 @@ static void jive_lcm_reset(unsigned int set)
357{ 358{
358 printk(KERN_DEBUG "%s(%d)\n", __func__, set); 359 printk(KERN_DEBUG "%s(%d)\n", __func__, set);
359 360
360 s3c2410_gpio_setpin(S3C2410_GPG(13), set); 361 gpio_set_value(S3C2410_GPG(13), set);
361 s3c2410_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_OUTPUT);
362} 362}
363 363
364#undef LCD_UPPER_MARGIN 364#undef LCD_UPPER_MARGIN
@@ -391,7 +391,7 @@ static struct ili9320_platdata jive_lcm_config = {
391 391
392static void jive_lcd_spi_chipselect(struct s3c2410_spigpio_info *spi, int cs) 392static void jive_lcd_spi_chipselect(struct s3c2410_spigpio_info *spi, int cs)
393{ 393{
394 s3c2410_gpio_setpin(S3C2410_GPB(7), cs ? 0 : 1); 394 gpio_set_value(S3C2410_GPB(7), cs ? 0 : 1);
395} 395}
396 396
397static struct s3c2410_spigpio_info jive_lcd_spi = { 397static struct s3c2410_spigpio_info jive_lcd_spi = {
@@ -413,7 +413,7 @@ static struct platform_device jive_device_lcdspi = {
413 413
414static void jive_wm8750_chipselect(struct s3c2410_spigpio_info *spi, int cs) 414static void jive_wm8750_chipselect(struct s3c2410_spigpio_info *spi, int cs)
415{ 415{
416 s3c2410_gpio_setpin(S3C2410_GPH(10), cs ? 0 : 1); 416 gpio_set_value(S3C2410_GPH(10), cs ? 0 : 1);
417} 417}
418 418
419static struct s3c2410_spigpio_info jive_wm8750_spi = { 419static struct s3c2410_spigpio_info jive_wm8750_spi = {
@@ -531,7 +531,7 @@ static void jive_power_off(void)
531 printk(KERN_INFO "powering system down...\n"); 531 printk(KERN_INFO "powering system down...\n");
532 532
533 s3c2410_gpio_setpin(S3C2410_GPC(5), 1); 533 s3c2410_gpio_setpin(S3C2410_GPC(5), 1);
534 s3c2410_gpio_cfgpin(S3C2410_GPC(5), S3C2410_GPIO_OUTPUT); 534 s3c_gpio_cfgpin(S3C2410_GPC(5), S3C2410_GPIO_OUTPUT);
535} 535}
536 536
537static void __init jive_machine_init(void) 537static void __init jive_machine_init(void)
@@ -636,22 +636,22 @@ static void __init jive_machine_init(void)
636 636
637 /* initialise the spi */ 637 /* initialise the spi */
638 638
639 s3c2410_gpio_setpin(S3C2410_GPG(13), 0); 639 gpio_request(S3C2410_GPG(13), "lcm reset");
640 s3c2410_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_OUTPUT); 640 gpio_direction_output(S3C2410_GPG(13), 0);
641 641
642 s3c2410_gpio_setpin(S3C2410_GPB(7), 1); 642 gpio_request(S3C2410_GPB(7), "jive spi");
643 s3c2410_gpio_cfgpin(S3C2410_GPB(7), S3C2410_GPIO_OUTPUT); 643 gpio_direction_output(S3C2410_GPB(7), 1);
644 644
645 s3c2410_gpio_setpin(S3C2410_GPB(6), 0); 645 s3c2410_gpio_setpin(S3C2410_GPB(6), 0);
646 s3c2410_gpio_cfgpin(S3C2410_GPB(6), S3C2410_GPIO_OUTPUT); 646 s3c_gpio_cfgpin(S3C2410_GPB(6), S3C2410_GPIO_OUTPUT);
647 647
648 s3c2410_gpio_setpin(S3C2410_GPG(8), 1); 648 s3c2410_gpio_setpin(S3C2410_GPG(8), 1);
649 s3c2410_gpio_cfgpin(S3C2410_GPG(8), S3C2410_GPIO_OUTPUT); 649 s3c_gpio_cfgpin(S3C2410_GPG(8), S3C2410_GPIO_OUTPUT);
650 650
651 /* initialise the WM8750 spi */ 651 /* initialise the WM8750 spi */
652 652
653 s3c2410_gpio_setpin(S3C2410_GPH(10), 1); 653 gpio_request(S3C2410_GPH(10), "jive wm8750 spi");
654 s3c2410_gpio_cfgpin(S3C2410_GPH(10), S3C2410_GPIO_OUTPUT); 654 gpio_direction_output(S3C2410_GPH(10), 1);
655 655
656 /* Turn off suspend on both USB ports, and switch the 656 /* Turn off suspend on both USB ports, and switch the
657 * selectable USB port to USB device mode. */ 657 * selectable USB port to USB device mode. */
diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c2412/mach-smdk2413.c
index 0392065af1a..faddb36ed23 100644
--- a/arch/arm/mach-s3c2412/mach-smdk2413.c
+++ b/arch/arm/mach-s3c2412/mach-smdk2413.c
@@ -85,10 +85,10 @@ static void smdk2413_udc_pullup(enum s3c2410_udc_cmd_e cmd)
85 switch (cmd) 85 switch (cmd)
86 { 86 {
87 case S3C2410_UDC_P_ENABLE : 87 case S3C2410_UDC_P_ENABLE :
88 s3c2410_gpio_setpin(S3C2410_GPF(2), 1); 88 gpio_set_value(S3C2410_GPF(2), 1);
89 break; 89 break;
90 case S3C2410_UDC_P_DISABLE : 90 case S3C2410_UDC_P_DISABLE :
91 s3c2410_gpio_setpin(S3C2410_GPF(2), 0); 91 gpio_set_value(S3C2410_GPF(2), 0);
92 break; 92 break;
93 case S3C2410_UDC_P_RESET : 93 case S3C2410_UDC_P_RESET :
94 break; 94 break;
@@ -134,8 +134,8 @@ static void __init smdk2413_machine_init(void)
134{ /* Turn off suspend on both USB ports, and switch the 134{ /* Turn off suspend on both USB ports, and switch the
135 * selectable USB port to USB device mode. */ 135 * selectable USB port to USB device mode. */
136 136
137 s3c2410_gpio_setpin(S3C2410_GPF(2), 0); 137 WARN_ON(gpio_request(S3C2410_GPF(2), "udc pull"));
138 s3c2410_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT); 138 gpio_direction_output(S3C2410_GPF(2), 0);
139 139
140 s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST | 140 s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
141 S3C2410_MISCCR_USBSUSPND0 | 141 S3C2410_MISCCR_USBSUSPND0 |
diff --git a/arch/arm/mach-s3c2416/Kconfig b/arch/arm/mach-s3c2416/Kconfig
new file mode 100644
index 00000000000..29103a6047d
--- /dev/null
+++ b/arch/arm/mach-s3c2416/Kconfig
@@ -0,0 +1,38 @@
1# arch/arm/mach-s3c2416/Kconfig
2#
3# Copyright 2009 Yauhen Kharuzhy <jekhor@gmail.com>
4#
5# Licensed under GPLv2
6
7# note, this also supports the S3C2450 which is so similar it has the same
8# ID code as the S3C2416.
9
10config CPU_S3C2416
11 bool
12 depends on ARCH_S3C2410
13 select CPU_ARM926T
14 select S3C2416_DMA if S3C2410_DMA
15 select CPU_LLSERIAL_S3C2440
16 select S3C_GPIO_PULL_UPDOWN
17 select SAMSUNG_CLKSRC
18 select S3C2443_CLOCK
19 help
20 Support for the S3C2416 SoC from the S3C24XX line
21
22config S3C2416_DMA
23 bool
24 depends on CPU_S3C2416
25 help
26 Internal config node for S3C2416 DMA support
27
28menu "S3C2416 Machines"
29
30config MACH_SMDK2416
31 bool "SMDK2416"
32 select CPU_S3C2416
33 select S3C_DEV_HSMMC
34 select S3C_DEV_HSMMC1
35 help
36 Say Y here if you are using an SMDK2416
37
38endmenu
diff --git a/arch/arm/mach-s3c2416/Makefile b/arch/arm/mach-s3c2416/Makefile
new file mode 100644
index 00000000000..6c12c7bf40a
--- /dev/null
+++ b/arch/arm/mach-s3c2416/Makefile
@@ -0,0 +1,19 @@
1# arch/arm/mach-s3c2416/Makefile
2#
3# Copyright 2009 Yauhen Kharuzhy <jekhor@gmail.com>
4#
5# Licensed under GPLv2
6
7obj-y :=
8obj-m :=
9obj-n :=
10obj- :=
11
12obj-$(CONFIG_CPU_S3C2416) += s3c2416.o clock.o
13obj-$(CONFIG_CPU_S3C2416) += irq.o
14
15#obj-$(CONFIG_S3C2416_DMA) += dma.o
16
17# Machine support
18
19obj-$(CONFIG_MACH_SMDK2416) += mach-smdk2416.o
diff --git a/arch/arm/mach-s3c2416/clock.c b/arch/arm/mach-s3c2416/clock.c
new file mode 100644
index 00000000000..7ccf5a2a2bf
--- /dev/null
+++ b/arch/arm/mach-s3c2416/clock.c
@@ -0,0 +1,135 @@
1/* linux/arch/arm/mach-s3c2416/clock.c
2 *
3 * Copyright (c) 2010 Simtec Electronics
4 * Copyright (c) 2010 Ben Dooks <ben-linux@fluff.org>
5 *
6 * S3C2416 Clock control support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/init.h>
15#include <linux/clk.h>
16
17#include <plat/s3c2416.h>
18#include <plat/s3c2443.h>
19#include <plat/clock.h>
20#include <plat/clock-clksrc.h>
21#include <plat/cpu.h>
22
23#include <plat/cpu-freq.h>
24#include <plat/pll6553x.h>
25#include <plat/pll.h>
26
27#include <asm/mach/map.h>
28
29#include <mach/regs-clock.h>
30#include <mach/regs-s3c2443-clock.h>
31
32static unsigned int armdiv[8] = {
33 [0] = 1,
34 [1] = 2,
35 [2] = 3,
36 [3] = 4,
37 [5] = 6,
38 [7] = 8,
39};
40
41/* ID to hardware numbering, 0 is HSMMC1, 1 is HSMMC0 */
42static struct clksrc_clk hsmmc_div[] = {
43 [0] = {
44 .clk = {
45 .name = "hsmmc-div",
46 .id = 1,
47 .parent = &clk_esysclk.clk,
48 },
49 .reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 },
50 },
51 [1] = {
52 .clk = {
53 .name = "hsmmc-div",
54 .id = 0,
55 .parent = &clk_esysclk.clk,
56 },
57 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
58 },
59};
60
61static struct clksrc_clk hsmmc_mux[] = {
62 [0] = {
63 .clk = {
64 .id = 1,
65 .name = "hsmmc-if",
66 .ctrlbit = (1 << 6),
67 .enable = s3c2443_clkcon_enable_s,
68 },
69 .sources = &(struct clksrc_sources) {
70 .nr_sources = 2,
71 .sources = (struct clk *[]) {
72 [0] = &hsmmc_div[0].clk,
73 [1] = NULL, /* to fix */
74 },
75 },
76 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 },
77 },
78 [1] = {
79 .clk = {
80 .id = 0,
81 .name = "hsmmc-if",
82 .ctrlbit = (1 << 12),
83 .enable = s3c2443_clkcon_enable_s,
84 },
85 .sources = &(struct clksrc_sources) {
86 .nr_sources = 2,
87 .sources = (struct clk *[]) {
88 [0] = &hsmmc_div[1].clk,
89 [1] = NULL, /* to fix */
90 },
91 },
92 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 },
93 },
94};
95
96
97static inline unsigned int s3c2416_fclk_div(unsigned long clkcon0)
98{
99 clkcon0 &= 7 << S3C2443_CLKDIV0_ARMDIV_SHIFT;
100
101 return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT];
102}
103
104void __init_or_cpufreq s3c2416_setup_clocks(void)
105{
106 s3c2443_common_setup_clocks(s3c2416_get_pll, s3c2416_fclk_div);
107}
108
109
110static struct clksrc_clk *clksrcs[] __initdata = {
111 &hsmmc_div[0],
112 &hsmmc_div[1],
113 &hsmmc_mux[0],
114 &hsmmc_mux[1],
115};
116
117void __init s3c2416_init_clocks(int xtal)
118{
119 u32 epllcon = __raw_readl(S3C2443_EPLLCON);
120 u32 epllcon1 = __raw_readl(S3C2443_EPLLCON+4);
121 int ptr;
122
123 /* s3c2416 EPLL compatible with s3c64xx */
124 clk_epll.rate = s3c_get_pll6553x(xtal, epllcon, epllcon1);
125
126 clk_epll.parent = &clk_epllref.clk;
127
128 s3c2443_common_init_clocks(xtal, s3c2416_get_pll, s3c2416_fclk_div);
129
130 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
131 s3c_register_clksrc(clksrcs[ptr], 1);
132
133 s3c_pwmclk_init();
134
135}
diff --git a/arch/arm/mach-s3c2416/irq.c b/arch/arm/mach-s3c2416/irq.c
new file mode 100644
index 00000000000..89f521d59d0
--- /dev/null
+++ b/arch/arm/mach-s3c2416/irq.c
@@ -0,0 +1,254 @@
1/* linux/arch/arm/mach-s3c2416/irq.c
2 *
3 * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
4 * as part of OpenInkpot project
5 * Copyright (c) 2009 Promwad Innovation Company
6 * Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22*/
23
24#include <linux/init.h>
25#include <linux/module.h>
26#include <linux/interrupt.h>
27#include <linux/ioport.h>
28#include <linux/sysdev.h>
29#include <linux/io.h>
30
31#include <mach/hardware.h>
32#include <asm/irq.h>
33
34#include <asm/mach/irq.h>
35
36#include <mach/regs-irq.h>
37#include <mach/regs-gpio.h>
38
39#include <plat/cpu.h>
40#include <plat/pm.h>
41#include <plat/irq.h>
42
43#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
44
45static inline void s3c2416_irq_demux(unsigned int irq, unsigned int len)
46{
47 unsigned int subsrc, submsk;
48 unsigned int end;
49
50 /* read the current pending interrupts, and the mask
51 * for what it is available */
52
53 subsrc = __raw_readl(S3C2410_SUBSRCPND);
54 submsk = __raw_readl(S3C2410_INTSUBMSK);
55
56 subsrc &= ~submsk;
57 subsrc >>= (irq - S3C2410_IRQSUB(0));
58 subsrc &= (1 << len)-1;
59
60 end = len + irq;
61
62 for (; irq < end && subsrc; irq++) {
63 if (subsrc & 1)
64 generic_handle_irq(irq);
65
66 subsrc >>= 1;
67 }
68}
69
70/* WDT/AC97 sub interrupts */
71
72static void s3c2416_irq_demux_wdtac97(unsigned int irq, struct irq_desc *desc)
73{
74 s3c2416_irq_demux(IRQ_S3C2443_WDT, 4);
75}
76
77#define INTMSK_WDTAC97 (1UL << (IRQ_WDT - IRQ_EINT0))
78#define SUBMSK_WDTAC97 INTMSK(IRQ_S3C2443_WDT, IRQ_S3C2443_AC97)
79
80static void s3c2416_irq_wdtac97_mask(unsigned int irqno)
81{
82 s3c_irqsub_mask(irqno, INTMSK_WDTAC97, SUBMSK_WDTAC97);
83}
84
85static void s3c2416_irq_wdtac97_unmask(unsigned int irqno)
86{
87 s3c_irqsub_unmask(irqno, INTMSK_WDTAC97);
88}
89
90static void s3c2416_irq_wdtac97_ack(unsigned int irqno)
91{
92 s3c_irqsub_maskack(irqno, INTMSK_WDTAC97, SUBMSK_WDTAC97);
93}
94
95static struct irq_chip s3c2416_irq_wdtac97 = {
96 .mask = s3c2416_irq_wdtac97_mask,
97 .unmask = s3c2416_irq_wdtac97_unmask,
98 .ack = s3c2416_irq_wdtac97_ack,
99};
100
101
102/* LCD sub interrupts */
103
104static void s3c2416_irq_demux_lcd(unsigned int irq, struct irq_desc *desc)
105{
106 s3c2416_irq_demux(IRQ_S3C2443_LCD1, 4);
107}
108
109#define INTMSK_LCD (1UL << (IRQ_LCD - IRQ_EINT0))
110#define SUBMSK_LCD INTMSK(IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4)
111
112static void s3c2416_irq_lcd_mask(unsigned int irqno)
113{
114 s3c_irqsub_mask(irqno, INTMSK_LCD, SUBMSK_LCD);
115}
116
117static void s3c2416_irq_lcd_unmask(unsigned int irqno)
118{
119 s3c_irqsub_unmask(irqno, INTMSK_LCD);
120}
121
122static void s3c2416_irq_lcd_ack(unsigned int irqno)
123{
124 s3c_irqsub_maskack(irqno, INTMSK_LCD, SUBMSK_LCD);
125}
126
127static struct irq_chip s3c2416_irq_lcd = {
128 .mask = s3c2416_irq_lcd_mask,
129 .unmask = s3c2416_irq_lcd_unmask,
130 .ack = s3c2416_irq_lcd_ack,
131};
132
133
134/* DMA sub interrupts */
135
136static void s3c2416_irq_demux_dma(unsigned int irq, struct irq_desc *desc)
137{
138 s3c2416_irq_demux(IRQ_S3C2443_DMA0, 6);
139}
140
141#define INTMSK_DMA (1UL << (IRQ_S3C2443_DMA - IRQ_EINT0))
142#define SUBMSK_DMA INTMSK(IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5)
143
144
145static void s3c2416_irq_dma_mask(unsigned int irqno)
146{
147 s3c_irqsub_mask(irqno, INTMSK_DMA, SUBMSK_DMA);
148}
149
150static void s3c2416_irq_dma_unmask(unsigned int irqno)
151{
152 s3c_irqsub_unmask(irqno, INTMSK_DMA);
153}
154
155static void s3c2416_irq_dma_ack(unsigned int irqno)
156{
157 s3c_irqsub_maskack(irqno, INTMSK_DMA, SUBMSK_DMA);
158}
159
160static struct irq_chip s3c2416_irq_dma = {
161 .mask = s3c2416_irq_dma_mask,
162 .unmask = s3c2416_irq_dma_unmask,
163 .ack = s3c2416_irq_dma_ack,
164};
165
166
167/* UART3 sub interrupts */
168
169static void s3c2416_irq_demux_uart3(unsigned int irq, struct irq_desc *desc)
170{
171 s3c2416_irq_demux(IRQ_S3C2443_UART3, 3);
172}
173
174#define INTMSK_UART3 (1UL << (IRQ_S3C2443_UART3 - IRQ_EINT0))
175#define SUBMSK_UART3 (0xf << (IRQ_S3C2443_RX3 - S3C2410_IRQSUB(0)))
176
177
178static void s3c2416_irq_uart3_mask(unsigned int irqno)
179{
180 s3c_irqsub_mask(irqno, INTMSK_UART3, SUBMSK_UART3);
181}
182
183static void s3c2416_irq_uart3_unmask(unsigned int irqno)
184{
185 s3c_irqsub_unmask(irqno, INTMSK_UART3);
186}
187
188static void s3c2416_irq_uart3_ack(unsigned int irqno)
189{
190 s3c_irqsub_maskack(irqno, INTMSK_UART3, SUBMSK_UART3);
191}
192
193static struct irq_chip s3c2416_irq_uart3 = {
194 .mask = s3c2416_irq_uart3_mask,
195 .unmask = s3c2416_irq_uart3_unmask,
196 .ack = s3c2416_irq_uart3_ack,
197};
198
199
200/* IRQ initialisation code */
201
202static int __init s3c2416_add_sub(unsigned int base,
203 void (*demux)(unsigned int,
204 struct irq_desc *),
205 struct irq_chip *chip,
206 unsigned int start, unsigned int end)
207{
208 unsigned int irqno;
209
210 set_irq_chip(base, &s3c_irq_level_chip);
211 set_irq_handler(base, handle_level_irq);
212 set_irq_chained_handler(base, demux);
213
214 for (irqno = start; irqno <= end; irqno++) {
215 set_irq_chip(irqno, chip);
216 set_irq_handler(irqno, handle_level_irq);
217 set_irq_flags(irqno, IRQF_VALID);
218 }
219
220 return 0;
221}
222
223static int __init s3c2416_irq_add(struct sys_device *sysdev)
224{
225 printk(KERN_INFO "S3C2416: IRQ Support\n");
226
227 s3c2416_add_sub(IRQ_LCD, s3c2416_irq_demux_lcd, &s3c2416_irq_lcd,
228 IRQ_S3C2443_LCD2, IRQ_S3C2443_LCD4);
229
230 s3c2416_add_sub(IRQ_S3C2443_DMA, s3c2416_irq_demux_dma,
231 &s3c2416_irq_dma, IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5);
232
233 s3c2416_add_sub(IRQ_S3C2443_UART3, s3c2416_irq_demux_uart3,
234 &s3c2416_irq_uart3,
235 IRQ_S3C2443_RX3, IRQ_S3C2443_ERR3);
236
237 s3c2416_add_sub(IRQ_WDT, s3c2416_irq_demux_wdtac97,
238 &s3c2416_irq_wdtac97,
239 IRQ_S3C2443_WDT, IRQ_S3C2443_AC97);
240
241 return 0;
242}
243
244static struct sysdev_driver s3c2416_irq_driver = {
245 .add = s3c2416_irq_add,
246};
247
248static int __init s3c2416_irq_init(void)
249{
250 return sysdev_driver_register(&s3c2416_sysclass, &s3c2416_irq_driver);
251}
252
253arch_initcall(s3c2416_irq_init);
254
diff --git a/arch/arm/mach-s3c2416/mach-smdk2416.c b/arch/arm/mach-s3c2416/mach-smdk2416.c
new file mode 100644
index 00000000000..99d24c44f30
--- /dev/null
+++ b/arch/arm/mach-s3c2416/mach-smdk2416.c
@@ -0,0 +1,150 @@
1/* linux/arch/arm/mach-s3c2416/mach-hanlin_v3c.c
2 *
3 * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
4 * as part of OpenInkpot project
5 * Copyright (c) 2009 Promwad Innovation Company
6 * Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/interrupt.h>
17#include <linux/list.h>
18#include <linux/timer.h>
19#include <linux/init.h>
20#include <linux/serial_core.h>
21#include <linux/platform_device.h>
22#include <linux/io.h>
23#include <linux/mtd/partitions.h>
24#include <linux/gpio.h>
25
26#include <asm/mach/arch.h>
27#include <asm/mach/map.h>
28#include <asm/mach/irq.h>
29
30#include <mach/hardware.h>
31#include <asm/irq.h>
32#include <asm/mach-types.h>
33
34#include <plat/regs-serial.h>
35#include <mach/regs-gpio.h>
36#include <mach/regs-lcd.h>
37
38#include <mach/idle.h>
39#include <mach/fb.h>
40#include <mach/leds-gpio.h>
41#include <plat/iic.h>
42
43#include <plat/s3c2416.h>
44#include <plat/clock.h>
45#include <plat/devs.h>
46#include <plat/cpu.h>
47#include <plat/nand.h>
48
49#include <plat/common-smdk.h>
50
51static struct map_desc smdk2416_iodesc[] __initdata = {
52 /* ISA IO Space map (memory space selected by A24) */
53
54 {
55 .virtual = (u32)S3C24XX_VA_ISA_WORD,
56 .pfn = __phys_to_pfn(S3C2410_CS2),
57 .length = 0x10000,
58 .type = MT_DEVICE,
59 }, {
60 .virtual = (u32)S3C24XX_VA_ISA_WORD + 0x10000,
61 .pfn = __phys_to_pfn(S3C2410_CS2 + (1<<24)),
62 .length = SZ_4M,
63 .type = MT_DEVICE,
64 }, {
65 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
66 .pfn = __phys_to_pfn(S3C2410_CS2),
67 .length = 0x10000,
68 .type = MT_DEVICE,
69 }, {
70 .virtual = (u32)S3C24XX_VA_ISA_BYTE + 0x10000,
71 .pfn = __phys_to_pfn(S3C2410_CS2 + (1<<24)),
72 .length = SZ_4M,
73 .type = MT_DEVICE,
74 }
75};
76
77#define UCON (S3C2410_UCON_DEFAULT | \
78 S3C2440_UCON_PCLK | \
79 S3C2443_UCON_RXERR_IRQEN)
80
81#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE)
82
83#define UFCON (S3C2410_UFCON_RXTRIG8 | \
84 S3C2410_UFCON_FIFOMODE | \
85 S3C2440_UFCON_TXTRIG16)
86
87static struct s3c2410_uartcfg smdk2416_uartcfgs[] __initdata = {
88 [0] = {
89 .hwport = 0,
90 .flags = 0,
91 .ucon = UCON,
92 .ulcon = ULCON,
93 .ufcon = UFCON,
94 },
95 [1] = {
96 .hwport = 1,
97 .flags = 0,
98 .ucon = UCON,
99 .ulcon = ULCON,
100 .ufcon = UFCON,
101 },
102 /* IR port */
103 [2] = {
104 .hwport = 2,
105 .flags = 0,
106 .ucon = UCON,
107 .ulcon = ULCON | 0x50,
108 .ufcon = UFCON,
109 }
110};
111
112static struct platform_device *smdk2416_devices[] __initdata = {
113 &s3c_device_wdt,
114 &s3c_device_ohci,
115 &s3c_device_i2c0,
116 &s3c_device_hsmmc0,
117 &s3c_device_hsmmc1,
118};
119
120static void __init smdk2416_map_io(void)
121{
122
123 s3c24xx_init_io(smdk2416_iodesc, ARRAY_SIZE(smdk2416_iodesc));
124 s3c24xx_init_clocks(12000000);
125 s3c24xx_init_uarts(smdk2416_uartcfgs, ARRAY_SIZE(smdk2416_uartcfgs));
126
127}
128
129static void __init smdk2416_machine_init(void)
130{
131 s3c_i2c0_set_platdata(NULL);
132
133 gpio_request(S3C2410_GPB(4), "USBHost Power");
134 gpio_direction_output(S3C2410_GPB(4), 1);
135
136 platform_add_devices(smdk2416_devices, ARRAY_SIZE(smdk2416_devices));
137 smdk_machine_init();
138}
139
140MACHINE_START(SMDK2416, "SMDK2416")
141 /* Maintainer: Yauhen Kharuzhy <jekhor@gmail.com> */
142 .phys_io = S3C2410_PA_UART,
143 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
144 .boot_params = S3C2410_SDRAM_PA + 0x100,
145
146 .init_irq = s3c24xx_init_irq,
147 .map_io = smdk2416_map_io,
148 .init_machine = smdk2416_machine_init,
149 .timer = &s3c24xx_timer,
150MACHINE_END
diff --git a/arch/arm/mach-s3c2416/s3c2416.c b/arch/arm/mach-s3c2416/s3c2416.c
new file mode 100644
index 00000000000..3bff05745d0
--- /dev/null
+++ b/arch/arm/mach-s3c2416/s3c2416.c
@@ -0,0 +1,128 @@
1/* linux/arch/arm/mach-s3c2416/s3c2416.c
2 *
3 * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
4 * as part of OpenInkpot project
5 * Copyright (c) 2009 Promwad Innovation Company
6 * Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
7 *
8 * Samsung S3C2416 Mobile CPU support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23*/
24
25#include <linux/kernel.h>
26#include <linux/types.h>
27#include <linux/interrupt.h>
28#include <linux/list.h>
29#include <linux/timer.h>
30#include <linux/init.h>
31#include <linux/gpio.h>
32#include <linux/platform_device.h>
33#include <linux/serial_core.h>
34#include <linux/sysdev.h>
35#include <linux/clk.h>
36#include <linux/io.h>
37
38#include <asm/mach/arch.h>
39#include <asm/mach/map.h>
40#include <asm/mach/irq.h>
41
42#include <mach/hardware.h>
43#include <asm/proc-fns.h>
44#include <asm/irq.h>
45
46#include <mach/reset.h>
47#include <mach/idle.h>
48#include <mach/regs-s3c2443-clock.h>
49
50#include <plat/gpio-core.h>
51#include <plat/gpio-cfg.h>
52#include <plat/gpio-cfg-helpers.h>
53#include <plat/s3c2416.h>
54#include <plat/devs.h>
55#include <plat/cpu.h>
56
57#include <plat/iic-core.h>
58
59static struct map_desc s3c2416_iodesc[] __initdata = {
60 IODESC_ENT(WATCHDOG),
61 IODESC_ENT(CLKPWR),
62 IODESC_ENT(TIMER),
63};
64
65struct sysdev_class s3c2416_sysclass = {
66 .name = "s3c2416-core",
67};
68
69static struct sys_device s3c2416_sysdev = {
70 .cls = &s3c2416_sysclass,
71};
72
73static void s3c2416_hard_reset(void)
74{
75 __raw_writel(S3C2443_SWRST_RESET, S3C2443_SWRST);
76}
77
78int __init s3c2416_init(void)
79{
80 printk(KERN_INFO "S3C2416: Initializing architecture\n");
81
82 s3c24xx_reset_hook = s3c2416_hard_reset;
83 /* s3c24xx_idle = s3c2416_idle; */
84
85 /* change WDT IRQ number */
86 s3c_device_wdt.resource[1].start = IRQ_S3C2443_WDT;
87 s3c_device_wdt.resource[1].end = IRQ_S3C2443_WDT;
88
89 /* the i2c devices are directly compatible with s3c2440 */
90 s3c_i2c0_setname("s3c2440-i2c");
91 s3c_i2c1_setname("s3c2440-i2c");
92
93 return sysdev_register(&s3c2416_sysdev);
94}
95
96void __init s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no)
97{
98 s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no);
99
100 s3c_device_nand.name = "s3c2416-nand";
101}
102
103/* s3c2416_map_io
104 *
105 * register the standard cpu IO areas, and any passed in from the
106 * machine specific initialisation.
107 */
108
109void __init s3c2416_map_io(void)
110{
111 s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_updown;
112 s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_updown;
113
114 iotable_init(s3c2416_iodesc, ARRAY_SIZE(s3c2416_iodesc));
115}
116
117/* need to register class before we actually register the device, and
118 * we also need to ensure that it has been initialised before any of the
119 * drivers even try to use it (even if not on an s3c2416 based system)
120 * as a driver which may support both 2443 and 2440 may try and use it.
121*/
122
123static int __init s3c2416_core_init(void)
124{
125 return sysdev_class_register(&s3c2416_sysclass);
126}
127
128core_initcall(s3c2416_core_init);
diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig
index 7f465265cf0..9d102b91209 100644
--- a/arch/arm/mach-s3c2440/Kconfig
+++ b/arch/arm/mach-s3c2440/Kconfig
@@ -6,6 +6,7 @@ config CPU_S3C2440
6 bool 6 bool
7 depends on ARCH_S3C2410 7 depends on ARCH_S3C2410
8 select CPU_ARM920T 8 select CPU_ARM920T
9 select S3C_GPIO_PULL_UP
9 select S3C2410_CLOCK 10 select S3C2410_CLOCK
10 select S3C2410_PM if PM 11 select S3C2410_PM if PM
11 select S3C2410_GPIO 12 select S3C2410_GPIO
diff --git a/arch/arm/mach-s3c2440/mach-mini2440.c b/arch/arm/mach-s3c2440/mach-mini2440.c
index 571b17683d9..a76bcda210a 100644
--- a/arch/arm/mach-s3c2440/mach-mini2440.c
+++ b/arch/arm/mach-s3c2440/mach-mini2440.c
@@ -53,6 +53,7 @@
53#include <linux/mtd/nand_ecc.h> 53#include <linux/mtd/nand_ecc.h>
54#include <linux/mtd/partitions.h> 54#include <linux/mtd/partitions.h>
55 55
56#include <plat/gpio-cfg.h>
56#include <plat/clock.h> 57#include <plat/clock.h>
57#include <plat/devs.h> 58#include <plat/devs.h>
58#include <plat/cpu.h> 59#include <plat/cpu.h>
@@ -102,10 +103,10 @@ static void mini2440_udc_pullup(enum s3c2410_udc_cmd_e cmd)
102 103
103 switch (cmd) { 104 switch (cmd) {
104 case S3C2410_UDC_P_ENABLE : 105 case S3C2410_UDC_P_ENABLE :
105 s3c2410_gpio_setpin(S3C2410_GPC(5), 1); 106 gpio_set_value(S3C2410_GPC(5), 1);
106 break; 107 break;
107 case S3C2410_UDC_P_DISABLE : 108 case S3C2410_UDC_P_DISABLE :
108 s3c2410_gpio_setpin(S3C2410_GPC(5), 0); 109 gpio_set_value(S3C2410_GPC(5), 0);
109 break; 110 break;
110 case S3C2410_UDC_P_RESET : 111 case S3C2410_UDC_P_RESET :
111 break; 112 break;
@@ -632,25 +633,25 @@ static void __init mini2440_init(void)
632 mini2440_parse_features(&features, mini2440_features_str); 633 mini2440_parse_features(&features, mini2440_features_str);
633 634
634 /* turn LCD on */ 635 /* turn LCD on */
635 s3c2410_gpio_cfgpin(S3C2410_GPC(0), S3C2410_GPC0_LEND); 636 s3c_gpio_cfgpin(S3C2410_GPC(0), S3C2410_GPC0_LEND);
636 637
637 /* Turn the backlight early on */ 638 /* Turn the backlight early on */
638 s3c2410_gpio_setpin(S3C2410_GPG(4), 1); 639 WARN_ON(gpio_request(S3C2410_GPG(4), "backlight"));
639 s3c2410_gpio_cfgpin(S3C2410_GPG(4), S3C2410_GPIO_OUTPUT); 640 gpio_direction_output(S3C2410_GPG(4), 1);
640 641
641 /* remove pullup on optional PWM backlight -- unused on 3.5 and 7"s */ 642 /* remove pullup on optional PWM backlight -- unused on 3.5 and 7"s */
642 s3c2410_gpio_pullup(S3C2410_GPB(1), 0); 643 s3c_gpio_setpull(S3C2410_GPB(1), S3C_GPIO_PULL_UP);
643 s3c2410_gpio_setpin(S3C2410_GPB(1), 0); 644 s3c2410_gpio_setpin(S3C2410_GPB(1), 0);
644 s3c2410_gpio_cfgpin(S3C2410_GPB(1), S3C2410_GPIO_INPUT); 645 s3c_gpio_cfgpin(S3C2410_GPB(1), S3C2410_GPIO_INPUT);
645 646
646 /* Make sure the D+ pullup pin is output */ 647 /* Make sure the D+ pullup pin is output */
647 s3c2410_gpio_cfgpin(S3C2410_GPC(5), S3C2410_GPIO_OUTPUT); 648 WARN_ON(gpio_request(S3C2410_GPC(5), "udc pup"));
649 gpio_direction_output(S3C2410_GPC(5), 0);
648 650
649 /* mark the key as input, without pullups (there is one on the board) */ 651 /* mark the key as input, without pullups (there is one on the board) */
650 for (i = 0; i < ARRAY_SIZE(mini2440_buttons); i++) { 652 for (i = 0; i < ARRAY_SIZE(mini2440_buttons); i++) {
651 s3c2410_gpio_pullup(mini2440_buttons[i].gpio, 0); 653 s3c_gpio_setpull(mini2440_buttons[i].gpio, S3C_GPIO_PULL_UP);
652 s3c2410_gpio_cfgpin(mini2440_buttons[i].gpio, 654 s3c_gpio_cfgpin(mini2440_buttons[i].gpio, S3C2410_GPIO_INPUT);
653 S3C2410_GPIO_INPUT);
654 } 655 }
655 if (features.lcd_index != -1) { 656 if (features.lcd_index != -1) {
656 int li; 657 int li;
diff --git a/arch/arm/mach-s3c2440/mach-nexcoder.c b/arch/arm/mach-s3c2440/mach-nexcoder.c
index 342041593f2..3ff62de45fd 100644
--- a/arch/arm/mach-s3c2440/mach-nexcoder.c
+++ b/arch/arm/mach-s3c2440/mach-nexcoder.c
@@ -40,6 +40,7 @@
40#include <plat/regs-serial.h> 40#include <plat/regs-serial.h>
41#include <plat/iic.h> 41#include <plat/iic.h>
42 42
43#include <plat/gpio-cfg.h>
43#include <plat/s3c2410.h> 44#include <plat/s3c2410.h>
44#include <plat/s3c244x.h> 45#include <plat/s3c244x.h>
45#include <plat/clock.h> 46#include <plat/clock.h>
@@ -122,15 +123,15 @@ static void __init nexcoder_sensorboard_init(void)
122{ 123{
123 // Initialize SCCB bus 124 // Initialize SCCB bus
124 s3c2410_gpio_setpin(S3C2410_GPE(14), 1); // IICSCL 125 s3c2410_gpio_setpin(S3C2410_GPE(14), 1); // IICSCL
125 s3c2410_gpio_cfgpin(S3C2410_GPE(14), S3C2410_GPIO_OUTPUT); 126 s3c_gpio_cfgpin(S3C2410_GPE(14), S3C2410_GPIO_OUTPUT);
126 s3c2410_gpio_setpin(S3C2410_GPE(15), 1); // IICSDA 127 s3c2410_gpio_setpin(S3C2410_GPE(15), 1); // IICSDA
127 s3c2410_gpio_cfgpin(S3C2410_GPE(15), S3C2410_GPIO_OUTPUT); 128 s3c_gpio_cfgpin(S3C2410_GPE(15), S3C2410_GPIO_OUTPUT);
128 129
129 // Power up the sensor board 130 // Power up the sensor board
130 s3c2410_gpio_setpin(S3C2410_GPF(1), 1); 131 s3c2410_gpio_setpin(S3C2410_GPF(1), 1);
131 s3c2410_gpio_cfgpin(S3C2410_GPF(1), S3C2410_GPIO_OUTPUT); // CAM_GPIO7 => nLDO_PWRDN 132 s3c_gpio_cfgpin(S3C2410_GPF(1), S3C2410_GPIO_OUTPUT); // CAM_GPIO7 => nLDO_PWRDN
132 s3c2410_gpio_setpin(S3C2410_GPF(2), 0); 133 s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
133 s3c2410_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT); // CAM_GPIO6 => CAM_PWRDN 134 s3c_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT); // CAM_GPIO6 => CAM_PWRDN
134} 135}
135 136
136static void __init nexcoder_map_io(void) 137static void __init nexcoder_map_io(void)
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c
index f35371db33f..319458da71a 100644
--- a/arch/arm/mach-s3c2440/mach-osiris.c
+++ b/arch/arm/mach-s3c2440/mach-osiris.c
@@ -49,6 +49,7 @@
49#include <linux/mtd/nand_ecc.h> 49#include <linux/mtd/nand_ecc.h>
50#include <linux/mtd/partitions.h> 50#include <linux/mtd/partitions.h>
51 51
52#include <plat/gpio-cfg.h>
52#include <plat/clock.h> 53#include <plat/clock.h>
53#include <plat/devs.h> 54#include <plat/devs.h>
54#include <plat/cpu.h> 55#include <plat/cpu.h>
@@ -298,7 +299,7 @@ static int osiris_pm_suspend(struct sys_device *sd, pm_message_t state)
298 299
299 /* ensure that an nRESET is not generated on resume. */ 300 /* ensure that an nRESET is not generated on resume. */
300 s3c2410_gpio_setpin(S3C2410_GPA(21), 1); 301 s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
301 s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT); 302 s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);
302 303
303 return 0; 304 return 0;
304} 305}
@@ -310,7 +311,7 @@ static int osiris_pm_resume(struct sys_device *sd)
310 311
311 __raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0); 312 __raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0);
312 313
313 s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT); 314 s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
314 315
315 return 0; 316 return 0;
316} 317}
diff --git a/arch/arm/mach-s3c2440/s3c2440.c b/arch/arm/mach-s3c2440/s3c2440.c
index 2b68f7ea45a..d50f3ae6173 100644
--- a/arch/arm/mach-s3c2440/s3c2440.c
+++ b/arch/arm/mach-s3c2440/s3c2440.c
@@ -19,6 +19,7 @@
19#include <linux/platform_device.h> 19#include <linux/platform_device.h>
20#include <linux/serial_core.h> 20#include <linux/serial_core.h>
21#include <linux/sysdev.h> 21#include <linux/sysdev.h>
22#include <linux/gpio.h>
22#include <linux/clk.h> 23#include <linux/clk.h>
23#include <linux/io.h> 24#include <linux/io.h>
24 25
@@ -33,6 +34,10 @@
33#include <plat/cpu.h> 34#include <plat/cpu.h>
34#include <plat/s3c244x.h> 35#include <plat/s3c244x.h>
35 36
37#include <plat/gpio-core.h>
38#include <plat/gpio-cfg.h>
39#include <plat/gpio-cfg-helpers.h>
40
36static struct sys_device s3c2440_sysdev = { 41static struct sys_device s3c2440_sysdev = {
37 .cls = &s3c2440_sysclass, 42 .cls = &s3c2440_sysclass,
38}; 43};
@@ -41,6 +46,9 @@ int __init s3c2440_init(void)
41{ 46{
42 printk("S3C2440: Initialising architecture\n"); 47 printk("S3C2440: Initialising architecture\n");
43 48
49 s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_1up;
50 s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_1up;
51
44 /* change irq for watchdog */ 52 /* change irq for watchdog */
45 53
46 s3c_device_wdt.resource[1].start = IRQ_S3C2440_WDT; 54 s3c_device_wdt.resource[1].start = IRQ_S3C2440_WDT;
diff --git a/arch/arm/mach-s3c2443/Kconfig b/arch/arm/mach-s3c2443/Kconfig
index 698140af247..4fef723126f 100644
--- a/arch/arm/mach-s3c2443/Kconfig
+++ b/arch/arm/mach-s3c2443/Kconfig
@@ -8,6 +8,7 @@ config CPU_S3C2443
8 select S3C2443_DMA if S3C2410_DMA 8 select S3C2443_DMA if S3C2410_DMA
9 select CPU_LLSERIAL_S3C2440 9 select CPU_LLSERIAL_S3C2440
10 select SAMSUNG_CLKSRC 10 select SAMSUNG_CLKSRC
11 select S3C2443_CLOCK
11 help 12 help
12 Support for the S3C2443 SoC from the S3C24XX line 13 Support for the S3C2443 SoC from the S3C24XX line
13 14
diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c
index 62cd4eaee01..83b1aa63d77 100644
--- a/arch/arm/mach-s3c2443/clock.c
+++ b/arch/arm/mach-s3c2443/clock.c
@@ -21,6 +21,7 @@
21*/ 21*/
22 22
23#include <linux/init.h> 23#include <linux/init.h>
24
24#include <linux/module.h> 25#include <linux/module.h>
25#include <linux/kernel.h> 26#include <linux/kernel.h>
26#include <linux/list.h> 27#include <linux/list.h>
@@ -54,111 +55,13 @@
54 * set the correct muxing at initialisation 55 * set the correct muxing at initialisation
55*/ 56*/
56 57
57static int s3c2443_gate(void __iomem *reg, struct clk *clk, int enable)
58{
59 u32 ctrlbit = clk->ctrlbit;
60 u32 con = __raw_readl(reg);
61
62 if (enable)
63 con |= ctrlbit;
64 else
65 con &= ~ctrlbit;
66
67 __raw_writel(con, reg);
68 return 0;
69}
70
71static int s3c2443_clkcon_enable_h(struct clk *clk, int enable)
72{
73 return s3c2443_gate(S3C2443_HCLKCON, clk, enable);
74}
75
76static int s3c2443_clkcon_enable_p(struct clk *clk, int enable)
77{
78 return s3c2443_gate(S3C2443_PCLKCON, clk, enable);
79}
80
81static int s3c2443_clkcon_enable_s(struct clk *clk, int enable)
82{
83 return s3c2443_gate(S3C2443_SCLKCON, clk, enable);
84}
85
86/* clock selections */ 58/* clock selections */
87 59
88/* mpllref is a direct descendant of clk_xtal by default, but it is not
89 * elided as the EPLL can be either sourced by the XTAL or EXTCLK and as
90 * such directly equating the two source clocks is impossible.
91 */
92static struct clk clk_mpllref = {
93 .name = "mpllref",
94 .parent = &clk_xtal,
95 .id = -1,
96};
97
98static struct clk clk_i2s_ext = { 60static struct clk clk_i2s_ext = {
99 .name = "i2s-ext", 61 .name = "i2s-ext",
100 .id = -1, 62 .id = -1,
101}; 63};
102 64
103static struct clk *clk_epllref_sources[] = {
104 [0] = &clk_mpllref,
105 [1] = &clk_mpllref,
106 [2] = &clk_xtal,
107 [3] = &clk_ext,
108};
109
110static struct clksrc_clk clk_epllref = {
111 .clk = {
112 .name = "epllref",
113 .id = -1,
114 },
115 .sources = &(struct clksrc_sources) {
116 .sources = clk_epllref_sources,
117 .nr_sources = ARRAY_SIZE(clk_epllref_sources),
118 },
119 .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 7 },
120};
121
122static unsigned long s3c2443_getrate_mdivclk(struct clk *clk)
123{
124 unsigned long parent_rate = clk_get_rate(clk->parent);
125 unsigned long div = __raw_readl(S3C2443_CLKDIV0);
126
127 div &= S3C2443_CLKDIV0_EXTDIV_MASK;
128 div >>= (S3C2443_CLKDIV0_EXTDIV_SHIFT-1); /* x2 */
129
130 return parent_rate / (div + 1);
131}
132
133static struct clk clk_mdivclk = {
134 .name = "mdivclk",
135 .parent = &clk_mpllref,
136 .id = -1,
137 .ops = &(struct clk_ops) {
138 .get_rate = s3c2443_getrate_mdivclk,
139 },
140};
141
142static struct clk *clk_msysclk_sources[] = {
143 [0] = &clk_mpllref,
144 [1] = &clk_mpll,
145 [2] = &clk_mdivclk,
146 [3] = &clk_mpllref,
147};
148
149static struct clksrc_clk clk_msysclk = {
150 .clk = {
151 .name = "msysclk",
152 .parent = &clk_xtal,
153 .id = -1,
154 },
155 .sources = &(struct clksrc_sources) {
156 .sources = clk_msysclk_sources,
157 .nr_sources = ARRAY_SIZE(clk_msysclk_sources),
158 },
159 .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 3 },
160};
161
162/* armdiv 65/* armdiv
163 * 66 *
164 * this clock is sourced from msysclk and can have a number of 67 * this clock is sourced from msysclk and can have a number of
@@ -266,44 +169,6 @@ static struct clksrc_clk clk_arm = {
266 .reg_src = { .reg = S3C2443_CLKDIV0, .size = 1, .shift = 13 }, 169 .reg_src = { .reg = S3C2443_CLKDIV0, .size = 1, .shift = 13 },
267}; 170};
268 171
269/* esysclk
270 *
271 * this is sourced from either the EPLL or the EPLLref clock
272*/
273
274static struct clk *clk_sysclk_sources[] = {
275 [0] = &clk_epllref.clk,
276 [1] = &clk_epll,
277};
278
279static struct clksrc_clk clk_esysclk = {
280 .clk = {
281 .name = "esysclk",
282 .parent = &clk_epll,
283 .id = -1,
284 },
285 .sources = &(struct clksrc_sources) {
286 .sources = clk_sysclk_sources,
287 .nr_sources = ARRAY_SIZE(clk_sysclk_sources),
288 },
289 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 6 },
290};
291
292/* uartclk
293 *
294 * UART baud-rate clock sourced from esysclk via a divisor
295*/
296
297static struct clksrc_clk clk_uart = {
298 .clk = {
299 .name = "uartclk",
300 .id = -1,
301 .parent = &clk_esysclk.clk,
302 },
303 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 },
304};
305
306
307/* hsspi 172/* hsspi
308 * 173 *
309 * high-speed spi clock, sourced from esysclk 174 * high-speed spi clock, sourced from esysclk
@@ -320,21 +185,6 @@ static struct clksrc_clk clk_hsspi = {
320 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 }, 185 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 },
321}; 186};
322 187
323/* usbhost
324 *
325 * usb host bus-clock, usually 48MHz to provide USB bus clock timing
326*/
327
328static struct clksrc_clk clk_usb_bus_host = {
329 .clk = {
330 .name = "usb-bus-host-parent",
331 .id = -1,
332 .parent = &clk_esysclk.clk,
333 .ctrlbit = S3C2443_SCLKCON_USBHOST,
334 .enable = s3c2443_clkcon_enable_s,
335 },
336 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 },
337};
338 188
339/* clk_hsmcc_div 189/* clk_hsmcc_div
340 * 190 *
@@ -433,89 +283,16 @@ static struct clksrc_clk clk_i2s = {
433 .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 14 }, 283 .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 14 },
434}; 284};
435 285
436/* cam-if
437 *
438 * camera interface bus-clock, divided down from esysclk
439*/
440
441static struct clksrc_clk clk_cam = {
442 .clk = {
443 .name = "camif-upll", /* same as 2440 name */
444 .id = -1,
445 .parent = &clk_esysclk.clk,
446 .ctrlbit = S3C2443_SCLKCON_CAMCLK,
447 .enable = s3c2443_clkcon_enable_s,
448 },
449 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 26 },
450};
451
452/* display-if
453 *
454 * display interface clock, divided from esysclk
455*/
456
457static struct clksrc_clk clk_display = {
458 .clk = {
459 .name = "display-if",
460 .id = -1,
461 .parent = &clk_esysclk.clk,
462 .ctrlbit = S3C2443_SCLKCON_DISPCLK,
463 .enable = s3c2443_clkcon_enable_s,
464 },
465 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 8, .shift = 16 },
466};
467
468/* prediv
469 *
470 * this divides the msysclk down to pass to h/p/etc.
471 */
472
473static unsigned long s3c2443_prediv_getrate(struct clk *clk)
474{
475 unsigned long rate = clk_get_rate(clk->parent);
476 unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
477
478 clkdiv0 &= S3C2443_CLKDIV0_PREDIV_MASK;
479 clkdiv0 >>= S3C2443_CLKDIV0_PREDIV_SHIFT;
480
481 return rate / (clkdiv0 + 1);
482}
483
484static struct clk clk_prediv = {
485 .name = "prediv",
486 .id = -1,
487 .parent = &clk_msysclk.clk,
488 .ops = &(struct clk_ops) {
489 .get_rate = s3c2443_prediv_getrate,
490 },
491};
492
493/* standard clock definitions */ 286/* standard clock definitions */
494 287
495static struct clk init_clocks_disable[] = { 288static struct clk init_clocks_off[] = {
496 { 289 {
497 .name = "nand",
498 .id = -1,
499 .parent = &clk_h,
500 }, {
501 .name = "sdi", 290 .name = "sdi",
502 .id = -1, 291 .id = -1,
503 .parent = &clk_p, 292 .parent = &clk_p,
504 .enable = s3c2443_clkcon_enable_p, 293 .enable = s3c2443_clkcon_enable_p,
505 .ctrlbit = S3C2443_PCLKCON_SDI, 294 .ctrlbit = S3C2443_PCLKCON_SDI,
506 }, { 295 }, {
507 .name = "adc",
508 .id = -1,
509 .parent = &clk_p,
510 .enable = s3c2443_clkcon_enable_p,
511 .ctrlbit = S3C2443_PCLKCON_ADC,
512 }, {
513 .name = "i2c",
514 .id = -1,
515 .parent = &clk_p,
516 .enable = s3c2443_clkcon_enable_p,
517 .ctrlbit = S3C2443_PCLKCON_IIC,
518 }, {
519 .name = "iis", 296 .name = "iis",
520 .id = -1, 297 .id = -1,
521 .parent = &clk_p, 298 .parent = &clk_p,
@@ -537,179 +314,12 @@ static struct clk init_clocks_disable[] = {
537}; 314};
538 315
539static struct clk init_clocks[] = { 316static struct clk init_clocks[] = {
540 {
541 .name = "dma",
542 .id = 0,
543 .parent = &clk_h,
544 .enable = s3c2443_clkcon_enable_h,
545 .ctrlbit = S3C2443_HCLKCON_DMA0,
546 }, {
547 .name = "dma",
548 .id = 1,
549 .parent = &clk_h,
550 .enable = s3c2443_clkcon_enable_h,
551 .ctrlbit = S3C2443_HCLKCON_DMA1,
552 }, {
553 .name = "dma",
554 .id = 2,
555 .parent = &clk_h,
556 .enable = s3c2443_clkcon_enable_h,
557 .ctrlbit = S3C2443_HCLKCON_DMA2,
558 }, {
559 .name = "dma",
560 .id = 3,
561 .parent = &clk_h,
562 .enable = s3c2443_clkcon_enable_h,
563 .ctrlbit = S3C2443_HCLKCON_DMA3,
564 }, {
565 .name = "dma",
566 .id = 4,
567 .parent = &clk_h,
568 .enable = s3c2443_clkcon_enable_h,
569 .ctrlbit = S3C2443_HCLKCON_DMA4,
570 }, {
571 .name = "dma",
572 .id = 5,
573 .parent = &clk_h,
574 .enable = s3c2443_clkcon_enable_h,
575 .ctrlbit = S3C2443_HCLKCON_DMA5,
576 }, {
577 .name = "lcd",
578 .id = -1,
579 .parent = &clk_h,
580 .enable = s3c2443_clkcon_enable_h,
581 .ctrlbit = S3C2443_HCLKCON_LCDC,
582 }, {
583 .name = "gpio",
584 .id = -1,
585 .parent = &clk_p,
586 .enable = s3c2443_clkcon_enable_p,
587 .ctrlbit = S3C2443_PCLKCON_GPIO,
588 }, {
589 .name = "usb-host",
590 .id = -1,
591 .parent = &clk_h,
592 .enable = s3c2443_clkcon_enable_h,
593 .ctrlbit = S3C2443_HCLKCON_USBH,
594 }, {
595 .name = "usb-device",
596 .id = -1,
597 .parent = &clk_h,
598 .enable = s3c2443_clkcon_enable_h,
599 .ctrlbit = S3C2443_HCLKCON_USBD,
600 }, {
601 .name = "hsmmc",
602 .id = -1,
603 .parent = &clk_h,
604 .enable = s3c2443_clkcon_enable_h,
605 .ctrlbit = S3C2443_HCLKCON_HSMMC,
606 }, {
607 .name = "cfc",
608 .id = -1,
609 .parent = &clk_h,
610 .enable = s3c2443_clkcon_enable_h,
611 .ctrlbit = S3C2443_HCLKCON_CFC,
612 }, {
613 .name = "ssmc",
614 .id = -1,
615 .parent = &clk_h,
616 .enable = s3c2443_clkcon_enable_h,
617 .ctrlbit = S3C2443_HCLKCON_SSMC,
618 }, {
619 .name = "timers",
620 .id = -1,
621 .parent = &clk_p,
622 .enable = s3c2443_clkcon_enable_p,
623 .ctrlbit = S3C2443_PCLKCON_PWMT,
624 }, {
625 .name = "uart",
626 .id = 0,
627 .parent = &clk_p,
628 .enable = s3c2443_clkcon_enable_p,
629 .ctrlbit = S3C2443_PCLKCON_UART0,
630 }, {
631 .name = "uart",
632 .id = 1,
633 .parent = &clk_p,
634 .enable = s3c2443_clkcon_enable_p,
635 .ctrlbit = S3C2443_PCLKCON_UART1,
636 }, {
637 .name = "uart",
638 .id = 2,
639 .parent = &clk_p,
640 .enable = s3c2443_clkcon_enable_p,
641 .ctrlbit = S3C2443_PCLKCON_UART2,
642 }, {
643 .name = "uart",
644 .id = 3,
645 .parent = &clk_p,
646 .enable = s3c2443_clkcon_enable_p,
647 .ctrlbit = S3C2443_PCLKCON_UART3,
648 }, {
649 .name = "rtc",
650 .id = -1,
651 .parent = &clk_p,
652 .enable = s3c2443_clkcon_enable_p,
653 .ctrlbit = S3C2443_PCLKCON_RTC,
654 }, {
655 .name = "watchdog",
656 .id = -1,
657 .parent = &clk_p,
658 .ctrlbit = S3C2443_PCLKCON_WDT,
659 }, {
660 .name = "usb-bus-host",
661 .id = -1,
662 .parent = &clk_usb_bus_host.clk,
663 }, {
664 .name = "ac97",
665 .id = -1,
666 .parent = &clk_p,
667 .ctrlbit = S3C2443_PCLKCON_AC97,
668 }
669};
670
671/* clocks to add where we need to check their parentage */
672
673static struct clksrc_clk __initdata *init_list[] = {
674 &clk_epllref, /* should be first */
675 &clk_esysclk,
676 &clk_msysclk,
677 &clk_arm,
678 &clk_i2s_eplldiv,
679 &clk_i2s,
680 &clk_cam,
681 &clk_uart,
682 &clk_display,
683 &clk_hsmmc_div,
684 &clk_usb_bus_host,
685}; 317};
686 318
687static void __init s3c2443_clk_initparents(void)
688{
689 int ptr;
690
691 for (ptr = 0; ptr < ARRAY_SIZE(init_list); ptr++)
692 s3c_set_clksrc(init_list[ptr], true);
693}
694
695static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0)
696{
697 clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
698
699 return clkcon0 + 1;
700}
701
702/* clocks to add straight away */ 319/* clocks to add straight away */
703 320
704static struct clksrc_clk *clksrcs[] __initdata = { 321static struct clksrc_clk *clksrcs[] __initdata = {
705 &clk_usb_bus_host,
706 &clk_epllref,
707 &clk_esysclk,
708 &clk_msysclk,
709 &clk_arm, 322 &clk_arm,
710 &clk_uart,
711 &clk_display,
712 &clk_cam,
713 &clk_i2s_eplldiv, 323 &clk_i2s_eplldiv,
714 &clk_i2s, 324 &clk_i2s,
715 &clk_hsspi, 325 &clk_hsspi,
@@ -717,92 +327,32 @@ static struct clksrc_clk *clksrcs[] __initdata = {
717}; 327};
718 328
719static struct clk *clks[] __initdata = { 329static struct clk *clks[] __initdata = {
720 &clk_ext,
721 &clk_epll,
722 &clk_usb_bus,
723 &clk_mpllref,
724 &clk_hsmmc, 330 &clk_hsmmc,
725 &clk_armdiv, 331 &clk_armdiv,
726 &clk_prediv,
727}; 332};
728 333
729void __init_or_cpufreq s3c2443_setup_clocks(void) 334void __init_or_cpufreq s3c2443_setup_clocks(void)
730{ 335{
731 unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON); 336 s3c2443_common_setup_clocks(s3c2443_get_mpll, s3c2443_fclk_div);
732 unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
733 struct clk *xtal_clk;
734 unsigned long xtal;
735 unsigned long pll;
736 unsigned long fclk;
737 unsigned long hclk;
738 unsigned long pclk;
739
740 xtal_clk = clk_get(NULL, "xtal");
741 xtal = clk_get_rate(xtal_clk);
742 clk_put(xtal_clk);
743
744 pll = s3c2443_get_mpll(mpllcon, xtal);
745 clk_msysclk.clk.rate = pll;
746
747 fclk = pll / s3c2443_fclk_div(clkdiv0);
748 hclk = s3c2443_prediv_getrate(&clk_prediv);
749 hclk /= s3c2443_get_hdiv(clkdiv0);
750 pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
751
752 s3c24xx_setup_clocks(fclk, hclk, pclk);
753
754 printk("S3C2443: mpll %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
755 (mpllcon & S3C2443_PLLCON_OFF) ? "off":"on",
756 print_mhz(pll), print_mhz(fclk),
757 print_mhz(hclk), print_mhz(pclk));
758
759 s3c24xx_setup_clocks(fclk, hclk, pclk);
760} 337}
761 338
762void __init s3c2443_init_clocks(int xtal) 339void __init s3c2443_init_clocks(int xtal)
763{ 340{
764 struct clk *clkp;
765 unsigned long epllcon = __raw_readl(S3C2443_EPLLCON); 341 unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
766 int ret;
767 int ptr; 342 int ptr;
768 343
769 /* s3c2443 parents h and p clocks from prediv */ 344 clk_epll.rate = s3c2443_get_epll(epllcon, xtal);
770 clk_h.parent = &clk_prediv; 345 clk_epll.parent = &clk_epllref.clk;
771 clk_p.parent = &clk_prediv; 346
347 s3c2443_common_init_clocks(xtal, s3c2443_get_mpll, s3c2443_fclk_div);
772 348
773 s3c24xx_register_baseclocks(xtal);
774 s3c2443_setup_clocks(); 349 s3c2443_setup_clocks();
775 s3c2443_clk_initparents();
776
777 for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
778 clkp = clks[ptr];
779 350
780 ret = s3c24xx_register_clock(clkp); 351 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
781 if (ret < 0) {
782 printk(KERN_ERR "Failed to register clock %s (%d)\n",
783 clkp->name, ret);
784 }
785 }
786 352
787 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) 353 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
788 s3c_register_clksrc(clksrcs[ptr], 1); 354 s3c_register_clksrc(clksrcs[ptr], 1);
789 355
790 clk_epll.rate = s3c2443_get_epll(epllcon, xtal);
791 clk_epll.parent = &clk_epllref.clk;
792 clk_usb_bus.parent = &clk_usb_bus_host.clk;
793
794 /* ensure usb bus clock is within correct rate of 48MHz */
795
796 if (clk_get_rate(&clk_usb_bus_host.clk) != (48 * 1000 * 1000)) {
797 printk(KERN_INFO "Warning: USB host bus not at 48MHz\n");
798 clk_set_rate(&clk_usb_bus_host.clk, 48*1000*1000);
799 }
800
801 printk("S3C2443: epll %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
802 (epllcon & S3C2443_PLLCON_OFF) ? "off":"on",
803 print_mhz(clk_get_rate(&clk_epll)),
804 print_mhz(clk_get_rate(&clk_usb_bus)));
805
806 /* register clocks from clock array */ 356 /* register clocks from clock array */
807 357
808 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); 358 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
@@ -819,17 +369,8 @@ void __init s3c2443_init_clocks(int xtal)
819 369
820 /* install (and disable) the clocks we do not need immediately */ 370 /* install (and disable) the clocks we do not need immediately */
821 371
822 clkp = init_clocks_disable; 372 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
823 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { 373 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
824
825 ret = s3c24xx_register_clock(clkp);
826 if (ret < 0) {
827 printk(KERN_ERR "Failed to register clock %s (%d)\n",
828 clkp->name, ret);
829 }
830
831 (clkp->enable)(clkp, 0);
832 }
833 374
834 s3c_pwmclk_init(); 375 s3c_pwmclk_init();
835} 376}
diff --git a/arch/arm/mach-s3c64xx/gpiolib.c b/arch/arm/mach-s3c64xx/gpiolib.c
index 66e6794481d..60c929a3cab 100644
--- a/arch/arm/mach-s3c64xx/gpiolib.c
+++ b/arch/arm/mach-s3c64xx/gpiolib.c
@@ -51,6 +51,7 @@
51 51
52static struct s3c_gpio_cfg gpio_4bit_cfg_noint = { 52static struct s3c_gpio_cfg gpio_4bit_cfg_noint = {
53 .set_config = s3c_gpio_setcfg_s3c64xx_4bit, 53 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
54 .get_config = s3c_gpio_getcfg_s3c64xx_4bit,
54 .set_pull = s3c_gpio_setpull_updown, 55 .set_pull = s3c_gpio_setpull_updown,
55 .get_pull = s3c_gpio_getpull_updown, 56 .get_pull = s3c_gpio_getpull_updown,
56}; 57};
@@ -58,12 +59,14 @@ static struct s3c_gpio_cfg gpio_4bit_cfg_noint = {
58static struct s3c_gpio_cfg gpio_4bit_cfg_eint0111 = { 59static struct s3c_gpio_cfg gpio_4bit_cfg_eint0111 = {
59 .cfg_eint = 7, 60 .cfg_eint = 7,
60 .set_config = s3c_gpio_setcfg_s3c64xx_4bit, 61 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
62 .get_config = s3c_gpio_getcfg_s3c64xx_4bit,
61 .set_pull = s3c_gpio_setpull_updown, 63 .set_pull = s3c_gpio_setpull_updown,
62 .get_pull = s3c_gpio_getpull_updown, 64 .get_pull = s3c_gpio_getpull_updown,
63}; 65};
64 66
65static struct s3c_gpio_cfg gpio_4bit_cfg_eint0011 = { 67static struct s3c_gpio_cfg gpio_4bit_cfg_eint0011 = {
66 .cfg_eint = 3, 68 .cfg_eint = 3,
69 .get_config = s3c_gpio_getcfg_s3c64xx_4bit,
67 .set_config = s3c_gpio_setcfg_s3c64xx_4bit, 70 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
68 .set_pull = s3c_gpio_setpull_updown, 71 .set_pull = s3c_gpio_setpull_updown,
69 .get_pull = s3c_gpio_getpull_updown, 72 .get_pull = s3c_gpio_getpull_updown,
@@ -171,6 +174,7 @@ static struct s3c_gpio_chip gpio_4bit2[] = {
171 174
172static struct s3c_gpio_cfg gpio_2bit_cfg_noint = { 175static struct s3c_gpio_cfg gpio_2bit_cfg_noint = {
173 .set_config = s3c_gpio_setcfg_s3c24xx, 176 .set_config = s3c_gpio_setcfg_s3c24xx,
177 .get_config = s3c_gpio_getcfg_s3c24xx,
174 .set_pull = s3c_gpio_setpull_updown, 178 .set_pull = s3c_gpio_setpull_updown,
175 .get_pull = s3c_gpio_getpull_updown, 179 .get_pull = s3c_gpio_getpull_updown,
176}; 180};
@@ -178,6 +182,7 @@ static struct s3c_gpio_cfg gpio_2bit_cfg_noint = {
178static struct s3c_gpio_cfg gpio_2bit_cfg_eint10 = { 182static struct s3c_gpio_cfg gpio_2bit_cfg_eint10 = {
179 .cfg_eint = 2, 183 .cfg_eint = 2,
180 .set_config = s3c_gpio_setcfg_s3c24xx, 184 .set_config = s3c_gpio_setcfg_s3c24xx,
185 .get_config = s3c_gpio_getcfg_s3c24xx,
181 .set_pull = s3c_gpio_setpull_updown, 186 .set_pull = s3c_gpio_setpull_updown,
182 .get_pull = s3c_gpio_getpull_updown, 187 .get_pull = s3c_gpio_getpull_updown,
183}; 188};
@@ -185,6 +190,7 @@ static struct s3c_gpio_cfg gpio_2bit_cfg_eint10 = {
185static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = { 190static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = {
186 .cfg_eint = 3, 191 .cfg_eint = 3,
187 .set_config = s3c_gpio_setcfg_s3c24xx, 192 .set_config = s3c_gpio_setcfg_s3c24xx,
193 .get_config = s3c_gpio_getcfg_s3c24xx,
188 .set_pull = s3c_gpio_setpull_updown, 194 .set_pull = s3c_gpio_setpull_updown,
189 .get_pull = s3c_gpio_getpull_updown, 195 .get_pull = s3c_gpio_getpull_updown,
190}; 196};
diff --git a/arch/arm/mach-s3c64xx/include/mach/pll.h b/arch/arm/mach-s3c64xx/include/mach/pll.h
index 90bbd72fdc4..5ef0bb698ee 100644
--- a/arch/arm/mach-s3c64xx/include/mach/pll.h
+++ b/arch/arm/mach-s3c64xx/include/mach/pll.h
@@ -20,6 +20,7 @@
20#define S3C6400_PLL_SDIV_SHIFT (0) 20#define S3C6400_PLL_SDIV_SHIFT (0)
21 21
22#include <asm/div64.h> 22#include <asm/div64.h>
23#include <plat/pll6553x.h>
23 24
24static inline unsigned long s3c6400_get_pll(unsigned long baseclk, 25static inline unsigned long s3c6400_get_pll(unsigned long baseclk,
25 u32 pllcon) 26 u32 pllcon)
@@ -37,38 +38,8 @@ static inline unsigned long s3c6400_get_pll(unsigned long baseclk,
37 return (unsigned long)fvco; 38 return (unsigned long)fvco;
38} 39}
39 40
40#define S3C6400_EPLL_MDIV_MASK ((1 << (23-16)) - 1)
41#define S3C6400_EPLL_PDIV_MASK ((1 << (13-8)) - 1)
42#define S3C6400_EPLL_SDIV_MASK ((1 << (2-0)) - 1)
43#define S3C6400_EPLL_MDIV_SHIFT (16)
44#define S3C6400_EPLL_PDIV_SHIFT (8)
45#define S3C6400_EPLL_SDIV_SHIFT (0)
46#define S3C6400_EPLL_KDIV_MASK (0xffff)
47
48static inline unsigned long s3c6400_get_epll(unsigned long baseclk) 41static inline unsigned long s3c6400_get_epll(unsigned long baseclk)
49{ 42{
50 unsigned long result; 43 return s3c_get_pll6553x(baseclk, __raw_readl(S3C_EPLL_CON0),
51 u32 epll0 = __raw_readl(S3C_EPLL_CON0); 44 __raw_readl(S3C_EPLL_CON1));
52 u32 epll1 = __raw_readl(S3C_EPLL_CON1);
53 u32 mdiv, pdiv, sdiv, kdiv;
54 u64 tmp;
55
56 mdiv = (epll0 >> S3C6400_EPLL_MDIV_SHIFT) & S3C6400_EPLL_MDIV_MASK;
57 pdiv = (epll0 >> S3C6400_EPLL_PDIV_SHIFT) & S3C6400_EPLL_PDIV_MASK;
58 sdiv = (epll0 >> S3C6400_EPLL_SDIV_SHIFT) & S3C6400_EPLL_SDIV_MASK;
59 kdiv = epll1 & S3C6400_EPLL_KDIV_MASK;
60
61 /* We need to multiple baseclk by mdiv (the integer part) and kdiv
62 * which is in 2^16ths, so shift mdiv up (does not overflow) and
63 * add kdiv before multiplying. The use of tmp is to avoid any
64 * overflows before shifting bac down into result when multipling
65 * by the mdiv and kdiv pair.
66 */
67
68 tmp = baseclk;
69 tmp *= (mdiv << 16) + kdiv;
70 do_div(tmp, (pdiv << sdiv));
71 result = tmp >> 16;
72
73 return result;
74} 45}
diff --git a/arch/arm/mach-s5p6440/gpio.c b/arch/arm/mach-s5p6440/gpio.c
index b0ea741177a..262dc75d5be 100644
--- a/arch/arm/mach-s5p6440/gpio.c
+++ b/arch/arm/mach-s5p6440/gpio.c
@@ -161,12 +161,15 @@ static struct s3c_gpio_cfg s5p6440_gpio_cfgs[] = {
161 }, { 161 }, {
162 .cfg_eint = 0, 162 .cfg_eint = 0,
163 .set_config = s3c_gpio_setcfg_s3c24xx, 163 .set_config = s3c_gpio_setcfg_s3c24xx,
164 .get_config = s3c_gpio_getcfg_s3c24xx,
164 }, { 165 }, {
165 .cfg_eint = 2, 166 .cfg_eint = 2,
166 .set_config = s3c_gpio_setcfg_s3c24xx, 167 .set_config = s3c_gpio_setcfg_s3c24xx,
168 .get_config = s3c_gpio_getcfg_s3c24xx,
167 }, { 169 }, {
168 .cfg_eint = 3, 170 .cfg_eint = 3,
169 .set_config = s3c_gpio_setcfg_s3c24xx, 171 .set_config = s3c_gpio_setcfg_s3c24xx,
172 .get_config = s3c_gpio_getcfg_s3c24xx,
170 }, 173 },
171}; 174};
172 175
@@ -279,6 +282,8 @@ void __init s5p6440_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
279 for (; nr_chips > 0; nr_chips--, chipcfg++) { 282 for (; nr_chips > 0; nr_chips--, chipcfg++) {
280 if (!chipcfg->set_config) 283 if (!chipcfg->set_config)
281 chipcfg->set_config = s3c_gpio_setcfg_s3c64xx_4bit; 284 chipcfg->set_config = s3c_gpio_setcfg_s3c64xx_4bit;
285 if (!chipcfg->get_config)
286 chipcfg->get_config = s3c_gpio_getcfg_s3c64xx_4bit;
282 if (!chipcfg->set_pull) 287 if (!chipcfg->set_pull)
283 chipcfg->set_pull = s3c_gpio_setpull_updown; 288 chipcfg->set_pull = s3c_gpio_setpull_updown;
284 if (!chipcfg->get_pull) 289 if (!chipcfg->get_pull)
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
index 6e93ef8f3d4..3ce8f010b3c 100644
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ b/arch/arm/plat-s3c24xx/Kconfig
@@ -9,6 +9,7 @@ config PLAT_S3C24XX
9 select NO_IOPORT 9 select NO_IOPORT
10 select ARCH_REQUIRE_GPIOLIB 10 select ARCH_REQUIRE_GPIOLIB
11 select S3C_DEVICE_NAND 11 select S3C_DEVICE_NAND
12 select S3C_GPIO_CFG_S3C24XX
12 help 13 help
13 Base platform code for any Samsung S3C24XX device 14 Base platform code for any Samsung S3C24XX device
14 15
@@ -44,6 +45,12 @@ config S3C2410_CLOCK
44 Clock code for the S3C2410, and similar processors which 45 Clock code for the S3C2410, and similar processors which
45 is currently includes the S3C2410, S3C2440, S3C2442. 46 is currently includes the S3C2410, S3C2440, S3C2442.
46 47
48config S3C2443_CLOCK
49 bool
50 help
51 Clock code for the S3C2443 and similar processors, which includes
52 the S3C2416 and S3C2450.
53
47config S3C24XX_DCLK 54config S3C24XX_DCLK
48 bool 55 bool
49 help 56 help
diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile
index c2237c41141..44aea8868f8 100644
--- a/arch/arm/plat-s3c24xx/Makefile
+++ b/arch/arm/plat-s3c24xx/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_PM) += pm.o
30obj-$(CONFIG_PM) += irq-pm.o 30obj-$(CONFIG_PM) += irq-pm.o
31obj-$(CONFIG_PM) += sleep.o 31obj-$(CONFIG_PM) += sleep.o
32obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o 32obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o
33obj-$(CONFIG_S3C2443_CLOCK) += s3c2443-clock.o
33obj-$(CONFIG_S3C2410_DMA) += dma.o 34obj-$(CONFIG_S3C2410_DMA) += dma.o
34obj-$(CONFIG_S3C2410_IOTIMING) += s3c2410-iotiming.o 35obj-$(CONFIG_S3C2410_IOTIMING) += s3c2410-iotiming.o
35obj-$(CONFIG_S3C2412_IOTIMING) += s3c2412-iotiming.o 36obj-$(CONFIG_S3C2412_IOTIMING) += s3c2412-iotiming.o
diff --git a/arch/arm/plat-s3c24xx/common-smdk.c b/arch/arm/plat-s3c24xx/common-smdk.c
index 9e0e20ad2e4..7b44d0c592b 100644
--- a/arch/arm/plat-s3c24xx/common-smdk.c
+++ b/arch/arm/plat-s3c24xx/common-smdk.c
@@ -42,6 +42,7 @@
42#include <plat/nand.h> 42#include <plat/nand.h>
43 43
44#include <plat/common-smdk.h> 44#include <plat/common-smdk.h>
45#include <plat/gpio-cfg.h>
45#include <plat/devs.h> 46#include <plat/devs.h>
46#include <plat/pm.h> 47#include <plat/pm.h>
47 48
@@ -185,10 +186,10 @@ void __init smdk_machine_init(void)
185{ 186{
186 /* Configure the LEDs (even if we have no LED support)*/ 187 /* Configure the LEDs (even if we have no LED support)*/
187 188
188 s3c2410_gpio_cfgpin(S3C2410_GPF(4), S3C2410_GPIO_OUTPUT); 189 s3c_gpio_cfgpin(S3C2410_GPF(4), S3C2410_GPIO_OUTPUT);
189 s3c2410_gpio_cfgpin(S3C2410_GPF(5), S3C2410_GPIO_OUTPUT); 190 s3c_gpio_cfgpin(S3C2410_GPF(5), S3C2410_GPIO_OUTPUT);
190 s3c2410_gpio_cfgpin(S3C2410_GPF(6), S3C2410_GPIO_OUTPUT); 191 s3c_gpio_cfgpin(S3C2410_GPF(6), S3C2410_GPIO_OUTPUT);
191 s3c2410_gpio_cfgpin(S3C2410_GPF(7), S3C2410_GPIO_OUTPUT); 192 s3c_gpio_cfgpin(S3C2410_GPF(7), S3C2410_GPIO_OUTPUT);
192 193
193 s3c2410_gpio_setpin(S3C2410_GPF(4), 1); 194 s3c2410_gpio_setpin(S3C2410_GPF(4), 1);
194 s3c2410_gpio_setpin(S3C2410_GPF(5), 1); 195 s3c2410_gpio_setpin(S3C2410_GPF(5), 1);
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
index 9ca64df35bf..76d0858c3cb 100644
--- a/arch/arm/plat-s3c24xx/cpu.c
+++ b/arch/arm/plat-s3c24xx/cpu.c
@@ -49,6 +49,7 @@
49#include <plat/s3c2400.h> 49#include <plat/s3c2400.h>
50#include <plat/s3c2410.h> 50#include <plat/s3c2410.h>
51#include <plat/s3c2412.h> 51#include <plat/s3c2412.h>
52#include <plat/s3c2416.h>
52#include <plat/s3c244x.h> 53#include <plat/s3c244x.h>
53#include <plat/s3c2443.h> 54#include <plat/s3c2443.h>
54 55
@@ -57,6 +58,7 @@
57static const char name_s3c2400[] = "S3C2400"; 58static const char name_s3c2400[] = "S3C2400";
58static const char name_s3c2410[] = "S3C2410"; 59static const char name_s3c2410[] = "S3C2410";
59static const char name_s3c2412[] = "S3C2412"; 60static const char name_s3c2412[] = "S3C2412";
61static const char name_s3c2416[] = "S3C2416/S3C2450";
60static const char name_s3c2440[] = "S3C2440"; 62static const char name_s3c2440[] = "S3C2440";
61static const char name_s3c2442[] = "S3C2442"; 63static const char name_s3c2442[] = "S3C2442";
62static const char name_s3c2442b[] = "S3C2442B"; 64static const char name_s3c2442b[] = "S3C2442B";
@@ -137,6 +139,15 @@ static struct cpu_table cpu_ids[] __initdata = {
137 .init = s3c2412_init, 139 .init = s3c2412_init,
138 .name = name_s3c2412, 140 .name = name_s3c2412,
139 }, 141 },
142 { /* a strange version of the s3c2416 */
143 .idcode = 0x32450003,
144 .idmask = 0xffffffff,
145 .map_io = s3c2416_map_io,
146 .init_clocks = s3c2416_init_clocks,
147 .init_uarts = s3c2416_init_uarts,
148 .init = s3c2416_init,
149 .name = name_s3c2416,
150 },
140 { 151 {
141 .idcode = 0x32443001, 152 .idcode = 0x32443001,
142 .idmask = 0xffffffff, 153 .idmask = 0xffffffff,
@@ -170,6 +181,16 @@ static struct map_desc s3c_iodesc[] __initdata = {
170 181
171static unsigned long s3c24xx_read_idcode_v5(void) 182static unsigned long s3c24xx_read_idcode_v5(void)
172{ 183{
184#if defined(CONFIG_CPU_S3C2416)
185 /* s3c2416 is v5, with S3C24XX_GSTATUS1 instead of S3C2412_GSTATUS1 */
186
187 u32 gs = __raw_readl(S3C24XX_GSTATUS1);
188
189 /* test for s3c2416 or similar device */
190 if ((gs >> 16) == 0x3245)
191 return gs;
192#endif
193
173#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413) 194#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
174 return __raw_readl(S3C2412_GSTATUS1); 195 return __raw_readl(S3C2412_GSTATUS1);
175#else 196#else
diff --git a/arch/arm/plat-s3c24xx/gpio.c b/arch/arm/plat-s3c24xx/gpio.c
index 5467470badf..45126d3aafc 100644
--- a/arch/arm/plat-s3c24xx/gpio.c
+++ b/arch/arm/plat-s3c24xx/gpio.c
@@ -1,6 +1,6 @@
1/* linux/arch/arm/plat-s3c24xx/gpio.c 1/* linux/arch/arm/plat-s3c24xx/gpio.c
2 * 2 *
3 * Copyright (c) 2004-2005 Simtec Electronics 3 * Copyright (c) 2004-2010 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 4 * Ben Dooks <ben@simtec.co.uk>
5 * 5 *
6 * S3C24XX GPIO support 6 * S3C24XX GPIO support
@@ -20,12 +20,12 @@
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21*/ 21*/
22 22
23
24#include <linux/kernel.h> 23#include <linux/kernel.h>
25#include <linux/init.h> 24#include <linux/init.h>
26#include <linux/module.h> 25#include <linux/module.h>
27#include <linux/interrupt.h> 26#include <linux/interrupt.h>
28#include <linux/ioport.h> 27#include <linux/ioport.h>
28#include <linux/gpio.h>
29#include <linux/io.h> 29#include <linux/io.h>
30 30
31#include <mach/hardware.h> 31#include <mach/hardware.h>
@@ -34,123 +34,34 @@
34 34
35#include <mach/regs-gpio.h> 35#include <mach/regs-gpio.h>
36 36
37void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function) 37/* gpiolib wrappers until these are totally eliminated */
38{
39 void __iomem *base = S3C24XX_GPIO_BASE(pin);
40 unsigned long mask;
41 unsigned long con;
42 unsigned long flags;
43
44 if (pin < S3C2410_GPIO_BANKB) {
45 mask = 1 << S3C2410_GPIO_OFFSET(pin);
46 } else {
47 mask = 3 << S3C2410_GPIO_OFFSET(pin)*2;
48 }
49
50 switch (function) {
51 case S3C2410_GPIO_LEAVE:
52 mask = 0;
53 function = 0;
54 break;
55
56 case S3C2410_GPIO_INPUT:
57 case S3C2410_GPIO_OUTPUT:
58 case S3C2410_GPIO_SFN2:
59 case S3C2410_GPIO_SFN3:
60 if (pin < S3C2410_GPIO_BANKB) {
61 function -= 1;
62 function &= 1;
63 function <<= S3C2410_GPIO_OFFSET(pin);
64 } else {
65 function &= 3;
66 function <<= S3C2410_GPIO_OFFSET(pin)*2;
67 }
68 }
69
70 /* modify the specified register wwith IRQs off */
71
72 local_irq_save(flags);
73
74 con = __raw_readl(base + 0x00);
75 con &= ~mask;
76 con |= function;
77
78 __raw_writel(con, base + 0x00);
79
80 local_irq_restore(flags);
81}
82
83EXPORT_SYMBOL(s3c2410_gpio_cfgpin);
84
85unsigned int s3c2410_gpio_getcfg(unsigned int pin)
86{
87 void __iomem *base = S3C24XX_GPIO_BASE(pin);
88 unsigned long val = __raw_readl(base);
89
90 if (pin < S3C2410_GPIO_BANKB) {
91 val >>= S3C2410_GPIO_OFFSET(pin);
92 val &= 1;
93 val += 1;
94 } else {
95 val >>= S3C2410_GPIO_OFFSET(pin)*2;
96 val &= 3;
97 }
98
99 return val | S3C2410_GPIO_INPUT;
100}
101
102EXPORT_SYMBOL(s3c2410_gpio_getcfg);
103 38
104void s3c2410_gpio_pullup(unsigned int pin, unsigned int to) 39void s3c2410_gpio_pullup(unsigned int pin, unsigned int to)
105{ 40{
106 void __iomem *base = S3C24XX_GPIO_BASE(pin); 41 int ret;
107 unsigned long offs = S3C2410_GPIO_OFFSET(pin);
108 unsigned long flags;
109 unsigned long up;
110 42
111 if (pin < S3C2410_GPIO_BANKB) 43 WARN_ON(to); /* should be none of these left */
112 return;
113 44
114 local_irq_save(flags); 45 if (!to) {
115 46 /* if pull is enabled, try first with up, and if that
116 up = __raw_readl(base + 0x08); 47 * fails, try using down */
117 up &= ~(1L << offs);
118 up |= to << offs;
119 __raw_writel(up, base + 0x08);
120 48
121 local_irq_restore(flags); 49 ret = s3c_gpio_setpull(pin, S3C_GPIO_PULL_UP);
50 if (ret)
51 s3c_gpio_setpull(pin, S3C_GPIO_PULL_DOWN);
52 } else {
53 s3c_gpio_setpull(pin, S3C_GPIO_PULL_NONE);
54 }
122} 55}
123
124EXPORT_SYMBOL(s3c2410_gpio_pullup); 56EXPORT_SYMBOL(s3c2410_gpio_pullup);
125 57
126int s3c2410_gpio_getpull(unsigned int pin)
127{
128 void __iomem *base = S3C24XX_GPIO_BASE(pin);
129 unsigned long offs = S3C2410_GPIO_OFFSET(pin);
130
131 if (pin < S3C2410_GPIO_BANKB)
132 return -EINVAL;
133
134 return (__raw_readl(base + 0x08) & (1L << offs)) ? 1 : 0;
135}
136
137EXPORT_SYMBOL(s3c2410_gpio_getpull);
138
139void s3c2410_gpio_setpin(unsigned int pin, unsigned int to) 58void s3c2410_gpio_setpin(unsigned int pin, unsigned int to)
140{ 59{
141 void __iomem *base = S3C24XX_GPIO_BASE(pin); 60 /* do this via gpiolib until all users removed */
142 unsigned long offs = S3C2410_GPIO_OFFSET(pin);
143 unsigned long flags;
144 unsigned long dat;
145
146 local_irq_save(flags);
147 61
148 dat = __raw_readl(base + 0x04); 62 gpio_request(pin, "temporary");
149 dat &= ~(1 << offs); 63 gpio_set_value(pin, to);
150 dat |= to << offs; 64 gpio_free(pin);
151 __raw_writel(dat, base + 0x04);
152
153 local_irq_restore(flags);
154} 65}
155 66
156EXPORT_SYMBOL(s3c2410_gpio_setpin); 67EXPORT_SYMBOL(s3c2410_gpio_setpin);
@@ -181,22 +92,3 @@ unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change)
181} 92}
182 93
183EXPORT_SYMBOL(s3c2410_modify_misccr); 94EXPORT_SYMBOL(s3c2410_modify_misccr);
184
185int s3c2410_gpio_getirq(unsigned int pin)
186{
187 if (pin < S3C2410_GPF(0) || pin > S3C2410_GPG(15))
188 return -EINVAL; /* not valid interrupts */
189
190 if (pin < S3C2410_GPG(0) && pin > S3C2410_GPF(7))
191 return -EINVAL; /* not valid pin */
192
193 if (pin < S3C2410_GPF(4))
194 return (pin - S3C2410_GPF(0)) + IRQ_EINT0;
195
196 if (pin < S3C2410_GPG(0))
197 return (pin - S3C2410_GPF(4)) + IRQ_EINT4;
198
199 return (pin - S3C2410_GPG(0)) + IRQ_EINT8;
200}
201
202EXPORT_SYMBOL(s3c2410_gpio_getirq);
diff --git a/arch/arm/plat-s3c24xx/gpiolib.c b/arch/arm/plat-s3c24xx/gpiolib.c
index 4f0f11a6a67..4c0896f2572 100644
--- a/arch/arm/plat-s3c24xx/gpiolib.c
+++ b/arch/arm/plat-s3c24xx/gpiolib.c
@@ -1,6 +1,6 @@
1/* linux/arch/arm/plat-s3c24xx/gpiolib.c 1/* linux/arch/arm/plat-s3c24xx/gpiolib.c
2 * 2 *
3 * Copyright (c) 2008 Simtec Electronics 3 * Copyright (c) 2008-2010 Simtec Electronics
4 * http://armlinux.simtec.co.uk/ 4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk> 5 * Ben Dooks <ben@simtec.co.uk>
6 * 6 *
@@ -21,6 +21,8 @@
21#include <linux/gpio.h> 21#include <linux/gpio.h>
22 22
23#include <plat/gpio-core.h> 23#include <plat/gpio-core.h>
24#include <plat/gpio-cfg.h>
25#include <plat/gpio-cfg-helpers.h>
24#include <mach/hardware.h> 26#include <mach/hardware.h>
25#include <asm/irq.h> 27#include <asm/irq.h>
26#include <plat/pm.h> 28#include <plat/pm.h>
@@ -77,10 +79,21 @@ static int s3c24xx_gpiolib_bankg_toirq(struct gpio_chip *chip, unsigned offset)
77 return IRQ_EINT8 + offset; 79 return IRQ_EINT8 + offset;
78} 80}
79 81
82static struct s3c_gpio_cfg s3c24xx_gpiocfg_banka = {
83 .set_config = s3c_gpio_setcfg_s3c24xx_a,
84 .get_config = s3c_gpio_getcfg_s3c24xx_a,
85};
86
87struct s3c_gpio_cfg s3c24xx_gpiocfg_default = {
88 .set_config = s3c_gpio_setcfg_s3c24xx,
89 .get_config = s3c_gpio_getcfg_s3c24xx,
90};
91
80struct s3c_gpio_chip s3c24xx_gpios[] = { 92struct s3c_gpio_chip s3c24xx_gpios[] = {
81 [0] = { 93 [0] = {
82 .base = S3C2410_GPACON, 94 .base = S3C2410_GPACON,
83 .pm = __gpio_pm(&s3c_gpio_pm_1bit), 95 .pm = __gpio_pm(&s3c_gpio_pm_1bit),
96 .config = &s3c24xx_gpiocfg_banka,
84 .chip = { 97 .chip = {
85 .base = S3C2410_GPA(0), 98 .base = S3C2410_GPA(0),
86 .owner = THIS_MODULE, 99 .owner = THIS_MODULE,
@@ -161,15 +174,58 @@ struct s3c_gpio_chip s3c24xx_gpios[] = {
161 .ngpio = 11, 174 .ngpio = 11,
162 }, 175 },
163 }, 176 },
177 /* GPIOS for the S3C2443 and later devices. */
178 {
179 .base = S3C2440_GPJCON,
180 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
181 .chip = {
182 .base = S3C2410_GPJ(0),
183 .owner = THIS_MODULE,
184 .label = "GPIOJ",
185 .ngpio = 16,
186 },
187 }, {
188 .base = S3C2443_GPKCON,
189 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
190 .chip = {
191 .base = S3C2410_GPK(0),
192 .owner = THIS_MODULE,
193 .label = "GPIOK",
194 .ngpio = 16,
195 },
196 }, {
197 .base = S3C2443_GPLCON,
198 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
199 .chip = {
200 .base = S3C2410_GPL(0),
201 .owner = THIS_MODULE,
202 .label = "GPIOL",
203 .ngpio = 15,
204 },
205 }, {
206 .base = S3C2443_GPMCON,
207 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
208 .chip = {
209 .base = S3C2410_GPM(0),
210 .owner = THIS_MODULE,
211 .label = "GPIOM",
212 .ngpio = 2,
213 },
214 },
164}; 215};
165 216
217
166static __init int s3c24xx_gpiolib_init(void) 218static __init int s3c24xx_gpiolib_init(void)
167{ 219{
168 struct s3c_gpio_chip *chip = s3c24xx_gpios; 220 struct s3c_gpio_chip *chip = s3c24xx_gpios;
169 int gpn; 221 int gpn;
170 222
171 for (gpn = 0; gpn < ARRAY_SIZE(s3c24xx_gpios); gpn++, chip++) 223 for (gpn = 0; gpn < ARRAY_SIZE(s3c24xx_gpios); gpn++, chip++) {
224 if (!chip->config)
225 chip->config = &s3c24xx_gpiocfg_default;
226
172 s3c_gpiolib_add(chip); 227 s3c_gpiolib_add(chip);
228 }
173 229
174 return 0; 230 return 0;
175} 231}
diff --git a/arch/arm/plat-s3c24xx/include/plat/pll.h b/arch/arm/plat-s3c24xx/include/plat/pll.h
index 7ea8bffa7a9..005729a1077 100644
--- a/arch/arm/plat-s3c24xx/include/plat/pll.h
+++ b/arch/arm/plat-s3c24xx/include/plat/pll.h
@@ -35,3 +35,28 @@ s3c24xx_get_pll(unsigned int pllval, unsigned int baseclk)
35 35
36 return (unsigned int)fvco; 36 return (unsigned int)fvco;
37} 37}
38
39#define S3C2416_PLL_M_SHIFT (14)
40#define S3C2416_PLL_P_SHIFT (5)
41#define S3C2416_PLL_S_MASK (7)
42#define S3C2416_PLL_M_MASK ((1 << 10) - 1)
43#define S3C2416_PLL_P_MASK (63)
44
45static inline unsigned int
46s3c2416_get_pll(unsigned int pllval, unsigned int baseclk)
47{
48 unsigned int m, p, s;
49 uint64_t fvco;
50
51 m = pllval >> S3C2416_PLL_M_SHIFT;
52 p = pllval >> S3C2416_PLL_P_SHIFT;
53
54 s = pllval & S3C2416_PLL_S_MASK;
55 m &= S3C2416_PLL_M_MASK;
56 p &= S3C2416_PLL_P_MASK;
57
58 fvco = (uint64_t)baseclk * m;
59 do_div(fvco, (p << s));
60
61 return (unsigned int)fvco;
62}
diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2416.h b/arch/arm/plat-s3c24xx/include/plat/s3c2416.h
new file mode 100644
index 00000000000..dc3c0907d22
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/plat/s3c2416.h
@@ -0,0 +1,31 @@
1/* linux/include/asm-arm/plat-s3c24xx/s3c2443.h
2 *
3 * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>
4 *
5 * Header file for s3c2416 cpu support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#ifdef CONFIG_CPU_S3C2416
13
14struct s3c2410_uartcfg;
15
16extern int s3c2416_init(void);
17
18extern void s3c2416_map_io(void);
19
20extern void s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no);
21
22extern void s3c2416_init_clocks(int xtal);
23
24extern int s3c2416_baseclk_add(void);
25
26#else
27#define s3c2416_init_clocks NULL
28#define s3c2416_init_uarts NULL
29#define s3c2416_map_io NULL
30#define s3c2416_init NULL
31#endif
diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2443.h b/arch/arm/plat-s3c24xx/include/plat/s3c2443.h
index 815b107ed89..a19715feb79 100644
--- a/arch/arm/plat-s3c24xx/include/plat/s3c2443.h
+++ b/arch/arm/plat-s3c24xx/include/plat/s3c2443.h
@@ -30,3 +30,22 @@ extern int s3c2443_baseclk_add(void);
30#define s3c2443_map_io NULL 30#define s3c2443_map_io NULL
31#define s3c2443_init NULL 31#define s3c2443_init NULL
32#endif 32#endif
33
34/* common code used by s3c2443 and others.
35 * note, not to be used outside of arch/arm/mach-s3c* */
36
37struct clk; /* some files don't need clk.h otherwise */
38
39typedef unsigned int (*pll_fn)(unsigned int reg, unsigned int base);
40typedef unsigned int (*fdiv_fn)(unsigned long clkcon0);
41
42extern void s3c2443_common_setup_clocks(pll_fn get_mpll, fdiv_fn fdiv);
43extern void s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, fdiv_fn fdiv);
44
45extern int s3c2443_clkcon_enable_h(struct clk *clk, int enable);
46extern int s3c2443_clkcon_enable_p(struct clk *clk, int enable);
47extern int s3c2443_clkcon_enable_s(struct clk *clk, int enable);
48
49extern struct clksrc_clk clk_epllref;
50extern struct clksrc_clk clk_esysclk;
51extern struct clksrc_clk clk_msysclk;
diff --git a/arch/arm/plat-s3c24xx/pm.c b/arch/arm/plat-s3c24xx/pm.c
index 3620dd29909..60627e63a25 100644
--- a/arch/arm/plat-s3c24xx/pm.c
+++ b/arch/arm/plat-s3c24xx/pm.c
@@ -43,6 +43,7 @@
43 43
44#include <asm/mach/time.h> 44#include <asm/mach/time.h>
45 45
46#include <plat/gpio-cfg.h>
46#include <plat/pm.h> 47#include <plat/pm.h>
47 48
48#define PFX "s3c24xx-pm: " 49#define PFX "s3c24xx-pm: "
@@ -90,22 +91,22 @@ static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
90{ 91{
91 unsigned long irqstate; 92 unsigned long irqstate;
92 unsigned long pinstate; 93 unsigned long pinstate;
93 int irq = s3c2410_gpio_getirq(pin); 94 int irq = gpio_to_irq(pin);
94 95
95 if (irqoffs < 4) 96 if (irqoffs < 4)
96 irqstate = s3c_irqwake_intmask & (1L<<irqoffs); 97 irqstate = s3c_irqwake_intmask & (1L<<irqoffs);
97 else 98 else
98 irqstate = s3c_irqwake_eintmask & (1L<<irqoffs); 99 irqstate = s3c_irqwake_eintmask & (1L<<irqoffs);
99 100
100 pinstate = s3c2410_gpio_getcfg(pin); 101 pinstate = s3c_gpio_getcfg(pin);
101 102
102 if (!irqstate) { 103 if (!irqstate) {
103 if (pinstate == S3C2410_GPIO_IRQ) 104 if (pinstate == S3C2410_GPIO_IRQ)
104 S3C_PMDBG("Leaving IRQ %d (pin %d) enabled\n", irq, pin); 105 S3C_PMDBG("Leaving IRQ %d (pin %d) as is\n", irq, pin);
105 } else { 106 } else {
106 if (pinstate == S3C2410_GPIO_IRQ) { 107 if (pinstate == S3C2410_GPIO_IRQ) {
107 S3C_PMDBG("Disabling IRQ %d (pin %d)\n", irq, pin); 108 S3C_PMDBG("Disabling IRQ %d (pin %d)\n", irq, pin);
108 s3c2410_gpio_cfgpin(pin, S3C2410_GPIO_INPUT); 109 s3c_gpio_cfgpin(pin, S3C2410_GPIO_INPUT);
109 } 110 }
110 } 111 }
111} 112}
diff --git a/arch/arm/plat-s3c24xx/s3c2410-clock.c b/arch/arm/plat-s3c24xx/s3c2410-clock.c
index b61bdb79373..9ecc5d91367 100644
--- a/arch/arm/plat-s3c24xx/s3c2410-clock.c
+++ b/arch/arm/plat-s3c24xx/s3c2410-clock.c
@@ -87,7 +87,7 @@ static int s3c2410_upll_enable(struct clk *clk, int enable)
87 87
88/* standard clock definitions */ 88/* standard clock definitions */
89 89
90static struct clk init_clocks_disable[] = { 90static struct clk init_clocks_off[] = {
91 { 91 {
92 .name = "nand", 92 .name = "nand",
93 .id = -1, 93 .id = -1,
@@ -249,17 +249,8 @@ int __init s3c2410_baseclk_add(void)
249 249
250 /* install (and disable) the clocks we do not need immediately */ 250 /* install (and disable) the clocks we do not need immediately */
251 251
252 clkp = init_clocks_disable; 252 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
253 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { 253 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
254
255 ret = s3c24xx_register_clock(clkp);
256 if (ret < 0) {
257 printk(KERN_ERR "Failed to register clock %s (%d)\n",
258 clkp->name, ret);
259 }
260
261 s3c2410_clkcon_enable(clkp, 0);
262 }
263 254
264 /* show the clock-slow value */ 255 /* show the clock-slow value */
265 256
diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c
new file mode 100644
index 00000000000..461f070eb62
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c
@@ -0,0 +1,472 @@
1/* linux/arch/arm/plat-s3c24xx/s3c2443-clock.c
2 *
3 * Copyright (c) 2007, 2010 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2443 Clock control suport - common code
7 */
8
9#include <linux/init.h>
10#include <linux/clk.h>
11#include <linux/io.h>
12
13#include <mach/regs-s3c2443-clock.h>
14
15#include <plat/s3c2443.h>
16#include <plat/clock.h>
17#include <plat/clock-clksrc.h>
18#include <plat/cpu.h>
19
20#include <plat/cpu-freq.h>
21
22
23static int s3c2443_gate(void __iomem *reg, struct clk *clk, int enable)
24{
25 u32 ctrlbit = clk->ctrlbit;
26 u32 con = __raw_readl(reg);
27
28 if (enable)
29 con |= ctrlbit;
30 else
31 con &= ~ctrlbit;
32
33 __raw_writel(con, reg);
34 return 0;
35}
36
37int s3c2443_clkcon_enable_h(struct clk *clk, int enable)
38{
39 return s3c2443_gate(S3C2443_HCLKCON, clk, enable);
40}
41
42int s3c2443_clkcon_enable_p(struct clk *clk, int enable)
43{
44 return s3c2443_gate(S3C2443_PCLKCON, clk, enable);
45}
46
47int s3c2443_clkcon_enable_s(struct clk *clk, int enable)
48{
49 return s3c2443_gate(S3C2443_SCLKCON, clk, enable);
50}
51
52/* mpllref is a direct descendant of clk_xtal by default, but it is not
53 * elided as the EPLL can be either sourced by the XTAL or EXTCLK and as
54 * such directly equating the two source clocks is impossible.
55 */
56struct clk clk_mpllref = {
57 .name = "mpllref",
58 .parent = &clk_xtal,
59 .id = -1,
60};
61
62static struct clk *clk_epllref_sources[] = {
63 [0] = &clk_mpllref,
64 [1] = &clk_mpllref,
65 [2] = &clk_xtal,
66 [3] = &clk_ext,
67};
68
69struct clksrc_clk clk_epllref = {
70 .clk = {
71 .name = "epllref",
72 .id = -1,
73 },
74 .sources = &(struct clksrc_sources) {
75 .sources = clk_epllref_sources,
76 .nr_sources = ARRAY_SIZE(clk_epllref_sources),
77 },
78 .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 7 },
79};
80
81/* esysclk
82 *
83 * this is sourced from either the EPLL or the EPLLref clock
84*/
85
86static struct clk *clk_sysclk_sources[] = {
87 [0] = &clk_epllref.clk,
88 [1] = &clk_epll,
89};
90
91struct clksrc_clk clk_esysclk = {
92 .clk = {
93 .name = "esysclk",
94 .parent = &clk_epll,
95 .id = -1,
96 },
97 .sources = &(struct clksrc_sources) {
98 .sources = clk_sysclk_sources,
99 .nr_sources = ARRAY_SIZE(clk_sysclk_sources),
100 },
101 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 6 },
102};
103
104static unsigned long s3c2443_getrate_mdivclk(struct clk *clk)
105{
106 unsigned long parent_rate = clk_get_rate(clk->parent);
107 unsigned long div = __raw_readl(S3C2443_CLKDIV0);
108
109 div &= S3C2443_CLKDIV0_EXTDIV_MASK;
110 div >>= (S3C2443_CLKDIV0_EXTDIV_SHIFT-1); /* x2 */
111
112 return parent_rate / (div + 1);
113}
114
115static struct clk clk_mdivclk = {
116 .name = "mdivclk",
117 .parent = &clk_mpllref,
118 .id = -1,
119 .ops = &(struct clk_ops) {
120 .get_rate = s3c2443_getrate_mdivclk,
121 },
122};
123
124static struct clk *clk_msysclk_sources[] = {
125 [0] = &clk_mpllref,
126 [1] = &clk_mpll,
127 [2] = &clk_mdivclk,
128 [3] = &clk_mpllref,
129};
130
131struct clksrc_clk clk_msysclk = {
132 .clk = {
133 .name = "msysclk",
134 .parent = &clk_xtal,
135 .id = -1,
136 },
137 .sources = &(struct clksrc_sources) {
138 .sources = clk_msysclk_sources,
139 .nr_sources = ARRAY_SIZE(clk_msysclk_sources),
140 },
141 .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 3 },
142};
143
144/* prediv
145 *
146 * this divides the msysclk down to pass to h/p/etc.
147 */
148
149static unsigned long s3c2443_prediv_getrate(struct clk *clk)
150{
151 unsigned long rate = clk_get_rate(clk->parent);
152 unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
153
154 clkdiv0 &= S3C2443_CLKDIV0_PREDIV_MASK;
155 clkdiv0 >>= S3C2443_CLKDIV0_PREDIV_SHIFT;
156
157 return rate / (clkdiv0 + 1);
158}
159
160static struct clk clk_prediv = {
161 .name = "prediv",
162 .id = -1,
163 .parent = &clk_msysclk.clk,
164 .ops = &(struct clk_ops) {
165 .get_rate = s3c2443_prediv_getrate,
166 },
167};
168
169/* usbhost
170 *
171 * usb host bus-clock, usually 48MHz to provide USB bus clock timing
172*/
173
174static struct clksrc_clk clk_usb_bus_host = {
175 .clk = {
176 .name = "usb-bus-host-parent",
177 .id = -1,
178 .parent = &clk_esysclk.clk,
179 .ctrlbit = S3C2443_SCLKCON_USBHOST,
180 .enable = s3c2443_clkcon_enable_s,
181 },
182 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 },
183};
184
185/* common clksrc clocks */
186
187static struct clksrc_clk clksrc_clks[] = {
188 {
189 /* ART baud-rate clock sourced from esysclk via a divisor */
190 .clk = {
191 .name = "uartclk",
192 .id = -1,
193 .parent = &clk_esysclk.clk,
194 },
195 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 },
196 }, {
197 /* camera interface bus-clock, divided down from esysclk */
198 .clk = {
199 .name = "camif-upll", /* same as 2440 name */
200 .id = -1,
201 .parent = &clk_esysclk.clk,
202 .ctrlbit = S3C2443_SCLKCON_CAMCLK,
203 .enable = s3c2443_clkcon_enable_s,
204 },
205 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 26 },
206 }, {
207 .clk = {
208 .name = "display-if",
209 .id = -1,
210 .parent = &clk_esysclk.clk,
211 .ctrlbit = S3C2443_SCLKCON_DISPCLK,
212 .enable = s3c2443_clkcon_enable_s,
213 },
214 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 8, .shift = 16 },
215 },
216};
217
218
219static struct clk init_clocks_off[] = {
220 {
221 .name = "adc",
222 .id = -1,
223 .parent = &clk_p,
224 .enable = s3c2443_clkcon_enable_p,
225 .ctrlbit = S3C2443_PCLKCON_ADC,
226 }, {
227 .name = "i2c",
228 .id = -1,
229 .parent = &clk_p,
230 .enable = s3c2443_clkcon_enable_p,
231 .ctrlbit = S3C2443_PCLKCON_IIC,
232 }
233};
234
235static struct clk init_clocks[] = {
236 {
237 .name = "dma",
238 .id = 0,
239 .parent = &clk_h,
240 .enable = s3c2443_clkcon_enable_h,
241 .ctrlbit = S3C2443_HCLKCON_DMA0,
242 }, {
243 .name = "dma",
244 .id = 1,
245 .parent = &clk_h,
246 .enable = s3c2443_clkcon_enable_h,
247 .ctrlbit = S3C2443_HCLKCON_DMA1,
248 }, {
249 .name = "dma",
250 .id = 2,
251 .parent = &clk_h,
252 .enable = s3c2443_clkcon_enable_h,
253 .ctrlbit = S3C2443_HCLKCON_DMA2,
254 }, {
255 .name = "dma",
256 .id = 3,
257 .parent = &clk_h,
258 .enable = s3c2443_clkcon_enable_h,
259 .ctrlbit = S3C2443_HCLKCON_DMA3,
260 }, {
261 .name = "dma",
262 .id = 4,
263 .parent = &clk_h,
264 .enable = s3c2443_clkcon_enable_h,
265 .ctrlbit = S3C2443_HCLKCON_DMA4,
266 }, {
267 .name = "dma",
268 .id = 5,
269 .parent = &clk_h,
270 .enable = s3c2443_clkcon_enable_h,
271 .ctrlbit = S3C2443_HCLKCON_DMA5,
272 }, {
273 .name = "hsmmc",
274 .id = 0,
275 .parent = &clk_h,
276 .enable = s3c2443_clkcon_enable_h,
277 .ctrlbit = S3C2443_HCLKCON_HSMMC,
278 }, {
279 .name = "gpio",
280 .id = -1,
281 .parent = &clk_p,
282 .enable = s3c2443_clkcon_enable_p,
283 .ctrlbit = S3C2443_PCLKCON_GPIO,
284 }, {
285 .name = "usb-host",
286 .id = -1,
287 .parent = &clk_h,
288 .enable = s3c2443_clkcon_enable_h,
289 .ctrlbit = S3C2443_HCLKCON_USBH,
290 }, {
291 .name = "usb-device",
292 .id = -1,
293 .parent = &clk_h,
294 .enable = s3c2443_clkcon_enable_h,
295 .ctrlbit = S3C2443_HCLKCON_USBD,
296 }, {
297 .name = "lcd",
298 .id = -1,
299 .parent = &clk_h,
300 .enable = s3c2443_clkcon_enable_h,
301 .ctrlbit = S3C2443_HCLKCON_LCDC,
302
303 }, {
304 .name = "timers",
305 .id = -1,
306 .parent = &clk_p,
307 .enable = s3c2443_clkcon_enable_p,
308 .ctrlbit = S3C2443_PCLKCON_PWMT,
309 }, {
310 .name = "cfc",
311 .id = -1,
312 .parent = &clk_h,
313 .enable = s3c2443_clkcon_enable_h,
314 .ctrlbit = S3C2443_HCLKCON_CFC,
315 }, {
316 .name = "ssmc",
317 .id = -1,
318 .parent = &clk_h,
319 .enable = s3c2443_clkcon_enable_h,
320 .ctrlbit = S3C2443_HCLKCON_SSMC,
321 }, {
322 .name = "uart",
323 .id = 0,
324 .parent = &clk_p,
325 .enable = s3c2443_clkcon_enable_p,
326 .ctrlbit = S3C2443_PCLKCON_UART0,
327 }, {
328 .name = "uart",
329 .id = 1,
330 .parent = &clk_p,
331 .enable = s3c2443_clkcon_enable_p,
332 .ctrlbit = S3C2443_PCLKCON_UART1,
333 }, {
334 .name = "uart",
335 .id = 2,
336 .parent = &clk_p,
337 .enable = s3c2443_clkcon_enable_p,
338 .ctrlbit = S3C2443_PCLKCON_UART2,
339 }, {
340 .name = "uart",
341 .id = 3,
342 .parent = &clk_p,
343 .enable = s3c2443_clkcon_enable_p,
344 .ctrlbit = S3C2443_PCLKCON_UART3,
345 }, {
346 .name = "rtc",
347 .id = -1,
348 .parent = &clk_p,
349 .enable = s3c2443_clkcon_enable_p,
350 .ctrlbit = S3C2443_PCLKCON_RTC,
351 }, {
352 .name = "watchdog",
353 .id = -1,
354 .parent = &clk_p,
355 .ctrlbit = S3C2443_PCLKCON_WDT,
356 }, {
357 .name = "ac97",
358 .id = -1,
359 .parent = &clk_p,
360 .ctrlbit = S3C2443_PCLKCON_AC97,
361 }, {
362 .name = "nand",
363 .id = -1,
364 .parent = &clk_h,
365 }, {
366 .name = "usb-bus-host",
367 .id = -1,
368 .parent = &clk_usb_bus_host.clk,
369 }
370};
371
372static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0)
373{
374 clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
375
376 return clkcon0 + 1;
377}
378
379/* EPLLCON compatible enough to get on/off information */
380
381void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll,
382 fdiv_fn get_fdiv)
383{
384 unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
385 unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON);
386 unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
387 struct clk *xtal_clk;
388 unsigned long xtal;
389 unsigned long pll;
390 unsigned long fclk;
391 unsigned long hclk;
392 unsigned long pclk;
393 int ptr;
394
395 xtal_clk = clk_get(NULL, "xtal");
396 xtal = clk_get_rate(xtal_clk);
397 clk_put(xtal_clk);
398
399 pll = get_mpll(mpllcon, xtal);
400 clk_msysclk.clk.rate = pll;
401
402 fclk = pll / get_fdiv(clkdiv0);
403 hclk = s3c2443_prediv_getrate(&clk_prediv);
404 hclk /= s3c2443_get_hdiv(clkdiv0);
405 pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
406
407 s3c24xx_setup_clocks(fclk, hclk, pclk);
408
409 printk("CPU: MPLL %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
410 (mpllcon & S3C2443_PLLCON_OFF) ? "off":"on",
411 print_mhz(pll), print_mhz(fclk),
412 print_mhz(hclk), print_mhz(pclk));
413
414 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_clks); ptr++)
415 s3c_set_clksrc(&clksrc_clks[ptr], true);
416
417 /* ensure usb bus clock is within correct rate of 48MHz */
418
419 if (clk_get_rate(&clk_usb_bus_host.clk) != (48 * 1000 * 1000)) {
420 printk(KERN_INFO "Warning: USB host bus not at 48MHz\n");
421 clk_set_rate(&clk_usb_bus_host.clk, 48*1000*1000);
422 }
423
424 printk("CPU: EPLL %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
425 (epllcon & S3C2443_PLLCON_OFF) ? "off":"on",
426 print_mhz(clk_get_rate(&clk_epll)),
427 print_mhz(clk_get_rate(&clk_usb_bus)));
428}
429
430static struct clk *clks[] __initdata = {
431 &clk_prediv,
432 &clk_mpllref,
433 &clk_mdivclk,
434 &clk_ext,
435 &clk_epll,
436 &clk_usb_bus,
437};
438
439static struct clksrc_clk *clksrcs[] __initdata = {
440 &clk_usb_bus_host,
441 &clk_epllref,
442 &clk_esysclk,
443 &clk_msysclk,
444};
445
446void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
447 fdiv_fn get_fdiv)
448{
449 int ptr;
450
451 /* s3c2443 parents h and p clocks from prediv */
452 clk_h.parent = &clk_prediv;
453 clk_p.parent = &clk_prediv;
454
455 clk_usb_bus.parent = &clk_usb_bus_host.clk;
456 clk_epll.parent = &clk_epllref.clk;
457
458 s3c24xx_register_baseclocks(xtal);
459 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
460
461 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
462 s3c_register_clksrc(clksrcs[ptr], 1);
463
464 s3c_register_clksrc(clksrc_clks, ARRAY_SIZE(clksrc_clks));
465 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
466
467 /* See s3c2443/etc notes on disabling clocks at init time */
468 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
469 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
470
471 s3c2443_common_setup_clocks(get_mpll, get_fdiv);
472}
diff --git a/arch/arm/plat-s3c24xx/setup-i2c.c b/arch/arm/plat-s3c24xx/setup-i2c.c
index 71a6accf114..9e90a7cbd1d 100644
--- a/arch/arm/plat-s3c24xx/setup-i2c.c
+++ b/arch/arm/plat-s3c24xx/setup-i2c.c
@@ -15,12 +15,13 @@
15 15
16struct platform_device; 16struct platform_device;
17 17
18#include <plat/gpio-cfg.h>
18#include <plat/iic.h> 19#include <plat/iic.h>
19#include <mach/hardware.h> 20#include <mach/hardware.h>
20#include <mach/regs-gpio.h> 21#include <mach/regs-gpio.h>
21 22
22void s3c_i2c0_cfg_gpio(struct platform_device *dev) 23void s3c_i2c0_cfg_gpio(struct platform_device *dev)
23{ 24{
24 s3c2410_gpio_cfgpin(S3C2410_GPE(15), S3C2410_GPE15_IICSDA); 25 s3c_gpio_cfgpin(S3C2410_GPE(15), S3C2410_GPE15_IICSDA);
25 s3c2410_gpio_cfgpin(S3C2410_GPE(14), S3C2410_GPE14_IICSCL); 26 s3c_gpio_cfgpin(S3C2410_GPE(14), S3C2410_GPE14_IICSCL);
26} 27}
diff --git a/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c b/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
index da7a61728c1..9793544a6ac 100644
--- a/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
+++ b/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
@@ -21,16 +21,16 @@ void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi,
21 int enable) 21 int enable)
22{ 22{
23 if (enable) { 23 if (enable) {
24 s3c2410_gpio_cfgpin(S3C2410_GPE(13), S3C2410_GPE13_SPICLK0); 24 s3c_gpio_cfgpin(S3C2410_GPE(13), S3C2410_GPE13_SPICLK0);
25 s3c2410_gpio_cfgpin(S3C2410_GPE(12), S3C2410_GPE12_SPIMOSI0); 25 s3c_gpio_cfgpin(S3C2410_GPE(12), S3C2410_GPE12_SPIMOSI0);
26 s3c2410_gpio_cfgpin(S3C2410_GPE(11), S3C2410_GPE11_SPIMISO0); 26 s3c_gpio_cfgpin(S3C2410_GPE(11), S3C2410_GPE11_SPIMISO0);
27 s3c2410_gpio_pullup(S3C2410_GPE(11), 0); 27 s3c2410_gpio_pullup(S3C2410_GPE(11), 0);
28 s3c2410_gpio_pullup(S3C2410_GPE(13), 0); 28 s3c2410_gpio_pullup(S3C2410_GPE(13), 0);
29 } else { 29 } else {
30 s3c2410_gpio_cfgpin(S3C2410_GPE(13), S3C2410_GPIO_INPUT); 30 s3c_gpio_cfgpin(S3C2410_GPE(13), S3C2410_GPIO_INPUT);
31 s3c2410_gpio_cfgpin(S3C2410_GPE(11), S3C2410_GPIO_INPUT); 31 s3c_gpio_cfgpin(S3C2410_GPE(11), S3C2410_GPIO_INPUT);
32 s3c2410_gpio_pullup(S3C2410_GPE(11), 1); 32 s3c_gpio_cfgpull(S3C2410_GPE(11), S3C_GPIO_PULL_NONE);
33 s3c2410_gpio_pullup(S3C2410_GPE(12), 1); 33 s3c_gpio_cfgpull(S3C2410_GPE(12), S3C_GPIO_PULL_NONE);
34 s3c2410_gpio_pullup(S3C2410_GPE(13), 1); 34 s3c_gpio_cfgpull(S3C2410_GPE(13), S3C_GPIO_PULL_NONE);
35 } 35 }
36} 36}
diff --git a/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c b/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c
index 89fcf5308cf..db9e9e477ec 100644
--- a/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c
+++ b/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c
@@ -23,16 +23,16 @@ void s3c24xx_spi_gpiocfg_bus1_gpd8_9_10(struct s3c2410_spi_info *spi,
23 23
24 printk(KERN_INFO "%s(%d)\n", __func__, enable); 24 printk(KERN_INFO "%s(%d)\n", __func__, enable);
25 if (enable) { 25 if (enable) {
26 s3c2410_gpio_cfgpin(S3C2410_GPD(10), S3C2440_GPD10_SPICLK1); 26 s3c_gpio_cfgpin(S3C2410_GPD(10), S3C2440_GPD10_SPICLK1);
27 s3c2410_gpio_cfgpin(S3C2410_GPD(9), S3C2440_GPD9_SPIMOSI1); 27 s3c_gpio_cfgpin(S3C2410_GPD(9), S3C2440_GPD9_SPIMOSI1);
28 s3c2410_gpio_cfgpin(S3C2410_GPD(8), S3C2440_GPD8_SPIMISO1); 28 s3c_gpio_cfgpin(S3C2410_GPD(8), S3C2440_GPD8_SPIMISO1);
29 s3c2410_gpio_pullup(S3C2410_GPD(10), 0); 29 s3c2410_gpio_pullup(S3C2410_GPD(10), 0);
30 s3c2410_gpio_pullup(S3C2410_GPD(9), 0); 30 s3c2410_gpio_pullup(S3C2410_GPD(9), 0);
31 } else { 31 } else {
32 s3c2410_gpio_cfgpin(S3C2410_GPD(8), S3C2410_GPIO_INPUT); 32 s3c_gpio_cfgpin(S3C2410_GPD(8), S3C2410_GPIO_INPUT);
33 s3c2410_gpio_cfgpin(S3C2410_GPD(9), S3C2410_GPIO_INPUT); 33 s3c_gpio_cfgpin(S3C2410_GPD(9), S3C2410_GPIO_INPUT);
34 s3c2410_gpio_pullup(S3C2410_GPD(10), 1); 34 s3c_gpio_cfgpull(S3C2410_GPD(10), S3C_GPIO_PULL_NONE);
35 s3c2410_gpio_pullup(S3C2410_GPD(9), 1); 35 s3c_gpio_cfgpull(S3C2410_GPD(9), S3C_GPIO_PULL_NONE);
36 s3c2410_gpio_pullup(S3C2410_GPD(8), 1); 36 s3c_gpio_cfgpull(S3C2410_GPD(8), S3C_GPIO_PULL_NONE);
37 } 37 }
38} 38}
diff --git a/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c b/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
index 86b9edc6741..8ea663a438b 100644
--- a/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
+++ b/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
@@ -21,16 +21,16 @@ void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi,
21 int enable) 21 int enable)
22{ 22{
23 if (enable) { 23 if (enable) {
24 s3c2410_gpio_cfgpin(S3C2410_GPG(7), S3C2410_GPG7_SPICLK1); 24 s3c_gpio_cfgpin(S3C2410_GPG(7), S3C2410_GPG7_SPICLK1);
25 s3c2410_gpio_cfgpin(S3C2410_GPG(6), S3C2410_GPG6_SPIMOSI1); 25 s3c_gpio_cfgpin(S3C2410_GPG(6), S3C2410_GPG6_SPIMOSI1);
26 s3c2410_gpio_cfgpin(S3C2410_GPG(5), S3C2410_GPG5_SPIMISO1); 26 s3c_gpio_cfgpin(S3C2410_GPG(5), S3C2410_GPG5_SPIMISO1);
27 s3c2410_gpio_pullup(S3C2410_GPG(5), 0); 27 s3c2410_gpio_pullup(S3C2410_GPG(5), 0);
28 s3c2410_gpio_pullup(S3C2410_GPG(6), 0); 28 s3c2410_gpio_pullup(S3C2410_GPG(6), 0);
29 } else { 29 } else {
30 s3c2410_gpio_cfgpin(S3C2410_GPG(7), S3C2410_GPIO_INPUT); 30 s3c_gpio_cfgpin(S3C2410_GPG(7), S3C2410_GPIO_INPUT);
31 s3c2410_gpio_cfgpin(S3C2410_GPG(5), S3C2410_GPIO_INPUT); 31 s3c_gpio_cfgpin(S3C2410_GPG(5), S3C2410_GPIO_INPUT);
32 s3c2410_gpio_pullup(S3C2410_GPG(5), 1); 32 s3c_gpio_cfgpull(S3C2410_GPG(5), S3C_GPIO_PULL_NONE);
33 s3c2410_gpio_pullup(S3C2410_GPG(6), 1); 33 s3c_gpio_cfgpull(S3C2410_GPG(6), S3C_GPIO_PULL_NONE);
34 s3c2410_gpio_pullup(S3C2410_GPG(7), 1); 34 s3c_gpio_cfgpull(S3C2410_GPG(7), S3C_GPIO_PULL_NONE);
35 } 35 }
36} 36}
diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c
index 1b25c9d8c40..8bf79f3efdf 100644
--- a/arch/arm/plat-samsung/clock.c
+++ b/arch/arm/plat-samsung/clock.c
@@ -376,6 +376,21 @@ void __init s3c_register_clocks(struct clk *clkp, int nr_clks)
376 } 376 }
377} 377}
378 378
379/**
380 * s3c_disable_clocks() - disable an array of clocks
381 * @clkp: Pointer to the first clock in the array.
382 * @nr_clks: Number of clocks to register.
383 *
384 * for internal use only at initialisation time. disable the clocks in the
385 * @clkp array.
386 */
387
388void __init s3c_disable_clocks(struct clk *clkp, int nr_clks)
389{
390 for (; nr_clks > 0; nr_clks--, clkp++)
391 (clkp->enable)(clkp, 0);
392}
393
379/* initalise all the clocks */ 394/* initalise all the clocks */
380 395
381int __init s3c24xx_register_baseclocks(unsigned long xtal) 396int __init s3c24xx_register_baseclocks(unsigned long xtal)
diff --git a/arch/arm/plat-samsung/gpio-config.c b/arch/arm/plat-samsung/gpio-config.c
index 44a84e89654..3282db360fa 100644
--- a/arch/arm/plat-samsung/gpio-config.c
+++ b/arch/arm/plat-samsung/gpio-config.c
@@ -1,7 +1,7 @@
1/* linux/arch/arm/plat-s3c/gpio-config.c 1/* linux/arch/arm/plat-s3c/gpio-config.c
2 * 2 *
3 * Copyright 2008 Openmoko, Inc. 3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics 4 * Copyright 2008-2010 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk> 5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/ 6 * http://armlinux.simtec.co.uk/
7 * 7 *
@@ -41,6 +41,26 @@ int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
41} 41}
42EXPORT_SYMBOL(s3c_gpio_cfgpin); 42EXPORT_SYMBOL(s3c_gpio_cfgpin);
43 43
44unsigned s3c_gpio_getcfg(unsigned int pin)
45{
46 struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
47 unsigned long flags;
48 unsigned ret = 0;
49 int offset;
50
51 if (chip) {
52 offset = pin - chip->chip.base;
53
54 local_irq_save(flags);
55 ret = s3c_gpio_do_getcfg(chip, offset);
56 local_irq_restore(flags);
57 }
58
59 return ret;
60}
61EXPORT_SYMBOL(s3c_gpio_getcfg);
62
63
44int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull) 64int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull)
45{ 65{
46 struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); 66 struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
@@ -61,8 +81,8 @@ int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull)
61EXPORT_SYMBOL(s3c_gpio_setpull); 81EXPORT_SYMBOL(s3c_gpio_setpull);
62 82
63#ifdef CONFIG_S3C_GPIO_CFG_S3C24XX 83#ifdef CONFIG_S3C_GPIO_CFG_S3C24XX
64int s3c_gpio_setcfg_s3c24xx_banka(struct s3c_gpio_chip *chip, 84int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
65 unsigned int off, unsigned int cfg) 85 unsigned int off, unsigned int cfg)
66{ 86{
67 void __iomem *reg = chip->base; 87 void __iomem *reg = chip->base;
68 unsigned int shift = off; 88 unsigned int shift = off;
@@ -87,6 +107,19 @@ int s3c_gpio_setcfg_s3c24xx_banka(struct s3c_gpio_chip *chip,
87 return 0; 107 return 0;
88} 108}
89 109
110unsigned s3c_gpio_getcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
111 unsigned int off)
112{
113 u32 con;
114
115 con = __raw_readl(chip->base);
116 con >>= off;
117 con &= 1;
118 con++;
119
120 return S3C_GPIO_SFN(con);
121}
122
90int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip, 123int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip,
91 unsigned int off, unsigned int cfg) 124 unsigned int off, unsigned int cfg)
92{ 125{
@@ -109,6 +142,19 @@ int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip,
109 142
110 return 0; 143 return 0;
111} 144}
145
146unsigned int s3c_gpio_getcfg_s3c24xx(struct s3c_gpio_chip *chip,
147 unsigned int off)
148{
149 u32 con;
150
151 con = __raw_readl(chip->base);
152 con >>= off * 2;
153 con &= 3;
154
155 /* this conversion works for IN and OUT as well as special mode */
156 return S3C_GPIO_SPECIAL(con);
157}
112#endif 158#endif
113 159
114#ifdef CONFIG_S3C_GPIO_CFG_S3C64XX 160#ifdef CONFIG_S3C_GPIO_CFG_S3C64XX
@@ -134,6 +180,25 @@ int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
134 180
135 return 0; 181 return 0;
136} 182}
183
184unsigned s3c_gpio_getcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
185 unsigned int off)
186{
187 void __iomem *reg = chip->base;
188 unsigned int shift = (off & 7) * 4;
189 u32 con;
190
191 if (off < 8 && chip->chip.ngpio > 8)
192 reg -= 4;
193
194 con = __raw_readl(reg);
195 con >>= shift;
196 con &= 0xf;
197
198 /* this conversion works for IN and OUT as well as special mode */
199 return S3C_GPIO_SPECIAL(con);
200}
201
137#endif /* CONFIG_S3C_GPIO_CFG_S3C64XX */ 202#endif /* CONFIG_S3C_GPIO_CFG_S3C64XX */
138 203
139#ifdef CONFIG_S3C_GPIO_PULL_UPDOWN 204#ifdef CONFIG_S3C_GPIO_PULL_UPDOWN
@@ -164,3 +229,35 @@ s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip,
164 return (__force s3c_gpio_pull_t)pup; 229 return (__force s3c_gpio_pull_t)pup;
165} 230}
166#endif 231#endif
232
233#ifdef CONFIG_S3C_GPIO_PULL_UP
234int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip,
235 unsigned int off, s3c_gpio_pull_t pull)
236{
237 void __iomem *reg = chip->base + 0x08;
238 u32 pup = __raw_readl(reg);
239
240 pup = __raw_readl(reg);
241
242 if (pup == S3C_GPIO_PULL_UP)
243 pup &= ~(1 << off);
244 else if (pup == S3C_GPIO_PULL_NONE)
245 pup |= (1 << off);
246 else
247 return -EINVAL;
248
249 __raw_writel(pup, reg);
250 return 0;
251}
252
253s3c_gpio_pull_t s3c_gpio_getpull_1up(struct s3c_gpio_chip *chip,
254 unsigned int off)
255{
256 void __iomem *reg = chip->base + 0x08;
257 u32 pup = __raw_readl(reg);
258
259 pup &= (1 << off);
260 return pup ? S3C_GPIO_PULL_NONE : S3C_GPIO_PULL_UP;
261}
262#endif /* CONFIG_S3C_GPIO_PULL_UP */
263
diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h
index 60b62692ac7..12caf48a6bd 100644
--- a/arch/arm/plat-samsung/include/plat/clock.h
+++ b/arch/arm/plat-samsung/include/plat/clock.h
@@ -91,6 +91,7 @@ extern int s3c24xx_register_clock(struct clk *clk);
91extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks); 91extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks);
92 92
93extern void s3c_register_clocks(struct clk *clk, int nr_clks); 93extern void s3c_register_clocks(struct clk *clk, int nr_clks);
94extern void s3c_disable_clocks(struct clk *clkp, int nr_clks);
94 95
95extern int s3c24xx_register_baseclocks(unsigned long xtal); 96extern int s3c24xx_register_baseclocks(unsigned long xtal);
96 97
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index d316b4a579f..5dbeb7991e6 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -73,6 +73,7 @@ extern struct sys_timer s3c24xx_timer;
73extern struct sysdev_class s3c2410_sysclass; 73extern struct sysdev_class s3c2410_sysclass;
74extern struct sysdev_class s3c2410a_sysclass; 74extern struct sysdev_class s3c2410a_sysclass;
75extern struct sysdev_class s3c2412_sysclass; 75extern struct sysdev_class s3c2412_sysclass;
76extern struct sysdev_class s3c2416_sysclass;
76extern struct sysdev_class s3c2440_sysclass; 77extern struct sysdev_class s3c2440_sysclass;
77extern struct sysdev_class s3c2442_sysclass; 78extern struct sysdev_class s3c2442_sysclass;
78extern struct sysdev_class s3c2443_sysclass; 79extern struct sysdev_class s3c2443_sysclass;
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
index dda19da037a..3e21c75feef 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
@@ -30,6 +30,12 @@ static inline int s3c_gpio_do_setcfg(struct s3c_gpio_chip *chip,
30 return (chip->config->set_config)(chip, off, config); 30 return (chip->config->set_config)(chip, off, config);
31} 31}
32 32
33static inline unsigned s3c_gpio_do_getcfg(struct s3c_gpio_chip *chip,
34 unsigned int off)
35{
36 return (chip->config->get_config)(chip, off);
37}
38
33static inline int s3c_gpio_do_setpull(struct s3c_gpio_chip *chip, 39static inline int s3c_gpio_do_setpull(struct s3c_gpio_chip *chip,
34 unsigned int off, s3c_gpio_pull_t pull) 40 unsigned int off, s3c_gpio_pull_t pull)
35{ 41{
@@ -53,6 +59,18 @@ extern int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip,
53 unsigned int off, unsigned int cfg); 59 unsigned int off, unsigned int cfg);
54 60
55/** 61/**
62 * s3c_gpio_getcfg_s3c24xx - S3C24XX style GPIO configuration read.
63 * @chip: The gpio chip that is being configured.
64 * @off: The offset for the GPIO being configured.
65 *
66 * The reverse of s3c_gpio_setcfg_s3c24xx(). Will return a value whicg
67 * could be directly passed back to s3c_gpio_setcfg_s3c24xx(), from the
68 * S3C_GPIO_SPECIAL() macro.
69 */
70unsigned int s3c_gpio_getcfg_s3c24xx(struct s3c_gpio_chip *chip,
71 unsigned int off);
72
73/**
56 * s3c_gpio_setcfg_s3c24xx_a - S3C24XX style GPIO configuration (Bank A) 74 * s3c_gpio_setcfg_s3c24xx_a - S3C24XX style GPIO configuration (Bank A)
57 * @chip: The gpio chip that is being configured. 75 * @chip: The gpio chip that is being configured.
58 * @off: The offset for the GPIO being configured. 76 * @off: The offset for the GPIO being configured.
@@ -65,6 +83,21 @@ extern int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip,
65extern int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip, 83extern int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
66 unsigned int off, unsigned int cfg); 84 unsigned int off, unsigned int cfg);
67 85
86
87/**
88 * s3c_gpio_getcfg_s3c24xx_a - S3C24XX style GPIO configuration read (Bank A)
89 * @chip: The gpio chip that is being configured.
90 * @off: The offset for the GPIO being configured.
91 *
92 * The reverse of s3c_gpio_setcfg_s3c24xx_a() turning an GPIO into a usable
93 * GPIO configuration value.
94 *
95 * @sa s3c_gpio_getcfg_s3c24xx
96 * @sa s3c_gpio_getcfg_s3c64xx_4bit
97 */
98extern unsigned s3c_gpio_getcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
99 unsigned int off);
100
68/** 101/**
69 * s3c_gpio_setcfg_s3c64xx_4bit - S3C64XX 4bit single register GPIO config. 102 * s3c_gpio_setcfg_s3c64xx_4bit - S3C64XX 4bit single register GPIO config.
70 * @chip: The gpio chip that is being configured. 103 * @chip: The gpio chip that is being configured.
@@ -85,6 +118,20 @@ extern int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
85 unsigned int off, unsigned int cfg); 118 unsigned int off, unsigned int cfg);
86 119
87 120
121/**
122 * s3c_gpio_getcfg_s3c64xx_4bit - S3C64XX 4bit single register GPIO config read.
123 * @chip: The gpio chip that is being configured.
124 * @off: The offset for the GPIO being configured.
125 *
126 * The reverse of s3c_gpio_setcfg_s3c64xx_4bit(), turning a gpio configuration
127 * register setting into a value the software can use, such as could be passed
128 * to s3c_gpio_setcfg_s3c64xx_4bit().
129 *
130 * @sa s3c_gpio_getcfg_s3c24xx
131 */
132extern unsigned s3c_gpio_getcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
133 unsigned int off);
134
88/* Pull-{up,down} resistor controls. 135/* Pull-{up,down} resistor controls.
89 * 136 *
90 * S3C2410,S3C2440,S3C24A0 = Pull-UP, 137 * S3C2410,S3C2440,S3C24A0 = Pull-UP,
@@ -146,6 +193,17 @@ extern s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip,
146 unsigned int off); 193 unsigned int off);
147 194
148/** 195/**
196 * s3c_gpio_getpull_1up() - Get configuration for choice of up or none
197 * @chip: The gpio chip that the GPIO pin belongs to
198 * @off: The offset to the pin to get the configuration of.
199 *
200 * This helper function reads the state of the pull-up resistor for the
201 * given GPIO in the same case as s3c_gpio_setpull_1up.
202*/
203extern s3c_gpio_pull_t s3c_gpio_getpull_1up(struct s3c_gpio_chip *chip,
204 unsigned int off);
205
206/**
149 * s3c_gpio_setpull_s3c2443() - Pull configuration for s3c2443. 207 * s3c_gpio_setpull_s3c2443() - Pull configuration for s3c2443.
150 * @chip: The gpio chip that is being configured. 208 * @chip: The gpio chip that is being configured.
151 * @off: The offset for the GPIO being configured. 209 * @off: The offset for the GPIO being configured.
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg.h b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
index 29cd6a86cad..8d01e853df3 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-cfg.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
@@ -77,6 +77,17 @@ struct s3c_gpio_cfg {
77 */ 77 */
78extern int s3c_gpio_cfgpin(unsigned int pin, unsigned int to); 78extern int s3c_gpio_cfgpin(unsigned int pin, unsigned int to);
79 79
80/**
81 * s3c_gpio_getcfg - Read the current function for a GPIO pin
82 * @pin: The pin to read the configuration value for.
83 *
84 * Read the configuration state of the given @pin, returning a value that
85 * could be passed back to s3c_gpio_cfgpin().
86 *
87 * @sa s3c_gpio_cfgpin
88 */
89extern unsigned s3c_gpio_getcfg(unsigned int pin);
90
80/* Define values for the pull-{up,down} available for each gpio pin. 91/* Define values for the pull-{up,down} available for each gpio pin.
81 * 92 *
82 * These values control the state of the weak pull-{up,down} resistors 93 * These values control the state of the weak pull-{up,down} resistors
diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h
index 49ff406a706..f0584f26d49 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-core.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-core.h
@@ -108,6 +108,9 @@ extern void samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip,
108extern void samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip); 108extern void samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip);
109extern void samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip); 109extern void samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip);
110 110
111/* exported for core SoC support to change */
112extern struct s3c_gpio_cfg s3c24xx_gpiocfg_default;
113
111#ifdef CONFIG_S3C_GPIO_TRACK 114#ifdef CONFIG_S3C_GPIO_TRACK
112extern struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END]; 115extern struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END];
113 116
diff --git a/arch/arm/plat-samsung/include/plat/pll6553x.h b/arch/arm/plat-samsung/include/plat/pll6553x.h
new file mode 100644
index 00000000000..b8b7e1d884f
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/pll6553x.h
@@ -0,0 +1,51 @@
1/* arch/arm/plat-samsung/include/plat/pll6553x.h
2 * partially from arch/arm/mach-s3c64xx/include/mach/pll.h
3 *
4 * Copyright 2008 Openmoko, Inc.
5 * Copyright 2008 Simtec Electronics
6 * Ben Dooks <ben@simtec.co.uk>
7 * http://armlinux.simtec.co.uk/
8 *
9 * Samsung PLL6553x PLL code
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14*/
15
16/* S3C6400 and compatible (S3C2416, etc.) EPLL code */
17
18#define PLL6553X_MDIV_MASK ((1 << (23-16)) - 1)
19#define PLL6553X_PDIV_MASK ((1 << (13-8)) - 1)
20#define PLL6553X_SDIV_MASK ((1 << (2-0)) - 1)
21#define PLL6553X_MDIV_SHIFT (16)
22#define PLL6553X_PDIV_SHIFT (8)
23#define PLL6553X_SDIV_SHIFT (0)
24#define PLL6553X_KDIV_MASK (0xffff)
25
26static inline unsigned long s3c_get_pll6553x(unsigned long baseclk,
27 u32 pll0, u32 pll1)
28{
29 unsigned long result;
30 u32 mdiv, pdiv, sdiv, kdiv;
31 u64 tmp;
32
33 mdiv = (pll0 >> PLL6553X_MDIV_SHIFT) & PLL6553X_MDIV_MASK;
34 pdiv = (pll0 >> PLL6553X_PDIV_SHIFT) & PLL6553X_PDIV_MASK;
35 sdiv = (pll0 >> PLL6553X_SDIV_SHIFT) & PLL6553X_SDIV_MASK;
36 kdiv = pll1 & PLL6553X_KDIV_MASK;
37
38 /* We need to multiple baseclk by mdiv (the integer part) and kdiv
39 * which is in 2^16ths, so shift mdiv up (does not overflow) and
40 * add kdiv before multiplying. The use of tmp is to avoid any
41 * overflows before shifting bac down into result when multipling
42 * by the mdiv and kdiv pair.
43 */
44
45 tmp = baseclk;
46 tmp *= (mdiv << 16) + kdiv;
47 do_div(tmp, (pdiv << sdiv));
48 result = tmp >> 16;
49
50 return result;
51}
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index f55c49475a8..5f3f03df92e 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -518,12 +518,13 @@ config SERIAL_S3C2412
518 Serial port support for the Samsung S3C2412 and S3C2413 SoC 518 Serial port support for the Samsung S3C2412 and S3C2413 SoC
519 519
520config SERIAL_S3C2440 520config SERIAL_S3C2440
521 tristate "Samsung S3C2440/S3C2442 Serial port support" 521 tristate "Samsung S3C2440/S3C2442/S3C2416 Serial port support"
522 depends on SERIAL_SAMSUNG && (CPU_S3C2440 || CPU_S3C2442) 522 depends on SERIAL_SAMSUNG && (CPU_S3C2440 || CPU_S3C2442 || CPU_S3C2416)
523 default y if CPU_S3C2440 523 default y if CPU_S3C2440
524 default y if CPU_S3C2442 524 default y if CPU_S3C2442
525 select SERIAL_SAMSUNG_UARTS_4 if CPU_S3C2416
525 help 526 help
526 Serial port support for the Samsung S3C2440 and S3C2442 SoC 527 Serial port support for the Samsung S3C2440, S3C2416 and S3C2442 SoC
527 528
528config SERIAL_S3C24A0 529config SERIAL_S3C24A0
529 tristate "Samsung S3C24A0 Serial port support" 530 tristate "Samsung S3C24A0 Serial port support"
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-22 11:44:29 -0400