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authorTony Lindgren <tony@atomide.com>2009-10-15 21:16:10 -0400
committerTony Lindgren <tony@atomide.com>2009-10-15 21:16:10 -0400
commita2bb28a0dbcc1370104a543d25eb28aab81d4a91 (patch)
treeaf81c8fe399a5e828b584617ffe6ee3df9f6fc07
parent012abeea669ea49636cf952d13298bb68654146a (diff)
parentf8631e7bba34d46d6ccea4cd90f7a0482770ff70 (diff)
Merge branch 'omap7xx-fortony-rc3' of git://robotfuzz.com/linwizard-kernel into omap7xx
Diffstat
-rw-r--r--arch/arm/mach-omap1/board-fsample.c18
-rw-r--r--arch/arm/mach-omap1/board-perseus2.c18
-rw-r--r--arch/arm/mach-omap1/clock.c24
-rw-r--r--arch/arm/mach-omap1/io.c45
-rw-r--r--arch/arm/mach-omap1/irq.c32
-rw-r--r--arch/arm/mach-omap1/mcbsp.c32
-rw-r--r--arch/arm/mach-omap1/mux.c70
-rw-r--r--arch/arm/mach-omap1/pm.c100
-rw-r--r--arch/arm/mach-omap1/pm.h53
-rw-r--r--arch/arm/mach-omap1/serial.c13
-rw-r--r--arch/arm/mach-omap1/sleep.S22
-rw-r--r--arch/arm/plat-omap/devices.c22
-rw-r--r--arch/arm/plat-omap/gpio.c227
-rw-r--r--arch/arm/plat-omap/include/mach/entry-macro.S8
-rw-r--r--arch/arm/plat-omap/include/mach/hardware.h2
-rw-r--r--arch/arm/plat-omap/include/mach/irqs.h229
-rw-r--r--arch/arm/plat-omap/include/mach/mcbsp.h6
-rw-r--r--arch/arm/plat-omap/include/mach/mux.h100
-rw-r--r--arch/arm/plat-omap/include/mach/omap7xx.h104
-rw-r--r--arch/arm/plat-omap/include/mach/uncompress.h3
-rw-r--r--arch/arm/plat-omap/io.c14
-rw-r--r--arch/arm/plat-omap/usb.c10
-rw-r--r--drivers/spi/omap_uwire.c8
23 files changed, 480 insertions, 680 deletions
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
index a7ead1b9322..74720e65f11 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -107,7 +107,7 @@ static struct resource smc91x_resources[] = {
107 .flags = IORESOURCE_MEM, 107 .flags = IORESOURCE_MEM,
108 }, 108 },
109 [1] = { 109 [1] = {
110 .start = INT_730_MPU_EXT_NIRQ, 110 .start = INT_7XX_MPU_EXT_NIRQ,
111 .end = 0, 111 .end = 0,
112 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, 112 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
113 }, 113 },
@@ -196,8 +196,8 @@ static struct platform_device smc91x_device = {
196 196
197static struct resource kp_resources[] = { 197static struct resource kp_resources[] = {
198 [0] = { 198 [0] = {
199 .start = INT_730_MPUIO_KEYPAD, 199 .start = INT_7XX_MPUIO_KEYPAD,
200 .end = INT_730_MPUIO_KEYPAD, 200 .end = INT_7XX_MPUIO_KEYPAD,
201 .flags = IORESOURCE_IRQ, 201 .flags = IORESOURCE_IRQ,
202 }, 202 },
203}; 203};
@@ -309,7 +309,7 @@ static void __init omap_fsample_map_io(void)
309 /* 309 /*
310 * Hold GSM Reset until needed 310 * Hold GSM Reset until needed
311 */ 311 */
312 omap_writew(omap_readw(OMAP730_DSP_M_CTL) & ~1, OMAP730_DSP_M_CTL); 312 omap_writew(omap_readw(OMAP7XX_DSP_M_CTL) & ~1, OMAP7XX_DSP_M_CTL);
313 313
314 /* 314 /*
315 * UARTs -> done automagically by 8250 driver 315 * UARTs -> done automagically by 8250 driver
@@ -320,21 +320,21 @@ static void __init omap_fsample_map_io(void)
320 */ 320 */
321 321
322 /* Flash: CS0 timings setup */ 322 /* Flash: CS0 timings setup */
323 omap_writel(0x0000fff3, OMAP730_FLASH_CFG_0); 323 omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_0);
324 omap_writel(0x00000088, OMAP730_FLASH_ACFG_0); 324 omap_writel(0x00000088, OMAP7XX_FLASH_ACFG_0);
325 325
326 /* 326 /*
327 * Ethernet support through the debug board 327 * Ethernet support through the debug board
328 * CS1 timings setup 328 * CS1 timings setup
329 */ 329 */
330 omap_writel(0x0000fff3, OMAP730_FLASH_CFG_1); 330 omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_1);
331 omap_writel(0x00000000, OMAP730_FLASH_ACFG_1); 331 omap_writel(0x00000000, OMAP7XX_FLASH_ACFG_1);
332 332
333 /* 333 /*
334 * Configure MPU_EXT_NIRQ IO in IO_CONF9 register, 334 * Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
335 * It is used as the Ethernet controller interrupt 335 * It is used as the Ethernet controller interrupt
336 */ 336 */
337 omap_writel(omap_readl(OMAP730_IO_CONF_9) & 0x1FFFFFFF, OMAP730_IO_CONF_9); 337 omap_writel(omap_readl(OMAP7XX_IO_CONF_9) & 0x1FFFFFFF, OMAP7XX_IO_CONF_9);
338} 338}
339 339
340MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample") 340MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample")
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
index 83406699f31..2f897cf2350 100644
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ b/arch/arm/mach-omap1/board-perseus2.c
@@ -74,7 +74,7 @@ static struct resource smc91x_resources[] = {
74 .flags = IORESOURCE_MEM, 74 .flags = IORESOURCE_MEM,
75 }, 75 },
76 [1] = { 76 [1] = {
77 .start = INT_730_MPU_EXT_NIRQ, 77 .start = INT_7XX_MPU_EXT_NIRQ,
78 .end = 0, 78 .end = 0,
79 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, 79 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
80 }, 80 },
@@ -163,8 +163,8 @@ static struct platform_device smc91x_device = {
163 163
164static struct resource kp_resources[] = { 164static struct resource kp_resources[] = {
165 [0] = { 165 [0] = {
166 .start = INT_730_MPUIO_KEYPAD, 166 .start = INT_7XX_MPUIO_KEYPAD,
167 .end = INT_730_MPUIO_KEYPAD, 167 .end = INT_7XX_MPUIO_KEYPAD,
168 .flags = IORESOURCE_IRQ, 168 .flags = IORESOURCE_IRQ,
169 }, 169 },
170}; 170};
@@ -270,7 +270,7 @@ static void __init omap_perseus2_map_io(void)
270 /* 270 /*
271 * Hold GSM Reset until needed 271 * Hold GSM Reset until needed
272 */ 272 */
273 omap_writew(omap_readw(OMAP730_DSP_M_CTL) & ~1, OMAP730_DSP_M_CTL); 273 omap_writew(omap_readw(OMAP7XX_DSP_M_CTL) & ~1, OMAP7XX_DSP_M_CTL);
274 274
275 /* 275 /*
276 * UARTs -> done automagically by 8250 driver 276 * UARTs -> done automagically by 8250 driver
@@ -281,21 +281,21 @@ static void __init omap_perseus2_map_io(void)
281 */ 281 */
282 282
283 /* Flash: CS0 timings setup */ 283 /* Flash: CS0 timings setup */
284 omap_writel(0x0000fff3, OMAP730_FLASH_CFG_0); 284 omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_0);
285 omap_writel(0x00000088, OMAP730_FLASH_ACFG_0); 285 omap_writel(0x00000088, OMAP7XX_FLASH_ACFG_0);
286 286
287 /* 287 /*
288 * Ethernet support through the debug board 288 * Ethernet support through the debug board
289 * CS1 timings setup 289 * CS1 timings setup
290 */ 290 */
291 omap_writel(0x0000fff3, OMAP730_FLASH_CFG_1); 291 omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_1);
292 omap_writel(0x00000000, OMAP730_FLASH_ACFG_1); 292 omap_writel(0x00000000, OMAP7XX_FLASH_ACFG_1);
293 293
294 /* 294 /*
295 * Configure MPU_EXT_NIRQ IO in IO_CONF9 register, 295 * Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
296 * It is used as the Ethernet controller interrupt 296 * It is used as the Ethernet controller interrupt
297 */ 297 */
298 omap_writel(omap_readl(OMAP730_IO_CONF_9) & 0x1FFFFFFF, OMAP730_IO_CONF_9); 298 omap_writel(omap_readl(OMAP7XX_IO_CONF_9) & 0x1FFFFFFF, OMAP7XX_IO_CONF_9);
299} 299}
300 300
301MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2") 301MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2")
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index 436eed22801..5f77b8355b4 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -69,13 +69,13 @@ struct omap_clk {
69 } 69 }
70 70
71#define CK_310 (1 << 0) 71#define CK_310 (1 << 0)
72#define CK_730 (1 << 1) 72#define CK_7XX (1 << 1)
73#define CK_1510 (1 << 2) 73#define CK_1510 (1 << 2)
74#define CK_16XX (1 << 3) 74#define CK_16XX (1 << 3)
75 75
76static struct omap_clk omap_clks[] = { 76static struct omap_clk omap_clks[] = {
77 /* non-ULPD clocks */ 77 /* non-ULPD clocks */
78 CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310), 78 CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310 | CK_7XX),
79 CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310), 79 CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310),
80 /* CK_GEN1 clocks */ 80 /* CK_GEN1 clocks */
81 CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX), 81 CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX),
@@ -83,7 +83,7 @@ static struct omap_clk omap_clks[] = {
83 CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310), 83 CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310),
84 CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), 84 CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
85 CLK(NULL, "arm_gpio_ck", &arm_gpio_ck, CK_1510 | CK_310), 85 CLK(NULL, "arm_gpio_ck", &arm_gpio_ck, CK_1510 | CK_310),
86 CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310), 86 CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
87 CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310), 87 CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
88 CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310), 88 CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
89 CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX), 89 CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX),
@@ -97,7 +97,7 @@ static struct omap_clk omap_clks[] = {
97 CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), 97 CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
98 CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX | CK_1510 | CK_310), 98 CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX | CK_1510 | CK_310),
99 /* CK_GEN3 clocks */ 99 /* CK_GEN3 clocks */
100 CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_730), 100 CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
101 CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310), 101 CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310),
102 CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX), 102 CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX),
103 CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX), 103 CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX),
@@ -108,7 +108,7 @@ static struct omap_clk omap_clks[] = {
108 CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310), 108 CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310),
109 CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX), 109 CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX),
110 CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX), 110 CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX),
111 CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_730), 111 CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_7XX),
112 CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310), 112 CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310),
113 /* ULPD clocks */ 113 /* ULPD clocks */
114 CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310), 114 CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310),
@@ -398,7 +398,7 @@ static int omap1_select_table_rate(struct clk * clk, unsigned long rate)
398 * Reprogramming the DPLL is tricky, it must be done from SRAM. 398 * Reprogramming the DPLL is tricky, it must be done from SRAM.
399 * (on 730, bit 13 must always be 1) 399 * (on 730, bit 13 must always be 1)
400 */ 400 */
401 if (cpu_is_omap730()) 401 if (cpu_is_omap7xx())
402 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000); 402 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000);
403 else 403 else
404 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val); 404 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
@@ -783,8 +783,8 @@ int __init omap1_clk_init(void)
783 cpu_mask |= CK_16XX; 783 cpu_mask |= CK_16XX;
784 if (cpu_is_omap1510()) 784 if (cpu_is_omap1510())
785 cpu_mask |= CK_1510; 785 cpu_mask |= CK_1510;
786 if (cpu_is_omap730()) 786 if (cpu_is_omap7xx())
787 cpu_mask |= CK_730; 787 cpu_mask |= CK_7XX;
788 if (cpu_is_omap310()) 788 if (cpu_is_omap310())
789 cpu_mask |= CK_310; 789 cpu_mask |= CK_310;
790 790
@@ -800,7 +800,7 @@ int __init omap1_clk_init(void)
800 crystal_type = info->system_clock_type; 800 crystal_type = info->system_clock_type;
801 } 801 }
802 802
803#if defined(CONFIG_ARCH_OMAP730) 803#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
804 ck_ref.rate = 13000000; 804 ck_ref.rate = 13000000;
805#elif defined(CONFIG_ARCH_OMAP16XX) 805#elif defined(CONFIG_ARCH_OMAP16XX)
806 if (crystal_type == 2) 806 if (crystal_type == 2)
@@ -847,7 +847,7 @@ int __init omap1_clk_init(void)
847 printk(KERN_ERR "System frequencies not set. Check your config.\n"); 847 printk(KERN_ERR "System frequencies not set. Check your config.\n");
848 /* Guess sane values (60MHz) */ 848 /* Guess sane values (60MHz) */
849 omap_writew(0x2290, DPLL_CTL); 849 omap_writew(0x2290, DPLL_CTL);
850 omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL); 850 omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL);
851 ck_dpll1.rate = 60000000; 851 ck_dpll1.rate = 60000000;
852 } 852 }
853#endif 853#endif
@@ -862,7 +862,7 @@ int __init omap1_clk_init(void)
862 862
863#if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE) 863#if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
864 /* Select slicer output as OMAP input clock */ 864 /* Select slicer output as OMAP input clock */
865 omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL); 865 omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, OMAP7XX_PCC_UPLD_CTRL);
866#endif 866#endif
867 867
868 /* Amstrad Delta wants BCLK high when inactive */ 868 /* Amstrad Delta wants BCLK high when inactive */
@@ -873,7 +873,7 @@ int __init omap1_clk_init(void)
873 873
874 /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */ 874 /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
875 /* (on 730, bit 13 must not be cleared) */ 875 /* (on 730, bit 13 must not be cleared) */
876 if (cpu_is_omap730()) 876 if (cpu_is_omap7xx())
877 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL); 877 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
878 else 878 else
879 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL); 879 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c
index 7030f9281ea..a27df2c14ac 100644
--- a/arch/arm/mach-omap1/io.c
+++ b/arch/arm/mach-omap1/io.c
@@ -36,33 +36,17 @@ static struct map_desc omap_io_desc[] __initdata = {
36 } 36 }
37}; 37};
38 38
39#ifdef CONFIG_ARCH_OMAP730 39#if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850)
40static struct map_desc omap730_io_desc[] __initdata = { 40static struct map_desc omap7xx_io_desc[] __initdata = {
41 { 41 {
42 .virtual = OMAP730_DSP_BASE, 42 .virtual = OMAP7XX_DSP_BASE,
43 .pfn = __phys_to_pfn(OMAP730_DSP_START), 43 .pfn = __phys_to_pfn(OMAP7XX_DSP_START),
44 .length = OMAP730_DSP_SIZE, 44 .length = OMAP7XX_DSP_SIZE,
45 .type = MT_DEVICE 45 .type = MT_DEVICE
46 }, { 46 }, {
47 .virtual = OMAP730_DSPREG_BASE, 47 .virtual = OMAP7XX_DSPREG_BASE,
48 .pfn = __phys_to_pfn(OMAP730_DSPREG_START), 48 .pfn = __phys_to_pfn(OMAP7XX_DSPREG_START),
49 .length = OMAP730_DSPREG_SIZE, 49 .length = OMAP7XX_DSPREG_SIZE,
50 .type = MT_DEVICE
51 }
52};
53#endif
54
55#ifdef CONFIG_ARCH_OMAP850
56static struct map_desc omap850_io_desc[] __initdata = {
57 {
58 .virtual = OMAP850_DSP_BASE,
59 .pfn = __phys_to_pfn(OMAP850_DSP_START),
60 .length = OMAP850_DSP_SIZE,
61 .type = MT_DEVICE
62 }, {
63 .virtual = OMAP850_DSPREG_BASE,
64 .pfn = __phys_to_pfn(OMAP850_DSPREG_START),
65 .length = OMAP850_DSPREG_SIZE,
66 .type = MT_DEVICE 50 .type = MT_DEVICE
67 } 51 }
68}; 52};
@@ -120,18 +104,11 @@ void __init omap1_map_common_io(void)
120 */ 104 */
121 omap_check_revision(); 105 omap_check_revision();
122 106
123#ifdef CONFIG_ARCH_OMAP730 107#if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850)
124 if (cpu_is_omap730()) { 108 if (cpu_is_omap7xx()) {
125 iotable_init(omap730_io_desc, ARRAY_SIZE(omap730_io_desc)); 109 iotable_init(omap7xx_io_desc, ARRAY_SIZE(omap7xx_io_desc));
126 }
127#endif
128
129#ifdef CONFIG_ARCH_OMAP850
130 if (cpu_is_omap850()) {
131 iotable_init(omap850_io_desc, ARRAY_SIZE(omap850_io_desc));
132 } 110 }
133#endif 111#endif
134
135#ifdef CONFIG_ARCH_OMAP15XX 112#ifdef CONFIG_ARCH_OMAP15XX
136 if (cpu_is_omap15xx()) { 113 if (cpu_is_omap15xx()) {
137 iotable_init(omap1510_io_desc, ARRAY_SIZE(omap1510_io_desc)); 114 iotable_init(omap1510_io_desc, ARRAY_SIZE(omap1510_io_desc));
diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c
index de03c844899..8f98b58575d 100644
--- a/arch/arm/mach-omap1/irq.c
+++ b/arch/arm/mach-omap1/irq.c
@@ -137,16 +137,8 @@ static void omap_irq_set_cfg(int irq, int fiq, int priority, int trigger)
137 irq_bank_writel(val, bank, offset); 137 irq_bank_writel(val, bank, offset);
138} 138}
139 139
140#ifdef CONFIG_ARCH_OMAP730 140#if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850)
141static struct omap_irq_bank omap730_irq_banks[] = { 141static struct omap_irq_bank omap7xx_irq_banks[] = {
142 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3f8e22f },
143 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb9c1f2 },
144 { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0x800040f3 },
145};
146#endif
147
148#ifdef CONFIG_ARCH_OMAP850
149static struct omap_irq_bank omap850_irq_banks[] = {
150 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3f8e22f }, 142 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3f8e22f },
151 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb9c1f2 }, 143 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb9c1f2 },
152 { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0x800040f3 }, 144 { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0x800040f3 },
@@ -186,16 +178,10 @@ void __init omap_init_irq(void)
186{ 178{
187 int i, j; 179 int i, j;
188 180
189#ifdef CONFIG_ARCH_OMAP730 181#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
190 if (cpu_is_omap730()) { 182 if (cpu_is_omap7xx()) {
191 irq_banks = omap730_irq_banks; 183 irq_banks = omap7xx_irq_banks;
192 irq_bank_count = ARRAY_SIZE(omap730_irq_banks); 184 irq_bank_count = ARRAY_SIZE(omap7xx_irq_banks);
193 }
194#endif
195#ifdef CONFIG_ARCH_OMAP850
196 if (cpu_is_omap850()) {
197 irq_banks = omap850_irq_banks;
198 irq_bank_count = ARRAY_SIZE(omap850_irq_banks);
199 } 185 }
200#endif 186#endif
201#ifdef CONFIG_ARCH_OMAP15XX 187#ifdef CONFIG_ARCH_OMAP15XX
@@ -247,10 +233,8 @@ void __init omap_init_irq(void)
247 233
248 /* Unmask level 2 handler */ 234 /* Unmask level 2 handler */
249 235
250 if (cpu_is_omap730()) 236 if (cpu_is_omap7xx())
251 omap_unmask_irq(INT_730_IH2_IRQ); 237 omap_unmask_irq(INT_7XX_IH2_IRQ);
252 else if (cpu_is_omap850())
253 omap_unmask_irq(INT_850_IH2_IRQ);
254 else if (cpu_is_omap15xx()) 238 else if (cpu_is_omap15xx())
255 omap_unmask_irq(INT_1510_IH2_IRQ); 239 omap_unmask_irq(INT_1510_IH2_IRQ);
256 else if (cpu_is_omap16xx()) 240 else if (cpu_is_omap16xx())
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
index 505d98cfe50..3a51cb210de 100644
--- a/arch/arm/mach-omap1/mcbsp.c
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -79,29 +79,29 @@ static struct omap_mcbsp_ops omap1_mcbsp_ops = {
79 .free = omap1_mcbsp_free, 79 .free = omap1_mcbsp_free,
80}; 80};
81 81
82#ifdef CONFIG_ARCH_OMAP730 82#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
83static struct omap_mcbsp_platform_data omap730_mcbsp_pdata[] = { 83static struct omap_mcbsp_platform_data omap7xx_mcbsp_pdata[] = {
84 { 84 {
85 .phys_base = OMAP730_MCBSP1_BASE, 85 .phys_base = OMAP7XX_MCBSP1_BASE,
86 .dma_rx_sync = OMAP_DMA_MCBSP1_RX, 86 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
87 .dma_tx_sync = OMAP_DMA_MCBSP1_TX, 87 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
88 .rx_irq = INT_730_McBSP1RX, 88 .rx_irq = INT_7XX_McBSP1RX,
89 .tx_irq = INT_730_McBSP1TX, 89 .tx_irq = INT_7XX_McBSP1TX,
90 .ops = &omap1_mcbsp_ops, 90 .ops = &omap1_mcbsp_ops,
91 }, 91 },
92 { 92 {
93 .phys_base = OMAP730_MCBSP2_BASE, 93 .phys_base = OMAP7XX_MCBSP2_BASE,
94 .dma_rx_sync = OMAP_DMA_MCBSP3_RX, 94 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
95 .dma_tx_sync = OMAP_DMA_MCBSP3_TX, 95 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
96 .rx_irq = INT_730_McBSP2RX, 96 .rx_irq = INT_7XX_McBSP2RX,
97 .tx_irq = INT_730_McBSP2TX, 97 .tx_irq = INT_7XX_McBSP2TX,
98 .ops = &omap1_mcbsp_ops, 98 .ops = &omap1_mcbsp_ops,
99 }, 99 },
100}; 100};
101#define OMAP730_MCBSP_PDATA_SZ ARRAY_SIZE(omap730_mcbsp_pdata) 101#define OMAP7XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap7xx_mcbsp_pdata)
102#else 102#else
103#define omap730_mcbsp_pdata NULL 103#define omap7xx_mcbsp_pdata NULL
104#define OMAP730_MCBSP_PDATA_SZ 0 104#define OMAP7XX_MCBSP_PDATA_SZ 0
105#endif 105#endif
106 106
107#ifdef CONFIG_ARCH_OMAP15XX 107#ifdef CONFIG_ARCH_OMAP15XX
@@ -172,8 +172,8 @@ static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
172 172
173int __init omap1_mcbsp_init(void) 173int __init omap1_mcbsp_init(void)
174{ 174{
175 if (cpu_is_omap730()) 175 if (cpu_is_omap7xx())
176 omap_mcbsp_count = OMAP730_MCBSP_PDATA_SZ; 176 omap_mcbsp_count = OMAP7XX_MCBSP_PDATA_SZ;
177 if (cpu_is_omap15xx()) 177 if (cpu_is_omap15xx())
178 omap_mcbsp_count = OMAP15XX_MCBSP_PDATA_SZ; 178 omap_mcbsp_count = OMAP15XX_MCBSP_PDATA_SZ;
179 if (cpu_is_omap16xx()) 179 if (cpu_is_omap16xx())
@@ -184,9 +184,9 @@ int __init omap1_mcbsp_init(void)
184 if (!mcbsp_ptr) 184 if (!mcbsp_ptr)
185 return -ENOMEM; 185 return -ENOMEM;
186 186
187 if (cpu_is_omap730()) 187 if (cpu_is_omap7xx())
188 omap_mcbsp_register_board_cfg(omap730_mcbsp_pdata, 188 omap_mcbsp_register_board_cfg(omap7xx_mcbsp_pdata,
189 OMAP730_MCBSP_PDATA_SZ); 189 OMAP7XX_MCBSP_PDATA_SZ);
190 190
191 if (cpu_is_omap15xx()) 191 if (cpu_is_omap15xx())
192 omap_mcbsp_register_board_cfg(omap15xx_mcbsp_pdata, 192 omap_mcbsp_register_board_cfg(omap15xx_mcbsp_pdata,
diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c
index 721e0d9d8b1..d59899d6a7f 100644
--- a/arch/arm/mach-omap1/mux.c
+++ b/arch/arm/mach-omap1/mux.c
@@ -35,47 +35,28 @@
35 35
36static struct omap_mux_cfg arch_mux_cfg; 36static struct omap_mux_cfg arch_mux_cfg;
37 37
38#ifdef CONFIG_ARCH_OMAP730 38#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
39static struct pin_config __initdata_or_module omap730_pins[] = { 39static struct pin_config __initdata_or_module omap7xx_pins[] = {
40MUX_CFG_730("E2_730_KBR0", 12, 21, 0, 20, 1, 0) 40MUX_CFG_7XX("E2_7XX_KBR0", 12, 21, 0, 20, 1, 0)
41MUX_CFG_730("J7_730_KBR1", 12, 25, 0, 24, 1, 0) 41MUX_CFG_7XX("J7_7XX_KBR1", 12, 25, 0, 24, 1, 0)
42MUX_CFG_730("E1_730_KBR2", 12, 29, 0, 28, 1, 0) 42MUX_CFG_7XX("E1_7XX_KBR2", 12, 29, 0, 28, 1, 0)
43MUX_CFG_730("F3_730_KBR3", 13, 1, 0, 0, 1, 0) 43MUX_CFG_7XX("F3_7XX_KBR3", 13, 1, 0, 0, 1, 0)
44MUX_CFG_730("D2_730_KBR4", 13, 5, 0, 4, 1, 0) 44MUX_CFG_7XX("D2_7XX_KBR4", 13, 5, 0, 4, 1, 0)
45MUX_CFG_730("C2_730_KBC0", 13, 9, 0, 8, 1, 0) 45MUX_CFG_7XX("C2_7XX_KBC0", 13, 9, 0, 8, 1, 0)
46MUX_CFG_730("D3_730_KBC1", 13, 13, 0, 12, 1, 0) 46MUX_CFG_7XX("D3_7XX_KBC1", 13, 13, 0, 12, 1, 0)
47MUX_CFG_730("E4_730_KBC2", 13, 17, 0, 16, 1, 0) 47MUX_CFG_7XX("E4_7XX_KBC2", 13, 17, 0, 16, 1, 0)
48MUX_CFG_730("F4_730_KBC3", 13, 21, 0, 20, 1, 0) 48MUX_CFG_7XX("F4_7XX_KBC3", 13, 21, 0, 20, 1, 0)
49MUX_CFG_730("E3_730_KBC4", 13, 25, 0, 24, 1, 0) 49MUX_CFG_7XX("E3_7XX_KBC4", 13, 25, 0, 24, 1, 0)
50 50
51MUX_CFG_730("AA17_730_USB_DM", 2, 21, 0, 20, 0, 0) 51MUX_CFG_7XX("AA17_7XX_USB_DM", 2, 21, 0, 20, 0, 0)
52MUX_CFG_730("W16_730_USB_PU_EN", 2, 25, 0, 24, 0, 0) 52MUX_CFG_7XX("W16_7XX_USB_PU_EN", 2, 25, 0, 24, 0, 0)
53MUX_CFG_730("W17_730_USB_VBUSI", 2, 29, 0, 28, 0, 0) 53MUX_CFG_7XX("W17_7XX_USB_VBUSI", 2, 29, 0, 28, 0, 0)
54}; 54};
55#define OMAP730_PINS_SZ ARRAY_SIZE(omap730_pins) 55#define OMAP7XX_PINS_SZ ARRAY_SIZE(omap7xx_pins)
56#else 56#else
57#define omap730_pins NULL 57#define omap7xx_pins NULL
58#define OMAP730_PINS_SZ 0 58#define OMAP7XX_PINS_SZ 0
59#endif /* CONFIG_ARCH_OMAP730 */ 59#endif /* CONFIG_ARCH_OMAP730 || CONFIG_ARCH_OMAP850 */
60
61#ifdef CONFIG_ARCH_OMAP850
62struct pin_config __initdata_or_module omap850_pins[] = {
63MUX_CFG_850("E2_850_KBR0", 12, 21, 0, 20, 1, 0)
64MUX_CFG_850("J7_850_KBR1", 12, 25, 0, 24, 1, 0)
65MUX_CFG_850("E1_850_KBR2", 12, 29, 0, 28, 1, 0)
66MUX_CFG_850("F3_850_KBR3", 13, 1, 0, 0, 1, 0)
67MUX_CFG_850("D2_850_KBR4", 13, 5, 0, 4, 1, 0)
68MUX_CFG_850("C2_850_KBC0", 13, 9, 0, 8, 1, 0)
69MUX_CFG_850("D3_850_KBC1", 13, 13, 0, 12, 1, 0)
70MUX_CFG_850("E4_850_KBC2", 13, 17, 0, 16, 1, 0)
71MUX_CFG_850("F4_850_KBC3", 13, 21, 0, 20, 1, 0)
72MUX_CFG_850("E3_850_KBC4", 13, 25, 0, 24, 1, 0)
73
74MUX_CFG_850("AA17_850_USB_DM", 2, 21, 0, 20, 0, 0)
75MUX_CFG_850("W16_850_USB_PU_EN", 2, 25, 0, 24, 0, 0)
76MUX_CFG_850("W17_850_USB_VBUSI", 2, 29, 0, 28, 0, 0)
77};
78#endif
79 60
80#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) 61#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
81static struct pin_config __initdata_or_module omap1xxx_pins[] = { 62static struct pin_config __initdata_or_module omap1xxx_pins[] = {
@@ -438,11 +419,6 @@ int __init_or_module omap1_cfg_reg(const struct pin_config *cfg)
438 printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n", 419 printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
439 cfg->pull_name, cfg->pull_reg, pull_orig, pull); 420 cfg->pull_name, cfg->pull_reg, pull_orig, pull);
440 } 421 }
441
442#ifdef CONFIG_ARCH_OMAP850
443 omap_mux_register(omap850_pins, ARRAY_SIZE(omap850_pins));
444#endif
445
446#endif 422#endif
447 423
448#ifdef CONFIG_OMAP_MUX_ERRORS 424#ifdef CONFIG_OMAP_MUX_ERRORS
@@ -454,9 +430,9 @@ int __init_or_module omap1_cfg_reg(const struct pin_config *cfg)
454 430
455int __init omap1_mux_init(void) 431int __init omap1_mux_init(void)
456{ 432{
457 if (cpu_is_omap730()) { 433 if (cpu_is_omap7xx()) {
458 arch_mux_cfg.pins = omap730_pins; 434 arch_mux_cfg.pins = omap7xx_pins;
459 arch_mux_cfg.size = OMAP730_PINS_SZ; 435 arch_mux_cfg.size = OMAP7XX_PINS_SZ;
460 arch_mux_cfg.cfg_reg = omap1_cfg_reg; 436 arch_mux_cfg.cfg_reg = omap1_cfg_reg;
461 } 437 }
462 438
diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c
index 5218943c91c..10f4e4adca1 100644
--- a/arch/arm/mach-omap1/pm.c
+++ b/arch/arm/mach-omap1/pm.c
@@ -62,7 +62,7 @@
62static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE]; 62static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
63static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE]; 63static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE];
64static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE]; 64static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
65static unsigned int mpui730_sleep_save[MPUI730_SLEEP_SAVE_SIZE]; 65static unsigned int mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_SIZE];
66static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE]; 66static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
67static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE]; 67static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
68 68
@@ -183,9 +183,9 @@ static void omap_pm_wakeup_setup(void)
183 * drivers must still separately call omap_set_gpio_wakeup() to 183 * drivers must still separately call omap_set_gpio_wakeup() to
184 * wake up to a GPIO interrupt. 184 * wake up to a GPIO interrupt.
185 */ 185 */
186 if (cpu_is_omap730()) 186 if (cpu_is_omap7xx())
187 level1_wake = OMAP_IRQ_BIT(INT_730_GPIO_BANK1) | 187 level1_wake = OMAP_IRQ_BIT(INT_7XX_GPIO_BANK1) |
188 OMAP_IRQ_BIT(INT_730_IH2_IRQ); 188 OMAP_IRQ_BIT(INT_7XX_IH2_IRQ);
189 else if (cpu_is_omap15xx()) 189 else if (cpu_is_omap15xx())
190 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) | 190 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
191 OMAP_IRQ_BIT(INT_1510_IH2_IRQ); 191 OMAP_IRQ_BIT(INT_1510_IH2_IRQ);
@@ -195,10 +195,10 @@ static void omap_pm_wakeup_setup(void)
195 195
196 omap_writel(~level1_wake, OMAP_IH1_MIR); 196 omap_writel(~level1_wake, OMAP_IH1_MIR);
197 197
198 if (cpu_is_omap730()) { 198 if (cpu_is_omap7xx()) {
199 omap_writel(~level2_wake, OMAP_IH2_0_MIR); 199 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
200 omap_writel(~(OMAP_IRQ_BIT(INT_730_WAKE_UP_REQ) | 200 omap_writel(~(OMAP_IRQ_BIT(INT_7XX_WAKE_UP_REQ) |
201 OMAP_IRQ_BIT(INT_730_MPUIO_KEYPAD)), 201 OMAP_IRQ_BIT(INT_7XX_MPUIO_KEYPAD)),
202 OMAP_IH2_1_MIR); 202 OMAP_IH2_1_MIR);
203 } else if (cpu_is_omap15xx()) { 203 } else if (cpu_is_omap15xx()) {
204 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD); 204 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
@@ -253,15 +253,15 @@ void omap1_pm_suspend(void)
253 * Save interrupt, MPUI, ARM and UPLD control registers. 253 * Save interrupt, MPUI, ARM and UPLD control registers.
254 */ 254 */
255 255
256 if (cpu_is_omap730()) { 256 if (cpu_is_omap7xx()) {
257 MPUI730_SAVE(OMAP_IH1_MIR); 257 MPUI7XX_SAVE(OMAP_IH1_MIR);
258 MPUI730_SAVE(OMAP_IH2_0_MIR); 258 MPUI7XX_SAVE(OMAP_IH2_0_MIR);
259 MPUI730_SAVE(OMAP_IH2_1_MIR); 259 MPUI7XX_SAVE(OMAP_IH2_1_MIR);
260 MPUI730_SAVE(MPUI_CTRL); 260 MPUI7XX_SAVE(MPUI_CTRL);
261 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG); 261 MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG);
262 MPUI730_SAVE(MPUI_DSP_API_CONFIG); 262 MPUI7XX_SAVE(MPUI_DSP_API_CONFIG);
263 MPUI730_SAVE(EMIFS_CONFIG); 263 MPUI7XX_SAVE(EMIFS_CONFIG);
264 MPUI730_SAVE(EMIFF_SDRAM_CONFIG); 264 MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG);
265 265
266 } else if (cpu_is_omap15xx()) { 266 } else if (cpu_is_omap15xx()) {
267 MPUI1510_SAVE(OMAP_IH1_MIR); 267 MPUI1510_SAVE(OMAP_IH1_MIR);
@@ -306,7 +306,7 @@ void omap1_pm_suspend(void)
306 omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1); 306 omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1);
307 307
308 /* shut down dsp_ck */ 308 /* shut down dsp_ck */
309 if (!cpu_is_omap730()) 309 if (!cpu_is_omap7xx())
310 omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL); 310 omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL);
311 311
312 /* temporarily enabling api_ck to access DSP registers */ 312 /* temporarily enabling api_ck to access DSP registers */
@@ -383,12 +383,12 @@ void omap1_pm_suspend(void)
383 ULPD_RESTORE(ULPD_CLOCK_CTRL); 383 ULPD_RESTORE(ULPD_CLOCK_CTRL);
384 ULPD_RESTORE(ULPD_STATUS_REQ); 384 ULPD_RESTORE(ULPD_STATUS_REQ);
385 385
386 if (cpu_is_omap730()) { 386 if (cpu_is_omap7xx()) {
387 MPUI730_RESTORE(EMIFS_CONFIG); 387 MPUI7XX_RESTORE(EMIFS_CONFIG);
388 MPUI730_RESTORE(EMIFF_SDRAM_CONFIG); 388 MPUI7XX_RESTORE(EMIFF_SDRAM_CONFIG);
389 MPUI730_RESTORE(OMAP_IH1_MIR); 389 MPUI7XX_RESTORE(OMAP_IH1_MIR);
390 MPUI730_RESTORE(OMAP_IH2_0_MIR); 390 MPUI7XX_RESTORE(OMAP_IH2_0_MIR);
391 MPUI730_RESTORE(OMAP_IH2_1_MIR); 391 MPUI7XX_RESTORE(OMAP_IH2_1_MIR);
392 } else if (cpu_is_omap15xx()) { 392 } else if (cpu_is_omap15xx()) {
393 MPUI1510_RESTORE(MPUI_CTRL); 393 MPUI1510_RESTORE(MPUI_CTRL);
394 MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG); 394 MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
@@ -461,13 +461,13 @@ static int omap_pm_read_proc(
461 ULPD_SAVE(ULPD_DPLL_CTRL); 461 ULPD_SAVE(ULPD_DPLL_CTRL);
462 ULPD_SAVE(ULPD_POWER_CTRL); 462 ULPD_SAVE(ULPD_POWER_CTRL);
463 463
464 if (cpu_is_omap730()) { 464 if (cpu_is_omap7xx()) {
465 MPUI730_SAVE(MPUI_CTRL); 465 MPUI7XX_SAVE(MPUI_CTRL);
466 MPUI730_SAVE(MPUI_DSP_STATUS); 466 MPUI7XX_SAVE(MPUI_DSP_STATUS);
467 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG); 467 MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG);
468 MPUI730_SAVE(MPUI_DSP_API_CONFIG); 468 MPUI7XX_SAVE(MPUI_DSP_API_CONFIG);
469 MPUI730_SAVE(EMIFF_SDRAM_CONFIG); 469 MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG);
470 MPUI730_SAVE(EMIFS_CONFIG); 470 MPUI7XX_SAVE(EMIFS_CONFIG);
471 } else if (cpu_is_omap15xx()) { 471 } else if (cpu_is_omap15xx()) {
472 MPUI1510_SAVE(MPUI_CTRL); 472 MPUI1510_SAVE(MPUI_CTRL);
473 MPUI1510_SAVE(MPUI_DSP_STATUS); 473 MPUI1510_SAVE(MPUI_DSP_STATUS);
@@ -517,20 +517,20 @@ static int omap_pm_read_proc(
517 ULPD_SHOW(ULPD_STATUS_REQ), 517 ULPD_SHOW(ULPD_STATUS_REQ),
518 ULPD_SHOW(ULPD_POWER_CTRL)); 518 ULPD_SHOW(ULPD_POWER_CTRL));
519 519
520 if (cpu_is_omap730()) { 520 if (cpu_is_omap7xx()) {
521 my_buffer_offset += sprintf(my_base + my_buffer_offset, 521 my_buffer_offset += sprintf(my_base + my_buffer_offset,
522 "MPUI730_CTRL_REG 0x%-8x \n" 522 "MPUI7XX_CTRL_REG 0x%-8x \n"
523 "MPUI730_DSP_STATUS_REG: 0x%-8x \n" 523 "MPUI7XX_DSP_STATUS_REG: 0x%-8x \n"
524 "MPUI730_DSP_BOOT_CONFIG_REG: 0x%-8x \n" 524 "MPUI7XX_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
525 "MPUI730_DSP_API_CONFIG_REG: 0x%-8x \n" 525 "MPUI7XX_DSP_API_CONFIG_REG: 0x%-8x \n"
526 "MPUI730_SDRAM_CONFIG_REG: 0x%-8x \n" 526 "MPUI7XX_SDRAM_CONFIG_REG: 0x%-8x \n"
527 "MPUI730_EMIFS_CONFIG_REG: 0x%-8x \n", 527 "MPUI7XX_EMIFS_CONFIG_REG: 0x%-8x \n",
528 MPUI730_SHOW(MPUI_CTRL), 528 MPUI7XX_SHOW(MPUI_CTRL),
529 MPUI730_SHOW(MPUI_DSP_STATUS), 529 MPUI7XX_SHOW(MPUI_DSP_STATUS),
530 MPUI730_SHOW(MPUI_DSP_BOOT_CONFIG), 530 MPUI7XX_SHOW(MPUI_DSP_BOOT_CONFIG),
531 MPUI730_SHOW(MPUI_DSP_API_CONFIG), 531 MPUI7XX_SHOW(MPUI_DSP_API_CONFIG),
532 MPUI730_SHOW(EMIFF_SDRAM_CONFIG), 532 MPUI7XX_SHOW(EMIFF_SDRAM_CONFIG),
533 MPUI730_SHOW(EMIFS_CONFIG)); 533 MPUI7XX_SHOW(EMIFS_CONFIG));
534 } else if (cpu_is_omap15xx()) { 534 } else if (cpu_is_omap15xx()) {
535 my_buffer_offset += sprintf(my_base + my_buffer_offset, 535 my_buffer_offset += sprintf(my_base + my_buffer_offset,
536 "MPUI1510_CTRL_REG 0x%-8x \n" 536 "MPUI1510_CTRL_REG 0x%-8x \n"
@@ -668,9 +668,9 @@ static int __init omap_pm_init(void)
668 * These routines need to be in SRAM as that's the only 668 * These routines need to be in SRAM as that's the only
669 * memory the MPU can see when it wakes up. 669 * memory the MPU can see when it wakes up.
670 */ 670 */
671 if (cpu_is_omap730()) { 671 if (cpu_is_omap7xx()) {
672 omap_sram_suspend = omap_sram_push(omap730_cpu_suspend, 672 omap_sram_suspend = omap_sram_push(omap7xx_cpu_suspend,
673 omap730_cpu_suspend_sz); 673 omap7xx_cpu_suspend_sz);
674 } else if (cpu_is_omap15xx()) { 674 } else if (cpu_is_omap15xx()) {
675 omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend, 675 omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
676 omap1510_cpu_suspend_sz); 676 omap1510_cpu_suspend_sz);
@@ -686,8 +686,8 @@ static int __init omap_pm_init(void)
686 686
687 pm_idle = omap1_pm_idle; 687 pm_idle = omap1_pm_idle;
688 688
689 if (cpu_is_omap730()) 689 if (cpu_is_omap7xx())
690 setup_irq(INT_730_WAKE_UP_REQ, &omap_wakeup_irq); 690 setup_irq(INT_7XX_WAKE_UP_REQ, &omap_wakeup_irq);
691 else if (cpu_is_omap16xx()) 691 else if (cpu_is_omap16xx())
692 setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq); 692 setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq);
693 693
@@ -700,8 +700,8 @@ static int __init omap_pm_init(void)
700 omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL); 700 omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
701 701
702 /* Configure IDLECT3 */ 702 /* Configure IDLECT3 */
703 if (cpu_is_omap730()) 703 if (cpu_is_omap7xx())
704 omap_writel(OMAP730_IDLECT3_VAL, OMAP730_IDLECT3); 704 omap_writel(OMAP7XX_IDLECT3_VAL, OMAP7XX_IDLECT3);
705 else if (cpu_is_omap16xx()) 705 else if (cpu_is_omap16xx())
706 omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3); 706 omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
707 707
diff --git a/arch/arm/mach-omap1/pm.h b/arch/arm/mach-omap1/pm.h
index c4f05bdcf8a..56a647986ae 100644
--- a/arch/arm/mach-omap1/pm.h
+++ b/arch/arm/mach-omap1/pm.h
@@ -98,13 +98,14 @@
98#define OMAP1610_IDLECT3 0xfffece24 98#define OMAP1610_IDLECT3 0xfffece24
99#define OMAP1610_IDLE_LOOP_REQUEST 0x0400 99#define OMAP1610_IDLE_LOOP_REQUEST 0x0400
100 100
101#define OMAP730_IDLECT1_SLEEP_VAL 0x16c7 101#define OMAP7XX_IDLECT1_SLEEP_VAL 0x16c7
102#define OMAP730_IDLECT2_SLEEP_VAL 0x09c7 102#define OMAP7XX_IDLECT2_SLEEP_VAL 0x09c7
103#define OMAP730_IDLECT3_VAL 0x3f 103#define OMAP7XX_IDLECT3_VAL 0x3f
104#define OMAP730_IDLECT3 0xfffece24 104#define OMAP7XX_IDLECT3 0xfffece24
105#define OMAP730_IDLE_LOOP_REQUEST 0x0C00 105#define OMAP7XX_IDLE_LOOP_REQUEST 0x0C00
106 106
107#if !defined(CONFIG_ARCH_OMAP730) && \ 107#if !defined(CONFIG_ARCH_OMAP730) && \
108 !defined(CONFIG_ARCH_OMAP850) && \
108 !defined(CONFIG_ARCH_OMAP15XX) && \ 109 !defined(CONFIG_ARCH_OMAP15XX) && \
109 !defined(CONFIG_ARCH_OMAP16XX) 110 !defined(CONFIG_ARCH_OMAP16XX)
110#warning "Power management for this processor not implemented yet" 111#warning "Power management for this processor not implemented yet"
@@ -122,17 +123,17 @@ extern void allow_idle_sleep(void);
122extern void omap1_pm_idle(void); 123extern void omap1_pm_idle(void);
123extern void omap1_pm_suspend(void); 124extern void omap1_pm_suspend(void);
124 125
125extern void omap730_cpu_suspend(unsigned short, unsigned short); 126extern void omap7xx_cpu_suspend(unsigned short, unsigned short);
126extern void omap1510_cpu_suspend(unsigned short, unsigned short); 127extern void omap1510_cpu_suspend(unsigned short, unsigned short);
127extern void omap1610_cpu_suspend(unsigned short, unsigned short); 128extern void omap1610_cpu_suspend(unsigned short, unsigned short);
128extern void omap730_idle_loop_suspend(void); 129extern void omap7xx_idle_loop_suspend(void);
129extern void omap1510_idle_loop_suspend(void); 130extern void omap1510_idle_loop_suspend(void);
130extern void omap1610_idle_loop_suspend(void); 131extern void omap1610_idle_loop_suspend(void);
131 132
132extern unsigned int omap730_cpu_suspend_sz; 133extern unsigned int omap7xx_cpu_suspend_sz;
133extern unsigned int omap1510_cpu_suspend_sz; 134extern unsigned int omap1510_cpu_suspend_sz;
134extern unsigned int omap1610_cpu_suspend_sz; 135extern unsigned int omap1610_cpu_suspend_sz;
135extern unsigned int omap730_idle_loop_suspend_sz; 136extern unsigned int omap7xx_idle_loop_suspend_sz;
136extern unsigned int omap1510_idle_loop_suspend_sz; 137extern unsigned int omap1510_idle_loop_suspend_sz;
137extern unsigned int omap1610_idle_loop_suspend_sz; 138extern unsigned int omap1610_idle_loop_suspend_sz;
138 139
@@ -155,9 +156,9 @@ extern void omap_serial_wake_trigger(int enable);
155#define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x)) 156#define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x))
156#define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] 157#define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]
157 158
158#define MPUI730_SAVE(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x] = omap_readl(x) 159#define MPUI7XX_SAVE(x) mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x] = omap_readl(x)
159#define MPUI730_RESTORE(x) omap_writel((mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x]), (x)) 160#define MPUI7XX_RESTORE(x) omap_writel((mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x]), (x))
160#define MPUI730_SHOW(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x] 161#define MPUI7XX_SHOW(x) mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x]
161 162
162#define MPUI1510_SAVE(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] = omap_readl(x) 163#define MPUI1510_SAVE(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] = omap_readl(x)
163#define MPUI1510_RESTORE(x) omap_writel((mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]), (x)) 164#define MPUI1510_RESTORE(x) omap_writel((mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]), (x))
@@ -232,24 +233,24 @@ enum mpui1510_save_state {
232#endif 233#endif
233}; 234};
234 235
235enum mpui730_save_state { 236enum mpui7xx_save_state {
236 MPUI730_SLEEP_SAVE_START = 0, 237 MPUI7XX_SLEEP_SAVE_START = 0,
237 /* 238 /*
238 * MPUI registers 32 bits 239 * MPUI registers 32 bits
239 */ 240 */
240 MPUI730_SLEEP_SAVE_MPUI_CTRL, 241 MPUI7XX_SLEEP_SAVE_MPUI_CTRL,
241 MPUI730_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG, 242 MPUI7XX_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
242 MPUI730_SLEEP_SAVE_MPUI_DSP_API_CONFIG, 243 MPUI7XX_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
243 MPUI730_SLEEP_SAVE_MPUI_DSP_STATUS, 244 MPUI7XX_SLEEP_SAVE_MPUI_DSP_STATUS,
244 MPUI730_SLEEP_SAVE_EMIFF_SDRAM_CONFIG, 245 MPUI7XX_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
245 MPUI730_SLEEP_SAVE_EMIFS_CONFIG, 246 MPUI7XX_SLEEP_SAVE_EMIFS_CONFIG,
246 MPUI730_SLEEP_SAVE_OMAP_IH1_MIR, 247 MPUI7XX_SLEEP_SAVE_OMAP_IH1_MIR,
247 MPUI730_SLEEP_SAVE_OMAP_IH2_0_MIR, 248 MPUI7XX_SLEEP_SAVE_OMAP_IH2_0_MIR,
248 MPUI730_SLEEP_SAVE_OMAP_IH2_1_MIR, 249 MPUI7XX_SLEEP_SAVE_OMAP_IH2_1_MIR,
249#if defined(CONFIG_ARCH_OMAP730) 250#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
250 MPUI730_SLEEP_SAVE_SIZE 251 MPUI7XX_SLEEP_SAVE_SIZE
251#else 252#else
252 MPUI730_SLEEP_SAVE_SIZE = 0 253 MPUI7XX_SLEEP_SAVE_SIZE = 0
253#endif 254#endif
254}; 255};
255 256
diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c
index d496e50fec4..ed07af109f0 100644
--- a/arch/arm/mach-omap1/serial.c
+++ b/arch/arm/mach-omap1/serial.c
@@ -110,18 +110,11 @@ void __init omap_serial_init(void)
110{ 110{
111 int i; 111 int i;
112 112
113 if (cpu_is_omap730()) { 113 if (cpu_is_omap7xx()) {
114 serial_platform_data[0].regshift = 0; 114 serial_platform_data[0].regshift = 0;
115 serial_platform_data[1].regshift = 0; 115 serial_platform_data[1].regshift = 0;
116 serial_platform_data[0].irq = INT_730_UART_MODEM_1; 116 serial_platform_data[0].irq = INT_7XX_UART_MODEM_1;
117 serial_platform_data[1].irq = INT_730_UART_MODEM_IRDA_2; 117 serial_platform_data[1].irq = INT_7XX_UART_MODEM_IRDA_2;
118 }
119
120 if (cpu_is_omap850()) {
121 serial_platform_data[0].regshift = 0;
122 serial_platform_data[1].regshift = 0;
123 serial_platform_data[0].irq = INT_850_UART_MODEM_1;
124 serial_platform_data[1].irq = INT_850_UART_MODEM_IRDA_2;
125 } 118 }
126 119
127 if (cpu_is_omap15xx()) { 120 if (cpu_is_omap15xx()) {
diff --git a/arch/arm/mach-omap1/sleep.S b/arch/arm/mach-omap1/sleep.S
index 22e8568339b..ef771ce8b03 100644
--- a/arch/arm/mach-omap1/sleep.S
+++ b/arch/arm/mach-omap1/sleep.S
@@ -1,7 +1,7 @@
1/* 1/*
2 * linux/arch/arm/mach-omap1/sleep.S 2 * linux/arch/arm/mach-omap1/sleep.S
3 * 3 *
4 * Low-level OMAP730/1510/1610 sleep/wakeUp support 4 * Low-level OMAP7XX/1510/1610 sleep/wakeUp support
5 * 5 *
6 * Initial SA1110 code: 6 * Initial SA1110 code:
7 * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com> 7 * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
@@ -57,8 +57,8 @@
57 * 57 *
58 */ 58 */
59 59
60#if defined(CONFIG_ARCH_OMAP730) 60#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
61ENTRY(omap730_cpu_suspend) 61ENTRY(omap7xx_cpu_suspend)
62 62
63 @ save registers on stack 63 @ save registers on stack
64 stmfd sp!, {r0 - r12, lr} 64 stmfd sp!, {r0 - r12, lr}
@@ -91,13 +91,13 @@ ENTRY(omap730_cpu_suspend)
91 91
92 @ turn off clock domains 92 @ turn off clock domains
93 @ do not disable PERCK (0x04) 93 @ do not disable PERCK (0x04)
94 mov r5, #OMAP730_IDLECT2_SLEEP_VAL & 0xff 94 mov r5, #OMAP7XX_IDLECT2_SLEEP_VAL & 0xff
95 orr r5, r5, #OMAP730_IDLECT2_SLEEP_VAL & 0xff00 95 orr r5, r5, #OMAP7XX_IDLECT2_SLEEP_VAL & 0xff00
96 strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff] 96 strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
97 97
98 @ request ARM idle 98 @ request ARM idle
99 mov r3, #OMAP730_IDLECT1_SLEEP_VAL & 0xff 99 mov r3, #OMAP7XX_IDLECT1_SLEEP_VAL & 0xff
100 orr r3, r3, #OMAP730_IDLECT1_SLEEP_VAL & 0xff00 100 orr r3, r3, #OMAP7XX_IDLECT1_SLEEP_VAL & 0xff00
101 strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff] 101 strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
102 102
103 @ disable instruction cache 103 @ disable instruction cache
@@ -113,7 +113,7 @@ ENTRY(omap730_cpu_suspend)
113 mov r2, #0 113 mov r2, #0
114 mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt 114 mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt
115/* 115/*
116 * omap730_cpu_suspend()'s resume point. 116 * omap7xx_cpu_suspend()'s resume point.
117 * 117 *
118 * It will just start executing here, so we'll restore stuff from the 118 * It will just start executing here, so we'll restore stuff from the
119 * stack. 119 * stack.
@@ -132,9 +132,9 @@ ENTRY(omap730_cpu_suspend)
132 @ restore regs and return 132 @ restore regs and return
133 ldmfd sp!, {r0 - r12, pc} 133 ldmfd sp!, {r0 - r12, pc}
134 134
135ENTRY(omap730_cpu_suspend_sz) 135ENTRY(omap7xx_cpu_suspend_sz)
136 .word . - omap730_cpu_suspend 136 .word . - omap7xx_cpu_suspend
137#endif /* CONFIG_ARCH_OMAP730 */ 137#endif /* CONFIG_ARCH_OMAP730 || CONFIG_ARCH_OMAP850 */
138 138
139#ifdef CONFIG_ARCH_OMAP15XX 139#ifdef CONFIG_ARCH_OMAP15XX
140ENTRY(omap1510_cpu_suspend) 140ENTRY(omap1510_cpu_suspend)
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index a64b692a1bf..d2f54753b01 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -113,17 +113,17 @@ static void omap_init_kp(void)
113 omap_cfg_reg(E19_1610_KBR4); 113 omap_cfg_reg(E19_1610_KBR4);
114 omap_cfg_reg(N19_1610_KBR5); 114 omap_cfg_reg(N19_1610_KBR5);
115 } else if (machine_is_omap_perseus2() || machine_is_omap_fsample()) { 115 } else if (machine_is_omap_perseus2() || machine_is_omap_fsample()) {
116 omap_cfg_reg(E2_730_KBR0); 116 omap_cfg_reg(E2_7XX_KBR0);
117 omap_cfg_reg(J7_730_KBR1); 117 omap_cfg_reg(J7_7XX_KBR1);
118 omap_cfg_reg(E1_730_KBR2); 118 omap_cfg_reg(E1_7XX_KBR2);
119 omap_cfg_reg(F3_730_KBR3); 119 omap_cfg_reg(F3_7XX_KBR3);
120 omap_cfg_reg(D2_730_KBR4); 120 omap_cfg_reg(D2_7XX_KBR4);
121 121
122 omap_cfg_reg(C2_730_KBC0); 122 omap_cfg_reg(C2_7XX_KBC0);
123 omap_cfg_reg(D3_730_KBC1); 123 omap_cfg_reg(D3_7XX_KBC1);
124 omap_cfg_reg(E4_730_KBC2); 124 omap_cfg_reg(E4_7XX_KBC2);
125 omap_cfg_reg(F4_730_KBC3); 125 omap_cfg_reg(F4_7XX_KBC3);
126 omap_cfg_reg(E3_730_KBC4); 126 omap_cfg_reg(E3_7XX_KBC4);
127 } else if (machine_is_omap_h4()) { 127 } else if (machine_is_omap_h4()) {
128 omap_cfg_reg(T19_24XX_KBR0); 128 omap_cfg_reg(T19_24XX_KBR0);
129 omap_cfg_reg(R19_24XX_KBR1); 129 omap_cfg_reg(R19_24XX_KBR1);
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 71ebd7fcfea..b0c73613a4e 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -68,36 +68,20 @@
68#define OMAP1610_GPIO_SET_DATAOUT 0x00f0 68#define OMAP1610_GPIO_SET_DATAOUT 0x00f0
69 69
70/* 70/*
71 * OMAP730 specific GPIO registers 71 * OMAP7XX specific GPIO registers
72 */ 72 */
73#define OMAP730_GPIO1_BASE OMAP1_IO_ADDRESS(0xfffbc000) 73#define OMAP7XX_GPIO1_BASE OMAP1_IO_ADDRESS(0xfffbc000)
74#define OMAP730_GPIO2_BASE OMAP1_IO_ADDRESS(0xfffbc800) 74#define OMAP7XX_GPIO2_BASE OMAP1_IO_ADDRESS(0xfffbc800)
75#define OMAP730_GPIO3_BASE OMAP1_IO_ADDRESS(0xfffbd000) 75#define OMAP7XX_GPIO3_BASE OMAP1_IO_ADDRESS(0xfffbd000)
76#define OMAP730_GPIO4_BASE OMAP1_IO_ADDRESS(0xfffbd800) 76#define OMAP7XX_GPIO4_BASE OMAP1_IO_ADDRESS(0xfffbd800)
77#define OMAP730_GPIO5_BASE OMAP1_IO_ADDRESS(0xfffbe000) 77#define OMAP7XX_GPIO5_BASE OMAP1_IO_ADDRESS(0xfffbe000)
78#define OMAP730_GPIO6_BASE OMAP1_IO_ADDRESS(0xfffbe800) 78#define OMAP7XX_GPIO6_BASE OMAP1_IO_ADDRESS(0xfffbe800)
79#define OMAP730_GPIO_DATA_INPUT 0x00 79#define OMAP7XX_GPIO_DATA_INPUT 0x00
80#define OMAP730_GPIO_DATA_OUTPUT 0x04 80#define OMAP7XX_GPIO_DATA_OUTPUT 0x04
81#define OMAP730_GPIO_DIR_CONTROL 0x08 81#define OMAP7XX_GPIO_DIR_CONTROL 0x08
82#define OMAP730_GPIO_INT_CONTROL 0x0c 82#define OMAP7XX_GPIO_INT_CONTROL 0x0c
83#define OMAP730_GPIO_INT_MASK 0x10 83#define OMAP7XX_GPIO_INT_MASK 0x10
84#define OMAP730_GPIO_INT_STATUS 0x14 84#define OMAP7XX_GPIO_INT_STATUS 0x14
85
86/*
87 * OMAP850 specific GPIO registers
88 */
89#define OMAP850_GPIO1_BASE OMAP1_IO_ADDRESS(0xfffbc000)
90#define OMAP850_GPIO2_BASE OMAP1_IO_ADDRESS(0xfffbc800)
91#define OMAP850_GPIO3_BASE OMAP1_IO_ADDRESS(0xfffbd000)
92#define OMAP850_GPIO4_BASE OMAP1_IO_ADDRESS(0xfffbd800)
93#define OMAP850_GPIO5_BASE OMAP1_IO_ADDRESS(0xfffbe000)
94#define OMAP850_GPIO6_BASE OMAP1_IO_ADDRESS(0xfffbe800)
95#define OMAP850_GPIO_DATA_INPUT 0x00
96#define OMAP850_GPIO_DATA_OUTPUT 0x04
97#define OMAP850_GPIO_DIR_CONTROL 0x08
98#define OMAP850_GPIO_INT_CONTROL 0x0c
99#define OMAP850_GPIO_INT_MASK 0x10
100#define OMAP850_GPIO_INT_STATUS 0x14
101 85
102#define OMAP1_MPUIO_VBASE OMAP1_IO_ADDRESS(OMAP1_MPUIO_BASE) 86#define OMAP1_MPUIO_VBASE OMAP1_IO_ADDRESS(OMAP1_MPUIO_BASE)
103 87
@@ -215,8 +199,7 @@ struct gpio_bank {
215#define METHOD_MPUIO 0 199#define METHOD_MPUIO 0
216#define METHOD_GPIO_1510 1 200#define METHOD_GPIO_1510 1
217#define METHOD_GPIO_1610 2 201#define METHOD_GPIO_1610 2
218#define METHOD_GPIO_730 3 202#define METHOD_GPIO_7XX 3
219#define METHOD_GPIO_850 4
220#define METHOD_GPIO_24XX 5 203#define METHOD_GPIO_24XX 5
221 204
222#ifdef CONFIG_ARCH_OMAP16XX 205#ifdef CONFIG_ARCH_OMAP16XX
@@ -236,31 +219,18 @@ static struct gpio_bank gpio_bank_1510[2] = {
236}; 219};
237#endif 220#endif
238 221
239#ifdef CONFIG_ARCH_OMAP730 222#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
240static struct gpio_bank gpio_bank_730[7] = { 223static struct gpio_bank gpio_bank_7xx[7] = {
241 { OMAP1_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, 224 { OMAP1_MPUIO_VBASE, INT_7XX_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
242 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 }, 225 { OMAP7XX_GPIO1_BASE, INT_7XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_7XX },
243 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 }, 226 { OMAP7XX_GPIO2_BASE, INT_7XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_7XX },
244 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 }, 227 { OMAP7XX_GPIO3_BASE, INT_7XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_7XX },
245 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 }, 228 { OMAP7XX_GPIO4_BASE, INT_7XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_7XX },
246 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 }, 229 { OMAP7XX_GPIO5_BASE, INT_7XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_7XX },
247 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 }, 230 { OMAP7XX_GPIO6_BASE, INT_7XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_7XX },
248}; 231};
249#endif 232#endif
250 233
251#ifdef CONFIG_ARCH_OMAP850
252static struct gpio_bank gpio_bank_850[7] = {
253 { OMAP1_MPUIO_VBASE, INT_850_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
254 { OMAP850_GPIO1_BASE, INT_850_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_850 },
255 { OMAP850_GPIO2_BASE, INT_850_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_850 },
256 { OMAP850_GPIO3_BASE, INT_850_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_850 },
257 { OMAP850_GPIO4_BASE, INT_850_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_850 },
258 { OMAP850_GPIO5_BASE, INT_850_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_850 },
259 { OMAP850_GPIO6_BASE, INT_850_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_850 },
260};
261#endif
262
263
264#ifdef CONFIG_ARCH_OMAP24XX 234#ifdef CONFIG_ARCH_OMAP24XX
265 235
266static struct gpio_bank gpio_bank_242x[4] = { 236static struct gpio_bank gpio_bank_242x[4] = {
@@ -402,14 +372,9 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
402 reg += OMAP1610_GPIO_DIRECTION; 372 reg += OMAP1610_GPIO_DIRECTION;
403 break; 373 break;
404#endif 374#endif
405#ifdef CONFIG_ARCH_OMAP730 375#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
406 case METHOD_GPIO_730: 376 case METHOD_GPIO_7XX:
407 reg += OMAP730_GPIO_DIR_CONTROL; 377 reg += OMAP7XX_GPIO_DIR_CONTROL;
408 break;
409#endif
410#ifdef CONFIG_ARCH_OMAP850
411 case METHOD_GPIO_850:
412 reg += OMAP850_GPIO_DIR_CONTROL;
413 break; 378 break;
414#endif 379#endif
415#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 380#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
@@ -469,19 +434,9 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
469 l = 1 << gpio; 434 l = 1 << gpio;
470 break; 435 break;
471#endif 436#endif
472#ifdef CONFIG_ARCH_OMAP730 437#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
473 case METHOD_GPIO_730: 438 case METHOD_GPIO_7XX:
474 reg += OMAP730_GPIO_DATA_OUTPUT; 439 reg += OMAP7XX_GPIO_DATA_OUTPUT;
475 l = __raw_readl(reg);
476 if (enable)
477 l |= 1 << gpio;
478 else
479 l &= ~(1 << gpio);
480 break;
481#endif
482#ifdef CONFIG_ARCH_OMAP850
483 case METHOD_GPIO_850:
484 reg += OMAP850_GPIO_DATA_OUTPUT;
485 l = __raw_readl(reg); 440 l = __raw_readl(reg);
486 if (enable) 441 if (enable)
487 l |= 1 << gpio; 442 l |= 1 << gpio;
@@ -537,14 +492,9 @@ static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
537 reg += OMAP1610_GPIO_DATAIN; 492 reg += OMAP1610_GPIO_DATAIN;
538 break; 493 break;
539#endif 494#endif
540#ifdef CONFIG_ARCH_OMAP730 495#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
541 case METHOD_GPIO_730: 496 case METHOD_GPIO_7XX:
542 reg += OMAP730_GPIO_DATA_INPUT; 497 reg += OMAP7XX_GPIO_DATA_INPUT;
543 break;
544#endif
545#ifdef CONFIG_ARCH_OMAP850
546 case METHOD_GPIO_850:
547 reg += OMAP850_GPIO_DATA_INPUT;
548 break; 498 break;
549#endif 499#endif
550#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 500#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
@@ -588,14 +538,9 @@ static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
588 reg += OMAP1610_GPIO_DATAOUT; 538 reg += OMAP1610_GPIO_DATAOUT;
589 break; 539 break;
590#endif 540#endif
591#ifdef CONFIG_ARCH_OMAP730 541#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
592 case METHOD_GPIO_730: 542 case METHOD_GPIO_7XX:
593 reg += OMAP730_GPIO_DATA_OUTPUT; 543 reg += OMAP7XX_GPIO_DATA_OUTPUT;
594 break;
595#endif
596#ifdef CONFIG_ARCH_OMAP850
597 case METHOD_GPIO_850:
598 reg += OMAP850_GPIO_DATA_OUTPUT;
599 break; 544 break;
600#endif 545#endif
601#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 546#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
@@ -797,21 +742,9 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
797 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA); 742 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
798 break; 743 break;
799#endif 744#endif
800#ifdef CONFIG_ARCH_OMAP730 745#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
801 case METHOD_GPIO_730: 746 case METHOD_GPIO_7XX:
802 reg += OMAP730_GPIO_INT_CONTROL; 747 reg += OMAP7XX_GPIO_INT_CONTROL;
803 l = __raw_readl(reg);
804 if (trigger & IRQ_TYPE_EDGE_RISING)
805 l |= 1 << gpio;
806 else if (trigger & IRQ_TYPE_EDGE_FALLING)
807 l &= ~(1 << gpio);
808 else
809 goto bad;
810 break;
811#endif
812#ifdef CONFIG_ARCH_OMAP850
813 case METHOD_GPIO_850:
814 reg += OMAP850_GPIO_INT_CONTROL;
815 l = __raw_readl(reg); 748 l = __raw_readl(reg);
816 if (trigger & IRQ_TYPE_EDGE_RISING) 749 if (trigger & IRQ_TYPE_EDGE_RISING)
817 l |= 1 << gpio; 750 l |= 1 << gpio;
@@ -897,14 +830,9 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
897 reg += OMAP1610_GPIO_IRQSTATUS1; 830 reg += OMAP1610_GPIO_IRQSTATUS1;
898 break; 831 break;
899#endif 832#endif
900#ifdef CONFIG_ARCH_OMAP730 833#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
901 case METHOD_GPIO_730: 834 case METHOD_GPIO_7XX:
902 reg += OMAP730_GPIO_INT_STATUS; 835 reg += OMAP7XX_GPIO_INT_STATUS;
903 break;
904#endif
905#ifdef CONFIG_ARCH_OMAP850
906 case METHOD_GPIO_850:
907 reg += OMAP850_GPIO_INT_STATUS;
908 break; 836 break;
909#endif 837#endif
910#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 838#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
@@ -971,16 +899,9 @@ static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
971 mask = 0xffff; 899 mask = 0xffff;
972 break; 900 break;
973#endif 901#endif
974#ifdef CONFIG_ARCH_OMAP730 902#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
975 case METHOD_GPIO_730: 903 case METHOD_GPIO_7XX:
976 reg += OMAP730_GPIO_INT_MASK; 904 reg += OMAP7XX_GPIO_INT_MASK;
977 mask = 0xffffffff;
978 inv = 1;
979 break;
980#endif
981#ifdef CONFIG_ARCH_OMAP850
982 case METHOD_GPIO_850:
983 reg += OMAP850_GPIO_INT_MASK;
984 mask = 0xffffffff; 905 mask = 0xffffffff;
985 inv = 1; 906 inv = 1;
986 break; 907 break;
@@ -1044,19 +965,9 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
1044 l = gpio_mask; 965 l = gpio_mask;
1045 break; 966 break;
1046#endif 967#endif
1047#ifdef CONFIG_ARCH_OMAP730 968#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1048 case METHOD_GPIO_730: 969 case METHOD_GPIO_7XX:
1049 reg += OMAP730_GPIO_INT_MASK; 970 reg += OMAP7XX_GPIO_INT_MASK;
1050 l = __raw_readl(reg);
1051 if (enable)
1052 l &= ~(gpio_mask);
1053 else
1054 l |= gpio_mask;
1055 break;
1056#endif
1057#ifdef CONFIG_ARCH_OMAP850
1058 case METHOD_GPIO_850:
1059 reg += OMAP850_GPIO_INT_MASK;
1060 l = __raw_readl(reg); 971 l = __raw_readl(reg);
1061 if (enable) 972 if (enable)
1062 l &= ~(gpio_mask); 973 l &= ~(gpio_mask);
@@ -1249,13 +1160,9 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1249 if (bank->method == METHOD_GPIO_1610) 1160 if (bank->method == METHOD_GPIO_1610)
1250 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1; 1161 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1251#endif 1162#endif
1252#ifdef CONFIG_ARCH_OMAP730 1163#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1253 if (bank->method == METHOD_GPIO_730) 1164 if (bank->method == METHOD_GPIO_7XX)
1254 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS; 1165 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
1255#endif
1256#ifdef CONFIG_ARCH_OMAP850
1257 if (bank->method == METHOD_GPIO_850)
1258 isr_reg = bank->base + OMAP850_GPIO_INT_STATUS;
1259#endif 1166#endif
1260#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 1167#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1261 if (bank->method == METHOD_GPIO_24XX) 1168 if (bank->method == METHOD_GPIO_24XX)
@@ -1524,11 +1431,8 @@ static int gpio_is_input(struct gpio_bank *bank, int mask)
1524 case METHOD_GPIO_1610: 1431 case METHOD_GPIO_1610:
1525 reg += OMAP1610_GPIO_DIRECTION; 1432 reg += OMAP1610_GPIO_DIRECTION;
1526 break; 1433 break;
1527 case METHOD_GPIO_730: 1434 case METHOD_GPIO_7XX:
1528 reg += OMAP730_GPIO_DIR_CONTROL; 1435 reg += OMAP7XX_GPIO_DIR_CONTROL;
1529 break;
1530 case METHOD_GPIO_850:
1531 reg += OMAP850_GPIO_DIR_CONTROL;
1532 break; 1436 break;
1533 case METHOD_GPIO_24XX: 1437 case METHOD_GPIO_24XX:
1534 reg += OMAP24XX_GPIO_OE; 1438 reg += OMAP24XX_GPIO_OE;
@@ -1695,21 +1599,13 @@ static int __init _omap_gpio_init(void)
1695 (rev >> 4) & 0x0f, rev & 0x0f); 1599 (rev >> 4) & 0x0f, rev & 0x0f);
1696 } 1600 }
1697#endif 1601#endif
1698#ifdef CONFIG_ARCH_OMAP730 1602#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1699 if (cpu_is_omap730()) { 1603 if (cpu_is_omap7xx()) {
1700 printk(KERN_INFO "OMAP730 GPIO hardware\n"); 1604 printk(KERN_INFO "OMAP7XX GPIO hardware\n");
1701 gpio_bank_count = 7;
1702 gpio_bank = gpio_bank_730;
1703 }
1704#endif
1705#ifdef CONFIG_ARCH_OMAP850
1706 if (cpu_is_omap850()) {
1707 printk(KERN_INFO "OMAP850 GPIO hardware\n");
1708 gpio_bank_count = 7; 1605 gpio_bank_count = 7;
1709 gpio_bank = gpio_bank_850; 1606 gpio_bank = gpio_bank_7xx;
1710 } 1607 }
1711#endif 1608#endif
1712
1713#ifdef CONFIG_ARCH_OMAP24XX 1609#ifdef CONFIG_ARCH_OMAP24XX
1714 if (cpu_is_omap242x()) { 1610 if (cpu_is_omap242x()) {
1715 int rev; 1611 int rev;
@@ -1768,11 +1664,11 @@ static int __init _omap_gpio_init(void)
1768 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1); 1664 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1769 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG); 1665 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1770 } 1666 }
1771 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_730) { 1667 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1772 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK); 1668 __raw_writel(0xffffffff, bank->base + OMAP7XX_GPIO_INT_MASK);
1773 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS); 1669 __raw_writel(0x00000000, bank->base + OMAP7XX_GPIO_INT_STATUS);
1774 1670
1775 gpio_count = 32; /* 730 has 32-bit GPIOs */ 1671 gpio_count = 32; /* 7xx has 32-bit GPIOs */
1776 } 1672 }
1777 1673
1778#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 1674#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
@@ -2160,8 +2056,7 @@ static int dbg_gpio_show(struct seq_file *s, void *unused)
2160 2056
2161 if (bank_is_mpuio(bank)) 2057 if (bank_is_mpuio(bank))
2162 gpio = OMAP_MPUIO(0); 2058 gpio = OMAP_MPUIO(0);
2163 else if (cpu_class_is_omap2() || cpu_is_omap730() || 2059 else if (cpu_class_is_omap2() || cpu_is_omap7xx())
2164 cpu_is_omap850())
2165 bankwidth = 32; 2060 bankwidth = 32;
2166 2061
2167 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) { 2062 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
diff --git a/arch/arm/plat-omap/include/mach/entry-macro.S b/arch/arm/plat-omap/include/mach/entry-macro.S
index a5592991634..abe086416e1 100644
--- a/arch/arm/plat-omap/include/mach/entry-macro.S
+++ b/arch/arm/plat-omap/include/mach/entry-macro.S
@@ -17,11 +17,11 @@
17 17
18#if defined(CONFIG_ARCH_OMAP1) 18#if defined(CONFIG_ARCH_OMAP1)
19 19
20#if defined(CONFIG_ARCH_OMAP730) && \ 20#if (defined(CONFIG_ARCH_OMAP730)||defined(CONFIG_ARCH_OMAP850)) && \
21 (defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)) 21 (defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX))
22#error "FIXME: OMAP730 doesn't support multiple-OMAP" 22#error "FIXME: OMAP7XX doesn't support multiple-OMAP"
23#elif defined(CONFIG_ARCH_OMAP730) 23#elif defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
24#define INT_IH2_IRQ INT_730_IH2_IRQ 24#define INT_IH2_IRQ INT_7XX_IH2_IRQ
25#elif defined(CONFIG_ARCH_OMAP15XX) 25#elif defined(CONFIG_ARCH_OMAP15XX)
26#define INT_IH2_IRQ INT_1510_IH2_IRQ 26#define INT_IH2_IRQ INT_1510_IH2_IRQ
27#elif defined(CONFIG_ARCH_OMAP16XX) 27#elif defined(CONFIG_ARCH_OMAP16XX)
diff --git a/arch/arm/plat-omap/include/mach/hardware.h b/arch/arm/plat-omap/include/mach/hardware.h
index 26c1fbff08a..99c42412c0a 100644
--- a/arch/arm/plat-omap/include/mach/hardware.h
+++ b/arch/arm/plat-omap/include/mach/hardware.h
@@ -280,7 +280,7 @@
280 * --------------------------------------------------------------------------- 280 * ---------------------------------------------------------------------------
281 */ 281 */
282 282
283#include "omap730.h" 283#include "omap7xx.h"
284#include "omap1510.h" 284#include "omap1510.h"
285#include "omap16xx.h" 285#include "omap16xx.h"
286#include "omap24xx.h" 286#include "omap24xx.h"
diff --git a/arch/arm/plat-omap/include/mach/irqs.h b/arch/arm/plat-omap/include/mach/irqs.h
index 28a165058b6..6a6d0281e1d 100644
--- a/arch/arm/plat-omap/include/mach/irqs.h
+++ b/arch/arm/plat-omap/include/mach/irqs.h
@@ -86,49 +86,26 @@
86#define INT_1610_SSR_FIFO_0 29 86#define INT_1610_SSR_FIFO_0 29
87 87
88/* 88/*
89 * OMAP-730 specific IRQ numbers for interrupt handler 1 89 * OMAP-7xx specific IRQ numbers for interrupt handler 1
90 */ 90 */
91#define INT_730_IH2_FIQ 0 91#define INT_7XX_IH2_FIQ 0
92#define INT_730_IH2_IRQ 1 92#define INT_7XX_IH2_IRQ 1
93#define INT_730_USB_NON_ISO 2 93#define INT_7XX_USB_NON_ISO 2
94#define INT_730_USB_ISO 3 94#define INT_7XX_USB_ISO 3
95#define INT_730_ICR 4 95#define INT_7XX_ICR 4
96#define INT_730_EAC 5 96#define INT_7XX_EAC 5
97#define INT_730_GPIO_BANK1 6 97#define INT_7XX_GPIO_BANK1 6
98#define INT_730_GPIO_BANK2 7 98#define INT_7XX_GPIO_BANK2 7
99#define INT_730_GPIO_BANK3 8 99#define INT_7XX_GPIO_BANK3 8
100#define INT_730_McBSP2TX 10 100#define INT_7XX_McBSP2TX 10
101#define INT_730_McBSP2RX 11 101#define INT_7XX_McBSP2RX 11
102#define INT_730_McBSP2RX_OVF 12 102#define INT_7XX_McBSP2RX_OVF 12
103#define INT_730_LCD_LINE 14 103#define INT_7XX_LCD_LINE 14
104#define INT_730_GSM_PROTECT 15 104#define INT_7XX_GSM_PROTECT 15
105#define INT_730_TIMER3 16 105#define INT_7XX_TIMER3 16
106#define INT_730_GPIO_BANK5 17 106#define INT_7XX_GPIO_BANK5 17
107#define INT_730_GPIO_BANK6 18 107#define INT_7XX_GPIO_BANK6 18
108#define INT_730_SPGIO_WR 29 108#define INT_7XX_SPGIO_WR 29
109
110/*
111 * OMAP-850 specific IRQ numbers for interrupt handler 1
112 */
113#define INT_850_IH2_FIQ 0
114#define INT_850_IH2_IRQ 1
115#define INT_850_USB_NON_ISO 2
116#define INT_850_USB_ISO 3
117#define INT_850_ICR 4
118#define INT_850_EAC 5
119#define INT_850_GPIO_BANK1 6
120#define INT_850_GPIO_BANK2 7
121#define INT_850_GPIO_BANK3 8
122#define INT_850_McBSP2TX 10
123#define INT_850_McBSP2RX 11
124#define INT_850_McBSP2RX_OVF 12
125#define INT_850_LCD_LINE 14
126#define INT_850_GSM_PROTECT 15
127#define INT_850_TIMER3 16
128#define INT_850_GPIO_BANK5 17
129#define INT_850_GPIO_BANK6 18
130#define INT_850_SPGIO_WR 29
131
132 109
133/* 110/*
134 * IRQ numbers for interrupt handler 2 111 * IRQ numbers for interrupt handler 2
@@ -206,120 +183,62 @@
206#define INT_1610_SHA1MD5 (91 + IH2_BASE) 183#define INT_1610_SHA1MD5 (91 + IH2_BASE)
207 184
208/* 185/*
209 * OMAP-730 specific IRQ numbers for interrupt handler 2 186 * OMAP-7xx specific IRQ numbers for interrupt handler 2
210 */
211#define INT_730_HW_ERRORS (0 + IH2_BASE)
212#define INT_730_NFIQ_PWR_FAIL (1 + IH2_BASE)
213#define INT_730_CFCD (2 + IH2_BASE)
214#define INT_730_CFIREQ (3 + IH2_BASE)
215#define INT_730_I2C (4 + IH2_BASE)
216#define INT_730_PCC (5 + IH2_BASE)
217#define INT_730_MPU_EXT_NIRQ (6 + IH2_BASE)
218#define INT_730_SPI_100K_1 (7 + IH2_BASE)
219#define INT_730_SYREN_SPI (8 + IH2_BASE)
220#define INT_730_VLYNQ (9 + IH2_BASE)
221#define INT_730_GPIO_BANK4 (10 + IH2_BASE)
222#define INT_730_McBSP1TX (11 + IH2_BASE)
223#define INT_730_McBSP1RX (12 + IH2_BASE)
224#define INT_730_McBSP1RX_OF (13 + IH2_BASE)
225#define INT_730_UART_MODEM_IRDA_2 (14 + IH2_BASE)
226#define INT_730_UART_MODEM_1 (15 + IH2_BASE)
227#define INT_730_MCSI (16 + IH2_BASE)
228#define INT_730_uWireTX (17 + IH2_BASE)
229#define INT_730_uWireRX (18 + IH2_BASE)
230#define INT_730_SMC_CD (19 + IH2_BASE)
231#define INT_730_SMC_IREQ (20 + IH2_BASE)
232#define INT_730_HDQ_1WIRE (21 + IH2_BASE)
233#define INT_730_TIMER32K (22 + IH2_BASE)
234#define INT_730_MMC_SDIO (23 + IH2_BASE)
235#define INT_730_UPLD (24 + IH2_BASE)
236#define INT_730_USB_HHC_1 (27 + IH2_BASE)
237#define INT_730_USB_HHC_2 (28 + IH2_BASE)
238#define INT_730_USB_GENI (29 + IH2_BASE)
239#define INT_730_USB_OTG (30 + IH2_BASE)
240#define INT_730_CAMERA_IF (31 + IH2_BASE)
241#define INT_730_RNG (32 + IH2_BASE)
242#define INT_730_DUAL_MODE_TIMER (33 + IH2_BASE)
243#define INT_730_DBB_RF_EN (34 + IH2_BASE)
244#define INT_730_MPUIO_KEYPAD (35 + IH2_BASE)
245#define INT_730_SHA1_MD5 (36 + IH2_BASE)
246#define INT_730_SPI_100K_2 (37 + IH2_BASE)
247#define INT_730_RNG_IDLE (38 + IH2_BASE)
248#define INT_730_MPUIO (39 + IH2_BASE)
249#define INT_730_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE)
250#define INT_730_LLPC_OE_FALLING (41 + IH2_BASE)
251#define INT_730_LLPC_OE_RISING (42 + IH2_BASE)
252#define INT_730_LLPC_VSYNC (43 + IH2_BASE)
253#define INT_730_WAKE_UP_REQ (46 + IH2_BASE)
254#define INT_730_DMA_CH6 (53 + IH2_BASE)
255#define INT_730_DMA_CH7 (54 + IH2_BASE)
256#define INT_730_DMA_CH8 (55 + IH2_BASE)
257#define INT_730_DMA_CH9 (56 + IH2_BASE)
258#define INT_730_DMA_CH10 (57 + IH2_BASE)
259#define INT_730_DMA_CH11 (58 + IH2_BASE)
260#define INT_730_DMA_CH12 (59 + IH2_BASE)
261#define INT_730_DMA_CH13 (60 + IH2_BASE)
262#define INT_730_DMA_CH14 (61 + IH2_BASE)
263#define INT_730_DMA_CH15 (62 + IH2_BASE)
264#define INT_730_NAND (63 + IH2_BASE)
265
266/*
267 * OMAP-850 specific IRQ numbers for interrupt handler 2
268 */ 187 */
269#define INT_850_HW_ERRORS (0 + IH2_BASE) 188#define INT_7XX_HW_ERRORS (0 + IH2_BASE)
270#define INT_850_NFIQ_PWR_FAIL (1 + IH2_BASE) 189#define INT_7XX_NFIQ_PWR_FAIL (1 + IH2_BASE)
271#define INT_850_CFCD (2 + IH2_BASE) 190#define INT_7XX_CFCD (2 + IH2_BASE)
272#define INT_850_CFIREQ (3 + IH2_BASE) 191#define INT_7XX_CFIREQ (3 + IH2_BASE)
273#define INT_850_I2C (4 + IH2_BASE) 192#define INT_7XX_I2C (4 + IH2_BASE)
274#define INT_850_PCC (5 + IH2_BASE) 193#define INT_7XX_PCC (5 + IH2_BASE)
275#define INT_850_MPU_EXT_NIRQ (6 + IH2_BASE) 194#define INT_7XX_MPU_EXT_NIRQ (6 + IH2_BASE)
276#define INT_850_SPI_100K_1 (7 + IH2_BASE) 195#define INT_7XX_SPI_100K_1 (7 + IH2_BASE)
277#define INT_850_SYREN_SPI (8 + IH2_BASE) 196#define INT_7XX_SYREN_SPI (8 + IH2_BASE)
278#define INT_850_VLYNQ (9 + IH2_BASE) 197#define INT_7XX_VLYNQ (9 + IH2_BASE)
279#define INT_850_GPIO_BANK4 (10 + IH2_BASE) 198#define INT_7XX_GPIO_BANK4 (10 + IH2_BASE)
280#define INT_850_McBSP1TX (11 + IH2_BASE) 199#define INT_7XX_McBSP1TX (11 + IH2_BASE)
281#define INT_850_McBSP1RX (12 + IH2_BASE) 200#define INT_7XX_McBSP1RX (12 + IH2_BASE)
282#define INT_850_McBSP1RX_OF (13 + IH2_BASE) 201#define INT_7XX_McBSP1RX_OF (13 + IH2_BASE)
283#define INT_850_UART_MODEM_IRDA_2 (14 + IH2_BASE) 202#define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE)
284#define INT_850_UART_MODEM_1 (15 + IH2_BASE) 203#define INT_7XX_UART_MODEM_1 (15 + IH2_BASE)
285#define INT_850_MCSI (16 + IH2_BASE) 204#define INT_7XX_MCSI (16 + IH2_BASE)
286#define INT_850_uWireTX (17 + IH2_BASE) 205#define INT_7XX_uWireTX (17 + IH2_BASE)
287#define INT_850_uWireRX (18 + IH2_BASE) 206#define INT_7XX_uWireRX (18 + IH2_BASE)
288#define INT_850_SMC_CD (19 + IH2_BASE) 207#define INT_7XX_SMC_CD (19 + IH2_BASE)
289#define INT_850_SMC_IREQ (20 + IH2_BASE) 208#define INT_7XX_SMC_IREQ (20 + IH2_BASE)
290#define INT_850_HDQ_1WIRE (21 + IH2_BASE) 209#define INT_7XX_HDQ_1WIRE (21 + IH2_BASE)
291#define INT_850_TIMER32K (22 + IH2_BASE) 210#define INT_7XX_TIMER32K (22 + IH2_BASE)
292#define INT_850_MMC_SDIO (23 + IH2_BASE) 211#define INT_7XX_MMC_SDIO (23 + IH2_BASE)
293#define INT_850_UPLD (24 + IH2_BASE) 212#define INT_7XX_UPLD (24 + IH2_BASE)
294#define INT_850_USB_HHC_1 (27 + IH2_BASE) 213#define INT_7XX_USB_HHC_1 (27 + IH2_BASE)
295#define INT_850_USB_HHC_2 (28 + IH2_BASE) 214#define INT_7XX_USB_HHC_2 (28 + IH2_BASE)
296#define INT_850_USB_GENI (29 + IH2_BASE) 215#define INT_7XX_USB_GENI (29 + IH2_BASE)
297#define INT_850_USB_OTG (30 + IH2_BASE) 216#define INT_7XX_USB_OTG (30 + IH2_BASE)
298#define INT_850_CAMERA_IF (31 + IH2_BASE) 217#define INT_7XX_CAMERA_IF (31 + IH2_BASE)
299#define INT_850_RNG (32 + IH2_BASE) 218#define INT_7XX_RNG (32 + IH2_BASE)
300#define INT_850_DUAL_MODE_TIMER (33 + IH2_BASE) 219#define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE)
301#define INT_850_DBB_RF_EN (34 + IH2_BASE) 220#define INT_7XX_DBB_RF_EN (34 + IH2_BASE)
302#define INT_850_MPUIO_KEYPAD (35 + IH2_BASE) 221#define INT_7XX_MPUIO_KEYPAD (35 + IH2_BASE)
303#define INT_850_SHA1_MD5 (36 + IH2_BASE) 222#define INT_7XX_SHA1_MD5 (36 + IH2_BASE)
304#define INT_850_SPI_100K_2 (37 + IH2_BASE) 223#define INT_7XX_SPI_100K_2 (37 + IH2_BASE)
305#define INT_850_RNG_IDLE (38 + IH2_BASE) 224#define INT_7XX_RNG_IDLE (38 + IH2_BASE)
306#define INT_850_MPUIO (39 + IH2_BASE) 225#define INT_7XX_MPUIO (39 + IH2_BASE)
307#define INT_850_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE) 226#define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE)
308#define INT_850_LLPC_OE_FALLING (41 + IH2_BASE) 227#define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE)
309#define INT_850_LLPC_OE_RISING (42 + IH2_BASE) 228#define INT_7XX_LLPC_OE_RISING (42 + IH2_BASE)
310#define INT_850_LLPC_VSYNC (43 + IH2_BASE) 229#define INT_7XX_LLPC_VSYNC (43 + IH2_BASE)
311#define INT_850_WAKE_UP_REQ (46 + IH2_BASE) 230#define INT_7XX_WAKE_UP_REQ (46 + IH2_BASE)
312#define INT_850_DMA_CH6 (53 + IH2_BASE) 231#define INT_7XX_DMA_CH6 (53 + IH2_BASE)
313#define INT_850_DMA_CH7 (54 + IH2_BASE) 232#define INT_7XX_DMA_CH7 (54 + IH2_BASE)
314#define INT_850_DMA_CH8 (55 + IH2_BASE) 233#define INT_7XX_DMA_CH8 (55 + IH2_BASE)
315#define INT_850_DMA_CH9 (56 + IH2_BASE) 234#define INT_7XX_DMA_CH9 (56 + IH2_BASE)
316#define INT_850_DMA_CH10 (57 + IH2_BASE) 235#define INT_7XX_DMA_CH10 (57 + IH2_BASE)
317#define INT_850_DMA_CH11 (58 + IH2_BASE) 236#define INT_7XX_DMA_CH11 (58 + IH2_BASE)
318#define INT_850_DMA_CH12 (59 + IH2_BASE) 237#define INT_7XX_DMA_CH12 (59 + IH2_BASE)
319#define INT_850_DMA_CH13 (60 + IH2_BASE) 238#define INT_7XX_DMA_CH13 (60 + IH2_BASE)
320#define INT_850_DMA_CH14 (61 + IH2_BASE) 239#define INT_7XX_DMA_CH14 (61 + IH2_BASE)
321#define INT_850_DMA_CH15 (62 + IH2_BASE) 240#define INT_7XX_DMA_CH15 (62 + IH2_BASE)
322#define INT_850_NAND (63 + IH2_BASE) 241#define INT_7XX_NAND (63 + IH2_BASE)
323 242
324#define INT_24XX_SYS_NIRQ 7 243#define INT_24XX_SYS_NIRQ 7
325#define INT_24XX_SDMA_IRQ0 12 244#define INT_24XX_SDMA_IRQ0 12
diff --git a/arch/arm/plat-omap/include/mach/mcbsp.h b/arch/arm/plat-omap/include/mach/mcbsp.h
index e0d6eca222c..7e9cae3e3d1 100644
--- a/arch/arm/plat-omap/include/mach/mcbsp.h
+++ b/arch/arm/plat-omap/include/mach/mcbsp.h
@@ -30,8 +30,8 @@
30#include <mach/hardware.h> 30#include <mach/hardware.h>
31#include <mach/clock.h> 31#include <mach/clock.h>
32 32
33#define OMAP730_MCBSP1_BASE 0xfffb1000 33#define OMAP7XX_MCBSP1_BASE 0xfffb1000
34#define OMAP730_MCBSP2_BASE 0xfffb1800 34#define OMAP7XX_MCBSP2_BASE 0xfffb1800
35 35
36#define OMAP1510_MCBSP1_BASE 0xe1011800 36#define OMAP1510_MCBSP1_BASE 0xe1011800
37#define OMAP1510_MCBSP2_BASE 0xfffb1000 37#define OMAP1510_MCBSP2_BASE 0xfffb1000
@@ -58,7 +58,7 @@
58#define OMAP44XX_MCBSP3_BASE 0x49026000 58#define OMAP44XX_MCBSP3_BASE 0x49026000
59#define OMAP44XX_MCBSP4_BASE 0x48074000 59#define OMAP44XX_MCBSP4_BASE 0x48074000
60 60
61#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) 61#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
62 62
63#define OMAP_MCBSP_REG_DRR2 0x00 63#define OMAP_MCBSP_REG_DRR2 0x00
64#define OMAP_MCBSP_REG_DRR1 0x02 64#define OMAP_MCBSP_REG_DRR1 0x02
diff --git a/arch/arm/plat-omap/include/mach/mux.h b/arch/arm/plat-omap/include/mach/mux.h
index 0f49d2d563d..f3c1d8a9045 100644
--- a/arch/arm/plat-omap/include/mach/mux.h
+++ b/arch/arm/plat-omap/include/mach/mux.h
@@ -51,23 +51,13 @@
51 .pu_pd_reg = PU_PD_SEL_##reg, \ 51 .pu_pd_reg = PU_PD_SEL_##reg, \
52 .pu_pd_val = status, 52 .pu_pd_val = status,
53 53
54#define MUX_REG_730(reg, mode_offset, mode) .mux_reg_name = "OMAP730_IO_CONF_"#reg, \ 54#define MUX_REG_7XX(reg, mode_offset, mode) .mux_reg_name = "OMAP7XX_IO_CONF_"#reg, \
55 .mux_reg = OMAP730_IO_CONF_##reg, \ 55 .mux_reg = OMAP7XX_IO_CONF_##reg, \
56 .mask_offset = mode_offset, \ 56 .mask_offset = mode_offset, \
57 .mask = mode, 57 .mask = mode,
58 58
59#define PULL_REG_730(reg, bit, status) .pull_name = "OMAP730_IO_CONF_"#reg, \ 59#define PULL_REG_7XX(reg, bit, status) .pull_name = "OMAP7XX_IO_CONF_"#reg, \
60 .pull_reg = OMAP730_IO_CONF_##reg, \ 60 .pull_reg = OMAP7XX_IO_CONF_##reg, \
61 .pull_bit = bit, \
62 .pull_val = status,
63
64#define MUX_REG_850(reg, mode_offset, mode) .mux_reg_name = "OMAP850_IO_CONF_"#reg, \
65 .mux_reg = OMAP850_IO_CONF_##reg, \
66 .mask_offset = mode_offset, \
67 .mask = mode,
68
69#define PULL_REG_850(reg, bit, status) .pull_name = "OMAP850_IO_CONF_"#reg, \
70 .pull_reg = OMAP850_IO_CONF_##reg, \
71 .pull_bit = bit, \ 61 .pull_bit = bit, \
72 .pull_val = status, 62 .pull_val = status,
73 63
@@ -84,21 +74,12 @@
84#define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \ 74#define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \
85 .pu_pd_val = status, 75 .pu_pd_val = status,
86 76
87#define MUX_REG_730(reg, mode_offset, mode) \ 77#define MUX_REG_7XX(reg, mode_offset, mode) \
88 .mux_reg = OMAP730_IO_CONF_##reg, \ 78 .mux_reg = OMAP7XX_IO_CONF_##reg, \
89 .mask_offset = mode_offset, \ 79 .mask_offset = mode_offset, \
90 .mask = mode, 80 .mask = mode,
91 81
92#define PULL_REG_730(reg, bit, status) .pull_reg = OMAP730_IO_CONF_##reg, \ 82#define PULL_REG_7XX(reg, bit, status) .pull_reg = OMAP7XX_IO_CONF_##reg, \
93 .pull_bit = bit, \
94 .pull_val = status,
95
96#define MUX_REG_850(reg, mode_offset, mode) \
97 .mux_reg = OMAP850_IO_CONF_##reg, \
98 .mask_offset = mode_offset, \
99 .mask = mode,
100
101#define PULL_REG_850(reg, bit, status) .pull_reg = OMAP850_IO_CONF_##reg, \
102 .pull_bit = bit, \ 83 .pull_bit = bit, \
103 .pull_val = status, 84 .pull_val = status,
104 85
@@ -118,32 +99,21 @@
118 99
119/* 100/*
120 * OMAP730/850 has a slightly different config for the pin mux. 101 * OMAP730/850 has a slightly different config for the pin mux.
121 * - config regs are the OMAP730_IO_CONF_x regs (see omap730.h) regs and 102 * - config regs are the OMAP7XX_IO_CONF_x regs (see omap730.h) regs and
122 * not the FUNC_MUX_CTRL_x regs from hardware.h 103 * not the FUNC_MUX_CTRL_x regs from hardware.h
123 * - for pull-up/down, only has one enable bit which is is in the same register 104 * - for pull-up/down, only has one enable bit which is is in the same register
124 * as mux config 105 * as mux config
125 */ 106 */
126#define MUX_CFG_730(desc, mux_reg, mode_offset, mode, \ 107#define MUX_CFG_7XX(desc, mux_reg, mode_offset, mode, \
127 pull_bit, pull_status, debug_status)\ 108 pull_bit, pull_status, debug_status)\
128{ \ 109{ \
129 .name = desc, \ 110 .name = desc, \
130 .debug = debug_status, \ 111 .debug = debug_status, \
131 MUX_REG_730(mux_reg, mode_offset, mode) \ 112 MUX_REG_7XX(mux_reg, mode_offset, mode) \
132 PULL_REG_730(mux_reg, pull_bit, pull_status) \ 113 PULL_REG_7XX(mux_reg, pull_bit, pull_status) \
133 PU_PD_REG(NA, 0) \ 114 PU_PD_REG(NA, 0) \
134}, 115},
135 116
136#define MUX_CFG_850(desc, mux_reg, mode_offset, mode, \
137 pull_bit, pull_status, debug_status)\
138{ \
139 .name = desc, \
140 .debug = debug_status, \
141 MUX_REG_850(mux_reg, mode_offset, mode) \
142 PULL_REG_850(mux_reg, pull_bit, pull_status) \
143 PU_PD_REG(NA, 0) \
144},
145
146
147#define MUX_CFG_24XX(desc, reg_offset, mode, \ 117#define MUX_CFG_24XX(desc, reg_offset, mode, \
148 pull_en, pull_mode, dbg) \ 118 pull_en, pull_mode, dbg) \
149{ \ 119{ \
@@ -232,45 +202,25 @@ struct pin_config {
232 202
233}; 203};
234 204
235enum omap730_index { 205enum omap7xx_index {
236 /* OMAP 730 keyboard */ 206 /* OMAP 730 keyboard */
237 E2_730_KBR0, 207 E2_7XX_KBR0,
238 J7_730_KBR1, 208 J7_7XX_KBR1,
239 E1_730_KBR2, 209 E1_7XX_KBR2,
240 F3_730_KBR3, 210 F3_7XX_KBR3,
241 D2_730_KBR4, 211 D2_7XX_KBR4,
242 C2_730_KBC0, 212 C2_7XX_KBC0,
243 D3_730_KBC1, 213 D3_7XX_KBC1,
244 E4_730_KBC2, 214 E4_7XX_KBC2,
245 F4_730_KBC3, 215 F4_7XX_KBC3,
246 E3_730_KBC4, 216 E3_7XX_KBC4,
247
248 /* USB */
249 AA17_730_USB_DM,
250 W16_730_USB_PU_EN,
251 W17_730_USB_VBUSI,
252};
253
254enum omap850_index {
255 /* OMAP 850 keyboard */
256 E2_850_KBR0,
257 J7_850_KBR1,
258 E1_850_KBR2,
259 F3_850_KBR3,
260 D2_850_KBR4,
261 C2_850_KBC0,
262 D3_850_KBC1,
263 E4_850_KBC2,
264 F4_850_KBC3,
265 E3_850_KBC4,
266 217
267 /* USB */ 218 /* USB */
268 AA17_850_USB_DM, 219 AA17_7XX_USB_DM,
269 W16_850_USB_PU_EN, 220 W16_7XX_USB_PU_EN,
270 W17_850_USB_VBUSI, 221 W17_7XX_USB_VBUSI,
271}; 222};
272 223
273
274enum omap1xxx_index { 224enum omap1xxx_index {
275 /* UART1 (BT_UART_GATING)*/ 225 /* UART1 (BT_UART_GATING)*/
276 UART1_TX = 0, 226 UART1_TX = 0,
diff --git a/arch/arm/plat-omap/include/mach/omap7xx.h b/arch/arm/plat-omap/include/mach/omap7xx.h
new file mode 100644
index 00000000000..53f52414b0e
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/omap7xx.h
@@ -0,0 +1,104 @@
1/* arch/arm/plat-omap/include/mach/omap7xx.h
2 *
3 * Hardware definitions for TI OMAP7XX processor.
4 *
5 * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
6 * Adapted for omap850 by Zebediah C. McClure <zmc@lurian.net>
7 * Adapted for omap7xx by Alistair Buxton <a.j.buxton@gmail.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29
30#ifndef __ASM_ARCH_OMAP7XX_H
31#define __ASM_ARCH_OMAP7XX_H
32
33/*
34 * ----------------------------------------------------------------------------
35 * Base addresses
36 * ----------------------------------------------------------------------------
37 */
38
39/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
40
41#define OMAP7XX_DSP_BASE 0xE0000000
42#define OMAP7XX_DSP_SIZE 0x50000
43#define OMAP7XX_DSP_START 0xE0000000
44
45#define OMAP7XX_DSPREG_BASE 0xE1000000
46#define OMAP7XX_DSPREG_SIZE SZ_128K
47#define OMAP7XX_DSPREG_START 0xE1000000
48
49/*
50 * ----------------------------------------------------------------------------
51 * OMAP7XX specific configuration registers
52 * ----------------------------------------------------------------------------
53 */
54#define OMAP7XX_CONFIG_BASE 0xfffe1000
55#define OMAP7XX_IO_CONF_0 0xfffe1070
56#define OMAP7XX_IO_CONF_1 0xfffe1074
57#define OMAP7XX_IO_CONF_2 0xfffe1078
58#define OMAP7XX_IO_CONF_3 0xfffe107c
59#define OMAP7XX_IO_CONF_4 0xfffe1080
60#define OMAP7XX_IO_CONF_5 0xfffe1084
61#define OMAP7XX_IO_CONF_6 0xfffe1088
62#define OMAP7XX_IO_CONF_7 0xfffe108c
63#define OMAP7XX_IO_CONF_8 0xfffe1090
64#define OMAP7XX_IO_CONF_9 0xfffe1094
65#define OMAP7XX_IO_CONF_10 0xfffe1098
66#define OMAP7XX_IO_CONF_11 0xfffe109c
67#define OMAP7XX_IO_CONF_12 0xfffe10a0
68#define OMAP7XX_IO_CONF_13 0xfffe10a4
69
70#define OMAP7XX_MODE_1 0xfffe1010
71#define OMAP7XX_MODE_2 0xfffe1014
72
73/* CSMI specials: in terms of base + offset */
74#define OMAP7XX_MODE2_OFFSET 0x14
75
76/*
77 * ----------------------------------------------------------------------------
78 * OMAP7XX traffic controller configuration registers
79 * ----------------------------------------------------------------------------
80 */
81#define OMAP7XX_FLASH_CFG_0 0xfffecc10
82#define OMAP7XX_FLASH_ACFG_0 0xfffecc50
83#define OMAP7XX_FLASH_CFG_1 0xfffecc14
84#define OMAP7XX_FLASH_ACFG_1 0xfffecc54
85
86/*
87 * ----------------------------------------------------------------------------
88 * OMAP7XX DSP control registers
89 * ----------------------------------------------------------------------------
90 */
91#define OMAP7XX_ICR_BASE 0xfffbb800
92#define OMAP7XX_DSP_M_CTL 0xfffbb804
93#define OMAP7XX_DSP_MMU_BASE 0xfffed200
94
95/*
96 * ----------------------------------------------------------------------------
97 * OMAP7XX PCC_UPLD configuration registers
98 * ----------------------------------------------------------------------------
99 */
100#define OMAP7XX_PCC_UPLD_CTRL_BASE (0xfffe0900)
101#define OMAP7XX_PCC_UPLD_CTRL (OMAP7XX_PCC_UPLD_CTRL_BASE + 0x00)
102
103#endif /* __ASM_ARCH_OMAP7XX_H */
104
diff --git a/arch/arm/plat-omap/include/mach/uncompress.h b/arch/arm/plat-omap/include/mach/uncompress.h
index 0814c5f210c..ddf7b88dec4 100644
--- a/arch/arm/plat-omap/include/mach/uncompress.h
+++ b/arch/arm/plat-omap/include/mach/uncompress.h
@@ -25,6 +25,7 @@ unsigned int system_rev;
25 25
26#define UART_OMAP_MDR1 0x08 /* mode definition register */ 26#define UART_OMAP_MDR1 0x08 /* mode definition register */
27#define OMAP_ID_730 0x355F 27#define OMAP_ID_730 0x355F
28#define OMAP_ID_850 0x362C
28#define ID_MASK 0x7fff 29#define ID_MASK 0x7fff
29#define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0) 30#define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0)
30#define omap_get_id() ((*(volatile unsigned int *)(0xfffed404)) >> 12) & ID_MASK 31#define omap_get_id() ((*(volatile unsigned int *)(0xfffed404)) >> 12) & ID_MASK
@@ -53,7 +54,7 @@ static void putc(int c)
53 /* MMU is not on, so cpu_is_omapXXXX() won't work here */ 54 /* MMU is not on, so cpu_is_omapXXXX() won't work here */
54 unsigned int omap_id = omap_get_id(); 55 unsigned int omap_id = omap_get_id();
55 56
56 if (omap_id == OMAP_ID_730) 57 if (omap_id == OMAP_ID_730 || omap_id == OMAP_ID_850)
57 shift = 0; 58 shift = 0;
58 59
59 if (check_port(uart, shift)) 60 if (check_port(uart, shift))
diff --git a/arch/arm/plat-omap/io.c b/arch/arm/plat-omap/io.c
index b6defa23e77..23a205f4a2b 100644
--- a/arch/arm/plat-omap/io.c
+++ b/arch/arm/plat-omap/io.c
@@ -13,7 +13,7 @@
13#include <linux/io.h> 13#include <linux/io.h>
14#include <linux/mm.h> 14#include <linux/mm.h>
15 15
16#include <mach/omap730.h> 16#include <mach/omap7xx.h>
17#include <mach/omap1510.h> 17#include <mach/omap1510.h>
18#include <mach/omap16xx.h> 18#include <mach/omap16xx.h>
19#include <mach/omap24xx.h> 19#include <mach/omap24xx.h>
@@ -33,13 +33,13 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
33 if (BETWEEN(p, OMAP1_IO_PHYS, OMAP1_IO_SIZE)) 33 if (BETWEEN(p, OMAP1_IO_PHYS, OMAP1_IO_SIZE))
34 return XLATE(p, OMAP1_IO_PHYS, OMAP1_IO_VIRT); 34 return XLATE(p, OMAP1_IO_PHYS, OMAP1_IO_VIRT);
35 } 35 }
36 if (cpu_is_omap730()) { 36 if (cpu_is_omap7xx()) {
37 if (BETWEEN(p, OMAP730_DSP_BASE, OMAP730_DSP_SIZE)) 37 if (BETWEEN(p, OMAP7XX_DSP_BASE, OMAP7XX_DSP_SIZE))
38 return XLATE(p, OMAP730_DSP_BASE, OMAP730_DSP_START); 38 return XLATE(p, OMAP7XX_DSP_BASE, OMAP7XX_DSP_START);
39 39
40 if (BETWEEN(p, OMAP730_DSPREG_BASE, OMAP730_DSPREG_SIZE)) 40 if (BETWEEN(p, OMAP7XX_DSPREG_BASE, OMAP7XX_DSPREG_SIZE))
41 return XLATE(p, OMAP730_DSPREG_BASE, 41 return XLATE(p, OMAP7XX_DSPREG_BASE,
42 OMAP730_DSPREG_START); 42 OMAP7XX_DSPREG_START);
43 } 43 }
44 if (cpu_is_omap15xx()) { 44 if (cpu_is_omap15xx()) {
45 if (BETWEEN(p, OMAP1510_DSP_BASE, OMAP1510_DSP_SIZE)) 45 if (BETWEEN(p, OMAP1510_DSP_BASE, OMAP1510_DSP_SIZE))
diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c
index 509f2ed99e2..3c40b8525df 100644
--- a/arch/arm/plat-omap/usb.c
+++ b/arch/arm/plat-omap/usb.c
@@ -614,8 +614,8 @@ omap_otg_init(struct omap_usb_config *config)
614 if (config->otg || config->register_host) { 614 if (config->otg || config->register_host) {
615 syscon &= ~HST_IDLE_EN; 615 syscon &= ~HST_IDLE_EN;
616 ohci_device.dev.platform_data = config; 616 ohci_device.dev.platform_data = config;
617 if (cpu_is_omap730()) 617 if (cpu_is_omap7xx())
618 ohci_resources[1].start = INT_730_USB_HHC_1; 618 ohci_resources[1].start = INT_7XX_USB_HHC_1;
619 status = platform_device_register(&ohci_device); 619 status = platform_device_register(&ohci_device);
620 if (status) 620 if (status)
621 pr_debug("can't register OHCI device, %d\n", status); 621 pr_debug("can't register OHCI device, %d\n", status);
@@ -626,8 +626,8 @@ omap_otg_init(struct omap_usb_config *config)
626 if (config->otg) { 626 if (config->otg) {
627 syscon &= ~OTG_IDLE_EN; 627 syscon &= ~OTG_IDLE_EN;
628 otg_device.dev.platform_data = config; 628 otg_device.dev.platform_data = config;
629 if (cpu_is_omap730()) 629 if (cpu_is_omap7xx())
630 otg_resources[1].start = INT_730_USB_OTG; 630 otg_resources[1].start = INT_7XX_USB_OTG;
631 status = platform_device_register(&otg_device); 631 status = platform_device_register(&otg_device);
632 if (status) 632 if (status)
633 pr_debug("can't register OTG device, %d\n", status); 633 pr_debug("can't register OTG device, %d\n", status);
@@ -731,7 +731,7 @@ static inline void omap_1510_usb_init(struct omap_usb_config *config) {}
731 731
732void __init omap_usb_init(struct omap_usb_config *pdata) 732void __init omap_usb_init(struct omap_usb_config *pdata)
733{ 733{
734 if (cpu_is_omap730() || cpu_is_omap16xx() || cpu_is_omap24xx()) 734 if (cpu_is_omap7xx() || cpu_is_omap16xx() || cpu_is_omap24xx())
735 omap_otg_init(pdata); 735 omap_otg_init(pdata);
736 else if (cpu_is_omap15xx()) 736 else if (cpu_is_omap15xx())
737 omap_1510_usb_init(pdata); 737 omap_1510_usb_init(pdata);
diff --git a/drivers/spi/omap_uwire.c b/drivers/spi/omap_uwire.c
index e75ba9b2889..7bcf409792c 100644
--- a/drivers/spi/omap_uwire.c
+++ b/drivers/spi/omap_uwire.c
@@ -52,7 +52,7 @@
52#include <asm/mach-types.h> 52#include <asm/mach-types.h>
53 53
54#include <mach/mux.h> 54#include <mach/mux.h>
55#include <mach/omap730.h> /* OMAP730_IO_CONF registers */ 55#include <mach/omap7xx.h> /* OMAP7XX_IO_CONF registers */
56 56
57 57
58/* FIXME address is now a platform device resource, 58/* FIXME address is now a platform device resource,
@@ -504,7 +504,7 @@ static int __init uwire_probe(struct platform_device *pdev)
504 } 504 }
505 clk_enable(uwire->ck); 505 clk_enable(uwire->ck);
506 506
507 if (cpu_is_omap730()) 507 if (cpu_is_omap7xx())
508 uwire_idx_shift = 1; 508 uwire_idx_shift = 1;
509 else 509 else
510 uwire_idx_shift = 2; 510 uwire_idx_shift = 2;
@@ -573,8 +573,8 @@ static int __init omap_uwire_init(void)
573 } 573 }
574 if (machine_is_omap_perseus2()) { 574 if (machine_is_omap_perseus2()) {
575 /* configure pins: MPU_UW_nSCS1, MPU_UW_SDO, MPU_UW_SCLK */ 575 /* configure pins: MPU_UW_nSCS1, MPU_UW_SDO, MPU_UW_SCLK */
576 int val = omap_readl(OMAP730_IO_CONF_9) & ~0x00EEE000; 576 int val = omap_readl(OMAP7XX_IO_CONF_9) & ~0x00EEE000;
577 omap_writel(val | 0x00AAA000, OMAP730_IO_CONF_9); 577 omap_writel(val | 0x00AAA000, OMAP7XX_IO_CONF_9);
578 } 578 }
579 579
580 return platform_driver_probe(&uwire_driver, uwire_probe); 580 return platform_driver_probe(&uwire_driver, uwire_probe);
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-19 12:49:00 -0400