diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2011-02-11 19:13:53 -0500 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2011-02-11 19:13:53 -0500 |
commit | a288465fa86731108c0ee590da505abe65480473 (patch) | |
tree | fb3ea0025fa4084dc7a5762a783f635affe39d5e | |
parent | 80d02d273641d515269c016d9e8da5882e4432e4 (diff) | |
parent | 0eb6aaf52965c14ba3ea245448c4806cfcd1d18c (diff) |
Merge branch 'next' of git://git.monstr.eu/linux-2.6-microblaze
* 'next' of git://git.monstr.eu/linux-2.6-microblaze:
microblaze: Fix msr instruction detection
microblaze: Fix pte_update function
microblaze: Fix asm compilation warning
microblaze: Fix IRQ flag handling for MSR=0
-rw-r--r-- | arch/microblaze/include/asm/irqflags.h | 2 | ||||
-rw-r--r-- | arch/microblaze/include/asm/pgtable.h | 27 | ||||
-rw-r--r-- | arch/microblaze/kernel/cpu/pvr.c | 4 | ||||
-rw-r--r-- | arch/microblaze/kernel/head.S | 15 | ||||
-rw-r--r-- | arch/microblaze/kernel/setup.c | 4 |
5 files changed, 25 insertions, 27 deletions
diff --git a/arch/microblaze/include/asm/irqflags.h b/arch/microblaze/include/asm/irqflags.h index 5fd31905775..c4532f032b3 100644 --- a/arch/microblaze/include/asm/irqflags.h +++ b/arch/microblaze/include/asm/irqflags.h | |||
@@ -12,7 +12,7 @@ | |||
12 | #include <linux/types.h> | 12 | #include <linux/types.h> |
13 | #include <asm/registers.h> | 13 | #include <asm/registers.h> |
14 | 14 | ||
15 | #ifdef CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR | 15 | #if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR |
16 | 16 | ||
17 | static inline unsigned long arch_local_irq_save(void) | 17 | static inline unsigned long arch_local_irq_save(void) |
18 | { | 18 | { |
diff --git a/arch/microblaze/include/asm/pgtable.h b/arch/microblaze/include/asm/pgtable.h index b23f6807587..885574a73f0 100644 --- a/arch/microblaze/include/asm/pgtable.h +++ b/arch/microblaze/include/asm/pgtable.h | |||
@@ -411,20 +411,19 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) | |||
411 | static inline unsigned long pte_update(pte_t *p, unsigned long clr, | 411 | static inline unsigned long pte_update(pte_t *p, unsigned long clr, |
412 | unsigned long set) | 412 | unsigned long set) |
413 | { | 413 | { |
414 | unsigned long old, tmp, msr; | 414 | unsigned long flags, old, tmp; |
415 | 415 | ||
416 | __asm__ __volatile__("\ | 416 | raw_local_irq_save(flags); |
417 | msrclr %2, 0x2\n\ | 417 | |
418 | nop\n\ | 418 | __asm__ __volatile__( "lw %0, %2, r0 \n" |
419 | lw %0, %4, r0\n\ | 419 | "andn %1, %0, %3 \n" |
420 | andn %1, %0, %5\n\ | 420 | "or %1, %1, %4 \n" |
421 | or %1, %1, %6\n\ | 421 | "sw %1, %2, r0 \n" |
422 | sw %1, %4, r0\n\ | 422 | : "=&r" (old), "=&r" (tmp) |
423 | mts rmsr, %2\n\ | 423 | : "r" ((unsigned long)(p + 1) - 4), "r" (clr), "r" (set) |
424 | nop" | 424 | : "cc"); |
425 | : "=&r" (old), "=&r" (tmp), "=&r" (msr), "=m" (*p) | 425 | |
426 | : "r" ((unsigned long)(p + 1) - 4), "r" (clr), "r" (set), "m" (*p) | 426 | raw_local_irq_restore(flags); |
427 | : "cc"); | ||
428 | 427 | ||
429 | return old; | 428 | return old; |
430 | } | 429 | } |
diff --git a/arch/microblaze/kernel/cpu/pvr.c b/arch/microblaze/kernel/cpu/pvr.c index e01afa68273..488c1ed24e3 100644 --- a/arch/microblaze/kernel/cpu/pvr.c +++ b/arch/microblaze/kernel/cpu/pvr.c | |||
@@ -27,7 +27,7 @@ | |||
27 | register unsigned tmp __asm__("r3"); \ | 27 | register unsigned tmp __asm__("r3"); \ |
28 | tmp = 0x0; /* Prevent warning about unused */ \ | 28 | tmp = 0x0; /* Prevent warning about unused */ \ |
29 | __asm__ __volatile__ ( \ | 29 | __asm__ __volatile__ ( \ |
30 | "mfs %0, rpvr" #pvrid ";" \ | 30 | "mfs %0, rpvr" #pvrid ";" \ |
31 | : "=r" (tmp) : : "memory"); \ | 31 | : "=r" (tmp) : : "memory"); \ |
32 | val = tmp; \ | 32 | val = tmp; \ |
33 | } | 33 | } |
@@ -54,7 +54,7 @@ int cpu_has_pvr(void) | |||
54 | if (!(flags & PVR_MSR_BIT)) | 54 | if (!(flags & PVR_MSR_BIT)) |
55 | return 0; | 55 | return 0; |
56 | 56 | ||
57 | get_single_pvr(0x00, pvr0); | 57 | get_single_pvr(0, pvr0); |
58 | pr_debug("%s: pvr0 is 0x%08x\n", __func__, pvr0); | 58 | pr_debug("%s: pvr0 is 0x%08x\n", __func__, pvr0); |
59 | 59 | ||
60 | if (pvr0 & PVR0_PVR_FULL_MASK) | 60 | if (pvr0 & PVR0_PVR_FULL_MASK) |
diff --git a/arch/microblaze/kernel/head.S b/arch/microblaze/kernel/head.S index 0db20b5abb5..778a5ce2e4f 100644 --- a/arch/microblaze/kernel/head.S +++ b/arch/microblaze/kernel/head.S | |||
@@ -62,15 +62,14 @@ real_start: | |||
62 | andi r1, r1, ~2 | 62 | andi r1, r1, ~2 |
63 | mts rmsr, r1 | 63 | mts rmsr, r1 |
64 | /* | 64 | /* |
65 | * Here is checking mechanism which check if Microblaze has msr instructions | 65 | * According to Xilinx, msrclr instruction behaves like 'mfs rX,rpc' |
66 | * We load msr and compare it with previous r1 value - if is the same, | 66 | * if the msrclr instruction is not enabled. We use this to detect |
67 | * msr instructions works if not - cpu don't have them. | 67 | * if the opcode is available, by issuing msrclr and then testing the result. |
68 | * r8 == 0 - msr instructions are implemented | ||
69 | * r8 != 0 - msr instructions are not implemented | ||
68 | */ | 70 | */ |
69 | /* r8=0 - I have msr instr, 1 - I don't have them */ | 71 | msrclr r8, 0 /* clear nothing - just read msr for test */ |
70 | rsubi r0, r0, 1 /* set the carry bit */ | 72 | cmpu r8, r8, r1 /* r1 must contain msr reg content */ |
71 | msrclr r0, 0x4 /* try to clear it */ | ||
72 | /* read the carry bit, r8 will be '0' if msrclr exists */ | ||
73 | addik r8, r0, 0 | ||
74 | 73 | ||
75 | /* r7 may point to an FDT, or there may be one linked in. | 74 | /* r7 may point to an FDT, or there may be one linked in. |
76 | if it's in r7, we've got to save it away ASAP. | 75 | if it's in r7, we've got to save it away ASAP. |
diff --git a/arch/microblaze/kernel/setup.c b/arch/microblaze/kernel/setup.c index bb1558e4b28..9312fbb37ef 100644 --- a/arch/microblaze/kernel/setup.c +++ b/arch/microblaze/kernel/setup.c | |||
@@ -161,11 +161,11 @@ void __init machine_early_init(const char *cmdline, unsigned int ram, | |||
161 | #if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR | 161 | #if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR |
162 | if (msr) | 162 | if (msr) |
163 | eprintk("!!!Your kernel has setup MSR instruction but " | 163 | eprintk("!!!Your kernel has setup MSR instruction but " |
164 | "CPU don't have it %d\n", msr); | 164 | "CPU don't have it %x\n", msr); |
165 | #else | 165 | #else |
166 | if (!msr) | 166 | if (!msr) |
167 | eprintk("!!!Your kernel not setup MSR instruction but " | 167 | eprintk("!!!Your kernel not setup MSR instruction but " |
168 | "CPU have it %d\n", msr); | 168 | "CPU have it %x\n", msr); |
169 | #endif | 169 | #endif |
170 | 170 | ||
171 | for (src = __ivt_start; src < __ivt_end; src++, dst++) | 171 | for (src = __ivt_start; src < __ivt_end; src++, dst++) |