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authorZang Roy-r61911 <tie-fei.zang@freescale.com>2007-03-09 00:27:28 -0500
committerKumar Gala <galak@kernel.crashing.org>2007-03-26 18:03:49 -0400
commit9eb90a0c3b333e27db74412833a36da3f27da6a3 (patch)
tree6837866f31059d9143405b3c908d29bc661ef9a6
parent3e4e97f42e134e1fe46bdf36bd5d874f5b4f8755 (diff)
[POWERPC] 86xx/85xx: Unify Freescale PCI Express memory map registers structure
Unify PCI Express memory map registers structure define to arch/pwoerpc/sysdev/fsl_pcie.h for Freescale 85xx/86xx processor family. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat
-rw-r--r--arch/powerpc/platforms/86xx/pci.c2
-rw-r--r--arch/powerpc/sysdev/fsl_pcie.h94
-rw-r--r--include/asm-powerpc/immap_86xx.h75
3 files changed, 95 insertions, 76 deletions
diff --git a/arch/powerpc/platforms/86xx/pci.c b/arch/powerpc/platforms/86xx/pci.c
index 481e18ed5be..ba86c48f446 100644
--- a/arch/powerpc/platforms/86xx/pci.c
+++ b/arch/powerpc/platforms/86xx/pci.c
@@ -22,9 +22,9 @@
22#include <asm/atomic.h> 22#include <asm/atomic.h>
23#include <asm/io.h> 23#include <asm/io.h>
24#include <asm/prom.h> 24#include <asm/prom.h>
25#include <asm/immap_86xx.h>
26#include <asm/pci-bridge.h> 25#include <asm/pci-bridge.h>
27#include <sysdev/fsl_soc.h> 26#include <sysdev/fsl_soc.h>
27#include <sysdev/fsl_pcie.h>
28 28
29#include "mpc86xx.h" 29#include "mpc86xx.h"
30 30
diff --git a/arch/powerpc/sysdev/fsl_pcie.h b/arch/powerpc/sysdev/fsl_pcie.h
new file mode 100644
index 00000000000..8d9779c84be
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_pcie.h
@@ -0,0 +1,94 @@
1/*
2 * MPC85xx/86xx PCI Express structure define
3 *
4 * Copyright 2007 Freescale Semiconductor, Inc
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 */
12
13#ifdef __KERNEL__
14#ifndef __POWERPC_FSL_PCIE_H
15#define __POWERPC_FSL_PCIE_H
16
17/* PCIE Express IO block registers in 85xx/86xx */
18
19struct ccsr_pex {
20 __be32 __iomem pex_config_addr; /* 0x.000 - PCI Express Configuration Address Register */
21 __be32 __iomem pex_config_data; /* 0x.004 - PCI Express Configuration Data Register */
22 u8 __iomem res1[4];
23 __be32 __iomem pex_otb_cpl_tor; /* 0x.00c - PCI Express Outbound completion timeout register */
24 __be32 __iomem pex_conf_tor; /* 0x.010 - PCI Express configuration timeout register */
25 u8 __iomem res2[12];
26 __be32 __iomem pex_pme_mes_dr; /* 0x.020 - PCI Express PME and message detect register */
27 __be32 __iomem pex_pme_mes_disr; /* 0x.024 - PCI Express PME and message disable register */
28 __be32 __iomem pex_pme_mes_ier; /* 0x.028 - PCI Express PME and message interrupt enable register */
29 __be32 __iomem pex_pmcr; /* 0x.02c - PCI Express power management command register */
30 u8 __iomem res3[3024];
31 __be32 __iomem pexotar0; /* 0x.c00 - PCI Express outbound translation address register 0 */
32 __be32 __iomem pexotear0; /* 0x.c04 - PCI Express outbound translation extended address register 0*/
33 u8 __iomem res4[8];
34 __be32 __iomem pexowar0; /* 0x.c10 - PCI Express outbound window attributes register 0*/
35 u8 __iomem res5[12];
36 __be32 __iomem pexotar1; /* 0x.c20 - PCI Express outbound translation address register 1 */
37 __be32 __iomem pexotear1; /* 0x.c24 - PCI Express outbound translation extended address register 1*/
38 __be32 __iomem pexowbar1; /* 0x.c28 - PCI Express outbound window base address register 1*/
39 u8 __iomem res6[4];
40 __be32 __iomem pexowar1; /* 0x.c30 - PCI Express outbound window attributes register 1*/
41 u8 __iomem res7[12];
42 __be32 __iomem pexotar2; /* 0x.c40 - PCI Express outbound translation address register 2 */
43 __be32 __iomem pexotear2; /* 0x.c44 - PCI Express outbound translation extended address register 2*/
44 __be32 __iomem pexowbar2; /* 0x.c48 - PCI Express outbound window base address register 2*/
45 u8 __iomem res8[4];
46 __be32 __iomem pexowar2; /* 0x.c50 - PCI Express outbound window attributes register 2*/
47 u8 __iomem res9[12];
48 __be32 __iomem pexotar3; /* 0x.c60 - PCI Express outbound translation address register 3 */
49 __be32 __iomem pexotear3; /* 0x.c64 - PCI Express outbound translation extended address register 3*/
50 __be32 __iomem pexowbar3; /* 0x.c68 - PCI Express outbound window base address register 3*/
51 u8 __iomem res10[4];
52 __be32 __iomem pexowar3; /* 0x.c70 - PCI Express outbound window attributes register 3*/
53 u8 __iomem res11[12];
54 __be32 __iomem pexotar4; /* 0x.c80 - PCI Express outbound translation address register 4 */
55 __be32 __iomem pexotear4; /* 0x.c84 - PCI Express outbound translation extended address register 4*/
56 __be32 __iomem pexowbar4; /* 0x.c88 - PCI Express outbound window base address register 4*/
57 u8 __iomem res12[4];
58 __be32 __iomem pexowar4; /* 0x.c90 - PCI Express outbound window attributes register 4*/
59 u8 __iomem res13[12];
60 u8 __iomem res14[256];
61 __be32 __iomem pexitar3; /* 0x.da0 - PCI Express inbound translation address register 3 */
62 u8 __iomem res15[4];
63 __be32 __iomem pexiwbar3; /* 0x.da8 - PCI Express inbound window base address register 3 */
64 __be32 __iomem pexiwbear3; /* 0x.dac - PCI Express inbound window base extended address register 3 */
65 __be32 __iomem pexiwar3; /* 0x.db0 - PCI Express inbound window attributes register 3 */
66 u8 __iomem res16[12];
67 __be32 __iomem pexitar2; /* 0x.dc0 - PCI Express inbound translation address register 2 */
68 u8 __iomem res17[4];
69 __be32 __iomem pexiwbar2; /* 0x.dc8 - PCI Express inbound window base address register 2 */
70 __be32 __iomem pexiwbear2; /* 0x.dcc - PCI Express inbound window base extended address register 2 */
71 __be32 __iomem pexiwar2; /* 0x.dd0 - PCI Express inbound window attributes register 2 */
72 u8 __iomem res18[12];
73 __be32 __iomem pexitar1; /* 0x.de0 - PCI Express inbound translation address register 2 */
74 u8 __iomem res19[4];
75 __be32 __iomem pexiwbar1; /* 0x.de8 - PCI Express inbound window base address register 2 */
76 __be32 __iomem pexiwbear1; /* 0x.dec - PCI Express inbound window base extended address register 2 */
77 __be32 __iomem pexiwar1; /* 0x.df0 - PCI Express inbound window attributes register 2 */
78 u8 __iomem res20[12];
79 __be32 __iomem pex_err_dr; /* 0x.e00 - PCI Express error detect register */
80 u8 __iomem res21[4];
81 __be32 __iomem pex_err_en; /* 0x.e08 - PCI Express error interrupt enable register */
82 u8 __iomem res22[4];
83 __be32 __iomem pex_err_disr; /* 0x.e10 - PCI Express error disable register */
84 u8 __iomem res23[12];
85 __be32 __iomem pex_err_cap_stat; /* 0x.e20 - PCI Express error capture status register */
86 u8 __iomem res24[4];
87 __be32 __iomem pex_err_cap_r0; /* 0x.e28 - PCI Express error capture register 0 */
88 __be32 __iomem pex_err_cap_r1; /* 0x.e2c - PCI Express error capture register 0 */
89 __be32 __iomem pex_err_cap_r2; /* 0x.e30 - PCI Express error capture register 0 */
90 __be32 __iomem pex_err_cap_r3; /* 0x.e34 - PCI Express error capture register 0 */
91};
92
93#endif /* __POWERPC_FSL_PCIE_H */
94#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/immap_86xx.h b/include/asm-powerpc/immap_86xx.h
index d905b662226..59b9e07b8e9 100644
--- a/include/asm-powerpc/immap_86xx.h
+++ b/include/asm-powerpc/immap_86xx.h
@@ -85,81 +85,6 @@ typedef struct ccsr_pci {
85 char res19[472]; 85 char res19[472];
86} ccsr_pci_t; 86} ccsr_pci_t;
87 87
88/* PCI Express Registers */
89typedef struct ccsr_pex {
90 uint pex_config_addr; /* 0x.000 - PCI Express Configuration Address Register */
91 uint pex_config_data; /* 0x.004 - PCI Express Configuration Data Register */
92 char res1[4];
93 uint pex_otb_cpl_tor; /* 0x.00c - PCI Express Outbound completion timeout register */
94 uint pex_conf_tor; /* 0x.010 - PCI Express configuration timeout register */
95 char res2[12];
96 uint pex_pme_mes_dr; /* 0x.020 - PCI Express PME and message detect register */
97 uint pex_pme_mes_disr; /* 0x.024 - PCI Express PME and message disable register */
98 uint pex_pme_mes_ier; /* 0x.028 - PCI Express PME and message interrupt enable register */
99 uint pex_pmcr; /* 0x.02c - PCI Express power management command register */
100 char res3[3024];
101 uint pexotar0; /* 0x.c00 - PCI Express outbound translation address register 0 */
102 uint pexotear0; /* 0x.c04 - PCI Express outbound translation extended address register 0*/
103 char res4[8];
104 uint pexowar0; /* 0x.c10 - PCI Express outbound window attributes register 0*/
105 char res5[12];
106 uint pexotar1; /* 0x.c20 - PCI Express outbound translation address register 1 */
107 uint pexotear1; /* 0x.c24 - PCI Express outbound translation extended address register 1*/
108 uint pexowbar1; /* 0x.c28 - PCI Express outbound window base address register 1*/
109 char res6[4];
110 uint pexowar1; /* 0x.c30 - PCI Express outbound window attributes register 1*/
111 char res7[12];
112 uint pexotar2; /* 0x.c40 - PCI Express outbound translation address register 2 */
113 uint pexotear2; /* 0x.c44 - PCI Express outbound translation extended address register 2*/
114 uint pexowbar2; /* 0x.c48 - PCI Express outbound window base address register 2*/
115 char res8[4];
116 uint pexowar2; /* 0x.c50 - PCI Express outbound window attributes register 2*/
117 char res9[12];
118 uint pexotar3; /* 0x.c60 - PCI Express outbound translation address register 3 */
119 uint pexotear3; /* 0x.c64 - PCI Express outbound translation extended address register 3*/
120 uint pexowbar3; /* 0x.c68 - PCI Express outbound window base address register 3*/
121 char res10[4];
122 uint pexowar3; /* 0x.c70 - PCI Express outbound window attributes register 3*/
123 char res11[12];
124 uint pexotar4; /* 0x.c80 - PCI Express outbound translation address register 4 */
125 uint pexotear4; /* 0x.c84 - PCI Express outbound translation extended address register 4*/
126 uint pexowbar4; /* 0x.c88 - PCI Express outbound window base address register 4*/
127 char res12[4];
128 uint pexowar4; /* 0x.c90 - PCI Express outbound window attributes register 4*/
129 char res13[12];
130 char res14[256];
131 uint pexitar3; /* 0x.da0 - PCI Express inbound translation address register 3 */
132 char res15[4];
133 uint pexiwbar3; /* 0x.da8 - PCI Express inbound window base address register 3 */
134 uint pexiwbear3; /* 0x.dac - PCI Express inbound window base extended address register 3 */
135 uint pexiwar3; /* 0x.db0 - PCI Express inbound window attributes register 3 */
136 char res16[12];
137 uint pexitar2; /* 0x.dc0 - PCI Express inbound translation address register 2 */
138 char res17[4];
139 uint pexiwbar2; /* 0x.dc8 - PCI Express inbound window base address register 2 */
140 uint pexiwbear2; /* 0x.dcc - PCI Express inbound window base extended address register 2 */
141 uint pexiwar2; /* 0x.dd0 - PCI Express inbound window attributes register 2 */
142 char res18[12];
143 uint pexitar1; /* 0x.de0 - PCI Express inbound translation address register 2 */
144 char res19[4];
145 uint pexiwbar1; /* 0x.de8 - PCI Express inbound window base address register 2 */
146 uint pexiwbear1; /* 0x.dec - PCI Express inbound window base extended address register 2 */
147 uint pexiwar1; /* 0x.df0 - PCI Express inbound window attributes register 2 */
148 char res20[12];
149 uint pex_err_dr; /* 0x.e00 - PCI Express error detect register */
150 char res21[4];
151 uint pex_err_en; /* 0x.e08 - PCI Express error interrupt enable register */
152 char res22[4];
153 uint pex_err_disr; /* 0x.e10 - PCI Express error disable register */
154 char res23[12];
155 uint pex_err_cap_stat; /* 0x.e20 - PCI Express error capture status register */
156 char res24[4];
157 uint pex_err_cap_r0; /* 0x.e28 - PCI Express error capture register 0 */
158 uint pex_err_cap_r1; /* 0x.e2c - PCI Express error capture register 0 */
159 uint pex_err_cap_r2; /* 0x.e30 - PCI Express error capture register 0 */
160 uint pex_err_cap_r3; /* 0x.e34 - PCI Express error capture register 0 */
161} ccsr_pex_t;
162
163/* Global Utility Registers */ 88/* Global Utility Registers */
164typedef struct ccsr_guts { 89typedef struct ccsr_guts {
165 uint porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */ 90 uint porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-11 19:44:23 -0500