Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
  [MIPS] cevt-txx9: Reset timer counter on initialization
  [MIPS] IP22: Fix crashes due to wrong L1_CACHE_BYTES
  [MIPS] IP32: Fix unexpected irq 71

3 files changed, 9 insertions, 1 deletions

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index e5a7c5d9636..24c5dee9176 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1006,7 +1006,7 @@ config BOOT_ELF32
 config MIPS_L1_CACHE_SHIFT
         int
         default "4" if MACH_DECSTATION
-        default "7" if SGI_IP27 || SGI_IP28 || SNI_RM
+        default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM
         default "4" if PMC_MSP4200_EVAL
         default "5"
 
diff --git a/arch/mips/kernel/cevt-txx9.c b/arch/mips/kernel/cevt-txx9.c
index 795cb8fb0d7..b5fc4eb412d 100644
--- a/arch/mips/kernel/cevt-txx9.c
+++ b/arch/mips/kernel/cevt-txx9.c
@@ -161,6 +161,9 @@ void __init txx9_tmr_init(unsigned long baseaddr)
         struct txx9_tmr_reg __iomem *tmrptr;
 
         tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));
+        /* Start once to make CounterResetEnable effective */
+        __raw_writel(TXx9_TMTCR_CRE | TXx9_TMTCR_TCE, &tmrptr->tcr);
+        /* Stop and reset the counter */
         __raw_writel(TXx9_TMTCR_CRE, &tmrptr->tcr);
         __raw_writel(0, &tmrptr->tisr);
         __raw_writel(0xffffffff, &tmrptr->cpra);
diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c
index b0ea0e43ba4..0d6b6663d5f 100644
--- a/arch/mips/sgi-ip32/ip32-irq.c
+++ b/arch/mips/sgi-ip32/ip32-irq.c
@@ -425,6 +425,11 @@ static void ip32_irq0(void)
         BUILD_BUG_ON(MACEISA_SERIAL2_RDMAOR_IRQ - MACEISA_AUDIO_SW_IRQ != 31);
 
         crime_int = crime->istat & crime_mask;
+
+        /* crime sometime delivers spurious interrupts, ignore them */
+        if (unlikely(crime_int == 0))
+                return;
+
         irq = MACE_VID_IN1_IRQ + __ffs(crime_int);
 
         if (crime_int & CRIME_MACEISA_INT_MASK) {