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authorMatthew Wilcox <matthew.r.wilcox@intel.com>2011-03-22 15:55:45 -0400
committerMatthew Wilcox <matthew.r.wilcox@intel.com>2011-11-04 15:53:01 -0400
commit7f53f9d2424533256ae86f7df5661a17de743de8 (patch)
tree93dc08a0de9ac52dca9479dc6c36808f431c1988
parent8ef700678f65e2eef1c3a94cdedb79d757608392 (diff)
NVMe: Correct the Controller Configuration settings
The arbitration field was extended by one bit, shifting the shutdown notification bits by one. Also, the SQ/CQ entry size was made configurable for future extensions. Reported-by: Paul Luse <paul.e.luse@intel.com> Signed-off-by: Matthew Wilcox <matthew.r.wilcox@intel.com>
-rw-r--r--drivers/block/nvme.c1
-rw-r--r--include/linux/nvme.h10
2 files changed, 7 insertions, 4 deletions
diff --git a/drivers/block/nvme.c b/drivers/block/nvme.c
index d3eeca5a3c4..014a7f6e39b 100644
--- a/drivers/block/nvme.c
+++ b/drivers/block/nvme.c
@@ -905,6 +905,7 @@ static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev)
905 dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM; 905 dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
906 dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT; 906 dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
907 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE; 907 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
908 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
908 909
909 writel(0, &dev->bar->cc); 910 writel(0, &dev->bar->cc);
910 writel(aqa, &dev->bar->aqa); 911 writel(aqa, &dev->bar->aqa);
diff --git a/include/linux/nvme.h b/include/linux/nvme.h
index 347ad5f9a72..9d6febb9152 100644
--- a/include/linux/nvme.h
+++ b/include/linux/nvme.h
@@ -41,10 +41,12 @@ enum {
41 NVME_CC_MPS_SHIFT = 7, 41 NVME_CC_MPS_SHIFT = 7,
42 NVME_CC_ARB_RR = 0 << 11, 42 NVME_CC_ARB_RR = 0 << 11,
43 NVME_CC_ARB_WRRU = 1 << 11, 43 NVME_CC_ARB_WRRU = 1 << 11,
44 NVME_CC_ARB_VS = 3 << 11, 44 NVME_CC_ARB_VS = 7 << 11,
45 NVME_CC_SHN_NONE = 0 << 13, 45 NVME_CC_SHN_NONE = 0 << 14,
46 NVME_CC_SHN_NORMAL = 1 << 13, 46 NVME_CC_SHN_NORMAL = 1 << 14,
47 NVME_CC_SHN_ABRUPT = 2 << 13, 47 NVME_CC_SHN_ABRUPT = 2 << 14,
48 NVME_CC_IOSQES = 6 << 16,
49 NVME_CC_IOCQES = 4 << 20,
48 NVME_CSTS_RDY = 1 << 0, 50 NVME_CSTS_RDY = 1 << 0,
49 NVME_CSTS_CFS = 1 << 1, 51 NVME_CSTS_CFS = 1 << 1,
50 NVME_CSTS_SHST_NORMAL = 0 << 2, 52 NVME_CSTS_SHST_NORMAL = 0 << 2,