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authorLinus Torvalds <torvalds@linux-foundation.org>2012-03-28 17:08:46 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-03-28 17:08:46 -0400
commit7bf97e1d5a94b6a71815771bb9452fc2c022c966 (patch)
treef89082dbd33a51a79c9a9c0dddb29e2b11b8207e
parent30304e5a79d424eb2c8707b3ff0e9b8bf6ab3e8f (diff)
parentc77c8a6fd3d57b586ff5ecb5ab5b32ca4f54fe75 (diff)
Merge tag 'gpio-for-linus' of git://git.secretlab.ca/git/linux-2.6
Pull GPIO changes for v3.4 from Grant Likely: "Primarily gpio device driver changes with some minor side effects under arch/arm and arch/x86. Also includes a few core changes such as explicitly supporting (electrical) open source and open drain outputs and some help for parsing gpio devicetree properties." Fix up context conflict due to Laxman Dewangan adding sleep control for the tps65910 driver separately for gpio's and regulators. * tag 'gpio-for-linus' of git://git.secretlab.ca/git/linux-2.6: (34 commits) gpio/ep93xx: Remove unused inline function and useless pr_err message gpio/sodaville: Mark broken due to core irqdomain migration gpio/omap: fix redundant decoding of gpio offset gpio/omap: fix incorrect update to context.irqenable1 gpio/omap: fix incorrect context restore logic in omap_gpio_runtime_* gpio/omap: fix missing dataout context save in _set_gpio_dataout_reg gpio/omap: fix _set_gpio_irqenable implementation gpio/omap: fix trigger type to unsigned gpio/omap: fix wakeup_en register update in _set_gpio_wakeup() gpio: tegra: tegra_gpio_config shouldn't be __init gpio/davinci: fix enabling unbanked GPIO IRQs gpio/davinci: fix oops on unbanked gpio irq request gpio/omap: Fix section warning for omap_mpuio_alloc_gc() ARM: tegra: export tegra_gpio_{en,dis}able gpio/gpio-stmpe: Fix the value returned by _get_value routine Documentation/gpio.txt: Explain expected pinctrl interaction GPIO: LPC32xx: Add output reading to GPO P3 GPIO: LPC32xx: Fix missing bit selection mask gpio/omap: fix wakeups on level-triggered GPIOs gpio/omap: Fix IRQ handling for SPARSE_IRQ ...
Diffstat
-rw-r--r--Documentation/devicetree/bindings/gpio/gpio-omap.txt36
-rw-r--r--Documentation/devicetree/bindings/gpio/sodaville.txt48
-rw-r--r--Documentation/gpio.txt40
-rw-r--r--arch/arm/plat-omap/include/plat/gpio.h22
-rw-r--r--arch/x86/platform/ce4100/falconfalls.dts7
-rw-r--r--drivers/gpio/Kconfig14
-rw-r--r--drivers/gpio/Makefile2
-rw-r--r--drivers/gpio/gpio-davinci.c26
-rw-r--r--drivers/gpio/gpio-ep93xx.c8
-rw-r--r--drivers/gpio/gpio-lpc32xx.c19
-rw-r--r--drivers/gpio/gpio-mc9s08dz60.c161
-rw-r--r--drivers/gpio/gpio-omap.c291
-rw-r--r--drivers/gpio/gpio-pl061.c7
-rw-r--r--drivers/gpio/gpio-sodaville.c302
-rw-r--r--drivers/gpio/gpio-stmpe.c2
-rw-r--r--drivers/gpio/gpio-tegra.c4
-rw-r--r--drivers/gpio/gpio-tps65910.c20
-rw-r--r--drivers/gpio/gpiolib.c98
-rw-r--r--drivers/of/gpio.c11
-rw-r--r--include/asm-generic/gpio.h4
-rw-r--r--include/linux/gpio.h6
-rw-r--r--include/linux/mfd/tps65910.h8
-rw-r--r--include/linux/of_gpio.h27
23 files changed, 1017 insertions, 146 deletions
diff --git a/Documentation/devicetree/bindings/gpio/gpio-omap.txt b/Documentation/devicetree/bindings/gpio/gpio-omap.txt
new file mode 100644
index 00000000000..bff51a2fee1
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-omap.txt
@@ -0,0 +1,36 @@
1OMAP GPIO controller bindings
2
3Required properties:
4- compatible:
5 - "ti,omap2-gpio" for OMAP2 controllers
6 - "ti,omap3-gpio" for OMAP3 controllers
7 - "ti,omap4-gpio" for OMAP4 controllers
8- #gpio-cells : Should be two.
9 - first cell is the pin number
10 - second cell is used to specify optional parameters (unused)
11- gpio-controller : Marks the device node as a GPIO controller.
12- #interrupt-cells : Should be 2.
13- interrupt-controller: Mark the device node as an interrupt controller
14 The first cell is the GPIO number.
15 The second cell is used to specify flags:
16 bits[3:0] trigger type and level flags:
17 1 = low-to-high edge triggered.
18 2 = high-to-low edge triggered.
19 4 = active high level-sensitive.
20 8 = active low level-sensitive.
21
22OMAP specific properties:
23- ti,hwmods: Name of the hwmod associated to the GPIO:
24 "gpio<X>", <X> being the 1-based instance number from the HW spec
25
26
27Example:
28
29gpio4: gpio4 {
30 compatible = "ti,omap4-gpio";
31 ti,hwmods = "gpio4";
32 #gpio-cells = <2>;
33 gpio-controller;
34 #interrupt-cells = <2>;
35 interrupt-controller;
36};
diff --git a/Documentation/devicetree/bindings/gpio/sodaville.txt b/Documentation/devicetree/bindings/gpio/sodaville.txt
new file mode 100644
index 00000000000..563eff22b97
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/sodaville.txt
@@ -0,0 +1,48 @@
1GPIO controller on CE4100 / Sodaville SoCs
2==========================================
3
4The bindings for CE4100's GPIO controller match the generic description
5which is covered by the gpio.txt file in this folder.
6
7The only additional property is the intel,muxctl property which holds the
8value which is written into the MUXCNTL register.
9
10There is no compatible property for now because the driver is probed via
11PCI id (vendor 0x8086 device 0x2e67).
12
13The interrupt specifier consists of two cells encoded as follows:
14 - <1st cell>: The interrupt-number that identifies the interrupt source.
15 - <2nd cell>: The level-sense information, encoded as follows:
16 4 - active high level-sensitive
17 8 - active low level-sensitive
18
19Example of the GPIO device and one user:
20
21 pcigpio: gpio@b,1 {
22 /* two cells for GPIO and interrupt */
23 #gpio-cells = <2>;
24 #interrupt-cells = <2>;
25 compatible = "pci8086,2e67.2",
26 "pci8086,2e67",
27 "pciclassff0000",
28 "pciclassff00";
29
30 reg = <0x15900 0x0 0x0 0x0 0x0>;
31 /* Interrupt line of the gpio device */
32 interrupts = <15 1>;
33 /* It is an interrupt and GPIO controller itself */
34 interrupt-controller;
35 gpio-controller;
36 intel,muxctl = <0>;
37 };
38
39 testuser@20 {
40 compatible = "example,testuser";
41 /* User the 11th GPIO line as an active high triggered
42 * level interrupt
43 */
44 interrupts = <11 8>;
45 interrupt-parent = <&pcigpio>;
46 /* Use this GPIO also with the gpio functions */
47 gpios = <&pcigpio 11 0>;
48 };
diff --git a/Documentation/gpio.txt b/Documentation/gpio.txt
index 792faa3c06c..620a07844e8 100644
--- a/Documentation/gpio.txt
+++ b/Documentation/gpio.txt
@@ -271,9 +271,26 @@ Some platforms may also use knowledge about what GPIOs are active for
271power management, such as by powering down unused chip sectors and, more 271power management, such as by powering down unused chip sectors and, more
272easily, gating off unused clocks. 272easily, gating off unused clocks.
273 273
274Note that requesting a GPIO does NOT cause it to be configured in any 274For GPIOs that use pins known to the pinctrl subsystem, that subsystem should
275way; it just marks that GPIO as in use. Separate code must handle any 275be informed of their use; a gpiolib driver's .request() operation may call
276pin setup (e.g. controlling which pin the GPIO uses, pullup/pulldown). 276pinctrl_request_gpio(), and a gpiolib driver's .free() operation may call
277pinctrl_free_gpio(). The pinctrl subsystem allows a pinctrl_request_gpio()
278to succeed concurrently with a pin or pingroup being "owned" by a device for
279pin multiplexing.
280
281Any programming of pin multiplexing hardware that is needed to route the
282GPIO signal to the appropriate pin should occur within a GPIO driver's
283.direction_input() or .direction_output() operations, and occur after any
284setup of an output GPIO's value. This allows a glitch-free migration from a
285pin's special function to GPIO. This is sometimes required when using a GPIO
286to implement a workaround on signals typically driven by a non-GPIO HW block.
287
288Some platforms allow some or all GPIO signals to be routed to different pins.
289Similarly, other aspects of the GPIO or pin may need to be configured, such as
290pullup/pulldown. Platform software should arrange that any such details are
291configured prior to gpio_request() being called for those GPIOs, e.g. using
292the pinctrl subsystem's mapping table, so that GPIO users need not be aware
293of these details.
277 294
278Also note that it's your responsibility to have stopped using a GPIO 295Also note that it's your responsibility to have stopped using a GPIO
279before you free it. 296before you free it.
@@ -302,6 +319,8 @@ where 'flags' is currently defined to specify the following properties:
302 319
303 * GPIOF_INIT_LOW - as output, set initial level to LOW 320 * GPIOF_INIT_LOW - as output, set initial level to LOW
304 * GPIOF_INIT_HIGH - as output, set initial level to HIGH 321 * GPIOF_INIT_HIGH - as output, set initial level to HIGH
322 * GPIOF_OPEN_DRAIN - gpio pin is open drain type.
323 * GPIOF_OPEN_SOURCE - gpio pin is open source type.
305 324
306since GPIOF_INIT_* are only valid when configured as output, so group valid 325since GPIOF_INIT_* are only valid when configured as output, so group valid
307combinations as: 326combinations as:
@@ -310,8 +329,19 @@ combinations as:
310 * GPIOF_OUT_INIT_LOW - configured as output, initial level LOW 329 * GPIOF_OUT_INIT_LOW - configured as output, initial level LOW
311 * GPIOF_OUT_INIT_HIGH - configured as output, initial level HIGH 330 * GPIOF_OUT_INIT_HIGH - configured as output, initial level HIGH
312 331
313In the future, these flags can be extended to support more properties such 332When setting the flag as GPIOF_OPEN_DRAIN then it will assume that pins is
314as open-drain status. 333open drain type. Such pins will not be driven to 1 in output mode. It is
334require to connect pull-up on such pins. By enabling this flag, gpio lib will
335make the direction to input when it is asked to set value of 1 in output mode
336to make the pin HIGH. The pin is make to LOW by driving value 0 in output mode.
337
338When setting the flag as GPIOF_OPEN_SOURCE then it will assume that pins is
339open source type. Such pins will not be driven to 0 in output mode. It is
340require to connect pull-down on such pin. By enabling this flag, gpio lib will
341make the direction to input when it is asked to set value of 0 in output mode
342to make the pin LOW. The pin is make to HIGH by driving value 1 in output mode.
343
344In the future, these flags can be extended to support more properties.
315 345
316Further more, to ease the claim/release of multiple GPIOs, 'struct gpio' is 346Further more, to ease the claim/release of multiple GPIOs, 'struct gpio' is
317introduced to encapsulate all three fields as: 347introduced to encapsulate all three fields as:
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index cb75b657b04..b8a96c6a1a3 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -218,30 +218,14 @@ extern void omap_set_gpio_debounce(int gpio, int enable);
218extern void omap_set_gpio_debounce_time(int gpio, int enable); 218extern void omap_set_gpio_debounce_time(int gpio, int enable);
219/*-------------------------------------------------------------------------*/ 219/*-------------------------------------------------------------------------*/
220 220
221/* Wrappers for "new style" GPIO calls, using the new infrastructure 221/*
222 * Wrappers for "new style" GPIO calls, using the new infrastructure
222 * which lets us plug in FPGA, I2C, and other implementations. 223 * which lets us plug in FPGA, I2C, and other implementations.
223 * * 224 *
224 * The original OMAP-specific calls should eventually be removed. 225 * The original OMAP-specific calls should eventually be removed.
225 */ 226 */
226 227
227#include <linux/errno.h> 228#include <linux/errno.h>
228#include <asm-generic/gpio.h> 229#include <asm-generic/gpio.h>
229 230
230static inline int irq_to_gpio(unsigned irq)
231{
232 int tmp;
233
234 /* omap1 SOC mpuio */
235 if (cpu_class_is_omap1() && (irq < (IH_MPUIO_BASE + 16)))
236 return (irq - IH_MPUIO_BASE) + OMAP_MAX_GPIO_LINES;
237
238 /* SOC gpio */
239 tmp = irq - IH_GPIO_BASE;
240 if (tmp < OMAP_MAX_GPIO_LINES)
241 return tmp;
242
243 /* we don't supply reverse mappings for non-SOC gpios */
244 return -EIO;
245}
246
247#endif 231#endif
diff --git a/arch/x86/platform/ce4100/falconfalls.dts b/arch/x86/platform/ce4100/falconfalls.dts
index e70be38ce03..ce874f872cc 100644
--- a/arch/x86/platform/ce4100/falconfalls.dts
+++ b/arch/x86/platform/ce4100/falconfalls.dts
@@ -208,16 +208,19 @@
208 interrupts = <14 1>; 208 interrupts = <14 1>;
209 }; 209 };
210 210
211 gpio@b,1 { 211 pcigpio: gpio@b,1 {
212 #gpio-cells = <2>;
213 #interrupt-cells = <2>;
212 compatible = "pci8086,2e67.2", 214 compatible = "pci8086,2e67.2",
213 "pci8086,2e67", 215 "pci8086,2e67",
214 "pciclassff0000", 216 "pciclassff0000",
215 "pciclassff00"; 217 "pciclassff00";
216 218
217 #gpio-cells = <2>;
218 reg = <0x15900 0x0 0x0 0x0 0x0>; 219 reg = <0x15900 0x0 0x0 0x0 0x0>;
219 interrupts = <15 1>; 220 interrupts = <15 1>;
221 interrupt-controller;
220 gpio-controller; 222 gpio-controller;
223 intel,muxctl = <0>;
221 }; 224 };
222 225
223 i2c-controller@b,2 { 226 i2c-controller@b,2 {
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 0409cf35add..edadbdad31d 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -236,6 +236,12 @@ config GPIO_MAX732X_IRQ
236 Say yes here to enable the max732x to be used as an interrupt 236 Say yes here to enable the max732x to be used as an interrupt
237 controller. It requires the driver to be built in the kernel. 237 controller. It requires the driver to be built in the kernel.
238 238
239config GPIO_MC9S08DZ60
240 bool "MX35 3DS BOARD MC9S08DZ60 GPIO functions"
241 depends on I2C && MACH_MX35_3DS
242 help
243 Select this to enable the MC9S08DZ60 GPIO driver
244
239config GPIO_PCA953X 245config GPIO_PCA953X
240 tristate "PCA953x, PCA955x, TCA64xx, and MAX7310 I/O ports" 246 tristate "PCA953x, PCA955x, TCA64xx, and MAX7310 I/O ports"
241 depends on I2C 247 depends on I2C
@@ -422,6 +428,14 @@ config GPIO_ML_IOH
422 Hub) which is for IVI(In-Vehicle Infotainment) use. 428 Hub) which is for IVI(In-Vehicle Infotainment) use.
423 This driver can access the IOH's GPIO device. 429 This driver can access the IOH's GPIO device.
424 430
431config GPIO_SODAVILLE
432 bool "Intel Sodaville GPIO support"
433 depends on X86 && PCI && OF && BROKEN
434 select GPIO_GENERIC
435 select GENERIC_IRQ_CHIP
436 help
437 Say Y here to support Intel Sodaville GPIO.
438
425config GPIO_TIMBERDALE 439config GPIO_TIMBERDALE
426 bool "Support for timberdale GPIO IP" 440 bool "Support for timberdale GPIO IP"
427 depends on MFD_TIMBERDALE && HAS_IOMEM 441 depends on MFD_TIMBERDALE && HAS_IOMEM
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 9a8fb54ae46..007f54bd008 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_GPIO_MAX7300) += gpio-max7300.o
27obj-$(CONFIG_GPIO_MAX7301) += gpio-max7301.o 27obj-$(CONFIG_GPIO_MAX7301) += gpio-max7301.o
28obj-$(CONFIG_GPIO_MAX732X) += gpio-max732x.o 28obj-$(CONFIG_GPIO_MAX732X) += gpio-max732x.o
29obj-$(CONFIG_GPIO_MC33880) += gpio-mc33880.o 29obj-$(CONFIG_GPIO_MC33880) += gpio-mc33880.o
30obj-$(CONFIG_GPIO_MC9S08DZ60) += gpio-mc9s08dz60.o
30obj-$(CONFIG_GPIO_MCP23S08) += gpio-mcp23s08.o 31obj-$(CONFIG_GPIO_MCP23S08) += gpio-mcp23s08.o
31obj-$(CONFIG_GPIO_ML_IOH) += gpio-ml-ioh.o 32obj-$(CONFIG_GPIO_ML_IOH) += gpio-ml-ioh.o
32obj-$(CONFIG_GPIO_MPC5200) += gpio-mpc5200.o 33obj-$(CONFIG_GPIO_MPC5200) += gpio-mpc5200.o
@@ -46,6 +47,7 @@ obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o
46obj-$(CONFIG_PLAT_SAMSUNG) += gpio-samsung.o 47obj-$(CONFIG_PLAT_SAMSUNG) += gpio-samsung.o
47obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o 48obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o
48obj-$(CONFIG_GPIO_SCH) += gpio-sch.o 49obj-$(CONFIG_GPIO_SCH) += gpio-sch.o
50obj-$(CONFIG_GPIO_SODAVILLE) += gpio-sodaville.o
49obj-$(CONFIG_GPIO_STMPE) += gpio-stmpe.o 51obj-$(CONFIG_GPIO_STMPE) += gpio-stmpe.o
50obj-$(CONFIG_GPIO_SX150X) += gpio-sx150x.o 52obj-$(CONFIG_GPIO_SX150X) += gpio-sx150x.o
51obj-$(CONFIG_GPIO_TC3589X) += gpio-tc3589x.o 53obj-$(CONFIG_GPIO_TC3589X) += gpio-tc3589x.o
diff --git a/drivers/gpio/gpio-davinci.c b/drivers/gpio/gpio-davinci.c
index df0d59570a8..3d000169285 100644
--- a/drivers/gpio/gpio-davinci.c
+++ b/drivers/gpio/gpio-davinci.c
@@ -313,10 +313,16 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
313 return -ENODEV; 313 return -ENODEV;
314} 314}
315 315
316static int gpio_irq_type_unbanked(struct irq_data *d, unsigned trigger) 316static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
317{ 317{
318 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); 318 struct davinci_gpio_controller *d;
319 u32 mask = (u32) irq_data_get_irq_handler_data(d); 319 struct davinci_gpio_regs __iomem *g;
320 struct davinci_soc_info *soc_info = &davinci_soc_info;
321 u32 mask;
322
323 d = (struct davinci_gpio_controller *)data->handler_data;
324 g = (struct davinci_gpio_regs __iomem *)d->regs;
325 mask = __gpio_mask(data->irq - soc_info->gpio_irq);
320 326
321 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 327 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
322 return -EINVAL; 328 return -EINVAL;
@@ -380,7 +386,7 @@ static int __init davinci_gpio_irq_setup(void)
380 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs. 386 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
381 */ 387 */
382 if (soc_info->gpio_unbanked) { 388 if (soc_info->gpio_unbanked) {
383 static struct irq_chip gpio_irqchip_unbanked; 389 static struct irq_chip_type gpio_unbanked;
384 390
385 /* pass "bank 0" GPIO IRQs to AINTC */ 391 /* pass "bank 0" GPIO IRQs to AINTC */
386 chips[0].chip.to_irq = gpio_to_irq_unbanked; 392 chips[0].chip.to_irq = gpio_to_irq_unbanked;
@@ -388,9 +394,10 @@ static int __init davinci_gpio_irq_setup(void)
388 394
389 /* AINTC handles mask/unmask; GPIO handles triggering */ 395 /* AINTC handles mask/unmask; GPIO handles triggering */
390 irq = bank_irq; 396 irq = bank_irq;
391 gpio_irqchip_unbanked = *irq_get_chip(irq); 397 gpio_unbanked = *container_of(irq_get_chip(irq),
392 gpio_irqchip_unbanked.name = "GPIO-AINTC"; 398 struct irq_chip_type, chip);
393 gpio_irqchip_unbanked.irq_set_type = gpio_irq_type_unbanked; 399 gpio_unbanked.chip.name = "GPIO-AINTC";
400 gpio_unbanked.chip.irq_set_type = gpio_irq_type_unbanked;
394 401
395 /* default trigger: both edges */ 402 /* default trigger: both edges */
396 g = gpio2regs(0); 403 g = gpio2regs(0);
@@ -399,9 +406,8 @@ static int __init davinci_gpio_irq_setup(void)
399 406
400 /* set the direct IRQs up to use that irqchip */ 407 /* set the direct IRQs up to use that irqchip */
401 for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) { 408 for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
402 irq_set_chip(irq, &gpio_irqchip_unbanked); 409 irq_set_chip(irq, &gpio_unbanked.chip);
403 irq_set_handler_data(irq, (void *)__gpio_mask(gpio)); 410 irq_set_handler_data(irq, &chips[gpio / 32]);
404 irq_set_chip_data(irq, (__force void *)g);
405 irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH); 411 irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
406 } 412 }
407 413
diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c
index 4ca5642e977..776b772523e 100644
--- a/drivers/gpio/gpio-ep93xx.c
+++ b/drivers/gpio/gpio-ep93xx.c
@@ -12,8 +12,6 @@
12 * published by the Free Software Foundation. 12 * published by the Free Software Foundation.
13 */ 13 */
14 14
15#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
16
17#include <linux/init.h> 15#include <linux/init.h>
18#include <linux/module.h> 16#include <linux/module.h>
19#include <linux/platform_device.h> 17#include <linux/platform_device.h>
@@ -65,11 +63,6 @@ static void ep93xx_gpio_update_int_params(unsigned port)
65 EP93XX_GPIO_REG(int_en_register_offset[port])); 63 EP93XX_GPIO_REG(int_en_register_offset[port]));
66} 64}
67 65
68static inline void ep93xx_gpio_int_mask(unsigned line)
69{
70 gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
71}
72
73static void ep93xx_gpio_int_debounce(unsigned int irq, bool enable) 66static void ep93xx_gpio_int_debounce(unsigned int irq, bool enable)
74{ 67{
75 int line = irq_to_gpio(irq); 68 int line = irq_to_gpio(irq);
@@ -212,7 +205,6 @@ static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
212 handler = handle_edge_irq; 205 handler = handle_edge_irq;
213 break; 206 break;
214 default: 207 default:
215 pr_err("failed to set irq type %d for gpio %d\n", type, gpio);
216 return -EINVAL; 208 return -EINVAL;
217 } 209 }
218 210
diff --git a/drivers/gpio/gpio-lpc32xx.c b/drivers/gpio/gpio-lpc32xx.c
index ddfacc5ce56..61c2d08d37b 100644
--- a/drivers/gpio/gpio-lpc32xx.c
+++ b/drivers/gpio/gpio-lpc32xx.c
@@ -59,12 +59,14 @@
59#define GPO3_PIN_TO_BIT(x) (1 << (x)) 59#define GPO3_PIN_TO_BIT(x) (1 << (x))
60#define GPIO012_PIN_IN_SEL(x, y) (((x) >> (y)) & 1) 60#define GPIO012_PIN_IN_SEL(x, y) (((x) >> (y)) & 1)
61#define GPIO3_PIN_IN_SHIFT(x) ((x) == 5 ? 24 : 10 + (x)) 61#define GPIO3_PIN_IN_SHIFT(x) ((x) == 5 ? 24 : 10 + (x))
62#define GPIO3_PIN_IN_SEL(x, y) ((x) >> GPIO3_PIN_IN_SHIFT(y)) 62#define GPIO3_PIN_IN_SEL(x, y) (((x) >> GPIO3_PIN_IN_SHIFT(y)) & 1)
63#define GPIO3_PIN5_IN_SEL(x) (((x) >> 24) & 1) 63#define GPIO3_PIN5_IN_SEL(x) (((x) >> 24) & 1)
64#define GPI3_PIN_IN_SEL(x, y) (((x) >> (y)) & 1) 64#define GPI3_PIN_IN_SEL(x, y) (((x) >> (y)) & 1)
65#define GPO3_PIN_IN_SEL(x, y) (((x) >> (y)) & 1)
65 66
66struct gpio_regs { 67struct gpio_regs {
67 void __iomem *inp_state; 68 void __iomem *inp_state;
69 void __iomem *outp_state;
68 void __iomem *outp_set; 70 void __iomem *outp_set;
69 void __iomem *outp_clr; 71 void __iomem *outp_clr;
70 void __iomem *dir_set; 72 void __iomem *dir_set;
@@ -145,6 +147,7 @@ static struct gpio_regs gpio_grp_regs_p2 = {
145 147
146static struct gpio_regs gpio_grp_regs_p3 = { 148static struct gpio_regs gpio_grp_regs_p3 = {
147 .inp_state = LPC32XX_GPIO_P3_INP_STATE, 149 .inp_state = LPC32XX_GPIO_P3_INP_STATE,
150 .outp_state = LPC32XX_GPIO_P3_OUTP_STATE,
148 .outp_set = LPC32XX_GPIO_P3_OUTP_SET, 151 .outp_set = LPC32XX_GPIO_P3_OUTP_SET,
149 .outp_clr = LPC32XX_GPIO_P3_OUTP_CLR, 152 .outp_clr = LPC32XX_GPIO_P3_OUTP_CLR,
150 .dir_set = LPC32XX_GPIO_P2_DIR_SET, 153 .dir_set = LPC32XX_GPIO_P2_DIR_SET,
@@ -240,6 +243,12 @@ static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group,
240 return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin); 243 return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin);
241} 244}
242 245
246static int __get_gpo_state_p3(struct lpc32xx_gpio_chip *group,
247 unsigned pin)
248{
249 return GPO3_PIN_IN_SEL(__raw_readl(group->gpio_grp->outp_state), pin);
250}
251
243/* 252/*
244 * GENERIC_GPIO primitives. 253 * GENERIC_GPIO primitives.
245 */ 254 */
@@ -340,6 +349,13 @@ static void lpc32xx_gpo_set_value(struct gpio_chip *chip, unsigned pin,
340 __set_gpo_level_p3(group, pin, value); 349 __set_gpo_level_p3(group, pin, value);
341} 350}
342 351
352static int lpc32xx_gpo_get_value(struct gpio_chip *chip, unsigned pin)
353{
354 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
355
356 return __get_gpo_state_p3(group, pin);
357}
358
343static int lpc32xx_gpio_request(struct gpio_chip *chip, unsigned pin) 359static int lpc32xx_gpio_request(struct gpio_chip *chip, unsigned pin)
344{ 360{
345 if (pin < chip->ngpio) 361 if (pin < chip->ngpio)
@@ -427,6 +443,7 @@ static struct lpc32xx_gpio_chip lpc32xx_gpiochip[] = {
427 .label = "gpo_p3", 443 .label = "gpo_p3",
428 .direction_output = lpc32xx_gpio_dir_out_always, 444 .direction_output = lpc32xx_gpio_dir_out_always,
429 .set = lpc32xx_gpo_set_value, 445 .set = lpc32xx_gpo_set_value,
446 .get = lpc32xx_gpo_get_value,
430 .request = lpc32xx_gpio_request, 447 .request = lpc32xx_gpio_request,
431 .base = LPC32XX_GPO_P3_GRP, 448 .base = LPC32XX_GPO_P3_GRP,
432 .ngpio = LPC32XX_GPO_P3_MAX, 449 .ngpio = LPC32XX_GPO_P3_MAX,
diff --git a/drivers/gpio/gpio-mc9s08dz60.c b/drivers/gpio/gpio-mc9s08dz60.c
new file mode 100644
index 00000000000..2738cc44d63
--- /dev/null
+++ b/drivers/gpio/gpio-mc9s08dz60.c
@@ -0,0 +1,161 @@
1/*
2 * Copyright 2009-2012 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * Author: Wu Guoxing <b39297@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/slab.h>
20#include <linux/i2c.h>
21#include <linux/gpio.h>
22
23#define GPIO_GROUP_NUM 2
24#define GPIO_NUM_PER_GROUP 8
25#define GPIO_NUM (GPIO_GROUP_NUM*GPIO_NUM_PER_GROUP)
26
27struct mc9s08dz60 {
28 struct i2c_client *client;
29 struct gpio_chip chip;
30};
31
32static inline struct mc9s08dz60 *to_mc9s08dz60(struct gpio_chip *gc)
33{
34 return container_of(gc, struct mc9s08dz60, chip);
35}
36
37
38static void mc9s_gpio_to_reg_and_bit(int offset, u8 *reg, u8 *bit)
39{
40 *reg = 0x20 + offset / GPIO_NUM_PER_GROUP;
41 *bit = offset % GPIO_NUM_PER_GROUP;
42}
43
44static int mc9s08dz60_get_value(struct gpio_chip *gc, unsigned offset)
45{
46 u8 reg, bit;
47 s32 value;
48 struct mc9s08dz60 *mc9s = to_mc9s08dz60(gc);
49
50 mc9s_gpio_to_reg_and_bit(offset, &reg, &bit);
51 value = i2c_smbus_read_byte_data(mc9s->client, reg);
52
53 return (value >= 0) ? (value >> bit) & 0x1 : 0;
54}
55
56static int mc9s08dz60_set(struct mc9s08dz60 *mc9s, unsigned offset, int val)
57{
58 u8 reg, bit;
59 s32 value;
60
61 mc9s_gpio_to_reg_and_bit(offset, &reg, &bit);
62 value = i2c_smbus_read_byte_data(mc9s->client, reg);
63 if (value >= 0) {
64 if (val)
65 value |= 1 << bit;
66 else
67 value &= ~(1 << bit);
68
69 return i2c_smbus_write_byte_data(mc9s->client, reg, value);
70 } else
71 return value;
72
73}
74
75
76static void mc9s08dz60_set_value(struct gpio_chip *gc, unsigned offset, int val)
77{
78 struct mc9s08dz60 *mc9s = to_mc9s08dz60(gc);
79
80 mc9s08dz60_set(mc9s, offset, val);
81}
82
83static int mc9s08dz60_direction_output(struct gpio_chip *gc,
84 unsigned offset, int val)
85{
86 struct mc9s08dz60 *mc9s = to_mc9s08dz60(gc);
87
88 return mc9s08dz60_set(mc9s, offset, val);
89}
90
91static int mc9s08dz60_probe(struct i2c_client *client,
92 const struct i2c_device_id *id)
93{
94 int ret = 0;
95 struct mc9s08dz60 *mc9s;
96
97 mc9s = kzalloc(sizeof(*mc9s), GFP_KERNEL);
98 if (!mc9s)
99 return -ENOMEM;
100
101 mc9s->chip.label = client->name;
102 mc9s->chip.base = -1;
103 mc9s->chip.dev = &client->dev;
104 mc9s->chip.owner = THIS_MODULE;
105 mc9s->chip.ngpio = GPIO_NUM;
106 mc9s->chip.can_sleep = 1;
107 mc9s->chip.get = mc9s08dz60_get_value;
108 mc9s->chip.set = mc9s08dz60_set_value;
109 mc9s->chip.direction_output = mc9s08dz60_direction_output;
110 mc9s->client = client;
111 i2c_set_clientdata(client, mc9s);
112
113 ret = gpiochip_add(&mc9s->chip);
114 if (ret)
115 goto error;
116
117 return 0;
118
119 error:
120 kfree(mc9s);
121 return ret;
122}
123
124static int mc9s08dz60_remove(struct i2c_client *client)
125{
126 struct mc9s08dz60 *mc9s;
127 int ret;
128
129 mc9s = i2c_get_clientdata(client);
130
131 ret = gpiochip_remove(&mc9s->chip);
132 if (!ret)
133 kfree(mc9s);
134
135 return ret;
136
137}
138
139static const struct i2c_device_id mc9s08dz60_id[] = {
140 {"mc9s08dz60", 0},
141 {},
142};
143
144MODULE_DEVICE_TABLE(i2c, mc9s08dz60_id);
145
146static struct i2c_driver mc9s08dz60_i2c_driver = {
147 .driver = {
148 .owner = THIS_MODULE,
149 .name = "mc9s08dz60",
150 },
151 .probe = mc9s08dz60_probe,
152 .remove = mc9s08dz60_remove,
153 .id_table = mc9s08dz60_id,
154};
155
156module_i2c_driver(mc9s08dz60_i2c_driver);
157
158MODULE_AUTHOR("Freescale Semiconductor, Inc. "
159 "Wu Guoxing <b39297@freescale.com>");
160MODULE_DESCRIPTION("mc9s08dz60 gpio function on mx35 3ds board");
161MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index f49bd6f47a5..1adc2ec1e38 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -19,9 +19,12 @@
19#include <linux/err.h> 19#include <linux/err.h>
20#include <linux/clk.h> 20#include <linux/clk.h>
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/slab.h> 22#include <linux/device.h>
23#include <linux/pm_runtime.h> 23#include <linux/pm_runtime.h>
24#include <linux/pm.h> 24#include <linux/pm.h>
25#include <linux/of.h>
26#include <linux/of_device.h>
27#include <linux/irqdomain.h>
25 28
26#include <mach/hardware.h> 29#include <mach/hardware.h>
27#include <asm/irq.h> 30#include <asm/irq.h>
@@ -50,10 +53,10 @@ struct gpio_regs {
50 53
51struct gpio_bank { 54struct gpio_bank {
52 struct list_head node; 55 struct list_head node;
53 unsigned long pbase;
54 void __iomem *base; 56 void __iomem *base;
55 u16 irq; 57 u16 irq;
56 u16 virtual_irq_start; 58 int irq_base;
59 struct irq_domain *domain;
57 u32 suspend_wakeup; 60 u32 suspend_wakeup;
58 u32 saved_wakeup; 61 u32 saved_wakeup;
59 u32 non_wakeup_gpios; 62 u32 non_wakeup_gpios;
@@ -77,7 +80,6 @@ struct gpio_bank {
77 int stride; 80 int stride;
78 u32 width; 81 u32 width;
79 int context_loss_count; 82 int context_loss_count;
80 u16 id;
81 int power_mode; 83 int power_mode;
82 bool workaround_enabled; 84 bool workaround_enabled;
83 85
@@ -91,6 +93,11 @@ struct gpio_bank {
91#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio)) 93#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
92#define GPIO_MOD_CTRL_BIT BIT(0) 94#define GPIO_MOD_CTRL_BIT BIT(0)
93 95
96static int irq_to_gpio(struct gpio_bank *bank, unsigned int gpio_irq)
97{
98 return gpio_irq - bank->irq_base + bank->chip.base;
99}
100
94static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) 101static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
95{ 102{
96 void __iomem *reg = bank->base; 103 void __iomem *reg = bank->base;
@@ -113,10 +120,13 @@ static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
113 void __iomem *reg = bank->base; 120 void __iomem *reg = bank->base;
114 u32 l = GPIO_BIT(bank, gpio); 121 u32 l = GPIO_BIT(bank, gpio);
115 122
116 if (enable) 123 if (enable) {
117 reg += bank->regs->set_dataout; 124 reg += bank->regs->set_dataout;
118 else 125 bank->context.dataout |= l;
126 } else {
119 reg += bank->regs->clr_dataout; 127 reg += bank->regs->clr_dataout;
128 bank->context.dataout &= ~l;
129 }
120 130
121 __raw_writel(l, reg); 131 __raw_writel(l, reg);
122} 132}
@@ -137,25 +147,25 @@ static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
137 bank->context.dataout = l; 147 bank->context.dataout = l;
138} 148}
139 149
140static int _get_gpio_datain(struct gpio_bank *bank, int gpio) 150static int _get_gpio_datain(struct gpio_bank *bank, int offset)
141{ 151{
142 void __iomem *reg = bank->base + bank->regs->datain; 152 void __iomem *reg = bank->base + bank->regs->datain;
143 153
144 return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0; 154 return (__raw_readl(reg) & (1 << offset)) != 0;
145} 155}
146 156
147static int _get_gpio_dataout(struct gpio_bank *bank, int gpio) 157static int _get_gpio_dataout(struct gpio_bank *bank, int offset)
148{ 158{
149 void __iomem *reg = bank->base + bank->regs->dataout; 159 void __iomem *reg = bank->base + bank->regs->dataout;
150 160
151 return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0; 161 return (__raw_readl(reg) & (1 << offset)) != 0;
152} 162}
153 163
154static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set) 164static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
155{ 165{
156 int l = __raw_readl(base + reg); 166 int l = __raw_readl(base + reg);
157 167
158 if (set) 168 if (set)
159 l |= mask; 169 l |= mask;
160 else 170 else
161 l &= ~mask; 171 l &= ~mask;
@@ -238,7 +248,7 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
238} 248}
239 249
240static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio, 250static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
241 int trigger) 251 unsigned trigger)
242{ 252{
243 void __iomem *base = bank->base; 253 void __iomem *base = bank->base;
244 u32 gpio_bit = 1 << gpio; 254 u32 gpio_bit = 1 << gpio;
@@ -320,7 +330,8 @@ static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
320static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {} 330static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
321#endif 331#endif
322 332
323static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) 333static int _set_gpio_triggering(struct gpio_bank *bank, int gpio,
334 unsigned trigger)
324{ 335{
325 void __iomem *reg = bank->base; 336 void __iomem *reg = bank->base;
326 void __iomem *base = bank->base; 337 void __iomem *base = bank->base;
@@ -367,7 +378,7 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
367 378
368static int gpio_irq_type(struct irq_data *d, unsigned type) 379static int gpio_irq_type(struct irq_data *d, unsigned type)
369{ 380{
370 struct gpio_bank *bank; 381 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
371 unsigned gpio; 382 unsigned gpio;
372 int retval; 383 int retval;
373 unsigned long flags; 384 unsigned long flags;
@@ -375,13 +386,11 @@ static int gpio_irq_type(struct irq_data *d, unsigned type)
375 if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE) 386 if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
376 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE); 387 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
377 else 388 else
378 gpio = d->irq - IH_GPIO_BASE; 389 gpio = irq_to_gpio(bank, d->irq);
379 390
380 if (type & ~IRQ_TYPE_SENSE_MASK) 391 if (type & ~IRQ_TYPE_SENSE_MASK)
381 return -EINVAL; 392 return -EINVAL;
382 393
383 bank = irq_data_get_irq_chip_data(d);
384
385 if (!bank->regs->leveldetect0 && 394 if (!bank->regs->leveldetect0 &&
386 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) 395 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
387 return -EINVAL; 396 return -EINVAL;
@@ -442,6 +451,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
442 if (bank->regs->set_irqenable) { 451 if (bank->regs->set_irqenable) {
443 reg += bank->regs->set_irqenable; 452 reg += bank->regs->set_irqenable;
444 l = gpio_mask; 453 l = gpio_mask;
454 bank->context.irqenable1 |= gpio_mask;
445 } else { 455 } else {
446 reg += bank->regs->irqenable; 456 reg += bank->regs->irqenable;
447 l = __raw_readl(reg); 457 l = __raw_readl(reg);
@@ -449,10 +459,10 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
449 l &= ~gpio_mask; 459 l &= ~gpio_mask;
450 else 460 else
451 l |= gpio_mask; 461 l |= gpio_mask;
462 bank->context.irqenable1 = l;
452 } 463 }
453 464
454 __raw_writel(l, reg); 465 __raw_writel(l, reg);
455 bank->context.irqenable1 = l;
456} 466}
457 467
458static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) 468static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
@@ -463,6 +473,7 @@ static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
463 if (bank->regs->clr_irqenable) { 473 if (bank->regs->clr_irqenable) {
464 reg += bank->regs->clr_irqenable; 474 reg += bank->regs->clr_irqenable;
465 l = gpio_mask; 475 l = gpio_mask;
476 bank->context.irqenable1 &= ~gpio_mask;
466 } else { 477 } else {
467 reg += bank->regs->irqenable; 478 reg += bank->regs->irqenable;
468 l = __raw_readl(reg); 479 l = __raw_readl(reg);
@@ -470,15 +481,18 @@ static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
470 l |= gpio_mask; 481 l |= gpio_mask;
471 else 482 else
472 l &= ~gpio_mask; 483 l &= ~gpio_mask;
484 bank->context.irqenable1 = l;
473 } 485 }
474 486
475 __raw_writel(l, reg); 487 __raw_writel(l, reg);
476 bank->context.irqenable1 = l;
477} 488}
478 489
479static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) 490static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
480{ 491{
481 _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); 492 if (enable)
493 _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
494 else
495 _disable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
482} 496}
483 497
484/* 498/*
@@ -495,7 +509,7 @@ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
495 unsigned long flags; 509 unsigned long flags;
496 510
497 if (bank->non_wakeup_gpios & gpio_bit) { 511 if (bank->non_wakeup_gpios & gpio_bit) {
498 dev_err(bank->dev, 512 dev_err(bank->dev,
499 "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio); 513 "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio);
500 return -EINVAL; 514 return -EINVAL;
501 } 515 }
@@ -506,6 +520,7 @@ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
506 else 520 else
507 bank->suspend_wakeup &= ~gpio_bit; 521 bank->suspend_wakeup &= ~gpio_bit;
508 522
523 __raw_writel(bank->suspend_wakeup, bank->base + bank->regs->wkup_en);
509 spin_unlock_irqrestore(&bank->lock, flags); 524 spin_unlock_irqrestore(&bank->lock, flags);
510 525
511 return 0; 526 return 0;
@@ -522,14 +537,10 @@ static void _reset_gpio(struct gpio_bank *bank, int gpio)
522/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ 537/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
523static int gpio_wake_enable(struct irq_data *d, unsigned int enable) 538static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
524{ 539{
525 unsigned int gpio = d->irq - IH_GPIO_BASE; 540 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
526 struct gpio_bank *bank; 541 unsigned int gpio = irq_to_gpio(bank, d->irq);
527 int retval;
528
529 bank = irq_data_get_irq_chip_data(d);
530 retval = _set_gpio_wakeup(bank, gpio, enable);
531 542
532 return retval; 543 return _set_gpio_wakeup(bank, gpio, enable);
533} 544}
534 545
535static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) 546static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
@@ -671,13 +682,15 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
671 if (!isr) 682 if (!isr)
672 break; 683 break;
673 684
674 gpio_irq = bank->virtual_irq_start; 685 gpio_irq = bank->irq_base;
675 for (; isr != 0; isr >>= 1, gpio_irq++) { 686 for (; isr != 0; isr >>= 1, gpio_irq++) {
676 gpio_index = GPIO_INDEX(bank, irq_to_gpio(gpio_irq)); 687 int gpio = irq_to_gpio(bank, gpio_irq);
677 688
678 if (!(isr & 1)) 689 if (!(isr & 1))
679 continue; 690 continue;
680 691
692 gpio_index = GPIO_INDEX(bank, gpio);
693
681 /* 694 /*
682 * Some chips can't respond to both rising and falling 695 * Some chips can't respond to both rising and falling
683 * at the same time. If this irq was requested with 696 * at the same time. If this irq was requested with
@@ -703,8 +716,8 @@ exit:
703 716
704static void gpio_irq_shutdown(struct irq_data *d) 717static void gpio_irq_shutdown(struct irq_data *d)
705{ 718{
706 unsigned int gpio = d->irq - IH_GPIO_BASE;
707 struct gpio_bank *bank = irq_data_get_irq_chip_data(d); 719 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
720 unsigned int gpio = irq_to_gpio(bank, d->irq);
708 unsigned long flags; 721 unsigned long flags;
709 722
710 spin_lock_irqsave(&bank->lock, flags); 723 spin_lock_irqsave(&bank->lock, flags);
@@ -714,16 +727,16 @@ static void gpio_irq_shutdown(struct irq_data *d)
714 727
715static void gpio_ack_irq(struct irq_data *d) 728static void gpio_ack_irq(struct irq_data *d)
716{ 729{
717 unsigned int gpio = d->irq - IH_GPIO_BASE;
718 struct gpio_bank *bank = irq_data_get_irq_chip_data(d); 730 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
731 unsigned int gpio = irq_to_gpio(bank, d->irq);
719 732
720 _clear_gpio_irqstatus(bank, gpio); 733 _clear_gpio_irqstatus(bank, gpio);
721} 734}
722 735
723static void gpio_mask_irq(struct irq_data *d) 736static void gpio_mask_irq(struct irq_data *d)
724{ 737{
725 unsigned int gpio = d->irq - IH_GPIO_BASE;
726 struct gpio_bank *bank = irq_data_get_irq_chip_data(d); 738 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
739 unsigned int gpio = irq_to_gpio(bank, d->irq);
727 unsigned long flags; 740 unsigned long flags;
728 741
729 spin_lock_irqsave(&bank->lock, flags); 742 spin_lock_irqsave(&bank->lock, flags);
@@ -734,8 +747,8 @@ static void gpio_mask_irq(struct irq_data *d)
734 747
735static void gpio_unmask_irq(struct irq_data *d) 748static void gpio_unmask_irq(struct irq_data *d)
736{ 749{
737 unsigned int gpio = d->irq - IH_GPIO_BASE;
738 struct gpio_bank *bank = irq_data_get_irq_chip_data(d); 750 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
751 unsigned int gpio = irq_to_gpio(bank, d->irq);
739 unsigned int irq_mask = GPIO_BIT(bank, gpio); 752 unsigned int irq_mask = GPIO_BIT(bank, gpio);
740 u32 trigger = irqd_get_trigger_type(d); 753 u32 trigger = irqd_get_trigger_type(d);
741 unsigned long flags; 754 unsigned long flags;
@@ -852,19 +865,15 @@ static int gpio_is_input(struct gpio_bank *bank, int mask)
852static int gpio_get(struct gpio_chip *chip, unsigned offset) 865static int gpio_get(struct gpio_chip *chip, unsigned offset)
853{ 866{
854 struct gpio_bank *bank; 867 struct gpio_bank *bank;
855 void __iomem *reg;
856 int gpio;
857 u32 mask; 868 u32 mask;
858 869
859 gpio = chip->base + offset;
860 bank = container_of(chip, struct gpio_bank, chip); 870 bank = container_of(chip, struct gpio_bank, chip);
861 reg = bank->base; 871 mask = (1 << offset);
862 mask = GPIO_BIT(bank, gpio);
863 872
864 if (gpio_is_input(bank, mask)) 873 if (gpio_is_input(bank, mask))
865 return _get_gpio_datain(bank, gpio); 874 return _get_gpio_datain(bank, offset);
866 else 875 else
867 return _get_gpio_dataout(bank, gpio); 876 return _get_gpio_dataout(bank, offset);
868} 877}
869 878
870static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) 879static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
@@ -917,7 +926,7 @@ static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
917 struct gpio_bank *bank; 926 struct gpio_bank *bank;
918 927
919 bank = container_of(chip, struct gpio_bank, chip); 928 bank = container_of(chip, struct gpio_bank, chip);
920 return bank->virtual_irq_start + offset; 929 return bank->irq_base + offset;
921} 930}
922 931
923/*---------------------------------------------------------------------*/ 932/*---------------------------------------------------------------------*/
@@ -970,7 +979,7 @@ static void omap_gpio_mod_init(struct gpio_bank *bank)
970 _gpio_rmw(base, bank->regs->ctrl, 0, 1); 979 _gpio_rmw(base, bank->regs->ctrl, 0, 1);
971} 980}
972 981
973static __init void 982static __devinit void
974omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start, 983omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
975 unsigned int num) 984 unsigned int num)
976{ 985{
@@ -1030,8 +1039,7 @@ static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
1030 1039
1031 gpiochip_add(&bank->chip); 1040 gpiochip_add(&bank->chip);
1032 1041
1033 for (j = bank->virtual_irq_start; 1042 for (j = bank->irq_base; j < bank->irq_base + bank->width; j++) {
1034 j < bank->virtual_irq_start + bank->width; j++) {
1035 irq_set_lockdep_class(j, &gpio_lock_class); 1043 irq_set_lockdep_class(j, &gpio_lock_class);
1036 irq_set_chip_data(j, bank); 1044 irq_set_chip_data(j, bank);
1037 if (bank->is_mpuio) { 1045 if (bank->is_mpuio) {
@@ -1046,39 +1054,38 @@ static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
1046 irq_set_handler_data(bank->irq, bank); 1054 irq_set_handler_data(bank->irq, bank);
1047} 1055}
1048 1056
1057static const struct of_device_id omap_gpio_match[];
1058
1049static int __devinit omap_gpio_probe(struct platform_device *pdev) 1059static int __devinit omap_gpio_probe(struct platform_device *pdev)
1050{ 1060{
1061 struct device *dev = &pdev->dev;
1062 struct device_node *node = dev->of_node;
1063 const struct of_device_id *match;
1051 struct omap_gpio_platform_data *pdata; 1064 struct omap_gpio_platform_data *pdata;
1052 struct resource *res; 1065 struct resource *res;
1053 struct gpio_bank *bank; 1066 struct gpio_bank *bank;
1054 int ret = 0; 1067 int ret = 0;
1055 1068
1056 if (!pdev->dev.platform_data) { 1069 match = of_match_device(of_match_ptr(omap_gpio_match), dev);
1057 ret = -EINVAL; 1070
1058 goto err_exit; 1071 pdata = match ? match->data : dev->platform_data;
1059 } 1072 if (!pdata)
1073 return -EINVAL;
1060 1074
1061 bank = kzalloc(sizeof(struct gpio_bank), GFP_KERNEL); 1075 bank = devm_kzalloc(&pdev->dev, sizeof(struct gpio_bank), GFP_KERNEL);
1062 if (!bank) { 1076 if (!bank) {
1063 dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n"); 1077 dev_err(dev, "Memory alloc failed\n");
1064 ret = -ENOMEM; 1078 return -ENOMEM;
1065 goto err_exit;
1066 } 1079 }
1067 1080
1068 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1081 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1069 if (unlikely(!res)) { 1082 if (unlikely(!res)) {
1070 dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", 1083 dev_err(dev, "Invalid IRQ resource\n");
1071 pdev->id); 1084 return -ENODEV;
1072 ret = -ENODEV;
1073 goto err_free;
1074 } 1085 }
1075 1086
1076 bank->irq = res->start; 1087 bank->irq = res->start;
1077 bank->id = pdev->id; 1088 bank->dev = dev;
1078
1079 pdata = pdev->dev.platform_data;
1080 bank->virtual_irq_start = pdata->virtual_irq_start;
1081 bank->dev = &pdev->dev;
1082 bank->dbck_flag = pdata->dbck_flag; 1089 bank->dbck_flag = pdata->dbck_flag;
1083 bank->stride = pdata->bank_stride; 1090 bank->stride = pdata->bank_stride;
1084 bank->width = pdata->bank_width; 1091 bank->width = pdata->bank_width;
@@ -1087,6 +1094,18 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev)
1087 bank->loses_context = pdata->loses_context; 1094 bank->loses_context = pdata->loses_context;
1088 bank->get_context_loss_count = pdata->get_context_loss_count; 1095 bank->get_context_loss_count = pdata->get_context_loss_count;
1089 bank->regs = pdata->regs; 1096 bank->regs = pdata->regs;
1097#ifdef CONFIG_OF_GPIO
1098 bank->chip.of_node = of_node_get(node);
1099#endif
1100
1101 bank->irq_base = irq_alloc_descs(-1, 0, bank->width, 0);
1102 if (bank->irq_base < 0) {
1103 dev_err(dev, "Couldn't allocate IRQ numbers\n");
1104 return -ENODEV;
1105 }
1106
1107 bank->domain = irq_domain_add_legacy(node, bank->width, bank->irq_base,
1108 0, &irq_domain_simple_ops, NULL);
1090 1109
1091 if (bank->regs->set_dataout && bank->regs->clr_dataout) 1110 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1092 bank->set_dataout = _set_gpio_dataout_reg; 1111 bank->set_dataout = _set_gpio_dataout_reg;
@@ -1098,18 +1117,20 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev)
1098 /* Static mapping, never released */ 1117 /* Static mapping, never released */
1099 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1118 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1100 if (unlikely(!res)) { 1119 if (unlikely(!res)) {
1101 dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", 1120 dev_err(dev, "Invalid mem resource\n");
1102 pdev->id); 1121 return -ENODEV;
1103 ret = -ENODEV;
1104 goto err_free;
1105 } 1122 }
1106 1123
1107 bank->base = ioremap(res->start, resource_size(res)); 1124 if (!devm_request_mem_region(dev, res->start, resource_size(res),
1125 pdev->name)) {
1126 dev_err(dev, "Region already claimed\n");
1127 return -EBUSY;
1128 }
1129
1130 bank->base = devm_ioremap(dev, res->start, resource_size(res));
1108 if (!bank->base) { 1131 if (!bank->base) {
1109 dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", 1132 dev_err(dev, "Could not ioremap\n");
1110 pdev->id); 1133 return -ENOMEM;
1111 ret = -ENOMEM;
1112 goto err_free;
1113 } 1134 }
1114 1135
1115 platform_set_drvdata(pdev, bank); 1136 platform_set_drvdata(pdev, bank);
@@ -1130,11 +1151,6 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev)
1130 list_add_tail(&bank->node, &omap_gpio_list); 1151 list_add_tail(&bank->node, &omap_gpio_list);
1131 1152
1132 return ret; 1153 return ret;
1133
1134err_free:
1135 kfree(bank);
1136err_exit:
1137 return ret;
1138} 1154}
1139 1155
1140#ifdef CONFIG_ARCH_OMAP2PLUS 1156#ifdef CONFIG_ARCH_OMAP2PLUS
@@ -1196,8 +1212,30 @@ static int omap_gpio_runtime_suspend(struct device *dev)
1196 struct gpio_bank *bank = platform_get_drvdata(pdev); 1212 struct gpio_bank *bank = platform_get_drvdata(pdev);
1197 u32 l1 = 0, l2 = 0; 1213 u32 l1 = 0, l2 = 0;
1198 unsigned long flags; 1214 unsigned long flags;
1215 u32 wake_low, wake_hi;
1199 1216
1200 spin_lock_irqsave(&bank->lock, flags); 1217 spin_lock_irqsave(&bank->lock, flags);
1218
1219 /*
1220 * Only edges can generate a wakeup event to the PRCM.
1221 *
1222 * Therefore, ensure any wake-up capable GPIOs have
1223 * edge-detection enabled before going idle to ensure a wakeup
1224 * to the PRCM is generated on a GPIO transition. (c.f. 34xx
1225 * NDA TRM 25.5.3.1)
1226 *
1227 * The normal values will be restored upon ->runtime_resume()
1228 * by writing back the values saved in bank->context.
1229 */
1230 wake_low = bank->context.leveldetect0 & bank->context.wake_en;
1231 if (wake_low)
1232 __raw_writel(wake_low | bank->context.fallingdetect,
1233 bank->base + bank->regs->fallingdetect);
1234 wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
1235 if (wake_hi)
1236 __raw_writel(wake_hi | bank->context.risingdetect,
1237 bank->base + bank->regs->risingdetect);
1238
1201 if (bank->power_mode != OFF_MODE) { 1239 if (bank->power_mode != OFF_MODE) {
1202 bank->power_mode = 0; 1240 bank->power_mode = 0;
1203 goto update_gpio_context_count; 1241 goto update_gpio_context_count;
@@ -1207,9 +1245,6 @@ static int omap_gpio_runtime_suspend(struct device *dev)
1207 * non-wakeup GPIOs. Otherwise spurious IRQs will be 1245 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1208 * generated. See OMAP2420 Errata item 1.101. 1246 * generated. See OMAP2420 Errata item 1.101.
1209 */ 1247 */
1210 if (!(bank->enabled_non_wakeup_gpios))
1211 goto update_gpio_context_count;
1212
1213 bank->saved_datain = __raw_readl(bank->base + 1248 bank->saved_datain = __raw_readl(bank->base +
1214 bank->regs->datain); 1249 bank->regs->datain);
1215 l1 = __raw_readl(bank->base + bank->regs->fallingdetect); 1250 l1 = __raw_readl(bank->base + bank->regs->fallingdetect);
@@ -1246,7 +1281,19 @@ static int omap_gpio_runtime_resume(struct device *dev)
1246 1281
1247 spin_lock_irqsave(&bank->lock, flags); 1282 spin_lock_irqsave(&bank->lock, flags);
1248 _gpio_dbck_enable(bank); 1283 _gpio_dbck_enable(bank);
1249 if (!bank->enabled_non_wakeup_gpios || !bank->workaround_enabled) { 1284
1285 /*
1286 * In ->runtime_suspend(), level-triggered, wakeup-enabled
1287 * GPIOs were set to edge trigger also in order to be able to
1288 * generate a PRCM wakeup. Here we restore the
1289 * pre-runtime_suspend() values for edge triggering.
1290 */
1291 __raw_writel(bank->context.fallingdetect,
1292 bank->base + bank->regs->fallingdetect);
1293 __raw_writel(bank->context.risingdetect,
1294 bank->base + bank->regs->risingdetect);
1295
1296 if (!bank->workaround_enabled) {
1250 spin_unlock_irqrestore(&bank->lock, flags); 1297 spin_unlock_irqrestore(&bank->lock, flags);
1251 return 0; 1298 return 0;
1252 } 1299 }
@@ -1397,11 +1444,95 @@ static const struct dev_pm_ops gpio_pm_ops = {
1397 NULL) 1444 NULL)
1398}; 1445};
1399 1446
1447#if defined(CONFIG_OF)
1448static struct omap_gpio_reg_offs omap2_gpio_regs = {
1449 .revision = OMAP24XX_GPIO_REVISION,
1450 .direction = OMAP24XX_GPIO_OE,
1451 .datain = OMAP24XX_GPIO_DATAIN,
1452 .dataout = OMAP24XX_GPIO_DATAOUT,
1453 .set_dataout = OMAP24XX_GPIO_SETDATAOUT,
1454 .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT,
1455 .irqstatus = OMAP24XX_GPIO_IRQSTATUS1,
1456 .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2,
1457 .irqenable = OMAP24XX_GPIO_IRQENABLE1,
1458 .irqenable2 = OMAP24XX_GPIO_IRQENABLE2,
1459 .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1,
1460 .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1,
1461 .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL,
1462 .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN,
1463 .ctrl = OMAP24XX_GPIO_CTRL,
1464 .wkup_en = OMAP24XX_GPIO_WAKE_EN,
1465 .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0,
1466 .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1,
1467 .risingdetect = OMAP24XX_GPIO_RISINGDETECT,
1468 .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT,
1469};
1470
1471static struct omap_gpio_reg_offs omap4_gpio_regs = {
1472 .revision = OMAP4_GPIO_REVISION,
1473 .direction = OMAP4_GPIO_OE,
1474 .datain = OMAP4_GPIO_DATAIN,
1475 .dataout = OMAP4_GPIO_DATAOUT,
1476 .set_dataout = OMAP4_GPIO_SETDATAOUT,
1477 .clr_dataout = OMAP4_GPIO_CLEARDATAOUT,
1478 .irqstatus = OMAP4_GPIO_IRQSTATUS0,
1479 .irqstatus2 = OMAP4_GPIO_IRQSTATUS1,
1480 .irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1481 .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1,
1482 .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1483 .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0,
1484 .debounce = OMAP4_GPIO_DEBOUNCINGTIME,
1485 .debounce_en = OMAP4_GPIO_DEBOUNCENABLE,
1486 .ctrl = OMAP4_GPIO_CTRL,
1487 .wkup_en = OMAP4_GPIO_IRQWAKEN0,
1488 .leveldetect0 = OMAP4_GPIO_LEVELDETECT0,
1489 .leveldetect1 = OMAP4_GPIO_LEVELDETECT1,
1490 .risingdetect = OMAP4_GPIO_RISINGDETECT,
1491 .fallingdetect = OMAP4_GPIO_FALLINGDETECT,
1492};
1493
1494static struct omap_gpio_platform_data omap2_pdata = {
1495 .regs = &omap2_gpio_regs,
1496 .bank_width = 32,
1497 .dbck_flag = false,
1498};
1499
1500static struct omap_gpio_platform_data omap3_pdata = {
1501 .regs = &omap2_gpio_regs,
1502 .bank_width = 32,
1503 .dbck_flag = true,
1504};
1505
1506static struct omap_gpio_platform_data omap4_pdata = {
1507 .regs = &omap4_gpio_regs,
1508 .bank_width = 32,
1509 .dbck_flag = true,
1510};
1511
1512static const struct of_device_id omap_gpio_match[] = {
1513 {
1514 .compatible = "ti,omap4-gpio",
1515 .data = &omap4_pdata,
1516 },
1517 {
1518 .compatible = "ti,omap3-gpio",
1519 .data = &omap3_pdata,
1520 },
1521 {
1522 .compatible = "ti,omap2-gpio",
1523 .data = &omap2_pdata,
1524 },
1525 { },
1526};
1527MODULE_DEVICE_TABLE(of, omap_gpio_match);
1528#endif
1529
1400static struct platform_driver omap_gpio_driver = { 1530static struct platform_driver omap_gpio_driver = {
1401 .probe = omap_gpio_probe, 1531 .probe = omap_gpio_probe,
1402 .driver = { 1532 .driver = {
1403 .name = "omap_gpio", 1533 .name = "omap_gpio",
1404 .pm = &gpio_pm_ops, 1534 .pm = &gpio_pm_ops,
1535 .of_match_table = of_match_ptr(omap_gpio_match),
1405 }, 1536 },
1406}; 1537};
1407 1538
diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c
index 77c9cc70fa7..b4b5da4fd2c 100644
--- a/drivers/gpio/gpio-pl061.c
+++ b/drivers/gpio/gpio-pl061.c
@@ -352,7 +352,12 @@ static int pl061_resume(struct device *dev)
352 return 0; 352 return 0;
353} 353}
354 354
355static SIMPLE_DEV_PM_OPS(pl061_dev_pm_ops, pl061_suspend, pl061_resume); 355static const struct dev_pm_ops pl061_dev_pm_ops = {
356 .suspend = pl061_suspend,
357 .resume = pl061_resume,
358 .freeze = pl061_suspend,
359 .restore = pl061_resume,
360};
356#endif 361#endif
357 362
358static struct amba_id pl061_ids[] = { 363static struct amba_id pl061_ids[] = {
diff --git a/drivers/gpio/gpio-sodaville.c b/drivers/gpio/gpio-sodaville.c
new file mode 100644
index 00000000000..9ba15d31d24
--- /dev/null
+++ b/drivers/gpio/gpio-sodaville.c
@@ -0,0 +1,302 @@
1/*
2 * GPIO interface for Intel Sodaville SoCs.
3 *
4 * Copyright (c) 2010, 2011 Intel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License 2 as published
8 * by the Free Software Foundation.
9 *
10 */
11
12#include <linux/errno.h>
13#include <linux/gpio.h>
14#include <linux/init.h>
15#include <linux/io.h>
16#include <linux/irq.h>
17#include <linux/interrupt.h>
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/pci.h>
21#include <linux/platform_device.h>
22#include <linux/of_irq.h>
23#include <linux/basic_mmio_gpio.h>
24
25#define DRV_NAME "sdv_gpio"
26#define SDV_NUM_PUB_GPIOS 12
27#define PCI_DEVICE_ID_SDV_GPIO 0x2e67
28#define GPIO_BAR 0
29
30#define GPOUTR 0x00
31#define GPOER 0x04
32#define GPINR 0x08
33
34#define GPSTR 0x0c
35#define GPIT1R0 0x10
36#define GPIO_INT 0x14
37#define GPIT1R1 0x18
38
39#define GPMUXCTL 0x1c
40
41struct sdv_gpio_chip_data {
42 int irq_base;
43 void __iomem *gpio_pub_base;
44 struct irq_domain id;
45 struct irq_chip_generic *gc;
46 struct bgpio_chip bgpio;
47};
48
49static int sdv_gpio_pub_set_type(struct irq_data *d, unsigned int type)
50{
51 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
52 struct sdv_gpio_chip_data *sd = gc->private;
53 void __iomem *type_reg;
54 u32 irq_offs = d->irq - sd->irq_base;
55 u32 reg;
56
57 if (irq_offs < 8)
58 type_reg = sd->gpio_pub_base + GPIT1R0;
59 else
60 type_reg = sd->gpio_pub_base + GPIT1R1;
61
62 reg = readl(type_reg);
63
64 switch (type) {
65 case IRQ_TYPE_LEVEL_HIGH:
66 reg &= ~BIT(4 * (irq_offs % 8));
67 break;
68
69 case IRQ_TYPE_LEVEL_LOW:
70 reg |= BIT(4 * (irq_offs % 8));
71 break;
72
73 default:
74 return -EINVAL;
75 }
76
77 writel(reg, type_reg);
78 return 0;
79}
80
81static irqreturn_t sdv_gpio_pub_irq_handler(int irq, void *data)
82{
83 struct sdv_gpio_chip_data *sd = data;
84 u32 irq_stat = readl(sd->gpio_pub_base + GPSTR);
85
86 irq_stat &= readl(sd->gpio_pub_base + GPIO_INT);
87 if (!irq_stat)
88 return IRQ_NONE;
89
90 while (irq_stat) {
91 u32 irq_bit = __fls(irq_stat);
92
93 irq_stat &= ~BIT(irq_bit);
94 generic_handle_irq(sd->irq_base + irq_bit);
95 }
96
97 return IRQ_HANDLED;
98}
99
100static int sdv_xlate(struct irq_domain *h, struct device_node *node,
101 const u32 *intspec, u32 intsize, irq_hw_number_t *out_hwirq,
102 u32 *out_type)
103{
104 u32 line, type;
105
106 if (node != h->of_node)
107 return -EINVAL;
108
109 if (intsize < 2)
110 return -EINVAL;
111
112 line = *intspec;
113 *out_hwirq = line;
114
115 intspec++;
116 type = *intspec;
117
118 switch (type) {
119 case IRQ_TYPE_LEVEL_LOW:
120 case IRQ_TYPE_LEVEL_HIGH:
121 *out_type = type;
122 break;
123 default:
124 return -EINVAL;
125 }
126 return 0;
127}
128
129static struct irq_domain_ops irq_domain_sdv_ops = {
130 .dt_translate = sdv_xlate,
131};
132
133static __devinit int sdv_register_irqsupport(struct sdv_gpio_chip_data *sd,
134 struct pci_dev *pdev)
135{
136 struct irq_chip_type *ct;
137 int ret;
138
139 sd->irq_base = irq_alloc_descs(-1, 0, SDV_NUM_PUB_GPIOS, -1);
140 if (sd->irq_base < 0)
141 return sd->irq_base;
142
143 /* mask + ACK all interrupt sources */
144 writel(0, sd->gpio_pub_base + GPIO_INT);
145 writel((1 << 11) - 1, sd->gpio_pub_base + GPSTR);
146
147 ret = request_irq(pdev->irq, sdv_gpio_pub_irq_handler, IRQF_SHARED,
148 "sdv_gpio", sd);
149 if (ret)
150 goto out_free_desc;
151
152 sd->id.irq_base = sd->irq_base;
153 sd->id.of_node = of_node_get(pdev->dev.of_node);
154 sd->id.ops = &irq_domain_sdv_ops;
155
156 /*
157 * This gpio irq controller latches level irqs. Testing shows that if
158 * we unmask & ACK the IRQ before the source of the interrupt is gone
159 * then the interrupt is active again.
160 */
161 sd->gc = irq_alloc_generic_chip("sdv-gpio", 1, sd->irq_base,
162 sd->gpio_pub_base, handle_fasteoi_irq);
163 if (!sd->gc) {
164 ret = -ENOMEM;
165 goto out_free_irq;
166 }
167
168 sd->gc->private = sd;
169 ct = sd->gc->chip_types;
170 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
171 ct->regs.eoi = GPSTR;
172 ct->regs.mask = GPIO_INT;
173 ct->chip.irq_mask = irq_gc_mask_clr_bit;
174 ct->chip.irq_unmask = irq_gc_mask_set_bit;
175 ct->chip.irq_eoi = irq_gc_eoi;
176 ct->chip.irq_set_type = sdv_gpio_pub_set_type;
177
178 irq_setup_generic_chip(sd->gc, IRQ_MSK(SDV_NUM_PUB_GPIOS),
179 IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST,
180 IRQ_LEVEL | IRQ_NOPROBE);
181
182 irq_domain_add(&sd->id);
183 return 0;
184out_free_irq:
185 free_irq(pdev->irq, sd);
186out_free_desc:
187 irq_free_descs(sd->irq_base, SDV_NUM_PUB_GPIOS);
188 return ret;
189}
190
191static int __devinit sdv_gpio_probe(struct pci_dev *pdev,
192 const struct pci_device_id *pci_id)
193{
194 struct sdv_gpio_chip_data *sd;
195 unsigned long addr;
196 const void *prop;
197 int len;
198 int ret;
199 u32 mux_val;
200
201 sd = kzalloc(sizeof(struct sdv_gpio_chip_data), GFP_KERNEL);
202 if (!sd)
203 return -ENOMEM;
204 ret = pci_enable_device(pdev);
205 if (ret) {
206 dev_err(&pdev->dev, "can't enable device.\n");
207 goto done;
208 }
209
210 ret = pci_request_region(pdev, GPIO_BAR, DRV_NAME);
211 if (ret) {
212 dev_err(&pdev->dev, "can't alloc PCI BAR #%d\n", GPIO_BAR);
213 goto disable_pci;
214 }
215
216 addr = pci_resource_start(pdev, GPIO_BAR);
217 if (!addr)
218 goto release_reg;
219 sd->gpio_pub_base = ioremap(addr, pci_resource_len(pdev, GPIO_BAR));
220
221 prop = of_get_property(pdev->dev.of_node, "intel,muxctl", &len);
222 if (prop && len == 4) {
223 mux_val = of_read_number(prop, 1);
224 writel(mux_val, sd->gpio_pub_base + GPMUXCTL);
225 }
226
227 ret = bgpio_init(&sd->bgpio, &pdev->dev, 4,
228 sd->gpio_pub_base + GPINR, sd->gpio_pub_base + GPOUTR,
229 NULL, sd->gpio_pub_base + GPOER, NULL, false);
230 if (ret)
231 goto unmap;
232 sd->bgpio.gc.ngpio = SDV_NUM_PUB_GPIOS;
233
234 ret = gpiochip_add(&sd->bgpio.gc);
235 if (ret < 0) {
236 dev_err(&pdev->dev, "gpiochip_add() failed.\n");
237 goto unmap;
238 }
239
240 ret = sdv_register_irqsupport(sd, pdev);
241 if (ret)
242 goto unmap;
243
244 pci_set_drvdata(pdev, sd);
245 dev_info(&pdev->dev, "Sodaville GPIO driver registered.\n");
246 return 0;
247
248unmap:
249 iounmap(sd->gpio_pub_base);
250release_reg:
251 pci_release_region(pdev, GPIO_BAR);
252disable_pci:
253 pci_disable_device(pdev);
254done:
255 kfree(sd);
256 return ret;
257}
258
259static void sdv_gpio_remove(struct pci_dev *pdev)
260{
261 struct sdv_gpio_chip_data *sd = pci_get_drvdata(pdev);
262
263 irq_domain_del(&sd->id);
264 free_irq(pdev->irq, sd);
265 irq_free_descs(sd->irq_base, SDV_NUM_PUB_GPIOS);
266
267 if (gpiochip_remove(&sd->bgpio.gc))
268 dev_err(&pdev->dev, "gpiochip_remove() failed.\n");
269
270 pci_release_region(pdev, GPIO_BAR);
271 iounmap(sd->gpio_pub_base);
272 pci_disable_device(pdev);
273 kfree(sd);
274}
275
276static struct pci_device_id sdv_gpio_pci_ids[] __devinitdata = {
277 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_SDV_GPIO) },
278 { 0, },
279};
280
281static struct pci_driver sdv_gpio_driver = {
282 .name = DRV_NAME,
283 .id_table = sdv_gpio_pci_ids,
284 .probe = sdv_gpio_probe,
285 .remove = sdv_gpio_remove,
286};
287
288static int __init sdv_gpio_init(void)
289{
290 return pci_register_driver(&sdv_gpio_driver);
291}
292module_init(sdv_gpio_init);
293
294static void __exit sdv_gpio_exit(void)
295{
296 pci_unregister_driver(&sdv_gpio_driver);
297}
298module_exit(sdv_gpio_exit);
299
300MODULE_AUTHOR("Hans J. Koch <hjk@linutronix.de>");
301MODULE_DESCRIPTION("GPIO interface for Intel Sodaville SoCs");
302MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpio/gpio-stmpe.c b/drivers/gpio/gpio-stmpe.c
index 094c5c4fd7f..dce34727bbf 100644
--- a/drivers/gpio/gpio-stmpe.c
+++ b/drivers/gpio/gpio-stmpe.c
@@ -54,7 +54,7 @@ static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
54 if (ret < 0) 54 if (ret < 0)
55 return ret; 55 return ret;
56 56
57 return ret & mask; 57 return !!(ret & mask);
58} 58}
59 59
60static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val) 60static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
index 6f17671260e..32de6707e3c 100644
--- a/drivers/gpio/gpio-tegra.c
+++ b/drivers/gpio/gpio-tegra.c
@@ -109,11 +109,13 @@ void tegra_gpio_enable(int gpio)
109{ 109{
110 tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1); 110 tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
111} 111}
112EXPORT_SYMBOL_GPL(tegra_gpio_enable);
112 113
113void tegra_gpio_disable(int gpio) 114void tegra_gpio_disable(int gpio)
114{ 115{
115 tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0); 116 tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
116} 117}
118EXPORT_SYMBOL_GPL(tegra_gpio_disable);
117 119
118static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 120static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
119{ 121{
@@ -459,7 +461,7 @@ static int __init tegra_gpio_init(void)
459} 461}
460postcore_initcall(tegra_gpio_init); 462postcore_initcall(tegra_gpio_init);
461 463
462void __init tegra_gpio_config(struct tegra_gpio_table *table, int num) 464void tegra_gpio_config(struct tegra_gpio_table *table, int num)
463{ 465{
464 int i; 466 int i;
465 467
diff --git a/drivers/gpio/gpio-tps65910.c b/drivers/gpio/gpio-tps65910.c
index 91f45b965d1..7eef648a335 100644
--- a/drivers/gpio/gpio-tps65910.c
+++ b/drivers/gpio/gpio-tps65910.c
@@ -69,6 +69,7 @@ static int tps65910_gpio_input(struct gpio_chip *gc, unsigned offset)
69void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base) 69void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base)
70{ 70{
71 int ret; 71 int ret;
72 struct tps65910_board *board_data;
72 73
73 if (!gpio_base) 74 if (!gpio_base)
74 return; 75 return;
@@ -80,10 +81,10 @@ void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base)
80 81
81 switch(tps65910_chip_id(tps65910)) { 82 switch(tps65910_chip_id(tps65910)) {
82 case TPS65910: 83 case TPS65910:
83 tps65910->gpio.ngpio = 6; 84 tps65910->gpio.ngpio = TPS65910_NUM_GPIO;
84 break; 85 break;
85 case TPS65911: 86 case TPS65911:
86 tps65910->gpio.ngpio = 9; 87 tps65910->gpio.ngpio = TPS65911_NUM_GPIO;
87 break; 88 break;
88 default: 89 default:
89 return; 90 return;
@@ -95,6 +96,21 @@ void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base)
95 tps65910->gpio.set = tps65910_gpio_set; 96 tps65910->gpio.set = tps65910_gpio_set;
96 tps65910->gpio.get = tps65910_gpio_get; 97 tps65910->gpio.get = tps65910_gpio_get;
97 98
99 /* Configure sleep control for gpios */
100 board_data = dev_get_platdata(tps65910->dev);
101 if (board_data) {
102 int i;
103 for (i = 0; i < tps65910->gpio.ngpio; ++i) {
104 if (board_data->en_gpio_sleep[i]) {
105 ret = tps65910_set_bits(tps65910,
106 TPS65910_GPIO0 + i, GPIO_SLEEP_MASK);
107 if (ret < 0)
108 dev_warn(tps65910->dev,
109 "GPIO Sleep setting failed\n");
110 }
111 }
112 }
113
98 ret = gpiochip_add(&tps65910->gpio); 114 ret = gpiochip_add(&tps65910->gpio);
99 115
100 if (ret) 116 if (ret)
diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index 17fdf4b6af9..5a75510d66b 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -58,6 +58,8 @@ struct gpio_desc {
58#define FLAG_TRIG_FALL 5 /* trigger on falling edge */ 58#define FLAG_TRIG_FALL 5 /* trigger on falling edge */
59#define FLAG_TRIG_RISE 6 /* trigger on rising edge */ 59#define FLAG_TRIG_RISE 6 /* trigger on rising edge */
60#define FLAG_ACTIVE_LOW 7 /* sysfs value has active low */ 60#define FLAG_ACTIVE_LOW 7 /* sysfs value has active low */
61#define FLAG_OPEN_DRAIN 8 /* Gpio is open drain type */
62#define FLAG_OPEN_SOURCE 9 /* Gpio is open source type */
61 63
62#define ID_SHIFT 16 /* add new flags before this one */ 64#define ID_SHIFT 16 /* add new flags before this one */
63 65
@@ -873,6 +875,7 @@ void gpio_unexport(unsigned gpio)
873{ 875{
874 struct gpio_desc *desc; 876 struct gpio_desc *desc;
875 int status = 0; 877 int status = 0;
878 struct device *dev = NULL;
876 879
877 if (!gpio_is_valid(gpio)) { 880 if (!gpio_is_valid(gpio)) {
878 status = -EINVAL; 881 status = -EINVAL;
@@ -884,19 +887,20 @@ void gpio_unexport(unsigned gpio)
884 desc = &gpio_desc[gpio]; 887 desc = &gpio_desc[gpio];
885 888
886 if (test_bit(FLAG_EXPORT, &desc->flags)) { 889 if (test_bit(FLAG_EXPORT, &desc->flags)) {
887 struct device *dev = NULL;
888 890
889 dev = class_find_device(&gpio_class, NULL, desc, match_export); 891 dev = class_find_device(&gpio_class, NULL, desc, match_export);
890 if (dev) { 892 if (dev) {
891 gpio_setup_irq(desc, dev, 0); 893 gpio_setup_irq(desc, dev, 0);
892 clear_bit(FLAG_EXPORT, &desc->flags); 894 clear_bit(FLAG_EXPORT, &desc->flags);
893 put_device(dev);
894 device_unregister(dev);
895 } else 895 } else
896 status = -ENODEV; 896 status = -ENODEV;
897 } 897 }
898 898
899 mutex_unlock(&sysfs_lock); 899 mutex_unlock(&sysfs_lock);
900 if (dev) {
901 device_unregister(dev);
902 put_device(dev);
903 }
900done: 904done:
901 if (status) 905 if (status)
902 pr_debug("%s: gpio%d status %d\n", __func__, gpio, status); 906 pr_debug("%s: gpio%d status %d\n", __func__, gpio, status);
@@ -1150,8 +1154,9 @@ EXPORT_SYMBOL_GPL(gpiochip_remove);
1150 * non-zero, this function will return to the caller and not iterate over any 1154 * non-zero, this function will return to the caller and not iterate over any
1151 * more gpio_chips. 1155 * more gpio_chips.
1152 */ 1156 */
1153struct gpio_chip *gpiochip_find(void *data, 1157struct gpio_chip *gpiochip_find(const void *data,
1154 int (*match)(struct gpio_chip *chip, void *data)) 1158 int (*match)(struct gpio_chip *chip,
1159 const void *data))
1155{ 1160{
1156 struct gpio_chip *chip = NULL; 1161 struct gpio_chip *chip = NULL;
1157 unsigned long flags; 1162 unsigned long flags;
@@ -1261,6 +1266,8 @@ void gpio_free(unsigned gpio)
1261 module_put(desc->chip->owner); 1266 module_put(desc->chip->owner);
1262 clear_bit(FLAG_ACTIVE_LOW, &desc->flags); 1267 clear_bit(FLAG_ACTIVE_LOW, &desc->flags);
1263 clear_bit(FLAG_REQUESTED, &desc->flags); 1268 clear_bit(FLAG_REQUESTED, &desc->flags);
1269 clear_bit(FLAG_OPEN_DRAIN, &desc->flags);
1270 clear_bit(FLAG_OPEN_SOURCE, &desc->flags);
1264 } else 1271 } else
1265 WARN_ON(extra_checks); 1272 WARN_ON(extra_checks);
1266 1273
@@ -1282,6 +1289,12 @@ int gpio_request_one(unsigned gpio, unsigned long flags, const char *label)
1282 if (err) 1289 if (err)
1283 return err; 1290 return err;
1284 1291
1292 if (flags & GPIOF_OPEN_DRAIN)
1293 set_bit(FLAG_OPEN_DRAIN, &gpio_desc[gpio].flags);
1294
1295 if (flags & GPIOF_OPEN_SOURCE)
1296 set_bit(FLAG_OPEN_SOURCE, &gpio_desc[gpio].flags);
1297
1285 if (flags & GPIOF_DIR_IN) 1298 if (flags & GPIOF_DIR_IN)
1286 err = gpio_direction_input(gpio); 1299 err = gpio_direction_input(gpio);
1287 else 1300 else
@@ -1431,6 +1444,14 @@ int gpio_direction_output(unsigned gpio, int value)
1431 struct gpio_desc *desc = &gpio_desc[gpio]; 1444 struct gpio_desc *desc = &gpio_desc[gpio];
1432 int status = -EINVAL; 1445 int status = -EINVAL;
1433 1446
1447 /* Open drain pin should not be driven to 1 */
1448 if (value && test_bit(FLAG_OPEN_DRAIN, &desc->flags))
1449 return gpio_direction_input(gpio);
1450
1451 /* Open source pin should not be driven to 0 */
1452 if (!value && test_bit(FLAG_OPEN_SOURCE, &desc->flags))
1453 return gpio_direction_input(gpio);
1454
1434 spin_lock_irqsave(&gpio_lock, flags); 1455 spin_lock_irqsave(&gpio_lock, flags);
1435 1456
1436 if (!gpio_is_valid(gpio)) 1457 if (!gpio_is_valid(gpio))
@@ -1560,6 +1581,7 @@ int __gpio_get_value(unsigned gpio)
1560 int value; 1581 int value;
1561 1582
1562 chip = gpio_to_chip(gpio); 1583 chip = gpio_to_chip(gpio);
1584 /* Should be using gpio_get_value_cansleep() */
1563 WARN_ON(chip->can_sleep); 1585 WARN_ON(chip->can_sleep);
1564 value = chip->get ? chip->get(chip, gpio - chip->base) : 0; 1586 value = chip->get ? chip->get(chip, gpio - chip->base) : 0;
1565 trace_gpio_value(gpio, 1, value); 1587 trace_gpio_value(gpio, 1, value);
@@ -1567,6 +1589,57 @@ int __gpio_get_value(unsigned gpio)
1567} 1589}
1568EXPORT_SYMBOL_GPL(__gpio_get_value); 1590EXPORT_SYMBOL_GPL(__gpio_get_value);
1569 1591
1592/*
1593 * _gpio_set_open_drain_value() - Set the open drain gpio's value.
1594 * @gpio: Gpio whose state need to be set.
1595 * @chip: Gpio chip.
1596 * @value: Non-zero for setting it HIGH otherise it will set to LOW.
1597 */
1598static void _gpio_set_open_drain_value(unsigned gpio,
1599 struct gpio_chip *chip, int value)
1600{
1601 int err = 0;
1602 if (value) {
1603 err = chip->direction_input(chip, gpio - chip->base);
1604 if (!err)
1605 clear_bit(FLAG_IS_OUT, &gpio_desc[gpio].flags);
1606 } else {
1607 err = chip->direction_output(chip, gpio - chip->base, 0);
1608 if (!err)
1609 set_bit(FLAG_IS_OUT, &gpio_desc[gpio].flags);
1610 }
1611 trace_gpio_direction(gpio, value, err);
1612 if (err < 0)
1613 pr_err("%s: Error in set_value for open drain gpio%d err %d\n",
1614 __func__, gpio, err);
1615}
1616
1617/*
1618 * _gpio_set_open_source() - Set the open source gpio's value.
1619 * @gpio: Gpio whose state need to be set.
1620 * @chip: Gpio chip.
1621 * @value: Non-zero for setting it HIGH otherise it will set to LOW.
1622 */
1623static void _gpio_set_open_source_value(unsigned gpio,
1624 struct gpio_chip *chip, int value)
1625{
1626 int err = 0;
1627 if (value) {
1628 err = chip->direction_output(chip, gpio - chip->base, 1);
1629 if (!err)
1630 set_bit(FLAG_IS_OUT, &gpio_desc[gpio].flags);
1631 } else {
1632 err = chip->direction_input(chip, gpio - chip->base);
1633 if (!err)
1634 clear_bit(FLAG_IS_OUT, &gpio_desc[gpio].flags);
1635 }
1636 trace_gpio_direction(gpio, !value, err);
1637 if (err < 0)
1638 pr_err("%s: Error in set_value for open source gpio%d err %d\n",
1639 __func__, gpio, err);
1640}
1641
1642
1570/** 1643/**
1571 * __gpio_set_value() - assign a gpio's value 1644 * __gpio_set_value() - assign a gpio's value
1572 * @gpio: gpio whose value will be assigned 1645 * @gpio: gpio whose value will be assigned
@@ -1581,9 +1654,15 @@ void __gpio_set_value(unsigned gpio, int value)
1581 struct gpio_chip *chip; 1654 struct gpio_chip *chip;
1582 1655
1583 chip = gpio_to_chip(gpio); 1656 chip = gpio_to_chip(gpio);
1657 /* Should be using gpio_set_value_cansleep() */
1584 WARN_ON(chip->can_sleep); 1658 WARN_ON(chip->can_sleep);
1585 trace_gpio_value(gpio, 0, value); 1659 trace_gpio_value(gpio, 0, value);
1586 chip->set(chip, gpio - chip->base, value); 1660 if (test_bit(FLAG_OPEN_DRAIN, &gpio_desc[gpio].flags))
1661 _gpio_set_open_drain_value(gpio, chip, value);
1662 else if (test_bit(FLAG_OPEN_SOURCE, &gpio_desc[gpio].flags))
1663 _gpio_set_open_source_value(gpio, chip, value);
1664 else
1665 chip->set(chip, gpio - chip->base, value);
1587} 1666}
1588EXPORT_SYMBOL_GPL(__gpio_set_value); 1667EXPORT_SYMBOL_GPL(__gpio_set_value);
1589 1668
@@ -1650,7 +1729,12 @@ void gpio_set_value_cansleep(unsigned gpio, int value)
1650 might_sleep_if(extra_checks); 1729 might_sleep_if(extra_checks);
1651 chip = gpio_to_chip(gpio); 1730 chip = gpio_to_chip(gpio);
1652 trace_gpio_value(gpio, 0, value); 1731 trace_gpio_value(gpio, 0, value);
1653 chip->set(chip, gpio - chip->base, value); 1732 if (test_bit(FLAG_OPEN_DRAIN, &gpio_desc[gpio].flags))
1733 _gpio_set_open_drain_value(gpio, chip, value);
1734 else if (test_bit(FLAG_OPEN_SOURCE, &gpio_desc[gpio].flags))
1735 _gpio_set_open_source_value(gpio, chip, value);
1736 else
1737 chip->set(chip, gpio - chip->base, value);
1654} 1738}
1655EXPORT_SYMBOL_GPL(gpio_set_value_cansleep); 1739EXPORT_SYMBOL_GPL(gpio_set_value_cansleep);
1656 1740
diff --git a/drivers/of/gpio.c b/drivers/of/gpio.c
index 7e62d15d60f..bba81216b4d 100644
--- a/drivers/of/gpio.c
+++ b/drivers/of/gpio.c
@@ -78,8 +78,9 @@ err0:
78EXPORT_SYMBOL(of_get_named_gpio_flags); 78EXPORT_SYMBOL(of_get_named_gpio_flags);
79 79
80/** 80/**
81 * of_gpio_count - Count GPIOs for a device 81 * of_gpio_named_count - Count GPIOs for a device
82 * @np: device node to count GPIOs for 82 * @np: device node to count GPIOs for
83 * @propname: property name containing gpio specifier(s)
83 * 84 *
84 * The function returns the count of GPIOs specified for a node. 85 * The function returns the count of GPIOs specified for a node.
85 * 86 *
@@ -93,14 +94,14 @@ EXPORT_SYMBOL(of_get_named_gpio_flags);
93 * defines four GPIOs (so this function will return 4), two of which 94 * defines four GPIOs (so this function will return 4), two of which
94 * are not specified. 95 * are not specified.
95 */ 96 */
96unsigned int of_gpio_count(struct device_node *np) 97unsigned int of_gpio_named_count(struct device_node *np, const char* propname)
97{ 98{
98 unsigned int cnt = 0; 99 unsigned int cnt = 0;
99 100
100 do { 101 do {
101 int ret; 102 int ret;
102 103
103 ret = of_parse_phandle_with_args(np, "gpios", "#gpio-cells", 104 ret = of_parse_phandle_with_args(np, propname, "#gpio-cells",
104 cnt, NULL); 105 cnt, NULL);
105 /* A hole in the gpios = <> counts anyway. */ 106 /* A hole in the gpios = <> counts anyway. */
106 if (ret < 0 && ret != -EEXIST) 107 if (ret < 0 && ret != -EEXIST)
@@ -109,7 +110,7 @@ unsigned int of_gpio_count(struct device_node *np)
109 110
110 return cnt; 111 return cnt;
111} 112}
112EXPORT_SYMBOL(of_gpio_count); 113EXPORT_SYMBOL(of_gpio_named_count);
113 114
114/** 115/**
115 * of_gpio_simple_xlate - translate gpio_spec to the GPIO number and flags 116 * of_gpio_simple_xlate - translate gpio_spec to the GPIO number and flags
@@ -228,7 +229,7 @@ void of_gpiochip_remove(struct gpio_chip *chip)
228} 229}
229 230
230/* Private function for resolving node pointer to gpio_chip */ 231/* Private function for resolving node pointer to gpio_chip */
231static int of_gpiochip_is_match(struct gpio_chip *chip, void *data) 232static int of_gpiochip_is_match(struct gpio_chip *chip, const void *data)
232{ 233{
233 return chip->of_node == data; 234 return chip->of_node == data;
234} 235}
diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
index 1ff4e221cb4..5f52690c3c8 100644
--- a/include/asm-generic/gpio.h
+++ b/include/asm-generic/gpio.h
@@ -142,9 +142,9 @@ extern int __must_check gpiochip_reserve(int start, int ngpio);
142/* add/remove chips */ 142/* add/remove chips */
143extern int gpiochip_add(struct gpio_chip *chip); 143extern int gpiochip_add(struct gpio_chip *chip);
144extern int __must_check gpiochip_remove(struct gpio_chip *chip); 144extern int __must_check gpiochip_remove(struct gpio_chip *chip);
145extern struct gpio_chip *gpiochip_find(void *data, 145extern struct gpio_chip *gpiochip_find(const void *data,
146 int (*match)(struct gpio_chip *chip, 146 int (*match)(struct gpio_chip *chip,
147 void *data)); 147 const void *data));
148 148
149 149
150/* Always use the library code for GPIO management calls, 150/* Always use the library code for GPIO management calls,
diff --git a/include/linux/gpio.h b/include/linux/gpio.h
index ed5a46707ad..6155ecf192b 100644
--- a/include/linux/gpio.h
+++ b/include/linux/gpio.h
@@ -14,6 +14,12 @@
14#define GPIOF_OUT_INIT_LOW (GPIOF_DIR_OUT | GPIOF_INIT_LOW) 14#define GPIOF_OUT_INIT_LOW (GPIOF_DIR_OUT | GPIOF_INIT_LOW)
15#define GPIOF_OUT_INIT_HIGH (GPIOF_DIR_OUT | GPIOF_INIT_HIGH) 15#define GPIOF_OUT_INIT_HIGH (GPIOF_DIR_OUT | GPIOF_INIT_HIGH)
16 16
17/* Gpio pin is open drain */
18#define GPIOF_OPEN_DRAIN (1 << 2)
19
20/* Gpio pin is open source */
21#define GPIOF_OPEN_SOURCE (1 << 3)
22
17/** 23/**
18 * struct gpio - a structure describing a GPIO with configuration 24 * struct gpio - a structure describing a GPIO with configuration
19 * @gpio: the GPIO number 25 * @gpio: the GPIO number
diff --git a/include/linux/mfd/tps65910.h b/include/linux/mfd/tps65910.h
index e34886397f9..1c6c2860d1a 100644
--- a/include/linux/mfd/tps65910.h
+++ b/include/linux/mfd/tps65910.h
@@ -659,6 +659,8 @@
659 659
660 660
661/*Register GPIO (0x80) register.RegisterDescription */ 661/*Register GPIO (0x80) register.RegisterDescription */
662#define GPIO_SLEEP_MASK 0x80
663#define GPIO_SLEEP_SHIFT 7
662#define GPIO_DEB_MASK 0x10 664#define GPIO_DEB_MASK 0x10
663#define GPIO_DEB_SHIFT 4 665#define GPIO_DEB_SHIFT 4
664#define GPIO_PUEN_MASK 0x08 666#define GPIO_PUEN_MASK 0x08
@@ -742,6 +744,11 @@
742#define TPS65910_GPIO_STS BIT(1) 744#define TPS65910_GPIO_STS BIT(1)
743#define TPS65910_GPIO_SET BIT(0) 745#define TPS65910_GPIO_SET BIT(0)
744 746
747/* Max number of TPS65910/11 GPIOs */
748#define TPS65910_NUM_GPIO 6
749#define TPS65911_NUM_GPIO 9
750#define TPS6591X_MAX_NUM_GPIO 9
751
745/* Regulator Index Definitions */ 752/* Regulator Index Definitions */
746#define TPS65910_REG_VRTC 0 753#define TPS65910_REG_VRTC 0
747#define TPS65910_REG_VIO 1 754#define TPS65910_REG_VIO 1
@@ -787,6 +794,7 @@ struct tps65910_board {
787 int irq_base; 794 int irq_base;
788 int vmbch_threshold; 795 int vmbch_threshold;
789 int vmbch2_threshold; 796 int vmbch2_threshold;
797 bool en_gpio_sleep[TPS6591X_MAX_NUM_GPIO];
790 unsigned long regulator_ext_sleep_control[TPS65910_NUM_REGS]; 798 unsigned long regulator_ext_sleep_control[TPS65910_NUM_REGS];
791 struct regulator_init_data *tps65910_pmic_init_data[TPS65910_NUM_REGS]; 799 struct regulator_init_data *tps65910_pmic_init_data[TPS65910_NUM_REGS];
792}; 800};
diff --git a/include/linux/of_gpio.h b/include/linux/of_gpio.h
index b254052a49d..81733d12cbe 100644
--- a/include/linux/of_gpio.h
+++ b/include/linux/of_gpio.h
@@ -50,7 +50,8 @@ static inline struct of_mm_gpio_chip *to_of_mm_gpio_chip(struct gpio_chip *gc)
50extern int of_get_named_gpio_flags(struct device_node *np, 50extern int of_get_named_gpio_flags(struct device_node *np,
51 const char *list_name, int index, enum of_gpio_flags *flags); 51 const char *list_name, int index, enum of_gpio_flags *flags);
52 52
53extern unsigned int of_gpio_count(struct device_node *np); 53extern unsigned int of_gpio_named_count(struct device_node *np,
54 const char* propname);
54 55
55extern int of_mm_gpiochip_add(struct device_node *np, 56extern int of_mm_gpiochip_add(struct device_node *np,
56 struct of_mm_gpio_chip *mm_gc); 57 struct of_mm_gpio_chip *mm_gc);
@@ -71,7 +72,8 @@ static inline int of_get_named_gpio_flags(struct device_node *np,
71 return -ENOSYS; 72 return -ENOSYS;
72} 73}
73 74
74static inline unsigned int of_gpio_count(struct device_node *np) 75static inline unsigned int of_gpio_named_count(struct device_node *np,
76 const char* propname)
75{ 77{
76 return 0; 78 return 0;
77} 79}
@@ -89,6 +91,27 @@ static inline void of_gpiochip_remove(struct gpio_chip *gc) { }
89#endif /* CONFIG_OF_GPIO */ 91#endif /* CONFIG_OF_GPIO */
90 92
91/** 93/**
94 * of_gpio_count - Count GPIOs for a device
95 * @np: device node to count GPIOs for
96 *
97 * The function returns the count of GPIOs specified for a node.
98 *
99 * Note that the empty GPIO specifiers counts too. For example,
100 *
101 * gpios = <0
102 * &pio1 1 2
103 * 0
104 * &pio2 3 4>;
105 *
106 * defines four GPIOs (so this function will return 4), two of which
107 * are not specified.
108 */
109static inline unsigned int of_gpio_count(struct device_node *np)
110{
111 return of_gpio_named_count(np, "gpios");
112}
113
114/**
92 * of_get_gpio_flags() - Get a GPIO number and flags to use with GPIO API 115 * of_get_gpio_flags() - Get a GPIO number and flags to use with GPIO API
93 * @np: device node to get GPIO from 116 * @np: device node to get GPIO from
94 * @index: index of the GPIO 117 * @index: index of the GPIO
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-20 19:45:50 -0400