diff options
author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-06-24 10:42:33 -0400 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-06-25 15:07:29 -0400 |
commit | 79f5b2c7599270aa3dcfffb445f8f520c05a7fc5 (patch) | |
tree | 7136bcd85119075fc624f8a6d55ddb6ac2dc870e | |
parent | 8090c6b9daa04dda649ac0a2209601042abfb0a4 (diff) |
drm/i915: make enable/disable_gt_powersave locking consistent
The enable functions grabbed dev->struct_mutex themselves, whereas
the disable functions expected dev->struct_mutex to be held by the
caller. Move the locking out to the (currently only) callsite of
intel_enable_gt_powersave to make this more consistent.
Originally this was prep work for future patches, but I've chased down
a totally wrong alley. Still, I think this is a sensible
clarification.
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 32 |
2 files changed, 15 insertions, 19 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index fdca5b925c6..3fbc802b494 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -7174,7 +7174,9 @@ void intel_modeset_init_hw(struct drm_device *dev) | |||
7174 | { | 7174 | { |
7175 | intel_init_clock_gating(dev); | 7175 | intel_init_clock_gating(dev); |
7176 | 7176 | ||
7177 | mutex_lock(&dev->struct_mutex); | ||
7177 | intel_enable_gt_powersave(dev); | 7178 | intel_enable_gt_powersave(dev); |
7179 | mutex_unlock(&dev->struct_mutex); | ||
7178 | 7180 | ||
7179 | if (IS_IVYBRIDGE(dev)) | 7181 | if (IS_IVYBRIDGE(dev)) |
7180 | ivb_pch_pwm_override(dev); | 7182 | ivb_pch_pwm_override(dev); |
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 2baba10723f..99bc1f33bfc 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c | |||
@@ -2349,8 +2349,9 @@ int intel_enable_rc6(const struct drm_device *dev) | |||
2349 | return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); | 2349 | return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); |
2350 | } | 2350 | } |
2351 | 2351 | ||
2352 | static void gen6_enable_rps(struct drm_i915_private *dev_priv) | 2352 | static void gen6_enable_rps(struct drm_device *dev) |
2353 | { | 2353 | { |
2354 | struct drm_i915_private *dev_priv = dev->dev_private; | ||
2354 | struct intel_ring_buffer *ring; | 2355 | struct intel_ring_buffer *ring; |
2355 | u32 rp_state_cap; | 2356 | u32 rp_state_cap; |
2356 | u32 gt_perf_status; | 2357 | u32 gt_perf_status; |
@@ -2359,6 +2360,8 @@ static void gen6_enable_rps(struct drm_i915_private *dev_priv) | |||
2359 | int rc6_mode; | 2360 | int rc6_mode; |
2360 | int i; | 2361 | int i; |
2361 | 2362 | ||
2363 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); | ||
2364 | |||
2362 | /* Here begins a magic sequence of register writes to enable | 2365 | /* Here begins a magic sequence of register writes to enable |
2363 | * auto-downclocking. | 2366 | * auto-downclocking. |
2364 | * | 2367 | * |
@@ -2366,7 +2369,6 @@ static void gen6_enable_rps(struct drm_i915_private *dev_priv) | |||
2366 | * userspace... | 2369 | * userspace... |
2367 | */ | 2370 | */ |
2368 | I915_WRITE(GEN6_RC_STATE, 0); | 2371 | I915_WRITE(GEN6_RC_STATE, 0); |
2369 | mutex_lock(&dev_priv->dev->struct_mutex); | ||
2370 | 2372 | ||
2371 | /* Clear the DBG now so we don't confuse earlier errors */ | 2373 | /* Clear the DBG now so we don't confuse earlier errors */ |
2372 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { | 2374 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { |
@@ -2491,15 +2493,17 @@ static void gen6_enable_rps(struct drm_i915_private *dev_priv) | |||
2491 | I915_WRITE(GEN6_PMINTRMSK, 0); | 2493 | I915_WRITE(GEN6_PMINTRMSK, 0); |
2492 | 2494 | ||
2493 | gen6_gt_force_wake_put(dev_priv); | 2495 | gen6_gt_force_wake_put(dev_priv); |
2494 | mutex_unlock(&dev_priv->dev->struct_mutex); | ||
2495 | } | 2496 | } |
2496 | 2497 | ||
2497 | static void gen6_update_ring_freq(struct drm_i915_private *dev_priv) | 2498 | static void gen6_update_ring_freq(struct drm_device *dev) |
2498 | { | 2499 | { |
2500 | struct drm_i915_private *dev_priv = dev->dev_private; | ||
2499 | int min_freq = 15; | 2501 | int min_freq = 15; |
2500 | int gpu_freq, ia_freq, max_ia_freq; | 2502 | int gpu_freq, ia_freq, max_ia_freq; |
2501 | int scaling_factor = 180; | 2503 | int scaling_factor = 180; |
2502 | 2504 | ||
2505 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); | ||
2506 | |||
2503 | max_ia_freq = cpufreq_quick_get_max(0); | 2507 | max_ia_freq = cpufreq_quick_get_max(0); |
2504 | /* | 2508 | /* |
2505 | * Default to measured freq if none found, PCU will ensure we don't go | 2509 | * Default to measured freq if none found, PCU will ensure we don't go |
@@ -2511,8 +2515,6 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv) | |||
2511 | /* Convert from kHz to MHz */ | 2515 | /* Convert from kHz to MHz */ |
2512 | max_ia_freq /= 1000; | 2516 | max_ia_freq /= 1000; |
2513 | 2517 | ||
2514 | mutex_lock(&dev_priv->dev->struct_mutex); | ||
2515 | |||
2516 | /* | 2518 | /* |
2517 | * For each potential GPU frequency, load a ring frequency we'd like | 2519 | * For each potential GPU frequency, load a ring frequency we'd like |
2518 | * to use for memory access. We do this by specifying the IA frequency | 2520 | * to use for memory access. We do this by specifying the IA frequency |
@@ -2543,8 +2545,6 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv) | |||
2543 | continue; | 2545 | continue; |
2544 | } | 2546 | } |
2545 | } | 2547 | } |
2546 | |||
2547 | mutex_unlock(&dev_priv->dev->struct_mutex); | ||
2548 | } | 2548 | } |
2549 | 2549 | ||
2550 | static void ironlake_teardown_rc6(struct drm_device *dev) | 2550 | static void ironlake_teardown_rc6(struct drm_device *dev) |
@@ -2615,12 +2615,11 @@ void ironlake_enable_rc6(struct drm_device *dev) | |||
2615 | if (!intel_enable_rc6(dev)) | 2615 | if (!intel_enable_rc6(dev)) |
2616 | return; | 2616 | return; |
2617 | 2617 | ||
2618 | mutex_lock(&dev->struct_mutex); | 2618 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2619 | |||
2619 | ret = ironlake_setup_rc6(dev); | 2620 | ret = ironlake_setup_rc6(dev); |
2620 | if (ret) { | 2621 | if (ret) |
2621 | mutex_unlock(&dev->struct_mutex); | ||
2622 | return; | 2622 | return; |
2623 | } | ||
2624 | 2623 | ||
2625 | /* | 2624 | /* |
2626 | * GPU can automatically power down the render unit if given a page | 2625 | * GPU can automatically power down the render unit if given a page |
@@ -2629,7 +2628,6 @@ void ironlake_enable_rc6(struct drm_device *dev) | |||
2629 | ret = intel_ring_begin(ring, 6); | 2628 | ret = intel_ring_begin(ring, 6); |
2630 | if (ret) { | 2629 | if (ret) { |
2631 | ironlake_teardown_rc6(dev); | 2630 | ironlake_teardown_rc6(dev); |
2632 | mutex_unlock(&dev->struct_mutex); | ||
2633 | return; | 2631 | return; |
2634 | } | 2632 | } |
2635 | 2633 | ||
@@ -2654,13 +2652,11 @@ void ironlake_enable_rc6(struct drm_device *dev) | |||
2654 | if (ret) { | 2652 | if (ret) { |
2655 | DRM_ERROR("failed to enable ironlake power power savings\n"); | 2653 | DRM_ERROR("failed to enable ironlake power power savings\n"); |
2656 | ironlake_teardown_rc6(dev); | 2654 | ironlake_teardown_rc6(dev); |
2657 | mutex_unlock(&dev->struct_mutex); | ||
2658 | return; | 2655 | return; |
2659 | } | 2656 | } |
2660 | 2657 | ||
2661 | I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN); | 2658 | I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN); |
2662 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); | 2659 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); |
2663 | mutex_unlock(&dev->struct_mutex); | ||
2664 | } | 2660 | } |
2665 | 2661 | ||
2666 | static unsigned long intel_pxfreq(u32 vidfreq) | 2662 | static unsigned long intel_pxfreq(u32 vidfreq) |
@@ -3237,8 +3233,6 @@ void intel_disable_gt_powersave(struct drm_device *dev) | |||
3237 | 3233 | ||
3238 | void intel_enable_gt_powersave(struct drm_device *dev) | 3234 | void intel_enable_gt_powersave(struct drm_device *dev) |
3239 | { | 3235 | { |
3240 | struct drm_i915_private *dev_priv = dev->dev_private; | ||
3241 | |||
3242 | if (IS_IRONLAKE_M(dev)) { | 3236 | if (IS_IRONLAKE_M(dev)) { |
3243 | ironlake_enable_drps(dev); | 3237 | ironlake_enable_drps(dev); |
3244 | ironlake_enable_rc6(dev); | 3238 | ironlake_enable_rc6(dev); |
@@ -3246,8 +3240,8 @@ void intel_enable_gt_powersave(struct drm_device *dev) | |||
3246 | } | 3240 | } |
3247 | 3241 | ||
3248 | if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) { | 3242 | if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) { |
3249 | gen6_enable_rps(dev_priv); | 3243 | gen6_enable_rps(dev); |
3250 | gen6_update_ring_freq(dev_priv); | 3244 | gen6_update_ring_freq(dev); |
3251 | } | 3245 | } |
3252 | } | 3246 | } |
3253 | 3247 | ||