regulator: initialization for ab8500 regulators

The regulators on the AB8500 have a lot of custom
hardware control settings pertaining to 8 external
signals, settings which are board-specific and need
be provided from the platform at startup.

Initialization added for regulators Vana, VextSupply1,
VextSupply2, VextSupply3, Vaux1, Vaux2, Vaux3, VTVout,
Vintcore12, Vaudio, Vdmic, Vamic1, Vamic2, VrefDDR.

Signed-off-by: Bengt Jonsson <bengt.g.jonsson@stericsson.com>
Reviewed-by: Rickard Andersson <rickard.andersson@stericsson.com>
Reviewed-by: Jonas Aberg <jonas.aberg@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>

5 files changed, 279 insertions, 3 deletions

diff --git a/arch/arm/mach-ux500/board-mop500-regulators.h b/arch/arm/mach-ux500/board-mop500-regulators.h
index 2675fae5253..f979b892e4f 100644
--- a/arch/arm/mach-ux500/board-mop500-regulators.h
+++ b/arch/arm/mach-ux500/board-mop500-regulators.h
@@ -14,6 +14,8 @@
 #include <linux/regulator/machine.h>
 #include <linux/regulator/ab8500.h>
 
+extern struct ab8500_regulator_reg_init
+ab8500_regulator_reg_init[AB8500_NUM_REGULATOR_REGISTERS];
 extern struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS];
 
 #endif
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 8790d984cac..d0076453d7f 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -20,6 +20,7 @@
 #include <linux/amba/serial.h>
 #include <linux/spi/spi.h>
 #include <linux/mfd/ab8500.h>
+#include <linux/regulator/ab8500.h>
 #include <linux/mfd/tc3589x.h>
 #include <linux/leds-lp5521.h>
 #include <linux/input.h>
diff --git a/drivers/regulator/ab8500.c b/drivers/regulator/ab8500.c
index 5a77630095d..d157146c865 100644
--- a/drivers/regulator/ab8500.c
+++ b/drivers/regulator/ab8500.c
@@ -526,6 +526,186 @@ static struct ab8500_regulator_info
 
 };
 
+struct ab8500_reg_init {
+        u8 bank;
+        u8 addr;
+        u8 mask;
+};
+
+#define REG_INIT(_id, _bank, _addr, _mask)      \
+        [_id] = {                               \
+                .bank = _bank,                  \
+                .addr = _addr,                  \
+                .mask = _mask,                  \
+        }
+
+static struct ab8500_reg_init ab8500_reg_init[] = {
+        /*
+         * 0x30, VanaRequestCtrl
+         * 0x0C, VpllRequestCtrl
+         * 0xc0, VextSupply1RequestCtrl
+         */
+        REG_INIT(AB8500_REGUREQUESTCTRL2,       0x03, 0x04, 0xfc),
+        /*
+         * 0x03, VextSupply2RequestCtrl
+         * 0x0c, VextSupply3RequestCtrl
+         * 0x30, Vaux1RequestCtrl
+         * 0xc0, Vaux2RequestCtrl
+         */
+        REG_INIT(AB8500_REGUREQUESTCTRL3,       0x03, 0x05, 0xff),
+        /*
+         * 0x03, Vaux3RequestCtrl
+         * 0x04, SwHPReq
+         */
+        REG_INIT(AB8500_REGUREQUESTCTRL4,       0x03, 0x06, 0x07),
+        /*
+         * 0x08, VanaSysClkReq1HPValid
+         * 0x20, Vaux1SysClkReq1HPValid
+         * 0x40, Vaux2SysClkReq1HPValid
+         * 0x80, Vaux3SysClkReq1HPValid
+         */
+        REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xe8),
+        /*
+         * 0x10, VextSupply1SysClkReq1HPValid
+         * 0x20, VextSupply2SysClkReq1HPValid
+         * 0x40, VextSupply3SysClkReq1HPValid
+         */
+        REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x70),
+        /*
+         * 0x08, VanaHwHPReq1Valid
+         * 0x20, Vaux1HwHPReq1Valid
+         * 0x40, Vaux2HwHPReq1Valid
+         * 0x80, Vaux3HwHPReq1Valid
+         */
+        REG_INIT(AB8500_REGUHWHPREQ1VALID1,     0x03, 0x09, 0xe8),
+        /*
+         * 0x01, VextSupply1HwHPReq1Valid
+         * 0x02, VextSupply2HwHPReq1Valid
+         * 0x04, VextSupply3HwHPReq1Valid
+         */
+        REG_INIT(AB8500_REGUHWHPREQ1VALID2,     0x03, 0x0a, 0x07),
+        /*
+         * 0x08, VanaHwHPReq2Valid
+         * 0x20, Vaux1HwHPReq2Valid
+         * 0x40, Vaux2HwHPReq2Valid
+         * 0x80, Vaux3HwHPReq2Valid
+         */
+        REG_INIT(AB8500_REGUHWHPREQ2VALID1,     0x03, 0x0b, 0xe8),
+        /*
+         * 0x01, VextSupply1HwHPReq2Valid
+         * 0x02, VextSupply2HwHPReq2Valid
+         * 0x04, VextSupply3HwHPReq2Valid
+         */
+        REG_INIT(AB8500_REGUHWHPREQ2VALID2,     0x03, 0x0c, 0x07),
+        /*
+         * 0x20, VanaSwHPReqValid
+         * 0x80, Vaux1SwHPReqValid
+         */
+        REG_INIT(AB8500_REGUSWHPREQVALID1,      0x03, 0x0d, 0xa0),
+        /*
+         * 0x01, Vaux2SwHPReqValid
+         * 0x02, Vaux3SwHPReqValid
+         * 0x04, VextSupply1SwHPReqValid
+         * 0x08, VextSupply2SwHPReqValid
+         * 0x10, VextSupply3SwHPReqValid
+         */
+        REG_INIT(AB8500_REGUSWHPREQVALID2,      0x03, 0x0e, 0x1f),
+        /*
+         * 0x02, SysClkReq2Valid1
+         * ...
+         * 0x80, SysClkReq8Valid1
+         */
+        REG_INIT(AB8500_REGUSYSCLKREQVALID1,    0x03, 0x0f, 0xfe),
+        /*
+         * 0x02, SysClkReq2Valid2
+         * ...
+         * 0x80, SysClkReq8Valid2
+         */
+        REG_INIT(AB8500_REGUSYSCLKREQVALID2,    0x03, 0x10, 0xfe),
+        /*
+         * 0x02, VTVoutEna
+         * 0x04, Vintcore12Ena
+         * 0x38, Vintcore12Sel
+         * 0x40, Vintcore12LP
+         * 0x80, VTVoutLP
+         */
+        REG_INIT(AB8500_REGUMISC1,              0x03, 0x80, 0xfe),
+        /*
+         * 0x02, VaudioEna
+         * 0x04, VdmicEna
+         * 0x08, Vamic1Ena
+         * 0x10, Vamic2Ena
+         */
+        REG_INIT(AB8500_VAUDIOSUPPLY,           0x03, 0x83, 0x1e),
+        /*
+         * 0x01, Vamic1_dzout
+         * 0x02, Vamic2_dzout
+         */
+        REG_INIT(AB8500_REGUCTRL1VAMIC,         0x03, 0x84, 0x03),
+        /*
+         * 0x0c, VanaRegu
+         * 0x03, VpllRegu
+         */
+        REG_INIT(AB8500_VPLLVANAREGU,           0x04, 0x06, 0x0f),
+        /*
+         * 0x01, VrefDDREna
+         * 0x02, VrefDDRSleepMode
+         */
+        REG_INIT(AB8500_VREFDDR,                0x04, 0x07, 0x03),
+        /*
+         * 0x03, VextSupply1Regu
+         * 0x0c, VextSupply2Regu
+         * 0x30, VextSupply3Regu
+         * 0x40, ExtSupply2Bypass
+         * 0x80, ExtSupply3Bypass
+         */
+        REG_INIT(AB8500_EXTSUPPLYREGU,          0x04, 0x08, 0xff),
+        /*
+         * 0x03, Vaux1Regu
+         * 0x0c, Vaux2Regu
+         */
+        REG_INIT(AB8500_VAUX12REGU,             0x04, 0x09, 0x0f),
+        /*
+         * 0x03, Vaux3Regu
+         */
+        REG_INIT(AB8500_VRF1VAUX3REGU,          0x04, 0x0a, 0x03),
+        /*
+         * 0x3f, Vsmps1Sel1
+         */
+        REG_INIT(AB8500_VSMPS1SEL1,             0x04, 0x13, 0x3f),
+        /*
+         * 0x0f, Vaux1Sel
+         */
+        REG_INIT(AB8500_VAUX1SEL,               0x04, 0x1f, 0x0f),
+        /*
+         * 0x0f, Vaux2Sel
+         */
+        REG_INIT(AB8500_VAUX2SEL,               0x04, 0x20, 0x0f),
+        /*
+         * 0x07, Vaux3Sel
+         */
+        REG_INIT(AB8500_VRF1VAUX3SEL,           0x04, 0x21, 0x07),
+        /*
+         * 0x01, VextSupply12LP
+         */
+        REG_INIT(AB8500_REGUCTRL2SPARE,         0x04, 0x22, 0x01),
+        /*
+         * 0x04, Vaux1Disch
+         * 0x08, Vaux2Disch
+         * 0x10, Vaux3Disch
+         * 0x20, Vintcore12Disch
+         * 0x40, VTVoutDisch
+         * 0x80, VaudioDisch
+         */
+        REG_INIT(AB8500_REGUCTRLDISCH,          0x04, 0x43, 0xfc),
+        /*
+         * 0x02, VanaDisch