diff options
author | Jorge Eduardo Candelaria <jorge.candelaria@ti.com> | 2010-05-12 13:18:40 -0400 |
---|---|---|
committer | Liam Girdwood <lrg@slimlogic.co.uk> | 2010-05-14 06:20:08 -0400 |
commit | 752ec2f2d97da34abffa1abff81c96183a895b28 (patch) | |
tree | cd28de5e3b1894cb1cd2e9ab10cb21185de34952 | |
parent | 9319b9da35179e11aa9c15d80062d63b36a0517f (diff) |
ARM: McBSP: Add support for omap4 in McBSP driver
McBSP module in OMAP4 needs to be able to set its tx/rx threshold
and enable the transmitter/receiver when starting an audio stream.
Signed-off-by: Jorge Eduardo Candelaria <jorge.candelaria@ti.com>
Signed-off-by: Margarita Olaya Cabrera <magi.olaya@ti.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
-rw-r--r-- | arch/arm/plat-omap/mcbsp.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index 8bbbb93e212..4820cabadce 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c | |||
@@ -488,7 +488,7 @@ void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold) | |||
488 | { | 488 | { |
489 | struct omap_mcbsp *mcbsp; | 489 | struct omap_mcbsp *mcbsp; |
490 | 490 | ||
491 | if (!cpu_is_omap34xx()) | 491 | if (!cpu_is_omap34xx() && !cpu_is_omap44xx()) |
492 | return; | 492 | return; |
493 | 493 | ||
494 | if (!omap_mcbsp_check_valid_id(id)) { | 494 | if (!omap_mcbsp_check_valid_id(id)) { |
@@ -510,7 +510,7 @@ void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold) | |||
510 | { | 510 | { |
511 | struct omap_mcbsp *mcbsp; | 511 | struct omap_mcbsp *mcbsp; |
512 | 512 | ||
513 | if (!cpu_is_omap34xx()) | 513 | if (!cpu_is_omap34xx() && !cpu_is_omap44xx()) |
514 | return; | 514 | return; |
515 | 515 | ||
516 | if (!omap_mcbsp_check_valid_id(id)) { | 516 | if (!omap_mcbsp_check_valid_id(id)) { |
@@ -641,7 +641,7 @@ static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) | |||
641 | * Enable wakup behavior, smart idle and all wakeups | 641 | * Enable wakup behavior, smart idle and all wakeups |
642 | * REVISIT: some wakeups may be unnecessary | 642 | * REVISIT: some wakeups may be unnecessary |
643 | */ | 643 | */ |
644 | if (cpu_is_omap34xx()) { | 644 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) { |
645 | u16 syscon; | 645 | u16 syscon; |
646 | 646 | ||
647 | syscon = MCBSP_READ(mcbsp, SYSCON); | 647 | syscon = MCBSP_READ(mcbsp, SYSCON); |
@@ -664,7 +664,7 @@ static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) | |||
664 | /* | 664 | /* |
665 | * Disable wakup behavior, smart idle and all wakeups | 665 | * Disable wakup behavior, smart idle and all wakeups |
666 | */ | 666 | */ |
667 | if (cpu_is_omap34xx()) { | 667 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) { |
668 | u16 syscon; | 668 | u16 syscon; |
669 | 669 | ||
670 | syscon = MCBSP_READ(mcbsp, SYSCON); | 670 | syscon = MCBSP_READ(mcbsp, SYSCON); |
@@ -913,7 +913,7 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx) | |||
913 | MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7)); | 913 | MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7)); |
914 | } | 914 | } |
915 | 915 | ||
916 | if (cpu_is_omap2430() || cpu_is_omap34xx()) { | 916 | if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) { |
917 | /* Release the transmitter and receiver */ | 917 | /* Release the transmitter and receiver */ |
918 | w = MCBSP_READ_CACHE(mcbsp, XCCR); | 918 | w = MCBSP_READ_CACHE(mcbsp, XCCR); |
919 | w &= ~(tx ? XDISABLE : 0); | 919 | w &= ~(tx ? XDISABLE : 0); |
@@ -943,7 +943,7 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx) | |||
943 | 943 | ||
944 | /* Reset transmitter */ | 944 | /* Reset transmitter */ |
945 | tx &= 1; | 945 | tx &= 1; |
946 | if (cpu_is_omap2430() || cpu_is_omap34xx()) { | 946 | if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) { |
947 | w = MCBSP_READ_CACHE(mcbsp, XCCR); | 947 | w = MCBSP_READ_CACHE(mcbsp, XCCR); |
948 | w |= (tx ? XDISABLE : 0); | 948 | w |= (tx ? XDISABLE : 0); |
949 | MCBSP_WRITE(mcbsp, XCCR, w); | 949 | MCBSP_WRITE(mcbsp, XCCR, w); |
@@ -953,7 +953,7 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx) | |||
953 | 953 | ||
954 | /* Reset receiver */ | 954 | /* Reset receiver */ |
955 | rx &= 1; | 955 | rx &= 1; |
956 | if (cpu_is_omap2430() || cpu_is_omap34xx()) { | 956 | if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) { |
957 | w = MCBSP_READ_CACHE(mcbsp, RCCR); | 957 | w = MCBSP_READ_CACHE(mcbsp, RCCR); |
958 | w |= (rx ? RDISABLE : 0); | 958 | w |= (rx ? RDISABLE : 0); |
959 | MCBSP_WRITE(mcbsp, RCCR, w); | 959 | MCBSP_WRITE(mcbsp, RCCR, w); |