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authorSascha Hauer <s.hauer@pengutronix.de>2011-05-09 12:41:35 -0400
committerSascha Hauer <s.hauer@pengutronix.de>2011-07-07 03:59:59 -0400
commit6b66ef01f550040674798395ec8c1a9e9f55af9a (patch)
tree4afdc3a401c3152a263f7b61268e854777424545
parentdb279c1b8dc8b7da9d8de94a0ce103c0b9b8e1ae (diff)
ARM i.MX: dmav1: kill SoC ifdefs
since we now can include all soc specific headers at once we do not need the ifdeffery anymore. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r--arch/arm/mach-imx/dma-v1.c25
1 files changed, 3 insertions, 22 deletions
diff --git a/arch/arm/mach-imx/dma-v1.c b/arch/arm/mach-imx/dma-v1.c
index 236f1495efa..4d76f67f270 100644
--- a/arch/arm/mach-imx/dma-v1.c
+++ b/arch/arm/mach-imx/dma-v1.c
@@ -475,7 +475,6 @@ void imx_dma_enable(int channel)
475 imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN | 475 imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN |
476 CCR_ACRPT, DMA_CCR(channel)); 476 CCR_ACRPT, DMA_CCR(channel));
477 477
478#ifdef CONFIG_ARCH_MX2
479 if ((cpu_is_mx21() || cpu_is_mx27()) && 478 if ((cpu_is_mx21() || cpu_is_mx27()) &&
480 imxdma->sg && imx_dma_hw_chain(imxdma)) { 479 imxdma->sg && imx_dma_hw_chain(imxdma)) {
481 imxdma->sg = sg_next(imxdma->sg); 480 imxdma->sg = sg_next(imxdma->sg);
@@ -487,7 +486,6 @@ void imx_dma_enable(int channel)
487 DMA_CCR(channel)); 486 DMA_CCR(channel));
488 } 487 }
489 } 488 }
490#endif
491 imxdma->in_use = 1; 489 imxdma->in_use = 1;
492 490
493 local_irq_restore(flags); 491 local_irq_restore(flags);
@@ -518,7 +516,6 @@ void imx_dma_disable(int channel)
518} 516}
519EXPORT_SYMBOL(imx_dma_disable); 517EXPORT_SYMBOL(imx_dma_disable);
520 518
521#ifdef CONFIG_ARCH_MX2
522static void imx_dma_watchdog(unsigned long chno) 519static void imx_dma_watchdog(unsigned long chno)
523{ 520{
524 struct imx_dma_channel *imxdma = &imx_dma_channels[chno]; 521 struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
@@ -530,7 +527,6 @@ static void imx_dma_watchdog(unsigned long chno)
530 if (imxdma->err_handler) 527 if (imxdma->err_handler)
531 imxdma->err_handler(chno, imxdma->data, IMX_DMA_ERR_TIMEOUT); 528 imxdma->err_handler(chno, imxdma->data, IMX_DMA_ERR_TIMEOUT);
532} 529}
533#endif
534 530
535static irqreturn_t dma_err_handler(int irq, void *dev_id) 531static irqreturn_t dma_err_handler(int irq, void *dev_id)
536{ 532{
@@ -654,10 +650,8 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
654{ 650{
655 int i, disr; 651 int i, disr;
656 652
657#ifdef CONFIG_ARCH_MX2
658 if (cpu_is_mx21() || cpu_is_mx27()) 653 if (cpu_is_mx21() || cpu_is_mx27())
659 dma_err_handler(irq, dev_id); 654 dma_err_handler(irq, dev_id);
660#endif
661 655
662 disr = imx_dmav1_readl(DMA_DISR); 656 disr = imx_dmav1_readl(DMA_DISR);
663 657
@@ -703,7 +697,6 @@ int imx_dma_request(int channel, const char *name)
703 imxdma->name = name; 697 imxdma->name = name;
704 local_irq_restore(flags); /* request_irq() can block */ 698 local_irq_restore(flags); /* request_irq() can block */
705 699
706#ifdef CONFIG_ARCH_MX2
707 if (cpu_is_mx21() || cpu_is_mx27()) { 700 if (cpu_is_mx21() || cpu_is_mx27()) {
708 ret = request_irq(MX2x_INT_DMACH0 + channel, 701 ret = request_irq(MX2x_INT_DMACH0 + channel,
709 dma_irq_handler, 0, "DMA", NULL); 702 dma_irq_handler, 0, "DMA", NULL);
@@ -717,7 +710,6 @@ int imx_dma_request(int channel, const char *name)
717 imxdma->watchdog.function = &imx_dma_watchdog; 710 imxdma->watchdog.function = &imx_dma_watchdog;
718 imxdma->watchdog.data = channel; 711 imxdma->watchdog.data = channel;
719 } 712 }
720#endif
721 713
722 return ret; 714 return ret;
723} 715}
@@ -744,10 +736,8 @@ void imx_dma_free(int channel)
744 imx_dma_disable(channel); 736 imx_dma_disable(channel);
745 imxdma->name = NULL; 737 imxdma->name = NULL;
746 738
747#ifdef CONFIG_ARCH_MX2
748 if (cpu_is_mx21() || cpu_is_mx27()) 739 if (cpu_is_mx21() || cpu_is_mx27())
749 free_irq(MX2x_INT_DMACH0 + channel, NULL); 740 free_irq(MX2x_INT_DMACH0 + channel, NULL);
750#endif
751 741
752 local_irq_restore(flags); 742 local_irq_restore(flags);
753} 743}
@@ -803,21 +793,13 @@ static int __init imx_dma_init(void)
803 int ret = 0; 793 int ret = 0;
804 int i; 794 int i;
805 795
806#ifdef CONFIG_ARCH_MX1
807 if (cpu_is_mx1()) 796 if (cpu_is_mx1())
808 imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR); 797 imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
809 else 798 else if (cpu_is_mx21())
810#endif
811#ifdef CONFIG_MACH_MX21
812 if (cpu_is_mx21())
813 imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR); 799 imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
814 else 800 else if (cpu_is_mx27())
815#endif
816#ifdef CONFIG_MACH_MX27
817 if (cpu_is_mx27())
818 imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR); 801 imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
819 else 802 else
820#endif
821 return 0; 803 return 0;
822 804
823 dma_clk = clk_get(NULL, "dma"); 805 dma_clk = clk_get(NULL, "dma");
@@ -828,7 +810,6 @@ static int __init imx_dma_init(void)
828 /* reset DMA module */ 810 /* reset DMA module */
829 imx_dmav1_writel(DCR_DRST, DMA_DCR); 811 imx_dmav1_writel(DCR_DRST, DMA_DCR);
830 812
831#ifdef CONFIG_ARCH_MX1
832 if (cpu_is_mx1()) { 813 if (cpu_is_mx1()) {
833 ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", NULL); 814 ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", NULL);
834 if (ret) { 815 if (ret) {
@@ -843,7 +824,7 @@ static int __init imx_dma_init(void)
843 return ret; 824 return ret;
844 } 825 }
845 } 826 }
846#endif 827
847 /* enable DMA module */ 828 /* enable DMA module */
848 imx_dmav1_writel(DCR_DEN, DMA_DCR); 829 imx_dmav1_writel(DCR_DEN, DMA_DCR);
849 830