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authorGreg Kroah-Hartman <gregkh@suse.de>2010-10-08 14:05:47 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2010-10-08 14:05:47 -0400
commit66cbd3ab35d35580ddf98304c280a6231685aa41 (patch)
tree64a55ec99419a0cd9a1114588964d15a5c1ad3a1
parent370adc7cb052a29531b8177d3be770ae9e631bd2 (diff)
Staging: brcm80211: s/uint32/u32/
Use the kernel types, don't invent your own. Cc: Brett Rudley <brudley@broadcom.com> Cc: Henry Ptasinski <henryp@broadcom.com> Cc: Nohee Ko <noheek@broadcom.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat
-rw-r--r--drivers/staging/brcm80211/brcmfmac/bcmsdh.c44
-rw-r--r--drivers/staging/brcm80211/brcmfmac/bcmsdh_linux.c4
-rw-r--r--drivers/staging/brcm80211/brcmfmac/bcmsdh_sdmmc.c54
-rw-r--r--drivers/staging/brcm80211/brcmfmac/bcmutils.c20
-rw-r--r--drivers/staging/brcm80211/brcmfmac/dhd.h10
-rw-r--r--drivers/staging/brcm80211/brcmfmac/dhd_cdc.c8
-rw-r--r--drivers/staging/brcm80211/brcmfmac/dhd_common.c28
-rw-r--r--drivers/staging/brcm80211/brcmfmac/dhd_linux.c26
-rw-r--r--drivers/staging/brcm80211/brcmfmac/dhd_sdio.c86
-rw-r--r--drivers/staging/brcm80211/brcmfmac/wl_cfg80211.c150
-rw-r--r--drivers/staging/brcm80211/brcmfmac/wl_cfg80211.h40
-rw-r--r--drivers/staging/brcm80211/brcmfmac/wl_iw.c42
-rw-r--r--drivers/staging/brcm80211/brcmfmac/wl_iw.h4
-rw-r--r--drivers/staging/brcm80211/include/aidmp.h230
-rw-r--r--drivers/staging/brcm80211/include/bcm_rpc.h2
-rw-r--r--drivers/staging/brcm80211/include/bcm_rpc_tp.h2
-rw-r--r--drivers/staging/brcm80211/include/bcm_xdr.h12
-rw-r--r--drivers/staging/brcm80211/include/bcmcdc.h8
-rw-r--r--drivers/staging/brcm80211/include/bcmdefs.h6
-rw-r--r--drivers/staging/brcm80211/include/bcmendian.h36
-rw-r--r--drivers/staging/brcm80211/include/bcmnvram.h10
-rw-r--r--drivers/staging/brcm80211/include/bcmsdbus.h12
-rw-r--r--drivers/staging/brcm80211/include/bcmsdh.h26
-rw-r--r--drivers/staging/brcm80211/include/bcmsdh_sdmmc.h8
-rw-r--r--drivers/staging/brcm80211/include/bcmsdpcm.h68
-rw-r--r--drivers/staging/brcm80211/include/bcmsrom_tbl.h4
-rw-r--r--drivers/staging/brcm80211/include/bcmutils.h36
-rw-r--r--drivers/staging/brcm80211/include/d11.h104
-rw-r--r--drivers/staging/brcm80211/include/dbus.h14
-rw-r--r--drivers/staging/brcm80211/include/hndpmu.h28
-rw-r--r--drivers/staging/brcm80211/include/hndrte_armtrap.h40
-rw-r--r--drivers/staging/brcm80211/include/hndrte_cons.h2
-rw-r--r--drivers/staging/brcm80211/include/linux_osl.h36
-rw-r--r--drivers/staging/brcm80211/include/msgtrace.h6
-rw-r--r--drivers/staging/brcm80211/include/nicpci.h14
-rw-r--r--drivers/staging/brcm80211/include/pci_core.h46
-rw-r--r--drivers/staging/brcm80211/include/pcicfg.h28
-rw-r--r--drivers/staging/brcm80211/include/pcie_core.h46
-rw-r--r--drivers/staging/brcm80211/include/proto/802.11.h32
-rw-r--r--drivers/staging/brcm80211/include/proto/bcmevent.h10
-rw-r--r--drivers/staging/brcm80211/include/sbchipc.h258
-rw-r--r--drivers/staging/brcm80211/include/sbconfig.h74
-rw-r--r--drivers/staging/brcm80211/include/sbhnddma.h92
-rw-r--r--drivers/staging/brcm80211/include/sbhndpio.h4
-rw-r--r--drivers/staging/brcm80211/include/sbsdpcmdev.h80
-rw-r--r--drivers/staging/brcm80211/include/sbsocram.h54
-rw-r--r--drivers/staging/brcm80211/include/siutils.h66
-rw-r--r--drivers/staging/brcm80211/include/spid.h6
-rw-r--r--drivers/staging/brcm80211/include/typedefs.h5
-rw-r--r--drivers/staging/brcm80211/include/wlioctl.h690
-rw-r--r--drivers/staging/brcm80211/phy/wlc_phy_cmn.c102
-rw-r--r--drivers/staging/brcm80211/phy/wlc_phy_hal.h12
-rw-r--r--drivers/staging/brcm80211/phy/wlc_phy_int.h76
-rw-r--r--drivers/staging/brcm80211/phy/wlc_phy_lcn.c130
-rw-r--r--drivers/staging/brcm80211/phy/wlc_phy_lcn.h18
-rw-r--r--drivers/staging/brcm80211/phy/wlc_phy_n.c200
-rw-r--r--drivers/staging/brcm80211/phy/wlc_phytbl_lcn.c38
-rw-r--r--drivers/staging/brcm80211/phy/wlc_phytbl_lcn.h8
-rw-r--r--drivers/staging/brcm80211/phy/wlc_phytbl_n.c100
-rw-r--r--drivers/staging/brcm80211/phy/wlc_phytbl_n.h12
-rw-r--r--drivers/staging/brcm80211/sys/wl_dbg.h4
-rw-r--r--drivers/staging/brcm80211/sys/wl_export.h6
-rw-r--r--drivers/staging/brcm80211/sys/wl_mac80211.c32
-rw-r--r--drivers/staging/brcm80211/sys/wl_mac80211.h12
-rw-r--r--drivers/staging/brcm80211/sys/wl_ucode.h14
-rw-r--r--drivers/staging/brcm80211/sys/wl_ucode_loader.c12
-rw-r--r--drivers/staging/brcm80211/sys/wlc_ampdu.c42
-rw-r--r--drivers/staging/brcm80211/sys/wlc_ampdu.h4
-rw-r--r--drivers/staging/brcm80211/sys/wlc_bmac.c136
-rw-r--r--drivers/staging/brcm80211/sys/wlc_bmac.h38
-rw-r--r--drivers/staging/brcm80211/sys/wlc_bsscfg.h10
-rw-r--r--drivers/staging/brcm80211/sys/wlc_channel.h2
-rw-r--r--drivers/staging/brcm80211/sys/wlc_event.h2
-rw-r--r--drivers/staging/brcm80211/sys/wlc_key.h4
-rw-r--r--drivers/staging/brcm80211/sys/wlc_mac80211.c84
-rw-r--r--drivers/staging/brcm80211/sys/wlc_mac80211.h66
-rw-r--r--drivers/staging/brcm80211/sys/wlc_phy_shim.c14
-rw-r--r--drivers/staging/brcm80211/sys/wlc_phy_shim.h18
-rw-r--r--drivers/staging/brcm80211/sys/wlc_pub.h32
-rw-r--r--drivers/staging/brcm80211/sys/wlc_rate.c2
-rw-r--r--drivers/staging/brcm80211/sys/wlc_rate.h10
-rw-r--r--drivers/staging/brcm80211/sys/wlc_rpc.h20
-rw-r--r--drivers/staging/brcm80211/sys/wlc_scb.h10
-rw-r--r--drivers/staging/brcm80211/util/aiutils.c76
-rw-r--r--drivers/staging/brcm80211/util/bcmotp.c18
-rw-r--r--drivers/staging/brcm80211/util/bcmsrom.c16
-rw-r--r--drivers/staging/brcm80211/util/bcmutils.c4
-rw-r--r--drivers/staging/brcm80211/util/hnddma.c88
-rw-r--r--drivers/staging/brcm80211/util/hndpmu.c182
-rw-r--r--drivers/staging/brcm80211/util/linux_osl.c14
-rw-r--r--drivers/staging/brcm80211/util/nicpci.c84
-rw-r--r--drivers/staging/brcm80211/util/qmath.c2
-rw-r--r--drivers/staging/brcm80211/util/sbutils.c52
-rw-r--r--drivers/staging/brcm80211/util/siutils.c80
-rw-r--r--drivers/staging/brcm80211/util/siutils_priv.h6
95 files changed, 2299 insertions, 2304 deletions
diff --git a/drivers/staging/brcm80211/brcmfmac/bcmsdh.c b/drivers/staging/brcm80211/brcmfmac/bcmsdh.c
index 8086b62c34b..fb051208843 100644
--- a/drivers/staging/brcm80211/brcmfmac/bcmsdh.c
+++ b/drivers/staging/brcm80211/brcmfmac/bcmsdh.c
@@ -36,11 +36,11 @@ const uint bcmsdh_msglevel = BCMSDH_ERROR_VAL;
36struct bcmsdh_info { 36struct bcmsdh_info {
37 bool init_success; /* underlying driver successfully attached */ 37 bool init_success; /* underlying driver successfully attached */
38 void *sdioh; /* handler for sdioh */ 38 void *sdioh; /* handler for sdioh */
39 uint32 vendevid; /* Target Vendor and Device ID on SD bus */ 39 u32 vendevid; /* Target Vendor and Device ID on SD bus */
40 osl_t *osh; 40 osl_t *osh;
41 bool regfail; /* Save status of last 41 bool regfail; /* Save status of last
42 reg_read/reg_write call */ 42 reg_read/reg_write call */
43 uint32 sbwad; /* Save backplane window address */ 43 u32 sbwad; /* Save backplane window address */
44}; 44};
45/* local copy of bcm sd handler */ 45/* local copy of bcm sd handler */
46bcmsdh_info_t *l_bcmsdh; 46bcmsdh_info_t *l_bcmsdh;
@@ -78,7 +78,7 @@ bcmsdh_info_t *bcmsdh_attach(osl_t *osh, void *cfghdl, void **regsva, uint irq)
78 bcmsdh->osh = osh; 78 bcmsdh->osh = osh;
79 bcmsdh->init_success = TRUE; 79 bcmsdh->init_success = TRUE;
80 80
81 *regsva = (uint32 *) SI_ENUM_BASE; 81 *regsva = (u32 *) SI_ENUM_BASE;
82 82
83 /* Report the BAR, to fix if needed */ 83 /* Report the BAR, to fix if needed */
84 bcmsdh->sbwad = SI_ENUM_BASE; 84 bcmsdh->sbwad = SI_ENUM_BASE;
@@ -181,7 +181,7 @@ int bcmsdh_devremove_reg(void *sdh, bcmsdh_cb_fn_t fn, void *argh)
181 return BCME_UNSUPPORTED; 181 return BCME_UNSUPPORTED;
182} 182}
183 183
184u8 bcmsdh_cfg_read(void *sdh, uint fnc_num, uint32 addr, int *err) 184u8 bcmsdh_cfg_read(void *sdh, uint fnc_num, u32 addr, int *err)
185{ 185{
186 bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *) sdh; 186 bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *) sdh;
187 SDIOH_API_RC status; 187 SDIOH_API_RC status;
@@ -217,7 +217,7 @@ u8 bcmsdh_cfg_read(void *sdh, uint fnc_num, uint32 addr, int *err)
217} 217}
218 218
219void 219void
220bcmsdh_cfg_write(void *sdh, uint fnc_num, uint32 addr, u8 data, int *err) 220bcmsdh_cfg_write(void *sdh, uint fnc_num, u32 addr, u8 data, int *err)
221{ 221{
222 bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *) sdh; 222 bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *) sdh;
223 SDIOH_API_RC status; 223 SDIOH_API_RC status;
@@ -249,11 +249,11 @@ bcmsdh_cfg_write(void *sdh, uint fnc_num, uint32 addr, u8 data, int *err)
249 __func__, fnc_num, addr, data)); 249 __func__, fnc_num, addr, data));
250} 250}
251 251
252uint32 bcmsdh_cfg_read_word(void *sdh, uint fnc_num, uint32 addr, int *err) 252u32 bcmsdh_cfg_read_word(void *sdh, uint fnc_num, u32 addr, int *err)
253{ 253{
254 bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *) sdh; 254 bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *) sdh;
255 SDIOH_API_RC status; 255 SDIOH_API_RC status;
256 uint32 data = 0; 256 u32 data = 0;
257 257
258 if (!bcmsdh) 258 if (!bcmsdh)
259 bcmsdh = l_bcmsdh; 259 bcmsdh = l_bcmsdh;
@@ -267,14 +267,14 @@ uint32 bcmsdh_cfg_read_word(void *sdh, uint fnc_num, uint32 addr, int *err)
267 if (err) 267 if (err)
268 *err = (SDIOH_API_SUCCESS(status) ? 0 : BCME_SDIO_ERROR); 268 *err = (SDIOH_API_SUCCESS(status) ? 0 : BCME_SDIO_ERROR);
269 269
270 BCMSDH_INFO(("%s:fun = %d, addr = 0x%x, uint32data = 0x%x\n", 270 BCMSDH_INFO(("%s:fun = %d, addr = 0x%x, u32data = 0x%x\n",
271 __func__, fnc_num, addr, data)); 271 __func__, fnc_num, addr, data));
272 272
273 return data; 273 return data;
274} 274}
275 275
276void 276void
277bcmsdh_cfg_write_word(void *sdh, uint fnc_num, uint32 addr, uint32 data, 277bcmsdh_cfg_write_word(void *sdh, uint fnc_num, u32 addr, u32 data,
278 int *err) 278 int *err)
279{ 279{
280 bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *) sdh; 280 bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *) sdh;
@@ -292,7 +292,7 @@ bcmsdh_cfg_write_word(void *sdh, uint fnc_num, uint32 addr, uint32 data,
292 if (err) 292 if (err)
293 *err = (SDIOH_API_SUCCESS(status) ? 0 : BCME_SDIO_ERROR); 293 *err = (SDIOH_API_SUCCESS(status) ? 0 : BCME_SDIO_ERROR);
294 294
295 BCMSDH_INFO(("%s:fun = %d, addr = 0x%x, uint32data = 0x%x\n", 295 BCMSDH_INFO(("%s:fun = %d, addr = 0x%x, u32data = 0x%x\n",
296 __func__, fnc_num, addr, data)); 296 __func__, fnc_num, addr, data));
297} 297}
298 298
@@ -336,7 +336,7 @@ int bcmsdh_cis_read(void *sdh, uint func, u8 * cis, uint length)
336 return SDIOH_API_SUCCESS(status) ? 0 : BCME_ERROR; 336 return SDIOH_API_SUCCESS(status) ? 0 : BCME_ERROR;
337} 337}
338 338
339static int bcmsdhsdio_set_sbaddr_window(void *sdh, uint32 address) 339static int bcmsdhsdio_set_sbaddr_window(void *sdh, u32 address)
340{ 340{
341 int err = 0; 341 int err = 0;
342 bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *) sdh; 342 bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *) sdh;
@@ -353,11 +353,11 @@ static int bcmsdhsdio_set_sbaddr_window(void *sdh, uint32 address)
353 return err; 353 return err;
354} 354}
355 355
356uint32 bcmsdh_reg_read(void *sdh, uint32 addr, uint size) 356u32 bcmsdh_reg_read(void *sdh, u32 addr, uint size)
357{ 357{
358 bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *) sdh; 358 bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *) sdh;
359 SDIOH_API_RC status; 359 SDIOH_API_RC status;
360 uint32 word = 0; 360 u32 word = 0;
361 uint bar0 = addr & ~SBSDIO_SB_OFT_ADDR_MASK; 361 uint bar0 = addr & ~SBSDIO_SB_OFT_ADDR_MASK;
362 362
363 BCMSDH_INFO(("%s:fun = 1, addr = 0x%x, ", __func__, addr)); 363 BCMSDH_INFO(("%s:fun = 1, addr = 0x%x, ", __func__, addr));
@@ -383,7 +383,7 @@ uint32 bcmsdh_reg_read(void *sdh, uint32 addr, uint size)
383 383
384 bcmsdh->regfail = !(SDIOH_API_SUCCESS(status)); 384 bcmsdh->regfail = !(SDIOH_API_SUCCESS(status));
385 385
386 BCMSDH_INFO(("uint32data = 0x%x\n", word)); 386 BCMSDH_INFO(("u32data = 0x%x\n", word));
387 387
388 /* if ok, return appropriately masked word */ 388 /* if ok, return appropriately masked word */
389 if (SDIOH_API_SUCCESS(status)) { 389 if (SDIOH_API_SUCCESS(status)) {
@@ -392,7 +392,7 @@ uint32 bcmsdh_reg_read(void *sdh, uint32 addr, uint size)
392 return word & 0xff; 392 return word & 0xff;
393 case sizeof(u16): 393 case sizeof(u16):
394 return word & 0xffff; 394 return word & 0xffff;
395 case sizeof(uint32): 395 case sizeof(u32):
396 return word; 396 return word;
397 default: 397 default:
398 bcmsdh->regfail = TRUE; 398 bcmsdh->regfail = TRUE;
@@ -406,7 +406,7 @@ uint32 bcmsdh_reg_read(void *sdh, uint32 addr, uint size)
406 return 0xFFFFFFFF; 406 return 0xFFFFFFFF;
407} 407}
408 408
409uint32 bcmsdh_reg_write(void *sdh, uint32 addr, uint size, uint32 data) 409u32 bcmsdh_reg_write(void *sdh, u32 addr, uint size, u32 data)
410{ 410{
411 bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *) sdh; 411 bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *) sdh;
412 SDIOH_API_RC status; 412 SDIOH_API_RC status;
@@ -451,7 +451,7 @@ bool bcmsdh_regfail(void *sdh)
451} 451}
452 452
453int 453int
454bcmsdh_recv_buf(void *sdh, uint32 addr, uint fn, uint flags, 454bcmsdh_recv_buf(void *sdh, u32 addr, uint fn, uint flags,
455 u8 *buf, uint nbytes, void *pkt, 455 u8 *buf, uint nbytes, void *pkt,
456 bcmsdh_cmplt_fn_t complete, void *handle) 456 bcmsdh_cmplt_fn_t complete, void *handle)
457{ 457{
@@ -496,7 +496,7 @@ bcmsdh_recv_buf(void *sdh, uint32 addr, uint fn, uint flags,
496} 496}
497 497
498int 498int
499bcmsdh_send_buf(void *sdh, uint32 addr, uint fn, uint flags, 499bcmsdh_send_buf(void *sdh, u32 addr, uint fn, uint flags,
500 u8 *buf, uint nbytes, void *pkt, 500 u8 *buf, uint nbytes, void *pkt,
501 bcmsdh_cmplt_fn_t complete, void *handle) 501 bcmsdh_cmplt_fn_t complete, void *handle)
502{ 502{
@@ -540,7 +540,7 @@ bcmsdh_send_buf(void *sdh, uint32 addr, uint fn, uint flags,
540 return SDIOH_API_SUCCESS(status) ? 0 : BCME_ERROR; 540 return SDIOH_API_SUCCESS(status) ? 0 : BCME_ERROR;
541} 541}
542 542
543int bcmsdh_rwdata(void *sdh, uint rw, uint32 addr, u8 *buf, uint nbytes) 543int bcmsdh_rwdata(void *sdh, uint rw, u32 addr, u8 *buf, uint nbytes)
544{ 544{
545 bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *) sdh; 545 bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *) sdh;
546 SDIOH_API_RC status; 546 SDIOH_API_RC status;
@@ -612,12 +612,12 @@ void *bcmsdh_get_sdioh(bcmsdh_info_t *sdh)
612} 612}
613 613
614/* Function to pass device-status bits to DHD. */ 614/* Function to pass device-status bits to DHD. */
615uint32 bcmsdh_get_dstatus(void *sdh) 615u32 bcmsdh_get_dstatus(void *sdh)
616{ 616{
617 return 0; 617 return 0;
618} 618}
619 619
620uint32 bcmsdh_cur_sbwad(void *sdh) 620u32 bcmsdh_cur_sbwad(void *sdh)
621{ 621{
622 bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *) sdh; 622 bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *) sdh;
623 623
@@ -627,7 +627,7 @@ uint32 bcmsdh_cur_sbwad(void *sdh)
627 return bcmsdh->sbwad; 627 return bcmsdh->sbwad;
628} 628}
629 629
630void bcmsdh_chipinfo(void *sdh, uint32 chip, uint32 chiprev) 630void bcmsdh_chipinfo(void *sdh, u32 chip, u32 chiprev)
631{ 631{
632 return; 632 return;
633} 633}
diff --git a/drivers/staging/brcm80211/brcmfmac/bcmsdh_linux.c b/drivers/staging/brcm80211/brcmfmac/bcmsdh_linux.c
index 8e7be0d7a57..d923d545845 100644
--- a/drivers/staging/brcm80211/brcmfmac/bcmsdh_linux.c
+++ b/drivers/staging/brcm80211/brcmfmac/bcmsdh_linux.c
@@ -164,7 +164,7 @@ int bcmsdh_probe(struct device *dev)
164 struct resource *r; 164 struct resource *r;
165#endif /* BCMLXSDMMC */ 165#endif /* BCMLXSDMMC */
166 int irq = 0; 166 int irq = 0;
167 uint32 vendevid; 167 u32 vendevid;
168 unsigned long irq_flags = 0; 168 unsigned long irq_flags = 0;
169 169
170#if !defined(BCMLXSDMMC) && defined(BCMPLATFORM_BUS) 170#if !defined(BCMLXSDMMC) && defined(BCMPLATFORM_BUS)
@@ -384,7 +384,7 @@ bcmsdh_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
384 if ((pdev->vendor == VENDOR_TI) 384 if ((pdev->vendor == VENDOR_TI)
385 && ((pdev->device == PCIXX21_FLASHMEDIA_ID) 385 && ((pdev->device == PCIXX21_FLASHMEDIA_ID)
386 || (pdev->device == PCIXX21_FLASHMEDIA0_ID))) { 386 || (pdev->device == PCIXX21_FLASHMEDIA0_ID))) {
387 uint32 config_reg; 387 u32 config_reg;
388 388
389 SDLX_MSG(("%s: Disabling TI FlashMedia Controller.\n", 389 SDLX_MSG(("%s: Disabling TI FlashMedia Controller.\n",
390 __func__)); 390 __func__));
diff --git a/drivers/staging/brcm80211/brcmfmac/bcmsdh_sdmmc.c b/drivers/staging/brcm80211/brcmfmac/bcmsdh_sdmmc.c
index c1b9ade3a0c..47617844c8e 100644
--- a/drivers/staging/brcm80211/brcmfmac/bcmsdh_sdmmc.c
+++ b/drivers/staging/brcm80211/brcmfmac/bcmsdh_sdmmc.c
@@ -44,7 +44,7 @@ extern void sdio_function_cleanup(void);
44static void IRQHandler(struct sdio_func *func); 44static void IRQHandler(struct sdio_func *func);
45static void IRQHandlerF2(struct sdio_func *func); 45static void IRQHandlerF2(struct sdio_func *func);
46#endif /* !defined(OOB_INTR_ONLY) */ 46#endif /* !defined(OOB_INTR_ONLY) */
47static int sdioh_sdmmc_get_cisaddr(sdioh_info_t *sd, uint32 regaddr); 47static int sdioh_sdmmc_get_cisaddr(sdioh_info_t *sd, u32 regaddr);
48extern int sdio_reset_comm(struct mmc_card *card); 48extern int sdio_reset_comm(struct mmc_card *card);
49 49
50extern PBCMSDH_SDMMC_INSTANCE gInstance; 50extern PBCMSDH_SDMMC_INSTANCE gInstance;
@@ -66,13 +66,13 @@ DHD_PM_RESUME_WAIT_INIT(sdioh_request_buffer_wait);
66 66
67#define DMA_ALIGN_MASK 0x03 67#define DMA_ALIGN_MASK 0x03
68 68
69int sdioh_sdmmc_card_regread(sdioh_info_t *sd, int func, uint32 regaddr, 69int sdioh_sdmmc_card_regread(sdioh_info_t *sd, int func, u32 regaddr,
70 int regsize, uint32 *data); 70 int regsize, u32 *data);
71 71
72static int sdioh_sdmmc_card_enablefuncs(sdioh_info_t *sd) 72static int sdioh_sdmmc_card_enablefuncs(sdioh_info_t *sd)
73{ 73{
74 int err_ret; 74 int err_ret;
75 uint32 fbraddr; 75 u32 fbraddr;
76 u8 func; 76 u8 func;
77 77
78 sd_trace(("%s\n", __func__)); 78 sd_trace(("%s\n", __func__));
@@ -406,7 +406,7 @@ sdioh_iovar_op(sdioh_info_t *si, const char *name,
406 int val_size; 406 int val_size;
407 int32 int_val = 0; 407 int32 int_val = 0;
408 bool bool_val; 408 bool bool_val;
409 uint32 actionid; 409 u32 actionid;
410 410
411 ASSERT(name); 411 ASSERT(name);
412 ASSERT(len >= 0); 412 ASSERT(len >= 0);
@@ -468,7 +468,7 @@ sdioh_iovar_op(sdioh_info_t *si, const char *name,
468 break; 468 break;
469 469
470 case IOV_GVAL(IOV_BLOCKSIZE): 470 case IOV_GVAL(IOV_BLOCKSIZE):
471 if ((uint32) int_val > si->num_funcs) { 471 if ((u32) int_val > si->num_funcs) {
472 bcmerror = BCME_BADARG; 472 bcmerror = BCME_BADARG;
473 break; 473 break;
474 } 474 }
@@ -478,7 +478,7 @@ sdioh_iovar_op(sdioh_info_t *si, const char *name,
478 478
479 case IOV_SVAL(IOV_BLOCKSIZE): 479 case IOV_SVAL(IOV_BLOCKSIZE):
480 { 480 {
481 uint func = ((uint32) int_val >> 16); 481 uint func = ((u32) int_val >> 16);
482 uint blksize = (u16) int_val; 482 uint blksize = (u16) int_val;
483 uint maxsize; 483 uint maxsize;
484 484
@@ -542,7 +542,7 @@ sdioh_iovar_op(sdioh_info_t *si, const char *name,
542 break; 542 break;
543 543
544 case IOV_GVAL(IOV_DIVISOR): 544 case IOV_GVAL(IOV_DIVISOR):
545 int_val = (uint32) sd_divisor; 545 int_val = (u32) sd_divisor;
546 bcopy(&int_val, arg, val_size); 546 bcopy(&int_val, arg, val_size);
547 break; 547 break;
548 548
@@ -551,7 +551,7 @@ sdioh_iovar_op(sdioh_info_t *si, const char *name,
551 break; 551 break;
552 552
553 case IOV_GVAL(IOV_POWER): 553 case IOV_GVAL(IOV_POWER):
554 int_val = (uint32) sd_power; 554 int_val = (u32) sd_power;
555 bcopy(&int_val, arg, val_size); 555 bcopy(&int_val, arg, val_size);
556 break; 556 break;
557 557
@@ -560,7 +560,7 @@ sdioh_iovar_op(sdioh_info_t *si, const char *name,
560 break; 560 break;
561 561
562 case IOV_GVAL(IOV_CLOCK): 562 case IOV_GVAL(IOV_CLOCK):
563 int_val = (uint32) sd_clock; 563 int_val = (u32) sd_clock;
564 bcopy(&int_val, arg, val_size); 564 bcopy(&int_val, arg, val_size);
565 break; 565 break;
566 566
@@ -569,7 +569,7 @@ sdioh_iovar_op(sdioh_info_t *si, const char *name,
569 break; 569 break;
570 570
571 case IOV_GVAL(IOV_SDMODE): 571 case IOV_GVAL(IOV_SDMODE):
572 int_val = (uint32) sd_sdmode; 572 int_val = (u32) sd_sdmode;
573 bcopy(&int_val, arg, val_size); 573 bcopy(&int_val, arg, val_size);
574 break; 574 break;
575 575
@@ -578,7 +578,7 @@ sdioh_iovar_op(sdioh_info_t *si, const char *name,
578 break; 578 break;
579 579
580 case IOV_GVAL(IOV_HISPEED): 580 case IOV_GVAL(IOV_HISPEED):
581 int_val = (uint32) sd_hiok; 581 int_val = (u32) sd_hiok;
582 bcopy(&int_val, arg, val_size); 582 bcopy(&int_val, arg, val_size);
583 break; 583 break;
584 584
@@ -703,7 +703,7 @@ SDIOH_API_RC sdioh_enable_hw_oob_intr(sdioh_info_t *sd, bool enable)
703#endif /* defined(OOB_INTR_ONLY) && defined(HW_OOB) */ 703#endif /* defined(OOB_INTR_ONLY) && defined(HW_OOB) */
704 704
705extern SDIOH_API_RC 705extern SDIOH_API_RC
706sdioh_cfg_read(sdioh_info_t *sd, uint fnc_num, uint32 addr, u8 *data) 706sdioh_cfg_read(sdioh_info_t *sd, uint fnc_num, u32 addr, u8 *data)
707{ 707{
708 SDIOH_API_RC status; 708 SDIOH_API_RC status;
709 /* No lock needed since sdioh_request_byte does locking */ 709 /* No lock needed since sdioh_request_byte does locking */
@@ -712,7 +712,7 @@ sdioh_cfg_read(sdioh_info_t *sd, uint fnc_num, uint32 addr, u8 *data)
712} 712}
713 713
714extern SDIOH_API_RC 714extern SDIOH_API_RC
715sdioh_cfg_write(sdioh_info_t *sd, uint fnc_num, uint32 addr, u8 *data) 715sdioh_cfg_write(sdioh_info_t *sd, uint fnc_num, u32 addr, u8 *data)
716{ 716{
717 /* No lock needed since sdioh_request_byte does locking */ 717 /* No lock needed since sdioh_request_byte does locking */
718 SDIOH_API_RC status; 718 SDIOH_API_RC status;
@@ -720,11 +720,11 @@ sdioh_cfg_write(sdioh_info_t *sd, uint fnc_num, uint32 addr, u8 *data)
720 return status; 720 return status;
721} 721}
722 722
723static int sdioh_sdmmc_get_cisaddr(sdioh_info_t *sd, uint32 regaddr) 723static int sdioh_sdmmc_get_cisaddr(sdioh_info_t *sd, u32 regaddr)
724{ 724{
725 /* read 24 bits and return valid 17 bit addr */ 725 /* read 24 bits and return valid 17 bit addr */
726 int i; 726 int i;
727 uint32 scratch, regdata; 727 u32 scratch, regdata;
728 u8 *ptr = (u8 *)&scratch; 728 u8 *ptr = (u8 *)&scratch;
729 for (i = 0; i < 3; i++) { 729 for (i = 0; i < 3; i++) {
730 if ((sdioh_sdmmc_card_regread(sd, 0, regaddr, 1, &regdata)) != 730 if ((sdioh_sdmmc_card_regread(sd, 0, regaddr, 1, &regdata)) !=
@@ -742,11 +742,11 @@ static int sdioh_sdmmc_get_cisaddr(sdioh_info_t *sd, uint32 regaddr)
742} 742}
743 743
744extern SDIOH_API_RC 744extern SDIOH_API_RC
745sdioh_cis_read(sdioh_info_t *sd, uint func, u8 *cisd, uint32 length) 745sdioh_cis_read(sdioh_info_t *sd, uint func, u8 *cisd, u32 length)
746{ 746{
747 uint32 count; 747 u32 count;
748 int offset; 748 int offset;
749 uint32 foo; 749 u32 foo;
750 u8 *cis = cisd; 750 u8 *cis = cisd;
751 751
752 sd_trace(("%s: Func = %d\n", __func__, func)); 752 sd_trace(("%s: Func = %d\n", __func__, func));
@@ -876,7 +876,7 @@ sdioh_request_byte(sdioh_info_t *sd, uint rw, uint func, uint regaddr,
876 876
877extern SDIOH_API_RC 877extern SDIOH_API_RC
878sdioh_request_word(sdioh_info_t *sd, uint cmd_type, uint rw, uint func, 878sdioh_request_word(sdioh_info_t *sd, uint cmd_type, uint rw, uint func,
879 uint addr, uint32 *word, uint nbytes) 879 uint addr, u32 *word, uint nbytes)
880{ 880{
881 int err_ret = SDIOH_API_RC_FAIL; 881 int err_ret = SDIOH_API_RC_FAIL;
882 882
@@ -932,7 +932,7 @@ sdioh_request_packet(sdioh_info_t *sd, uint fix_inc, uint write, uint func,
932 uint addr, void *pkt) 932 uint addr, void *pkt)
933{ 933{
934 bool fifo = (fix_inc == SDIOH_DATA_FIX); 934 bool fifo = (fix_inc == SDIOH_DATA_FIX);
935 uint32 SGCount = 0; 935 u32 SGCount = 0;
936 int err_ret = 0; 936 int err_ret = 0;
937 937
938 void *pnext; 938 void *pnext;
@@ -963,7 +963,7 @@ sdioh_request_packet(sdioh_info_t *sd, uint fix_inc, uint write, uint func,
963 * is supposed to give 963 * is supposed to give
964 * us something we can work with. 964 * us something we can work with.
965 */ 965 */
966 ASSERT(((uint32) (PKTDATA(pkt)) & DMA_ALIGN_MASK) == 0); 966 ASSERT(((u32) (PKTDATA(pkt)) & DMA_ALIGN_MASK) == 0);
967 967
968 if ((write) && (!fifo)) { 968 if ((write) && (!fifo)) {
969 err_ret = sdio_memcpy_toio(gInstance->func[func], addr, 969 err_ret = sdio_memcpy_toio(gInstance->func[func], addr,
@@ -1067,7 +1067,7 @@ sdioh_request_buffer(sdioh_info_t *sd, uint pio_dma, uint fix_inc, uint write,
1067#else 1067#else
1068 PKTFREE(sd->osh, mypkt, write ? TRUE : FALSE); 1068 PKTFREE(sd->osh, mypkt, write ? TRUE : FALSE);
1069#endif /* DHD_USE_STATIC_BUF */ 1069#endif /* DHD_USE_STATIC_BUF */
1070 } else if (((uint32) (PKTDATA(pkt)) & DMA_ALIGN_MASK) != 0) { 1070 } else if (((u32) (PKTDATA(pkt)) & DMA_ALIGN_MASK) != 0) {
1071 /* Case 2: We have a packet, but it is unaligned. */ 1071 /* Case 2: We have a packet, but it is unaligned. */
1072 1072
1073 /* In this case, we cannot have a chain. */ 1073 /* In this case, we cannot have a chain. */
@@ -1156,8 +1156,8 @@ void sdioh_sdmmc_devintr_on(sdioh_info_t *sd)
1156 1156
1157/* Read client card reg */ 1157/* Read client card reg */
1158int 1158int
1159sdioh_sdmmc_card_regread(sdioh_info_t *sd, int func, uint32 regaddr, 1159sdioh_sdmmc_card_regread(sdioh_info_t *sd, int func, u32 regaddr,
1160 int regsize, uint32 *data) 1160 int regsize, u32 *data)
1161{ 1161{
1162 1162
1163 if ((func == 0) || (regsize == 1)) { 1163 if ((func == 0) || (regsize == 1)) {
@@ -1222,8 +1222,8 @@ static void IRQHandlerF2(struct sdio_func *func)
1222#ifdef NOTUSED 1222#ifdef NOTUSED
1223/* Write client card reg */ 1223/* Write client card reg */
1224static int 1224static int
1225sdioh_sdmmc_card_regwrite(sdioh_info_t *sd, int func, uint32 regaddr, 1225sdioh_sdmmc_card_regwrite(sdioh_info_t *sd, int func, u32 regaddr,
1226 int regsize, uint32 data) 1226 int regsize, u32 data)
1227{ 1227{
1228 1228
1229 if ((func == 0) || (regsize == 1)) { 1229 if ((func == 0) || (regsize == 1)) {
diff --git a/drivers/staging/brcm80211/brcmfmac/bcmutils.c b/drivers/staging/brcm80211/brcmfmac/bcmutils.c
index 3eff4fe1739..4db3acc763b 100644
--- a/drivers/staging/brcm80211/brcmfmac/bcmutils.c
+++ b/drivers/staging/brcm80211/brcmfmac/bcmutils.c
@@ -1170,7 +1170,7 @@ u16 hndcrc16(u8 *pdata, /* pointer to array of data to process */
1170 return crc; 1170 return crc;
1171} 1171}
1172 1172
1173static const uint32 crc32_table[256] = { 1173static const u32 crc32_table[256] = {
1174 0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA, 1174 0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA,
1175 0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3, 1175 0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3,
1176 0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988, 1176 0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988,
@@ -1237,9 +1237,9 @@ static const uint32 crc32_table[256] = {
1237 0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D 1237 0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D
1238}; 1238};
1239 1239
1240uint32 hndcrc32(u8 *pdata, /* pointer to array of data to process */ 1240u32 hndcrc32(u8 *pdata, /* pointer to array of data to process */
1241 uint nbytes, /* number of input data bytes to process */ 1241 uint nbytes, /* number of input data bytes to process */
1242 uint32 crc /* either CRC32_INIT_VALUE or previous 1242 u32 crc /* either CRC32_INIT_VALUE or previous
1243 return value */ 1243 return value */
1244) 1244)
1245{ 1245{
@@ -1288,8 +1288,8 @@ void testcrc32(void)
1288 uint j, k, l; 1288 uint j, k, l;
1289 u8 *buf; 1289 u8 *buf;
1290 uint len[CNBUFS]; 1290 uint len[CNBUFS];
1291 uint32 crcr; 1291 u32 crcr;
1292 uint32 crc32tv[CNBUFS] = { 1292 u32 crc32tv[CNBUFS] = {
1293 0xd2cb1faa, 0xd385c8fa, 0xf5b4f3f3, 0x55789e20, 0x00343110}; 1293 0xd2cb1faa, 0xd385c8fa, 0xf5b4f3f3, 0x55789e20, 0x00343110};
1294 1294
1295 ASSERT((buf = MALLOC(CBUFSIZ * CNBUFS)) != NULL); 1295 ASSERT((buf = MALLOC(CBUFSIZ * CNBUFS)) != NULL);
@@ -1408,13 +1408,13 @@ bcm_tlv_t *bcm_parse_ordered_tlvs(void *buf, int buflen, uint key)
1408#if defined(WLMSG_PRHDRS) || defined(WLMSG_PRPKT) || defined(WLMSG_ASSOC) || \ 1408#if defined(WLMSG_PRHDRS) || defined(WLMSG_PRPKT) || defined(WLMSG_ASSOC) || \
1409 defined(DHD_DEBUG) 1409 defined(DHD_DEBUG)
1410int 1410int
1411bcm_format_flags(const bcm_bit_desc_t *bd, uint32 flags, char *buf, int len) 1411bcm_format_flags(const bcm_bit_desc_t *bd, u32 flags, char *buf, int len)
1412{ 1412{
1413 int i; 1413 int i;
1414 char *p = buf; 1414 char *p = buf;
1415 char hexstr[16]; 1415 char hexstr[16];
1416 int slen = 0; 1416 int slen = 0;
1417 uint32 bit; 1417 u32 bit;
1418 const char *name; 1418 const char *name;
1419 1419
1420 if (len < 2 || !buf) 1420 if (len < 2 || !buf)
@@ -1500,7 +1500,7 @@ void prhex(const char *msg, unsigned char *buf, uint nbytes)
1500#endif /* defined(WLMSG_PRHDRS) || defined(WLMSG_PRPKT) */ 1500#endif /* defined(WLMSG_PRHDRS) || defined(WLMSG_PRPKT) */
1501 1501
1502/* Produce a human-readable string for boardrev */ 1502/* Produce a human-readable string for boardrev */
1503char *bcm_brev_str(uint32 brev, char *buf) 1503char *bcm_brev_str(u32 brev, char *buf)
1504{ 1504{
1505 if (brev < 0x100) 1505 if (brev < 0x100)
1506 snprintf(buf, 8, "%d.%d", (brev & 0xf0) >> 4, brev & 0xf); 1506 snprintf(buf, 8, "%d.%d", (brev & 0xf0) >> 4, brev & 0xf);
@@ -1540,7 +1540,7 @@ void printbig(char *buf)
1540/* routine to dump fields in a fileddesc structure */ 1540/* routine to dump fields in a fileddesc structure */
1541uint 1541uint
1542bcmdumpfields(bcmutl_rdreg_rtn read_rtn, void *arg0, uint arg1, 1542bcmdumpfields(bcmutl_rdreg_rtn read_rtn, void *arg0, uint arg1,
1543 struct fielddesc *fielddesc_array, char *buf, uint32 bufsize) 1543 struct fielddesc *fielddesc_array, char *buf, u32 bufsize)
1544{ 1544{
1545 uint filled_len; 1545 uint filled_len;
1546 int len; 1546 int len;
@@ -1555,7 +1555,7 @@ bcmdumpfields(bcmutl_rdreg_rtn read_rtn, void *arg0, uint arg1,
1555 len = snprintf(buf, bufsize, cur_ptr->nameandfmt, 1555 len = snprintf(buf, bufsize, cur_ptr->nameandfmt,
1556 read_rtn(arg0, arg1, cur_ptr->offset)); 1556 read_rtn(arg0, arg1, cur_ptr->offset));
1557 /* check for snprintf overflow or error */ 1557 /* check for snprintf overflow or error */
1558 if (len < 0 || (uint32) len >= bufsize) 1558 if (len < 0 || (u32) len >= bufsize)
1559 len = bufsize - 1; 1559 len = bufsize - 1;
1560 buf += len; 1560 buf += len;
1561 bufsize -= len; 1561 bufsize -= len;
diff --git a/drivers/staging/brcm80211/brcmfmac/dhd.h b/drivers/staging/brcm80211/brcmfmac/dhd.h
index bcbb2f12b33..332e99e500a 100644
--- a/drivers/staging/brcm80211/brcmfmac/dhd.h
+++ b/drivers/staging/brcm80211/brcmfmac/dhd.h
@@ -359,10 +359,10 @@ extern void dhd_os_sdtxunlock(dhd_pub_t *pub);
359int setScheduler(struct task_struct *p, int policy, struct sched_param *param); 359int setScheduler(struct task_struct *p, int policy, struct sched_param *param);
360 360
361typedef struct { 361typedef struct {
362 uint32 limit; /* Expiration time (usec) */ 362 u32 limit; /* Expiration time (usec) */
363 uint32 increment; /* Current expiration increment (usec) */ 363 u32 increment; /* Current expiration increment (usec) */
364 uint32 elapsed; /* Current elapsed time (usec) */ 364 u32 elapsed; /* Current elapsed time (usec) */
365 uint32 tick; /* O/S tick time (usec) */ 365 u32 tick; /* O/S tick time (usec) */
366} dhd_timeout_t; 366} dhd_timeout_t;
367 367
368extern void dhd_timeout_start(dhd_timeout_t *tmo, uint usec); 368extern void dhd_timeout_start(dhd_timeout_t *tmo, uint usec);
@@ -377,7 +377,7 @@ extern void wl_event_to_host_order(wl_event_msg_t *evt);
377extern void dhd_common_init(void); 377extern void dhd_common_init(void);
378 378
379extern int dhd_add_if(struct dhd_info *dhd, int ifidx, void *handle, 379extern int dhd_add_if(struct dhd_info *dhd, int ifidx, void *handle,
380 char *name, u8 *mac_addr, uint32 flags, u8 bssidx); 380 char *name, u8 *mac_addr, u32 flags, u8 bssidx);
381extern void dhd_del_if(struct dhd_info *dhd, int ifidx); 381extern void dhd_del_if(struct dhd_info *dhd, int ifidx);
382 382
383extern void dhd_vif_add(struct dhd_info *dhd, int ifidx, char *name); 383extern void dhd_vif_add(struct dhd_info *dhd, int ifidx, char *name);
diff --git a/drivers/staging/brcm80211/brcmfmac/dhd_cdc.c b/drivers/staging/brcm80211/brcmfmac/dhd_cdc.c
index 492138f4eb6..71047cadfb1 100644
--- a/drivers/staging/brcm80211/brcmfmac/dhd_cdc.c
+++ b/drivers/staging/brcm80211/brcmfmac/dhd_cdc.c
@@ -54,7 +54,7 @@ extern int dhd_preinit_ioctls(dhd_pub_t *dhd);
54typedef struct dhd_prot { 54typedef struct dhd_prot {
55 u16 reqid; 55 u16 reqid;
56 u8 pending; 56 u8 pending;
57 uint32 lastcmd; 57 u32 lastcmd;
58 u8 bus_header[BUS_HEADER_LEN]; 58 u8 bus_header[BUS_HEADER_LEN];
59 cdc_ioctl_t msg; 59 cdc_ioctl_t msg;
60 unsigned char buf[WLC_IOCTL_MAXLEN + ROUND_UP_MARGIN]; 60 unsigned char buf[WLC_IOCTL_MAXLEN + ROUND_UP_MARGIN];
@@ -78,7 +78,7 @@ static int dhdcdc_msg(dhd_pub_t *dhd)
78 return dhd_bus_txctl(dhd->bus, (unsigned char *)&prot->msg, len); 78 return dhd_bus_txctl(dhd->bus, (unsigned char *)&prot->msg, len);
79} 79}
80 80
81static int dhdcdc_cmplt(dhd_pub_t *dhd, uint32 id, uint32 len) 81static int dhdcdc_cmplt(dhd_pub_t *dhd, u32 id, u32 len)
82{ 82{
83 int ret; 83 int ret;
84 dhd_prot_t *prot = dhd->prot; 84 dhd_prot_t *prot = dhd->prot;
@@ -103,7 +103,7 @@ dhdcdc_query_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd, void *buf, uint len)
103 cdc_ioctl_t *msg = &prot->msg; 103 cdc_ioctl_t *msg = &prot->msg;
104 void *info; 104 void *info;
105 int ret = 0, retries = 0; 105 int ret = 0, retries = 0;
106 uint32 id, flags = 0; 106 u32 id, flags = 0;
107 107
108 DHD_TRACE(("%s: Enter\n", __func__)); 108 DHD_TRACE(("%s: Enter\n", __func__));
109 DHD_CTL(("%s: cmd %d len %d\n", __func__, cmd, len)); 109 DHD_CTL(("%s: cmd %d len %d\n", __func__, cmd, len));
@@ -182,7 +182,7 @@ int dhdcdc_set_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd, void *buf, uint len)
182 dhd_prot_t *prot = dhd->prot; 182 dhd_prot_t *prot = dhd->prot;
183 cdc_ioctl_t *msg = &prot->msg; 183 cdc_ioctl_t *msg = &prot->msg;
184 int ret = 0; 184 int ret = 0;
185 uint32 flags, id; 185 u32 flags, id;
186 186
187 DHD_TRACE(("%s: Enter\n", __func__)); 187 DHD_TRACE(("%s: Enter\n", __func__));
188 DHD_CTL(("%s: cmd %d len %d\n", __func__, cmd, len)); 188 DHD_CTL(("%s: cmd %d len %d\n", __func__, cmd, len));
diff --git a/drivers/staging/brcm80211/brcmfmac/dhd_common.c b/drivers/staging/brcm80211/brcmfmac/dhd_common.c
index 90879975dee..10854314b13 100644
--- a/drivers/staging/brcm80211/brcmfmac/dhd_common.c
+++ b/drivers/staging/brcm80211/brcmfmac/dhd_common.c
@@ -30,9 +30,9 @@ char fw_path[MOD_PARAM_PATHLEN];
30char nv_path[MOD_PARAM_PATHLEN]; 30char nv_path[MOD_PARAM_PATHLEN];
31 31
32/* Last connection success/failure status */ 32/* Last connection success/failure status */
33uint32 dhd_conn_event; 33u32 dhd_conn_event;
34uint32 dhd_conn_status; 34u32 dhd_conn_status;
35uint32 dhd_conn_reason; 35u32 dhd_conn_reason;
36 36
37#define htod32(i) i 37#define htod32(i) i
38#define htod16(i) i 38#define htod16(i) i
@@ -200,7 +200,7 @@ static int dhd_dump(dhd_pub_t *dhdp, char *buf, int buflen)
200} 200}
201 201
202static int 202static int
203dhd_doiovar(dhd_pub_t *dhd_pub, const bcm_iovar_t *vi, uint32 actionid, 203dhd_doiovar(dhd_pub_t *dhd_pub, const bcm_iovar_t *vi, u32 actionid,
204 const char *name, void *params, int plen, void *arg, int len, 204 const char *name, void *params, int plen, void *arg, int len,
205 int val_size) 205 int val_size)
206{ 206{
@@ -313,7 +313,7 @@ exit:
313} 313}
314 314
315/* Store the status of a connection attempt for later retrieval by an iovar */ 315/* Store the status of a connection attempt for later retrieval by an iovar */
316void dhd_store_conn_status(uint32 event, uint32 status, uint32 reason) 316void dhd_store_conn_status(u32 event, u32 status, u32 reason)
317{ 317{
318 /* Do not overwrite a WLC_E_PRUNE with a WLC_E_SET_SSID 318 /* Do not overwrite a WLC_E_PRUNE with a WLC_E_SET_SSID
319 * because an encryption/rsn mismatch results in both events, and 319 * because an encryption/rsn mismatch results in both events, and
@@ -387,7 +387,7 @@ dhd_iovar_op(dhd_pub_t *dhd_pub, const char *name,
387 int bcmerror = 0; 387 int bcmerror = 0;
388 int val_size; 388 int val_size;
389 const bcm_iovar_t *vi = NULL; 389 const bcm_iovar_t *vi = NULL;
390 uint32 actionid; 390 u32 actionid;
391 391
392 DHD_TRACE(("%s: Enter\n", __func__)); 392 DHD_TRACE(("%s: Enter\n", __func__));
393 393
@@ -750,9 +750,9 @@ static void wl_show_host_event(wl_event_msg_t *event, void *event_data)
750 750
751 case WLC_E_TRACE: 751 case WLC_E_TRACE:
752 { 752 {
753 static uint32 seqnum_prev; 753 static u32 seqnum_prev;
754 msgtrace_hdr_t hdr; 754 msgtrace_hdr_t hdr;
755 uint32 nblost; 755 u32 nblost;
756 char *s, *p; 756 char *s, *p;
757 757
758 buf = (unsigned char *) event_data; 758 buf = (unsigned char *) event_data;
@@ -835,7 +835,7 @@ wl_host_event(struct dhd_info *dhd, int *ifidx, void *pktdata,
835 /* check whether packet is a BRCM event pkt */ 835 /* check whether packet is a BRCM event pkt */
836 bcm_event_t *pvt_data = (bcm_event_t *) pktdata; 836 bcm_event_t *pvt_data = (bcm_event_t *) pktdata;
837 char *event_data; 837 char *event_data;
838 uint32 type, status; 838 u32 type, status;
839 u16 flags; 839 u16 flags;
840 int evlen; 840 int evlen;
841 841
@@ -912,7 +912,7 @@ wl_host_event(struct dhd_info *dhd, int *ifidx, void *pktdata,
912 912
913 /* put it back to WLC_E_NDIS_LINK */ 913 /* put it back to WLC_E_NDIS_LINK */
914 if (type == WLC_E_NDIS_LINK) { 914 if (type == WLC_E_NDIS_LINK) {
915 uint32 temp; 915 u32 temp;
916 916
917 temp = ntoh32_ua((void *)&event->event_type); 917 temp = ntoh32_ua((void *)&event->event_type);
918 DHD_TRACE(("Converted to WLC_E_LINK type %d\n", temp)); 918 DHD_TRACE(("Converted to WLC_E_LINK type %d\n", temp));
@@ -1072,8 +1072,8 @@ void dhd_pktfilter_offload_set(dhd_pub_t *dhd, char *arg)
1072 int buf_len; 1072 int buf_len;
1073 int str_len; 1073 int str_len;
1074 int rc; 1074 int rc;
1075 uint32 mask_size; 1075 u32 mask_size;
1076 uint32 pattern_size; 1076 u32 pattern_size;
1077 char *argv[8], *buf = 0; 1077 char *argv[8], *buf = 0;
1078 int i = 0; 1078 int i = 0;
1079 char *arg_save = 0, *arg_org = 0; 1079 char *arg_save = 0, *arg_org = 0;
@@ -1242,8 +1242,8 @@ int dhd_preinit_ioctls(dhd_pub_t *dhd)
1242 uint up = 0; 1242 uint up = 0;
1243 char buf[128], *ptr; 1243 char buf[128], *ptr;
1244 uint power_mode = PM_FAST; 1244 uint power_mode = PM_FAST;
1245 uint32 dongle_align = DHD_SDALIGN; 1245 u32 dongle_align = DHD_SDALIGN;
1246 uint32 glom = 0; 1246 u32 glom = 0;
1247 uint bcn_timeout = 3; 1247 uint bcn_timeout = 3;
1248 int scan_assoc_time = 40; 1248 int scan_assoc_time = 40;
1249 int scan_unassoc_time = 40; 1249 int scan_unassoc_time = 40;
diff --git a/drivers/staging/brcm80211/brcmfmac/dhd_linux.c b/drivers/staging/brcm80211/brcmfmac/dhd_linux.c
index 72eed5bac2f..79138d04f33 100644
--- a/drivers/staging/brcm80211/brcmfmac/dhd_linux.c
+++ b/drivers/staging/brcm80211/brcmfmac/dhd_linux.c
@@ -425,8 +425,8 @@ extern int dhd_wait_pend8021x(struct net_device *dev);
425#ifndef BDC 425#ifndef BDC
426#error TOE requires BDC 426#error TOE requires BDC
427#endif /* !BDC */ 427#endif /* !BDC */
428static int dhd_toe_get(dhd_info_t *dhd, int idx, uint32 *toe_ol); 428static int dhd_toe_get(dhd_info_t *dhd, int idx, u32 *toe_ol);
429static int dhd_toe_set(dhd_info_t *dhd, int idx, uint32 toe_ol); 429static int dhd_toe_set(dhd_info_t *dhd, int idx, u32 toe_ol);
430#endif /* TOE */ 430#endif /* TOE */
431 431
432static int dhd_wl_host_event(dhd_info_t *dhd, int *ifidx, void *pktdata, 432static int dhd_wl_host_event(dhd_info_t *dhd, int *ifidx, void *pktdata,
@@ -712,7 +712,7 @@ static void _dhd_set_multicast_list(dhd_info_t *dhd, int ifidx)
712{ 712{
713 struct net_device *dev; 713 struct net_device *dev;
714 struct netdev_hw_addr *ha; 714 struct netdev_hw_addr *ha;
715 uint32 allmulti, cnt; 715 u32 allmulti, cnt;
716 716
717 wl_ioctl_t ioc; 717 wl_ioctl_t ioc;
718 char *buf, *bufp; 718 char *buf, *bufp;
@@ -1434,7 +1434,7 @@ void dhd_sched_dpc(dhd_pub_t *dhdp)
1434#ifdef TOE 1434#ifdef TOE
1435/* Retrieve current toe component enables, which are kept 1435/* Retrieve current toe component enables, which are kept
1436 as a bitmap in toe_ol iovar */ 1436 as a bitmap in toe_ol iovar */
1437static int dhd_toe_get(dhd_info_t *dhd, int ifidx, uint32 *toe_ol) 1437static int dhd_toe_get(dhd_info_t *dhd, int ifidx, u32 *toe_ol)
1438{ 1438{
1439 wl_ioctl_t ioc; 1439 wl_ioctl_t ioc;
1440 char buf[32]; 1440 char buf[32];
@@ -1462,13 +1462,13 @@ static int dhd_toe_get(dhd_info_t *dhd, int ifidx, uint32 *toe_ol)
1462 return ret; 1462 return ret;
1463 } 1463 }
1464 1464
1465 memcpy(toe_ol, buf, sizeof(uint32)); 1465 memcpy(toe_ol, buf, sizeof(u32));
1466 return 0; 1466 return 0;
1467} 1467}
1468 1468
1469/* Set current toe component enables in toe_ol iovar, 1469/* Set current toe component enables in toe_ol iovar,
1470 and set toe global enable iovar */ 1470 and set toe global enable iovar */
1471static int dhd_toe_set(dhd_info_t *dhd, int ifidx, uint32 toe_ol) 1471static int dhd_toe_set(dhd_info_t *dhd, int ifidx, u32 toe_ol)
1472{ 1472{
1473 wl_ioctl_t ioc; 1473 wl_ioctl_t ioc;
1474 char buf[32]; 1474 char buf[32];
@@ -1484,7 +1484,7 @@ static int dhd_toe_set(dhd_info_t *dhd, int ifidx, uint32 toe_ol)
1484 /* Set toe_ol as requested */ 1484 /* Set toe_ol as requested */
1485 1485
1486 strcpy(buf, "toe_ol"); 1486 strcpy(buf, "toe_ol");
1487 memcpy(&buf[sizeof("toe_ol")], &toe_ol, sizeof(uint32)); 1487 memcpy(&buf[sizeof("toe_ol")], &toe_ol, sizeof(u32));
1488 1488
1489 ret = dhd_prot_ioctl(&dhd->pub, ifidx, &ioc, ioc.buf, ioc.len); 1489 ret = dhd_prot_ioctl(&dhd->pub, ifidx, &ioc, ioc.buf, ioc.len);
1490 if (ret < 0) { 1490 if (ret < 0) {
@@ -1498,7 +1498,7 @@ static int dhd_toe_set(dhd_info_t *dhd, int ifidx, uint32 toe_ol)
1498 toe = (toe_ol != 0); 1498 toe = (toe_ol != 0);
1499 1499
1500 strcpy(buf, "toe"); 1500 strcpy(buf, "toe");
1501 memcpy(&buf[sizeof("toe")], &toe, sizeof(uint32)); 1501 memcpy(&buf[sizeof("toe")], &toe, sizeof(u32));
1502 1502
1503 ret = dhd_prot_ioctl(&dhd->pub, ifidx, &ioc, ioc.buf, ioc.len); 1503 ret = dhd_prot_ioctl(&dhd->pub, ifidx, &ioc, ioc.buf, ioc.len);
1504 if (ret < 0) { 1504 if (ret < 0) {
@@ -1530,17 +1530,17 @@ static int dhd_ethtool(dhd_info_t *dhd, void *uaddr)
1530{ 1530{
1531 struct ethtool_drvinfo info; 1531 struct ethtool_drvinfo info;
1532 char drvname[sizeof(info.driver)]; 1532 char drvname[sizeof(info.driver)];
1533 uint32 cmd; 1533 u32 cmd;
1534#ifdef TOE 1534#ifdef TOE
1535 struct ethtool_value edata; 1535 struct ethtool_value edata;
1536 uint32 toe_cmpnt, csum_dir; 1536 u32 toe_cmpnt, csum_dir;
1537 int ret; 1537 int ret;
1538#endif 1538#endif
1539 1539
1540 DHD_TRACE(("%s: Enter\n", __func__)); 1540 DHD_TRACE(("%s: Enter\n", __func__));
1541 1541
1542 /* all ethtool calls start with a cmd word */ 1542 /* all ethtool calls start with a cmd word */
1543 if (copy_from_user(&cmd, uaddr, sizeof(uint32))) 1543 if (copy_from_user(&cmd, uaddr, sizeof(u32)))
1544 return -EFAULT; 1544 return -EFAULT;
1545 1545
1546 switch (cmd) { 1546 switch (cmd) {
@@ -1794,7 +1794,7 @@ static int dhd_open(struct net_device *net)
1794{ 1794{
1795 dhd_info_t *dhd = *(dhd_info_t **) netdev_priv(net); 1795 dhd_info_t *dhd = *(dhd_info_t **) netdev_priv(net);
1796#ifdef TOE 1796#ifdef TOE
1797 uint32 toe_ol; 1797 u32 toe_ol;
1798#endif 1798#endif
1799 int ifidx = dhd_net2idx(dhd, net); 1799 int ifidx = dhd_net2idx(dhd, net);
1800 int32 ret = 0; 1800 int32 ret = 0;
@@ -1854,7 +1854,7 @@ void dhd_osl_detach(osl_t *osh)
1854 1854
1855int 1855int
1856dhd_add_if(dhd_info_t *dhd, int ifidx, void *handle, char *name, 1856dhd_add_if(dhd_info_t *dhd, int ifidx, void *handle, char *name,
1857 u8 *mac_addr, uint32 flags, u8 bssidx) 1857 u8 *mac_addr, u32 flags, u8 bssidx)
1858{ 1858{
1859 dhd_if_t *ifp; 1859 dhd_if_t *ifp;
1860 1860
diff --git a/drivers/staging/brcm80211/brcmfmac/dhd_sdio.c b/drivers/staging/brcm80211/brcmfmac/dhd_sdio.c
index fb5e4b6a75a..5fbb2a54964 100644
--- a/drivers/staging/brcm80211/brcmfmac/dhd_sdio.c
+++ b/drivers/staging/brcm80211/brcmfmac/dhd_sdio.c
@@ -167,18 +167,18 @@ typedef struct dhd_bus {
167 si_t *sih; /* Handle for SI calls */ 167 si_t *sih; /* Handle for SI calls */
168 char *vars; /* Variables (from CIS and/or other) */ 168 char *vars; /* Variables (from CIS and/or other) */
169 uint varsz; /* Size of variables buffer */ 169 uint varsz; /* Size of variables buffer */
170 uint32 sbaddr; /* Current SB window pointer (-1, invalid) */ 170 u32 sbaddr; /* Current SB window pointer (-1, invalid) */
171 171
172 sdpcmd_regs_t *regs; /* Registers for SDIO core */ 172 sdpcmd_regs_t *regs; /* Registers for SDIO core */
173 uint sdpcmrev; /* SDIO core revision */ 173 uint sdpcmrev; /* SDIO core revision */
174 uint armrev; /* CPU core revision */ 174 uint armrev; /* CPU core revision */
175 uint ramrev; /* SOCRAM core revision */ 175 uint ramrev; /* SOCRAM core revision */
176 uint32 ramsize; /* Size of RAM in SOCRAM (bytes) */ 176 u32 ramsize; /* Size of RAM in SOCRAM (bytes) */
177 uint32 orig_ramsize; /* Size of RAM in SOCRAM (bytes) */ 177 u32 orig_ramsize; /* Size of RAM in SOCRAM (bytes) */
178 178
179 uint32 bus; /* gSPI or SDIO bus */ 179 u32 bus; /* gSPI or SDIO bus */
180 uint32 hostintmask; /* Copy of Host Interrupt Mask */ 180 u32 hostintmask; /* Copy of Host Interrupt Mask */
181 uint32 intstatus; /* Intstatus bits (events) pending */ 181 u32 intstatus; /* Intstatus bits (events) pending */
182 bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */ 182 bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
183 bool fcstate; /* State of dongle flow-control */ 183 bool fcstate; /* State of dongle flow-control */
184 184
@@ -295,7 +295,7 @@ typedef struct dhd_bus {
295 uint f1regdata; /* Number of f1 register accesses */ 295 uint f1regdata; /* Number of f1 register accesses */
296 296
297 u8 *ctrl_frame_buf; 297 u8 *ctrl_frame_buf;
298 uint32 ctrl_frame_len; 298 u32 ctrl_frame_len;
299 bool ctrl_frame_stat; 299 bool ctrl_frame_stat;
300} dhd_bus_t; 300} dhd_bus_t;
301 301
@@ -442,10 +442,10 @@ static void dhdsdio_release_dongle(dhd_bus_t *bus, osl_t * osh);
442static uint process_nvram_vars(char *varbuf, uint len); 442static uint process_nvram_vars(char *varbuf, uint len);
443 443
444static void dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size); 444static void dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size);
445static int dhd_bcmsdh_recv_buf(dhd_bus_t *bus, uint32 addr, uint fn, 445static int dhd_bcmsdh_recv_buf(dhd_bus_t *bus, u32 addr, uint fn,
446 uint flags, u8 *buf, uint nbytes, void *pkt, 446 uint flags, u8 *buf, uint nbytes, void *pkt,
447 bcmsdh_cmplt_fn_t complete, void *handle); 447 bcmsdh_cmplt_fn_t complete, void *handle);
448static int dhd_bcmsdh_send_buf(dhd_bus_t *bus, uint32 addr, uint fn, 448static int dhd_bcmsdh_send_buf(dhd_bus_t *bus, u32 addr, uint fn,
449 uint flags, u8 *buf, uint nbytes, void *pkt, 449 uint flags, u8 *buf, uint nbytes, void *pkt,
450 bcmsdh_cmplt_fn_t complete, void *handle); 450 bcmsdh_cmplt_fn_t complete, void *handle);
451 451
@@ -470,7 +470,7 @@ static void dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size)
470 bus->ramsize = dhd_dongle_memsize; 470 bus->ramsize = dhd_dongle_memsize;
471} 471}
472 472
473static int dhdsdio_set_siaddr_window(dhd_bus_t *bus, uint32 address) 473static int dhdsdio_set_siaddr_window(dhd_bus_t *bus, u32 address)
474{ 474{
475 int err = 0; 475 int err = 0;
476 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRLOW, 476 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRLOW,
@@ -519,7 +519,7 @@ static int dhdsdio_htclk(dhd_bus_t *bus, bool on, bool pendok)
519 519
520 if (pendok && ((bus->sih->buscoretype == PCMCIA_CORE_ID) 520 if (pendok && ((bus->sih->buscoretype == PCMCIA_CORE_ID)
521 && (bus->sih->buscorerev == 9))) { 521 && (bus->sih->buscorerev == 9))) {
522 uint32 dummy, retries; 522 u32 dummy, retries;
523 R_SDREG(dummy, &bus->regs->clockctlstatus, retries); 523 R_SDREG(dummy, &bus->regs->clockctlstatus, retries);
524 } 524 }
525 525
@@ -905,7 +905,7 @@ static int dhdsdio_txpkt(dhd_bus_t *bus, void *pkt, uint chan, bool free_pkt)
905 osl_t *osh; 905 osl_t *osh;
906 u8 *frame; 906 u8 *frame;
907 u16 len, pad = 0; 907 u16 len, pad = 0;
908 uint32 swheader; 908 u32 swheader;
909 uint retries = 0; 909 uint retries = 0;
910 bcmsdh_info_t *sdh; 910 bcmsdh_info_t *sdh;
911 void *new; 911 void *new;
@@ -1162,7 +1162,7 @@ int dhd_bus_txdata(struct dhd_bus *bus, void *pkt)
1162static uint dhdsdio_sendfromq(dhd_bus_t *bus, uint maxframes) 1162static uint dhdsdio_sendfromq(dhd_bus_t *bus, uint maxframes)
1163{ 1163{
1164 void *pkt; 1164 void *pkt;
1165 uint32 intstatus = 0; 1165 u32 intstatus = 0;
1166 uint retries = 0; 1166 uint retries = 0;
1167 int ret = 0, prec_out; 1167 int ret = 0, prec_out;
1168 uint cnt = 0; 1168 uint cnt = 0;
@@ -1223,7 +1223,7 @@ int dhd_bus_txctl(struct dhd_bus *bus, unsigned char *msg, uint msglen)
1223{ 1223{
1224 u8 *frame; 1224 u8 *frame;
1225 u16 len; 1225 u16 len;
1226 uint32 swheader; 1226 u32 swheader;
1227 uint retries = 0; 1227 uint retries = 0;
1228 bcmsdh_info_t *sdh = bus->sdh; 1228 bcmsdh_info_t *sdh = bus->sdh;
1229 u8 doff = 0; 1229 u8 doff = 0;
@@ -1692,11 +1692,11 @@ static int dhdsdio_pktgen_set(dhd_bus_t *bus, u8 *arg)
1692#endif /* SDTEST */ 1692#endif /* SDTEST */
1693 1693
1694static int 1694static int
1695dhdsdio_membytes(dhd_bus_t *bus, bool write, uint32 address, u8 *data, 1695dhdsdio_membytes(dhd_bus_t *bus, bool write, u32 address, u8 *data,
1696 uint size) 1696 uint size)
1697{ 1697{
1698 int bcmerror = 0; 1698 int bcmerror = 0;
1699 uint32 sdaddr; 1699 u32 sdaddr;
1700 uint dsize; 1700 uint dsize;
1701 1701
1702 /* Determine initial transfer parameters */ 1702 /* Determine initial transfer parameters */
@@ -1754,7 +1754,7 @@ xfer_done:
1754#ifdef DHD_DEBUG 1754#ifdef DHD_DEBUG
1755static int dhdsdio_readshared(dhd_bus_t *bus, sdpcm_shared_t *sh) 1755static int dhdsdio_readshared(dhd_bus_t *bus, sdpcm_shared_t *sh)
1756{ 1756{
1757 uint32 addr; 1757 u32 addr;
1758 int rv; 1758 int rv;
1759 1759
1760 /* Read last word in memory to determine address of 1760 /* Read last word in memory to determine address of
@@ -1987,7 +1987,7 @@ static int dhdsdio_readconsole(dhd_bus_t *bus)
1987{ 1987{
1988 dhd_console_t *c = &bus->console; 1988 dhd_console_t *c = &bus->console;
1989 u8 line[CONSOLE_LINE_MAX], ch; 1989 u8 line[CONSOLE_LINE_MAX], ch;
1990 uint32 n, idx, addr; 1990 u32 n, idx, addr;
1991 int rv; 1991 int rv;
1992 1992
1993 /* Don't do anything until FWREADY updates console address */ 1993 /* Don't do anything until FWREADY updates console address */
@@ -2095,7 +2095,7 @@ err:
2095} 2095}
2096 2096
2097static int 2097static int
2098dhdsdio_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, uint32 actionid, 2098dhdsdio_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, u32 actionid,
2099 const char *name, void *params, int plen, void *arg, int len, 2099 const char *name, void *params, int plen, void *arg, int len,
2100 int val_size) 2100 int val_size)
2101{ 2101{
@@ -2208,7 +2208,7 @@ dhdsdio_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, uint32 actionid,
2208 case IOV_SVAL(IOV_MEMBYTES): 2208 case IOV_SVAL(IOV_MEMBYTES):
2209 case IOV_GVAL(IOV_MEMBYTES): 2209 case IOV_GVAL(IOV_MEMBYTES):
2210 { 2210 {
2211 uint32 address; 2211 u32 address;
2212 uint size, dsize; 2212 uint size, dsize;
2213 u8 *data; 2213 u8 *data;
2214 2214
@@ -2216,7 +2216,7 @@ dhdsdio_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, uint32 actionid,
2216 2216
2217 ASSERT(plen >= 2 * sizeof(int)); 2217 ASSERT(plen >= 2 * sizeof(int));
2218 2218
2219 address = (uint32) int_val; 2219 address = (u32) int_val;
2220 bcopy((char *)params + sizeof(int_val), &int_val, 2220 bcopy((char *)params + sizeof(int_val), &int_val,
2221 sizeof(int_val)); 2221 sizeof(int_val));
2222 size = (uint) int_val; 2222 size = (uint) int_val;
@@ -2332,7 +2332,7 @@ dhdsdio_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, uint32 actionid,
2332 case IOV_GVAL(IOV_SDREG): 2332 case IOV_GVAL(IOV_SDREG):
2333 { 2333 {
2334 sdreg_t *sd_ptr; 2334 sdreg_t *sd_ptr;
2335 uint32 addr, size; 2335 u32 addr, size;
2336 2336
2337 sd_ptr = (sdreg_t *) params; 2337 sd_ptr = (sdreg_t *) params;
2338 2338
@@ -2348,7 +2348,7 @@ dhdsdio_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, uint32 actionid,
2348 case IOV_SVAL(IOV_SDREG): 2348 case IOV_SVAL(IOV_SDREG):
2349 { 2349 {
2350 sdreg_t *sd_ptr; 2350 sdreg_t *sd_ptr;
2351 uint32 addr, size; 2351 u32 addr, size;
2352 2352
2353 sd_ptr = (sdreg_t *) params; 2353 sd_ptr = (sdreg_t *) params;
2354 2354
@@ -2365,7 +2365,7 @@ dhdsdio_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, uint32 actionid,
2365 case IOV_GVAL(IOV_SBREG): 2365 case IOV_GVAL(IOV_SBREG):
2366 { 2366 {
2367 sdreg_t sdreg; 2367 sdreg_t sdreg;
2368 uint32 addr, size; 2368 u32 addr, size;
2369 2369
2370 bcopy(params, &sdreg, sizeof(sdreg)); 2370 bcopy(params, &sdreg, sizeof(sdreg));
2371 2371
@@ -2381,7 +2381,7 @@ dhdsdio_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, uint32 actionid,
2381 case IOV_SVAL(IOV_SBREG): 2381 case IOV_SVAL(IOV_SBREG):
2382 { 2382 {
2383 sdreg_t sdreg; 2383 sdreg_t sdreg;
2384 uint32 addr, size; 2384 u32 addr, size;
2385 2385
2386 bcopy(params, &sdreg, sizeof(sdreg)); 2386 bcopy(params, &sdreg, sizeof(sdreg));
2387 2387
@@ -2512,10 +2512,10 @@ exit:
2512static int dhdsdio_write_vars(dhd_bus_t *bus) 2512static int dhdsdio_write_vars(dhd_bus_t *bus)
2513{ 2513{
2514 int bcmerror = 0; 2514 int bcmerror = 0;
2515 uint32 varsize; 2515 u32 varsize;
2516 uint32 varaddr; 2516 u32 varaddr;
2517 u8 *vbuffer; 2517 u8 *vbuffer;
2518 uint32 varsizew; 2518 u32 varsizew;
2519#ifdef DHD_DEBUG 2519#ifdef DHD_DEBUG
2520 char *nvram_ularray; 2520 char *nvram_ularray;
2521#endif /* DHD_DEBUG */ 2521#endif /* DHD_DEBUG */
@@ -2639,7 +2639,7 @@ static int dhdsdio_download_state(dhd_bus_t *bus, bool enter)
2639 2639
2640 /* Clear the top bit of memory */ 2640 /* Clear the top bit of memory */
2641 if (bus->ramsize) { 2641 if (bus->ramsize) {
2642 uint32 zeros = 0; 2642 u32 zeros = 0;
2643 dhdsdio_membytes(bus, TRUE, bus->ramsize - 4, 2643 dhdsdio_membytes(bus, TRUE, bus->ramsize - 4,
2644 (u8 *)&zeros, 4); 2644 (u8 *)&zeros, 4);
2645 } 2645 }
@@ -2710,7 +2710,7 @@ dhd_bus_iovar_op(dhd_pub_t *dhdp, const char *name,
2710 const bcm_iovar_t *vi = NULL; 2710 const bcm_iovar_t *vi = NULL;
2711 int bcmerror = 0; 2711 int bcmerror = 0;
2712 int val_size; 2712 int val_size;
2713 uint32 actionid; 2713 u32 actionid;
2714 2714
2715 DHD_TRACE(("%s: Enter\n", __func__)); 2715 DHD_TRACE(("%s: Enter\n", __func__));
2716 2716
@@ -2823,7 +2823,7 @@ exit:
2823void dhd_bus_stop(struct dhd_bus *bus, bool enforce_mutex) 2823void dhd_bus_stop(struct dhd_bus *bus, bool enforce_mutex)
2824{ 2824{
2825 osl_t *osh = bus->dhd->osh; 2825 osl_t *osh = bus->dhd->osh;
2826 uint32 local_hostintmask; 2826 u32 local_hostintmask;
2827 u8 saveclk; 2827 u8 saveclk;
2828 uint retries; 2828 uint retries;
2829 int err; 2829 int err;
@@ -4208,11 +4208,11 @@ deliver:
4208 return rxcount; 4208 return rxcount;
4209} 4209}
4210 4210
4211static uint32 dhdsdio_hostmail(dhd_bus_t *bus) 4211static u32 dhdsdio_hostmail(dhd_bus_t *bus)
4212{ 4212{
4213 sdpcmd_regs_t *regs = bus->regs; 4213 sdpcmd_regs_t *regs = bus->regs;
4214 uint32 intstatus = 0; 4214 u32 intstatus = 0;
4215 uint32 hmb_data; 4215 u32 hmb_data;
4216 u8 fcbits; 4216 u8 fcbits;
4217 uint retries = 0; 4217 uint retries = 0;
4218 4218
@@ -4286,7 +4286,7 @@ bool dhdsdio_dpc(dhd_bus_t *bus)
4286{ 4286{
4287 bcmsdh_info_t *sdh = bus->sdh; 4287 bcmsdh_info_t *sdh = bus->sdh;
4288 sdpcmd_regs_t *regs = bus->regs; 4288 sdpcmd_regs_t *regs = bus->regs;
4289 uint32 intstatus, newstatus = 0; 4289 u32 intstatus, newstatus = 0;
4290 uint retries = 0; 4290 uint retries = 0;
4291 uint rxlimit = dhd_rxbound; /* Rx frames to read before resched */ 4291 uint rxlimit = dhd_rxbound; /* Rx frames to read before resched */
4292 uint txlimit = dhd_txbound; /* Tx frames to send before resched */ 4292 uint txlimit = dhd_txbound; /* Tx frames to send before resched */
@@ -4460,7 +4460,7 @@ clkwait:
4460 ret = 4460 ret =
4461 dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2, 4461 dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
4462 F2SYNC, (u8 *) bus->ctrl_frame_buf, 4462 F2SYNC, (u8 *) bus->ctrl_frame_buf,
4463 (uint32) bus->ctrl_frame_len, NULL, 4463 (u32) bus->ctrl_frame_len, NULL,
4464 NULL, NULL); 4464 NULL, NULL);
4465 ASSERT(ret != BCME_PENDING); 4465 ASSERT(ret != BCME_PENDING);
4466 4466
@@ -4875,7 +4875,7 @@ extern bool dhd_bus_watchdog(dhd_pub_t *dhdp)
4875 4875
4876 /* Poll period: check device if appropriate. */ 4876 /* Poll period: check device if appropriate. */
4877 if (bus->poll && (++bus->polltick >= bus->pollrate)) { 4877 if (bus->poll && (++bus->polltick >= bus->pollrate)) {
4878 uint32 intstatus = 0; 4878 u32 intstatus = 0;
4879 4879
4880 /* Reset poll tick */ 4880 /* Reset poll tick */
4881 bus->polltick = 0; 4881 bus->polltick = 0;
@@ -4957,7 +4957,7 @@ extern bool dhd_bus_watchdog(dhd_pub_t *dhdp)
4957extern int dhd_bus_console_in(dhd_pub_t *dhdp, unsigned char *msg, uint msglen) 4957extern int dhd_bus_console_in(dhd_pub_t *dhdp, unsigned char *msg, uint msglen)
4958{ 4958{
4959 dhd_bus_t *bus = dhdp->bus; 4959 dhd_bus_t *bus = dhdp->bus;
4960 uint32 addr, val; 4960 u32 addr, val;
4961 int rv; 4961 int rv;
4962 void *pkt; 4962 void *pkt;
4963 4963
@@ -5765,9 +5765,9 @@ static int dhdsdio_download_code_file(struct dhd_bus *bus, char *fw_path)
5765 __func__, MEMBLOCK)); 5765 __func__, MEMBLOCK));
5766 goto err; 5766 goto err;
5767 } 5767 }
5768 if ((uint32) (uintptr) memblock % DHD_SDALIGN) 5768 if ((u32) (uintptr) memblock % DHD_SDALIGN)
5769 memptr += 5769 memptr +=
5770 (DHD_SDALIGN - ((uint32) (uintptr) memblock % DHD_SDALIGN)); 5770 (DHD_SDALIGN - ((u32) (uintptr) memblock % DHD_SDALIGN));
5771 5771
5772 /* Download image */ 5772 /* Download image */
5773 while ((len = 5773 while ((len =
@@ -6010,7 +6010,7 @@ err:
6010} 6010}
6011 6011
6012static int 6012static int
6013dhd_bcmsdh_recv_buf(dhd_bus_t *bus, uint32 addr, uint fn, uint flags, 6013dhd_bcmsdh_recv_buf(dhd_bus_t *bus, u32 addr, uint fn, uint flags,
6014 u8 *buf, uint nbytes, void *pkt, 6014 u8 *buf, uint nbytes, void *pkt,
6015 bcmsdh_cmplt_fn_t complete, void *handle) 6015 bcmsdh_cmplt_fn_t complete, void *handle)
6016{ 6016{
@@ -6024,7 +6024,7 @@ dhd_bcmsdh_recv_buf(dhd_bus_t *bus, uint32 addr, uint fn, uint flags,
6024} 6024}
6025 6025
6026static int 6026static int
6027dhd_bcmsdh_send_buf(dhd_bus_t *bus, uint32 addr, uint fn, uint flags, 6027dhd_bcmsdh_send_buf(dhd_bus_t *bus, u32 addr, uint fn, uint flags,
6028 u8 *buf, uint nbytes, void *pkt, 6028 u8 *buf, uint nbytes, void *pkt,
6029 bcmsdh_cmplt_fn_t complete, void *handle) 6029 bcmsdh_cmplt_fn_t complete, void *handle)
6030{ 6030{
@@ -6091,7 +6091,7 @@ int dhd_bus_devreset(dhd_pub_t *dhdp, u8 flag)
6091 6091
6092 /* Attempt to re-attach & download */ 6092 /* Attempt to re-attach & download */
6093 if (dhdsdio_probe_attach(bus, bus->dhd->osh, bus->sdh, 6093 if (dhdsdio_probe_attach(bus, bus->dhd->osh, bus->sdh,
6094 (uint32 *) SI_ENUM_BASE, 6094 (u32 *) SI_ENUM_BASE,
6095 bus->cl_devid)) { 6095 bus->cl_devid)) {
6096 /* Attempt to download binary to the dongle */ 6096 /* Attempt to download binary to the dongle */
6097 if (dhdsdio_probe_init 6097 if (dhdsdio_probe_init
diff --git a/drivers/staging/brcm80211/brcmfmac/wl_cfg80211.c b/drivers/staging/brcm80211/brcmfmac/wl_cfg80211.c
index 1c3b0d88f90..46f841f0b53 100644
--- a/drivers/staging/brcm80211/brcmfmac/wl_cfg80211.c
+++ b/drivers/staging/brcm80211/brcmfmac/wl_cfg80211.c
@@ -50,7 +50,7 @@
50static struct sdio_func *cfg80211_sdio_func; 50static struct sdio_func *cfg80211_sdio_func;
51static struct wl_dev *wl_cfg80211_dev; 51static struct wl_dev *wl_cfg80211_dev;
52 52
53uint32 wl_dbg_level = WL_DBG_ERR | WL_DBG_INFO; 53u32 wl_dbg_level = WL_DBG_ERR | WL_DBG_INFO;
54 54
55#define WL_4329_FW_FILE "brcm/bcm4329-fullmac-4-218-248-5.bin" 55#define WL_4329_FW_FILE "brcm/bcm4329-fullmac-4-218-248-5.bin"
56#define WL_4329_NVRAM_FILE "brcm/bcm4329-fullmac-4-218-248-5.txt" 56#define WL_4329_NVRAM_FILE "brcm/bcm4329-fullmac-4-218-248-5.txt"
@@ -60,14 +60,14 @@ uint32 wl_dbg_level = WL_DBG_ERR | WL_DBG_INFO;
60*/ 60*/
61static int32 wl_cfg80211_change_iface(struct wiphy *wiphy, 61static int32 wl_cfg80211_change_iface(struct wiphy *wiphy,
62 struct net_device *ndev, 62 struct net_device *ndev,
63 enum nl80211_iftype type, uint32 *flags, 63 enum nl80211_iftype type, u32 *flags,
64 struct vif_params *params); 64 struct vif_params *params);
65static int32 __wl_cfg80211_scan(struct wiphy *wiphy, struct net_device *ndev, 65static int32 __wl_cfg80211_scan(struct wiphy *wiphy, struct net_device *ndev,
66 struct cfg80211_scan_request *request, 66 struct cfg80211_scan_request *request,
67 struct cfg80211_ssid *this_ssid); 67 struct cfg80211_ssid *this_ssid);
68static int32 wl_cfg80211_scan(struct wiphy *wiphy, struct net_device *ndev, 68static int32 wl_cfg80211_scan(struct wiphy *wiphy, struct net_device *ndev,
69 struct cfg80211_scan_request *request); 69 struct cfg80211_scan_request *request);
70static int32 wl_cfg80211_set_wiphy_params(struct wiphy *wiphy, uint32 changed); 70static int32 wl_cfg80211_set_wiphy_params(struct wiphy *wiphy, u32 changed);
71static int32 wl_cfg80211_join_ibss(struct wiphy *wiphy, struct net_device *dev, 71static int32 wl_cfg80211_join_ibss(struct wiphy *wiphy, struct net_device *dev,
72 struct cfg80211_ibss_params *params); 72 struct cfg80211_ibss_params *params);
73static int32 wl_cfg80211_leave_ibss(struct wiphy *wiphy, 73static int32 wl_cfg80211_leave_ibss(struct wiphy *wiphy,
@@ -129,7 +129,7 @@ static void wl_unlock_eq(struct wl_priv *wl);
129static void wl_init_eq_lock(struct wl_priv *wl); 129static void wl_init_eq_lock(struct wl_priv *wl);
130static void wl_init_eloop_handler(struct wl_event_loop *el); 130static void wl_init_eloop_handler(struct wl_event_loop *el);
131static struct wl_event_q *wl_deq_event(struct wl_priv *wl); 131static struct wl_event_q *wl_deq_event(struct wl_priv *wl);
132static int32 wl_enq_event(struct wl_priv *wl, uint32 type, 132static int32 wl_enq_event(struct wl_priv *wl, u32 type,
133 const wl_event_msg_t *msg, void *data); 133 const wl_event_msg_t *msg, void *data);
134static void wl_put_event(struct wl_event_q *e); 134static void wl_put_event(struct wl_event_q *e);
135static void wl_wakeup_event(struct wl_priv *wl); 135static void wl_wakeup_event(struct wl_priv *wl);
@@ -165,15 +165,15 @@ static __used int32 wl_dev_bufvar_set(struct net_device *dev, s8 *name,
165static int32 wl_dev_intvar_set(struct net_device *dev, s8 *name, int32 val); 165static int32 wl_dev_intvar_set(struct net_device *dev, s8 *name, int32 val);
166static int32 wl_dev_intvar_get(struct net_device *dev, s8 *name, 166static int32 wl_dev_intvar_get(struct net_device *dev, s8 *name,
167 int32 *retval); 167 int32 *retval);
168static int32 wl_dev_ioctl(struct net_device *dev, uint32 cmd, void *arg, 168static int32 wl_dev_ioctl(struct net_device *dev, u32 cmd, void *arg,
169 uint32 len); 169 u32 len);
170 170
171/* 171/*
172** cfg80211 set_wiphy_params utilities 172** cfg80211 set_wiphy_params utilities
173*/ 173*/
174static int32 wl_set_frag(struct net_device *dev, uint32 frag_threshold); 174static int32 wl_set_frag(struct net_device *dev, u32 frag_threshold);
175static int32 wl_set_rts(struct net_device *dev, uint32 frag_threshold); 175static int32 wl_set_rts(struct net_device *dev, u32 frag_threshold);
176static int32 wl_set_retry(struct net_device *dev, uint32 retry, bool l); 176static int32 wl_set_retry(struct net_device *dev, u32 retry, bool l);
177 177
178/* 178/*
179** wl profile utilities 179** wl profile utilities
@@ -205,7 +205,7 @@ static void wl_rst_ie(struct wl_priv *wl);
205static int32 wl_add_ie(struct wl_priv *wl, u8 t, u8 l, u8 *v); 205static int32 wl_add_ie(struct wl_priv *wl, u8 t, u8 l, u8 *v);
206static int32 wl_mrg_ie(struct wl_priv *wl, u8 *ie_stream, u16 ie_size); 206static int32 wl_mrg_ie(struct wl_priv *wl, u8 *ie_stream, u16 ie_size);
207static int32 wl_cp_ie(struct wl_priv *wl, u8 *dst, u16 dst_size); 207static int32 wl_cp_ie(struct wl_priv *wl, u8 *dst, u16 dst_size);
208static uint32 wl_get_ielen(struct wl_priv *wl); 208static u32 wl_get_ielen(struct wl_priv *wl);
209 209
210static int32 wl_mode_to_nl80211_iftype(int32 mode); 210static int32 wl_mode_to_nl80211_iftype(int32 mode);
211 211
@@ -233,7 +233,7 @@ static void swap_key_to_BE(struct wl_wsec_key *key);
233static int32 wl_init_priv_mem(struct wl_priv *wl); 233static int32 wl_init_priv_mem(struct wl_priv *wl);
234static void wl_deinit_priv_mem(struct wl_priv *wl); 234static void wl_deinit_priv_mem(struct wl_priv *wl);
235 235
236static void wl_delay(uint32 ms); 236static void wl_delay(u32 ms);
237 237
238/* 238/*
239** store/restore cfg80211 instance data 239** store/restore cfg80211 instance data
@@ -267,19 +267,19 @@ static void wl_init_conf(struct wl_conf *conf);
267#ifndef EMBEDDED_PLATFORM 267#ifndef EMBEDDED_PLATFORM
268static int32 wl_dongle_mode(struct net_device *ndev, int32 iftype); 268static int32 wl_dongle_mode(struct net_device *ndev, int32 iftype);
269static int32 wl_dongle_country(struct net_device *ndev, u8 ccode); 269static int32 wl_dongle_country(struct net_device *ndev, u8 ccode);
270static int32 wl_dongle_up(struct net_device *ndev, uint32 up); 270static int32 wl_dongle_up(struct net_device *ndev, u32 up);
271static int32 wl_dongle_power(struct net_device *ndev, uint32 power_mode); 271static int32 wl_dongle_power(struct net_device *ndev, u32 power_mode);
272static int32 wl_dongle_glom(struct net_device *ndev, uint32 glom, 272static int32 wl_dongle_glom(struct net_device *ndev, u32 glom,
273 uint32 dongle_align); 273 u32 dongle_align);
274static int32 wl_dongle_roam(struct net_device *ndev, uint32 roamvar, 274static int32 wl_dongle_roam(struct net_device *ndev, u32 roamvar,
275 uint32 bcn_timeout); 275 u32 bcn_timeout);
276static int32 wl_dongle_eventmsg(struct net_device *ndev); 276static int32 wl_dongle_eventmsg(struct net_device *ndev);
277static int32 wl_dongle_scantime(struct net_device *ndev, int32 scan_assoc_time, 277static int32 wl_dongle_scantime(struct net_device *ndev, int32 scan_assoc_time,
278 int32 scan_unassoc_time); 278 int32 scan_unassoc_time);
279static int32 wl_dongle_offload(struct net_device *ndev, int32 arpoe, 279static int32 wl_dongle_offload(struct net_device *ndev, int32 arpoe,
280 int32 arp_ol); 280 int32 arp_ol);
281static int32 wl_pattern_atoh(s8 *src, s8 *dst); 281static int32 wl_pattern_atoh(s8 *src, s8 *dst);
282static int32 wl_dongle_filter(struct net_device *ndev, uint32 filter_mode); 282static int32 wl_dongle_filter(struct net_device *ndev, u32 filter_mode);
283static int32 wl_update_wiphybands(struct wl_priv *wl); 283static int32 wl_update_wiphybands(struct wl_priv *wl);
284#endif /* !EMBEDDED_PLATFORM */ 284#endif /* !EMBEDDED_PLATFORM */
285static int32 wl_config_dongle(struct wl_priv *wl, bool need_lock); 285static int32 wl_config_dongle(struct wl_priv *wl, bool need_lock);
@@ -302,7 +302,7 @@ static int32 wl_run_iscan(struct wl_iscan_ctrl *iscan, struct wlc_ssid *ssid,
302static int32 wl_do_iscan(struct wl_priv *wl); 302static int32 wl_do_iscan(struct wl_priv *wl);
303static int32 wl_wakeup_iscan(struct wl_iscan_ctrl *iscan); 303static int32 wl_wakeup_iscan(struct wl_iscan_ctrl *iscan);
304static int32 wl_invoke_iscan(struct wl_priv *wl); 304static int32 wl_invoke_iscan(struct wl_priv *wl);
305static int32 wl_get_iscan_results(struct wl_iscan_ctrl *iscan, uint32 *status, 305static int32 wl_get_iscan_results(struct wl_iscan_ctrl *iscan, u32 *status,
306 struct wl_scan_results **bss_list); 306 struct wl_scan_results **bss_list);
307static void wl_notify_iscan_complete(struct wl_iscan_ctrl *iscan, bool aborted); 307static void wl_notify_iscan_complete(struct wl_iscan_ctrl *iscan, bool aborted);
308static void wl_init_iscan_eloop(struct wl_iscan_eloop *el); 308static void wl_init_iscan_eloop(struct wl_iscan_eloop *el);
@@ -319,7 +319,7 @@ static void wl_init_fw(struct wl_fw_ctrl *fw);
319/* 319/*
320* find most significant bit set 320* find most significant bit set
321*/ 321*/
322static __used uint32 wl_find_msb(u16 bit16); 322static __used u32 wl_find_msb(u16 bit16);
323 323
324/* 324/*
325* update pmklist to dongle 325* update pmklist to dongle
@@ -540,7 +540,7 @@ static struct ieee80211_supported_band __wl_band_5ghz_n = {
540 .n_bitrates = wl_a_rates_size, 540 .n_bitrates = wl_a_rates_size,
541}; 541};
542 542
543static const uint32 __wl_cipher_suites[] = { 543static const u32 __wl_cipher_suites[] = {
544 WLAN_CIPHER_SUITE_WEP40, 544 WLAN_CIPHER_SUITE_WEP40,
545 WLAN_CIPHER_SUITE_WEP104, 545 WLAN_CIPHER_SUITE_WEP104,
546 WLAN_CIPHER_SUITE_TKIP, 546 WLAN_CIPHER_SUITE_TKIP,
@@ -571,7 +571,7 @@ static void swap_key_to_BE(struct wl_wsec_key *key)
571} 571}
572 572
573static int32 573static int32
574wl_dev_ioctl(struct net_device *dev, uint32 cmd, void *arg, uint32 len) 574wl_dev_ioctl(struct net_device *dev, u32 cmd, void *arg, u32 len)
575{ 575{
576 struct ifreq ifr; 576 struct ifreq ifr;
577 struct wl_ioctl ioc; 577 struct wl_ioctl ioc;
@@ -595,7 +595,7 @@ wl_dev_ioctl(struct net_device *dev, uint32 cmd, void *arg, uint32 len)
595 595
596static int32 596static int32
597wl_cfg80211_change_iface(struct wiphy *wiphy, struct net_device *ndev, 597wl_cfg80211_change_iface(struct wiphy *wiphy, struct net_device *ndev,
598 enum nl80211_iftype type, uint32 *flags, 598 enum nl80211_iftype type, u32 *flags,
599 struct vif_params *params) 599 struct vif_params *params)
600{ 600{
601 struct wl_priv *wl = wiphy_to_wl(wiphy); 601 struct wl_priv *wl = wiphy_to_wl(wiphy);
@@ -866,7 +866,7 @@ wl_cfg80211_scan(struct wiphy *wiphy, struct net_device *ndev,
866static int32 wl_dev_intvar_set(struct net_device *dev, s8 *name, int32 val) 866static int32 wl_dev_intvar_set(struct net_device *dev, s8 *name, int32 val)
867{ 867{
868 s8 buf[WLC_IOCTL_SMLEN]; 868 s8 buf[WLC_IOCTL_SMLEN];
869 uint32 len; 869 u32 len;
870 int32 err = 0; 870 int32 err = 0;
871 871
872 val = htod32(val); 872 val = htod32(val);
@@ -888,8 +888,8 @@ wl_dev_intvar_get(struct net_device *dev, s8 *name, int32 *retval)
888 s8 buf[WLC_IOCTL_SMLEN]; 888 s8 buf[WLC_IOCTL_SMLEN];
889 int32 val; 889 int32 val;
890 } var; 890 } var;
891 uint32 len; 891 u32 len;
892 uint32 data_null; 892 u32 data_null;
893 int32 err = 0; 893 int32 err = 0;
894 894
895 len = 895 len =
@@ -905,7 +905,7 @@ wl_dev_intvar_get(struct net_device *dev, s8 *name, int32 *retval)
905 return err; 905 return err;
906} 906}
907 907
908static int32 wl_set_rts(struct net_device *dev, uint32 rts_threshold) 908static int32 wl_set_rts(struct net_device *dev, u32 rts_threshold)
909{ 909{
910 int32 err = 0; 910 int32 err = 0;
911 911
@@ -917,7 +917,7 @@ static int32 wl_set_rts(struct net_device *dev, uint32 rts_threshold)
917 return err; 917 return err;
918} 918}
919 919
920static int32 wl_set_frag(struct net_device *dev, uint32 frag_threshold) 920static int32 wl_set_frag(struct net_device *dev, u32 frag_threshold)
921{ 921{
922 int32 err = 0; 922 int32 err = 0;
923 923
@@ -929,10 +929,10 @@ static int32 wl_set_frag(struct net_device *dev, uint32 frag_threshold)
929 return err; 929 return err;
930} 930}
931 931
932static int32 wl_set_retry(struct net_device *dev, uint32 retry, bool l) 932static int32 wl_set_retry(struct net_device *dev, u32 retry, bool l)
933{ 933{
934 int32 err = 0; 934 int32 err = 0;
935 uint32 cmd = (l ? WLC_SET_LRL : WLC_SET_SRL); 935 u32 cmd = (l ? WLC_SET_LRL : WLC_SET_SRL);
936 936
937 retry = htod32(retry); 937 retry = htod32(retry);
938 err = wl_dev_ioctl(dev, cmd, &retry, sizeof(retry)); 938 err = wl_dev_ioctl(dev, cmd, &retry, sizeof(retry));
@@ -943,7 +943,7 @@ static int32 wl_set_retry(struct net_device *dev, uint32 retry, bool l)
943 return err; 943 return err;
944} 944}
945 945
946static int32 wl_cfg80211_set_wiphy_params(struct wiphy *wiphy, uint32 changed) 946static int32 wl_cfg80211_set_wiphy_params(struct wiphy *wiphy, u32 changed)
947{ 947{
948 struct wl_priv *wl = wiphy_to_wl(wiphy); 948 struct wl_priv *wl = wiphy_to_wl(wiphy);
949 struct net_device *ndev = wl_to_ndev(wl); 949 struct net_device *ndev = wl_to_ndev(wl);
@@ -1270,8 +1270,8 @@ wl_set_set_sharedkey(struct net_device *dev,
1270&& (sec->cipher_pairwise & (WLAN_CIPHER_SUITE_WEP40 | 1270&& (sec->cipher_pairwise & (WLAN_CIPHER_SUITE_WEP40 |
1271 WLAN_CIPHER_SUITE_WEP104))) { 1271 WLAN_CIPHER_SUITE_WEP104))) {
1272 memset(&key, 0, sizeof(key)); 1272 memset(&key, 0, sizeof(key));
1273 key.len = (uint32) sme->key_len; 1273 key.len = (u32) sme->key_len;
1274 key.index = (uint32) sme->key_idx; 1274 key.index = (u32) sme->key_idx;
1275 if (unlikely(key.len > sizeof(key.data))) { 1275 if (unlikely(key.len > sizeof(key.data))) {
1276 WL_ERR(("Too long key length (%u)\n", key.len)); 1276 WL_ERR(("Too long key length (%u)\n", key.len));
1277 return -EINVAL; 1277 return -EINVAL;
@@ -1481,7 +1481,7 @@ static int32
1481wl_cfg80211_config_default_key(struct wiphy *wiphy, struct net_device *dev, 1481wl_cfg80211_config_default_key(struct wiphy *wiphy, struct net_device *dev,
1482 u8 key_idx) 1482 u8 key_idx)
1483{ 1483{
1484 uint32 index; 1484 u32 index;
1485 int32 wsec; 1485 int32 wsec;
1486 int32 err = 0; 1486 int32 err = 0;
1487 1487
@@ -1496,7 +1496,7 @@ wl_cfg80211_config_default_key(struct wiphy *wiphy, struct net_device *dev,
1496 wsec = dtoh32(wsec); 1496 wsec = dtoh32(wsec);
1497 if (wsec & WEP_ENABLED) { 1497 if (wsec & WEP_ENABLED) {
1498 /* Just select a new current key */ 1498 /* Just select a new current key */
1499 index = (uint32) key_idx; 1499 index = (u32) key_idx;
1500 index = htod32(index); 1500 index = htod32(index);
1501 err = wl_dev_ioctl(dev, WLC_SET_KEY_PRIMARY, &index, 1501 err = wl_dev_ioctl(dev, WLC_SET_KEY_PRIMARY, &index,
1502 sizeof(index)); 1502 sizeof(index));
@@ -1515,12 +1515,12 @@ wl_add_keyext(struct wiphy *wiphy, struct net_device *dev,
1515 int32 err = 0; 1515 int32 err = 0;
1516 1516
1517 memset(&key, 0, sizeof(key)); 1517 memset(&key, 0, sizeof(key));
1518 key.index = (uint32) key_idx; 1518 key.index = (u32) key_idx;
1519 /* Instead of bcast for ea address for default wep keys, 1519 /* Instead of bcast for ea address for default wep keys,
1520 driver needs it to be Null */ 1520 driver needs it to be Null */
1521 if (!ETHER_ISMULTI(mac_addr)) 1521 if (!ETHER_ISMULTI(mac_addr))
1522 memcpy((char *)&key.ea, (void *)mac_addr, ETHER_ADDR_LEN); 1522 memcpy((char *)&key.ea, (void *)mac_addr, ETHER_ADDR_LEN);
1523 key.len = (uint32) params->key_len; 1523 key.len = (u32) params->key_len;
1524 /* check for key index change */ 1524 /* check for key index change */
1525 if (key.len == 0) { 1525 if (key.len == 0) {
1526 /* key delete */ 1526 /* key delete */
@@ -1611,8 +1611,8 @@ wl_cfg80211_add_key(struct wiphy *wiphy, struct net_device *dev,
1611 return wl_add_keyext(wiphy, dev, key_idx, mac_addr, params); 1611 return wl_add_keyext(wiphy, dev, key_idx, mac_addr, params);
1612 memset(&key, 0, sizeof(key)); 1612 memset(&key, 0, sizeof(key));
1613 1613
1614 key.len = (uint32) params->key_len; 1614 key.len = (u32) params->key_len;
1615 key.index = (uint32) key_idx; 1615 key.index = (u32) key_idx;
1616 1616
1617 if (unlikely(key.len > sizeof(key.data))) { 1617 if (unlikely(key.len > sizeof(key.data))) {
1618 WL_ERR(("Too long key length (%u)\n", key.len)); 1618 WL_ERR(("Too long key length (%u)\n", key.len));
@@ -1691,7 +1691,7 @@ wl_cfg80211_del_key(struct wiphy *wiphy, struct net_device *dev,
1691 CHECK_SYS_UP(); 1691 CHECK_SYS_UP();
1692 memset(&key, 0, sizeof(key)); 1692 memset(&key, 0, sizeof(key));
1693 1693
1694 key.index = (uint32) key_idx; 1694 key.index = (u32) key_idx;
1695 key.flags = WL_PRIMARY_KEY; 1695 key.flags = WL_PRIMARY_KEY;
1696 key.algo = CRYPTO_ALGO_OFF; 1696 key.algo = CRYPTO_ALGO_OFF;
1697 1697
@@ -1867,9 +1867,9 @@ wl_cfg80211_set_power_mgmt(struct wiphy *wiphy, struct net_device *dev,
1867 return err; 1867 return err;
1868} 1868}
1869 1869
1870static __used uint32 wl_find_msb(u16 bit16) 1870static __used u32 wl_find_msb(u16 bit16)
1871{ 1871{
1872 uint32 ret = 0; 1872 u32 ret = 0;
1873 1873
1874 if (bit16 & 0xff00) { 1874 if (bit16 & 0xff00) {
1875 ret += 8; 1875 ret += 8;
@@ -1904,7 +1904,7 @@ wl_cfg80211_set_bitrate_mask(struct wiphy *wiphy, struct net_device *dev,
1904 int32 val; 1904 int32 val;
1905 int32 err_bg; 1905 int32 err_bg;
1906 int32 err_a; 1906 int32 err_a;
1907 uint32 legacy; 1907 u32 legacy;
1908 int32 err = 0; 1908 int32 err = 0;
1909 1909
1910 CHECK_SYS_UP(); 1910 CHECK_SYS_UP();
@@ -2252,8 +2252,8 @@ static int32 wl_inform_single_bss(struct wl_priv *wl, struct wl_bss_info *bi)
2252 struct ieee80211_supported_band *band; 2252 struct ieee80211_supported_band *band;
2253 struct wl_cfg80211_bss_info *notif_bss_info; 2253 struct wl_cfg80211_bss_info *notif_bss_info;
2254 struct wl_scan_req *sr = wl_to_sr(wl); 2254 struct wl_scan_req *sr = wl_to_sr(wl);
2255 uint32 signal; 2255 u32 signal;
2256 uint32 freq; 2256 u32 freq;
2257 int32 err = 0; 2257 int32 err = 0;
2258 2258
2259 if (unlikely(dtoh32(bi->length) > WL_BSS_INFO_MAX)) { 2259 if (unlikely(dtoh32(bi->length) > WL_BSS_INFO_MAX)) {
@@ -2316,7 +2316,7 @@ static int32 wl_inform_single_bss(struct wl_priv *wl, struct wl_bss_info *bi)
2316 2316
2317static bool wl_is_linkup(struct wl_priv *wl, const wl_event_msg_t *e) 2317static bool wl_is_linkup(struct wl_priv *wl, const wl_event_msg_t *e)
2318{ 2318{
2319 uint32 event = ntoh32(e->event_type); 2319 u32 event = ntoh32(e->event_type);
2320 u16 flags = ntoh16(e->flags); 2320 u16 flags = ntoh16(e->flags);
2321 2321
2322 if (event == WLC_E_JOIN || event == WLC_E_ASSOC_IND 2322 if (event == WLC_E_JOIN || event == WLC_E_ASSOC_IND
@@ -2338,7 +2338,7 @@ static bool wl_is_linkup(struct wl_priv *wl, const wl_event_msg_t *e)
2338 2338
2339static bool wl_is_linkdown(struct wl_priv *wl, const wl_event_msg_t *e) 2339static bool wl_is_linkdown(struct wl_priv *wl, const wl_event_msg_t *e)
2340{ 2340{
2341 uint32 event = ntoh32(e->event_type); 2341 u32 event = ntoh32(e->event_type);
2342 u16 flags = ntoh16(e->flags); 2342 u16 flags = ntoh16(e->flags);
2343 2343
2344 if (event == WLC_E_DEAUTH_IND || event == WLC_E_DISASSOC_IND) { 2344 if (event == WLC_E_DEAUTH_IND || event == WLC_E_DISASSOC_IND) {
@@ -2353,8 +2353,8 @@ static bool wl_is_linkdown(struct wl_priv *wl, const wl_event_msg_t *e)
2353 2353
2354static bool wl_is_nonetwork(struct wl_priv *wl, const wl_event_msg_t *e) 2354static bool wl_is_nonetwork(struct wl_priv *wl, const wl_event_msg_t *e)
2355{ 2355{
2356 uint32 event = ntoh32(e->event_type); 2356 u32 event = ntoh32(e->event_type);
2357 uint32 status = ntoh32(e->status); 2357 u32 status = ntoh32(e->status);
2358 2358
2359 if (event == WLC_E_SET_SSID || event == WLC_E_LINK) { 2359 if (event == WLC_E_SET_SSID || event == WLC_E_LINK) {
2360 if (status == WLC_E_STATUS_NO_NETWORKS) 2360 if (status == WLC_E_STATUS_NO_NETWORKS)
@@ -2415,7 +2415,7 @@ static __used int32
2415wl_dev_bufvar_set(struct net_device *dev, s8 *name, s8 *buf, int32 len) 2415wl_dev_bufvar_set(struct net_device *dev, s8 *name, s8 *buf, int32 len)
2416{ 2416{
2417 struct wl_priv *wl = ndev_to_wl(dev); 2417 struct wl_priv *wl = ndev_to_wl(dev);
2418 uint32 buflen; 2418 u32 buflen;
2419 2419
2420 buflen = bcm_mkiovar(name, buf, len, wl->ioctl_buf, WL_IOCTL_LEN_MAX); 2420 buflen = bcm_mkiovar(name, buf, len, wl->ioctl_buf, WL_IOCTL_LEN_MAX);
2421 BUG_ON(unlikely(!buflen)); 2421 BUG_ON(unlikely(!buflen));
@@ -2428,7 +2428,7 @@ wl_dev_bufvar_get(struct net_device *dev, s8 *name, s8 *buf,
2428 int32 buf_len) 2428 int32 buf_len)
2429{ 2429{
2430 struct wl_priv *wl = ndev_to_wl(dev); 2430 struct wl_priv *wl = ndev_to_wl(dev);
2431 uint32 len; 2431 u32 len;
2432 int32 err = 0; 2432 int32 err = 0;
2433 2433
2434 len = bcm_mkiovar(name, NULL, 0, wl->ioctl_buf, WL_IOCTL_LEN_MAX); 2434 len = bcm_mkiovar(name, NULL, 0, wl->ioctl_buf, WL_IOCTL_LEN_MAX);
@@ -2449,8 +2449,8 @@ static int32 wl_get_assoc_ies(struct wl_priv *wl)
2449 struct net_device *ndev = wl_to_ndev(wl); 2449 struct net_device *ndev = wl_to_ndev(wl);
2450 struct wl_assoc_ielen *assoc_info; 2450 struct wl_assoc_ielen *assoc_info;
2451 struct wl_connect_info *conn_info = wl_to_conn(wl); 2451 struct wl_connect_info *conn_info = wl_to_conn(wl);
2452 uint32 req_len; 2452 u32 req_len;
2453 uint32 resp_len; 2453 u32 resp_len;
2454 int32 err = 0; 2454 int32 err = 0;
2455 2455
2456 err = wl_dev_bufvar_get(ndev, "assoc_info", wl->extra_buf, 2456 err = wl_dev_bufvar_get(ndev, "assoc_info", wl->extra_buf,
@@ -2515,7 +2515,7 @@ static int32 wl_update_bss_info(struct wl_priv *wl)
2515 rtnl_lock(); 2515 rtnl_lock();
2516 if (unlikely(!bss)) { 2516 if (unlikely(!bss)) {
2517 WL_DBG(("Could not find the AP\n")); 2517 WL_DBG(("Could not find the AP\n"));
2518 *(uint32 *) wl->extra_buf = htod32(WL_EXTRA_BUF_MAX); 2518 *(u32 *) wl->extra_buf = htod32(WL_EXTRA_BUF_MAX);
2519 err = wl_dev_ioctl(wl_to_ndev(wl), WLC_GET_BSS_INFO, 2519 err = wl_dev_ioctl(wl_to_ndev(wl), WLC_GET_BSS_INFO,
2520 wl->extra_buf, WL_EXTRA_BUF_MAX); 2520 wl->extra_buf, WL_EXTRA_BUF_MAX);
2521 if (unlikely(err)) { 2521 if (unlikely(err)) {
@@ -2624,7 +2624,7 @@ wl_notify_scan_status(struct wl_priv *wl, struct net_device *ndev,
2624{ 2624{
2625 struct channel_info channel_inform; 2625 struct channel_info channel_inform;
2626 struct wl_scan_results *bss_list; 2626 struct wl_scan_results *bss_list;
2627 uint32 len = WL_SCAN_BUF_MAX; 2627 u32 len = WL_SCAN_BUF_MAX;
2628 int32 err = 0; 2628 int32 err = 0;
2629 2629
2630 if (wl->iscan_on && wl->iscan_kickstart) 2630 if (wl->iscan_on && wl->iscan_kickstart)
@@ -2678,11 +2678,11 @@ scan_done_out:
2678 2678
2679static void wl_init_conf(struct wl_conf *conf) 2679static void wl_init_conf(struct wl_conf *conf)
2680{ 2680{
2681 conf->mode = (uint32)-1; 2681 conf->mode = (u32)-1;
2682 conf->frag_threshold = (uint32)-1; 2682 conf->frag_threshold = (u32)-1;
2683 conf->rts_threshold = (uint32)-1; 2683 conf->rts_threshold = (u32)-1;
2684 conf->retry_short = (uint32)-1; 2684 conf->retry_short = (u32)-1;
2685 conf->retry_long = (uint32)-1; 2685 conf->retry_long = (u32)-1;
2686 conf->tx_power = -1; 2686 conf->tx_power = -1;
2687} 2687}
2688 2688
@@ -2852,7 +2852,7 @@ static int32 wl_wakeup_iscan(struct wl_iscan_ctrl *iscan)
2852} 2852}
2853 2853
2854static int32 2854static int32
2855wl_get_iscan_results(struct wl_iscan_ctrl *iscan, uint32 *status, 2855wl_get_iscan_results(struct wl_iscan_ctrl *iscan, u32 *status,
2856 struct wl_scan_results **bss_list) 2856 struct wl_scan_results **bss_list)
2857{ 2857{
2858 struct wl_iscan_results list; 2858 struct wl_iscan_results list;
@@ -2948,7 +2948,7 @@ static int32 wl_iscan_thread(void *data)
2948 struct wl_iscan_ctrl *iscan = (struct wl_iscan_ctrl *)data; 2948 struct wl_iscan_ctrl *iscan = (struct wl_iscan_ctrl *)data;
2949 struct wl_priv *wl = iscan_to_wl(iscan); 2949 struct wl_priv *wl = iscan_to_wl(iscan);
2950 struct wl_iscan_eloop *el = &iscan->el; 2950 struct wl_iscan_eloop *el = &iscan->el;
2951 uint32 status; 2951 u32 status;
2952 int err = 0; 2952 int err = 0;
2953 2953
2954 sched_setscheduler(current, SCHED_FIFO, &param); 2954 sched_setscheduler(current, SCHED_FIFO, &param);
@@ -3192,7 +3192,7 @@ static int32 wl_event_handler(void *data)
3192void 3192void
3193wl_cfg80211_event(struct net_device *ndev, const wl_event_msg_t * e, void *data) 3193wl_cfg80211_event(struct net_device *ndev, const wl_event_msg_t * e, void *data)
3194{ 3194{
3195 uint32 event_type = ntoh32(e->event_type); 3195 u32 event_type = ntoh32(e->event_type);
3196 struct wl_priv *wl = ndev_to_wl(ndev); 3196 struct wl_priv *wl = ndev_to_wl(ndev);
3197#if (WL_DBG_LEVEL > 0) 3197#if (WL_DBG_LEVEL > 0)
3198 s8 *estr = (event_type <= sizeof(wl_dbg_estr) / WL_DBG_ESTR_MAX - 1) ? 3198 s8 *estr = (event_type <= sizeof(wl_dbg_estr) / WL_DBG_ESTR_MAX - 1) ?
@@ -3245,7 +3245,7 @@ static struct wl_event_q *wl_deq_event(struct wl_priv *wl)
3245*/ 3245*/
3246 3246
3247static int32 3247static int32
3248wl_enq_event(struct wl_priv *wl, uint32 event, const wl_event_msg_t *msg, 3248wl_enq_event(struct wl_priv *wl, u32 event, const wl_event_msg_t *msg,
3249 void *data) 3249 void *data)
3250{ 3250{
3251 struct wl_event_q *e; 3251 struct wl_event_q *e;
@@ -3337,7 +3337,7 @@ static int32 wl_dongle_country(struct net_device *ndev, u8 ccode)
3337 return err; 3337 return err;
3338} 3338}
3339 3339
3340static int32 wl_dongle_up(struct net_device *ndev, uint32 up) 3340static int32 wl_dongle_up(struct net_device *ndev, u32 up)
3341{ 3341{
3342 int32 err = 0; 3342 int32 err = 0;
3343 3343
@@ -3348,7 +3348,7 @@ static int32 wl_dongle_up(struct net_device *ndev, uint32 up)
3348 return err; 3348 return err;
3349} 3349}
3350 3350
3351static int32 wl_dongle_power(struct net_device *ndev, uint32 power_mode) 3351static int32 wl_dongle_power(struct net_device *ndev, u32 power_mode)
3352{ 3352{
3353 int32 err = 0; 3353 int32 err = 0;
3354 3354
@@ -3360,7 +3360,7 @@ static int32 wl_dongle_power(struct net_device *ndev, uint32 power_mode)
3360} 3360}
3361 3361
3362static int32 3362static int32
3363wl_dongle_glom(struct net_device *ndev, uint32 glom, uint32 dongle_align) 3363wl_dongle_glom(struct net_device *ndev, u32 glom, u32 dongle_align)
3364{ 3364{
3365 s8 iovbuf[WL_EVENTING_MASK_LEN + 12]; /* Room for "event_msgs" + 3365 s8 iovbuf[WL_EVENTING_MASK_LEN + 12]; /* Room for "event_msgs" +
3366 '\0' + bitvec */ 3366 '\0' + bitvec */
@@ -3386,7 +3386,7 @@ dongle_glom_out:
3386} 3386}
3387 3387
3388static int32 3388static int32
3389wl_dongle_roam(struct net_device *ndev, uint32 roamvar, uint32 bcn_timeout) 3389wl_dongle_roam(struct net_device *ndev, u32 roamvar, u32 bcn_timeout)
3390{ 3390{
3391 s8 iovbuf[WL_EVENTING_MASK_LEN + 12]; /* Room for "event_msgs" + 3391 s8 iovbuf[WL_EVENTING_MASK_LEN + 12]; /* Room for "event_msgs" +
3392 '\0' + bitvec */ 3392 '\0' + bitvec */
@@ -3551,7 +3551,7 @@ static int32 wl_pattern_atoh(s8 *src, s8 *dst)
3551 return i; 3551 return i;
3552} 3552}
3553 3553
3554static int32 wl_dongle_filter(struct net_device *ndev, uint32 filter_mode) 3554static int32 wl_dongle_filter(struct net_device *ndev, u32 filter_mode)
3555{ 3555{
3556 s8 iovbuf[WL_EVENTING_MASK_LEN + 12]; /* Room for "event_msgs" + 3556 s8 iovbuf[WL_EVENTING_MASK_LEN + 12]; /* Room for "event_msgs" +
3557 '\0' + bitvec */ 3557 '\0' + bitvec */
@@ -3560,8 +3560,8 @@ static int32 wl_dongle_filter(struct net_device *ndev, uint32 filter_mode)
3560 struct wl_pkt_filter *pkt_filterp; 3560 struct wl_pkt_filter *pkt_filterp;
3561 int32 buf_len; 3561 int32 buf_len;
3562 int32 str_len; 3562 int32 str_len;
3563 uint32 mask_size; 3563 u32 mask_size;
3564 uint32 pattern_size; 3564 u32 pattern_size;
3565 s8 buf[256]; 3565 s8 buf[256];
3566 int32 err = 0; 3566 int32 err = 0;
3567 3567
@@ -3852,7 +3852,7 @@ wl_update_prof(struct wl_priv *wl, const wl_event_msg_t *e, void *data,
3852 return err; 3852 return err;
3853} 3853}
3854 3854
3855void wl_cfg80211_dbg_level(uint32 level) 3855void wl_cfg80211_dbg_level(u32 level)
3856{ 3856{
3857 /* 3857 /*
3858 * prohibit to change debug level 3858 * prohibit to change debug level
@@ -3926,7 +3926,7 @@ static int32 wl_cp_ie(struct wl_priv *wl, u8 *dst, u16 dst_size)
3926 return err; 3926 return err;
3927} 3927}
3928 3928
3929static uint32 wl_get_ielen(struct wl_priv *wl) 3929static u32 wl_get_ielen(struct wl_priv *wl)
3930{ 3930{
3931 struct wl_ie *ie = wl_to_ie(wl); 3931 struct wl_ie *ie = wl_to_ie(wl);
3932 3932
@@ -3966,7 +3966,7 @@ static void wl_init_eq_lock(struct wl_priv *wl)
3966 spin_lock_init(&wl->eq_lock); 3966 spin_lock_init(&wl->eq_lock);
3967} 3967}
3968 3968
3969static void wl_delay(uint32 ms) 3969static void wl_delay(u32 ms)
3970{ 3970{
3971 if (ms < 1000 / HZ) { 3971 if (ms < 1000 / HZ) {
3972 cond_resched(); 3972 cond_resched();
@@ -3986,7 +3986,7 @@ static void *wl_get_drvdata(struct wl_dev *dev)
3986 return dev->driver_data; 3986 return dev->driver_data;
3987} 3987}
3988 3988
3989int32 wl_cfg80211_read_fw(s8 *buf, uint32 size) 3989int32 wl_cfg80211_read_fw(s8 *buf, u32 size)
3990{ 3990{
3991 const struct firmware *fw_entry; 3991 const struct firmware *fw_entry;
3992 struct wl_priv *wl; 3992 struct wl_priv *wl;
diff --git a/drivers/staging/brcm80211/brcmfmac/wl_cfg80211.h b/drivers/staging/brcm80211/brcmfmac/wl_cfg80211.h
index 3843f75410b..1b0566ef00a 100644
--- a/drivers/staging/brcm80211/brcmfmac/wl_cfg80211.h
+++ b/drivers/staging/brcm80211/brcmfmac/wl_cfg80211.h
@@ -153,11 +153,11 @@ enum wl_fw_status {
153 153
154/* dongle configuration */ 154/* dongle configuration */
155struct wl_conf { 155struct wl_conf {
156 uint32 mode; /* adhoc , infrastructure or ap */ 156 u32 mode; /* adhoc , infrastructure or ap */
157 uint32 frag_threshold; 157 u32 frag_threshold;
158 uint32 rts_threshold; 158 u32 rts_threshold;
159 uint32 retry_short; 159 u32 retry_short;
160 uint32 retry_long; 160 u32 retry_long;
161 int32 tx_power; 161 int32 tx_power;
162 struct ieee80211_channel channel; 162 struct ieee80211_channel channel;
163}; 163};
@@ -201,18 +201,18 @@ struct wl_ie {
201/* event queue for cfg80211 main event */ 201/* event queue for cfg80211 main event */
202struct wl_event_q { 202struct wl_event_q {
203 struct list_head eq_list; 203 struct list_head eq_list;
204 uint32 etype; 204 u32 etype;
205 wl_event_msg_t emsg; 205 wl_event_msg_t emsg;
206 s8 edata[1]; 206 s8 edata[1];
207}; 207};
208 208
209/* security information with currently associated ap */ 209/* security information with currently associated ap */
210struct wl_security { 210struct wl_security {
211 uint32 wpa_versions; 211 u32 wpa_versions;
212 uint32 auth_type; 212 u32 auth_type;
213 uint32 cipher_pairwise; 213 u32 cipher_pairwise;
214 uint32 cipher_group; 214 u32 cipher_group;
215 uint32 wpa_auth; 215 u32 wpa_auth;
216}; 216};
217 217
218/* ibss information for currently joined ibss network */ 218/* ibss information for currently joined ibss network */
@@ -226,7 +226,7 @@ struct wl_ibss {
226 226
227/* dongle profile */ 227/* dongle profile */
228struct wl_profile { 228struct wl_profile {
229 uint32 mode; 229 u32 mode;
230 struct wlc_ssid ssid; 230 struct wlc_ssid ssid;
231 u8 bssid[ETHER_ADDR_LEN]; 231 u8 bssid[ETHER_ADDR_LEN];
232 struct wl_security sec; 232 struct wl_security sec;
@@ -244,8 +244,8 @@ struct wl_iscan_eloop {
244struct wl_iscan_ctrl { 244struct wl_iscan_ctrl {
245 struct net_device *dev; 245 struct net_device *dev;
246 struct timer_list timer; 246 struct timer_list timer;
247 uint32 timer_ms; 247 u32 timer_ms;
248 uint32 timer_on; 248 u32 timer_on;
249 int32 state; 249 int32 state;
250 int32 pid; 250 int32 pid;
251 struct semaphore sync; 251 struct semaphore sync;
@@ -268,15 +268,15 @@ struct wl_connect_info {
268struct wl_fw_ctrl { 268struct wl_fw_ctrl {
269 const struct firmware *fw_entry; 269 const struct firmware *fw_entry;
270 unsigned long status; 270 unsigned long status;
271 uint32 ptr; 271 u32 ptr;
272 s8 fw_name[WL_FILE_NAME_MAX]; 272 s8 fw_name[WL_FILE_NAME_MAX];
273 s8 nvram_name[WL_FILE_NAME_MAX]; 273 s8 nvram_name[WL_FILE_NAME_MAX];
274}; 274};
275 275
276/* assoc ie length */ 276/* assoc ie length */
277struct wl_assoc_ielen { 277struct wl_assoc_ielen {
278 uint32 req_len; 278 u32 req_len;
279 uint32 resp_len; 279 u32 resp_len;
280}; 280};
281 281
282/* wpa2 pmk list */ 282/* wpa2 pmk list */
@@ -318,7 +318,7 @@ struct wl_priv {
318 int32 event_pid; /* pid of main event handler thread */ 318 int32 event_pid; /* pid of main event handler thread */
319 unsigned long status; /* current dongle status */ 319 unsigned long status; /* current dongle status */
320 void *pub; 320 void *pub;
321 uint32 channel; /* current channel */ 321 u32 channel; /* current channel */
322 bool iscan_on; /* iscan on/off switch */ 322 bool iscan_on; /* iscan on/off switch */
323 bool iscan_kickstart; /* indicate iscan already started */ 323 bool iscan_kickstart; /* indicate iscan already started */
324 bool active_scan; /* current scan mode */ 324 bool active_scan; /* current scan mode */
@@ -369,11 +369,11 @@ extern void wl_cfg80211_sdio_func(void *func); /* set sdio function info */
369extern struct sdio_func *wl_cfg80211_get_sdio_func(void); /* set sdio function info */ 369extern struct sdio_func *wl_cfg80211_get_sdio_func(void); /* set sdio function info */
370extern int32 wl_cfg80211_up(void); /* dongle up */ 370extern int32 wl_cfg80211_up(void); /* dongle up */
371extern int32 wl_cfg80211_down(void); /* dongle down */ 371extern int32 wl_cfg80211_down(void); /* dongle down */
372extern void wl_cfg80211_dbg_level(uint32 level); /* set dongle 372extern void wl_cfg80211_dbg_level(u32 level); /* set dongle
373 debugging level */ 373 debugging level */
374extern void *wl_cfg80211_request_fw(s8 *file_name); /* request fw /nvram 374extern void *wl_cfg80211_request_fw(s8 *file_name); /* request fw /nvram
375 downloading */ 375 downloading */
376extern int32 wl_cfg80211_read_fw(s8 *buf, uint32 size); /* read fw 376extern int32 wl_cfg80211_read_fw(s8 *buf, u32 size); /* read fw
377 image */ 377 image */
378extern void wl_cfg80211_release_fw(void); /* release fw */ 378extern void wl_cfg80211_release_fw(void); /* release fw */
379extern s8 *wl_cfg80211_get_fwname(void); /* get firmware name for 379extern s8 *wl_cfg80211_get_fwname(void); /* get firmware name for
diff --git a/drivers/staging/brcm80211/brcmfmac/wl_iw.c b/drivers/staging/brcm80211/brcmfmac/wl_iw.c
index 5306368ecd5..910e56d3ae9 100644
--- a/drivers/staging/brcm80211/brcmfmac/wl_iw.c
+++ b/drivers/staging/brcm80211/brcmfmac/wl_iw.c
@@ -66,8 +66,8 @@ bool g_set_essid_before_scan = TRUE;
66static int g_onoff = G_WLAN_SET_ON; 66static int g_onoff = G_WLAN_SET_ON;
67wl_iw_extra_params_t g_wl_iw_params; 67wl_iw_extra_params_t g_wl_iw_params;
68 68
69extern bool wl_iw_conn_status_str(uint32 event_type, uint32 status, 69extern bool wl_iw_conn_status_str(u32 event_type, u32 status,
70 uint32 reason, char *stringBuf, uint buflen); 70 u32 reason, char *stringBuf, uint buflen);
71 71
72uint wl_msg_level = WL_ERROR_VAL; 72uint wl_msg_level = WL_ERROR_VAL;
73 73
@@ -127,8 +127,8 @@ typedef struct iscan_buf {
127typedef struct iscan_info { 127typedef struct iscan_info {
128 struct net_device *dev; 128 struct net_device *dev;
129 struct timer_list timer; 129 struct timer_list timer;
130 uint32 timer_ms; 130 u32 timer_ms;
131 uint32 timer_on; 131 u32 timer_on;
132 int iscan_state; 132 int iscan_state;
133 iscan_buf_t *list_hdr; 133 iscan_buf_t *list_hdr;
134 iscan_buf_t *list_cur; 134 iscan_buf_t *list_cur;
@@ -493,7 +493,7 @@ wl_iw_get_range(struct net_device *dev,
493 struct iw_point *dwrq, char *extra) 493 struct iw_point *dwrq, char *extra)
494{ 494{
495 struct iw_range *range = (struct iw_range *)extra; 495 struct iw_range *range = (struct iw_range *)extra;
496 wl_uint32_list_t *list; 496 wl_u32_list_t *list;
497 wl_rateset_t rateset; 497 wl_rateset_t rateset;
498 s8 *channels; 498 s8 *channels;
499 int error, i, k; 499 int error, i, k;
@@ -519,7 +519,7 @@ wl_iw_get_range(struct net_device *dev,
519 WL_ERROR(("Could not alloc channels\n")); 519 WL_ERROR(("Could not alloc channels\n"));
520 return -ENOMEM; 520 return -ENOMEM;
521 } 521 }
522 list = (wl_uint32_list_t *) channels; 522 list = (wl_u32_list_t *) channels;
523 523
524 dwrq->length = sizeof(struct iw_range); 524 dwrq->length = sizeof(struct iw_range);
525 memset(range, 0, sizeof(range)); 525 memset(range, 0, sizeof(range));
@@ -1097,14 +1097,14 @@ static void wl_iw_set_event_mask(struct net_device *dev)
1097 iovbuf, sizeof(iovbuf)); 1097 iovbuf, sizeof(iovbuf));
1098} 1098}
1099 1099
1100static uint32 wl_iw_iscan_get(iscan_info_t *iscan) 1100static u32 wl_iw_iscan_get(iscan_info_t *iscan)
1101{ 1101{
1102 iscan_buf_t *buf; 1102 iscan_buf_t *buf;
1103 iscan_buf_t *ptr; 1103 iscan_buf_t *ptr;
1104 wl_iscan_results_t *list_buf; 1104 wl_iscan_results_t *list_buf;
1105 wl_iscan_results_t list; 1105 wl_iscan_results_t list;
1106 wl_scan_results_t *results; 1106 wl_scan_results_t *results;
1107 uint32 status; 1107 u32 status;
1108 int res = 0; 1108 int res = 0;
1109 1109
1110 MUTEX_LOCK_WL_SCAN_SET(); 1110 MUTEX_LOCK_WL_SCAN_SET();
@@ -1185,7 +1185,7 @@ static void wl_iw_send_scan_complete(iscan_info_t *iscan)
1185 1185
1186static int _iscan_sysioc_thread(void *data) 1186static int _iscan_sysioc_thread(void *data)
1187{ 1187{
1188 uint32 status; 1188 u32 status;
1189 iscan_info_t *iscan = (iscan_info_t *) data; 1189 iscan_info_t *iscan = (iscan_info_t *) data;
1190 static bool iscan_pass_abort = FALSE; 1190 static bool iscan_pass_abort = FALSE;
1191 DAEMONIZE("iscan_sysioc"); 1191 DAEMONIZE("iscan_sysioc");
@@ -1745,7 +1745,7 @@ wl_iw_iscan_get_scan(struct net_device *dev,
1745 char *event = extra, *end = extra + dwrq->length, *value; 1745 char *event = extra, *end = extra + dwrq->length, *value;
1746 iscan_info_t *iscan = g_iscan; 1746 iscan_info_t *iscan = g_iscan;
1747 iscan_buf_t *p_buf; 1747 iscan_buf_t *p_buf;
1748 uint32 counter = 0; 1748 u32 counter = 0;
1749 u8 channel; 1749 u8 channel;
1750 1750
1751 WL_TRACE(("%s %s buflen_from_user %d:\n", dev->name, __func__, 1751 WL_TRACE(("%s %s buflen_from_user %d:\n", dev->name, __func__,
@@ -3300,13 +3300,13 @@ int wl_iw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3300} 3300}
3301 3301
3302bool 3302bool
3303wl_iw_conn_status_str(uint32 event_type, uint32 status, uint32 reason, 3303wl_iw_conn_status_str(u32 event_type, u32 status, u32 reason,
3304 char *stringBuf, uint buflen) 3304 char *stringBuf, uint buflen)
3305{ 3305{
3306 typedef struct conn_fail_event_map_t { 3306 typedef struct conn_fail_event_map_t {
3307 uint32 inEvent; 3307 u32 inEvent;
3308 uint32 inStatus; 3308 u32 inStatus;
3309 uint32 inReason; 3309 u32 inReason;
3310 const char *outName; 3310 const char *outName;
3311 const char *outCause; 3311 const char *outCause;
3312 } conn_fail_event_map_t; 3312 } conn_fail_event_map_t;
@@ -3380,9 +3380,9 @@ wl_iw_conn_status_str(uint32 event_type, uint32 status, uint32 reason,
3380static bool 3380static bool
3381wl_iw_check_conn_fail(wl_event_msg_t *e, char *stringBuf, uint buflen) 3381wl_iw_check_conn_fail(wl_event_msg_t *e, char *stringBuf, uint buflen)
3382{ 3382{
3383 uint32 event = ntoh32(e->event_type); 3383 u32 event = ntoh32(e->event_type);
3384 uint32 status = ntoh32(e->status); 3384 u32 status = ntoh32(e->status);
3385 uint32 reason = ntoh32(e->reason); 3385 u32 reason = ntoh32(e->reason);
3386 3386
3387 if (wl_iw_conn_status_str(event, status, reason, stringBuf, buflen)) { 3387 if (wl_iw_conn_status_str(event, status, reason, stringBuf, buflen)) {
3388 return TRUE; 3388 return TRUE;
@@ -3401,12 +3401,12 @@ void wl_iw_event(struct net_device *dev, wl_event_msg_t *e, void *data)
3401 union iwreq_data wrqu; 3401 union iwreq_data wrqu;
3402 char extra[IW_CUSTOM_MAX + 1]; 3402 char extra[IW_CUSTOM_MAX + 1];
3403 int cmd = 0; 3403 int cmd = 0;
3404 uint32 event_type = ntoh32(e->event_type); 3404 u32 event_type = ntoh32(e->event_type);
3405 u16 flags = ntoh16(e->flags); 3405 u16 flags = ntoh16(e->flags);
3406 uint32 datalen = ntoh32(e->datalen); 3406 u32 datalen = ntoh32(e->datalen);
3407 uint32 status = ntoh32(e->status); 3407 u32 status = ntoh32(e->status);
3408 wl_iw_t *iw; 3408 wl_iw_t *iw;
3409 uint32 toto; 3409 u32 toto;
3410 memset(&wrqu, 0, sizeof(wrqu)); 3410 memset(&wrqu, 0, sizeof(wrqu));
3411 memset(extra, 0, sizeof(extra)); 3411 memset(extra, 0, sizeof(extra));
3412 iw = 0; 3412 iw = 0;
diff --git a/drivers/staging/brcm80211/brcmfmac/wl_iw.h b/drivers/staging/brcm80211/brcmfmac/wl_iw.h
index cca4fd7f9e7..14886578cdd 100644
--- a/drivers/staging/brcm80211/brcmfmac/wl_iw.h
+++ b/drivers/staging/brcm80211/brcmfmac/wl_iw.h
@@ -93,8 +93,8 @@ typedef struct wl_iw {
93 struct iw_statistics wstats; 93 struct iw_statistics wstats;
94 94
95 int spy_num; 95 int spy_num;
96 uint32 pwsec; 96 u32 pwsec;
97 uint32 gwsec; 97 u32 gwsec;
98 bool privacy_invoked; 98 bool privacy_invoked;
99 99
100 struct ether_addr spy_addr[IW_MAX_SPY]; 100 struct ether_addr spy_addr[IW_MAX_SPY];
diff --git a/drivers/staging/brcm80211/include/aidmp.h b/drivers/staging/brcm80211/include/aidmp.h
index e64dd034569..d33f0202cec 100644
--- a/drivers/staging/brcm80211/include/aidmp.h
+++ b/drivers/staging/brcm80211/include/aidmp.h
@@ -103,121 +103,121 @@
103#ifndef _LANGUAGE_ASSEMBLY 103#ifndef _LANGUAGE_ASSEMBLY
104 104
105typedef volatile struct _aidmp { 105typedef volatile struct _aidmp {
106 uint32 oobselina30; /* 0x000 */ 106 u32 oobselina30; /* 0x000 */
107 uint32 oobselina74; /* 0x004 */ 107 u32 oobselina74; /* 0x004 */
108 uint32 PAD[6]; 108 u32 PAD[6];
109 uint32 oobselinb30; /* 0x020 */ 109 u32 oobselinb30; /* 0x020 */
110 uint32 oobselinb74; /* 0x024 */ 110 u32 oobselinb74; /* 0x024 */
111 uint32 PAD[6]; 111 u32 PAD[6];
112 uint32 oobselinc30; /* 0x040 */ 112 u32 oobselinc30; /* 0x040 */
113 uint32 oobselinc74; /* 0x044 */ 113 u32 oobselinc74; /* 0x044 */
114 uint32 PAD[6]; 114 u32 PAD[6];
115 uint32 oobselind30; /* 0x060 */ 115 u32 oobselind30; /* 0x060 */
116 uint32 oobselind74; /* 0x064 */ 116 u32 oobselind74; /* 0x064 */
117 uint32 PAD[38]; 117 u32 PAD[38];
118 uint32 oobselouta30; /* 0x100 */ 118 u32 oobselouta30; /* 0x100 */
119 uint32 oobselouta74; /* 0x104 */ 119 u32 oobselouta74; /* 0x104 */
120 uint32 PAD[6]; 120 u32 PAD[6];
121 uint32 oobseloutb30; /* 0x120 */ 121 u32 oobseloutb30; /* 0x120 */
122 uint32 oobseloutb74; /* 0x124 */ 122 u32 oobseloutb74; /* 0x124 */
123 uint32 PAD[6]; 123 u32 PAD[6];
124 uint32 oobseloutc30; /* 0x140 */ 124 u32 oobseloutc30; /* 0x140 */
125 uint32 oobseloutc74; /* 0x144 */ 125 u32 oobseloutc74; /* 0x144 */
126 uint32 PAD[6]; 126 u32 PAD[6];
127 uint32 oobseloutd30; /* 0x160 */ 127 u32 oobseloutd30; /* 0x160 */
128 uint32 oobseloutd74; /* 0x164 */ 128 u32 oobseloutd74; /* 0x164 */
129 uint32 PAD[38]; 129 u32 PAD[38];
130 uint32 oobsynca; /* 0x200 */ 130 u32 oobsynca; /* 0x200 */
131 uint32 oobseloutaen; /* 0x204 */ 131 u32 oobseloutaen; /* 0x204 */
132 uint32 PAD[6]; 132 u32 PAD[6];
133 uint32 oobsyncb; /* 0x220 */ 133 u32 oobsyncb; /* 0x220 */
134 uint32 oobseloutben; /* 0x224 */ 134 u32 oobseloutben; /* 0x224 */
135 uint32 PAD[6]; 135 u32 PAD[6];
136 uint32 oobsyncc; /* 0x240 */ 136 u32 oobsyncc; /* 0x240 */
137 uint32 oobseloutcen; /* 0x244 */ 137 u32 oobseloutcen; /* 0x244 */
138 uint32 PAD[6]; 138 u32 PAD[6];
139 uint32 oobsyncd; /* 0x260 */ 139 u32 oobsyncd; /* 0x260 */
140 uint32 oobseloutden; /* 0x264 */ 140 u32 oobseloutden; /* 0x264 */
141 uint32 PAD[38]; 141 u32 PAD[38];
142 uint32 oobaextwidth; /* 0x300 */ 142 u32 oobaextwidth; /* 0x300 */
143 uint32 oobainwidth; /* 0x304 */ 143 u32 oobainwidth; /* 0x304 */
144 uint32 oobaoutwidth; /* 0x308 */ 144 u32 oobaoutwidth; /* 0x308 */
145 uint32 PAD[5]; 145 u32 PAD[5];
146 uint32 oobbextwidth; /* 0x320 */ 146 u32 oobbextwidth; /* 0x320 */
147 uint32 oobbinwidth; /* 0x324 */ 147 u32 oobbinwidth; /* 0x324 */
148 uint32 oobboutwidth; /* 0x328 */ 148 u32 oobboutwidth; /* 0x328 */
149 uint32 PAD[5]; 149 u32 PAD[5];
150 uint32 oobcextwidth; /* 0x340 */ 150 u32 oobcextwidth; /* 0x340 */
151 uint32 oobcinwidth; /* 0x344 */ 151 u32 oobcinwidth; /* 0x344 */
152 uint32 oobcoutwidth; /* 0x348 */ 152 u32 oobcoutwidth; /* 0x348 */
153 uint32 PAD[5]; 153 u32 PAD[5];
154 uint32 oobdextwidth; /* 0x360 */ 154 u32 oobdextwidth; /* 0x360 */
155 uint32 oobdinwidth; /* 0x364 */ 155 u32 oobdinwidth; /* 0x364 */
156 uint32 oobdoutwidth; /* 0x368 */ 156 u32 oobdoutwidth; /* 0x368 */
157 uint32 PAD[37]; 157 u32 PAD[37];
158 uint32 ioctrlset; /* 0x400 */ 158 u32 ioctrlset; /* 0x400 */
159 uint32 ioctrlclear; /* 0x404 */ 159 u32 ioctrlclear; /* 0x404 */
160 uint32 ioctrl; /* 0x408 */ 160 u32 ioctrl; /* 0x408 */
161 uint32 PAD[61]; 161 u32 PAD[61];
162 uint32 iostatus; /* 0x500 */ 162 u32 iostatus; /* 0x500 */
163 uint32 PAD[127]; 163 u32 PAD[127];
164 uint32 ioctrlwidth; /* 0x700 */ 164 u32 ioctrlwidth; /* 0x700 */
165 uint32 iostatuswidth; /* 0x704 */ 165 u32 iostatuswidth; /* 0x704 */
166 uint32 PAD[62]; 166 u32 PAD[62];
167 uint32 resetctrl; /* 0x800 */ 167 u32 resetctrl; /* 0x800 */
168 uint32 resetstatus; /* 0x804 */ 168 u32 resetstatus; /* 0x804 */
169 uint32 resetreadid; /* 0x808 */ 169 u32 resetreadid; /* 0x808 */
170 uint32 resetwriteid; /* 0x80c */ 170 u32 resetwriteid; /* 0x80c */
171 uint32 PAD[60]; 171 u32 PAD[60];
172 uint32 errlogctrl; /* 0x900 */ 172 u32 errlogctrl; /* 0x900 */
173 uint32 errlogdone; /* 0x904 */ 173 u32 errlogdone; /* 0x904 */
174 uint32 errlogstatus; /* 0x908 */ 174 u32 errlogstatus; /* 0x908 */
175 uint32 errlogaddrlo; /* 0x90c */ 175 u32 errlogaddrlo; /* 0x90c */
176 uint32 errlogaddrhi; /* 0x910 */ 176 u32 errlogaddrhi; /* 0x910 */
177 uint32 errlogid; /* 0x914 */ 177 u32 errlogid; /* 0x914 */
178 uint32 errloguser; /* 0x918 */ 178 u32 errloguser; /* 0x918 */
179 uint32 errlogflags; /* 0x91c */ 179 u32 errlogflags; /* 0x91c */
180 uint32 PAD[56]; 180 u32 PAD[56];
181 uint32 intstatus; /* 0xa00 */ 181 u32 intstatus; /* 0xa00 */
182 uint32 PAD[127]; 182 u32 PAD[127];
183 uint32 config; /* 0xe00 */ 183 u32 config; /* 0xe00 */
184 uint32 PAD[63]; 184 u32 PAD[63];
185 uint32 itcr; /* 0xf00 */ 185 u32 itcr; /* 0xf00 */
186 uint32 PAD[3]; 186 u32 PAD[3];
187 uint32 itipooba; /* 0xf10 */ 187 u32 itipooba; /* 0xf10 */
188 uint32 itipoobb; /* 0xf14 */ 188 u32 itipoobb; /* 0xf14 */
189 uint32 itipoobc; /* 0xf18 */ 189 u32 itipoobc; /* 0xf18 */
190 uint32 itipoobd; /* 0xf1c */ 190 u32 itipoobd; /* 0xf1c */
191 uint32 PAD[4]; 191 u32 PAD[4];
192 uint32 itipoobaout; /* 0xf30 */ 192 u32 itipoobaout; /* 0xf30 */
193 uint32 itipoobbout; /* 0xf34 */ 193 u32 itipoobbout; /* 0xf34 */
194 uint32 itipoobcout; /* 0xf38 */ 194 u32 itipoobcout; /* 0xf38 */
195 uint32 itipoobdout; /* 0xf3c */ 195 u32 itipoobdout; /* 0xf3c */
196 uint32 PAD[4]; 196 u32 PAD[4];
197 uint32 itopooba; /* 0xf50 */ 197 u32 itopooba; /* 0xf50 */
198 uint32 itopoobb; /* 0xf54 */ 198 u32 itopoobb; /* 0xf54 */
199 uint32 itopoobc; /* 0xf58 */ 199 u32 itopoobc; /* 0xf58 */
200 uint32 itopoobd; /* 0xf5c */ 200 u32 itopoobd; /* 0xf5c */
201 uint32 PAD[4]; 201 u32 PAD[4];
202 uint32 itopoobain; /* 0xf70 */ 202 u32 itopoobain; /* 0xf70 */
203 uint32 itopoobbin; /* 0xf74 */ 203 u32 itopoobbin; /* 0xf74 */
204 uint32 itopoobcin; /* 0xf78 */ 204 u32 itopoobcin; /* 0xf78 */
205 uint32 itopoobdin; /* 0xf7c */ 205 u32 itopoobdin; /* 0xf7c */
206 uint32 PAD[4]; 206 u32 PAD[4];
207 uint32 itopreset; /* 0xf90 */ 207 u32 itopreset; /* 0xf90 */
208 uint32 PAD[15]; 208 u32 PAD[15];
209 uint32 peripherialid4; /* 0xfd0 */ 209 u32 peripherialid4; /* 0xfd0 */
210 uint32 peripherialid5; /* 0xfd4 */ 210 u32 peripherialid5; /* 0xfd4 */
211 uint32 peripherialid6; /* 0xfd8 */ 211 u32 peripherialid6; /* 0xfd8 */
212 uint32 peripherialid7; /* 0xfdc */ 212 u32 peripherialid7; /* 0xfdc */
213 uint32 peripherialid0; /* 0xfe0 */ 213 u32 peripherialid0; /* 0xfe0 */
214 uint32 peripherialid1; /* 0xfe4 */ 214 u32 peripherialid1; /* 0xfe4 */
215 uint32 peripherialid2; /* 0xfe8 */ 215 u32 peripherialid2; /* 0xfe8 */
216 uint32 peripherialid3; /* 0xfec */ 216 u32 peripherialid3; /* 0xfec */
217 uint32 componentid0; /* 0xff0 */ 217 u32 componentid0; /* 0xff0 */
218 uint32 componentid1; /* 0xff4 */ 218 u32 componentid1; /* 0xff4 */
219 uint32 componentid2; /* 0xff8 */ 219 u32 componentid2; /* 0xff8 */
220 uint32 componentid3; /* 0xffc */ 220 u32 componentid3; /* 0xffc */
221} aidmp_t; 221} aidmp_t;
222 222
223#endif /* _LANGUAGE_ASSEMBLY */ 223#endif /* _LANGUAGE_ASSEMBLY */
diff --git a/drivers/staging/brcm80211/include/bcm_rpc.h b/drivers/staging/brcm80211/include/bcm_rpc.h
index 8aa864dcc9c..e1f3cfd77cd 100644
--- a/drivers/staging/brcm80211/include/bcm_rpc.h
+++ b/drivers/staging/brcm80211/include/bcm_rpc.h
@@ -65,7 +65,7 @@ extern uint bcm_rpc_buf_header_len(struct rpc_info *rpci);
65#define RPC_PKTLOG_SIZE 50 /* Depth of the history */ 65#define RPC_PKTLOG_SIZE 50 /* Depth of the history */
66#define RPC_PKTLOG_RD_LEN 3 66#define RPC_PKTLOG_RD_LEN 3
67#define RPC_PKTLOG_DUMP_SIZE 150 /* dump size should be more than the product of above two */ 67#define RPC_PKTLOG_DUMP_SIZE 150 /* dump size should be more than the product of above two */
68extern int bcm_rpc_pktlog_get(struct rpc_info *rpci, uint32 *buf, 68extern int bcm_rpc_pktlog_get(struct rpc_info *rpci, u32 *buf,
69 uint buf_size, bool send); 69 uint buf_size, bool send);
70extern int bcm_rpc_dump(rpc_info_t *rpci, struct bcmstrbuf *b); 70extern int bcm_rpc_dump(rpc_info_t *rpci, struct bcmstrbuf *b);
71 71
diff --git a/drivers/staging/brcm80211/include/bcm_rpc_tp.h b/drivers/staging/brcm80211/include/bcm_rpc_tp.h
index c0cc425d18d..bb8dc6dd6f4 100644
--- a/drivers/staging/brcm80211/include/bcm_rpc_tp.h
+++ b/drivers/staging/brcm80211/include/bcm_rpc_tp.h
@@ -112,7 +112,7 @@ extern void bcm_rpc_tp_txq_wm_get(rpc_tp_info_t *rpc_th, u8 *hiwm,
112 u8 *lowm); 112 u8 *lowm);
113#endif /* WLC_LOW */ 113#endif /* WLC_LOW */
114 114
115extern void bcm_rpc_tp_agg_set(rpc_tp_info_t *rpcb, uint32 reason, bool set); 115extern void bcm_rpc_tp_agg_set(rpc_tp_info_t *rpcb, u32 reason, bool set);
116extern void bcm_rpc_tp_agg_limit_set(rpc_tp_info_t *rpc_th, u8 sf, 116extern void bcm_rpc_tp_agg_limit_set(rpc_tp_info_t *rpc_th, u8 sf,
117 u16 bytes); 117 u16 bytes);
118extern void bcm_rpc_tp_agg_limit_get(rpc_tp_info_t *rpc_th, u8 *sf, 118extern void bcm_rpc_tp_agg_limit_get(rpc_tp_info_t *rpc_th, u8 *sf,
diff --git a/drivers/staging/brcm80211/include/bcm_xdr.h b/drivers/staging/brcm80211/include/bcm_xdr.h
index 749cb198fe0..715f0045ce9 100644
--- a/drivers/staging/brcm80211/include/bcm_xdr.h
+++ b/drivers/staging/brcm80211/include/bcm_xdr.h
@@ -33,8 +33,8 @@ typedef struct {
33 33
34void bcm_xdr_buf_init(bcm_xdr_buf_t *b, void *buf, size_t len); 34void bcm_xdr_buf_init(bcm_xdr_buf_t *b, void *buf, size_t len);
35 35
36int bcm_xdr_pack_uint32(bcm_xdr_buf_t *b, uint32 val); 36int bcm_xdr_pack_u32(bcm_xdr_buf_t *b, u32 val);
37int bcm_xdr_unpack_uint32(bcm_xdr_buf_t *b, uint32 *pval); 37int bcm_xdr_unpack_u32(bcm_xdr_buf_t *b, u32 *pval);
38int bcm_xdr_pack_int32(bcm_xdr_buf_t *b, int32 val); 38int bcm_xdr_pack_int32(bcm_xdr_buf_t *b, int32 val);
39int bcm_xdr_unpack_int32(bcm_xdr_buf_t *b, int32 *pval); 39int bcm_xdr_unpack_int32(bcm_xdr_buf_t *b, int32 *pval);
40int bcm_xdr_pack_s8(bcm_xdr_buf_t *b, s8 val); 40int bcm_xdr_pack_s8(bcm_xdr_buf_t *b, s8 val);
@@ -47,12 +47,12 @@ int bcm_xdr_unpack_opaque_varlen(bcm_xdr_buf_t *b, uint *plen, void **pdata);
47int bcm_xdr_pack_string(bcm_xdr_buf_t *b, char *str); 47int bcm_xdr_pack_string(bcm_xdr_buf_t *b, char *str);
48int bcm_xdr_unpack_string(bcm_xdr_buf_t *b, uint *plen, char **pstr); 48int bcm_xdr_unpack_string(bcm_xdr_buf_t *b, uint *plen, char **pstr);
49 49
50int bcm_xdr_pack_u8_vec(bcm_xdr_buf_t *, u8 *vec, uint32 elems); 50int bcm_xdr_pack_u8_vec(bcm_xdr_buf_t *, u8 *vec, u32 elems);
51int bcm_xdr_unpack_u8_vec(bcm_xdr_buf_t *, u8 *vec, uint32 elems); 51int bcm_xdr_unpack_u8_vec(bcm_xdr_buf_t *, u8 *vec, u32 elems);
52int bcm_xdr_pack_u16_vec(bcm_xdr_buf_t *b, uint len, void *vec); 52int bcm_xdr_pack_u16_vec(bcm_xdr_buf_t *b, uint len, void *vec);
53int bcm_xdr_unpack_u16_vec(bcm_xdr_buf_t *b, uint len, void *vec); 53int bcm_xdr_unpack_u16_vec(bcm_xdr_buf_t *b, uint len, void *vec);
54int bcm_xdr_pack_uint32_vec(bcm_xdr_buf_t *b, uint len, void *vec); 54int bcm_xdr_pack_u32_vec(bcm_xdr_buf_t *b, uint len, void *vec);
55int bcm_xdr_unpack_uint32_vec(bcm_xdr_buf_t *b, uint len, void *vec); 55int bcm_xdr_unpack_u32_vec(bcm_xdr_buf_t *b, uint len, void *vec);
56 56
57int bcm_xdr_pack_opaque_raw(bcm_xdr_buf_t *b, uint len, void *data); 57int bcm_xdr_pack_opaque_raw(bcm_xdr_buf_t *b, uint len, void *data);
58int bcm_xdr_pack_opaque_pad(bcm_xdr_buf_t *b); 58int bcm_xdr_pack_opaque_pad(bcm_xdr_buf_t *b);
diff --git a/drivers/staging/brcm80211/include/bcmcdc.h b/drivers/staging/brcm80211/include/bcmcdc.h
index 2ddcd37c7e0..10c1ddcd5e5 100644
--- a/drivers/staging/brcm80211/include/bcmcdc.h
+++ b/drivers/staging/brcm80211/include/bcmcdc.h
@@ -16,11 +16,11 @@
16#include <proto/ethernet.h> 16#include <proto/ethernet.h>
17 17
18typedef struct cdc_ioctl { 18typedef struct cdc_ioctl {
19 uint32 cmd; /* ioctl command value */ 19 u32 cmd; /* ioctl command value */
20 uint32 len; /* lower 16: output buflen; upper 16: 20 u32 len; /* lower 16: output buflen; upper 16:
21 input buflen (excludes header) */ 21 input buflen (excludes header) */
22 uint32 flags; /* flag defns given below */ 22 u32 flags; /* flag defns given below */
23 uint32 status; /* status code returned from the device */ 23 u32 status; /* status code returned from the device */
24} cdc_ioctl_t; 24} cdc_ioctl_t;
25 25
26/* Max valid buffer size that can be sent to the dongle */ 26/* Max valid buffer size that can be sent to the dongle */
diff --git a/drivers/staging/brcm80211/include/bcmdefs.h b/drivers/staging/brcm80211/include/bcmdefs.h
index 67b36904684..e7b3e97b641 100644
--- a/drivers/staging/brcm80211/include/bcmdefs.h
+++ b/drivers/staging/brcm80211/include/bcmdefs.h
@@ -104,8 +104,8 @@
104 104
105#ifdef BCMDMA64OSL 105#ifdef BCMDMA64OSL
106typedef struct { 106typedef struct {
107 uint32 loaddr; 107 u32 loaddr;
108 uint32 hiaddr; 108 u32 hiaddr;
109} dma64addr_t; 109} dma64addr_t;
110 110
111typedef dma64addr_t dmaaddr_t; 111typedef dma64addr_t dmaaddr_t;
@@ -134,7 +134,7 @@ typedef unsigned long dmaaddr_t;
134/* One physical DMA segment */ 134/* One physical DMA segment */
135typedef struct { 135typedef struct {
136 dmaaddr_t addr; 136 dmaaddr_t addr;
137 uint32 length; 137 u32 length;
138} hnddma_seg_t; 138} hnddma_seg_t;
139 139
140#define MAX_DMA_SEGS 4 140#define MAX_DMA_SEGS 4
diff --git a/drivers/staging/brcm80211/include/bcmendian.h b/drivers/staging/brcm80211/include/bcmendian.h
index 6a9ca37664f..52296fb9fc5 100644
--- a/drivers/staging/brcm80211/include/bcmendian.h
+++ b/drivers/staging/brcm80211/include/bcmendian.h
@@ -26,15 +26,15 @@
26 26
27/* Reverse the bytes in a 32-bit value */ 27/* Reverse the bytes in a 32-bit value */
28#define BCMSWAP32(val) \ 28#define BCMSWAP32(val) \
29 ((uint32)((((uint32)(val) & (uint32)0x000000ffU) << 24) | \ 29 ((u32)((((u32)(val) & (u32)0x000000ffU) << 24) | \
30 (((uint32)(val) & (uint32)0x0000ff00U) << 8) | \ 30 (((u32)(val) & (u32)0x0000ff00U) << 8) | \
31 (((uint32)(val) & (uint32)0x00ff0000U) >> 8) | \ 31 (((u32)(val) & (u32)0x00ff0000U) >> 8) | \
32 (((uint32)(val) & (uint32)0xff000000U) >> 24))) 32 (((u32)(val) & (u32)0xff000000U) >> 24)))
33 33
34/* Reverse the two 16-bit halves of a 32-bit value */ 34/* Reverse the two 16-bit halves of a 32-bit value */
35#define BCMSWAP32BY16(val) \ 35#define BCMSWAP32BY16(val) \
36 ((uint32)((((uint32)(val) & (uint32)0x0000ffffU) << 16) | \ 36 ((u32)((((u32)(val) & (u32)0x0000ffffU) << 16) | \
37 (((uint32)(val) & (uint32)0xffff0000U) >> 16))) 37 (((u32)(val) & (u32)0xffff0000U) >> 16)))
38 38
39/* Byte swapping macros 39/* Byte swapping macros
40 * Host <=> Network (Big Endian) for 16- and 32-bit values 40 * Host <=> Network (Big Endian) for 16- and 32-bit values
@@ -107,13 +107,13 @@
107#define ltoh_ua(ptr) \ 107#define ltoh_ua(ptr) \
108 (sizeof(*(ptr)) == sizeof(u8) ? *(const u8 *)(ptr) : \ 108 (sizeof(*(ptr)) == sizeof(u8) ? *(const u8 *)(ptr) : \
109 sizeof(*(ptr)) == sizeof(u16) ? _LTOH16_UA((const u8 *)(ptr)) : \ 109 sizeof(*(ptr)) == sizeof(u16) ? _LTOH16_UA((const u8 *)(ptr)) : \
110 sizeof(*(ptr)) == sizeof(uint32) ? _LTOH32_UA((const u8 *)(ptr)) : \ 110 sizeof(*(ptr)) == sizeof(u32) ? _LTOH32_UA((const u8 *)(ptr)) : \
111 *(u8 *)0) 111 *(u8 *)0)
112 112
113#define ntoh_ua(ptr) \ 113#define ntoh_ua(ptr) \
114 (sizeof(*(ptr)) == sizeof(u8) ? *(const u8 *)(ptr) : \ 114 (sizeof(*(ptr)) == sizeof(u8) ? *(const u8 *)(ptr) : \
115 sizeof(*(ptr)) == sizeof(u16) ? _NTOH16_UA((const u8 *)(ptr)) : \ 115 sizeof(*(ptr)) == sizeof(u16) ? _NTOH16_UA((const u8 *)(ptr)) : \
116 sizeof(*(ptr)) == sizeof(uint32) ? _NTOH32_UA((const u8 *)(ptr)) : \ 116 sizeof(*(ptr)) == sizeof(u32) ? _NTOH32_UA((const u8 *)(ptr)) : \
117 *(u8 *)0) 117 *(u8 *)0)
118 118
119#ifdef __GNUC__ 119#ifdef __GNUC__
@@ -128,12 +128,12 @@
128}) 128})
129 129
130#define bcmswap32(val) ({ \ 130#define bcmswap32(val) ({ \
131 uint32 _val = (val); \ 131 u32 _val = (val); \
132 BCMSWAP32(_val); \ 132 BCMSWAP32(_val); \
133}) 133})
134 134
135#define bcmswap32by16(val) ({ \ 135#define bcmswap32by16(val) ({ \
136 uint32 _val = (val); \ 136 u32 _val = (val); \
137 BCMSWAP32BY16(_val); \ 137 BCMSWAP32BY16(_val); \
138}) 138})
139 139
@@ -154,7 +154,7 @@
154}) 154})
155 155
156#define htol32_ua_store(val, bytes) ({ \ 156#define htol32_ua_store(val, bytes) ({ \
157 uint32 _val = (val); \ 157 u32 _val = (val); \
158 u8 *_bytes = (u8 *)(bytes); \ 158 u8 *_bytes = (u8 *)(bytes); \
159 _bytes[0] = _val & 0xff; \ 159 _bytes[0] = _val & 0xff; \
160 _bytes[1] = (_val >> 8) & 0xff; \ 160 _bytes[1] = (_val >> 8) & 0xff; \
@@ -170,7 +170,7 @@
170}) 170})
171 171
172#define hton32_ua_store(val, bytes) ({ \ 172#define hton32_ua_store(val, bytes) ({ \
173 uint32 _val = (val); \ 173 u32 _val = (val); \
174 u8 *_bytes = (u8 *)(bytes); \ 174 u8 *_bytes = (u8 *)(bytes); \
175 _bytes[0] = _val >> 24; \ 175 _bytes[0] = _val >> 24; \
176 _bytes[1] = (_val >> 16) & 0xff; \ 176 _bytes[1] = (_val >> 16) & 0xff; \
@@ -206,12 +206,12 @@ static inline u16 bcmswap16(u16 val)
206 return BCMSWAP16(val); 206 return BCMSWAP16(val);
207} 207}
208 208
209static inline uint32 bcmswap32(uint32 val) 209static inline u32 bcmswap32(u32 val)
210{ 210{
211 return BCMSWAP32(val); 211 return BCMSWAP32(val);
212} 212}
213 213
214static inline uint32 bcmswap32by16(uint32 val) 214static inline u32 bcmswap32by16(u32 val)
215{ 215{
216 return BCMSWAP32BY16(val); 216 return BCMSWAP32BY16(val);
217} 217}
@@ -241,7 +241,7 @@ static inline void htol16_ua_store(u16 val, u8 *bytes)
241/* 241/*
242 * Store 32-bit value to unaligned little-endian byte array. 242 * Store 32-bit value to unaligned little-endian byte array.
243 */ 243 */
244static inline void htol32_ua_store(uint32 val, u8 *bytes) 244static inline void htol32_ua_store(u32 val, u8 *bytes)
245{ 245{
246 bytes[0] = val & 0xff; 246 bytes[0] = val & 0xff;
247 bytes[1] = (val >> 8) & 0xff; 247 bytes[1] = (val >> 8) & 0xff;
@@ -261,7 +261,7 @@ static inline void hton16_ua_store(u16 val, u8 *bytes)
261/* 261/*
262 * Store 32-bit value to unaligned network-(big-)endian byte array. 262 * Store 32-bit value to unaligned network-(big-)endian byte array.
263 */ 263 */
264static inline void hton32_ua_store(uint32 val, u8 *bytes) 264static inline void hton32_ua_store(u32 val, u8 *bytes)
265{ 265{
266 bytes[0] = val >> 24; 266 bytes[0] = val >> 24;
267 bytes[1] = (val >> 16) & 0xff; 267 bytes[1] = (val >> 16) & 0xff;
@@ -280,7 +280,7 @@ static inline u16 ltoh16_ua(const void *bytes)
280/* 280/*
281 * Load 32-bit value from unaligned little-endian byte array. 281 * Load 32-bit value from unaligned little-endian byte array.
282 */ 282 */
283static inline uint32 ltoh32_ua(const void *bytes) 283static inline u32 ltoh32_ua(const void *bytes)
284{ 284{
285 return _LTOH32_UA((const u8 *)bytes); 285 return _LTOH32_UA((const u8 *)bytes);
286} 286}
@@ -296,7 +296,7 @@ static inline u16 ntoh16_ua(const void *bytes)
296/* 296/*
297 * Load 32-bit value from unaligned big-(network-)endian byte array. 297 * Load 32-bit value from unaligned big-(network-)endian byte array.
298 */ 298 */
299static inline uint32 ntoh32_ua(const void *bytes) 299static inline u32 ntoh32_ua(const void *bytes)
300{ 300{
301 return _NTOH32_UA((const u8 *)bytes); 301 return _NTOH32_UA((const u8 *)bytes);
302} 302}
diff --git a/drivers/staging/brcm80211/include/bcmnvram.h b/drivers/staging/brcm80211/include/bcmnvram.h
index 93ac2cbf85b..eb64c300491 100644
--- a/drivers/staging/brcm80211/include/bcmnvram.h
+++ b/drivers/staging/brcm80211/include/bcmnvram.h
@@ -23,11 +23,11 @@
23#include <bcmdefs.h> 23#include <bcmdefs.h>
24 24
25struct nvram_header { 25struct nvram_header {
26 uint32 magic; 26 u32 magic;
27 uint32 len; 27 u32 len;
28 uint32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */ 28 u32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
29 uint32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */ 29 u32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
30 uint32 config_ncdl; /* ncdl values for memc */ 30 u32 config_ncdl; /* ncdl values for memc */
31}; 31};
32 32
33struct nvram_tuple { 33struct nvram_tuple {
diff --git a/drivers/staging/brcm80211/include/bcmsdbus.h b/drivers/staging/brcm80211/include/bcmsdbus.h
index 0336400a6d2..ca99495eaa8 100644
--- a/drivers/staging/brcm80211/include/bcmsdbus.h
+++ b/drivers/staging/brcm80211/include/bcmsdbus.h
@@ -72,22 +72,22 @@ extern SDIOH_API_RC sdioh_request_byte(sdioh_info_t *si, uint rw, uint fnc,
72/* read or write 2/4 bytes using cmd53 */ 72/* read or write 2/4 bytes using cmd53 */
73extern SDIOH_API_RC sdioh_request_word(sdioh_info_t *si, uint cmd_type, 73extern SDIOH_API_RC sdioh_request_word(sdioh_info_t *si, uint cmd_type,
74 uint rw, uint fnc, uint addr, 74 uint rw, uint fnc, uint addr,
75 uint32 *word, uint nbyte); 75 u32 *word, uint nbyte);
76 76
77/* read or write any buffer using cmd53 */ 77/* read or write any buffer using cmd53 */
78extern SDIOH_API_RC sdioh_request_buffer(sdioh_info_t *si, uint pio_dma, 78extern SDIOH_API_RC sdioh_request_buffer(sdioh_info_t *si, uint pio_dma,
79 uint fix_inc, uint rw, uint fnc_num, 79 uint fix_inc, uint rw, uint fnc_num,
80 uint32 addr, uint regwidth, 80 u32 addr, uint regwidth,
81 uint32 buflen, u8 *buffer, 81 u32 buflen, u8 *buffer,
82 void *pkt); 82 void *pkt);
83 83
84/* get cis data */ 84/* get cis data */
85extern SDIOH_API_RC sdioh_cis_read(sdioh_info_t *si, uint fuc, u8 *cis, 85extern SDIOH_API_RC sdioh_cis_read(sdioh_info_t *si, uint fuc, u8 *cis,
86 uint32 length); 86 u32 length);
87 87
88extern SDIOH_API_RC sdioh_cfg_read(sdioh_info_t *si, uint fuc, uint32 addr, 88extern SDIOH_API_RC sdioh_cfg_read(sdioh_info_t *si, uint fuc, u32 addr,
89 u8 *data); 89 u8 *data);
90extern SDIOH_API_RC sdioh_cfg_write(sdioh_info_t *si, uint fuc, uint32 addr, 90extern SDIOH_API_RC sdioh_cfg_write(sdioh_info_t *si, uint fuc, u32 addr,
91 u8 *data); 91 u8 *data);
92 92
93/* query number of io functions */ 93/* query number of io functions */
diff --git a/drivers/staging/brcm80211/include/bcmsdh.h b/drivers/staging/brcm80211/include/bcmsdh.h
index a43f9cd0888..6b80983d43c 100644
--- a/drivers/staging/brcm80211/include/bcmsdh.h
+++ b/drivers/staging/brcm80211/include/bcmsdh.h
@@ -75,15 +75,15 @@ extern int bcmsdh_devremove_reg(void *sdh, bcmsdh_cb_fn_t fn, void *argh);
75 * data: data byte to write 75 * data: data byte to write
76 * err: pointer to error code (or NULL) 76 * err: pointer to error code (or NULL)
77 */ 77 */
78extern u8 bcmsdh_cfg_read(void *sdh, uint func, uint32 addr, int *err); 78extern u8 bcmsdh_cfg_read(void *sdh, uint func, u32 addr, int *err);
79extern void bcmsdh_cfg_write(void *sdh, uint func, uint32 addr, u8 data, 79extern void bcmsdh_cfg_write(void *sdh, uint func, u32 addr, u8 data,
80 int *err); 80 int *err);
81 81
82/* Read/Write 4bytes from/to cfg space */ 82/* Read/Write 4bytes from/to cfg space */
83extern uint32 bcmsdh_cfg_read_word(void *sdh, uint fnc_num, uint32 addr, 83extern u32 bcmsdh_cfg_read_word(void *sdh, uint fnc_num, u32 addr,
84 int *err); 84 int *err);
85extern void bcmsdh_cfg_write_word(void *sdh, uint fnc_num, uint32 addr, 85extern void bcmsdh_cfg_write_word(void *sdh, uint fnc_num, u32 addr,
86 uint32 data, int *err); 86 u32 data, int *err);
87 87
88/* Read CIS content for specified function. 88/* Read CIS content for specified function.
89 * fn: function whose CIS is being requested (0 is common CIS) 89 * fn: function whose CIS is being requested (0 is common CIS)
@@ -99,8 +99,8 @@ extern int bcmsdh_cis_read(void *sdh, uint func, u8 *cis, uint length);
99 * size: register width in bytes (2 or 4) 99 * size: register width in bytes (2 or 4)
100 * data: data for register write 100 * data: data for register write
101 */ 101 */
102extern uint32 bcmsdh_reg_read(void *sdh, uint32 addr, uint size); 102extern u32 bcmsdh_reg_read(void *sdh, u32 addr, uint size);
103extern uint32 bcmsdh_reg_write(void *sdh, uint32 addr, uint size, uint32 data); 103extern u32 bcmsdh_reg_write(void *sdh, u32 addr, uint size, u32 data);
104 104
105/* Indicate if last reg read/write failed */ 105/* Indicate if last reg read/write failed */
106extern bool bcmsdh_regfail(void *sdh); 106extern bool bcmsdh_regfail(void *sdh);
@@ -118,10 +118,10 @@ extern bool bcmsdh_regfail(void *sdh);
118 * NOTE: Async operation is not currently supported. 118 * NOTE: Async operation is not currently supported.
119 */ 119 */
120typedef void (*bcmsdh_cmplt_fn_t) (void *handle, int status, bool sync_waiting); 120typedef void (*bcmsdh_cmplt_fn_t) (void *handle, int status, bool sync_waiting);
121extern int bcmsdh_send_buf(void *sdh, uint32 addr, uint fn, uint flags, 121extern int bcmsdh_send_buf(void *sdh, u32 addr, uint fn, uint flags,
122 u8 *buf, uint nbytes, void *pkt, 122 u8 *buf, uint nbytes, void *pkt,
123 bcmsdh_cmplt_fn_t complete, void *handle); 123 bcmsdh_cmplt_fn_t complete, void *handle);
124extern int bcmsdh_recv_buf(void *sdh, uint32 addr, uint fn, uint flags, 124extern int bcmsdh_recv_buf(void *sdh, u32 addr, uint fn, uint flags,
125 u8 *buf, uint nbytes, void *pkt, 125 u8 *buf, uint nbytes, void *pkt,
126 bcmsdh_cmplt_fn_t complete, void *handle); 126 bcmsdh_cmplt_fn_t complete, void *handle);
127 127
@@ -140,7 +140,7 @@ extern int bcmsdh_recv_buf(void *sdh, uint32 addr, uint fn, uint flags,
140 * nbytes: number of bytes to transfer to/from buf 140 * nbytes: number of bytes to transfer to/from buf
141 * Returns 0 or error code. 141 * Returns 0 or error code.
142 */ 142 */
143extern int bcmsdh_rwdata(void *sdh, uint rw, uint32 addr, u8 *buf, 143extern int bcmsdh_rwdata(void *sdh, uint rw, u32 addr, u8 *buf,
144 uint nbytes); 144 uint nbytes);
145 145
146/* Issue an abort to the specified function */ 146/* Issue an abort to the specified function */
@@ -187,12 +187,12 @@ extern bool bcmsdh_chipmatch(u16 vendor, u16 device);
187extern void bcmsdh_device_remove(void *sdh); 187extern void bcmsdh_device_remove(void *sdh);
188 188
189/* Function to pass device-status bits to DHD. */ 189/* Function to pass device-status bits to DHD. */
190extern uint32 bcmsdh_get_dstatus(void *sdh); 190extern u32 bcmsdh_get_dstatus(void *sdh);
191 191
192/* Function to return current window addr */ 192/* Function to return current window addr */
193extern uint32 bcmsdh_cur_sbwad(void *sdh); 193extern u32 bcmsdh_cur_sbwad(void *sdh);
194 194
195/* Function to pass chipid and rev to lower layers for controlling pr's */ 195/* Function to pass chipid and rev to lower layers for controlling pr's */
196extern void bcmsdh_chipinfo(void *sdh, uint32 chip, uint32 chiprev); 196extern void bcmsdh_chipinfo(void *sdh, u32 chip, u32 chiprev);
197 197
198#endif /* _bcmsdh_h_ */ 198#endif /* _bcmsdh_h_ */
diff --git a/drivers/staging/brcm80211/include/bcmsdh_sdmmc.h b/drivers/staging/brcm80211/include/bcmsdh_sdmmc.h
index 7f237004e6a..7c232e55dfe 100644
--- a/drivers/staging/brcm80211/include/bcmsdh_sdmmc.h
+++ b/drivers/staging/brcm80211/include/bcmsdh_sdmmc.h
@@ -68,8 +68,8 @@ struct sdioh_info {
68 int sd_mode; /* SD1/SD4/SPI */ 68 int sd_mode; /* SD1/SD4/SPI */
69 int client_block_size[SDIOD_MAX_IOFUNCS]; /* Blocksize */ 69 int client_block_size[SDIOD_MAX_IOFUNCS]; /* Blocksize */
70 u8 num_funcs; /* Supported funcs on client */ 70 u8 num_funcs; /* Supported funcs on client */
71 uint32 com_cis_ptr; 71 u32 com_cis_ptr;
72 uint32 func_cis_ptr[SDIOD_MAX_IOFUNCS]; 72 u32 func_cis_ptr[SDIOD_MAX_IOFUNCS];
73 uint max_dma_len; 73 uint max_dma_len;
74 uint max_dma_descriptors; /* DMA Descriptors supported by this controller. */ 74 uint max_dma_descriptors; /* DMA Descriptors supported by this controller. */
75 /* SDDMA_DESCRIPTOR SGList[32]; *//* Scatter/Gather DMA List */ 75 /* SDDMA_DESCRIPTOR SGList[32]; *//* Scatter/Gather DMA List */
@@ -94,7 +94,7 @@ extern void sdioh_sdmmc_devintr_off(sdioh_info_t *sd);
94 */ 94 */
95 95
96/* Register mapping routines */ 96/* Register mapping routines */
97extern uint32 *sdioh_sdmmc_reg_map(osl_t *osh, int32 addr, int size); 97extern u32 *sdioh_sdmmc_reg_map(osl_t *osh, int32 addr, int size);
98extern void sdioh_sdmmc_reg_unmap(osl_t *osh, int32 addr, int size); 98extern void sdioh_sdmmc_reg_unmap(osl_t *osh, int32 addr, int size);
99 99
100/* Interrupt (de)registration routines */ 100/* Interrupt (de)registration routines */
@@ -104,7 +104,7 @@ extern void sdioh_sdmmc_free_irq(uint irq, sdioh_info_t *sd);
104typedef struct _BCMSDH_SDMMC_INSTANCE { 104typedef struct _BCMSDH_SDMMC_INSTANCE {
105 sdioh_info_t *sd; 105 sdioh_info_t *sd;
106 struct sdio_func *func[SDIOD_MAX_IOFUNCS]; 106 struct sdio_func *func[SDIOD_MAX_IOFUNCS];
107 uint32 host_claimed; 107 u32 host_claimed;
108} BCMSDH_SDMMC_INSTANCE, *PBCMSDH_SDMMC_INSTANCE; 108} BCMSDH_SDMMC_INSTANCE, *PBCMSDH_SDMMC_INSTANCE;
109 109
110#endif /* __BCMSDH_SDMMC_H__ */ 110#endif /* __BCMSDH_SDMMC_H__ */
diff --git a/drivers/staging/brcm80211/include/bcmsdpcm.h b/drivers/staging/brcm80211/include/bcmsdpcm.h
index 117cd1f5969..ab5945a68b9 100644
--- a/drivers/staging/brcm80211/include/bcmsdpcm.h
+++ b/drivers/staging/brcm80211/include/bcmsdpcm.h
@@ -153,33 +153,33 @@
153 */ 153 */
154 154
155typedef volatile struct { 155typedef volatile struct {
156 uint32 cmd52rd; /* Cmd52RdCount, SDIO: cmd52 reads */ 156 u32 cmd52rd; /* Cmd52RdCount, SDIO: cmd52 reads */
157 uint32 cmd52wr; /* Cmd52WrCount, SDIO: cmd52 writes */ 157 u32 cmd52wr; /* Cmd52WrCount, SDIO: cmd52 writes */
158 uint32 cmd53rd; /* Cmd53RdCount, SDIO: cmd53 reads */ 158 u32 cmd53rd; /* Cmd53RdCount, SDIO: cmd53 reads */
159 uint32 cmd53wr; /* Cmd53WrCount, SDIO: cmd53 writes */ 159 u32 cmd53wr; /* Cmd53WrCount, SDIO: cmd53 writes */
160 uint32 abort; /* AbortCount, SDIO: aborts */ 160 u32 abort; /* AbortCount, SDIO: aborts */
161 uint32 datacrcerror; /* DataCrcErrorCount, SDIO: frames w/CRC error */ 161 u32 datacrcerror; /* DataCrcErrorCount, SDIO: frames w/CRC error */
162 uint32 rdoutofsync; /* RdOutOfSyncCount, SDIO/PCMCIA: Rd Frm out of sync */ 162 u32 rdoutofsync; /* RdOutOfSyncCount, SDIO/PCMCIA: Rd Frm out of sync */
163 uint32 wroutofsync; /* RdOutOfSyncCount, SDIO/PCMCIA: Wr Frm out of sync */ 163 u32 wroutofsync; /* RdOutOfSyncCount, SDIO/PCMCIA: Wr Frm out of sync */
164 uint32 writebusy; /* WriteBusyCount, SDIO: device asserted "busy" */ 164 u32 writebusy; /* WriteBusyCount, SDIO: device asserted "busy" */
165 uint32 readwait; /* ReadWaitCount, SDIO: no data ready for a read cmd */ 165 u32 readwait; /* ReadWaitCount, SDIO: no data ready for a read cmd */
166 uint32 readterm; /* ReadTermCount, SDIO: read frame termination cmds */ 166 u32 readterm; /* ReadTermCount, SDIO: read frame termination cmds */
167 uint32 writeterm; /* WriteTermCount, SDIO: write frames termination cmds */ 167 u32 writeterm; /* WriteTermCount, SDIO: write frames termination cmds */
168 uint32 rxdescuflo; /* receive descriptor underflows */ 168 u32 rxdescuflo; /* receive descriptor underflows */
169 uint32 rxfifooflo; /* receive fifo overflows */ 169 u32 rxfifooflo; /* receive fifo overflows */
170 uint32 txfifouflo; /* transmit fifo underflows */ 170 u32 txfifouflo; /* transmit fifo underflows */
171 uint32 runt; /* runt (too short) frames recv'd from bus */ 171 u32 runt; /* runt (too short) frames recv'd from bus */
172 uint32 badlen; /* frame's rxh len does not match its hw tag len */ 172 u32 badlen; /* frame's rxh len does not match its hw tag len */
173 uint32 badcksum; /* frame's hw tag chksum doesn't agree with len value */ 173 u32 badcksum; /* frame's hw tag chksum doesn't agree with len value */
174 uint32 seqbreak; /* break in sequence # space from one rx frame to the next */ 174 u32 seqbreak; /* break in sequence # space from one rx frame to the next */
175 uint32 rxfcrc; /* frame rx header indicates crc error */ 175 u32 rxfcrc; /* frame rx header indicates crc error */
176 uint32 rxfwoos; /* frame rx header indicates write out of sync */ 176 u32 rxfwoos; /* frame rx header indicates write out of sync */
177 uint32 rxfwft; /* frame rx header indicates write frame termination */ 177 u32 rxfwft; /* frame rx header indicates write frame termination */
178 uint32 rxfabort; /* frame rx header indicates frame aborted */ 178 u32 rxfabort; /* frame rx header indicates frame aborted */
179 uint32 woosint; /* write out of sync interrupt */ 179 u32 woosint; /* write out of sync interrupt */
180 uint32 roosint; /* read out of sync interrupt */ 180 u32 roosint; /* read out of sync interrupt */
181 uint32 rftermint; /* read frame terminate interrupt */ 181 u32 rftermint; /* read frame terminate interrupt */
182 uint32 wftermint; /* write frame terminate interrupt */ 182 u32 wftermint; /* write frame terminate interrupt */
183} sdpcmd_cnt_t; 183} sdpcmd_cnt_t;
184 184
185/* 185/*
@@ -241,13 +241,13 @@ typedef volatile struct {
241#define SDPCM_SHARED_TRAP 0x0400 241#define SDPCM_SHARED_TRAP 0x0400
242 242
243typedef struct { 243typedef struct {
244 uint32 flags; 244 u32 flags;
245 uint32 trap_addr; 245 u32 trap_addr;
246 uint32 assert_exp_addr; 246 u32 assert_exp_addr;
247 uint32 assert_file_addr; 247 u32 assert_file_addr;
248 uint32 assert_line; 248 u32 assert_line;
249 uint32 console_addr; /* Address of hndrte_cons_t */ 249 u32 console_addr; /* Address of hndrte_cons_t */
250 uint32 msgtrace_addr; 250 u32 msgtrace_addr;
251} sdpcm_shared_t; 251} sdpcm_shared_t;
252 252
253extern sdpcm_shared_t sdpcm_shared; 253extern sdpcm_shared_t sdpcm_shared;
diff --git a/drivers/staging/brcm80211/include/bcmsrom_tbl.h b/drivers/staging/brcm80211/include/bcmsrom_tbl.h
index eea3085bc01..22ae7c1c18f 100644
--- a/drivers/staging/brcm80211/include/bcmsrom_tbl.h
+++ b/drivers/staging/brcm80211/include/bcmsrom_tbl.h
@@ -22,8 +22,8 @@
22 22
23typedef struct { 23typedef struct {
24 const char *name; 24 const char *name;
25 uint32 revmask; 25 u32 revmask;
26 uint32 flags; 26 u32 flags;
27 u16 off; 27 u16 off;
28 u16 mask; 28 u16 mask;
29} sromvar_t; 29} sromvar_t;
diff --git a/drivers/staging/brcm80211/include/bcmutils.h b/drivers/staging/brcm80211/include/bcmutils.h
index c7e8b3a2143..abc6262682c 100644
--- a/drivers/staging/brcm80211/include/bcmutils.h
+++ b/drivers/staging/brcm80211/include/bcmutils.h
@@ -327,7 +327,7 @@ extern "C" {
327 "s16", \ 327 "s16", \
328 "u16", \ 328 "u16", \
329 "int32", \ 329 "int32", \
330 "uint32", \ 330 "u32", \
331 "buffer", \ 331 "buffer", \
332 "" } 332 "" }
333 333
@@ -517,7 +517,7 @@ extern "C" {
517 517
518/* bcm_format_flags() bit description structure */ 518/* bcm_format_flags() bit description structure */
519 typedef struct bcm_bit_desc { 519 typedef struct bcm_bit_desc {
520 uint32 bit; 520 u32 bit;
521 const char *name; 521 const char *name;
522 } bcm_bit_desc_t; 522 } bcm_bit_desc_t;
523 523
@@ -546,17 +546,17 @@ extern "C" {
546 3) == 0) { 546 3) == 0) {
547 /* ARM CM3 rel time: 1229 (727 if alignment check could be omitted) */ 547 /* ARM CM3 rel time: 1229 (727 if alignment check could be omitted) */
548 /* x86 supports unaligned. This version runs 6x-9x faster on x86. */ 548 /* x86 supports unaligned. This version runs 6x-9x faster on x86. */
549 ((uint32 *) dst)[0] = 549 ((u32 *) dst)[0] =
550 ((const uint32 *)src1)[0] ^ ((const uint32 *) 550 ((const u32 *)src1)[0] ^ ((const u32 *)
551 src2)[0]; 551 src2)[0];
552 ((uint32 *) dst)[1] = 552 ((u32 *) dst)[1] =
553 ((const uint32 *)src1)[1] ^ ((const uint32 *) 553 ((const u32 *)src1)[1] ^ ((const u32 *)
554 src2)[1]; 554 src2)[1];
555 ((uint32 *) dst)[2] = 555 ((u32 *) dst)[2] =
556 ((const uint32 *)src1)[2] ^ ((const uint32 *) 556 ((const u32 *)src1)[2] ^ ((const u32 *)
557 src2)[2]; 557 src2)[2];
558 ((uint32 *) dst)[3] = 558 ((u32 *) dst)[3] =
559 ((const uint32 *)src1)[3] ^ ((const uint32 *) 559 ((const u32 *)src1)[3] ^ ((const u32 *)
560 src2)[3]; 560 src2)[3];
561 } else { 561 } else {
562 /* ARM CM3 rel time: 4668 (4191 if alignment check could be omitted) */ 562 /* ARM CM3 rel time: 4668 (4191 if alignment check could be omitted) */
@@ -572,7 +572,7 @@ extern "C" {
572 extern u16 BCMROMFN(hndcrc16) (u8 *p, uint nbytes, u16 crc); 572 extern u16 BCMROMFN(hndcrc16) (u8 *p, uint nbytes, u16 crc);
573/* format/print */ 573/* format/print */
574#if defined(BCMDBG) 574#if defined(BCMDBG)
575 extern int bcm_format_flags(const bcm_bit_desc_t *bd, uint32 flags, 575 extern int bcm_format_flags(const bcm_bit_desc_t *bd, u32 flags,
576 char *buf, int len); 576 char *buf, int len);
577 extern int bcm_format_hex(char *str, const void *bytes, int len); 577 extern int bcm_format_hex(char *str, const void *bytes, int len);
578#endif 578#endif
@@ -584,7 +584,7 @@ extern "C" {
584#endif /* BRCM_FULLMAC */ 584#endif /* BRCM_FULLMAC */
585 extern char *bcm_chipname(uint chipid, char *buf, uint len); 585 extern char *bcm_chipname(uint chipid, char *buf, uint len);
586#ifdef BRCM_FULLMAC 586#ifdef BRCM_FULLMAC
587 extern char *bcm_brev_str(uint32 brev, char *buf); 587 extern char *bcm_brev_str(u32 brev, char *buf);
588 extern void printbig(char *buf); 588 extern void printbig(char *buf);
589#endif /* BRCM_FULLMAC */ 589#endif /* BRCM_FULLMAC */
590 extern void prhex(const char *msg, unsigned char *buf, uint len); 590 extern void prhex(const char *msg, unsigned char *buf, uint len);
@@ -604,7 +604,7 @@ extern "C" {
604#endif 604#endif
605 605
606/* multi-bool data type: set of bools, mbool is true if any is set */ 606/* multi-bool data type: set of bools, mbool is true if any is set */
607 typedef uint32 mbool; 607 typedef u32 mbool;
608#define mboolset(mb, bit) ((mb) |= (bit)) /* set one bool */ 608#define mboolset(mb, bit) ((mb) |= (bit)) /* set one bool */
609#define mboolclr(mb, bit) ((mb) &= ~(bit)) /* clear one bool */ 609#define mboolclr(mb, bit) ((mb) &= ~(bit)) /* clear one bool */
610#define mboolisset(mb, bit) (((mb) & (bit)) != 0) /* TRUE if one bool is set */ 610#define mboolisset(mb, bit) (((mb) & (bit)) != 0) /* TRUE if one bool is set */
@@ -619,8 +619,8 @@ extern "C" {
619/* generic datastruct to help dump routines */ 619/* generic datastruct to help dump routines */
620 struct fielddesc { 620 struct fielddesc {
621 const char *nameandfmt; 621 const char *nameandfmt;
622 uint32 offset; 622 u32 offset;
623 uint32 len; 623 u32 len;
624 }; 624 };
625 625
626#ifdef BRCM_FULLMAC 626#ifdef BRCM_FULLMAC
@@ -631,12 +631,12 @@ extern "C" {
631 extern void bcm_print_bytes(char *name, const unsigned char *cdata, int len); 631 extern void bcm_print_bytes(char *name, const unsigned char *cdata, int len);
632#endif 632#endif
633 633
634 typedef uint32(*bcmutl_rdreg_rtn) (void *arg0, uint arg1, 634 typedef u32(*bcmutl_rdreg_rtn) (void *arg0, uint arg1,
635 uint32 offset); 635 u32 offset);
636#ifdef BRCM_FULLMAC 636#ifdef BRCM_FULLMAC
637 extern uint bcmdumpfields(bcmutl_rdreg_rtn func_ptr, void *arg0, 637 extern uint bcmdumpfields(bcmutl_rdreg_rtn func_ptr, void *arg0,
638 uint arg1, struct fielddesc *str, char *buf, 638 uint arg1, struct fielddesc *str, char *buf,
639 uint32 bufsize); 639 u32 bufsize);
640 640
641 extern uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf, 641 extern uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf,
642 uint len); 642 uint len);
diff --git a/drivers/staging/brcm80211/include/d11.h b/drivers/staging/brcm80211/include/d11.h
index b2f2afc151b..5789e0828eb 100644
--- a/drivers/staging/brcm80211/include/d11.h
+++ b/drivers/staging/brcm80211/include/d11.h
@@ -65,15 +65,15 @@
65#define TX_CTL_FIFO TX_AC_VO_FIFO 65#define TX_CTL_FIFO TX_AC_VO_FIFO
66 66
67typedef volatile struct { 67typedef volatile struct {
68 uint32 intstatus; 68 u32 intstatus;
69 uint32 intmask; 69 u32 intmask;
70} intctrlregs_t; 70} intctrlregs_t;
71 71
72/* read: 32-bit register that can be read as 32-bit or as 2 16-bit 72/* read: 32-bit register that can be read as 32-bit or as 2 16-bit
73 * write: only low 16b-it half can be written 73 * write: only low 16b-it half can be written
74 */ 74 */
75typedef volatile union { 75typedef volatile union {
76 uint32 pmqhostdata; /* read only! */ 76 u32 pmqhostdata; /* read only! */
77 struct { 77 struct {
78 u16 pmqctrlstatus; /* read/write */ 78 u16 pmqctrlstatus; /* read/write */
79 u16 PAD; 79 u16 PAD;
@@ -107,74 +107,74 @@ typedef volatile struct {
107 */ 107 */
108typedef volatile struct _d11regs { 108typedef volatile struct _d11regs {
109 /* Device Control ("semi-standard host registers") */ 109 /* Device Control ("semi-standard host registers") */
110 uint32 PAD[3]; /* 0x0 - 0x8 */ 110 u32 PAD[3]; /* 0x0 - 0x8 */
111 uint32 biststatus; /* 0xC */ 111 u32 biststatus; /* 0xC */
112 uint32 biststatus2; /* 0x10 */ 112 u32 biststatus2; /* 0x10 */
113 uint32 PAD; /* 0x14 */ 113 u32 PAD; /* 0x14 */
114 uint32 gptimer; /* 0x18 *//* for corerev >= 3 */ 114 u32 gptimer; /* 0x18 *//* for corerev >= 3 */
115 uint32 usectimer; /* 0x1c *//* for corerev >= 26 */ 115 u32 usectimer; /* 0x1c *//* for corerev >= 26 */
116 116
117 /* Interrupt Control *//* 0x20 */ 117 /* Interrupt Control *//* 0x20 */
118 intctrlregs_t intctrlregs[8]; 118 intctrlregs_t intctrlregs[8];
119 119
120 uint32 PAD[40]; /* 0x60 - 0xFC */ 120 u32 PAD[40]; /* 0x60 - 0xFC */
121 121
122 /* tx fifos 6-7 and rx fifos 1-3 removed in corerev 5 */ 122 /* tx fifos 6-7 and rx fifos 1-3 removed in corerev 5 */
123 uint32 intrcvlazy[4]; /* 0x100 - 0x10C */ 123 u32 intrcvlazy[4]; /* 0x100 - 0x10C */
124 124
125 uint32 PAD[4]; /* 0x110 - 0x11c */ 125 u32 PAD[4]; /* 0x110 - 0x11c */
126 126
127 uint32 maccontrol; /* 0x120 */ 127 u32 maccontrol; /* 0x120 */
128 uint32 maccommand; /* 0x124 */ 128 u32 maccommand; /* 0x124 */
129 uint32 macintstatus; /* 0x128 */ 129 u32 macintstatus; /* 0x128 */
130 uint32 macintmask; /* 0x12C */ 130 u32 macintmask; /* 0x12C */
131 131
132 /* Transmit Template Access */ 132 /* Transmit Template Access */
133 uint32 tplatewrptr; /* 0x130 */ 133 u32 tplatewrptr; /* 0x130 */
134 uint32 tplatewrdata; /* 0x134 */ 134 u32 tplatewrdata; /* 0x134 */
135 uint32 PAD[2]; /* 0x138 - 0x13C */ 135 u32 PAD[2]; /* 0x138 - 0x13C */
136 136
137 /* PMQ registers */ 137 /* PMQ registers */
138 pmqreg_t pmqreg; /* 0x140 */ 138 pmqreg_t pmqreg; /* 0x140 */
139 uint32 pmqpatl; /* 0x144 */ 139 u32 pmqpatl; /* 0x144 */
140 uint32 pmqpath; /* 0x148 */ 140 u32 pmqpath; /* 0x148 */
141 uint32 PAD; /* 0x14C */ 141 u32 PAD; /* 0x14C */
142 142
143 uint32 chnstatus; /* 0x150 */ 143 u32 chnstatus; /* 0x150 */
144 uint32 psmdebug; /* 0x154 *//* for corerev >= 3 */ 144 u32 psmdebug; /* 0x154 *//* for corerev >= 3 */
145 uint32 phydebug; /* 0x158 *//* for corerev >= 3 */ 145 u32 phydebug; /* 0x158 *//* for corerev >= 3 */
146 uint32 machwcap; /* 0x15C *//* Corerev >= 13 */ 146 u32 machwcap; /* 0x15C *//* Corerev >= 13 */
147 147
148 /* Extended Internal Objects */ 148 /* Extended Internal Objects */
149 uint32 objaddr; /* 0x160 */ 149 u32 objaddr; /* 0x160 */
150 uint32 objdata; /* 0x164 */ 150 u32 objdata; /* 0x164 */
151 uint32 PAD[2]; /* 0x168 - 0x16c */ 151 u32 PAD[2]; /* 0x168 - 0x16c */
152 152
153 /* New txstatus registers on corerev >= 5 */ 153 /* New txstatus registers on corerev >= 5 */
154 uint32 frmtxstatus; /* 0x170 */ 154 u32 frmtxstatus; /* 0x170 */
155 uint32 frmtxstatus2; /* 0x174 */ 155 u32 frmtxstatus2; /* 0x174 */
156 uint32 PAD[2]; /* 0x178 - 0x17c */ 156 u32 PAD[2]; /* 0x178 - 0x17c */
157 157
158 /* New TSF host access on corerev >= 3 */ 158 /* New TSF host access on corerev >= 3 */
159 159
160 uint32 tsf_timerlow; /* 0x180 */ 160 u32 tsf_timerlow; /* 0x180 */
161 uint32 tsf_timerhigh; /* 0x184 */ 161 u32 tsf_timerhigh; /* 0x184 */
162 uint32 tsf_cfprep; /* 0x188 */ 162 u32 tsf_cfprep; /* 0x188 */
163 uint32 tsf_cfpstart; /* 0x18c */ 163 u32 tsf_cfpstart; /* 0x18c */
164 uint32 tsf_cfpmaxdur32; /* 0x190 */ 164 u32 tsf_cfpmaxdur32; /* 0x190 */
165 uint32 PAD[3]; /* 0x194 - 0x19c */ 165 u32 PAD[3]; /* 0x194 - 0x19c */
166 166
167 uint32 maccontrol1; /* 0x1a0 */ 167 u32 maccontrol1; /* 0x1a0 */
168 uint32 machwcap1; /* 0x1a4 */ 168 u32 machwcap1; /* 0x1a4 */
169 uint32 PAD[14]; /* 0x1a8 - 0x1dc */ 169 u32 PAD[14]; /* 0x1a8 - 0x1dc */
170 170
171 /* Clock control and hardware workarounds (corerev >= 13) */ 171 /* Clock control and hardware workarounds (corerev >= 13) */
172 uint32 clk_ctl_st; /* 0x1e0 */ 172 u32 clk_ctl_st; /* 0x1e0 */
173 uint32 hw_war; 173 u32 hw_war;
174 uint32 d11_phypllctl; /* 0x1e8 (corerev == 16), the phypll request/avail bits are 174 u32 d11_phypllctl; /* 0x1e8 (corerev == 16), the phypll request/avail bits are
175 * moved to clk_ctl_st for corerev >= 17 175 * moved to clk_ctl_st for corerev >= 17
176 */ 176 */
177 uint32 PAD[5]; /* 0x1ec - 0x1fc */ 177 u32 PAD[5]; /* 0x1ec - 0x1fc */
178 178
179 /* 0x200-0x37F dma/pio registers */ 179 /* 0x200-0x37F dma/pio registers */
180 volatile union { 180 volatile union {
@@ -185,14 +185,14 @@ typedef volatile struct _d11regs {
185 /* FIFO diagnostic port access */ 185 /* FIFO diagnostic port access */
186 dma32diag_t dmafifo; /* 0x380 - 0x38C */ 186 dma32diag_t dmafifo; /* 0x380 - 0x38C */
187 187
188 uint32 aggfifocnt; /* 0x390 */ 188 u32 aggfifocnt; /* 0x390 */
189 uint32 aggfifodata; /* 0x394 */ 189 u32 aggfifodata; /* 0x394 */
190 uint32 PAD[16]; /* 0x398 - 0x3d4 */ 190 u32 PAD[16]; /* 0x398 - 0x3d4 */
191 u16 radioregaddr; /* 0x3d8 */ 191 u16 radioregaddr; /* 0x3d8 */
192 u16 radioregdata; /* 0x3da */ 192 u16 radioregdata; /* 0x3da */
193 193
194 /* time delay between the change on rf disable input and radio shutdown corerev 10 */ 194 /* time delay between the change on rf disable input and radio shutdown corerev 10 */
195 uint32 rfdisabledly; /* 0x3DC */ 195 u32 rfdisabledly; /* 0x3DC */
196 196
197 /* PHY register access */ 197 /* PHY register access */
198 u16 phyversion; /* 0x3e0 - 0x0 */ 198 u16 phyversion; /* 0x3e0 - 0x0 */
@@ -640,7 +640,7 @@ BWL_PRE_PACKED_STRUCT struct ofdm_phy_hdr {
640 640
641#define D11A_PHY_HDR_GRATE(phdr) ((phdr)->rlpt[0] & 0x0f) 641#define D11A_PHY_HDR_GRATE(phdr) ((phdr)->rlpt[0] & 0x0f)
642#define D11A_PHY_HDR_GRES(phdr) (((phdr)->rlpt[0] >> 4) & 0x01) 642#define D11A_PHY_HDR_GRES(phdr) (((phdr)->rlpt[0] >> 4) & 0x01)
643#define D11A_PHY_HDR_GLENGTH(phdr) (((uint32 *)((phdr)->rlpt) >> 5) & 0x0fff) 643#define D11A_PHY_HDR_GLENGTH(phdr) (((u32 *)((phdr)->rlpt) >> 5) & 0x0fff)
644#define D11A_PHY_HDR_GPARITY(phdr) (((phdr)->rlpt[3] >> 1) & 0x01) 644#define D11A_PHY_HDR_GPARITY(phdr) (((phdr)->rlpt[3] >> 1) & 0x01)
645#define D11A_PHY_HDR_GTAIL(phdr) (((phdr)->rlpt[3] >> 2) & 0x3f) 645#define D11A_PHY_HDR_GTAIL(phdr) (((phdr)->rlpt[3] >> 2) & 0x3f)
646 646
@@ -651,7 +651,7 @@ BWL_PRE_PACKED_STRUCT struct ofdm_phy_hdr {
651#define D11A_PHY_HDR_SRES(phdr) ((phdr)->rlpt[0] &= 0xef) 651#define D11A_PHY_HDR_SRES(phdr) ((phdr)->rlpt[0] &= 0xef)
652/* length is number of octets in PSDU */ 652/* length is number of octets in PSDU */
653#define D11A_PHY_HDR_SLENGTH(phdr, length) \ 653#define D11A_PHY_HDR_SLENGTH(phdr, length) \
654 (*(uint32 *)((phdr)->rlpt) = *(uint32 *)((phdr)->rlpt) | \ 654 (*(u32 *)((phdr)->rlpt) = *(u32 *)((phdr)->rlpt) | \
655 (((length) & 0x0fff) << 5)) 655 (((length) & 0x0fff) << 5))
656/* set the tail to all zeros */ 656/* set the tail to all zeros */
657#define D11A_PHY_HDR_STAIL(phdr) ((phdr)->rlpt[3] &= 0x03) 657#define D11A_PHY_HDR_STAIL(phdr) ((phdr)->rlpt[3] &= 0x03)
@@ -1330,7 +1330,7 @@ BWL_PRE_PACKED_STRUCT struct d11rxhdr {
1330typedef struct wlc_d11rxhdr wlc_d11rxhdr_t; 1330typedef struct wlc_d11rxhdr wlc_d11rxhdr_t;
1331BWL_PRE_PACKED_STRUCT struct wlc_d11rxhdr { 1331BWL_PRE_PACKED_STRUCT struct wlc_d11rxhdr {
1332 d11rxhdr_t rxhdr; 1332 d11rxhdr_t rxhdr;
1333 uint32 tsf_l; /* TSF_L reading */ 1333 u32 tsf_l; /* TSF_L reading */
1334 s8 rssi; /* computed instanteneous rssi in BMAC */ 1334 s8 rssi; /* computed instanteneous rssi in BMAC */
1335 s8 rxpwr0; /* obsoleted, place holder for legacy ROM code. use rxpwr[] */ 1335 s8 rxpwr0; /* obsoleted, place holder for legacy ROM code. use rxpwr[] */
1336 s8 rxpwr1; /* obsoleted, place holder for legacy ROM code. use rxpwr[] */ 1336 s8 rxpwr1; /* obsoleted, place holder for legacy ROM code. use rxpwr[] */
diff --git a/drivers/staging/brcm80211/include/dbus.h b/drivers/staging/brcm80211/include/dbus.h
index 0fbb06662ee..52666632470 100644
--- a/drivers/staging/brcm80211/include/dbus.h
+++ b/drivers/staging/brcm80211/include/dbus.h
@@ -111,10 +111,10 @@ typedef struct {
111 * Let upper layer account for packets/bytes 111 * Let upper layer account for packets/bytes
112 */ 112 */
113typedef struct { 113typedef struct {
114 uint32 rx_errors; 114 u32 rx_errors;
115 uint32 tx_errors; 115 u32 tx_errors;
116 uint32 rx_dropped; 116 u32 rx_dropped;
117 uint32 tx_dropped; 117 u32 tx_dropped;
118} dbus_stats_t; 118} dbus_stats_t;
119 119
120/* 120/*
@@ -127,8 +127,8 @@ typedef struct {
127struct dbus_callbacks; 127struct dbus_callbacks;
128struct exec_parms; 128struct exec_parms;
129 129
130typedef void *(*probe_cb_t) (void *arg, const char *desc, uint32 bustype, 130typedef void *(*probe_cb_t) (void *arg, const char *desc, u32 bustype,
131 uint32 hdrlen); 131 u32 hdrlen);
132typedef void (*disconnect_cb_t) (void *arg); 132typedef void (*disconnect_cb_t) (void *arg);
133typedef void *(*exec_cb_t) (struct exec_parms *args); 133typedef void *(*exec_cb_t) (struct exec_parms *args);
134 134
@@ -260,7 +260,7 @@ extern int dbus_get_config(const dbus_pub_t *pub, dbus_config_t *config);
260extern void *dbus_pktget(const dbus_pub_t *pub, int len); 260extern void *dbus_pktget(const dbus_pub_t *pub, int len);
261extern void dbus_pktfree(const dbus_pub_t *pub, void *pkt); 261extern void dbus_pktfree(const dbus_pub_t *pub, void *pkt);
262 262
263extern int dbus_set_errmask(const dbus_pub_t *pub, uint32 mask); 263extern int dbus_set_errmask(const dbus_pub_t *pub, u32 mask);
264extern int dbus_pnp_sleep(const dbus_pub_t *pub); 264extern int dbus_pnp_sleep(const dbus_pub_t *pub);
265extern int dbus_pnp_resume(const dbus_pub_t *pub, int *fw_reload); 265extern int dbus_pnp_resume(const dbus_pub_t *pub, int *fw_reload);
266extern int dbus_pnp_disconnect(const dbus_pub_t *pub); 266extern int dbus_pnp_disconnect(const dbus_pub_t *pub);
diff --git a/drivers/staging/brcm80211/include/hndpmu.h b/drivers/staging/brcm80211/include/hndpmu.h
index b1011938099..bbcf0eecd21 100644
--- a/drivers/staging/brcm80211/include/hndpmu.h
+++ b/drivers/staging/brcm80211/include/hndpmu.h
@@ -30,17 +30,17 @@
30 30
31extern void si_pmu_init(si_t *sih, osl_t *osh); 31extern void si_pmu_init(si_t *sih, osl_t *osh);
32extern void si_pmu_chip_init(si_t *sih, osl_t *osh); 32extern void si_pmu_chip_init(si_t *sih, osl_t *osh);
33extern void si_pmu_pll_init(si_t *sih, osl_t *osh, uint32 xtalfreq); 33extern void si_pmu_pll_init(si_t *sih, osl_t *osh, u32 xtalfreq);
34extern void si_pmu_res_init(si_t *sih, osl_t *osh); 34extern void si_pmu_res_init(si_t *sih, osl_t *osh);
35extern void si_pmu_swreg_init(si_t *sih, osl_t *osh); 35extern void si_pmu_swreg_init(si_t *sih, osl_t *osh);
36 36
37extern uint32 si_pmu_force_ilp(si_t *sih, osl_t *osh, bool force); 37extern u32 si_pmu_force_ilp(si_t *sih, osl_t *osh, bool force);
38 38
39extern uint32 si_pmu_si_clock(si_t *sih, osl_t *osh); 39extern u32 si_pmu_si_clock(si_t *sih, osl_t *osh);
40extern uint32 si_pmu_cpu_clock(si_t *sih, osl_t *osh); 40extern u32 si_pmu_cpu_clock(si_t *sih, osl_t *osh);
41extern uint32 si_pmu_mem_clock(si_t *sih, osl_t *osh); 41extern u32 si_pmu_mem_clock(si_t *sih, osl_t *osh);
42extern uint32 si_pmu_alp_clock(si_t *sih, osl_t *osh); 42extern u32 si_pmu_alp_clock(si_t *sih, osl_t *osh);
43extern uint32 si_pmu_ilp_clock(si_t *sih, osl_t *osh); 43extern u32 si_pmu_ilp_clock(si_t *sih, osl_t *osh);
44 44
45extern void si_pmu_set_switcher_voltage(si_t *sih, osl_t *osh, 45extern void si_pmu_set_switcher_voltage(si_t *sih, osl_t *osh,
46 u8 bb_voltage, u8 rf_voltage); 46 u8 bb_voltage, u8 rf_voltage);
@@ -52,20 +52,20 @@ extern void si_pmu_pllupd(si_t *sih);
52extern void si_pmu_spuravoid(si_t *sih, osl_t *osh, u8 spuravoid); 52extern void si_pmu_spuravoid(si_t *sih, osl_t *osh, u8 spuravoid);
53 53
54extern bool si_pmu_is_otp_powered(si_t *sih, osl_t *osh); 54extern bool si_pmu_is_otp_powered(si_t *sih, osl_t *osh);
55extern uint32 si_pmu_measure_alpclk(si_t *sih, osl_t *osh); 55extern u32 si_pmu_measure_alpclk(si_t *sih, osl_t *osh);
56 56
57extern uint32 si_pmu_chipcontrol(si_t *sih, uint reg, uint32 mask, uint32 val); 57extern u32 si_pmu_chipcontrol(si_t *sih, uint reg, u32 mask, u32 val);
58extern uint32 si_pmu_regcontrol(si_t *sih, uint reg, uint32 mask, uint32 val); 58extern u32 si_pmu_regcontrol(si_t *sih, uint reg, u32 mask, u32 val);
59extern uint32 si_pmu_pllcontrol(si_t *sih, uint reg, uint32 mask, uint32 val); 59extern u32 si_pmu_pllcontrol(si_t *sih, uint reg, u32 mask, u32 val);
60extern void si_pmu_pllupd(si_t *sih); 60extern void si_pmu_pllupd(si_t *sih);
61extern void si_pmu_sprom_enable(si_t *sih, osl_t *osh, bool enable); 61extern void si_pmu_sprom_enable(si_t *sih, osl_t *osh, bool enable);
62 62
63extern void si_pmu_radio_enable(si_t *sih, bool enable); 63extern void si_pmu_radio_enable(si_t *sih, bool enable);
64extern uint32 si_pmu_waitforclk_on_backplane(si_t *sih, osl_t *osh, 64extern u32 si_pmu_waitforclk_on_backplane(si_t *sih, osl_t *osh,
65 uint32 clk, uint32 delay); 65 u32 clk, u32 delay);
66 66
67extern void si_pmu_otp_power(si_t *sih, osl_t *osh, bool on); 67extern void si_pmu_otp_power(si_t *sih, osl_t *osh, bool on);
68extern void si_sdiod_drive_strength_init(si_t *sih, osl_t *osh, 68extern void si_sdiod_drive_strength_init(si_t *sih, osl_t *osh,
69 uint32 drivestrength); 69 u32 drivestrength);
70 70
71#endif /* _hndpmu_h_ */ 71#endif /* _hndpmu_h_ */
diff --git a/drivers/staging/brcm80211/include/hndrte_armtrap.h b/drivers/staging/brcm80211/include/hndrte_armtrap.h
index 5d00dabebb3..8dc636d2ad6 100644
--- a/drivers/staging/brcm80211/include/hndrte_armtrap.h
+++ b/drivers/staging/brcm80211/include/hndrte_armtrap.h
@@ -50,26 +50,26 @@
50#include <typedefs.h> 50#include <typedefs.h>
51 51
52typedef struct _trap_struct { 52typedef struct _trap_struct {
53 uint32 type; 53 u32 type;
54 uint32 epc; 54 u32 epc;
55 uint32 cpsr; 55 u32 cpsr;
56 uint32 spsr; 56 u32 spsr;
57 uint32 r0; 57 u32 r0;
58 uint32 r1; 58 u32 r1;
59 uint32 r2; 59 u32 r2;
60 uint32 r3; 60 u32 r3;
61 uint32 r4; 61 u32 r4;
62 uint32 r5; 62 u32 r5;
63 uint32 r6; 63 u32 r6;
64 uint32 r7; 64 u32 r7;
65 uint32 r8; 65 u32 r8;
66 uint32 r9; 66 u32 r9;
67 uint32 r10; 67 u32 r10;
68 uint32 r11; 68 u32 r11;
69 uint32 r12; 69 u32 r12;
70 uint32 r13; 70 u32 r13;
71 uint32 r14; 71 u32 r14;
72 uint32 pc; 72 u32 pc;
73} trap_t; 73} trap_t;
74 74
75#endif /* !_LANGUAGE_ASSEMBLY */ 75#endif /* !_LANGUAGE_ASSEMBLY */
diff --git a/drivers/staging/brcm80211/include/hndrte_cons.h b/drivers/staging/brcm80211/include/hndrte_cons.h
index 74a7f27d920..9e8442f5034 100644
--- a/drivers/staging/brcm80211/include/hndrte_cons.h
+++ b/drivers/staging/brcm80211/include/hndrte_cons.h
@@ -21,7 +21,7 @@
21#define LOG_BUF_LEN 1024 21#define LOG_BUF_LEN 1024
22 22
23typedef struct { 23typedef struct {
24 uint32 buf; /* Can't be pointer on (64-bit) hosts */ 24 u32 buf; /* Can't be pointer on (64-bit) hosts */
25 uint buf_size; 25 uint buf_size;
26 uint idx; 26 uint idx;
27 char *_buf_compat; /* Redundant pointer for backward compat. */ 27 char *_buf_compat; /* Redundant pointer for backward compat. */
diff --git a/drivers/staging/brcm80211/include/linux_osl.h b/drivers/staging/brcm80211/include/linux_osl.h
index 5ef540f9416..ea1de98b59a 100644
--- a/drivers/staging/brcm80211/include/linux_osl.h
+++ b/drivers/staging/brcm80211/include/linux_osl.h
@@ -30,7 +30,7 @@ extern void osl_os_close_image(void *image);
30extern osl_t *osl_attach(void *pdev, uint bustype, bool pkttag); 30extern osl_t *osl_attach(void *pdev, uint bustype, bool pkttag);
31extern void osl_detach(osl_t *osh); 31extern void osl_detach(osl_t *osh);
32 32
33extern uint32 g_assert_type; 33extern u32 g_assert_type;
34 34
35#if defined(BCMDBG_ASSERT) 35#if defined(BCMDBG_ASSERT)
36#define ASSERT(exp) \ 36#define ASSERT(exp) \
@@ -57,7 +57,7 @@ extern void osl_delay(uint usec);
57 osl_pci_read_config((osh), (offset), (size)) 57 osl_pci_read_config((osh), (offset), (size))
58#define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \ 58#define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \
59 osl_pci_write_config((osh), (offset), (size), (val)) 59 osl_pci_write_config((osh), (offset), (size), (val))
60extern uint32 osl_pci_read_config(osl_t *osh, uint offset, uint size); 60extern u32 osl_pci_read_config(osl_t *osh, uint offset, uint size);
61extern void osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val); 61extern void osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val);
62 62
63/* PCI device bus # and slot # */ 63/* PCI device bus # and slot # */
@@ -165,7 +165,7 @@ extern int osl_error(int bcmerror);
165/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */ 165/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
166#define PKTBUFSZ 2048 /* largest reasonable packet buffer, driver uses for ethernet MTU */ 166#define PKTBUFSZ 2048 /* largest reasonable packet buffer, driver uses for ethernet MTU */
167 167
168#define OSL_SYSUPTIME() ((uint32)jiffies * (1000 / HZ)) 168#define OSL_SYSUPTIME() ((u32)jiffies * (1000 / HZ))
169#define printf(fmt, args...) printk(fmt , ## args) 169#define printf(fmt, args...) printk(fmt , ## args)
170#ifdef BRCM_FULLMAC 170#ifdef BRCM_FULLMAC
171#include <linux/kernel.h> /* for vsn/printf's */ 171#include <linux/kernel.h> /* for vsn/printf's */
@@ -184,7 +184,7 @@ extern int osl_error(int bcmerror);
184#define R_REG(osh, r) (\ 184#define R_REG(osh, r) (\
185 SELECT_BUS_READ(osh, sizeof(*(r)) == sizeof(u8) ? readb((volatile u8*)(r)) : \ 185 SELECT_BUS_READ(osh, sizeof(*(r)) == sizeof(u8) ? readb((volatile u8*)(r)) : \
186 sizeof(*(r)) == sizeof(u16) ? readw((volatile u16*)(r)) : \ 186 sizeof(*(r)) == sizeof(u16) ? readw((volatile u16*)(r)) : \
187 readl((volatile uint32*)(r)), OSL_READ_REG(osh, r)) \ 187 readl((volatile u32*)(r)), OSL_READ_REG(osh, r)) \
188) 188)
189#else /* __mips__ */ 189#else /* __mips__ */
190#define R_REG(osh, r) (\ 190#define R_REG(osh, r) (\
@@ -199,9 +199,9 @@ extern int osl_error(int bcmerror);
199 case sizeof(u16): \ 199 case sizeof(u16): \
200 __osl_v = readw((volatile u16*)(r)); \ 200 __osl_v = readw((volatile u16*)(r)); \
201 break; \ 201 break; \
202 case sizeof(uint32): \ 202 case sizeof(u32): \
203 __osl_v = \ 203 __osl_v = \
204 readl((volatile uint32*)(r)); \ 204 readl((volatile u32*)(r)); \
205 break; \ 205 break; \
206 } \ 206 } \
207 __asm__ __volatile__("sync"); \ 207 __asm__ __volatile__("sync"); \
@@ -224,8 +224,8 @@ extern int osl_error(int bcmerror);
224 writeb((u8)(v), (volatile u8*)(r)); break; \ 224 writeb((u8)(v), (volatile u8*)(r)); break; \
225 case sizeof(u16): \ 225 case sizeof(u16): \
226 writew((u16)(v), (volatile u16*)(r)); break; \ 226 writew((u16)(v), (volatile u16*)(r)); break; \
227 case sizeof(uint32): \ 227 case sizeof(u32): \
228 writel((uint32)(v), (volatile uint32*)(r)); break; \ 228 writel((u32)(v), (volatile u32*)(r)); break; \
229 }, \ 229 }, \
230 (OSL_WRITE_REG(osh, r, v))); \ 230 (OSL_WRITE_REG(osh, r, v))); \
231 } while (0) 231 } while (0)
@@ -243,8 +243,8 @@ extern int osl_error(int bcmerror);
243 __osl_v = \ 243 __osl_v = \
244 readw((volatile u16*)((uintptr)(r)^2)); \ 244 readw((volatile u16*)((uintptr)(r)^2)); \
245 break; \ 245 break; \
246 case sizeof(uint32): \ 246 case sizeof(u32): \
247 __osl_v = readl((volatile uint32*)(r)); \ 247 __osl_v = readl((volatile u32*)(r)); \
248 break; \ 248 break; \
249 } \ 249 } \
250 __osl_v; \ 250 __osl_v; \
@@ -260,9 +260,9 @@ extern int osl_error(int bcmerror);
260 case sizeof(u16): \ 260 case sizeof(u16): \
261 writew((u16)(v), \ 261 writew((u16)(v), \
262 (volatile u16*)((uintptr)(r)^2)); break; \ 262 (volatile u16*)((uintptr)(r)^2)); break; \
263 case sizeof(uint32): \ 263 case sizeof(u32): \
264 writel((uint32)(v), \ 264 writel((u32)(v), \
265 (volatile uint32*)(r)); break; \ 265 (volatile u32*)(r)); break; \
266 }, \ 266 }, \
267 (OSL_WRITE_REG(osh, r, v))); \ 267 (OSL_WRITE_REG(osh, r, v))); \
268 } while (0) 268 } while (0)
@@ -402,7 +402,7 @@ osl_pkt_tonative(osl_pubinfo_t *osh, void *pkt)
402#define RPC_READ_REG(osh, r) (\ 402#define RPC_READ_REG(osh, r) (\
403 sizeof(*(r)) == sizeof(u8) ? osl_readb((osh), (volatile u8*)(r)) : \ 403 sizeof(*(r)) == sizeof(u8) ? osl_readb((osh), (volatile u8*)(r)) : \
404 sizeof(*(r)) == sizeof(u16) ? osl_readw((osh), (volatile u16*)(r)) : \ 404 sizeof(*(r)) == sizeof(u16) ? osl_readw((osh), (volatile u16*)(r)) : \
405 osl_readl((osh), (volatile uint32*)(r)) \ 405 osl_readl((osh), (volatile u32*)(r)) \
406) 406)
407#define RPC_WRITE_REG(osh, r, v) do { \ 407#define RPC_WRITE_REG(osh, r, v) do { \
408 switch (sizeof(*(r))) { \ 408 switch (sizeof(*(r))) { \
@@ -412,18 +412,18 @@ osl_pkt_tonative(osl_pubinfo_t *osh, void *pkt)
412 case sizeof(u16): \ 412 case sizeof(u16): \
413 osl_writew((osh), (volatile u16*)(r), (u16)(v)); \ 413 osl_writew((osh), (volatile u16*)(r), (u16)(v)); \
414 break; \ 414 break; \
415 case sizeof(uint32): \ 415 case sizeof(u32): \
416 osl_writel((osh), (volatile uint32*)(r), (uint32)(v)); \ 416 osl_writel((osh), (volatile u32*)(r), (u32)(v)); \
417 break; \ 417 break; \
418 } \ 418 } \
419} while (0) 419} while (0)
420 420
421extern u8 osl_readb(osl_t *osh, volatile u8 *r); 421extern u8 osl_readb(osl_t *osh, volatile u8 *r);
422extern u16 osl_readw(osl_t *osh, volatile u16 *r); 422extern u16 osl_readw(osl_t *osh, volatile u16 *r);
423extern uint32 osl_readl(osl_t *osh, volatile uint32 *r); 423extern u32 osl_readl(osl_t *osh, volatile u32 *r);
424extern void osl_writeb(osl_t *osh, volatile u8 *r, u8 v); 424extern void osl_writeb(osl_t *osh, volatile u8 *r, u8 v);
425extern void osl_writew(osl_t *osh, volatile u16 *r, u16 v); 425extern void osl_writew(osl_t *osh, volatile u16 *r, u16 v);
426extern void osl_writel(osl_t *osh, volatile uint32 *r, uint32 v); 426extern void osl_writel(osl_t *osh, volatile u32 *r, u32 v);
427#endif /* BCMSDIO */ 427#endif /* BCMSDIO */
428 428
429#endif /* _linux_osl_h_ */ 429#endif /* _linux_osl_h_ */
diff --git a/drivers/staging/brcm80211/include/msgtrace.h b/drivers/staging/brcm80211/include/msgtrace.h
index f88c7b60da5..a4cf8d285f2 100644
--- a/drivers/staging/brcm80211/include/msgtrace.h
+++ b/drivers/staging/brcm80211/include/msgtrace.h
@@ -29,14 +29,14 @@ typedef BWL_PRE_PACKED_STRUCT struct msgtrace_hdr {
29 u8 version; 29 u8 version;
30 u8 spare; 30 u8 spare;
31 u16 len; /* Len of the trace */ 31 u16 len; /* Len of the trace */
32 uint32 seqnum; /* Sequence number of message. Useful 32 u32 seqnum; /* Sequence number of message. Useful
33 * if the messsage has been lost 33 * if the messsage has been lost
34 * because of DMA error or a bus reset 34 * because of DMA error or a bus reset
35 * (ex: SDIO Func2) 35 * (ex: SDIO Func2)
36 */ 36 */
37 uint32 discarded_bytes; /* Number of discarded bytes because of 37 u32 discarded_bytes; /* Number of discarded bytes because of
38 trace overflow */ 38 trace overflow */
39 uint32 discarded_printf; /* Number of discarded printf 39 u32 discarded_printf; /* Number of discarded printf
40 because of trace overflow */ 40 because of trace overflow */
41} BWL_POST_PACKED_STRUCT msgtrace_hdr_t; 41} BWL_POST_PACKED_STRUCT msgtrace_hdr_t;
42 42
diff --git a/drivers/staging/brcm80211/include/nicpci.h b/drivers/staging/brcm80211/include/nicpci.h
index bab11c7a190..76578db8b85 100644
--- a/drivers/staging/brcm80211/include/nicpci.h
+++ b/drivers/staging/brcm80211/include/nicpci.h
@@ -46,14 +46,14 @@
46struct sbpcieregs; 46struct sbpcieregs;
47 47
48extern u8 pcicore_find_pci_capability(osl_t *osh, u8 req_cap_id, 48extern u8 pcicore_find_pci_capability(osl_t *osh, u8 req_cap_id,
49 unsigned char *buf, uint32 *buflen); 49 unsigned char *buf, u32 *buflen);
50extern uint pcie_readreg(osl_t *osh, struct sbpcieregs *pcieregs, 50extern uint pcie_readreg(osl_t *osh, struct sbpcieregs *pcieregs,
51 uint addrtype, uint offset); 51 uint addrtype, uint offset);
52extern uint pcie_writereg(osl_t *osh, struct sbpcieregs *pcieregs, 52extern uint pcie_writereg(osl_t *osh, struct sbpcieregs *pcieregs,
53 uint addrtype, uint offset, uint val); 53 uint addrtype, uint offset, uint val);
54 54
55extern u8 pcie_clkreq(void *pch, uint32 mask, uint32 val); 55extern u8 pcie_clkreq(void *pch, u32 mask, u32 val);
56extern uint32 pcie_lcreg(void *pch, uint32 mask, uint32 val); 56extern u32 pcie_lcreg(void *pch, u32 mask, u32 val);
57 57
58extern void *pcicore_init(si_t *sih, osl_t *osh, void *regs); 58extern void *pcicore_init(si_t *sih, osl_t *osh, void *regs);
59extern void pcicore_deinit(void *pch); 59extern void pcicore_deinit(void *pch);
@@ -64,11 +64,11 @@ extern void pcicore_sleep(void *pch);
64extern void pcicore_down(void *pch, int state); 64extern void pcicore_down(void *pch, int state);
65 65
66extern void pcie_war_ovr_aspm_update(void *pch, u8 aspm); 66extern void pcie_war_ovr_aspm_update(void *pch, u8 aspm);
67extern uint32 pcicore_pcieserdesreg(void *pch, uint32 mdioslave, uint32 offset, 67extern u32 pcicore_pcieserdesreg(void *pch, u32 mdioslave, u32 offset,
68 uint32 mask, uint32 val); 68 u32 mask, u32 val);
69 69
70extern uint32 pcicore_pciereg(void *pch, uint32 offset, uint32 mask, 70extern u32 pcicore_pciereg(void *pch, u32 offset, u32 mask,
71 uint32 val, uint type); 71 u32 val, uint type);
72 72
73extern bool pcicore_pmecap_fast(osl_t *osh); 73extern bool pcicore_pmecap_fast(osl_t *osh);
74extern void pcicore_pmeen(void *pch); 74extern void pcicore_pmeen(void *pch);
diff --git a/drivers/staging/brcm80211/include/pci_core.h b/drivers/staging/brcm80211/include/pci_core.h
index abd8e88ac0d..90ef3695da9 100644
--- a/drivers/staging/brcm80211/include/pci_core.h
+++ b/drivers/staging/brcm80211/include/pci_core.h
@@ -28,30 +28,30 @@
28 28
29/* Sonics side: PCI core and host control registers */ 29/* Sonics side: PCI core and host control registers */
30typedef struct sbpciregs { 30typedef struct sbpciregs {
31 uint32 control; /* PCI control */ 31 u32 control; /* PCI control */
32 uint32 PAD[3]; 32 u32 PAD[3];
33 uint32 arbcontrol; /* PCI arbiter control */ 33 u32 arbcontrol; /* PCI arbiter control */
34 uint32 clkrun; /* Clkrun Control (>=rev11) */ 34 u32 clkrun; /* Clkrun Control (>=rev11) */
35 uint32 PAD[2]; 35 u32 PAD[2];
36 uint32 intstatus; /* Interrupt status */ 36 u32 intstatus; /* Interrupt status */
37 uint32 intmask; /* Interrupt mask */ 37 u32 intmask; /* Interrupt mask */
38 uint32 sbtopcimailbox; /* Sonics to PCI mailbox */ 38 u32 sbtopcimailbox; /* Sonics to PCI mailbox */
39 uint32 PAD[9]; 39 u32 PAD[9];
40 uint32 bcastaddr; /* Sonics broadcast address */ 40 u32 bcastaddr; /* Sonics broadcast address */
41 uint32 bcastdata; /* Sonics broadcast data */ 41 u32 bcastdata; /* Sonics broadcast data */
42 uint32 PAD[2]; 42 u32 PAD[2];
43 uint32 gpioin; /* ro: gpio input (>=rev2) */ 43 u32 gpioin; /* ro: gpio input (>=rev2) */
44 uint32 gpioout; /* rw: gpio output (>=rev2) */ 44 u32 gpioout; /* rw: gpio output (>=rev2) */
45 uint32 gpioouten; /* rw: gpio output enable (>= rev2) */ 45 u32 gpioouten; /* rw: gpio output enable (>= rev2) */
46 uint32 gpiocontrol; /* rw: gpio control (>= rev2) */ 46 u32 gpiocontrol; /* rw: gpio control (>= rev2) */
47 uint32 PAD[36]; 47 u32 PAD[36];
48 uint32 sbtopci0; /* Sonics to PCI translation 0 */ 48 u32 sbtopci0; /* Sonics to PCI translation 0 */
49 uint32 sbtopci1; /* Sonics to PCI translation 1 */ 49 u32 sbtopci1; /* Sonics to PCI translation 1 */
50 uint32 sbtopci2; /* Sonics to PCI translation 2 */ 50 u32 sbtopci2; /* Sonics to PCI translation 2 */
51 uint32 PAD[189]; 51 u32 PAD[189];
52 uint32 pcicfg[4][64]; /* 0x400 - 0x7FF, PCI Cfg Space (>=rev8) */ 52 u32 pcicfg[4][64]; /* 0x400 - 0x7FF, PCI Cfg Space (>=rev8) */
53 u16 sprom[36]; /* SPROM shadow Area */ 53 u16 sprom[36]; /* SPROM shadow Area */
54 uint32 PAD[46]; 54 u32 PAD[46];
55} sbpciregs_t; 55} sbpciregs_t;
56 56
57#endif /* _LANGUAGE_ASSEMBLY */ 57#endif /* _LANGUAGE_ASSEMBLY */
diff --git a/drivers/staging/brcm80211/include/pcicfg.h b/drivers/staging/brcm80211/include/pcicfg.h
index abfc82cc0d9..3a19e1d243c 100644
--- a/drivers/staging/brcm80211/include/pcicfg.h
+++ b/drivers/staging/brcm80211/include/pcicfg.h
@@ -115,12 +115,12 @@ typedef struct _pci_config_regs {
115 u8 latency_timer; 115 u8 latency_timer;
116 u8 header_type; 116 u8 header_type;
117 u8 bist; 117 u8 bist;
118 uint32 base[PCI_BAR_MAX]; 118 u32 base[PCI_BAR_MAX];
119 uint32 cardbus_cis; 119 u32 cardbus_cis;
120 u16 subsys_vendor; 120 u16 subsys_vendor;
121 u16 subsys_id; 121 u16 subsys_id;
122 uint32 baserom; 122 u32 baserom;
123 uint32 rsvd_a[PCR_RSVDA_MAX]; 123 u32 rsvd_a[PCR_RSVDA_MAX];
124 u8 int_line; 124 u8 int_line;
125 u8 int_pin; 125 u8 int_pin;
126 u8 min_gnt; 126 u8 min_gnt;
@@ -343,7 +343,7 @@ typedef struct _ppb_config_regs {
343 u8 latency_timer; 343 u8 latency_timer;
344 u8 header_type; 344 u8 header_type;
345 u8 bist; 345 u8 bist;
346 uint32 rsvd_a[PPB_RSVDA_MAX]; 346 u32 rsvd_a[PPB_RSVDA_MAX];
347 u8 prim_bus; 347 u8 prim_bus;
348 u8 sec_bus; 348 u8 sec_bus;
349 u8 sub_bus; 349 u8 sub_bus;
@@ -355,20 +355,20 @@ typedef struct _ppb_config_regs {
355 u16 mem_lim; 355 u16 mem_lim;
356 u16 pf_mem_base; 356 u16 pf_mem_base;
357 u16 pf_mem_lim; 357 u16 pf_mem_lim;
358 uint32 pf_mem_base_hi; 358 u32 pf_mem_base_hi;
359 uint32 pf_mem_lim_hi; 359 u32 pf_mem_lim_hi;
360 u16 io_base_hi; 360 u16 io_base_hi;
361 u16 io_lim_hi; 361 u16 io_lim_hi;
362 u16 subsys_vendor; 362 u16 subsys_vendor;
363 u16 subsys_id; 363 u16 subsys_id;
364 uint32 rsvd_b; 364 u32 rsvd_b;
365 u8 rsvd_c; 365 u8 rsvd_c;
366 u8 int_pin; 366 u8 int_pin;
367 u16 bridge_ctrl; 367 u16 bridge_ctrl;
368 u8 chip_ctrl; 368 u8 chip_ctrl;
369 u8 diag_ctrl; 369 u8 diag_ctrl;
370 u16 arb_ctrl; 370 u16 arb_ctrl;
371 uint32 rsvd_d[PPB_RSVDD_MAX]; 371 u32 rsvd_d[PPB_RSVDD_MAX];
372 u8 dev_dep[192]; 372 u8 dev_dep[192];
373} ppb_config_regs; 373} ppb_config_regs;
374 374
@@ -385,7 +385,7 @@ typedef struct _pciconfig_cap_msi {
385 u8 capID; 385 u8 capID;
386 u8 nextptr; 386 u8 nextptr;
387 u16 msgctrl; 387 u16 msgctrl;
388 uint32 msgaddr; 388 u32 msgaddr;
389} pciconfig_cap_msi; 389} pciconfig_cap_msi;
390 390
391/* Data structure to define the Power managment facility 391/* Data structure to define the Power managment facility
@@ -410,18 +410,18 @@ typedef struct _pciconfig_cap_pcie {
410 u8 capID; 410 u8 capID;
411 u8 nextptr; 411 u8 nextptr;
412 u16 pcie_cap; 412 u16 pcie_cap;
413 uint32 dev_cap; 413 u32 dev_cap;
414 u16 dev_ctrl; 414 u16 dev_ctrl;
415 u16 dev_status; 415 u16 dev_status;
416 uint32 link_cap; 416 u32 link_cap;
417 u16 link_ctrl; 417 u16 link_ctrl;
418 u16 link_status; 418 u16 link_status;
419 uint32 slot_cap; 419 u32 slot_cap;
420 u16 slot_ctrl; 420 u16 slot_ctrl;
421 u16 slot_status; 421 u16 slot_status;
422 u16 root_ctrl; 422 u16 root_ctrl;
423 u16 root_cap; 423 u16 root_cap;
424 uint32 root_status; 424 u32 root_status;
425} pciconfig_cap_pcie; 425} pciconfig_cap_pcie;
426 426
427/* PCIE Enhanced CAPABILITY DEFINES */ 427/* PCIE Enhanced CAPABILITY DEFINES */
diff --git a/drivers/staging/brcm80211/include/pcie_core.h b/drivers/staging/brcm80211/include/pcie_core.h
index 9dcd6a00e91..cd54ddcf459 100644
--- a/drivers/staging/brcm80211/include/pcie_core.h
+++ b/drivers/staging/brcm80211/include/pcie_core.h
@@ -46,36 +46,36 @@
46 46
47/* SB side: PCIE core and host control registers */ 47/* SB side: PCIE core and host control registers */
48typedef struct sbpcieregs { 48typedef struct sbpcieregs {
49 uint32 control; /* host mode only */ 49 u32 control; /* host mode only */
50 uint32 PAD[2]; 50 u32 PAD[2];
51 uint32 biststatus; /* bist Status: 0x00C */ 51 u32 biststatus; /* bist Status: 0x00C */
52 uint32 gpiosel; /* PCIE gpio sel: 0x010 */ 52 u32 gpiosel; /* PCIE gpio sel: 0x010 */
53 uint32 gpioouten; /* PCIE gpio outen: 0x14 */ 53 u32 gpioouten; /* PCIE gpio outen: 0x14 */
54 uint32 PAD[2]; 54 u32 PAD[2];
55 uint32 intstatus; /* Interrupt status: 0x20 */ 55 u32 intstatus; /* Interrupt status: 0x20 */
56 uint32 intmask; /* Interrupt mask: 0x24 */ 56 u32 intmask; /* Interrupt mask: 0x24 */
57 uint32 sbtopcimailbox; /* sb to pcie mailbox: 0x028 */ 57 u32 sbtopcimailbox; /* sb to pcie mailbox: 0x028 */
58 uint32 PAD[53]; 58 u32 PAD[53];
59 uint32 sbtopcie0; /* sb to pcie translation 0: 0x100 */ 59 u32 sbtopcie0; /* sb to pcie translation 0: 0x100 */
60 uint32 sbtopcie1; /* sb to pcie translation 1: 0x104 */ 60 u32 sbtopcie1; /* sb to pcie translation 1: 0x104 */
61 uint32 sbtopcie2; /* sb to pcie translation 2: 0x108 */ 61 u32 sbtopcie2; /* sb to pcie translation 2: 0x108 */
62 uint32 PAD[5]; 62 u32 PAD[5];
63 63
64 /* pcie core supports in direct access to config space */ 64 /* pcie core supports in direct access to config space */
65 uint32 configaddr; /* pcie config space access: Address field: 0x120 */ 65 u32 configaddr; /* pcie config space access: Address field: 0x120 */
66 uint32 configdata; /* pcie config space access: Data field: 0x124 */ 66 u32 configdata; /* pcie config space access: Data field: 0x124 */
67 67
68 /* mdio access to serdes */ 68 /* mdio access to serdes */
69 uint32 mdiocontrol; /* controls the mdio access: 0x128 */ 69 u32 mdiocontrol; /* controls the mdio access: 0x128 */
70 uint32 mdiodata; /* Data to the mdio access: 0x12c */ 70 u32 mdiodata; /* Data to the mdio access: 0x12c */
71 71
72 /* pcie protocol phy/dllp/tlp register indirect access mechanism */ 72 /* pcie protocol phy/dllp/tlp register indirect access mechanism */
73 uint32 pcieindaddr; /* indirect access to the internal register: 0x130 */ 73 u32 pcieindaddr; /* indirect access to the internal register: 0x130 */
74 uint32 pcieinddata; /* Data to/from the internal regsiter: 0x134 */ 74 u32 pcieinddata; /* Data to/from the internal regsiter: 0x134 */
75 75
76 uint32 clkreqenctrl; /* >= rev 6, Clkreq rdma control : 0x138 */ 76 u32 clkreqenctrl; /* >= rev 6, Clkreq rdma control : 0x138 */
77 uint32 PAD[177]; 77 u32 PAD[177];
78 uint32 pciecfg[4][64]; /* 0x400 - 0x7FF, PCIE Cfg Space */ 78 u32 pciecfg[4][64]; /* 0x400 - 0x7FF, PCIE Cfg Space */
79 u16 sprom[64]; /* SPROM shadow Area */ 79 u16 sprom[64]; /* SPROM shadow Area */
80} sbpcieregs_t; 80} sbpcieregs_t;
81 81
diff --git a/drivers/staging/brcm80211/include/proto/802.11.h b/drivers/staging/brcm80211/include/proto/802.11.h
index 8358d064a63..db26cf10662 100644
--- a/drivers/staging/brcm80211/include/proto/802.11.h
+++ b/drivers/staging/brcm80211/include/proto/802.11.h
@@ -81,7 +81,7 @@ BWL_PRE_PACKED_STRUCT struct dot11_management_header {
81#define DOT11_MGMT_HDR_LEN 24 81#define DOT11_MGMT_HDR_LEN 24
82 82
83BWL_PRE_PACKED_STRUCT struct dot11_bcn_prb { 83BWL_PRE_PACKED_STRUCT struct dot11_bcn_prb {
84 uint32 timestamp[2]; 84 u32 timestamp[2];
85 u16 beacon_interval; 85 u16 beacon_interval;
86 u16 capability; 86 u16 capability;
87} BWL_POST_PACKED_STRUCT; 87} BWL_POST_PACKED_STRUCT;
@@ -236,20 +236,20 @@ typedef struct wme_param_ie wme_param_ie_t;
236#define DOT11_MAXNUMFRAGS 16 236#define DOT11_MAXNUMFRAGS 16
237 237
238typedef struct d11cnt { 238typedef struct d11cnt {
239 uint32 txfrag; 239 u32 txfrag;
240 uint32 txmulti; 240 u32 txmulti;
241 uint32 txfail; 241 u32 txfail;
242 uint32 txretry; 242 u32 txretry;
243 uint32 txretrie; 243 u32 txretrie;
244 uint32 rxdup; 244 u32 rxdup;
245 uint32 txrts; 245 u32 txrts;
246 uint32 txnocts; 246 u32 txnocts;
247 uint32 txnoack; 247 u32 txnoack;
248 uint32 rxfrag; 248 u32 rxfrag;
249 uint32 rxmulti; 249 u32 rxmulti;
250 uint32 rxcrc; 250 u32 rxcrc;
251 uint32 txfrmsnt; 251 u32 txfrmsnt;
252 uint32 rxundec; 252 u32 rxundec;
253} d11cnt_t; 253} d11cnt_t;
254 254
255#define MCSSET_LEN 16 255#define MCSSET_LEN 16
@@ -259,7 +259,7 @@ BWL_PRE_PACKED_STRUCT struct ht_cap_ie {
259 u8 params; 259 u8 params;
260 u8 supp_mcs[MCSSET_LEN]; 260 u8 supp_mcs[MCSSET_LEN];
261 u16 ext_htcap; 261 u16 ext_htcap;
262 uint32 txbf_cap; 262 u32 txbf_cap;
263 u8 as_cap; 263 u8 as_cap;
264} BWL_POST_PACKED_STRUCT; 264} BWL_POST_PACKED_STRUCT;
265typedef struct ht_cap_ie ht_cap_ie_t; 265typedef struct ht_cap_ie ht_cap_ie_t;
diff --git a/drivers/staging/brcm80211/include/proto/bcmevent.h b/drivers/staging/brcm80211/include/proto/bcmevent.h
index 2a5598b6296..0a7231df0ce 100644
--- a/drivers/staging/brcm80211/include/proto/bcmevent.h
+++ b/drivers/staging/brcm80211/include/proto/bcmevent.h
@@ -30,11 +30,11 @@
30typedef BWL_PRE_PACKED_STRUCT struct { 30typedef BWL_PRE_PACKED_STRUCT struct {
31 u16 version; 31 u16 version;
32 u16 flags; 32 u16 flags;
33 uint32 event_type; 33 u32 event_type;
34 uint32 status; 34 u32 status;
35 uint32 reason; 35 u32 reason;
36 uint32 auth_type; 36 u32 auth_type;
37 uint32 datalen; 37 u32 datalen;
38 struct ether_addr addr; 38 struct ether_addr addr;
39 char ifname[BCM_MSG_IFNAME_MAX]; 39 char ifname[BCM_MSG_IFNAME_MAX];
40} BWL_POST_PACKED_STRUCT wl_event_msg_t; 40} BWL_POST_PACKED_STRUCT wl_event_msg_t;
diff --git a/drivers/staging/brcm80211/include/sbchipc.h b/drivers/staging/brcm80211/include/sbchipc.h
index 6a63b65fc72..f608894b117 100644
--- a/drivers/staging/brcm80211/include/sbchipc.h
+++ b/drivers/staging/brcm80211/include/sbchipc.h
@@ -27,147 +27,147 @@
27#endif /* PAD */ 27#endif /* PAD */
28 28
29typedef volatile struct { 29typedef volatile struct {
30 uint32 chipid; /* 0x0 */ 30 u32 chipid; /* 0x0 */
31 uint32 capabilities; 31 u32 capabilities;
32 uint32 corecontrol; /* corerev >= 1 */ 32 u32 corecontrol; /* corerev >= 1 */
33 uint32 bist; 33 u32 bist;
34 34
35 /* OTP */ 35 /* OTP */
36 uint32 otpstatus; /* 0x10, corerev >= 10 */ 36 u32 otpstatus; /* 0x10, corerev >= 10 */
37 uint32 otpcontrol; 37 u32 otpcontrol;
38 uint32 otpprog; 38 u32 otpprog;
39 uint32 otplayout; /* corerev >= 23 */ 39 u32 otplayout; /* corerev >= 23 */
40 40
41 /* Interrupt control */ 41 /* Interrupt control */
42 uint32 intstatus; /* 0x20 */ 42 u32 intstatus; /* 0x20 */
43 uint32 intmask; 43 u32 intmask;
44 44
45 /* Chip specific regs */ 45 /* Chip specific regs */
46 uint32 chipcontrol; /* 0x28, rev >= 11 */ 46 u32 chipcontrol; /* 0x28, rev >= 11 */
47 uint32 chipstatus; /* 0x2c, rev >= 11 */ 47 u32 chipstatus; /* 0x2c, rev >= 11 */
48 48
49 /* Jtag Master */ 49 /* Jtag Master */
50 uint32 jtagcmd; /* 0x30, rev >= 10 */ 50 u32 jtagcmd; /* 0x30, rev >= 10 */
51 uint32 jtagir; 51 u32 jtagir;
52 uint32 jtagdr; 52 u32 jtagdr;
53 uint32 jtagctrl; 53 u32 jtagctrl;
54 54
55 /* serial flash interface registers */ 55 /* serial flash interface registers */
56 uint32 flashcontrol; /* 0x40 */ 56 u32 flashcontrol; /* 0x40 */
57 uint32 flashaddress; 57 u32 flashaddress;
58 uint32 flashdata; 58 u32 flashdata;
59 uint32 PAD[1]; 59 u32 PAD[1];
60 60
61 /* Silicon backplane configuration broadcast control */ 61 /* Silicon backplane configuration broadcast control */
62 uint32 broadcastaddress; /* 0x50 */ 62 u32 broadcastaddress; /* 0x50 */
63 uint32 broadcastdata; 63 u32 broadcastdata;
64 64
65 /* gpio - cleared only by power-on-reset */ 65 /* gpio - cleared only by power-on-reset */
66 uint32 gpiopullup; /* 0x58, corerev >= 20 */ 66 u32 gpiopullup; /* 0x58, corerev >= 20 */
67 uint32 gpiopulldown; /* 0x5c, corerev >= 20 */ 67 u32 gpiopulldown; /* 0x5c, corerev >= 20 */
68 uint32 gpioin; /* 0x60 */ 68 u32 gpioin; /* 0x60 */
69 uint32 gpioout; /* 0x64 */ 69 u32 gpioout; /* 0x64 */
70 uint32 gpioouten; /* 0x68 */ 70 u32 gpioouten; /* 0x68 */
71 uint32 gpiocontrol; /* 0x6C */ 71 u32 gpiocontrol; /* 0x6C */
72 uint32 gpiointpolarity; /* 0x70 */ 72 u32 gpiointpolarity; /* 0x70 */
73 uint32 gpiointmask; /* 0x74 */ 73 u32 gpiointmask; /* 0x74 */
74 74
75 /* GPIO events corerev >= 11 */ 75 /* GPIO events corerev >= 11 */
76 uint32 gpioevent; 76 u32 gpioevent;
77 uint32 gpioeventintmask; 77 u32 gpioeventintmask;
78 78
79 /* Watchdog timer */ 79 /* Watchdog timer */
80 uint32 watchdog; /* 0x80 */ 80 u32 watchdog; /* 0x80 */
81 81
82 /* GPIO events corerev >= 11 */ 82 /* GPIO events corerev >= 11 */
83 uint32 gpioeventintpolarity; 83 u32 gpioeventintpolarity;
84 84
85 /* GPIO based LED powersave registers corerev >= 16 */ 85 /* GPIO based LED powersave registers corerev >= 16 */
86 uint32 gpiotimerval; /* 0x88 */ 86 u32 gpiotimerval; /* 0x88 */
87 uint32 gpiotimeroutmask; 87 u32 gpiotimeroutmask;
88 88
89 /* clock control */ 89 /* clock control */
90 uint32 clockcontrol_n; /* 0x90 */ 90 u32 clockcontrol_n; /* 0x90 */
91 uint32 clockcontrol_sb; /* aka m0 */ 91 u32 clockcontrol_sb; /* aka m0 */
92 uint32 clockcontrol_pci; /* aka m1 */ 92 u32 clockcontrol_pci; /* aka m1 */
93 uint32 clockcontrol_m2; /* mii/uart/mipsref */ 93 u32 clockcontrol_m2; /* mii/uart/mipsref */
94 uint32 clockcontrol_m3; /* cpu */ 94 u32 clockcontrol_m3; /* cpu */
95 uint32 clkdiv; /* corerev >= 3 */ 95 u32 clkdiv; /* corerev >= 3 */
96 uint32 gpiodebugsel; /* corerev >= 28 */ 96 u32 gpiodebugsel; /* corerev >= 28 */
97 uint32 capabilities_ext; /* 0xac */ 97 u32 capabilities_ext; /* 0xac */
98 98
99 /* pll delay registers (corerev >= 4) */ 99 /* pll delay registers (corerev >= 4) */
100 uint32 pll_on_delay; /* 0xb0 */ 100 u32 pll_on_delay; /* 0xb0 */
101 uint32 fref_sel_delay; 101 u32 fref_sel_delay;
102 uint32 slow_clk_ctl; /* 5 < corerev < 10 */ 102 u32 slow_clk_ctl; /* 5 < corerev < 10 */
103 uint32 PAD; 103 u32 PAD;
104 104
105 /* Instaclock registers (corerev >= 10) */ 105 /* Instaclock registers (corerev >= 10) */
106 uint32 system_clk_ctl; /* 0xc0 */ 106 u32 system_clk_ctl; /* 0xc0 */
107 uint32 clkstatestretch; 107 u32 clkstatestretch;
108 uint32 PAD[2]; 108 u32 PAD[2];
109 109
110 /* Indirect backplane access (corerev >= 22) */ 110 /* Indirect backplane access (corerev >= 22) */
111 uint32 bp_addrlow; /* 0xd0 */ 111 u32 bp_addrlow; /* 0xd0 */
112 uint32 bp_addrhigh; 112 u32 bp_addrhigh;
113 uint32 bp_data; 113 u32 bp_data;
114 uint32 PAD; 114 u32 PAD;
115 uint32 bp_indaccess; 115 u32 bp_indaccess;
116 uint32 PAD[3]; 116 u32 PAD[3];
117 117
118 /* More clock dividers (corerev >= 32) */ 118 /* More clock dividers (corerev >= 32) */
119 uint32 clkdiv2; 119 u32 clkdiv2;
120 uint32 PAD[2]; 120 u32 PAD[2];
121 121
122 /* In AI chips, pointer to erom */ 122 /* In AI chips, pointer to erom */
123 uint32 eromptr; /* 0xfc */ 123 u32 eromptr; /* 0xfc */
124 124
125 /* ExtBus control registers (corerev >= 3) */ 125 /* ExtBus control registers (corerev >= 3) */
126 uint32 pcmcia_config; /* 0x100 */ 126 u32 pcmcia_config; /* 0x100 */
127 uint32 pcmcia_memwait; 127 u32 pcmcia_memwait;
128 uint32 pcmcia_attrwait; 128 u32 pcmcia_attrwait;
129 uint32 pcmcia_iowait; 129 u32 pcmcia_iowait;
130 uint32 ide_config; 130 u32 ide_config;
131 uint32 ide_memwait; 131 u32 ide_memwait;
132 uint32 ide_attrwait; 132 u32 ide_attrwait;
133 uint32 ide_iowait; 133 u32 ide_iowait;
134 uint32 prog_config; 134 u32 prog_config;
135 uint32 prog_waitcount; 135 u32 prog_waitcount;
136 uint32 flash_config; 136 u32 flash_config;
137 uint32 flash_waitcount; 137 u32 flash_waitcount;
138 uint32 SECI_config; /* 0x130 SECI configuration */ 138 u32 SECI_config; /* 0x130 SECI configuration */
139 uint32 PAD[3]; 139 u32 PAD[3];
140 140
141 /* Enhanced Coexistence Interface (ECI) registers (corerev >= 21) */ 141 /* Enhanced Coexistence Interface (ECI) registers (corerev >= 21) */
142 uint32 eci_output; /* 0x140 */ 142 u32 eci_output; /* 0x140 */
143 uint32 eci_control; 143 u32 eci_control;
144 uint32 eci_inputlo; 144 u32 eci_inputlo;
145 uint32 eci_inputmi; 145 u32 eci_inputmi;
146 uint32 eci_inputhi; 146 u32 eci_inputhi;
147 uint32 eci_inputintpolaritylo; 147 u32 eci_inputintpolaritylo;
148 uint32 eci_inputintpolaritymi; 148 u32 eci_inputintpolaritymi;
149 uint32 eci_inputintpolarityhi; 149 u32 eci_inputintpolarityhi;
150 uint32 eci_intmasklo; 150 u32 eci_intmasklo;
151 uint32 eci_intmaskmi; 151 u32 eci_intmaskmi;
152 uint32 eci_intmaskhi; 152 u32 eci_intmaskhi;
153 uint32 eci_eventlo; 153 u32 eci_eventlo;
154 uint32 eci_eventmi; 154 u32 eci_eventmi;
155 uint32 eci_eventhi; 155 u32 eci_eventhi;
156 uint32 eci_eventmasklo; 156 u32 eci_eventmasklo;
157 uint32 eci_eventmaskmi; 157 u32 eci_eventmaskmi;
158 uint32 eci_eventmaskhi; 158 u32 eci_eventmaskhi;
159 uint32 PAD[3]; 159 u32 PAD[3];
160 160
161 /* SROM interface (corerev >= 32) */ 161 /* SROM interface (corerev >= 32) */
162 uint32 sromcontrol; /* 0x190 */ 162 u32 sromcontrol; /* 0x190 */
163 uint32 sromaddress; 163 u32 sromaddress;
164 uint32 sromdata; 164 u32 sromdata;
165 uint32 PAD[17]; 165 u32 PAD[17];
166 166
167 /* Clock control and hardware workarounds (corerev >= 20) */ 167 /* Clock control and hardware workarounds (corerev >= 20) */
168 uint32 clk_ctl_st; /* 0x1e0 */ 168 u32 clk_ctl_st; /* 0x1e0 */
169 uint32 hw_war; 169 u32 hw_war;
170 uint32 PAD[70]; 170 u32 PAD[70];
171 171
172 /* UARTs */ 172 /* UARTs */
173 u8 uart0data; /* 0x300 */ 173 u8 uart0data; /* 0x300 */
@@ -188,38 +188,38 @@ typedef volatile struct {
188 u8 uart1lsr; 188 u8 uart1lsr;
189 u8 uart1msr; 189 u8 uart1msr;
190 u8 uart1scratch; 190 u8 uart1scratch;
191 uint32 PAD[126]; 191 u32 PAD[126];
192 192
193 /* PMU registers (corerev >= 20) */ 193 /* PMU registers (corerev >= 20) */
194 uint32 pmucontrol; /* 0x600 */ 194 u32 pmucontrol; /* 0x600 */
195 uint32 pmucapabilities; 195 u32 pmucapabilities;
196 uint32 pmustatus; 196 u32 pmustatus;
197 uint32 res_state; 197 u32 res_state;
198 uint32 res_pending; 198 u32 res_pending;
199 uint32 pmutimer; 199 u32 pmutimer;
200 uint32 min_res_mask; 200 u32 min_res_mask;
201 uint32 max_res_mask; 201 u32 max_res_mask;
202 uint32 res_table_sel; 202 u32 res_table_sel;
203 uint32 res_dep_mask; 203 u32 res_dep_mask;
204 uint32 res_updn_timer; 204 u32 res_updn_timer;
205 uint32 res_timer; 205 u32 res_timer;
206 uint32 clkstretch; 206 u32 clkstretch;
207 uint32 pmuwatchdog; 207 u32 pmuwatchdog;
208 uint32 gpiosel; /* 0x638, rev >= 1 */ 208 u32 gpiosel; /* 0x638, rev >= 1 */
209 uint32 gpioenable; /* 0x63c, rev >= 1 */ 209 u32 gpioenable; /* 0x63c, rev >= 1 */
210 uint32 res_req_timer_sel; 210 u32 res_req_timer_sel;
211 uint32 res_req_timer; 211 u32 res_req_timer;
212 uint32 res_req_mask; 212 u32 res_req_mask;
213 uint32 PAD; 213 u32 PAD;
214 uint32 chipcontrol_addr; /* 0x650 */ 214 u32 chipcontrol_addr; /* 0x650 */
215 uint32 chipcontrol_data; /* 0x654 */ 215 u32 chipcontrol_data; /* 0x654 */
216 uint32 regcontrol_addr; 216 u32 regcontrol_addr;
217 uint32 regcontrol_data; 217 u32 regcontrol_data;
218 uint32 pllcontrol_addr; 218 u32 pllcontrol_addr;
219 uint32 pllcontrol_data; 219 u32 pllcontrol_data;
220 uint32 pmustrapopt; /* 0x668, corerev >= 28 */ 220 u32 pmustrapopt; /* 0x668, corerev >= 28 */
221 uint32 pmu_xtalfreq; /* 0x66C, pmurev >= 10 */ 221 u32 pmu_xtalfreq; /* 0x66C, pmurev >= 10 */
222 uint32 PAD[100]; 222 u32 PAD[100];
223 u16 sromotp[768]; 223 u16 sromotp[768];
224} chipcregs_t; 224} chipcregs_t;
225 225
diff --git a/drivers/staging/brcm80211/include/sbconfig.h b/drivers/staging/brcm80211/include/sbconfig.h
index c296f60eef9..5247f01ec36 100644
--- a/drivers/staging/brcm80211/include/sbconfig.h
+++ b/drivers/staging/brcm80211/include/sbconfig.h
@@ -74,43 +74,43 @@
74#ifndef _LANGUAGE_ASSEMBLY 74#ifndef _LANGUAGE_ASSEMBLY
75 75
76typedef volatile struct _sbconfig { 76typedef volatile struct _sbconfig {
77 uint32 PAD[2]; 77 u32 PAD[2];
78 uint32 sbipsflag; /* initiator port ocp slave flag */ 78 u32 sbipsflag; /* initiator port ocp slave flag */
79 uint32 PAD[3]; 79 u32 PAD[3];
80 uint32 sbtpsflag; /* target port ocp slave flag */ 80 u32 sbtpsflag; /* target port ocp slave flag */
81 uint32 PAD[11]; 81 u32 PAD[11];
82 uint32 sbtmerrloga; /* (sonics >= 2.3) */ 82 u32 sbtmerrloga; /* (sonics >= 2.3) */
83 uint32 PAD; 83 u32 PAD;
84 uint32 sbtmerrlog; /* (sonics >= 2.3) */ 84 u32 sbtmerrlog; /* (sonics >= 2.3) */
85 uint32 PAD[3]; 85 u32 PAD[3];
86 uint32 sbadmatch3; /* address match3 */ 86 u32 sbadmatch3; /* address match3 */
87 uint32 PAD; 87 u32 PAD;
88 uint32 sbadmatch2; /* address match2 */ 88 u32 sbadmatch2; /* address match2 */
89 uint32 PAD; 89 u32 PAD;
90 uint32 sbadmatch1; /* address match1 */ 90 u32 sbadmatch1; /* address match1 */
91 uint32 PAD[7]; 91 u32 PAD[7];
92 uint32 sbimstate; /* initiator agent state */ 92 u32 sbimstate; /* initiator agent state */
93 uint32 sbintvec; /* interrupt mask */ 93 u32 sbintvec; /* interrupt mask */
94 uint32 sbtmstatelow; /* target state */ 94 u32 sbtmstatelow; /* target state */
95 uint32 sbtmstatehigh; /* target state */ 95 u32 sbtmstatehigh; /* target state */
96 uint32 sbbwa0; /* bandwidth allocation table0 */ 96 u32 sbbwa0; /* bandwidth allocation table0 */
97 uint32 PAD; 97 u32 PAD;
98 uint32 sbimconfiglow; /* initiator configuration */ 98 u32 sbimconfiglow; /* initiator configuration */
99 uint32 sbimconfighigh; /* initiator configuration */ 99 u32 sbimconfighigh; /* initiator configuration */
100 uint32 sbadmatch0; /* address match0 */ 100 u32 sbadmatch0; /* address match0 */
101 uint32 PAD; 101 u32 PAD;
102 uint32 sbtmconfiglow; /* target configuration */ 102 u32 sbtmconfiglow; /* target configuration */
103 uint32 sbtmconfighigh; /* target configuration */ 103 u32 sbtmconfighigh; /* target configuration */
104 uint32 sbbconfig; /* broadcast configuration */ 104 u32 sbbconfig; /* broadcast configuration */
105 uint32 PAD; 105 u32 PAD;
106 uint32 sbbstate; /* broadcast state */ 106 u32 sbbstate; /* broadcast state */
107 uint32 PAD[3]; 107 u32 PAD[3];
108 uint32 sbactcnfg; /* activate configuration */ 108 u32 sbactcnfg; /* activate configuration */
109 uint32 PAD[3]; 109 u32 PAD[3];
110 uint32 sbflagst; /* current sbflags */ 110 u32 sbflagst; /* current sbflags */
111 uint32 PAD[3]; 111 u32 PAD[3];
112 uint32 sbidlow; /* identification */ 112 u32 sbidlow; /* identification */
113 uint32 sbidhigh; /* identification */ 113 u32 sbidhigh; /* identification */
114} sbconfig_t; 114} sbconfig_t;
115 115
116#endif /* _LANGUAGE_ASSEMBLY */ 116#endif /* _LANGUAGE_ASSEMBLY */
diff --git a/drivers/staging/brcm80211/include/sbhnddma.h b/drivers/staging/brcm80211/include/sbhnddma.h
index 34e78fad515..09e6d33ee57 100644
--- a/drivers/staging/brcm80211/include/sbhnddma.h
+++ b/drivers/staging/brcm80211/include/sbhnddma.h
@@ -27,10 +27,10 @@
27 27
28/* dma registers per channel(xmt or rcv) */ 28/* dma registers per channel(xmt or rcv) */
29typedef volatile struct { 29typedef volatile struct {
30 uint32 control; /* enable, et al */ 30 u32 control; /* enable, et al */
31 uint32 addr; /* descriptor ring base address (4K aligned) */ 31 u32 addr; /* descriptor ring base address (4K aligned) */
32 uint32 ptr; /* last descriptor posted to chip */ 32 u32 ptr; /* last descriptor posted to chip */
33 uint32 status; /* current active descriptor, et al */ 33 u32 status; /* current active descriptor, et al */
34} dma32regs_t; 34} dma32regs_t;
35 35
36typedef volatile struct { 36typedef volatile struct {
@@ -39,10 +39,10 @@ typedef volatile struct {
39} dma32regp_t; 39} dma32regp_t;
40 40
41typedef volatile struct { /* diag access */ 41typedef volatile struct { /* diag access */
42 uint32 fifoaddr; /* diag address */ 42 u32 fifoaddr; /* diag address */
43 uint32 fifodatalow; /* low 32bits of data */ 43 u32 fifodatalow; /* low 32bits of data */
44 uint32 fifodatahigh; /* high 32bits of data */ 44 u32 fifodatahigh; /* high 32bits of data */
45 uint32 pad; /* reserved */ 45 u32 pad; /* reserved */
46} dma32diag_t; 46} dma32diag_t;
47 47
48/* 48/*
@@ -50,8 +50,8 @@ typedef volatile struct { /* diag access */
50 * Descriptors are only read by the hardware, never written back. 50 * Descriptors are only read by the hardware, never written back.
51 */ 51 */
52typedef volatile struct { 52typedef volatile struct {
53 uint32 ctrl; /* misc control bits & bufcount */ 53 u32 ctrl; /* misc control bits & bufcount */
54 uint32 addr; /* data buffer address */ 54 u32 addr; /* data buffer address */
55} dma32dd_t; 55} dma32dd_t;
56 56
57/* 57/*
@@ -64,12 +64,12 @@ typedef volatile struct {
64#define D32MAXDD (D32MAXRINGSZ / sizeof (dma32dd_t)) 64#define D32MAXDD (D32MAXRINGSZ / sizeof (dma32dd_t))
65 65
66/* transmit channel control */ 66/* transmit channel control */
67#define XC_XE ((uint32)1 << 0) /* transmit enable */ 67#define XC_XE ((u32)1 << 0) /* transmit enable */
68#define XC_SE ((uint32)1 << 1) /* transmit suspend request */ 68#define XC_SE ((u32)1 << 1) /* transmit suspend request */
69#define XC_LE ((uint32)1 << 2) /* loopback enable */ 69#define XC_LE ((u32)1 << 2) /* loopback enable */
70#define XC_FL ((uint32)1 << 4) /* flush request */ 70#define XC_FL ((u32)1 << 4) /* flush request */
71#define XC_PD ((uint32)1 << 11) /* parity check disable */ 71#define XC_PD ((u32)1 << 11) /* parity check disable */
72#define XC_AE ((uint32)3 << 16) /* address extension bits */ 72#define XC_AE ((u32)3 << 16) /* address extension bits */
73#define XC_AE_SHIFT 16 73#define XC_AE_SHIFT 16
74 74
75/* transmit descriptor table pointer */ 75/* transmit descriptor table pointer */
@@ -95,14 +95,14 @@ typedef volatile struct {
95#define XS_AD_SHIFT 20 95#define XS_AD_SHIFT 20
96 96
97/* receive channel control */ 97/* receive channel control */
98#define RC_RE ((uint32)1 << 0) /* receive enable */ 98#define RC_RE ((u32)1 << 0) /* receive enable */
99#define RC_RO_MASK 0xfe /* receive frame offset */ 99#define RC_RO_MASK 0xfe /* receive frame offset */
100#define RC_RO_SHIFT 1 100#define RC_RO_SHIFT 1
101#define RC_FM ((uint32)1 << 8) /* direct fifo receive (pio) mode */ 101#define RC_FM ((u32)1 << 8) /* direct fifo receive (pio) mode */
102#define RC_SH ((uint32)1 << 9) /* separate rx header descriptor enable */ 102#define RC_SH ((u32)1 << 9) /* separate rx header descriptor enable */
103#define RC_OC ((uint32)1 << 10) /* overflow continue */ 103#define RC_OC ((u32)1 << 10) /* overflow continue */
104#define RC_PD ((uint32)1 << 11) /* parity check disable */ 104#define RC_PD ((u32)1 << 11) /* parity check disable */
105#define RC_AE ((uint32)3 << 16) /* address extension bits */ 105#define RC_AE ((u32)3 << 16) /* address extension bits */
106#define RC_AE_SHIFT 16 106#define RC_AE_SHIFT 16
107 107
108/* receive descriptor table pointer */ 108/* receive descriptor table pointer */
@@ -143,13 +143,13 @@ typedef volatile struct {
143 143
144/* descriptor control flags */ 144/* descriptor control flags */
145#define CTRL_BC_MASK 0x00001fff /* buffer byte count, real data len must <= 4KB */ 145#define CTRL_BC_MASK 0x00001fff /* buffer byte count, real data len must <= 4KB */
146#define CTRL_AE ((uint32)3 << 16) /* address extension bits */ 146#define CTRL_AE ((u32)3 << 16) /* address extension bits */
147#define CTRL_AE_SHIFT 16 147#define CTRL_AE_SHIFT 16
148#define CTRL_PARITY ((uint32)3 << 18) /* parity bit */ 148#define CTRL_PARITY ((u32)3 << 18) /* parity bit */
149#define CTRL_EOT ((uint32)1 << 28) /* end of descriptor table */ 149#define CTRL_EOT ((u32)1 << 28) /* end of descriptor table */
150#define CTRL_IOC ((uint32)1 << 29) /* interrupt on completion */ 150#define CTRL_IOC ((u32)1 << 29) /* interrupt on completion */
151#define CTRL_EOF ((uint32)1 << 30) /* end of frame */ 151#define CTRL_EOF ((u32)1 << 30) /* end of frame */
152#define CTRL_SOF ((uint32)1 << 31) /* start of frame */ 152#define CTRL_SOF ((u32)1 << 31) /* start of frame */
153 153
154/* control flags in the range [27:20] are core-specific and not defined here */ 154/* control flags in the range [27:20] are core-specific and not defined here */
155#define CTRL_CORE_MASK 0x0ff00000 155#define CTRL_CORE_MASK 0x0ff00000
@@ -158,12 +158,12 @@ typedef volatile struct {
158 158
159/* dma registers per channel(xmt or rcv) */ 159/* dma registers per channel(xmt or rcv) */
160typedef volatile struct { 160typedef volatile struct {
161 uint32 control; /* enable, et al */ 161 u32 control; /* enable, et al */
162 uint32 ptr; /* last descriptor posted to chip */ 162 u32 ptr; /* last descriptor posted to chip */
163 uint32 addrlow; /* descriptor ring base address low 32-bits (8K aligned) */ 163 u32 addrlow; /* descriptor ring base address low 32-bits (8K aligned) */
164 uint32 addrhigh; /* descriptor ring base address bits 63:32 (8K aligned) */ 164 u32 addrhigh; /* descriptor ring base address bits 63:32 (8K aligned) */
165 uint32 status0; /* current descriptor, xmt state */ 165 u32 status0; /* current descriptor, xmt state */
166 uint32 status1; /* active descriptor, xmt error */ 166 u32 status1; /* active descriptor, xmt error */
167} dma64regs_t; 167} dma64regs_t;
168 168
169typedef volatile struct { 169typedef volatile struct {
@@ -172,10 +172,10 @@ typedef volatile struct {
172} dma64regp_t; 172} dma64regp_t;
173 173
174typedef volatile struct { /* diag access */ 174typedef volatile struct { /* diag access */
175 uint32 fifoaddr; /* diag address */ 175 u32 fifoaddr; /* diag address */
176 uint32 fifodatalow; /* low 32bits of data */ 176 u32 fifodatalow; /* low 32bits of data */
177 uint32 fifodatahigh; /* high 32bits of data */ 177 u32 fifodatahigh; /* high 32bits of data */
178 uint32 pad; /* reserved */ 178 u32 pad; /* reserved */
179} dma64diag_t; 179} dma64diag_t;
180 180
181/* 181/*
@@ -183,10 +183,10 @@ typedef volatile struct { /* diag access */
183 * Descriptors are only read by the hardware, never written back. 183 * Descriptors are only read by the hardware, never written back.
184 */ 184 */
185typedef volatile struct { 185typedef volatile struct {
186 uint32 ctrl1; /* misc control bits & bufcount */ 186 u32 ctrl1; /* misc control bits & bufcount */
187 uint32 ctrl2; /* buffer count and address extension */ 187 u32 ctrl2; /* buffer count and address extension */
188 uint32 addrlow; /* memory address of the date buffer, bits 31:0 */ 188 u32 addrlow; /* memory address of the date buffer, bits 31:0 */
189 uint32 addrhigh; /* memory address of the date buffer, bits 63:32 */ 189 u32 addrhigh; /* memory address of the date buffer, bits 63:32 */
190} dma64dd_t; 190} dma64dd_t;
191 191
192/* 192/*
@@ -287,10 +287,10 @@ typedef volatile struct {
287 287
288/* descriptor control flags 1 */ 288/* descriptor control flags 1 */
289#define D64_CTRL_COREFLAGS 0x0ff00000 /* core specific flags */ 289#define D64_CTRL_COREFLAGS 0x0ff00000 /* core specific flags */
290#define D64_CTRL1_EOT ((uint32)1 << 28) /* end of descriptor table */ 290#define D64_CTRL1_EOT ((u32)1 << 28) /* end of descriptor table */
291#define D64_CTRL1_IOC ((uint32)1 << 29) /* interrupt on completion */ 291#define D64_CTRL1_IOC ((u32)1 << 29) /* interrupt on completion */
292#define D64_CTRL1_EOF ((uint32)1 << 30) /* end of frame */ 292#define D64_CTRL1_EOF ((u32)1 << 30) /* end of frame */
293#define D64_CTRL1_SOF ((uint32)1 << 31) /* start of frame */ 293#define D64_CTRL1_SOF ((u32)1 << 31) /* start of frame */
294 294
295/* descriptor control flags 2 */ 295/* descriptor control flags 2 */
296#define D64_CTRL2_BC_MASK 0x00007fff /* buffer byte count. real data len must <= 16KB */ 296#define D64_CTRL2_BC_MASK 0x00007fff /* buffer byte count. real data len must <= 16KB */
diff --git a/drivers/staging/brcm80211/include/sbhndpio.h b/drivers/staging/brcm80211/include/sbhndpio.h
index a73367c051d..9eabdb56da7 100644
--- a/drivers/staging/brcm80211/include/sbhndpio.h
+++ b/drivers/staging/brcm80211/include/sbhndpio.h
@@ -39,8 +39,8 @@ typedef volatile struct {
39 39
40/* 4byte-wide pio register set per channel(xmt or rcv) */ 40/* 4byte-wide pio register set per channel(xmt or rcv) */
41typedef volatile struct { 41typedef volatile struct {
42 uint32 fifocontrol; 42 u32 fifocontrol;
43 uint32 fifodata; 43 u32 fifodata;
44} pio4regs_t; 44} pio4regs_t;
45 45
46/* a pair of pio channels(tx and rx) */ 46/* a pair of pio channels(tx and rx) */
diff --git a/drivers/staging/brcm80211/include/sbsdpcmdev.h b/drivers/staging/brcm80211/include/sbsdpcmdev.h
index ac68e150c88..afd35811d4a 100644
--- a/drivers/staging/brcm80211/include/sbsdpcmdev.h
+++ b/drivers/staging/brcm80211/include/sbsdpcmdev.h
@@ -26,38 +26,38 @@
26 26
27typedef volatile struct { 27typedef volatile struct {
28 dma64regs_t xmt; /* dma tx */ 28 dma64regs_t xmt; /* dma tx */
29 uint32 PAD[2]; 29 u32 PAD[2];
30 dma64regs_t rcv; /* dma rx */ 30 dma64regs_t rcv; /* dma rx */
31 uint32 PAD[2]; 31 u32 PAD[2];
32} dma64p_t; 32} dma64p_t;
33 33
34/* dma64 sdiod corerev >= 1 */ 34/* dma64 sdiod corerev >= 1 */
35typedef volatile struct { 35typedef volatile struct {
36 dma64p_t dma64regs[2]; 36 dma64p_t dma64regs[2];
37 dma64diag_t dmafifo; /* DMA Diagnostic Regs, 0x280-0x28c */ 37 dma64diag_t dmafifo; /* DMA Diagnostic Regs, 0x280-0x28c */
38 uint32 PAD[92]; 38 u32 PAD[92];
39} sdiodma64_t; 39} sdiodma64_t;
40 40
41/* dma32 sdiod corerev == 0 */ 41/* dma32 sdiod corerev == 0 */
42typedef volatile struct { 42typedef volatile struct {
43 dma32regp_t dma32regs[2]; /* dma tx & rx, 0x200-0x23c */ 43 dma32regp_t dma32regs[2]; /* dma tx & rx, 0x200-0x23c */
44 dma32diag_t dmafifo; /* DMA Diagnostic Regs, 0x240-0x24c */ 44 dma32diag_t dmafifo; /* DMA Diagnostic Regs, 0x240-0x24c */
45 uint32 PAD[108]; 45 u32 PAD[108];
46} sdiodma32_t; 46} sdiodma32_t;
47 47
48/* dma32 regs for pcmcia core */ 48/* dma32 regs for pcmcia core */
49typedef volatile struct { 49typedef volatile struct {
50 dma32regp_t dmaregs; /* DMA Regs, 0x200-0x21c, rev8 */ 50 dma32regp_t dmaregs; /* DMA Regs, 0x200-0x21c, rev8 */
51 dma32diag_t dmafifo; /* DMA Diagnostic Regs, 0x220-0x22c */ 51 dma32diag_t dmafifo; /* DMA Diagnostic Regs, 0x220-0x22c */
52 uint32 PAD[116]; 52 u32 PAD[116];
53} pcmdma32_t; 53} pcmdma32_t;
54 54
55/* core registers */ 55/* core registers */
56typedef volatile struct { 56typedef volatile struct {
57 uint32 corecontrol; /* CoreControl, 0x000, rev8 */ 57 u32 corecontrol; /* CoreControl, 0x000, rev8 */
58 uint32 corestatus; /* CoreStatus, 0x004, rev8 */ 58 u32 corestatus; /* CoreStatus, 0x004, rev8 */
59 uint32 PAD[1]; 59 u32 PAD[1];
60 uint32 biststatus; /* BistStatus, 0x00c, rev8 */ 60 u32 biststatus; /* BistStatus, 0x00c, rev8 */
61 61
62 /* PCMCIA access */ 62 /* PCMCIA access */
63 u16 pcmciamesportaladdr; /* PcmciaMesPortalAddr, 0x010, rev8 */ 63 u16 pcmciamesportaladdr; /* PcmciaMesPortalAddr, 0x010, rev8 */
@@ -70,21 +70,21 @@ typedef volatile struct {
70 u16 PAD[1]; 70 u16 PAD[1];
71 71
72 /* interrupt */ 72 /* interrupt */
73 uint32 intstatus; /* IntStatus, 0x020, rev8 */ 73 u32 intstatus; /* IntStatus, 0x020, rev8 */
74 uint32 hostintmask; /* IntHostMask, 0x024, rev8 */ 74 u32 hostintmask; /* IntHostMask, 0x024, rev8 */
75 uint32 intmask; /* IntSbMask, 0x028, rev8 */ 75 u32 intmask; /* IntSbMask, 0x028, rev8 */
76 uint32 sbintstatus; /* SBIntStatus, 0x02c, rev8 */ 76 u32 sbintstatus; /* SBIntStatus, 0x02c, rev8 */
77 uint32 sbintmask; /* SBIntMask, 0x030, rev8 */ 77 u32 sbintmask; /* SBIntMask, 0x030, rev8 */
78 uint32 funcintmask; /* SDIO Function Interrupt Mask, SDIO rev4 */ 78 u32 funcintmask; /* SDIO Function Interrupt Mask, SDIO rev4 */
79 uint32 PAD[2]; 79 u32 PAD[2];
80 uint32 tosbmailbox; /* ToSBMailbox, 0x040, rev8 */ 80 u32 tosbmailbox; /* ToSBMailbox, 0x040, rev8 */
81 uint32 tohostmailbox; /* ToHostMailbox, 0x044, rev8 */ 81 u32 tohostmailbox; /* ToHostMailbox, 0x044, rev8 */
82 uint32 tosbmailboxdata; /* ToSbMailboxData, 0x048, rev8 */ 82 u32 tosbmailboxdata; /* ToSbMailboxData, 0x048, rev8 */
83 uint32 tohostmailboxdata; /* ToHostMailboxData, 0x04c, rev8 */ 83 u32 tohostmailboxdata; /* ToHostMailboxData, 0x04c, rev8 */
84 84
85 /* synchronized access to registers in SDIO clock domain */ 85 /* synchronized access to registers in SDIO clock domain */
86 uint32 sdioaccess; /* SdioAccess, 0x050, rev8 */ 86 u32 sdioaccess; /* SdioAccess, 0x050, rev8 */
87 uint32 PAD[3]; 87 u32 PAD[3];
88 88
89 /* PCMCIA frame control */ 89 /* PCMCIA frame control */
90 u8 pcmciaframectrl; /* pcmciaFrameCtrl, 0x060, rev8 */ 90 u8 pcmciaframectrl; /* pcmciaFrameCtrl, 0x060, rev8 */
@@ -93,25 +93,25 @@ typedef volatile struct {
93 u8 PAD[155]; 93 u8 PAD[155];
94 94
95 /* interrupt batching control */ 95 /* interrupt batching control */
96 uint32 intrcvlazy; /* IntRcvLazy, 0x100, rev8 */ 96 u32 intrcvlazy; /* IntRcvLazy, 0x100, rev8 */
97 uint32 PAD[3]; 97 u32 PAD[3];
98 98
99 /* counters */ 99 /* counters */
100 uint32 cmd52rd; /* Cmd52RdCount, 0x110, rev8, SDIO: cmd52 reads */ 100 u32 cmd52rd; /* Cmd52RdCount, 0x110, rev8, SDIO: cmd52 reads */
101 uint32 cmd52wr; /* Cmd52WrCount, 0x114, rev8, SDIO: cmd52 writes */ 101 u32 cmd52wr; /* Cmd52WrCount, 0x114, rev8, SDIO: cmd52 writes */
102 uint32 cmd53rd; /* Cmd53RdCount, 0x118, rev8, SDIO: cmd53 reads */ 102 u32 cmd53rd; /* Cmd53RdCount, 0x118, rev8, SDIO: cmd53 reads */
103 uint32 cmd53wr; /* Cmd53WrCount, 0x11c, rev8, SDIO: cmd53 writes */ 103 u32 cmd53wr; /* Cmd53WrCount, 0x11c, rev8, SDIO: cmd53 writes */
104 uint32 abort; /* AbortCount, 0x120, rev8, SDIO: aborts */ 104 u32 abort; /* AbortCount, 0x120, rev8, SDIO: aborts */
105 uint32 datacrcerror; /* DataCrcErrorCount, 0x124, rev8, SDIO: frames w/bad CRC */ 105 u32 datacrcerror; /* DataCrcErrorCount, 0x124, rev8, SDIO: frames w/bad CRC */
106 uint32 rdoutofsync; /* RdOutOfSyncCount, 0x128, rev8, SDIO/PCMCIA: Rd Frm OOS */ 106 u32 rdoutofsync; /* RdOutOfSyncCount, 0x128, rev8, SDIO/PCMCIA: Rd Frm OOS */
107 uint32 wroutofsync; /* RdOutOfSyncCount, 0x12c, rev8, SDIO/PCMCIA: Wr Frm OOS */ 107 u32 wroutofsync; /* RdOutOfSyncCount, 0x12c, rev8, SDIO/PCMCIA: Wr Frm OOS */
108 uint32 writebusy; /* WriteBusyCount, 0x130, rev8, SDIO: dev asserted "busy" */ 108 u32 writebusy; /* WriteBusyCount, 0x130, rev8, SDIO: dev asserted "busy" */
109 uint32 readwait; /* ReadWaitCount, 0x134, rev8, SDIO: read: no data avail */ 109 u32 readwait; /* ReadWaitCount, 0x134, rev8, SDIO: read: no data avail */
110 uint32 readterm; /* ReadTermCount, 0x138, rev8, SDIO: rd frm terminates */ 110 u32 readterm; /* ReadTermCount, 0x138, rev8, SDIO: rd frm terminates */
111 uint32 writeterm; /* WriteTermCount, 0x13c, rev8, SDIO: wr frm terminates */ 111 u32 writeterm; /* WriteTermCount, 0x13c, rev8, SDIO: wr frm terminates */
112 uint32 PAD[40]; 112 u32 PAD[40];
113 uint32 clockctlstatus; /* ClockCtlStatus, 0x1e0, rev8 */ 113 u32 clockctlstatus; /* ClockCtlStatus, 0x1e0, rev8 */
114 uint32 PAD[7]; 114 u32 PAD[7];
115 115
116 /* DMA engines */ 116 /* DMA engines */
117 volatile union { 117 volatile union {
@@ -141,7 +141,7 @@ typedef volatile struct {
141 141
142 /* sprom "size" & "blank" info */ 142 /* sprom "size" & "blank" info */
143 u16 spromstatus; /* SPROMStatus, 0x7BE, rev2 */ 143 u16 spromstatus; /* SPROMStatus, 0x7BE, rev2 */
144 uint32 PAD[464]; 144 u32 PAD[464];
145 145
146 /* Sonics SiliconBackplane registers */ 146 /* Sonics SiliconBackplane registers */
147 sbconfig_t sbconfig; /* SbConfig Regs, 0xf00-0xfff, rev8 */ 147 sbconfig_t sbconfig; /* SbConfig Regs, 0xf00-0xfff, rev8 */
diff --git a/drivers/staging/brcm80211/include/sbsocram.h b/drivers/staging/brcm80211/include/sbsocram.h
index 7b09be9d58b..0cfe9852b27 100644
--- a/drivers/staging/brcm80211/include/sbsocram.h
+++ b/drivers/staging/brcm80211/include/sbsocram.h
@@ -28,34 +28,34 @@
28 28
29/* Memcsocram core registers */ 29/* Memcsocram core registers */
30typedef volatile struct sbsocramregs { 30typedef volatile struct sbsocramregs {
31 uint32 coreinfo; 31 u32 coreinfo;
32 uint32 bwalloc; 32 u32 bwalloc;
33 uint32 extracoreinfo; 33 u32 extracoreinfo;
34 uint32 biststat; 34 u32 biststat;
35 uint32 bankidx; 35 u32 bankidx;
36 uint32 standbyctrl; 36 u32 standbyctrl;
37 37
38 uint32 errlogstatus; /* rev 6 */ 38 u32 errlogstatus; /* rev 6 */
39 uint32 errlogaddr; /* rev 6 */ 39 u32 errlogaddr; /* rev 6 */
40 /* used for patching rev 3 & 5 */ 40 /* used for patching rev 3 & 5 */
41 uint32 cambankidx; 41 u32 cambankidx;
42 uint32 cambankstandbyctrl; 42 u32 cambankstandbyctrl;
43 uint32 cambankpatchctrl; 43 u32 cambankpatchctrl;
44 uint32 cambankpatchtblbaseaddr; 44 u32 cambankpatchtblbaseaddr;
45 uint32 cambankcmdreg; 45 u32 cambankcmdreg;
46 uint32 cambankdatareg; 46 u32 cambankdatareg;
47 uint32 cambankmaskreg; 47 u32 cambankmaskreg;
48 uint32 PAD[1]; 48 u32 PAD[1];
49 uint32 bankinfo; /* corev 8 */ 49 u32 bankinfo; /* corev 8 */
50 uint32 PAD[15]; 50 u32 PAD[15];
51 uint32 extmemconfig; 51 u32 extmemconfig;
52 uint32 extmemparitycsr; 52 u32 extmemparitycsr;
53 uint32 extmemparityerrdata; 53 u32 extmemparityerrdata;
54 uint32 extmemparityerrcnt; 54 u32 extmemparityerrcnt;
55 uint32 extmemwrctrlandsize; 55 u32 extmemwrctrlandsize;
56 uint32 PAD[84]; 56 u32 PAD[84];
57 uint32 workaround; 57 u32 workaround;
58 uint32 pwrctl; /* corerev >= 2 */ 58 u32 pwrctl; /* corerev >= 2 */
59} sbsocramregs_t; 59} sbsocramregs_t;
60 60
61#endif /* _LANGUAGE_ASSEMBLY */ 61#endif /* _LANGUAGE_ASSEMBLY */
diff --git a/drivers/staging/brcm80211/include/siutils.h b/drivers/staging/brcm80211/include/siutils.h
index 3544583b30a..c13bf93f9c5 100644
--- a/drivers/staging/brcm80211/include/siutils.h
+++ b/drivers/staging/brcm80211/include/siutils.h
@@ -34,10 +34,10 @@ struct si_pub {
34 uint buscorerev; /* buscore rev */ 34 uint buscorerev; /* buscore rev */
35 uint buscoreidx; /* buscore index */ 35 uint buscoreidx; /* buscore index */
36 int ccrev; /* chip common core rev */ 36 int ccrev; /* chip common core rev */
37 uint32 cccaps; /* chip common capabilities */ 37 u32 cccaps; /* chip common capabilities */
38 uint32 cccaps_ext; /* chip common capabilities extension */ 38 u32 cccaps_ext; /* chip common capabilities extension */
39 int pmurev; /* pmu core rev */ 39 int pmurev; /* pmu core rev */
40 uint32 pmucaps; /* pmu capabilities */ 40 u32 pmucaps; /* pmu capabilities */
41 uint boardtype; /* board type */ 41 uint boardtype; /* board type */
42 uint boardvendor; /* board vendor */ 42 uint boardvendor; /* board vendor */
43 uint boardflags; /* board flags */ 43 uint boardflags; /* board flags */
@@ -45,7 +45,7 @@ struct si_pub {
45 uint chip; /* chip number */ 45 uint chip; /* chip number */
46 uint chiprev; /* chip revision */ 46 uint chiprev; /* chip revision */
47 uint chippkg; /* chip package option */ 47 uint chippkg; /* chip package option */
48 uint32 chipst; /* chip status */ 48 u32 chipst; /* chip status */
49 bool issim; /* chip is in simulation or emulation */ 49 bool issim; /* chip is in simulation or emulation */
50 uint socirev; /* SOC interconnect rev */ 50 uint socirev; /* SOC interconnect rev */
51 bool pci_pr32414; 51 bool pci_pr32414;
@@ -122,7 +122,7 @@ typedef const struct si_pub si_t;
122#define CCPLL_ENAB(sih) ((sih)->cccaps & CC_CAP_PLL_MASK) 122#define CCPLL_ENAB(sih) ((sih)->cccaps & CC_CAP_PLL_MASK)
123#endif 123#endif
124 124
125typedef void (*gpio_handler_t) (uint32 stat, void *arg); 125typedef void (*gpio_handler_t) (u32 stat, void *arg);
126 126
127/* External PA enable mask */ 127/* External PA enable mask */
128#define GPIO_CTRL_EPA_EN_MASK 0x40 128#define GPIO_CTRL_EPA_EN_MASK 0x40
@@ -141,9 +141,9 @@ extern uint si_corerev(si_t *sih);
141extern void *si_osh(si_t *sih); 141extern void *si_osh(si_t *sih);
142extern uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, 142extern uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask,
143 uint val); 143 uint val);
144extern void si_write_wrapperreg(si_t *sih, uint32 offset, uint32 val); 144extern void si_write_wrapperreg(si_t *sih, u32 offset, u32 val);
145extern uint32 si_core_cflags(si_t *sih, uint32 mask, uint32 val); 145extern u32 si_core_cflags(si_t *sih, u32 mask, u32 val);
146extern uint32 si_core_sflags(si_t *sih, uint32 mask, uint32 val); 146extern u32 si_core_sflags(si_t *sih, u32 mask, u32 val);
147extern bool si_iscoreup(si_t *sih); 147extern bool si_iscoreup(si_t *sih);
148extern uint si_findcoreidx(si_t *sih, uint coreid, uint coreunit); 148extern uint si_findcoreidx(si_t *sih, uint coreid, uint coreunit);
149#ifndef BCMSDIO 149#ifndef BCMSDIO
@@ -153,10 +153,10 @@ extern void *si_setcore(si_t *sih, uint coreid, uint coreunit);
153extern void *si_switch_core(si_t *sih, uint coreid, uint *origidx, 153extern void *si_switch_core(si_t *sih, uint coreid, uint *origidx,
154 uint *intr_val); 154 uint *intr_val);
155extern void si_restore_core(si_t *sih, uint coreid, uint intr_val); 155extern void si_restore_core(si_t *sih, uint coreid, uint intr_val);
156extern void si_core_reset(si_t *sih, uint32 bits, uint32 resetbits); 156extern void si_core_reset(si_t *sih, u32 bits, u32 resetbits);
157extern void si_core_disable(si_t *sih, uint32 bits); 157extern void si_core_disable(si_t *sih, u32 bits);
158extern uint32 si_alp_clock(si_t *sih); 158extern u32 si_alp_clock(si_t *sih);
159extern uint32 si_ilp_clock(si_t *sih); 159extern u32 si_ilp_clock(si_t *sih);
160extern void si_pci_setup(si_t *sih, uint coremask); 160extern void si_pci_setup(si_t *sih, uint coremask);
161extern void si_setint(si_t *sih, int siflag); 161extern void si_setint(si_t *sih, int siflag);
162extern bool si_backplane64(si_t *sih); 162extern bool si_backplane64(si_t *sih);
@@ -169,10 +169,10 @@ extern u16 si_clkctl_fast_pwrup_delay(si_t *sih);
169extern bool si_clkctl_cc(si_t *sih, uint mode); 169extern bool si_clkctl_cc(si_t *sih, uint mode);
170extern int si_clkctl_xtal(si_t *sih, uint what, bool on); 170extern int si_clkctl_xtal(si_t *sih, uint what, bool on);
171extern bool si_deviceremoved(si_t *sih); 171extern bool si_deviceremoved(si_t *sih);
172extern uint32 si_socram_size(si_t *sih); 172extern u32 si_socram_size(si_t *sih);
173 173
174extern void si_watchdog(si_t *sih, uint ticks); 174extern void si_watchdog(si_t *sih, uint ticks);
175extern uint32 si_gpiocontrol(si_t *sih, uint32 mask, uint32 val, 175extern u32 si_gpiocontrol(si_t *sih, u32 mask, u32 val,
176 u8 priority); 176 u8 priority);
177 177
178#ifdef BCMSDIO 178#ifdef BCMSDIO
@@ -212,15 +212,15 @@ extern void si_sprom_init(si_t *sih);
212 212
213#define IS_SIM(chippkg) ((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID)) 213#define IS_SIM(chippkg) ((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID))
214 214
215typedef uint32(*si_intrsoff_t) (void *intr_arg); 215typedef u32(*si_intrsoff_t) (void *intr_arg);
216typedef void (*si_intrsrestore_t) (void *intr_arg, uint32 arg); 216typedef void (*si_intrsrestore_t) (void *intr_arg, u32 arg);
217typedef bool(*si_intrsenabled_t) (void *intr_arg); 217typedef bool(*si_intrsenabled_t) (void *intr_arg);
218 218
219typedef struct gpioh_item { 219typedef struct gpioh_item {
220 void *arg; 220 void *arg;
221 bool level; 221 bool level;
222 gpio_handler_t handler; 222 gpio_handler_t handler;
223 uint32 event; 223 u32 event;
224 struct gpioh_item *next; 224 struct gpioh_item *next;
225} gpioh_item_t; 225} gpioh_item_t;
226 226
@@ -250,19 +250,19 @@ typedef struct si_info {
250 uint curidx; /* current core index */ 250 uint curidx; /* current core index */
251 uint numcores; /* # discovered cores */ 251 uint numcores; /* # discovered cores */
252 uint coreid[SI_MAXCORES]; /* id of each core */ 252 uint coreid[SI_MAXCORES]; /* id of each core */
253 uint32 coresba[SI_MAXCORES]; /* backplane address of each core */ 253 u32 coresba[SI_MAXCORES]; /* backplane address of each core */
254 void *regs2[SI_MAXCORES]; /* va of each core second register set (usbh20) */ 254 void *regs2[SI_MAXCORES]; /* va of each core second register set (usbh20) */
255 uint32 coresba2[SI_MAXCORES]; /* address of each core second register set (usbh20) */ 255 u32 coresba2[SI_MAXCORES]; /* address of each core second register set (usbh20) */
256 uint32 coresba_size[SI_MAXCORES]; /* backplane address space size */ 256 u32 coresba_size[SI_MAXCORES]; /* backplane address space size */
257 uint32 coresba2_size[SI_MAXCORES]; /* second address space size */ 257 u32 coresba2_size[SI_MAXCORES]; /* second address space size */
258 258
259 void *curwrap; /* current wrapper va */ 259 void *curwrap; /* current wrapper va */
260 void *wrappers[SI_MAXCORES]; /* other cores wrapper va */ 260 void *wrappers[SI_MAXCORES]; /* other cores wrapper va */
261 uint32 wrapba[SI_MAXCORES]; /* address of controlling wrapper */ 261 u32 wrapba[SI_MAXCORES]; /* address of controlling wrapper */
262 262
263 uint32 cia[SI_MAXCORES]; /* erom cia entry for each core */ 263 u32 cia[SI_MAXCORES]; /* erom cia entry for each core */
264 uint32 cib[SI_MAXCORES]; /* erom cia entry for each core */ 264 u32 cib[SI_MAXCORES]; /* erom cia entry for each core */
265 uint32 oob_router; /* oob router registers for axi */ 265 u32 oob_router; /* oob router registers for axi */
266} si_info_t; 266} si_info_t;
267 267
268#define SI_INFO(sih) (si_info_t *)(uintptr)sih 268#define SI_INFO(sih) (si_info_t *)(uintptr)sih
@@ -356,17 +356,17 @@ extern uint ai_corevendor(si_t *sih);
356extern uint ai_corerev(si_t *sih); 356extern uint ai_corerev(si_t *sih);
357extern bool ai_iscoreup(si_t *sih); 357extern bool ai_iscoreup(si_t *sih);
358extern void *ai_setcoreidx(si_t *sih, uint coreidx); 358extern void *ai_setcoreidx(si_t *sih, uint coreidx);
359extern uint32 ai_core_cflags(si_t *sih, uint32 mask, uint32 val); 359extern u32 ai_core_cflags(si_t *sih, u32 mask, u32 val);
360extern void ai_core_cflags_wo(si_t *sih, uint32 mask, uint32 val); 360extern void ai_core_cflags_wo(si_t *sih, u32 mask, u32 val);
361extern uint32 ai_core_sflags(si_t *sih, uint32 mask, uint32 val); 361extern u32 ai_core_sflags(si_t *sih, u32 mask, u32 val);
362extern uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, 362extern uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask,
363 uint val); 363 uint val);
364extern void ai_core_reset(si_t *sih, uint32 bits, uint32 resetbits); 364extern void ai_core_reset(si_t *sih, u32 bits, u32 resetbits);
365extern void ai_core_disable(si_t *sih, uint32 bits); 365extern void ai_core_disable(si_t *sih, u32 bits);
366extern int ai_numaddrspaces(si_t *sih); 366extern int ai_numaddrspaces(si_t *sih);
367extern uint32 ai_addrspace(si_t *sih, uint asidx); 367extern u32 ai_addrspace(si_t *sih, uint asidx);
368extern uint32 ai_addrspacesize(si_t *sih, uint asidx); 368extern u32 ai_addrspacesize(si_t *sih, uint asidx);
369extern void ai_write_wrap_reg(si_t *sih, uint32 offset, uint32 val); 369extern void ai_write_wrap_reg(si_t *sih, u32 offset, u32 val);
370 370
371#ifdef BCMSDIO 371#ifdef BCMSDIO
372#define si_setcoreidx(sih, idx) sb_setcoreidx(sih, idx) 372#define si_setcoreidx(sih, idx) sb_setcoreidx(sih, idx)
diff --git a/drivers/staging/brcm80211/include/spid.h b/drivers/staging/brcm80211/include/spid.h
index 45932be07c1..e0abb843288 100644
--- a/drivers/staging/brcm80211/include/spid.h
+++ b/drivers/staging/brcm80211/include/spid.h
@@ -31,12 +31,12 @@ typedef volatile struct {
31 u8 reset_bp; /* 0x03, reset on wlan/bt backplane reset (corerev >= 1) */ 31 u8 reset_bp; /* 0x03, reset on wlan/bt backplane reset (corerev >= 1) */
32 u16 intr_reg; /* 0x04, Intr status register */ 32 u16 intr_reg; /* 0x04, Intr status register */
33 u16 intr_en_reg; /* 0x06, Intr mask register */ 33 u16 intr_en_reg; /* 0x06, Intr mask register */
34 uint32 status_reg; /* 0x08, RO, Status bits of last spi transfer */ 34 u32 status_reg; /* 0x08, RO, Status bits of last spi transfer */
35 u16 f1_info_reg; /* 0x0c, RO, enabled, ready for data transfer, blocksize */ 35 u16 f1_info_reg; /* 0x0c, RO, enabled, ready for data transfer, blocksize */
36 u16 f2_info_reg; /* 0x0e, RO, enabled, ready for data transfer, blocksize */ 36 u16 f2_info_reg; /* 0x0e, RO, enabled, ready for data transfer, blocksize */
37 u16 f3_info_reg; /* 0x10, RO, enabled, ready for data transfer, blocksize */ 37 u16 f3_info_reg; /* 0x10, RO, enabled, ready for data transfer, blocksize */
38 uint32 test_read; /* 0x14, RO 0xfeedbead signature */ 38 u32 test_read; /* 0x14, RO 0xfeedbead signature */
39 uint32 test_rw; /* 0x18, RW */ 39 u32 test_rw; /* 0x18, RW */
40 u8 resp_delay_f0; /* 0x1c, read resp delay bytes for F0 (corerev >= 3) */ 40 u8 resp_delay_f0; /* 0x1c, read resp delay bytes for F0 (corerev >= 3) */
41 u8 resp_delay_f1; /* 0x1d, read resp delay bytes for F1 (corerev >= 3) */ 41 u8 resp_delay_f1; /* 0x1d, read resp delay bytes for F1 (corerev >= 3) */
42 u8 resp_delay_f2; /* 0x1e, read resp delay bytes for F2 (corerev >= 3) */ 42 u8 resp_delay_f2; /* 0x1e, read resp delay bytes for F2 (corerev >= 3) */
diff --git a/drivers/staging/brcm80211/include/typedefs.h b/drivers/staging/brcm80211/include/typedefs.h
index 6660e2323cf..8ed792b0395 100644
--- a/drivers/staging/brcm80211/include/typedefs.h
+++ b/drivers/staging/brcm80211/include/typedefs.h
@@ -44,10 +44,6 @@ typedef unsigned int uint;
44 44
45/* define [u]int32/64, uintptr */ 45/* define [u]int32/64, uintptr */
46 46
47#ifndef TYPEDEF_UINT32
48typedef unsigned int uint32;
49#endif
50
51#ifndef TYPEDEF_UINTPTR 47#ifndef TYPEDEF_UINTPTR
52typedef unsigned int uintptr; 48typedef unsigned int uintptr;
53#endif 49#endif
@@ -77,7 +73,6 @@ typedef signed int int32;
77#define AUTO (-1) /* Auto = -1 */ 73#define AUTO (-1) /* Auto = -1 */
78 74
79#undef TYPEDEF_UINT 75#undef TYPEDEF_UINT
80#undef TYPEDEF_UINT32
81#undef TYPEDEF_UINTPTR 76#undef TYPEDEF_UINTPTR
82#undef TYPEDEF_INT32 77#undef TYPEDEF_INT32
83 78
diff --git a/drivers/staging/brcm80211/include/wlioctl.h b/drivers/staging/brcm80211/include/wlioctl.h
index fe67367d81a..6ac4f3155bb 100644
--- a/drivers/staging/brcm80211/include/wlioctl.h
+++ b/drivers/staging/brcm80211/include/wlioctl.h
@@ -39,8 +39,8 @@
39#define LEGACY_WL_BSS_INFO_VERSION 107 /* older version of wl_bss_info struct */ 39#define LEGACY_WL_BSS_INFO_VERSION 107 /* older version of wl_bss_info struct */
40 40
41typedef struct wl_bss_info_107 { 41typedef struct wl_bss_info_107 {
42 uint32 version; /* version field */ 42 u32 version; /* version field */
43 uint32 length; /* byte length of data in this record, 43 u32 length; /* byte length of data in this record,
44 * starting at version and including IEs 44 * starting at version and including IEs
45 */ 45 */
46 struct ether_addr BSSID; 46 struct ether_addr BSSID;
@@ -57,7 +57,7 @@ typedef struct wl_bss_info_107 {
57 u8 dtim_period; /* DTIM period */ 57 u8 dtim_period; /* DTIM period */
58 s16 RSSI; /* receive signal strength (in dBm) */ 58 s16 RSSI; /* receive signal strength (in dBm) */
59 s8 phy_noise; /* noise (in dBm) */ 59 s8 phy_noise; /* noise (in dBm) */
60 uint32 ie_length; /* byte length of Information Elements */ 60 u32 ie_length; /* byte length of Information Elements */
61 /* variable length Information Elements */ 61 /* variable length Information Elements */
62} wl_bss_info_107_t; 62} wl_bss_info_107_t;
63 63
@@ -72,8 +72,8 @@ typedef struct wl_bss_info_107 {
72 * next bss_info structure in a vector (in wl_scan_results_t) 72 * next bss_info structure in a vector (in wl_scan_results_t)
73 */ 73 */
74typedef struct wl_bss_info_108 { 74typedef struct wl_bss_info_108 {
75 uint32 version; /* version field */ 75 u32 version; /* version field */
76 uint32 length; /* byte length of data in this record, 76 u32 length; /* byte length of data in this record,
77 * starting at version and including IEs 77 * starting at version and including IEs
78 */ 78 */
79 struct ether_addr BSSID; 79 struct ether_addr BSSID;
@@ -92,15 +92,15 @@ typedef struct wl_bss_info_108 {
92 s8 phy_noise; /* noise (in dBm) */ 92 s8 phy_noise; /* noise (in dBm) */
93 93
94 u8 n_cap; /* BSS is 802.11N Capable */ 94 u8 n_cap; /* BSS is 802.11N Capable */
95 uint32 nbss_cap; /* 802.11N BSS Capabilities (based on HT_CAP_*) */ 95 u32 nbss_cap; /* 802.11N BSS Capabilities (based on HT_CAP_*) */
96 u8 ctl_ch; /* 802.11N BSS control channel number */ 96 u8 ctl_ch; /* 802.11N BSS control channel number */
97 uint32 reserved32[1]; /* Reserved for expansion of BSS properties */ 97 u32 reserved32[1]; /* Reserved for expansion of BSS properties */
98 u8 flags; /* flags */ 98 u8 flags; /* flags */
99 u8 reserved[3]; /* Reserved for expansion of BSS properties */ 99 u8 reserved[3]; /* Reserved for expansion of BSS properties */
100 u8 basic_mcs[MCSSET_LEN]; /* 802.11N BSS required MCS set */ 100 u8 basic_mcs[MCSSET_LEN]; /* 802.11N BSS required MCS set */
101 101
102 u16 ie_offset; /* offset at which IEs start, from beginning */ 102 u16 ie_offset; /* offset at which IEs start, from beginning */
103 uint32 ie_length; /* byte length of Information Elements */ 103 u32 ie_length; /* byte length of Information Elements */
104 /* Add new fields here */ 104 /* Add new fields here */
105 /* variable length Information Elements */ 105 /* variable length Information Elements */
106} wl_bss_info_108_t; 106} wl_bss_info_108_t;
@@ -116,8 +116,8 @@ typedef struct wl_bss_info_108 {
116 * next bss_info structure in a vector (in wl_scan_results_t) 116 * next bss_info structure in a vector (in wl_scan_results_t)
117 */ 117 */
118typedef struct wl_bss_info { 118typedef struct wl_bss_info {
119 uint32 version; /* version field */ 119 u32 version; /* version field */
120 uint32 length; /* byte length of data in this record, 120 u32 length; /* byte length of data in this record,
121 * starting at version and including IEs 121 * starting at version and including IEs
122 */ 122 */
123 struct ether_addr BSSID; 123 struct ether_addr BSSID;
@@ -136,22 +136,22 @@ typedef struct wl_bss_info {
136 s8 phy_noise; /* noise (in dBm) */ 136 s8 phy_noise; /* noise (in dBm) */
137 137
138 u8 n_cap; /* BSS is 802.11N Capable */ 138 u8 n_cap; /* BSS is 802.11N Capable */
139 uint32 nbss_cap; /* 802.11N BSS Capabilities (based on HT_CAP_*) */ 139 u32 nbss_cap; /* 802.11N BSS Capabilities (based on HT_CAP_*) */
140 u8 ctl_ch; /* 802.11N BSS control channel number */ 140 u8 ctl_ch; /* 802.11N BSS control channel number */
141 uint32 reserved32[1]; /* Reserved for expansion of BSS properties */ 141 u32 reserved32[1]; /* Reserved for expansion of BSS properties */
142 u8 flags; /* flags */ 142 u8 flags; /* flags */
143 u8 reserved[3]; /* Reserved for expansion of BSS properties */ 143 u8 reserved[3]; /* Reserved for expansion of BSS properties */
144 u8 basic_mcs[MCSSET_LEN]; /* 802.11N BSS required MCS set */ 144 u8 basic_mcs[MCSSET_LEN]; /* 802.11N BSS required MCS set */
145 145
146 u16 ie_offset; /* offset at which IEs start, from beginning */ 146 u16 ie_offset; /* offset at which IEs start, from beginning */
147 uint32 ie_length; /* byte length of Information Elements */ 147 u32 ie_length; /* byte length of Information Elements */
148 s16 SNR; /* average SNR of during frame reception */ 148 s16 SNR; /* average SNR of during frame reception */
149 /* Add new fields here */ 149 /* Add new fields here */
150 /* variable length Information Elements */ 150 /* variable length Information Elements */
151} wl_bss_info_t; 151} wl_bss_info_t;
152 152
153typedef struct wlc_ssid { 153typedef struct wlc_ssid {
154 uint32 SSID_len; 154 u32 SSID_len;
155 unsigned char SSID[32]; 155 unsigned char SSID[32];
156} wlc_ssid_t; 156} wlc_ssid_t;
157 157
@@ -159,8 +159,8 @@ typedef struct chan_scandata {
159 u8 txpower; 159 u8 txpower;
160 u8 pad; 160 u8 pad;
161 chanspec_t channel; /* Channel num, bw, ctrl_sb and band */ 161 chanspec_t channel; /* Channel num, bw, ctrl_sb and band */
162 uint32 channel_mintime; 162 u32 channel_mintime;
163 uint32 channel_maxtime; 163 u32 channel_maxtime;
164} chan_scandata_t; 164} chan_scandata_t;
165 165
166typedef enum wl_scan_type { 166typedef enum wl_scan_type {
@@ -181,7 +181,7 @@ typedef struct wl_extdscan_params {
181 s8 band; /* band */ 181 s8 band; /* band */
182 s8 pad; 182 s8 pad;
183 wlc_ssid_t ssid[WLC_EXTDSCAN_MAX_SSID]; /* ssid list */ 183 wlc_ssid_t ssid[WLC_EXTDSCAN_MAX_SSID]; /* ssid list */
184 uint32 tx_rate; /* in 500ksec units */ 184 u32 tx_rate; /* in 500ksec units */
185 wl_scan_type_t scan_type; /* enum */ 185 wl_scan_type_t scan_type; /* enum */
186 int32 channel_num; 186 int32 channel_num;
187 chan_scandata_t channel_list[1]; /* list of chandata structs */ 187 chan_scandata_t channel_list[1]; /* list of chandata structs */
@@ -247,7 +247,7 @@ typedef struct wl_scan_params {
247 247
248/* incremental scan struct */ 248/* incremental scan struct */
249typedef struct wl_iscan_params { 249typedef struct wl_iscan_params {
250 uint32 version; 250 u32 version;
251 u16 action; 251 u16 action;
252 u16 scan_duration; 252 u16 scan_duration;
253 wl_scan_params_t params; 253 wl_scan_params_t params;
@@ -257,9 +257,9 @@ typedef struct wl_iscan_params {
257#define WL_ISCAN_PARAMS_FIXED_SIZE (OFFSETOF(wl_iscan_params_t, params) + sizeof(wlc_ssid_t)) 257#define WL_ISCAN_PARAMS_FIXED_SIZE (OFFSETOF(wl_iscan_params_t, params) + sizeof(wlc_ssid_t))
258 258
259typedef struct wl_scan_results { 259typedef struct wl_scan_results {
260 uint32 buflen; 260 u32 buflen;
261 uint32 version; 261 u32 version;
262 uint32 count; 262 u32 count;
263 wl_bss_info_t bss_info[1]; 263 wl_bss_info_t bss_info[1];
264} wl_scan_results_t; 264} wl_scan_results_t;
265 265
@@ -276,7 +276,7 @@ typedef struct wl_scan_results {
276#define ESCAN_REQ_VERSION 1 276#define ESCAN_REQ_VERSION 1
277 277
278typedef struct wl_escan_params { 278typedef struct wl_escan_params {
279 uint32 version; 279 u32 version;
280 u16 action; 280 u16 action;
281 u16 sync_id; 281 u16 sync_id;
282 wl_scan_params_t params; 282 wl_scan_params_t params;
@@ -285,8 +285,8 @@ typedef struct wl_escan_params {
285#define WL_ESCAN_PARAMS_FIXED_SIZE (OFFSETOF(wl_escan_params_t, params) + sizeof(wlc_ssid_t)) 285#define WL_ESCAN_PARAMS_FIXED_SIZE (OFFSETOF(wl_escan_params_t, params) + sizeof(wlc_ssid_t))
286 286
287typedef struct wl_escan_result { 287typedef struct wl_escan_result {
288 uint32 buflen; 288 u32 buflen;
289 uint32 version; 289 u32 version;
290 u16 sync_id; 290 u16 sync_id;
291 u16 bss_count; 291 u16 bss_count;
292 wl_bss_info_t bss_info[1]; 292 wl_bss_info_t bss_info[1];
@@ -296,7 +296,7 @@ typedef struct wl_escan_result {
296 296
297/* incremental scan results struct */ 297/* incremental scan results struct */
298typedef struct wl_iscan_results { 298typedef struct wl_iscan_results {
299 uint32 status; 299 u32 status;
300 wl_scan_results_t results; 300 wl_scan_results_t results;
301} wl_iscan_results_t; 301} wl_iscan_results_t;
302 302
@@ -312,23 +312,23 @@ typedef struct wl_probe_params {
312 312
313#define WL_NUMRATES 16 /* max # of rates in a rateset */ 313#define WL_NUMRATES 16 /* max # of rates in a rateset */
314typedef struct wl_rateset { 314typedef struct wl_rateset {
315 uint32 count; /* # rates in this set */ 315 u32 count; /* # rates in this set */
316 u8 rates[WL_NUMRATES]; /* rates in 500kbps units w/hi bit set if basic */ 316 u8 rates[WL_NUMRATES]; /* rates in 500kbps units w/hi bit set if basic */
317} wl_rateset_t; 317} wl_rateset_t;
318 318
319typedef struct wl_rateset_args { 319typedef struct wl_rateset_args {
320 uint32 count; /* # rates in this set */ 320 u32 count; /* # rates in this set */
321 u8 rates[WL_NUMRATES]; /* rates in 500kbps units w/hi bit set if basic */ 321 u8 rates[WL_NUMRATES]; /* rates in 500kbps units w/hi bit set if basic */
322 u8 mcs[MCSSET_LEN]; /* supported mcs index bit map */ 322 u8 mcs[MCSSET_LEN]; /* supported mcs index bit map */
323} wl_rateset_args_t; 323} wl_rateset_args_t;
324 324
325/* uint32 list */ 325/* u32 list */
326typedef struct wl_uint32_list { 326typedef struct wl_u32_list {
327 /* in - # of elements, out - # of entries */ 327 /* in - # of elements, out - # of entries */
328 uint32 count; 328 u32 count;
329 /* variable length uint32 list */ 329 /* variable length u32 list */
330 uint32 element[1]; 330 u32 element[1];
331} wl_uint32_list_t; 331} wl_u32_list_t;
332 332
333/* used for association with a specific BSSID and chanspec list */ 333/* used for association with a specific BSSID and chanspec list */
334typedef struct wl_assoc_params { 334typedef struct wl_assoc_params {
@@ -415,12 +415,12 @@ typedef struct {
415#define CCA_ERRNO_TOO_FEW 5 /* Only 1 channel was input */ 415#define CCA_ERRNO_TOO_FEW 5 /* Only 1 channel was input */
416 416
417typedef struct { 417typedef struct {
418 uint32 duration; /* millisecs spent sampling this channel */ 418 u32 duration; /* millisecs spent sampling this channel */
419 uint32 congest_ibss; /* millisecs in our bss (presumably this traffic will */ 419 u32 congest_ibss; /* millisecs in our bss (presumably this traffic will */
420 /* move if cur bss moves channels) */ 420 /* move if cur bss moves channels) */
421 uint32 congest_obss; /* traffic not in our bss */ 421 u32 congest_obss; /* traffic not in our bss */
422 uint32 interference; /* millisecs detecting a non 802.11 interferer. */ 422 u32 interference; /* millisecs detecting a non 802.11 interferer. */
423 uint32 timestamp; /* second timestamp */ 423 u32 timestamp; /* second timestamp */
424} cca_congest_t; 424} cca_congest_t;
425 425
426typedef struct { 426typedef struct {
@@ -447,18 +447,18 @@ typedef struct wl_country {
447} wl_country_t; 447} wl_country_t;
448 448
449typedef struct wl_channels_in_country { 449typedef struct wl_channels_in_country {
450 uint32 buflen; 450 u32 buflen;
451 uint32 band; 451 u32 band;
452 char country_abbrev[WLC_CNTRY_BUF_SZ]; 452 char country_abbrev[WLC_CNTRY_BUF_SZ];
453 uint32 count; 453 u32 count;
454 uint32 channel[1]; 454 u32 channel[1];
455} wl_channels_in_country_t; 455} wl_channels_in_country_t;
456 456
457typedef struct wl_country_list { 457typedef struct wl_country_list {
458 uint32 buflen; 458 u32 buflen;
459 uint32 band_set; 459 u32 band_set;
460 uint32 band; 460 u32 band;
461 uint32 count; 461 u32 count;
462 char country_abbrev[1]; 462 char country_abbrev[1];
463} wl_country_list_t; 463} wl_country_list_t;
464 464
@@ -477,15 +477,15 @@ typedef struct wl_rm_req_elt {
477 s8 type; 477 s8 type;
478 s8 flags; 478 s8 flags;
479 chanspec_t chanspec; 479 chanspec_t chanspec;
480 uint32 token; /* token for this measurement */ 480 u32 token; /* token for this measurement */
481 uint32 tsf_h; /* TSF high 32-bits of Measurement start time */ 481 u32 tsf_h; /* TSF high 32-bits of Measurement start time */
482 uint32 tsf_l; /* TSF low 32-bits */ 482 u32 tsf_l; /* TSF low 32-bits */
483 uint32 dur; /* TUs */ 483 u32 dur; /* TUs */
484} wl_rm_req_elt_t; 484} wl_rm_req_elt_t;
485 485
486typedef struct wl_rm_req { 486typedef struct wl_rm_req {
487 uint32 token; /* overall measurement set token */ 487 u32 token; /* overall measurement set token */
488 uint32 count; /* number of measurement requests */ 488 u32 count; /* number of measurement requests */
489 void *cb; /* completion callback function: may be NULL */ 489 void *cb; /* completion callback function: may be NULL */
490 void *cb_arg; /* arg to completion callback function */ 490 void *cb_arg; /* arg to completion callback function */
491 wl_rm_req_elt_t req[1]; /* variable length block of requests */ 491 wl_rm_req_elt_t req[1]; /* variable length block of requests */
@@ -496,11 +496,11 @@ typedef struct wl_rm_rep_elt {
496 s8 type; 496 s8 type;
497 s8 flags; 497 s8 flags;
498 chanspec_t chanspec; 498 chanspec_t chanspec;
499 uint32 token; /* token for this measurement */ 499 u32 token; /* token for this measurement */
500 uint32 tsf_h; /* TSF high 32-bits of Measurement start time */ 500 u32 tsf_h; /* TSF high 32-bits of Measurement start time */
501 uint32 tsf_l; /* TSF low 32-bits */ 501 u32 tsf_l; /* TSF low 32-bits */
502 uint32 dur; /* TUs */ 502 u32 dur; /* TUs */
503 uint32 len; /* byte length of data block */ 503 u32 len; /* byte length of data block */
504 u8 data[1]; /* variable length data block */ 504 u8 data[1]; /* variable length data block */
505} wl_rm_rep_elt_t; 505} wl_rm_rep_elt_t;
506#define WL_RM_REP_ELT_FIXED_LEN 24 /* length excluding data block */ 506#define WL_RM_REP_ELT_FIXED_LEN 24 /* length excluding data block */
@@ -512,8 +512,8 @@ typedef struct wl_rm_rpi_rep {
512} wl_rm_rpi_rep_t; 512} wl_rm_rpi_rep_t;
513 513
514typedef struct wl_rm_rep { 514typedef struct wl_rm_rep {
515 uint32 token; /* overall measurement set token */ 515 u32 token; /* overall measurement set token */
516 uint32 len; /* length of measurement report block */ 516 u32 len; /* length of measurement report block */
517 wl_rm_rep_elt_t rep[1]; /* variable length block of reports */ 517 wl_rm_rep_elt_t rep[1]; /* variable length block of reports */
518} wl_rm_rep_t; 518} wl_rm_rep_t;
519#define WL_RM_REP_FIXED_LEN 8 519#define WL_RM_REP_FIXED_LEN 8
@@ -539,22 +539,22 @@ typedef struct wl_rm_rep {
539#define WL_IBSS_PEER_GROUP_KEY (1 << 6) /* Indicates a group key for a IBSS PEER */ 539#define WL_IBSS_PEER_GROUP_KEY (1 << 6) /* Indicates a group key for a IBSS PEER */
540 540
541typedef struct wl_wsec_key { 541typedef struct wl_wsec_key {
542 uint32 index; /* key index */ 542 u32 index; /* key index */
543 uint32 len; /* key length */ 543 u32 len; /* key length */
544 u8 data[DOT11_MAX_KEY_SIZE]; /* key data */ 544 u8 data[DOT11_MAX_KEY_SIZE]; /* key data */
545 uint32 pad_1[18]; 545 u32 pad_1[18];
546 uint32 algo; /* CRYPTO_ALGO_AES_CCM, CRYPTO_ALGO_WEP128, etc */ 546 u32 algo; /* CRYPTO_ALGO_AES_CCM, CRYPTO_ALGO_WEP128, etc */
547 uint32 flags; /* misc flags */ 547 u32 flags; /* misc flags */
548 uint32 pad_2[2]; 548 u32 pad_2[2];
549 int pad_3; 549 int pad_3;
550 int iv_initialized; /* has IV been initialized already? */ 550 int iv_initialized; /* has IV been initialized already? */
551 int pad_4; 551 int pad_4;
552 /* Rx IV */ 552 /* Rx IV */
553 struct { 553 struct {
554 uint32 hi; /* upper 32 bits of IV */ 554 u32 hi; /* upper 32 bits of IV */
555 u16 lo; /* lower 16 bits of IV */ 555 u16 lo; /* lower 16 bits of IV */
556 } rxiv; 556 } rxiv;
557 uint32 pad_5[2]; 557 u32 pad_5[2];
558 struct ether_addr ea; /* per station */ 558 struct ether_addr ea; /* per station */
559} wl_wsec_key_t; 559} wl_wsec_key_t;
560 560
@@ -602,7 +602,7 @@ typedef struct _pmkid {
602} pmkid_t; 602} pmkid_t;
603 603
604typedef struct _pmkid_list { 604typedef struct _pmkid_list {
605 uint32 npmkid; 605 u32 npmkid;
606 pmkid_t pmkid[1]; 606 pmkid_t pmkid[1];
607} pmkid_list_t; 607} pmkid_list_t;
608 608
@@ -612,13 +612,13 @@ typedef struct _pmkid_cand {
612} pmkid_cand_t; 612} pmkid_cand_t;
613 613
614typedef struct _pmkid_cand_list { 614typedef struct _pmkid_cand_list {
615 uint32 npmkid_cand; 615 u32 npmkid_cand;
616 pmkid_cand_t pmkid_cand[1]; 616 pmkid_cand_t pmkid_cand[1];
617} pmkid_cand_list_t; 617} pmkid_cand_list_t;
618 618
619typedef struct wl_led_info { 619typedef struct wl_led_info {
620 uint32 index; /* led index */ 620 u32 index; /* led index */
621 uint32 behavior; 621 u32 behavior;
622 u8 activehi; 622 u8 activehi;
623} wl_led_info_t; 623} wl_led_info_t;
624 624
@@ -634,9 +634,9 @@ typedef struct {
634 634
635/* similar cis (srom or otp) struct [iovar: may not be aligned] */ 635/* similar cis (srom or otp) struct [iovar: may not be aligned] */
636typedef struct { 636typedef struct {
637 uint32 source; /* cis source */ 637 u32 source; /* cis source */
638 uint32 byteoff; /* byte offset */ 638 u32 byteoff; /* byte offset */
639 uint32 nbytes; /* number of bytes */ 639 u32 nbytes; /* number of bytes */
640 /* data follows here */ 640 /* data follows here */
641} cis_rw_t; 641} cis_rw_t;
642 642
@@ -646,9 +646,9 @@ typedef struct {
646 646
647/* R_REG and W_REG struct passed through ioctl */ 647/* R_REG and W_REG struct passed through ioctl */
648typedef struct { 648typedef struct {
649 uint32 byteoff; /* byte offset of the field in d11regs_t */ 649 u32 byteoff; /* byte offset of the field in d11regs_t */
650 uint32 val; /* read/write value of the field */ 650 u32 val; /* read/write value of the field */
651 uint32 size; /* sizeof the field */ 651 u32 size; /* sizeof the field */
652 uint band; /* band (optional) */ 652 uint band; /* band (optional) */
653} rw_reg_t; 653} rw_reg_t;
654 654
@@ -704,20 +704,20 @@ typedef struct {
704 u16 ver; /* version of this struct */ 704 u16 ver; /* version of this struct */
705 u16 len; /* length in bytes of this structure */ 705 u16 len; /* length in bytes of this structure */
706 u16 cap; /* sta's advertised capabilities */ 706 u16 cap; /* sta's advertised capabilities */
707 uint32 flags; /* flags defined below */ 707 u32 flags; /* flags defined below */
708 uint32 idle; /* time since data pkt rx'd from sta */ 708 u32 idle; /* time since data pkt rx'd from sta */
709 struct ether_addr ea; /* Station address */ 709 struct ether_addr ea; /* Station address */
710 wl_rateset_t rateset; /* rateset in use */ 710 wl_rateset_t rateset; /* rateset in use */
711 uint32 in; /* seconds elapsed since associated */ 711 u32 in; /* seconds elapsed since associated */
712 uint32 listen_interval_inms; /* Min Listen interval in ms for this STA */ 712 u32 listen_interval_inms; /* Min Listen interval in ms for this STA */
713 uint32 tx_pkts; /* # of packets transmitted */ 713 u32 tx_pkts; /* # of packets transmitted */
714 uint32 tx_failures; /* # of packets failed */ 714 u32 tx_failures; /* # of packets failed */
715 uint32 rx_ucast_pkts; /* # of unicast packets received */ 715 u32 rx_ucast_pkts; /* # of unicast packets received */
716 uint32 rx_mcast_pkts; /* # of multicast packets received */ 716 u32 rx_mcast_pkts; /* # of multicast packets received */
717 uint32 tx_rate; /* Rate of last successful tx frame */ 717 u32 tx_rate; /* Rate of last successful tx frame */
718 uint32 rx_rate; /* Rate of last successful rx frame */ 718 u32 rx_rate; /* Rate of last successful rx frame */
719 uint32 rx_decrypt_succeeds; /* # of packet decrypted successfully */ 719 u32 rx_decrypt_succeeds; /* # of packet decrypted successfully */
720 uint32 rx_decrypt_failures; /* # of packet decrypted unsuccessfully */ 720 u32 rx_decrypt_failures; /* # of packet decrypted unsuccessfully */
721} sta_info_t; 721} sta_info_t;
722 722
723#define WL_OLD_STAINFO_SIZE OFFSETOF(sta_info_t, tx_pkts) 723#define WL_OLD_STAINFO_SIZE OFFSETOF(sta_info_t, tx_pkts)
@@ -745,7 +745,7 @@ typedef struct {
745 745
746/* Used to get specific STA parameters */ 746/* Used to get specific STA parameters */
747typedef struct { 747typedef struct {
748 uint32 val; 748 u32 val;
749 struct ether_addr ea; 749 struct ether_addr ea;
750} scb_val_t; 750} scb_val_t;
751 751
@@ -1208,7 +1208,7 @@ typedef struct wl_po {
1208 u16 phy_type; /* Phy type */ 1208 u16 phy_type; /* Phy type */
1209 u16 band; 1209 u16 band;
1210 u16 cckpo; 1210 u16 cckpo;
1211 uint32 ofdmpo; 1211 u32 ofdmpo;
1212 u16 mcspo[8]; 1212 u16 mcspo[8];
1213} wl_po_t; 1213} wl_po_t;
1214 1214
@@ -1371,8 +1371,8 @@ typedef struct wl_po {
1371 1371
1372/* RSSI per antenna */ 1372/* RSSI per antenna */
1373typedef struct { 1373typedef struct {
1374 uint32 version; /* version field */ 1374 u32 version; /* version field */
1375 uint32 count; /* number of valid antenna rssi */ 1375 u32 count; /* number of valid antenna rssi */
1376 s8 rssi_ant[WL_RSSI_ANT_MAX]; /* rssi per antenna */ 1376 s8 rssi_ant[WL_RSSI_ANT_MAX]; /* rssi per antenna */
1377} wl_rssi_ant_t; 1377} wl_rssi_ant_t;
1378 1378
@@ -1401,7 +1401,7 @@ typedef struct {
1401#define WL_TX_POWER_MCS40_NUM 17 1401#define WL_TX_POWER_MCS40_NUM 17
1402 1402
1403typedef struct { 1403typedef struct {
1404 uint32 flags; 1404 u32 flags;
1405 chanspec_t chanspec; /* txpwr report for this channel */ 1405 chanspec_t chanspec; /* txpwr report for this channel */
1406 chanspec_t local_chanspec; /* channel on which we are associated */ 1406 chanspec_t local_chanspec; /* channel on which we are associated */
1407 u8 local_max; /* local max according to the AP */ 1407 u8 local_max; /* local max according to the AP */
@@ -1449,7 +1449,7 @@ typedef struct {
1449#define WL_TX_POWER_F_SISO 8 1449#define WL_TX_POWER_F_SISO 8
1450 1450
1451typedef struct { 1451typedef struct {
1452 uint32 flags; 1452 u32 flags;
1453 chanspec_t chanspec; /* txpwr report for this channel */ 1453 chanspec_t chanspec; /* txpwr report for this channel */
1454 chanspec_t local_chanspec; /* channel on which we are associated */ 1454 chanspec_t local_chanspec; /* channel on which we are associated */
1455 u8 local_max; /* local max according to the AP */ 1455 u8 local_max; /* local max according to the AP */
@@ -1497,231 +1497,231 @@ typedef struct {
1497 u16 length; /* length of entire structure */ 1497 u16 length; /* length of entire structure */
1498 1498
1499 /* transmit stat counters */ 1499 /* transmit stat counters */
1500 uint32 txframe; /* tx data frames */ 1500 u32 txframe; /* tx data frames */
1501 uint32 txbyte; /* tx data bytes */ 1501 u32 txbyte; /* tx data bytes */
1502 uint32 txretrans; /* tx mac retransmits */ 1502 u32 txretrans; /* tx mac retransmits */
1503 uint32 txerror; /* tx data errors (derived: sum of others) */ 1503 u32 txerror; /* tx data errors (derived: sum of others) */
1504 uint32 txctl; /* tx management frames */ 1504 u32 txctl; /* tx management frames */
1505 uint32 txprshort; /* tx short preamble frames */ 1505 u32 txprshort; /* tx short preamble frames */
1506 uint32 txserr; /* tx status errors */ 1506 u32 txserr; /* tx status errors */
1507 uint32 txnobuf; /* tx out of buffers errors */ 1507 u32 txnobuf; /* tx out of buffers errors */
1508 uint32 txnoassoc; /* tx discard because we're not associated */ 1508 u32 txnoassoc; /* tx discard because we're not associated */
1509 uint32 txrunt; /* tx runt frames */ 1509 u32 txrunt; /* tx runt frames */
1510 uint32 txchit; /* tx header cache hit (fastpath) */ 1510 u32 txchit; /* tx header cache hit (fastpath) */
1511 uint32 txcmiss; /* tx header cache miss (slowpath) */ 1511 u32 txcmiss; /* tx header cache miss (slowpath) */
1512 uint32 ieee_tx_status; /* calls to ieee80211_tx_status */ 1512 u32 ieee_tx_status; /* calls to ieee80211_tx_status */
1513 uint32 ieee_tx; /* tx calls frm mac0211 */ 1513 u32 ieee_tx; /* tx calls frm mac0211 */
1514 uint32 ieee_rx; /* calls to ieee_rx */ 1514 u32 ieee_rx; /* calls to ieee_rx */
1515 1515
1516 /* transmit chip error counters */ 1516 /* transmit chip error counters */
1517 uint32 txuflo; /* tx fifo underflows */ 1517 u32 txuflo; /* tx fifo underflows */
1518 uint32 txphyerr; /* tx phy errors (indicated in tx status) */ 1518 u32 txphyerr; /* tx phy errors (indicated in tx status) */
1519 uint32 txphycrs; 1519 u32 txphycrs;
1520 1520
1521 /* receive stat counters */ 1521 /* receive stat counters */
1522 uint32 rxframe; /* rx data frames */ 1522 u32 rxframe; /* rx data frames */
1523 uint32 rxbyte; /* rx data bytes */ 1523 u32 rxbyte; /* rx data bytes */
1524 uint32 rxerror; /* rx data errors (derived: sum of others) */ 1524 u32 rxerror; /* rx data errors (derived: sum of others) */
1525 uint32 rxctl; /* rx management frames */ 1525 u32 rxctl; /* rx management frames */
1526 uint32 rxnobuf; /* rx out of buffers errors */ 1526 u32 rxnobuf; /* rx out of buffers errors */
1527 uint32 rxnondata; /* rx non data frames in the data channel errors */ 1527 u32 rxnondata; /* rx non data frames in the data channel errors */
1528 uint32 rxbadds; /* rx bad DS errors */ 1528 u32 rxbadds; /* rx bad DS errors */
1529 uint32 rxbadcm; /* rx bad control or management frames */ 1529 u32 rxbadcm; /* rx bad control or management frames */
1530 uint32 rxfragerr; /* rx fragmentation errors */ 1530 u32 rxfragerr; /* rx fragmentation errors */
1531 uint32 rxrunt; /* rx runt frames */ 1531 u32 rxrunt; /* rx runt frames */
1532 uint32 rxgiant; /* rx giant frames */ 1532 u32 rxgiant; /* rx giant frames */
1533 uint32 rxnoscb; /* rx no scb error */ 1533 u32 rxnoscb; /* rx no scb error */
1534 uint32 rxbadproto; /* rx invalid frames */ 1534 u32 rxbadproto; /* rx invalid frames */
1535 uint32 rxbadsrcmac; /* rx frames with Invalid Src Mac */ 1535 u32 rxbadsrcmac; /* rx frames with Invalid Src Mac */
1536 uint32 rxbadda; /* rx frames tossed for invalid da */ 1536 u32 rxbadda; /* rx frames tossed for invalid da */
1537 uint32 rxfilter; /* rx frames filtered out */ 1537 u32 rxfilter; /* rx frames filtered out */
1538 1538
1539 /* receive chip error counters */ 1539 /* receive chip error counters */
1540 uint32 rxoflo; /* rx fifo overflow errors */ 1540 u32 rxoflo; /* rx fifo overflow errors */
1541 uint32 rxuflo[NFIFO]; /* rx dma descriptor underflow errors */ 1541 u32 rxuflo[NFIFO]; /* rx dma descriptor underflow errors */
1542 1542
1543 uint32 d11cnt_txrts_off; /* d11cnt txrts value when reset d11cnt */ 1543 u32 d11cnt_txrts_off; /* d11cnt txrts value when reset d11cnt */
1544 uint32 d11cnt_rxcrc_off; /* d11cnt rxcrc value when reset d11cnt */ 1544 u32 d11cnt_rxcrc_off; /* d11cnt rxcrc value when reset d11cnt */
1545 uint32 d11cnt_txnocts_off; /* d11cnt txnocts value when reset d11cnt */ 1545 u32 d11cnt_txnocts_off; /* d11cnt txnocts value when reset d11cnt */
1546 1546
1547 /* misc counters */ 1547 /* misc counters */
1548 uint32 dmade; /* tx/rx dma descriptor errors */ 1548 u32 dmade; /* tx/rx dma descriptor errors */
1549 uint32 dmada; /* tx/rx dma data errors */ 1549 u32 dmada; /* tx/rx dma data errors */
1550 uint32 dmape; /* tx/rx dma descriptor protocol errors */ 1550 u32 dmape; /* tx/rx dma descriptor protocol errors */
1551 uint32 reset; /* reset count */ 1551 u32 reset; /* reset count */
1552 uint32 tbtt; /* cnts the TBTT int's */ 1552 u32 tbtt; /* cnts the TBTT int's */
1553 uint32 txdmawar; 1553 u32 txdmawar;
1554 uint32 pkt_callback_reg_fail; /* callbacks register failure */ 1554 u32 pkt_callback_reg_fail; /* callbacks register failure */
1555 1555
1556 /* MAC counters: 32-bit version of d11.h's macstat_t */ 1556 /* MAC counters: 32-bit version of d11.h's macstat_t */
1557 uint32 txallfrm; /* total number of frames sent, incl. Data, ACK, RTS, CTS, 1557 u32 txallfrm; /* total number of frames sent, incl. Data, ACK, RTS, CTS,
1558 * Control Management (includes retransmissions) 1558 * Control Management (includes retransmissions)
1559 */ 1559 */
1560 uint32 txrtsfrm; /* number of RTS sent out by the MAC */ 1560 u32 txrtsfrm; /* number of RTS sent out by the MAC */
1561 uint32 txctsfrm; /* number of CTS sent out by the MAC */ 1561 u32 txctsfrm; /* number of CTS sent out by the MAC */
1562 uint32 txackfrm; /* number of ACK frames sent out */ 1562 u32 txackfrm; /* number of ACK frames sent out */
1563 uint32 txdnlfrm; /* Not used */ 1563 u32 txdnlfrm; /* Not used */
1564 uint32 txbcnfrm; /* beacons transmitted */ 1564 u32 txbcnfrm; /* beacons transmitted */
1565 uint32 txfunfl[8]; /* per-fifo tx underflows */ 1565 u32 txfunfl[8]; /* per-fifo tx underflows */
1566 uint32 txtplunfl; /* Template underflows (mac was too slow to transmit ACK/CTS 1566 u32 txtplunfl; /* Template underflows (mac was too slow to transmit ACK/CTS
1567 * or BCN) 1567 * or BCN)
1568 */ 1568 */
1569 uint32 txphyerror; /* Transmit phy error, type of error is reported in tx-status for 1569 u32 txphyerror; /* Transmit phy error, type of error is reported in tx-status for
1570 * driver enqueued frames 1570 * driver enqueued frames
1571 */ 1571 */
1572 uint32 rxfrmtoolong; /* Received frame longer than legal limit (2346 bytes) */ 1572 u32 rxfrmtoolong; /* Received frame longer than legal limit (2346 bytes) */
1573 uint32 rxfrmtooshrt; /* Received frame did not contain enough bytes for its frame type */ 1573 u32 rxfrmtooshrt; /* Received frame did not contain enough bytes for its frame type */
1574 uint32 rxinvmachdr; /* Either the protocol version != 0 or frame type not 1574 u32 rxinvmachdr; /* Either the protocol version != 0 or frame type not
1575 * data/control/management 1575 * data/control/management
1576 */ 1576 */
1577 uint32 rxbadfcs; /* number of frames for which the CRC check failed in the MAC */ 1577 u32 rxbadfcs; /* number of frames for which the CRC check failed in the MAC */
1578 uint32 rxbadplcp; /* parity check of the PLCP header failed */ 1578 u32 rxbadplcp; /* parity check of the PLCP header failed */
1579 uint32 rxcrsglitch; /* PHY was able to correlate the preamble but not the header */ 1579 u32 rxcrsglitch; /* PHY was able to correlate the preamble but not the header */
1580 uint32 rxstrt; /* Number of received frames with a good PLCP 1580 u32 rxstrt; /* Number of received frames with a good PLCP
1581 * (i.e. passing parity check) 1581 * (i.e. passing parity check)
1582 */ 1582 */
1583 uint32 rxdfrmucastmbss; /* Number of received DATA frames with good FCS and matching RA */ 1583 u32 rxdfrmucastmbss; /* Number of received DATA frames with good FCS and matching RA */
1584 uint32 rxmfrmucastmbss; /* number of received mgmt frames with good FCS and matching RA */ 1584 u32 rxmfrmucastmbss; /* number of received mgmt frames with good FCS and matching RA */
1585 uint32 rxcfrmucast; /* number of received CNTRL frames with good FCS and matching RA */ 1585 u32 rxcfrmucast; /* number of received CNTRL frames with good FCS and matching RA */
1586 uint32 rxrtsucast; /* number of unicast RTS addressed to the MAC (good FCS) */ 1586 u32 rxrtsucast; /* number of unicast RTS addressed to the MAC (good FCS) */
1587 uint32 rxctsucast; /* number of unicast CTS addressed to the MAC (good FCS) */ 1587 u32 rxctsucast; /* number of unicast CTS addressed to the MAC (good FCS) */
1588 uint32 rxackucast; /* number of ucast ACKS received (good FCS) */ 1588 u32 rxackucast; /* number of ucast ACKS received (good FCS) */
1589 uint32 rxdfrmocast; /* number of received DATA frames (good FCS and not matching RA) */ 1589 u32 rxdfrmocast; /* number of received DATA frames (good FCS and not matching RA) */
1590 uint32 rxmfrmocast; /* number of received MGMT frames (good FCS and not matching RA) */ 1590 u32 rxmfrmocast; /* number of received MGMT frames (good FCS and not matching RA) */
1591 uint32 rxcfrmocast; /* number of received CNTRL frame (good FCS and not matching RA) */ 1591 u32 rxcfrmocast; /* number of received CNTRL frame (good FCS and not matching RA) */
1592 uint32 rxrtsocast; /* number of received RTS not addressed to the MAC */ 1592 u32 rxrtsocast; /* number of received RTS not addressed to the MAC */
1593 uint32 rxctsocast; /* number of received CTS not addressed to the MAC */ 1593 u32 rxctsocast; /* number of received CTS not addressed to the MAC */
1594 uint32 rxdfrmmcast; /* number of RX Data multicast frames received by the MAC */ 1594 u32 rxdfrmmcast; /* number of RX Data multicast frames received by the MAC */
1595 uint32 rxmfrmmcast; /* number of RX Management multicast frames received by the MAC */ 1595 u32 rxmfrmmcast; /* number of RX Management multicast frames received by the MAC */
1596 uint32 rxcfrmmcast; /* number of RX Control multicast frames received by the MAC 1596 u32 rxcfrmmcast; /* number of RX Control multicast frames received by the MAC
1597 * (unlikely to see these) 1597 * (unlikely to see these)
1598 */ 1598 */
1599 uint32 rxbeaconmbss; /* beacons received from member of BSS */ 1599 u32 rxbeaconmbss; /* beacons received from member of BSS */
1600 uint32 rxdfrmucastobss; /* number of unicast frames addressed to the MAC from 1600 u32 rxdfrmucastobss; /* number of unicast frames addressed to the MAC from
1601 * other BSS (WDS FRAME) 1601 * other BSS (WDS FRAME)
1602 */ 1602 */
1603 uint32 rxbeaconobss; /* beacons received from other BSS */ 1603 u32 rxbeaconobss; /* beacons received from other BSS */
1604 uint32 rxrsptmout; /* Number of response timeouts for transmitted frames 1604 u32 rxrsptmout; /* Number of response timeouts for transmitted frames
1605 * expecting a response 1605 * expecting a response
1606 */ 1606 */
1607 uint32 bcntxcancl; /* transmit beacons canceled due to receipt of beacon (IBSS) */ 1607 u32 bcntxcancl; /* transmit beacons canceled due to receipt of beacon (IBSS) */
1608 uint32 rxf0ovfl; /* Number of receive fifo 0 overflows */ 1608 u32 rxf0ovfl; /* Number of receive fifo 0 overflows */
1609 uint32 rxf1ovfl; /* Number of receive fifo 1 overflows (obsolete) */ 1609 u32 rxf1ovfl; /* Number of receive fifo 1 overflows (obsolete) */
1610 uint32 rxf2ovfl; /* Number of receive fifo 2 overflows (obsolete) */ 1610 u32 rxf2ovfl; /* Number of receive fifo 2 overflows (obsolete) */
1611 uint32 txsfovfl; /* Number of transmit status fifo overflows (obsolete) */ 1611 u32 txsfovfl; /* Number of transmit status fifo overflows (obsolete) */
1612 uint32 pmqovfl; /* Number of PMQ overflows */ 1612 u32 pmqovfl; /* Number of PMQ overflows */
1613 uint32 rxcgprqfrm; /* Number of received Probe requests that made it into 1613 u32 rxcgprqfrm; /* Number of received Probe requests that made it into
1614 * the PRQ fifo 1614 * the PRQ fifo
1615 */ 1615 */
1616 uint32 rxcgprsqovfl; /* Rx Probe Request Que overflow in the AP */ 1616 u32 rxcgprsqovfl; /* Rx Probe Request Que overflow in the AP */
1617 uint32 txcgprsfail; /* Tx Probe Response Fail. AP sent probe response but did 1617 u32 txcgprsfail; /* Tx Probe Response Fail. AP sent probe response but did
1618 * not get ACK 1618 * not get ACK
1619 */ 1619 */
1620 uint32 txcgprssuc; /* Tx Probe Response Success (ACK was received) */ 1620 u32 txcgprssuc; /* Tx Probe Response Success (ACK was received) */
1621 uint32 prs_timeout; /* Number of probe requests that were dropped from the PRQ 1621 u32 prs_timeout; /* Number of probe requests that were dropped from the PRQ
1622 * fifo because a probe response could not be sent out within 1622 * fifo because a probe response could not be sent out within
1623 * the time limit defined in M_PRS_MAXTIME 1623 * the time limit defined in M_PRS_MAXTIME
1624 */ 1624 */
1625 uint32 rxnack; 1625 u32 rxnack;
1626 uint32 frmscons; 1626 u32 frmscons;
1627 uint32 txnack; 1627 u32 txnack;
1628 uint32 txglitch_nack; /* obsolete */ 1628 u32 txglitch_nack; /* obsolete */
1629 uint32 txburst; /* obsolete */ 1629 u32 txburst; /* obsolete */
1630 1630
1631 /* 802.11 MIB counters, pp. 614 of 802.11 reaff doc. */ 1631 /* 802.11 MIB counters, pp. 614 of 802.11 reaff doc. */
1632 uint32 txfrag; /* dot11TransmittedFragmentCount */ 1632 u32 txfrag; /* dot11TransmittedFragmentCount */
1633 uint32 txmulti; /* dot11MulticastTransmittedFrameCount */ 1633 u32 txmulti; /* dot11MulticastTransmittedFrameCount */
1634 uint32 txfail; /* dot11FailedCount */ 1634 u32 txfail; /* dot11FailedCount */
1635 uint32 txretry; /* dot11RetryCount */ 1635 u32 txretry; /* dot11RetryCount */
1636 uint32 txretrie; /* dot11MultipleRetryCount */ 1636 u32 txretrie; /* dot11MultipleRetryCount */
1637 uint32 rxdup; /* dot11FrameduplicateCount */ 1637 u32 rxdup; /* dot11FrameduplicateCount */
1638 uint32 txrts; /* dot11RTSSuccessCount */ 1638 u32 txrts; /* dot11RTSSuccessCount */
1639 uint32 txnocts; /* dot11RTSFailureCount */ 1639 u32 txnocts; /* dot11RTSFailureCount */
1640 uint32 txnoack; /* dot11ACKFailureCount */ 1640 u32 txnoack; /* dot11ACKFailureCount */
1641 uint32 rxfrag; /* dot11ReceivedFragmentCount */ 1641 u32 rxfrag; /* dot11ReceivedFragmentCount */
1642 uint32 rxmulti; /* dot11MulticastReceivedFrameCount */ 1642 u32 rxmulti; /* dot11MulticastReceivedFrameCount */
1643 uint32 rxcrc; /* dot11FCSErrorCount */ 1643 u32 rxcrc; /* dot11FCSErrorCount */
1644 uint32 txfrmsnt; /* dot11TransmittedFrameCount (bogus MIB?) */ 1644 u32 txfrmsnt; /* dot11TransmittedFrameCount (bogus MIB?) */
1645 uint32 rxundec; /* dot11WEPUndecryptableCount */ 1645 u32 rxundec; /* dot11WEPUndecryptableCount */
1646 1646
1647 /* WPA2 counters (see rxundec for DecryptFailureCount) */ 1647 /* WPA2 counters (see rxundec for DecryptFailureCount) */
1648 uint32 tkipmicfaill; /* TKIPLocalMICFailures */ 1648 u32 tkipmicfaill; /* TKIPLocalMICFailures */
1649 uint32 tkipcntrmsr; /* TKIPCounterMeasuresInvoked */ 1649 u32 tkipcntrmsr; /* TKIPCounterMeasuresInvoked */
1650 uint32 tkipreplay; /* TKIPReplays */ 1650 u32 tkipreplay; /* TKIPReplays */
1651 uint32 ccmpfmterr; /* CCMPFormatErrors */ 1651 u32 ccmpfmterr; /* CCMPFormatErrors */
1652 uint32 ccmpreplay; /* CCMPReplays */ 1652 u32 ccmpreplay; /* CCMPReplays */
1653 uint32 ccmpundec; /* CCMPDecryptErrors */ 1653 u32 ccmpundec; /* CCMPDecryptErrors */
1654 uint32 fourwayfail; /* FourWayHandshakeFailures */ 1654 u32 fourwayfail; /* FourWayHandshakeFailures */
1655 uint32 wepundec; /* dot11WEPUndecryptableCount */ 1655 u32 wepundec; /* dot11WEPUndecryptableCount */
1656 uint32 wepicverr; /* dot11WEPICVErrorCount */ 1656 u32 wepicverr; /* dot11WEPICVErrorCount */
1657 uint32 decsuccess; /* DecryptSuccessCount */ 1657 u32 decsuccess; /* DecryptSuccessCount */
1658 uint32 tkipicverr; /* TKIPICVErrorCount */ 1658 u32 tkipicverr; /* TKIPICVErrorCount */
1659 uint32 wepexcluded; /* dot11WEPExcludedCount */ 1659 u32 wepexcluded; /* dot11WEPExcludedCount */
1660 1660
1661 uint32 rxundec_mcst; /* dot11WEPUndecryptableCount */ 1661 u32 rxundec_mcst; /* dot11WEPUndecryptableCount */
1662 1662
1663 /* WPA2 counters (see rxundec for DecryptFailureCount) */ 1663 /* WPA2 counters (see rxundec for DecryptFailureCount) */
1664 uint32 tkipmicfaill_mcst; /* TKIPLocalMICFailures */ 1664 u32 tkipmicfaill_mcst; /* TKIPLocalMICFailures */
1665 uint32 tkipcntrmsr_mcst; /* TKIPCounterMeasuresInvoked */ 1665 u32 tkipcntrmsr_mcst; /* TKIPCounterMeasuresInvoked */
1666 uint32 tkipreplay_mcst; /* TKIPReplays */ 1666 u32 tkipreplay_mcst; /* TKIPReplays */
1667 uint32 ccmpfmterr_mcst; /* CCMPFormatErrors */ 1667 u32 ccmpfmterr_mcst; /* CCMPFormatErrors */
1668 uint32 ccmpreplay_mcst; /* CCMPReplays */ 1668 u32 ccmpreplay_mcst; /* CCMPReplays */
1669 uint32 ccmpundec_mcst; /* CCMPDecryptErrors */ 1669 u32 ccmpundec_mcst; /* CCMPDecryptErrors */
1670 uint32 fourwayfail_mcst; /* FourWayHandshakeFailures */ 1670 u32 fourwayfail_mcst; /* FourWayHandshakeFailures */
1671 uint32 wepundec_mcst; /* dot11WEPUndecryptableCount */ 1671 u32 wepundec_mcst; /* dot11WEPUndecryptableCount */
1672 uint32 wepicverr_mcst; /* dot11WEPICVErrorCount */ 1672 u32 wepicverr_mcst; /* dot11WEPICVErrorCount */
1673 uint32 decsuccess_mcst; /* DecryptSuccessCount */ 1673 u32 decsuccess_mcst; /* DecryptSuccessCount */
1674 uint32 tkipicverr_mcst; /* TKIPICVErrorCount */ 1674 u32 tkipicverr_mcst; /* TKIPICVErrorCount */
1675 uint32 wepexcluded_mcst; /* dot11WEPExcludedCount */ 1675 u32 wepexcluded_mcst; /* dot11WEPExcludedCount */
1676 1676
1677 uint32 txchanrej; /* Tx frames suppressed due to channel rejection */ 1677 u32 txchanrej; /* Tx frames suppressed due to channel rejection */
1678 uint32 txexptime; /* Tx frames suppressed due to timer expiration */ 1678 u32 txexptime; /* Tx frames suppressed due to timer expiration */
1679 uint32 psmwds; /* Count PSM watchdogs */ 1679 u32 psmwds; /* Count PSM watchdogs */
1680 uint32 phywatchdog; /* Count Phy watchdogs (triggered by ucode) */ 1680 u32 phywatchdog; /* Count Phy watchdogs (triggered by ucode) */
1681 1681
1682 /* MBSS counters, AP only */ 1682 /* MBSS counters, AP only */
1683 uint32 prq_entries_handled; /* PRQ entries read in */ 1683 u32 prq_entries_handled; /* PRQ entries read in */
1684 uint32 prq_undirected_entries; /* which were bcast bss & ssid */ 1684 u32 prq_undirected_entries; /* which were bcast bss & ssid */
1685 uint32 prq_bad_entries; /* which could not be translated to info */ 1685 u32 prq_bad_entries; /* which could not be translated to info */
1686 uint32 atim_suppress_count; /* TX suppressions on ATIM fifo */ 1686 u32 atim_suppress_count; /* TX suppressions on ATIM fifo */
1687 uint32 bcn_template_not_ready; /* Template marked in use on send bcn ... */ 1687 u32 bcn_template_not_ready; /* Template marked in use on send bcn ... */
1688 uint32 bcn_template_not_ready_done; /* ...but "DMA done" interrupt rcvd */ 1688 u32 bcn_template_not_ready_done; /* ...but "DMA done" interrupt rcvd */
1689 uint32 late_tbtt_dpc; /* TBTT DPC did not happen in time */ 1689 u32 late_tbtt_dpc; /* TBTT DPC did not happen in time */
1690 1690
1691 /* per-rate receive stat counters */ 1691 /* per-rate receive stat counters */
1692 uint32 rx1mbps; /* packets rx at 1Mbps */ 1692 u32 rx1mbps; /* packets rx at 1Mbps */
1693 uint32 rx2mbps; /* packets rx at 2Mbps */ 1693 u32 rx2mbps; /* packets rx at 2Mbps */
1694 uint32 rx5mbps5; /* packets rx at 5.5Mbps */ 1694 u32 rx5mbps5; /* packets rx at 5.5Mbps */
1695 uint32 rx6mbps; /* packets rx at 6Mbps */ 1695 u32 rx6mbps; /* packets rx at 6Mbps */
1696 uint32 rx9mbps; /* packets rx at 9Mbps */ 1696 u32 rx9mbps; /* packets rx at 9Mbps */
1697 uint32 rx11mbps; /* packets rx at 11Mbps */ 1697 u32 rx11mbps; /* packets rx at 11Mbps */
1698 uint32 rx12mbps; /* packets rx at 12Mbps */ 1698 u32 rx12mbps; /* packets rx at 12Mbps */
1699 uint32 rx18mbps; /* packets rx at 18Mbps */ 1699 u32 rx18mbps; /* packets rx at 18Mbps */
1700 uint32 rx24mbps; /* packets rx at 24Mbps */ 1700 u32 rx24mbps; /* packets rx at 24Mbps */
1701 uint32 rx36mbps; /* packets rx at 36Mbps */ 1701 u32 rx36mbps; /* packets rx at 36Mbps */
1702 uint32 rx48mbps; /* packets rx at 48Mbps */ 1702 u32 rx48mbps; /* packets rx at 48Mbps */
1703 uint32 rx54mbps; /* packets rx at 54Mbps */ 1703 u32 rx54mbps; /* packets rx at 54Mbps */
1704 uint32 rx108mbps; /* packets rx at 108mbps */ 1704 u32 rx108mbps; /* packets rx at 108mbps */
1705 uint32 rx162mbps; /* packets rx at 162mbps */ 1705 u32 rx162mbps; /* packets rx at 162mbps */
1706 uint32 rx216mbps; /* packets rx at 216 mbps */ 1706 u32 rx216mbps; /* packets rx at 216 mbps */
1707 uint32 rx270mbps; /* packets rx at 270 mbps */ 1707 u32 rx270mbps; /* packets rx at 270 mbps */
1708 uint32 rx324mbps; /* packets rx at 324 mbps */ 1708 u32 rx324mbps; /* packets rx at 324 mbps */
1709 uint32 rx378mbps; /* packets rx at 378 mbps */ 1709 u32 rx378mbps; /* packets rx at 378 mbps */
1710 uint32 rx432mbps; /* packets rx at 432 mbps */ 1710 u32 rx432mbps; /* packets rx at 432 mbps */
1711 uint32 rx486mbps; /* packets rx at 486 mbps */ 1711 u32 rx486mbps; /* packets rx at 486 mbps */
1712 uint32 rx540mbps; /* packets rx at 540 mbps */ 1712 u32 rx540mbps; /* packets rx at 540 mbps */
1713 1713
1714 /* pkteng rx frame stats */ 1714 /* pkteng rx frame stats */
1715 uint32 pktengrxducast; /* unicast frames rxed by the pkteng code */ 1715 u32 pktengrxducast; /* unicast frames rxed by the pkteng code */
1716 uint32 pktengrxdmcast; /* multicast frames rxed by the pkteng code */ 1716 u32 pktengrxdmcast; /* multicast frames rxed by the pkteng code */
1717 1717
1718 uint32 rfdisable; /* count of radio disables */ 1718 u32 rfdisable; /* count of radio disables */
1719 uint32 bphy_rxcrsglitch; /* PHY count of bphy glitches */ 1719 u32 bphy_rxcrsglitch; /* PHY count of bphy glitches */
1720 1720
1721 uint32 txmpdu_sgi; /* count for sgi transmit */ 1721 u32 txmpdu_sgi; /* count for sgi transmit */
1722 uint32 rxmpdu_sgi; /* count for sgi received */ 1722 u32 rxmpdu_sgi; /* count for sgi received */
1723 uint32 txmpdu_stbc; /* count for stbc transmit */ 1723 u32 txmpdu_stbc; /* count for stbc transmit */
1724 uint32 rxmpdu_stbc; /* count for stbc received */ 1724 u32 rxmpdu_stbc; /* count for stbc received */
1725} wl_cnt_t; 1725} wl_cnt_t;
1726 1726
1727#define WL_DELTA_STATS_T_VERSION 1 /* current version of wl_delta_stats_t struct */ 1727#define WL_DELTA_STATS_T_VERSION 1 /* current version of wl_delta_stats_t struct */
@@ -1731,44 +1731,44 @@ typedef struct {
1731 u16 length; /* length of entire structure */ 1731 u16 length; /* length of entire structure */
1732 1732
1733 /* transmit stat counters */ 1733 /* transmit stat counters */
1734 uint32 txframe; /* tx data frames */ 1734 u32 txframe; /* tx data frames */
1735 uint32 txbyte; /* tx data bytes */ 1735 u32 txbyte; /* tx data bytes */
1736 uint32 txretrans; /* tx mac retransmits */ 1736 u32 txretrans; /* tx mac retransmits */
1737 uint32 txfail; /* tx failures */ 1737 u32 txfail; /* tx failures */
1738 1738
1739 /* receive stat counters */ 1739 /* receive stat counters */
1740 uint32 rxframe; /* rx data frames */ 1740 u32 rxframe; /* rx data frames */
1741 uint32 rxbyte; /* rx data bytes */ 1741 u32 rxbyte; /* rx data bytes */
1742 1742
1743 /* per-rate receive stat counters */ 1743 /* per-rate receive stat counters */
1744 uint32 rx1mbps; /* packets rx at 1Mbps */ 1744 u32 rx1mbps; /* packets rx at 1Mbps */
1745 uint32 rx2mbps; /* packets rx at 2Mbps */ 1745 u32 rx2mbps; /* packets rx at 2Mbps */
1746 uint32 rx5mbps5; /* packets rx at 5.5Mbps */ 1746 u32 rx5mbps5; /* packets rx at 5.5Mbps */
1747 uint32 rx6mbps; /* packets rx at 6Mbps */ 1747 u32 rx6mbps; /* packets rx at 6Mbps */
1748 uint32 rx9mbps; /* packets rx at 9Mbps */ 1748 u32 rx9mbps; /* packets rx at 9Mbps */
1749 uint32 rx11mbps; /* packets rx at 11Mbps */ 1749 u32 rx11mbps; /* packets rx at 11Mbps */
1750 uint32 rx12mbps; /* packets rx at 12Mbps */ 1750 u32 rx12mbps; /* packets rx at 12Mbps */
1751 uint32 rx18mbps; /* packets rx at 18Mbps */ 1751 u32 rx18mbps; /* packets rx at 18Mbps */
1752 uint32 rx24mbps; /* packets rx at 24Mbps */ 1752 u32 rx24mbps; /* packets rx at 24Mbps */
1753 uint32 rx36mbps; /* packets rx at 36Mbps */ 1753 u32 rx36mbps; /* packets rx at 36Mbps */
1754 uint32 rx48mbps; /* packets rx at 48Mbps */ 1754 u32 rx48mbps; /* packets rx at 48Mbps */
1755 uint32 rx54mbps; /* packets rx at 54Mbps */ 1755 u32 rx54mbps; /* packets rx at 54Mbps */
1756 uint32 rx108mbps; /* packets rx at 108mbps */ 1756 u32 rx108mbps; /* packets rx at 108mbps */
1757 uint32 rx162mbps; /* packets rx at 162mbps */ 1757 u32 rx162mbps; /* packets rx at 162mbps */
1758 uint32 rx216mbps; /* packets rx at 216 mbps */ 1758 u32 rx216mbps; /* packets rx at 216 mbps */
1759 uint32 rx270mbps; /* packets rx at 270 mbps */ 1759 u32 rx270mbps; /* packets rx at 270 mbps */
1760 uint32 rx324mbps; /* packets rx at 324 mbps */ 1760 u32 rx324mbps; /* packets rx at 324 mbps */
1761 uint32 rx378mbps; /* packets rx at 378 mbps */ 1761 u32 rx378mbps; /* packets rx at 378 mbps */
1762 uint32 rx432mbps; /* packets rx at 432 mbps */ 1762 u32 rx432mbps; /* packets rx at 432 mbps */
1763 uint32 rx486mbps; /* packets rx at 486 mbps */ 1763 u32 rx486mbps; /* packets rx at 486 mbps */
1764 uint32 rx540mbps; /* packets rx at 540 mbps */ 1764 u32 rx540mbps; /* packets rx at 540 mbps */
1765} wl_delta_stats_t; 1765} wl_delta_stats_t;
1766 1766
1767#define WL_WME_CNT_VERSION 1 /* current version of wl_wme_cnt_t */ 1767#define WL_WME_CNT_VERSION 1 /* current version of wl_wme_cnt_t */
1768 1768
1769typedef struct { 1769typedef struct {
1770 uint32 packets; 1770 u32 packets;
1771 uint32 bytes; 1771 u32 bytes;
1772} wl_traffic_stats_t; 1772} wl_traffic_stats_t;
1773 1773
1774typedef struct { 1774typedef struct {
@@ -1787,8 +1787,8 @@ typedef struct {
1787} wl_wme_cnt_t; 1787} wl_wme_cnt_t;
1788 1788
1789struct wl_msglevel2 { 1789struct wl_msglevel2 {
1790 uint32 low; 1790 u32 low;
1791 uint32 high; 1791 u32 high;
1792}; 1792};
1793 1793
1794#ifdef WLBA 1794#ifdef WLBA
@@ -1801,34 +1801,34 @@ typedef struct wlc_ba_cnt {
1801 u16 length; /* length of entire structure */ 1801 u16 length; /* length of entire structure */
1802 1802
1803 /* transmit stat counters */ 1803 /* transmit stat counters */
1804 uint32 txpdu; /* pdus sent */ 1804 u32 txpdu; /* pdus sent */
1805 uint32 txsdu; /* sdus sent */ 1805 u32 txsdu; /* sdus sent */
1806 uint32 txfc; /* tx side flow controlled packets */ 1806 u32 txfc; /* tx side flow controlled packets */
1807 uint32 txfci; /* tx side flow control initiated */ 1807 u32 txfci; /* tx side flow control initiated */
1808 uint32 txretrans; /* retransmitted pdus */ 1808 u32 txretrans; /* retransmitted pdus */
1809 uint32 txbatimer; /* ba resend due to timer */ 1809 u32 txbatimer; /* ba resend due to timer */
1810 uint32 txdrop; /* dropped packets */ 1810 u32 txdrop; /* dropped packets */
1811 uint32 txaddbareq; /* addba req sent */ 1811 u32 txaddbareq; /* addba req sent */
1812 uint32 txaddbaresp; /* addba resp sent */ 1812 u32 txaddbaresp; /* addba resp sent */
1813 uint32 txdelba; /* delba sent */ 1813 u32 txdelba; /* delba sent */
1814 uint32 txba; /* ba sent */ 1814 u32 txba; /* ba sent */
1815 uint32 txbar; /* bar sent */ 1815 u32 txbar; /* bar sent */
1816 uint32 txpad[4]; /* future */ 1816 u32 txpad[4]; /* future */
1817 1817
1818 /* receive side counters */ 1818 /* receive side counters */
1819 uint32 rxpdu; /* pdus recd */ 1819 u32 rxpdu; /* pdus recd */
1820 uint32 rxqed; /* pdus buffered before sending up */ 1820 u32 rxqed; /* pdus buffered before sending up */
1821 uint32 rxdup; /* duplicate pdus */ 1821 u32 rxdup; /* duplicate pdus */
1822 uint32 rxnobuf; /* pdus discarded due to no buf */ 1822 u32 rxnobuf; /* pdus discarded due to no buf */
1823 uint32 rxaddbareq; /* addba req recd */ 1823 u32 rxaddbareq; /* addba req recd */
1824 uint32 rxaddbaresp; /* addba resp recd */ 1824 u32 rxaddbaresp; /* addba resp recd */
1825 uint32 rxdelba; /* delba recd */ 1825 u32 rxdelba; /* delba recd */
1826 uint32 rxba; /* ba recd */ 1826 u32 rxba; /* ba recd */
1827 uint32 rxbar; /* bar recd */ 1827 u32 rxbar; /* bar recd */
1828 uint32 rxinvba; /* invalid ba recd */ 1828 u32 rxinvba; /* invalid ba recd */
1829 uint32 rxbaholes; /* ba recd with holes */ 1829 u32 rxbaholes; /* ba recd with holes */
1830 uint32 rxunexp; /* unexpected packets */ 1830 u32 rxunexp; /* unexpected packets */
1831 uint32 rxpad[4]; /* future */ 1831 u32 rxpad[4]; /* future */
1832} wlc_ba_cnt_t; 1832} wlc_ba_cnt_t;
1833#endif /* WLBA */ 1833#endif /* WLBA */
1834 1834
@@ -1889,7 +1889,7 @@ typedef struct tspec_per_sta_arg {
1889 1889
1890/* structure for max bandwidth for each access category */ 1890/* structure for max bandwidth for each access category */
1891typedef struct wme_max_bandwidth { 1891typedef struct wme_max_bandwidth {
1892 uint32 ac[AC_COUNT]; /* max bandwidth for each access category */ 1892 u32 ac[AC_COUNT]; /* max bandwidth for each access category */
1893} wme_max_bandwidth_t; 1893} wme_max_bandwidth_t;
1894 1894
1895#define WL_WME_MBW_PARAMS_IO_BYTES (sizeof(wme_max_bandwidth_t)) 1895#define WL_WME_MBW_PARAMS_IO_BYTES (sizeof(wme_max_bandwidth_t))
@@ -1930,10 +1930,10 @@ typedef enum wl_pkt_filter_type {
1930 * that indicates which bits within the pattern should be matched. 1930 * that indicates which bits within the pattern should be matched.
1931 */ 1931 */
1932typedef struct wl_pkt_filter_pattern { 1932typedef struct wl_pkt_filter_pattern {
1933 uint32 offset; /* Offset within received packet to start pattern matching. 1933 u32 offset; /* Offset within received packet to start pattern matching.
1934 * Offset '0' is the first byte of the ethernet header. 1934 * Offset '0' is the first byte of the ethernet header.
1935 */ 1935 */
1936 uint32 size_bytes; /* Size of the pattern. Bitmask must be the same size. */ 1936 u32 size_bytes; /* Size of the pattern. Bitmask must be the same size. */
1937 u8 mask_and_pattern[1]; /* Variable length mask and pattern data. mask starts 1937 u8 mask_and_pattern[1]; /* Variable length mask and pattern data. mask starts
1938 * at offset 0. Pattern immediately follows mask. 1938 * at offset 0. Pattern immediately follows mask.
1939 */ 1939 */
@@ -1941,9 +1941,9 @@ typedef struct wl_pkt_filter_pattern {
1941 1941
1942/* IOVAR "pkt_filter_add" parameter. Used to install packet filters. */ 1942/* IOVAR "pkt_filter_add" parameter. Used to install packet filters. */
1943typedef struct wl_pkt_filter { 1943typedef struct wl_pkt_filter {
1944 uint32 id; /* Unique filter id, specified by app. */ 1944 u32 id; /* Unique filter id, specified by app. */
1945 uint32 type; /* Filter type (WL_PKT_FILTER_TYPE_xxx). */ 1945 u32 type; /* Filter type (WL_PKT_FILTER_TYPE_xxx). */
1946 uint32 negate_match; /* Negate the result of filter matches */ 1946 u32 negate_match; /* Negate the result of filter matches */
1947 union { /* Filter definitions */ 1947 union { /* Filter definitions */
1948 wl_pkt_filter_pattern_t pattern; /* Pattern matching filter */ 1948 wl_pkt_filter_pattern_t pattern; /* Pattern matching filter */
1949 } u; 1949 } u;
@@ -1954,13 +1954,13 @@ typedef struct wl_pkt_filter {
1954 1954
1955/* IOVAR "pkt_filter_enable" parameter. */ 1955/* IOVAR "pkt_filter_enable" parameter. */
1956typedef struct wl_pkt_filter_enable { 1956typedef struct wl_pkt_filter_enable {
1957 uint32 id; /* Unique filter id */ 1957 u32 id; /* Unique filter id */
1958 uint32 enable; /* Enable/disable bool */ 1958 u32 enable; /* Enable/disable bool */
1959} wl_pkt_filter_enable_t; 1959} wl_pkt_filter_enable_t;
1960 1960
1961/* IOVAR "pkt_filter_list" parameter. Used to retrieve a list of installed filters. */ 1961/* IOVAR "pkt_filter_list" parameter. Used to retrieve a list of installed filters. */
1962typedef struct wl_pkt_filter_list { 1962typedef struct wl_pkt_filter_list {
1963 uint32 num; /* Number of installed packet filters */ 1963 u32 num; /* Number of installed packet filters */
1964 wl_pkt_filter_t filter[1]; /* Variable array of packet filters. */ 1964 wl_pkt_filter_t filter[1]; /* Variable array of packet filters. */
1965} wl_pkt_filter_list_t; 1965} wl_pkt_filter_list_t;
1966 1966
@@ -1968,16 +1968,16 @@ typedef struct wl_pkt_filter_list {
1968 1968
1969/* IOVAR "pkt_filter_stats" parameter. Used to retrieve debug statistics. */ 1969/* IOVAR "pkt_filter_stats" parameter. Used to retrieve debug statistics. */
1970typedef struct wl_pkt_filter_stats { 1970typedef struct wl_pkt_filter_stats {
1971 uint32 num_pkts_matched; /* # filter matches for specified filter id */ 1971 u32 num_pkts_matched; /* # filter matches for specified filter id */
1972 uint32 num_pkts_forwarded; /* # packets fwded from dongle to host for all filters */ 1972 u32 num_pkts_forwarded; /* # packets fwded from dongle to host for all filters */
1973 uint32 num_pkts_discarded; /* # packets discarded by dongle for all filters */ 1973 u32 num_pkts_discarded; /* # packets discarded by dongle for all filters */
1974} wl_pkt_filter_stats_t; 1974} wl_pkt_filter_stats_t;
1975 1975
1976typedef struct wl_pkteng { 1976typedef struct wl_pkteng {
1977 uint32 flags; 1977 u32 flags;
1978 uint32 delay; /* Inter-packet delay */ 1978 u32 delay; /* Inter-packet delay */
1979 uint32 nframes; /* Number of frames */ 1979 u32 nframes; /* Number of frames */
1980 uint32 length; /* Packet length */ 1980 u32 length; /* Packet length */
1981 u8 seqno; /* Enable/disable sequence no. */ 1981 u8 seqno; /* Enable/disable sequence no. */
1982 struct ether_addr dest; /* Destination address */ 1982 struct ether_addr dest; /* Destination address */
1983 struct ether_addr src; /* Source address */ 1983 struct ether_addr src; /* Source address */
diff --git a/drivers/staging/brcm80211/phy/wlc_phy_cmn.c b/drivers/staging/brcm80211/phy/wlc_phy_cmn.c
index 17f816f02ee..643b1073f68 100644
--- a/drivers/staging/brcm80211/phy/wlc_phy_cmn.c
+++ b/drivers/staging/brcm80211/phy/wlc_phy_cmn.c
@@ -30,7 +30,7 @@
30#include <wlc_phy_radio.h> 30#include <wlc_phy_radio.h>
31#include <wlc_phy_lcn.h> 31#include <wlc_phy_lcn.h>
32 32
33uint32 phyhal_msg_level = PHYHAL_ERROR; 33u32 phyhal_msg_level = PHYHAL_ERROR;
34 34
35typedef struct _chan_info_basic { 35typedef struct _chan_info_basic {
36 u16 chan; 36 u16 chan;
@@ -126,10 +126,10 @@ const u8 ofdm_rate_lookup[] = {
126#define PHY_WREG_LIMIT 24 126#define PHY_WREG_LIMIT 24
127 127
128static void wlc_set_phy_uninitted(phy_info_t *pi); 128static void wlc_set_phy_uninitted(phy_info_t *pi);
129static uint32 wlc_phy_get_radio_ver(phy_info_t *pi); 129static u32 wlc_phy_get_radio_ver(phy_info_t *pi);
130static void wlc_phy_timercb_phycal(void *arg); 130static void wlc_phy_timercb_phycal(void *arg);
131 131
132static bool wlc_phy_noise_calc_phy(phy_info_t *pi, uint32 *cmplx_pwr, 132static bool wlc_phy_noise_calc_phy(phy_info_t *pi, u32 *cmplx_pwr,
133 s8 *pwr_ant); 133 s8 *pwr_ant);
134 134
135static void wlc_phy_cal_perical_mphase_schedule(phy_info_t *pi, uint delay); 135static void wlc_phy_cal_perical_mphase_schedule(phy_info_t *pi, uint delay);
@@ -142,8 +142,8 @@ static void wlc_phy_txpower_reg_limit_calc(phy_info_t *pi,
142static bool wlc_phy_cal_txpower_recalc_sw(phy_info_t *pi); 142static bool wlc_phy_cal_txpower_recalc_sw(phy_info_t *pi);
143 143
144static s8 wlc_user_txpwr_antport_to_rfport(phy_info_t *pi, uint chan, 144static s8 wlc_user_txpwr_antport_to_rfport(phy_info_t *pi, uint chan,
145 uint32 band, u8 rate); 145 u32 band, u8 rate);
146static void wlc_phy_upd_env_txpwr_rate_limits(phy_info_t *pi, uint32 band); 146static void wlc_phy_upd_env_txpwr_rate_limits(phy_info_t *pi, u32 band);
147static s8 wlc_phy_env_measure_vbat(phy_info_t *pi); 147static s8 wlc_phy_env_measure_vbat(phy_info_t *pi);
148static s8 wlc_phy_env_measure_temperature(phy_info_t *pi); 148static s8 wlc_phy_env_measure_temperature(phy_info_t *pi);
149 149
@@ -304,31 +304,31 @@ void write_radio_reg(phy_info_t *pi, u16 addr, u16 val)
304 } 304 }
305} 305}
306 306
307static uint32 read_radio_id(phy_info_t *pi) 307static u32 read_radio_id(phy_info_t *pi)
308{ 308{
309 uint32 id; 309 u32 id;
310 310
311 if (NORADIO_ENAB(pi->pubpi)) 311 if (NORADIO_ENAB(pi->pubpi))
312 return NORADIO_IDCODE; 312 return NORADIO_IDCODE;
313 313
314 if (D11REV_GE(pi->sh->corerev, 24)) { 314 if (D11REV_GE(pi->sh->corerev, 24)) {
315 uint32 b0, b1, b2; 315 u32 b0, b1, b2;
316 316
317 W_REG(pi->sh->osh, &pi->regs->radioregaddr, 0); 317 W_REG(pi->sh->osh, &pi->regs->radioregaddr, 0);
318#ifdef __mips__ 318#ifdef __mips__
319 (void)R_REG(pi->sh->osh, &pi->regs->radioregaddr); 319 (void)R_REG(pi->sh->osh, &pi->regs->radioregaddr);
320#endif 320#endif
321 b0 = (uint32) R_REG(pi->sh->osh, &pi->regs->radioregdata); 321 b0 = (u32) R_REG(pi->sh->osh, &pi->regs->radioregdata);
322 W_REG(pi->sh->osh, &pi->regs->radioregaddr, 1); 322 W_REG(pi->sh->osh, &pi->regs->radioregaddr, 1);
323#ifdef __mips__ 323#ifdef __mips__
324 (void)R_REG(pi->sh->osh, &pi->regs->radioregaddr); 324 (void)R_REG(pi->sh->osh, &pi->regs->radioregaddr);
325#endif 325#endif
326 b1 = (uint32) R_REG(pi->sh->osh, &pi->regs->radioregdata); 326 b1 = (u32) R_REG(pi->sh->osh, &pi->regs->radioregdata);
327 W_REG(pi->sh->osh, &pi->regs->radioregaddr, 2); 327 W_REG(pi->sh->osh, &pi->regs->radioregaddr, 2);
328#ifdef __mips__ 328#ifdef __mips__
329 (void)R_REG(pi->sh->osh, &pi->regs->radioregaddr); 329 (void)R_REG(pi->sh->osh, &pi->regs->radioregaddr);
330#endif 330#endif
331 b2 = (uint32) R_REG(pi->sh->osh, &pi->regs->radioregdata); 331 b2 = (u32) R_REG(pi->sh->osh, &pi->regs->radioregdata);
332 332
333 id = ((b0 & 0xf) << 28) | (((b2 << 8) | b1) << 12) | ((b0 >> 4) 333 id = ((b0 & 0xf) << 28) | (((b2 << 8) | b1) << 12) | ((b0 >> 4)
334 & 0xf); 334 & 0xf);
@@ -337,8 +337,8 @@ static uint32 read_radio_id(phy_info_t *pi)
337#ifdef __mips__ 337#ifdef __mips__
338 (void)R_REG(pi->sh->osh, &pi->regs->phy4waddr); 338 (void)R_REG(pi->sh->osh, &pi->regs->phy4waddr);
339#endif 339#endif
340 id = (uint32) R_REG(pi->sh->osh, &pi->regs->phy4wdatalo); 340 id = (u32) R_REG(pi->sh->osh, &pi->regs->phy4wdatalo);
341 id |= (uint32) R_REG(pi->sh->osh, &pi->regs->phy4wdatahi) << 16; 341 id |= (u32) R_REG(pi->sh->osh, &pi->regs->phy4wdatahi) << 16;
342 } 342 }
343 pi->phy_wreg = 0; 343 pi->phy_wreg = 0;
344 return id; 344 return id;
@@ -396,7 +396,7 @@ void write_phy_channel_reg(phy_info_t *pi, uint val)
396#if defined(BCMDBG) 396#if defined(BCMDBG)
397static bool wlc_phy_war41476(phy_info_t *pi) 397static bool wlc_phy_war41476(phy_info_t *pi)
398{ 398{
399 uint32 mc = R_REG(pi->sh->osh, &pi->regs->maccontrol); 399 u32 mc = R_REG(pi->sh->osh, &pi->regs->maccontrol);
400 400
401 return ((mc & MCTL_EN_MAC) == 0) 401 return ((mc & MCTL_EN_MAC) == 0)
402 || ((mc & MCTL_PHYLOCK) == MCTL_PHYLOCK); 402 || ((mc & MCTL_PHYLOCK) == MCTL_PHYLOCK);
@@ -439,7 +439,7 @@ void write_phy_reg(phy_info_t *pi, u16 addr, u16 val)
439 if (addr == 0x72) 439 if (addr == 0x72)
440 (void)R_REG(osh, &regs->phyregdata); 440 (void)R_REG(osh, &regs->phyregdata);
441#else 441#else
442 W_REG(osh, (volatile uint32 *)(uintptr) (&regs->phyregaddr), 442 W_REG(osh, (volatile u32 *)(uintptr) (&regs->phyregaddr),
443 addr | (val << 16)); 443 addr | (val << 16));
444 if (BUSTYPE(pi->sh->bustype) == PCI_BUS) { 444 if (BUSTYPE(pi->sh->bustype) == PCI_BUS) {
445 if (++pi->phy_wreg >= pi->phy_wreg_limit) { 445 if (++pi->phy_wreg >= pi->phy_wreg_limit) {
@@ -607,7 +607,7 @@ void BCMATTACHFN(wlc_phy_shared_detach) (shared_phy_t *phy_sh)
607wlc_phy_t *BCMATTACHFN(wlc_phy_attach) (shared_phy_t *sh, void *regs, 607wlc_phy_t *BCMATTACHFN(wlc_phy_attach) (shared_phy_t *sh, void *regs,
608 int bandtype, char *vars) { 608 int bandtype, char *vars) {
609 phy_info_t *pi; 609 phy_info_t *pi;
610 uint32 sflags = 0; 610 u32 sflags = 0;
611 uint phyversion; 611 uint phyversion;
612 int i; 612 int i;
613 osl_t *osh; 613 osl_t *osh;
@@ -686,7 +686,7 @@ wlc_phy_t *BCMATTACHFN(wlc_phy_attach) (shared_phy_t *sh, void *regs,
686 pi->pubpi.radioid = NORADIO_ID; 686 pi->pubpi.radioid = NORADIO_ID;
687 pi->pubpi.radiorev = 5; 687 pi->pubpi.radiorev = 5;
688 } else { 688 } else {
689 uint32 idcode; 689 u32 idcode;
690 690
691 wlc_phy_anacore((wlc_phy_t *) pi, ON); 691 wlc_phy_anacore((wlc_phy_t *) pi, ON);
692 692
@@ -833,7 +833,7 @@ bool wlc_phy_get_encore(wlc_phy_t *pih)
833 return pi->pubpi.abgphy_encore; 833 return pi->pubpi.abgphy_encore;
834} 834}
835 835
836uint32 wlc_phy_get_coreflags(wlc_phy_t *pih) 836u32 wlc_phy_get_coreflags(wlc_phy_t *pih)
837{ 837{
838 phy_info_t *pi = (phy_info_t *) pih; 838 phy_info_t *pi = (phy_info_t *) pih;
839 return pi->pubpi.coreflags; 839 return pi->pubpi.coreflags;
@@ -899,11 +899,11 @@ void wlc_phy_anacore(wlc_phy_t *pih, bool on)
899 } 899 }
900} 900}
901 901
902uint32 wlc_phy_clk_bwbits(wlc_phy_t *pih) 902u32 wlc_phy_clk_bwbits(wlc_phy_t *pih)
903{ 903{
904 phy_info_t *pi = (phy_info_t *) pih; 904 phy_info_t *pi = (phy_info_t *) pih;
905 905
906 uint32 phy_bw_clkbits = 0; 906 u32 phy_bw_clkbits = 0;
907 907
908 if (pi && (ISNPHY(pi) || ISLCNPHY(pi))) { 908 if (pi && (ISNPHY(pi) || ISLCNPHY(pi))) {
909 switch (pi->bw) { 909 switch (pi->bw) {
@@ -973,7 +973,7 @@ void wlc_phy_hw_state_upd(wlc_phy_t *pih, bool newstate)
973 973
974void WLBANDINITFN(wlc_phy_init) (wlc_phy_t *pih, chanspec_t chanspec) 974void WLBANDINITFN(wlc_phy_init) (wlc_phy_t *pih, chanspec_t chanspec)
975{ 975{
976 uint32 mc; 976 u32 mc;
977 initfn_t phy_init = NULL; 977 initfn_t phy_init = NULL;
978 phy_info_t *pi = (phy_info_t *) pih; 978 phy_info_t *pi = (phy_info_t *) pih;
979 979
@@ -1064,9 +1064,9 @@ int BCMUNINITFN(wlc_phy_down) (wlc_phy_t *pih)
1064 return callbacks; 1064 return callbacks;
1065} 1065}
1066 1066
1067static uint32 wlc_phy_get_radio_ver(phy_info_t *pi) 1067static u32 wlc_phy_get_radio_ver(phy_info_t *pi)
1068{ 1068{
1069 uint32 ver; 1069 u32 ver;
1070 1070
1071 ver = read_radio_id(pi); 1071 ver = read_radio_id(pi);
1072 1072
@@ -1091,7 +1091,7 @@ wlc_phy_table_addr(phy_info_t *pi, uint tbl_id, uint tbl_offset,
1091 } 1091 }
1092} 1092}
1093 1093
1094void wlc_phy_table_data_write(phy_info_t *pi, uint width, uint32 val) 1094void wlc_phy_table_data_write(phy_info_t *pi, uint width, u32 val)
1095{ 1095{
1096 ASSERT((width == 8) || (width == 16) || (width == 32)); 1096 ASSERT((width == 8) || (width == 16) || (width == 32));
1097 1097
@@ -1126,7 +1126,7 @@ wlc_phy_write_table(phy_info_t *pi, const phytbl_info_t *ptbl_info,
1126 uint tbl_width = ptbl_info->tbl_width; 1126 uint tbl_width = ptbl_info->tbl_width;
1127 const u8 *ptbl_8b = (const u8 *)ptbl_info->tbl_ptr; 1127 const u8 *ptbl_8b = (const u8 *)ptbl_info->tbl_ptr;
1128 const u16 *ptbl_16b = (const u16 *)ptbl_info->tbl_ptr; 1128 const u16 *ptbl_16b = (const u16 *)ptbl_info->tbl_ptr;
1129 const uint32 *ptbl_32b = (const uint32 *)ptbl_info->tbl_ptr; 1129 const u32 *ptbl_32b = (const u32 *)ptbl_info->tbl_ptr;
1130 1130
1131 ASSERT((tbl_width == 8) || (tbl_width == 16) || (tbl_width == 32)); 1131 ASSERT((tbl_width == 8) || (tbl_width == 16) || (tbl_width == 32));
1132 1132
@@ -1169,7 +1169,7 @@ wlc_phy_read_table(phy_info_t *pi, const phytbl_info_t *ptbl_info,
1169 uint tbl_width = ptbl_info->tbl_width; 1169 uint tbl_width = ptbl_info->tbl_width;
1170 u8 *ptbl_8b = (u8 *) (uintptr) ptbl_info->tbl_ptr; 1170 u8 *ptbl_8b = (u8 *) (uintptr) ptbl_info->tbl_ptr;
1171 u16 *ptbl_16b = (u16 *) (uintptr) ptbl_info->tbl_ptr; 1171 u16 *ptbl_16b = (u16 *) (uintptr) ptbl_info->tbl_ptr;
1172 uint32 *ptbl_32b = (uint32 *) (uintptr) ptbl_info->tbl_ptr; 1172 u32 *ptbl_32b = (u32 *) (uintptr) ptbl_info->tbl_ptr;
1173 1173
1174 ASSERT((tbl_width == 8) || (tbl_width == 16) || (tbl_width == 32)); 1174 ASSERT((tbl_width == 8) || (tbl_width == 16) || (tbl_width == 32));
1175 1175
@@ -1264,11 +1264,11 @@ void wlc_phy_do_dummy_tx(phy_info_t *pi, bool ofdm, bool pa_on)
1264 0x6e, 0x84, 0x0b, 0x00, 0x00, 0x00, 0xd4, 0x00, 0x00, 0x00, 1264 0x6e, 0x84, 0x0b, 0x00, 0x00, 0x00, 0xd4, 0x00, 0x00, 0x00,
1265 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00 1265 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00
1266 }; 1266 };
1267 uint32 *dummypkt; 1267 u32 *dummypkt;
1268 1268
1269 ASSERT((R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC) == 0); 1269 ASSERT((R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC) == 0);
1270 1270
1271 dummypkt = (uint32 *) (ofdm ? ofdmpkt : cckpkt); 1271 dummypkt = (u32 *) (ofdm ? ofdmpkt : cckpkt);
1272 wlapi_bmac_write_template_ram(pi->sh->physhim, 0, DUMMY_PKT_LEN, 1272 wlapi_bmac_write_template_ram(pi->sh->physhim, 0, DUMMY_PKT_LEN,
1273 dummypkt); 1273 dummypkt);
1274 1274
@@ -1783,7 +1783,7 @@ wlc_phy_txpower_sromlimit_max_get(wlc_phy_t *ppi, uint chan, u8 *max_txpwr,
1783 1783
1784void 1784void
1785wlc_phy_txpower_boardlimit_band(wlc_phy_t *ppi, uint bandunit, int32 *max_pwr, 1785wlc_phy_txpower_boardlimit_band(wlc_phy_t *ppi, uint bandunit, int32 *max_pwr,
1786 int32 *min_pwr, uint32 *step_pwr) 1786 int32 *min_pwr, u32 *step_pwr)
1787{ 1787{
1788 return; 1788 return;
1789} 1789}
@@ -1813,7 +1813,7 @@ void wlc_phy_txpower_recalc_target(phy_info_t *pi)
1813 u8 max_num_rate; 1813 u8 max_num_rate;
1814 u8 start_rate = 0; 1814 u8 start_rate = 0;
1815 chanspec_t chspec; 1815 chanspec_t chspec;
1816 uint32 band = CHSPEC2WLC_BAND(pi->radio_chanspec); 1816 u32 band = CHSPEC2WLC_BAND(pi->radio_chanspec);
1817 initfn_t txpwr_recalc_fn = NULL; 1817 initfn_t txpwr_recalc_fn = NULL;
1818 1818
1819 chspec = pi->radio_chanspec; 1819 chspec = pi->radio_chanspec;
@@ -1826,7 +1826,7 @@ void wlc_phy_txpower_recalc_target(phy_info_t *pi)
1826 1826
1827 pactrl = 0; 1827 pactrl = 0;
1828 if (ISLCNPHY(pi)) { 1828 if (ISLCNPHY(pi)) {
1829 uint32 offset_mcs, i; 1829 u32 offset_mcs, i;
1830 1830
1831 if (CHSPEC_IS40(pi->radio_chanspec)) { 1831 if (CHSPEC_IS40(pi->radio_chanspec)) {
1832 offset_mcs = pi->mcs40_po; 1832 offset_mcs = pi->mcs40_po;
@@ -2080,7 +2080,7 @@ void wlc_phy_txpwr_percent_set(wlc_phy_t *ppi, u8 txpwr_percent)
2080 pi->txpwr_percent = txpwr_percent; 2080 pi->txpwr_percent = txpwr_percent;
2081} 2081}
2082 2082
2083void wlc_phy_machwcap_set(wlc_phy_t *ppi, uint32 machwcap) 2083void wlc_phy_machwcap_set(wlc_phy_t *ppi, u32 machwcap)
2084{ 2084{
2085 phy_info_t *pi = (phy_info_t *) ppi; 2085 phy_info_t *pi = (phy_info_t *) ppi;
2086 2086
@@ -2270,14 +2270,14 @@ void wlc_phy_txpower_ipa_upd(phy_info_t *pi)
2270 } 2270 }
2271} 2271}
2272 2272
2273static uint32 wlc_phy_txpower_est_power_nphy(phy_info_t *pi); 2273static u32 wlc_phy_txpower_est_power_nphy(phy_info_t *pi);
2274 2274
2275static uint32 wlc_phy_txpower_est_power_nphy(phy_info_t *pi) 2275static u32 wlc_phy_txpower_est_power_nphy(phy_info_t *pi)
2276{ 2276{
2277 s16 tx0_status, tx1_status; 2277 s16 tx0_status, tx1_status;
2278 u16 estPower1, estPower2; 2278 u16 estPower1, estPower2;
2279 u8 pwr0, pwr1, adj_pwr0, adj_pwr1; 2279 u8 pwr0, pwr1, adj_pwr0, adj_pwr1;
2280 uint32 est_pwr; 2280 u32 est_pwr;
2281 2281
2282 estPower1 = read_phy_reg(pi, 0x118); 2282 estPower1 = read_phy_reg(pi, 0x118);
2283 estPower2 = read_phy_reg(pi, 0x119); 2283 estPower2 = read_phy_reg(pi, 0x119);
@@ -2317,7 +2317,7 @@ static uint32 wlc_phy_txpower_est_power_nphy(phy_info_t *pi)
2317 } 2317 }
2318 2318
2319 est_pwr = 2319 est_pwr =
2320 (uint32) ((pwr0 << 24) | (pwr1 << 16) | (adj_pwr0 << 8) | adj_pwr1); 2320 (u32) ((pwr0 << 24) | (pwr1 << 16) | (adj_pwr0 << 8) | adj_pwr1);
2321 return est_pwr; 2321 return est_pwr;
2322} 2322}
2323 2323
@@ -2360,7 +2360,7 @@ wlc_phy_txpower_get_current(wlc_phy_t *ppi, tx_power_t *power, uint channel)
2360 } 2360 }
2361 2361
2362 if (ISNPHY(pi)) { 2362 if (ISNPHY(pi)) {
2363 uint32 est_pout; 2363 u32 est_pout;
2364 2364
2365 wlapi_suspend_mac_and_wait(pi->sh->physhim); 2365 wlapi_suspend_mac_and_wait(pi->sh->physhim);
2366 wlc_phyreg_enter((wlc_phy_t *) pi); 2366 wlc_phyreg_enter((wlc_phy_t *) pi);
@@ -2504,7 +2504,7 @@ void wlc_phy_ant_rxdiv_set(wlc_phy_t *ppi, u8 val)
2504} 2504}
2505 2505
2506static bool 2506static bool
2507wlc_phy_noise_calc_phy(phy_info_t *pi, uint32 *cmplx_pwr, s8 *pwr_ant) 2507wlc_phy_noise_calc_phy(phy_info_t *pi, u32 *cmplx_pwr, s8 *pwr_ant)
2508{ 2508{
2509 s8 cmplx_pwr_dbm[PHY_CORE_MAX]; 2509 s8 cmplx_pwr_dbm[PHY_CORE_MAX];
2510 u8 i; 2510 u8 i;
@@ -2616,7 +2616,7 @@ wlc_phy_noise_sample_request(wlc_phy_t *pih, u8 reason, u8 ch)
2616 MCMD_BG_NOISE); 2616 MCMD_BG_NOISE);
2617 } else { 2617 } else {
2618 phy_iq_est_t est[PHY_CORE_MAX]; 2618 phy_iq_est_t est[PHY_CORE_MAX];
2619 uint32 cmplx_pwr[PHY_CORE_MAX]; 2619 u32 cmplx_pwr[PHY_CORE_MAX];
2620 s8 noise_dbm_ant[PHY_CORE_MAX]; 2620 s8 noise_dbm_ant[PHY_CORE_MAX];
2621 u16 log_num_samps, num_samps, classif_state = 0; 2621 u16 log_num_samps, num_samps, classif_state = 0;
2622 u8 wait_time = 32; 2622 u8 wait_time = 32;
@@ -2698,10 +2698,10 @@ static void wlc_phy_noise_cb(phy_info_t *pi, u8 channel, s8 noise_dbm)
2698 2698
2699static s8 wlc_phy_noise_read_shmem(phy_info_t *pi) 2699static s8 wlc_phy_noise_read_shmem(phy_info_t *pi)
2700{ 2700{
2701 uint32 cmplx_pwr[PHY_CORE_MAX]; 2701 u32 cmplx_pwr[PHY_CORE_MAX];
2702 s8 noise_dbm_ant[PHY_CORE_MAX]; 2702 s8 noise_dbm_ant[PHY_CORE_MAX];
2703 u16 lo, hi; 2703 u16 lo, hi;
2704 uint32 cmplx_pwr_tot = 0; 2704 u32 cmplx_pwr_tot = 0;
2705 s8 noise_dbm = PHY_NOISE_FIXED_VAL_NPHY; 2705 s8 noise_dbm = PHY_NOISE_FIXED_VAL_NPHY;
2706 u8 idx, core; 2706 u8 idx, core;
2707 2707
@@ -2746,7 +2746,7 @@ void wlc_phy_noise_sample_intr(wlc_phy_t *pih)
2746 s8 noise_dbm = PHY_NOISE_FIXED_VAL_NPHY; 2746 s8 noise_dbm = PHY_NOISE_FIXED_VAL_NPHY;
2747 2747
2748 if (ISLCNPHY(pi)) { 2748 if (ISLCNPHY(pi)) {
2749 uint32 cmplx_pwr, cmplx_pwr0, cmplx_pwr1; 2749 u32 cmplx_pwr, cmplx_pwr0, cmplx_pwr1;
2750 u16 lo, hi; 2750 u16 lo, hi;
2751 int32 pwr_offset_dB, gain_dB; 2751 int32 pwr_offset_dB, gain_dB;
2752 u16 status_0, status_1; 2752 u16 status_0, status_1;
@@ -2836,10 +2836,10 @@ s8 lcnphy_gain_index_offset_for_pkt_rssi[] = {
2836 0 2836 0
2837}; 2837};
2838 2838
2839void wlc_phy_compute_dB(uint32 *cmplx_pwr, s8 *p_cmplx_pwr_dB, u8 core) 2839void wlc_phy_compute_dB(u32 *cmplx_pwr, s8 *p_cmplx_pwr_dB, u8 core)
2840{ 2840{
2841 u8 shift_ct, lsb, msb, secondmsb, i; 2841 u8 shift_ct, lsb, msb, secondmsb, i;
2842 uint32 tmp; 2842 u32 tmp;
2843 2843
2844 for (i = 0; i < core; i++) { 2844 for (i = 0; i < core; i++) {
2845 tmp = cmplx_pwr[i]; 2845 tmp = cmplx_pwr[i];
@@ -3021,7 +3021,7 @@ void wlc_phy_BSSinit(wlc_phy_t *pih, bool bonlyap, int rssi)
3021} 3021}
3022 3022
3023void 3023void
3024wlc_phy_papd_decode_epsilon(uint32 epsilon, int32 *eps_real, int32 *eps_imag) 3024wlc_phy_papd_decode_epsilon(u32 epsilon, int32 *eps_real, int32 *eps_imag)
3025{ 3025{
3026 *eps_imag = (epsilon >> 13); 3026 *eps_imag = (epsilon >> 13);
3027 if (*eps_imag > 0xfff) 3027 if (*eps_imag > 0xfff)
@@ -3219,9 +3219,9 @@ u8 wlc_phy_nbits(int32 value)
3219 return nbits; 3219 return nbits;
3220} 3220}
3221 3221
3222uint32 wlc_phy_sqrt_int(uint32 value) 3222u32 wlc_phy_sqrt_int(u32 value)
3223{ 3223{
3224 uint32 root = 0, shift = 0; 3224 u32 root = 0, shift = 0;
3225 3225
3226 for (shift = 0; shift < 32; shift += 2) { 3226 for (shift = 0; shift < 32; shift += 2) {
3227 if (((0x40000000 >> shift) + root) <= value) { 3227 if (((0x40000000 >> shift) + root) <= value) {
@@ -3363,7 +3363,7 @@ void wlc_lcnphy_epa_switch(phy_info_t *pi, bool mode)
3363} 3363}
3364 3364
3365static s8 3365static s8
3366wlc_user_txpwr_antport_to_rfport(phy_info_t *pi, uint chan, uint32 band, 3366wlc_user_txpwr_antport_to_rfport(phy_info_t *pi, uint chan, u32 band,
3367 u8 rate) 3367 u8 rate)
3368{ 3368{
3369 s8 offset = 0; 3369 s8 offset = 0;
@@ -3389,7 +3389,7 @@ static s8 wlc_phy_env_measure_temperature(phy_info_t *pi)
3389 return 0; 3389 return 0;
3390} 3390}
3391 3391
3392static void wlc_phy_upd_env_txpwr_rate_limits(phy_info_t *pi, uint32 band) 3392static void wlc_phy_upd_env_txpwr_rate_limits(phy_info_t *pi, u32 band)
3393{ 3393{
3394 u8 i; 3394 u8 i;
3395 s8 temp, vbat; 3395 s8 temp, vbat;
@@ -3414,9 +3414,9 @@ wlc_phy_get_pwrdet_offsets(phy_info_t *pi, s8 *cckoffset, s8 *ofdmoffset)
3414 *ofdmoffset = 0; 3414 *ofdmoffset = 0;
3415} 3415}
3416 3416
3417uint32 wlc_phy_qdiv_roundup(uint32 dividend, uint32 divisor, u8 precision) 3417u32 wlc_phy_qdiv_roundup(u32 dividend, u32 divisor, u8 precision)
3418{ 3418{
3419 uint32 quotient, remainder, roundup, rbit; 3419 u32 quotient, remainder, roundup, rbit;
3420 3420
3421 ASSERT(divisor); 3421 ASSERT(divisor);
3422 3422
diff --git a/drivers/staging/brcm80211/phy/wlc_phy_hal.h b/drivers/staging/brcm80211/phy/wlc_phy_hal.h
index 849530a8e00..e92e4e6efda 100644
--- a/drivers/staging/brcm80211/phy/wlc_phy_hal.h
+++ b/drivers/staging/brcm80211/phy/wlc_phy_hal.h
@@ -147,8 +147,8 @@ typedef struct shared_phy_params {
147 uint boardtype; 147 uint boardtype;
148 uint boardrev; 148 uint boardrev;
149 uint boardvendor; 149 uint boardvendor;
150 uint32 boardflags; 150 u32 boardflags;
151 uint32 boardflags2; 151 u32 boardflags2;
152} shared_phy_params_t; 152} shared_phy_params_t;
153 153
154#ifdef WLC_LOW 154#ifdef WLC_LOW
@@ -163,14 +163,14 @@ extern bool wlc_phy_get_phyversion(wlc_phy_t *pih, u16 *phytype,
163 u16 *phyrev, u16 *radioid, 163 u16 *phyrev, u16 *radioid,
164 u16 *radiover); 164 u16 *radiover);
165extern bool wlc_phy_get_encore(wlc_phy_t *pih); 165extern bool wlc_phy_get_encore(wlc_phy_t *pih);
166extern uint32 wlc_phy_get_coreflags(wlc_phy_t *pih); 166extern u32 wlc_phy_get_coreflags(wlc_phy_t *pih);
167 167
168extern void wlc_phy_hw_clk_state_upd(wlc_phy_t *ppi, bool newstate); 168extern void wlc_phy_hw_clk_state_upd(wlc_phy_t *ppi, bool newstate);
169extern void wlc_phy_hw_state_upd(wlc_phy_t *ppi, bool newstate); 169extern void wlc_phy_hw_state_upd(wlc_phy_t *ppi, bool newstate);
170extern void wlc_phy_init(wlc_phy_t *ppi, chanspec_t chanspec); 170extern void wlc_phy_init(wlc_phy_t *ppi, chanspec_t chanspec);
171extern void wlc_phy_watchdog(wlc_phy_t *ppi); 171extern void wlc_phy_watchdog(wlc_phy_t *ppi);
172extern int wlc_phy_down(wlc_phy_t *ppi); 172extern int wlc_phy_down(wlc_phy_t *ppi);
173extern uint32 wlc_phy_clk_bwbits(wlc_phy_t *pih); 173extern u32 wlc_phy_clk_bwbits(wlc_phy_t *pih);
174extern void wlc_phy_cal_init(wlc_phy_t *ppi); 174extern void wlc_phy_cal_init(wlc_phy_t *ppi);
175extern void wlc_phy_antsel_init(wlc_phy_t *ppi, bool lut_init); 175extern void wlc_phy_antsel_init(wlc_phy_t *ppi, bool lut_init);
176 176
@@ -205,7 +205,7 @@ extern void wlc_phy_txpower_sromlimit(wlc_phy_t *ppi, uint chan,
205extern void wlc_phy_txpower_sromlimit_max_get(wlc_phy_t *ppi, uint chan, 205extern void wlc_phy_txpower_sromlimit_max_get(wlc_phy_t *ppi, uint chan,
206 u8 *_max_, u8 *_min_); 206 u8 *_max_, u8 *_min_);
207extern void wlc_phy_txpower_boardlimit_band(wlc_phy_t *ppi, uint band, int32 *, 207extern void wlc_phy_txpower_boardlimit_band(wlc_phy_t *ppi, uint band, int32 *,
208 int32 *, uint32 *); 208 int32 *, u32 *);
209extern void wlc_phy_txpower_limit_set(wlc_phy_t *ppi, struct txpwr_limits *, 209extern void wlc_phy_txpower_limit_set(wlc_phy_t *ppi, struct txpwr_limits *,
210 chanspec_t chanspec); 210 chanspec_t chanspec);
211extern int wlc_phy_txpower_get(wlc_phy_t *ppi, uint *qdbm, bool *override); 211extern int wlc_phy_txpower_get(wlc_phy_t *ppi, uint *qdbm, bool *override);
@@ -248,7 +248,7 @@ extern bool wlc_phy_test_ison(wlc_phy_t *ppi);
248extern void wlc_phy_txpwr_percent_set(wlc_phy_t *ppi, u8 txpwr_percent); 248extern void wlc_phy_txpwr_percent_set(wlc_phy_t *ppi, u8 txpwr_percent);
249extern void wlc_phy_ofdm_rateset_war(wlc_phy_t *pih, bool war); 249extern void wlc_phy_ofdm_rateset_war(wlc_phy_t *pih, bool war);
250extern void wlc_phy_bf_preempt_enable(wlc_phy_t *pih, bool bf_preempt); 250extern void wlc_phy_bf_preempt_enable(wlc_phy_t *pih, bool bf_preempt);
251extern void wlc_phy_machwcap_set(wlc_phy_t *ppi, uint32 machwcap); 251extern void wlc_phy_machwcap_set(wlc_phy_t *ppi, u32 machwcap);
252 252
253extern void wlc_phy_runbist_config(wlc_phy_t *ppi, bool start_end); 253extern void wlc_phy_runbist_config(wlc_phy_t *ppi, bool start_end);
254 254
diff --git a/drivers/staging/brcm80211/phy/wlc_phy_int.h b/drivers/staging/brcm80211/phy/wlc_phy_int.h
index 91e9f7ae776..1c178117f0f 100644
--- a/drivers/staging/brcm80211/phy/wlc_phy_int.h
+++ b/drivers/staging/brcm80211/phy/wlc_phy_int.h
@@ -27,7 +27,7 @@
27#define PHYHAL_TRACE 0x0002 27#define PHYHAL_TRACE 0x0002
28#define PHYHAL_INFORM 0x0004 28#define PHYHAL_INFORM 0x0004
29 29
30extern uint32 phyhal_msg_level; 30extern u32 phyhal_msg_level;
31 31
32#define PHY_INFORM_ON() (phyhal_msg_level & PHYHAL_INFORM) 32#define PHY_INFORM_ON() (phyhal_msg_level & PHYHAL_INFORM)
33#define PHY_THERMAL_ON() (phyhal_msg_level & PHYHAL_THERMAL) 33#define PHY_THERMAL_ON() (phyhal_msg_level & PHYHAL_THERMAL)
@@ -292,10 +292,10 @@ typedef struct _phy_table_info {
292 292
293typedef struct phytbl_info { 293typedef struct phytbl_info {
294 const void *tbl_ptr; 294 const void *tbl_ptr;
295 uint32 tbl_len; 295 u32 tbl_len;
296 uint32 tbl_id; 296 u32 tbl_id;
297 uint32 tbl_offset; 297 u32 tbl_offset;
298 uint32 tbl_width; 298 u32 tbl_width;
299} phytbl_info_t; 299} phytbl_info_t;
300 300
301typedef struct { 301typedef struct {
@@ -485,8 +485,8 @@ typedef struct _nphy_txgains {
485typedef struct _nphy_noisevar_buf { 485typedef struct _nphy_noisevar_buf {
486 int bufcount; 486 int bufcount;
487 int tone_id[PHY_NOISEVAR_BUFSIZE]; 487 int tone_id[PHY_NOISEVAR_BUFSIZE];
488 uint32 noise_vars[PHY_NOISEVAR_BUFSIZE]; 488 u32 noise_vars[PHY_NOISEVAR_BUFSIZE];
489 uint32 min_noise_vars[PHY_NOISEVAR_BUFSIZE]; 489 u32 min_noise_vars[PHY_NOISEVAR_BUFSIZE];
490} phy_noisevar_buf_t; 490} phy_noisevar_buf_t;
491 491
492typedef struct { 492typedef struct {
@@ -510,7 +510,7 @@ typedef struct {
510 u16 txiqlocal_bestcoeffs[11]; 510 u16 txiqlocal_bestcoeffs[11];
511 u16 txiqlocal_bestcoeffs_valid; 511 u16 txiqlocal_bestcoeffs_valid;
512 512
513 uint32 papd_eps_tbl[PHY_PAPD_EPS_TBL_SIZE_LCNPHY]; 513 u32 papd_eps_tbl[PHY_PAPD_EPS_TBL_SIZE_LCNPHY];
514 u16 analog_gain_ref; 514 u16 analog_gain_ref;
515 u16 lut_begin; 515 u16 lut_begin;
516 u16 lut_end; 516 u16 lut_end;
@@ -530,7 +530,7 @@ struct shared_phy {
530 si_t *sih; 530 si_t *sih;
531 void *physhim; 531 void *physhim;
532 uint corerev; 532 uint corerev;
533 uint32 machwcap; 533 u32 machwcap;
534 bool up; 534 bool up;
535 bool clk; 535 bool clk;
536 uint now; 536 uint now;
@@ -543,8 +543,8 @@ struct shared_phy {
543 uint boardtype; 543 uint boardtype;
544 uint boardrev; 544 uint boardrev;
545 uint boardvendor; 545 uint boardvendor;
546 uint32 boardflags; 546 u32 boardflags;
547 uint32 boardflags2; 547 u32 boardflags2;
548 uint bustype; 548 uint bustype;
549 uint buscorerev; 549 uint buscorerev;
550 uint fast_timer; 550 uint fast_timer;
@@ -688,8 +688,8 @@ struct phy_info {
688 688
689 bool edcrs_threshold_lock; 689 bool edcrs_threshold_lock;
690 690
691 uint32 tr_R_gain_val; 691 u32 tr_R_gain_val;
692 uint32 tr_T_gain_val; 692 u32 tr_T_gain_val;
693 693
694 s16 ofdm_analog_filt_bw_override; 694 s16 ofdm_analog_filt_bw_override;
695 s16 cck_analog_filt_bw_override; 695 s16 cck_analog_filt_bw_override;
@@ -701,11 +701,11 @@ struct phy_info {
701 u16 crsglitch_prev; 701 u16 crsglitch_prev;
702 bool interference_mode_crs; 702 bool interference_mode_crs;
703 703
704 uint32 phy_tx_tone_freq; 704 u32 phy_tx_tone_freq;
705 uint phy_lastcal; 705 uint phy_lastcal;
706 bool phy_forcecal; 706 bool phy_forcecal;
707 bool phy_fixed_noise; 707 bool phy_fixed_noise;
708 uint32 xtalfreq; 708 u32 xtalfreq;
709 u8 pdiv; 709 u8 pdiv;
710 s8 carrier_suppr_disable; 710 s8 carrier_suppr_disable;
711 711
@@ -781,16 +781,16 @@ struct phy_info {
781 781
782 bool nphy_tableloaded; 782 bool nphy_tableloaded;
783 s8 nphy_rssisel; 783 s8 nphy_rssisel;
784 uint32 nphy_bb_mult_save; 784 u32 nphy_bb_mult_save;
785 u16 nphy_txiqlocal_bestc[11]; 785 u16 nphy_txiqlocal_bestc[11];
786 bool nphy_txiqlocal_coeffsvalid; 786 bool nphy_txiqlocal_coeffsvalid;
787 phy_txpwrindex_t nphy_txpwrindex[PHY_CORE_NUM_2]; 787 phy_txpwrindex_t nphy_txpwrindex[PHY_CORE_NUM_2];
788 phy_pwrctrl_t nphy_pwrctrl_info[PHY_CORE_NUM_2]; 788 phy_pwrctrl_t nphy_pwrctrl_info[PHY_CORE_NUM_2];
789 u16 cck2gpo; 789 u16 cck2gpo;
790 uint32 ofdm2gpo; 790 u32 ofdm2gpo;
791 uint32 ofdm5gpo; 791 u32 ofdm5gpo;
792 uint32 ofdm5glpo; 792 u32 ofdm5glpo;
793 uint32 ofdm5ghpo; 793 u32 ofdm5ghpo;
794 u8 bw402gpo; 794 u8 bw402gpo;
795 u8 bw405gpo; 795 u8 bw405gpo;
796 u8 bw405glpo; 796 u8 bw405glpo;
@@ -811,7 +811,7 @@ struct phy_info {
811 u16 mcs5gpo[8]; 811 u16 mcs5gpo[8];
812 u16 mcs5glpo[8]; 812 u16 mcs5glpo[8];
813 u16 mcs5ghpo[8]; 813 u16 mcs5ghpo[8];
814 uint32 nphy_rxcalparams; 814 u32 nphy_rxcalparams;
815 815
816 u8 phy_spuravoid; 816 u8 phy_spuravoid;
817 bool phy_isspuravoid; 817 bool phy_isspuravoid;
@@ -863,7 +863,7 @@ struct phy_info {
863 u8 nphy_papd_cal_gain_index[2]; 863 u8 nphy_papd_cal_gain_index[2];
864 s16 nphy_papd_epsilon_offset[2]; 864 s16 nphy_papd_epsilon_offset[2];
865 bool nphy_papd_recal_enable; 865 bool nphy_papd_recal_enable;
866 uint32 nphy_papd_recal_counter; 866 u32 nphy_papd_recal_counter;
867 bool nphy_force_papd_cal; 867 bool nphy_force_papd_cal;
868 bool nphy_papdcomp; 868 bool nphy_papdcomp;
869 bool ipa2g_on; 869 bool ipa2g_on;
@@ -935,8 +935,8 @@ struct phy_info {
935 s8 txpwrindex[PHY_CORE_MAX]; 935 s8 txpwrindex[PHY_CORE_MAX];
936 936
937 u8 phycal_tempdelta; 937 u8 phycal_tempdelta;
938 uint32 mcs20_po; 938 u32 mcs20_po;
939 uint32 mcs40_po; 939 u32 mcs40_po;
940}; 940};
941 941
942typedef int32 fixed; 942typedef int32 fixed;
@@ -948,8 +948,8 @@ typedef struct _cint32 {
948 948
949typedef struct radio_regs { 949typedef struct radio_regs {
950 u16 address; 950 u16 address;
951 uint32 init_a; 951 u32 init_a;
952 uint32 init_g; 952 u32 init_g;
953 u8 do_init_a; 953 u8 do_init_a;
954 u8 do_init_g; 954 u8 do_init_g;
955} radio_regs_t; 955} radio_regs_t;
@@ -1018,15 +1018,15 @@ extern void wlc_phy_write_table(phy_info_t *pi,
1018extern void wlc_phy_table_addr(phy_info_t *pi, uint tbl_id, uint tbl_offset, 1018extern void wlc_phy_table_addr(phy_info_t *pi, uint tbl_id, uint tbl_offset,
1019 u16 tblAddr, u16 tblDataHi, 1019 u16 tblAddr, u16 tblDataHi,
1020 u16 tblDataLo); 1020 u16 tblDataLo);
1021extern void wlc_phy_table_data_write(phy_info_t *pi, uint width, uint32 val); 1021extern void wlc_phy_table_data_write(phy_info_t *pi, uint width, u32 val);
1022 1022
1023extern void write_phy_channel_reg(phy_info_t *pi, uint val); 1023extern void write_phy_channel_reg(phy_info_t *pi, uint val);
1024extern void wlc_phy_txpower_update_shm(phy_info_t *pi); 1024extern void wlc_phy_txpower_update_shm(phy_info_t *pi);
1025 1025
1026extern void wlc_phy_cordic(fixed theta, cint32 *val); 1026extern void wlc_phy_cordic(fixed theta, cint32 *val);
1027extern u8 wlc_phy_nbits(int32 value); 1027extern u8 wlc_phy_nbits(int32 value);
1028extern uint32 wlc_phy_sqrt_int(uint32 value); 1028extern u32 wlc_phy_sqrt_int(u32 value);
1029extern void wlc_phy_compute_dB(uint32 *cmplx_pwr, s8 *p_dB, u8 core); 1029extern void wlc_phy_compute_dB(u32 *cmplx_pwr, s8 *p_dB, u8 core);
1030 1030
1031extern uint wlc_phy_init_radio_regs_allbands(phy_info_t *pi, 1031extern uint wlc_phy_init_radio_regs_allbands(phy_info_t *pi,
1032 radio_20xx_regs_t *radioregs); 1032 radio_20xx_regs_t *radioregs);
@@ -1036,7 +1036,7 @@ extern uint wlc_phy_init_radio_regs(phy_info_t *pi, radio_regs_t *radioregs,
1036extern void wlc_phy_txpower_ipa_upd(phy_info_t *pi); 1036extern void wlc_phy_txpower_ipa_upd(phy_info_t *pi);
1037 1037
1038extern void wlc_phy_do_dummy_tx(phy_info_t *pi, bool ofdm, bool pa_on); 1038extern void wlc_phy_do_dummy_tx(phy_info_t *pi, bool ofdm, bool pa_on);
1039extern void wlc_phy_papd_decode_epsilon(uint32 epsilon, int32 *eps_real, 1039extern void wlc_phy_papd_decode_epsilon(u32 epsilon, int32 *eps_real,
1040 int32 *eps_imag); 1040 int32 *eps_imag);
1041 1041
1042extern void wlc_phy_cal_perical_mphase_reset(phy_info_t *pi); 1042extern void wlc_phy_cal_perical_mphase_reset(phy_info_t *pi);
@@ -1094,7 +1094,7 @@ extern void wlc_lcnphy_epa_switch(phy_info_t *pi, bool mode);
1094extern void wlc_2064_vco_cal(phy_info_t *pi); 1094extern void wlc_2064_vco_cal(phy_info_t *pi);
1095 1095
1096extern void wlc_phy_txpower_recalc_target(phy_info_t *pi); 1096extern void wlc_phy_txpower_recalc_target(phy_info_t *pi);
1097extern uint32 wlc_phy_qdiv_roundup(uint32 dividend, uint32 divisor, 1097extern u32 wlc_phy_qdiv_roundup(u32 dividend, u32 divisor,
1098 u8 precision); 1098 u8 precision);
1099 1099
1100#define LCNPHY_TBL_ID_PAPDCOMPDELTATBL 0x18 1100#define LCNPHY_TBL_ID_PAPDCOMPDELTATBL 0x18
@@ -1133,8 +1133,8 @@ extern int32 wlc_lcnphy_rx_signal_power(phy_info_t *pi, int32 gain_index);
1133 1133
1134typedef struct _phy_iq_est { 1134typedef struct _phy_iq_est {
1135 int32 iq_prod; 1135 int32 iq_prod;
1136 uint32 i_pwr; 1136 u32 i_pwr;
1137 uint32 q_pwr; 1137 u32 q_pwr;
1138} phy_iq_est_t; 1138} phy_iq_est_t;
1139 1139
1140extern void wlc_phy_stay_in_carriersearch_nphy(phy_info_t *pi, bool enable); 1140extern void wlc_phy_stay_in_carriersearch_nphy(phy_info_t *pi, bool enable);
@@ -1148,10 +1148,10 @@ extern void wlc_nphy_deaf_mode(phy_info_t *pi, bool mode);
1148 0x72, 0x74, 0x73) 1148 0x72, 0x74, 0x73)
1149#define wlc_nphy_table_data_write(pi, w, v) wlc_phy_table_data_write((pi), (w), (v)) 1149#define wlc_nphy_table_data_write(pi, w, v) wlc_phy_table_data_write((pi), (w), (v))
1150 1150
1151extern void wlc_phy_table_read_nphy(phy_info_t *pi, uint32, uint32 l, uint32 o, 1151extern void wlc_phy_table_read_nphy(phy_info_t *pi, u32, u32 l, u32 o,
1152 uint32 w, void *d); 1152 u32 w, void *d);
1153extern void wlc_phy_table_write_nphy(phy_info_t *pi, uint32, uint32, uint32, 1153extern void wlc_phy_table_write_nphy(phy_info_t *pi, u32, u32, u32,
1154 uint32, const void *); 1154 u32, const void *);
1155 1155
1156#define PHY_IPA(pi) \ 1156#define PHY_IPA(pi) \
1157 ((pi->ipa2g_on && CHSPEC_IS2G(pi->radio_chanspec)) || \ 1157 ((pi->ipa2g_on && CHSPEC_IS2G(pi->radio_chanspec)) || \
@@ -1206,7 +1206,7 @@ extern void wlc_phy_rssi_cal_nphy(phy_info_t *pi);
1206extern int wlc_phy_aci_scan_nphy(phy_info_t *pi); 1206extern int wlc_phy_aci_scan_nphy(phy_info_t *pi);
1207extern void wlc_phy_cal_txgainctrl_nphy(phy_info_t *pi, int32 dBm_targetpower, 1207extern void wlc_phy_cal_txgainctrl_nphy(phy_info_t *pi, int32 dBm_targetpower,
1208 bool debug); 1208 bool debug);
1209extern int wlc_phy_tx_tone_nphy(phy_info_t *pi, uint32 f_kHz, u16 max_val, 1209extern int wlc_phy_tx_tone_nphy(phy_info_t *pi, u32 f_kHz, u16 max_val,
1210 u8 mode, u8, bool); 1210 u8 mode, u8, bool);
1211extern void wlc_phy_stopplayback_nphy(phy_info_t *pi); 1211extern void wlc_phy_stopplayback_nphy(phy_info_t *pi);
1212extern void wlc_phy_est_tonepwr_nphy(phy_info_t *pi, int32 *qdBm_pwrbuf, 1212extern void wlc_phy_est_tonepwr_nphy(phy_info_t *pi, int32 *qdBm_pwrbuf,
diff --git a/drivers/staging/brcm80211/phy/wlc_phy_lcn.c b/drivers/staging/brcm80211/phy/wlc_phy_lcn.c
index 1b90f79eaa5..cfaf0135321 100644
--- a/drivers/staging/brcm80211/phy/wlc_phy_lcn.c
+++ b/drivers/staging/brcm80211/phy/wlc_phy_lcn.c
@@ -180,9 +180,9 @@ typedef struct {
180} lcnphy_unsign16_struct; 180} lcnphy_unsign16_struct;
181 181
182typedef struct { 182typedef struct {
183 uint32 iq_prod; 183 u32 iq_prod;
184 uint32 i_pwr; 184 u32 i_pwr;
185 uint32 q_pwr; 185 u32 q_pwr;
186} lcnphy_iq_est_t; 186} lcnphy_iq_est_t;
187 187
188typedef struct { 188typedef struct {
@@ -423,7 +423,7 @@ lcnphy_rx_iqcomp_t lcnphy_rx_iqcomp_table_rev0[] = {
423 {216, 0, 0}, 423 {216, 0, 0},
424}; 424};
425 425
426static const uint32 lcnphy_23bitgaincode_table[] = { 426static const u32 lcnphy_23bitgaincode_table[] = {
427 0x200100, 427 0x200100,
428 0x200200, 428 0x200200,
429 0x200004, 429 0x200004,
@@ -545,7 +545,7 @@ static const s8 lcnphy_gain_index_offset_for_rssi[] = {
545}; 545};
546 546
547extern const u8 spur_tbl_rev0[]; 547extern const u8 spur_tbl_rev0[];
548extern const uint32 dot11lcnphytbl_rx_gain_info_sz_rev1; 548extern const u32 dot11lcnphytbl_rx_gain_info_sz_rev1;
549extern const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_rev1[]; 549extern const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_rev1[];
550extern const dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313_bt_epa; 550extern const dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313_bt_epa;
551extern const dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313_bt_epa_p250; 551extern const dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313_bt_epa_p250;
@@ -976,7 +976,7 @@ u16
976#define FIXED_TXPWR 78 976#define FIXED_TXPWR 78
977#define LCNPHY_TEMPSENSE(val) ((s16)((val > 255) ? (val - 512) : val)) 977#define LCNPHY_TEMPSENSE(val) ((s16)((val > 255) ? (val - 512) : val))
978 978
979static uint32 wlc_lcnphy_qdiv_roundup(uint32 divident, uint32 divisor, 979static u32 wlc_lcnphy_qdiv_roundup(u32 divident, u32 divisor,
980 u8 precision); 980 u8 precision);
981static void wlc_lcnphy_set_rx_gain_by_distribution(phy_info_t *pi, 981static void wlc_lcnphy_set_rx_gain_by_distribution(phy_info_t *pi,
982 u16 ext_lna, u16 trsw, 982 u16 ext_lna, u16 trsw,
@@ -1002,7 +1002,7 @@ static void wlc_lcnphy_afe_clk_init(phy_info_t *pi, u8 mode);
1002extern void wlc_lcnphy_tx_pwr_ctrl_init(wlc_phy_t *ppi); 1002extern void wlc_lcnphy_tx_pwr_ctrl_init(wlc_phy_t *ppi);
1003extern void wlc_lcnphy_pktengtx(wlc_phy_t *ppi, wl_pkteng_t *pkteng, 1003extern void wlc_lcnphy_pktengtx(wlc_phy_t *ppi, wl_pkteng_t *pkteng,
1004 u8 rate, struct ether_addr *sa, 1004 u8 rate, struct ether_addr *sa,
1005 uint32 wait_delay); 1005 u32 wait_delay);
1006static void wlc_lcnphy_radio_2064_channel_tune_4313(phy_info_t *pi, 1006static void wlc_lcnphy_radio_2064_channel_tune_4313(phy_info_t *pi,
1007 u8 channel); 1007 u8 channel);
1008 1008
@@ -1048,9 +1048,9 @@ void wlc_lcnphy_read_table(phy_info_t *pi, phytbl_info_t *pti)
1048} 1048}
1049 1049
1050static void 1050static void
1051wlc_lcnphy_common_read_table(phy_info_t *pi, uint32 tbl_id, 1051wlc_lcnphy_common_read_table(phy_info_t *pi, u32 tbl_id,
1052 const void *tbl_ptr, uint32 tbl_len, 1052 const void *tbl_ptr, u32 tbl_len,
1053 uint32 tbl_width, uint32 tbl_offset) 1053 u32 tbl_width, u32 tbl_offset)
1054{ 1054{
1055 phytbl_info_t tab; 1055 phytbl_info_t tab;
1056 tab.tbl_id = tbl_id; 1056 tab.tbl_id = tbl_id;
@@ -1062,9 +1062,9 @@ wlc_lcnphy_common_read_table(phy_info_t *pi, uint32 tbl_id,
1062} 1062}
1063 1063
1064static void 1064static void
1065wlc_lcnphy_common_write_table(phy_info_t *pi, uint32 tbl_id, 1065wlc_lcnphy_common_write_table(phy_info_t *pi, u32 tbl_id,
1066 const void *tbl_ptr, uint32 tbl_len, 1066 const void *tbl_ptr, u32 tbl_len,
1067 uint32 tbl_width, uint32 tbl_offset) 1067 u32 tbl_width, u32 tbl_offset)
1068{ 1068{
1069 1069
1070 phytbl_info_t tab; 1070 phytbl_info_t tab;
@@ -1076,10 +1076,10 @@ wlc_lcnphy_common_write_table(phy_info_t *pi, uint32 tbl_id,
1076 wlc_lcnphy_write_table(pi, &tab); 1076 wlc_lcnphy_write_table(pi, &tab);
1077} 1077}
1078 1078
1079static uint32 1079static u32
1080wlc_lcnphy_qdiv_roundup(uint32 dividend, uint32 divisor, u8 precision) 1080wlc_lcnphy_qdiv_roundup(u32 dividend, u32 divisor, u8 precision)
1081{ 1081{
1082 uint32 quotient, remainder, roundup, rbit; 1082 u32 quotient, remainder, roundup, rbit;
1083 1083
1084 ASSERT(divisor); 1084 ASSERT(divisor);
1085 1085
@@ -1140,7 +1140,7 @@ s8 wlc_lcnphy_get_current_tx_pwr_idx(phy_info_t *pi)
1140 return index; 1140 return index;
1141} 1141}
1142 1142
1143static uint32 wlc_lcnphy_measure_digital_power(phy_info_t *pi, u16 nsamples) 1143static u32 wlc_lcnphy_measure_digital_power(phy_info_t *pi, u16 nsamples)
1144{ 1144{
1145 lcnphy_iq_est_t iq_est = { 0, 0, 0 }; 1145 lcnphy_iq_est_t iq_est = { 0, 0, 0 };
1146 1146
@@ -1327,7 +1327,7 @@ static void wlc_lcnphy_set_bbmult(phy_info_t *pi, u8 m0)
1327 1327
1328static void wlc_lcnphy_clear_tx_power_offsets(phy_info_t *pi) 1328static void wlc_lcnphy_clear_tx_power_offsets(phy_info_t *pi)
1329{ 1329{
1330 uint32 data_buf[64]; 1330 u32 data_buf[64];
1331 phytbl_info_t tab; 1331 phytbl_info_t tab;
1332 1332
1333 bzero(data_buf, sizeof(data_buf)); 1333 bzero(data_buf, sizeof(data_buf));
@@ -1461,7 +1461,7 @@ static void wlc_lcnphy_pwrctrl_rssiparams(phy_info_t *pi)
1461static void wlc_lcnphy_tssi_setup(phy_info_t *pi) 1461static void wlc_lcnphy_tssi_setup(phy_info_t *pi)
1462{ 1462{
1463 phytbl_info_t tab; 1463 phytbl_info_t tab;
1464 uint32 rfseq, ind; 1464 u32 rfseq, ind;
1465 1465
1466 tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL; 1466 tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
1467 tab.tbl_width = 32; 1467 tab.tbl_width = 32;
@@ -1615,7 +1615,7 @@ static void wlc_lcnphy_txpower_reset_npt(phy_info_t *pi)
1615void wlc_lcnphy_txpower_recalc_target(phy_info_t *pi) 1615void wlc_lcnphy_txpower_recalc_target(phy_info_t *pi)
1616{ 1616{
1617 phytbl_info_t tab; 1617 phytbl_info_t tab;
1618 uint32 rate_table[WLC_NUM_RATES_CCK + WLC_NUM_RATES_OFDM + 1618 u32 rate_table[WLC_NUM_RATES_CCK + WLC_NUM_RATES_OFDM +
1619 WLC_NUM_RATES_MCS_1_STREAM]; 1619 WLC_NUM_RATES_MCS_1_STREAM];
1620 uint i, j; 1620 uint i, j;
1621 if (wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi)) 1621 if (wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi))
@@ -1626,7 +1626,7 @@ void wlc_lcnphy_txpower_recalc_target(phy_info_t *pi)
1626 if (i == WLC_NUM_RATES_CCK + WLC_NUM_RATES_OFDM) 1626 if (i == WLC_NUM_RATES_CCK + WLC_NUM_RATES_OFDM)
1627 j = TXP_FIRST_MCS_20_SISO; 1627 j = TXP_FIRST_MCS_20_SISO;
1628 1628
1629 rate_table[i] = (uint32) ((int32) (-pi->tx_power_offset[j])); 1629 rate_table[i] = (u32) ((int32) (-pi->tx_power_offset[j]));
1630 } 1630 }
1631 1631
1632 tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL; 1632 tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
@@ -1645,8 +1645,8 @@ void wlc_lcnphy_txpower_recalc_target(phy_info_t *pi)
1645 1645
1646static void wlc_lcnphy_set_tx_pwr_soft_ctrl(phy_info_t *pi, s8 index) 1646static void wlc_lcnphy_set_tx_pwr_soft_ctrl(phy_info_t *pi, s8 index)
1647{ 1647{
1648 uint32 cck_offset[4] = { 22, 22, 22, 22 }; 1648 u32 cck_offset[4] = { 22, 22, 22, 22 };
1649 uint32 ofdm_offset, reg_offset_cck; 1649 u32 ofdm_offset, reg_offset_cck;
1650 int i; 1650 int i;
1651 u16 index2; 1651 u16 index2;
1652 phytbl_info_t tab; 1652 phytbl_info_t tab;
@@ -1733,8 +1733,8 @@ static s8 wlc_lcnphy_tempcompensated_txpwrctrl(phy_info_t *pi)
1733 temp_diff = -temp_diff; 1733 temp_diff = -temp_diff;
1734 } 1734 }
1735 1735
1736 delta_temp = (s8) wlc_lcnphy_qdiv_roundup((uint32) (temp_diff * 192), 1736 delta_temp = (s8) wlc_lcnphy_qdiv_roundup((u32) (temp_diff * 192),
1737 (uint32) (pi_lcn-> 1737 (u32) (pi_lcn->
1738 lcnphy_tempsense_slope 1738 lcnphy_tempsense_slope
1739 * 10), 0); 1739 * 10), 0);
1740 if (neg) 1740 if (neg)
@@ -2155,7 +2155,7 @@ static void wlc_lcnphy_vbat_temp_sense_setup(phy_info_t *pi, u8 mode)
2155 u8 auxpga_vmidcourse, auxpga_vmidfine, auxpga_gain; 2155 u8 auxpga_vmidcourse, auxpga_vmidfine, auxpga_gain;
2156 u16 auxpga_vmid; 2156 u16 auxpga_vmid;
2157 phytbl_info_t tab; 2157 phytbl_info_t tab;
2158 uint32 val; 2158 u32 val;
2159 u8 save_reg007, save_reg0FF, save_reg11F, save_reg005, save_reg025, 2159 u8 save_reg007, save_reg0FF, save_reg11F, save_reg005, save_reg025,
2160 save_reg112; 2160 save_reg112;
2161 u16 values_to_save[14]; 2161 u16 values_to_save[14];
@@ -2455,7 +2455,7 @@ void wlc_lcnphy_set_tx_pwr_by_index(phy_info_t *pi, int index)
2455 phytbl_info_t tab; 2455 phytbl_info_t tab;
2456 u16 a, b; 2456 u16 a, b;
2457 u8 bb_mult; 2457 u8 bb_mult;
2458 uint32 bbmultiqcomp, txgain, locoeffs, rfpower; 2458 u32 bbmultiqcomp, txgain, locoeffs, rfpower;
2459 lcnphy_txgains_t gains; 2459 lcnphy_txgains_t gains;
2460 phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy; 2460 phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
2461 2461
@@ -2523,9 +2523,9 @@ static void wlc_lcnphy_set_trsw_override(phy_info_t *pi, bool tx, bool rx)
2523 2523
2524static void wlc_lcnphy_clear_papd_comptable(phy_info_t *pi) 2524static void wlc_lcnphy_clear_papd_comptable(phy_info_t *pi)
2525{ 2525{
2526 uint32 j; 2526 u32 j;
2527 phytbl_info_t tab; 2527 phytbl_info_t tab;
2528 uint32 temp_offset[128]; 2528 u32 temp_offset[128];
2529 tab.tbl_ptr = temp_offset; 2529 tab.tbl_ptr = temp_offset;
2530 tab.tbl_len = 128; 2530 tab.tbl_len = 128;
2531 tab.tbl_id = LCNPHY_TBL_ID_PAPDCOMPDELTATBL; 2531 tab.tbl_id = LCNPHY_TBL_ID_PAPDCOMPDELTATBL;
@@ -2734,10 +2734,10 @@ wlc_lcnphy_start_tx_tone(phy_info_t *pi, int32 f_kHz, u16 max_val,
2734{ 2734{
2735 u8 phy_bw; 2735 u8 phy_bw;
2736 u16 num_samps, t, k; 2736 u16 num_samps, t, k;
2737 uint32 bw; 2737 u32 bw;
2738 fixed theta = 0, rot = 0; 2738 fixed theta = 0, rot = 0;
2739 cint32 tone_samp; 2739 cint32 tone_samp;
2740 uint32 data_buf[64]; 2740 u32 data_buf[64];
2741 u16 i_samp, q_samp; 2741 u16 i_samp, q_samp;
2742 phytbl_info_t tab; 2742 phytbl_info_t tab;
2743 phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy; 2743 phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
@@ -2761,7 +2761,7 @@ wlc_lcnphy_start_tx_tone(phy_info_t *pi, int32 f_kHz, u16 max_val,
2761 num_samps = bw / ABS(f_kHz); 2761 num_samps = bw / ABS(f_kHz);
2762 ASSERT(num_samps <= ARRAYSIZE(data_buf)); 2762 ASSERT(num_samps <= ARRAYSIZE(data_buf));
2763 k++; 2763 k++;
2764 } while ((num_samps * (uint32) (ABS(f_kHz))) != bw); 2764 } while ((num_samps * (u32) (ABS(f_kHz))) != bw);
2765 } else 2765 } else
2766 num_samps = 2; 2766 num_samps = 2;
2767 2767
@@ -2868,7 +2868,7 @@ static void wlc_lcnphy_txpwrtbl_iqlo_cal(phy_info_t *pi)
2868 u8 save_bb_mult; 2868 u8 save_bb_mult;
2869 u16 a, b, didq, save_pa_gain = 0; 2869 u16 a, b, didq, save_pa_gain = 0;
2870 uint idx, SAVE_txpwrindex = 0xFF; 2870 uint idx, SAVE_txpwrindex = 0xFF;
2871 uint32 val; 2871 u32 val;
2872 u16 SAVE_txpwrctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi); 2872 u16 SAVE_txpwrctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi);
2873 phytbl_info_t tab; 2873 phytbl_info_t tab;
2874 u8 ei0, eq0, fi0, fq0; 2874 u8 ei0, eq0, fi0, fq0;
@@ -2949,7 +2949,7 @@ static void wlc_lcnphy_txpwrtbl_iqlo_cal(phy_info_t *pi)
2949 2949
2950 wlc_lcnphy_read_table(pi, &tab); 2950 wlc_lcnphy_read_table(pi, &tab);
2951 val = (val & 0xfff00000) | 2951 val = (val & 0xfff00000) |
2952 ((uint32) (a & 0x3FF) << 10) | (b & 0x3ff); 2952 ((u32) (a & 0x3FF) << 10) | (b & 0x3ff);
2953 wlc_lcnphy_write_table(pi, &tab); 2953 wlc_lcnphy_write_table(pi, &tab);
2954 2954
2955 val = didq; 2955 val = didq;
@@ -3172,12 +3172,12 @@ wlc_lcnphy_rx_iq_est(phy_info_t *pi,
3172 wait_count++; 3172 wait_count++;
3173 } 3173 }
3174 3174
3175 iq_est->iq_prod = ((uint32) read_phy_reg(pi, 0x483) << 16) | 3175 iq_est->iq_prod = ((u32) read_phy_reg(pi, 0x483) << 16) |
3176 (uint32) read_phy_reg(pi, 0x484); 3176 (u32) read_phy_reg(pi, 0x484);
3177 iq_est->i_pwr = ((uint32) read_phy_reg(pi, 0x485) << 16) | 3177 iq_est->i_pwr = ((u32) read_phy_reg(pi, 0x485) << 16) |
3178 (uint32) read_phy_reg(pi, 0x486); 3178 (u32) read_phy_reg(pi, 0x486);
3179 iq_est->q_pwr = ((uint32) read_phy_reg(pi, 0x487) << 16) | 3179 iq_est->q_pwr = ((u32) read_phy_reg(pi, 0x487) << 16) |
3180 (uint32) read_phy_reg(pi, 0x488); 3180 (u32) read_phy_reg(pi, 0x488);
3181 3181
3182 cleanup: 3182 cleanup:
3183 mod_phy_reg(pi, 0x410, (0x1 << 3), (1) << 3); 3183 mod_phy_reg(pi, 0x410, (0x1 << 3), (1) << 3);
@@ -3196,7 +3196,7 @@ static bool wlc_lcnphy_calc_rx_iq_comp(phy_info_t *pi, u16 num_samps)
3196 int32 a, b, temp; 3196 int32 a, b, temp;
3197 s16 iq_nbits, qq_nbits, arsh, brsh; 3197 s16 iq_nbits, qq_nbits, arsh, brsh;
3198 int32 iq; 3198 int32 iq;
3199 uint32 ii, qq; 3199 u32 ii, qq;
3200 phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy; 3200 phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
3201 3201
3202 a0_new = ((read_phy_reg(pi, 0x645) & (0x3ff << 0)) >> 0); 3202 a0_new = ((read_phy_reg(pi, 0x645) & (0x3ff << 0)) >> 0);
@@ -3254,7 +3254,7 @@ static bool wlc_lcnphy_calc_rx_iq_comp(phy_info_t *pi, u16 num_samps)
3254 } 3254 }
3255 b /= temp; 3255 b /= temp;
3256 b -= a * a; 3256 b -= a * a;
3257 b = (int32) wlc_phy_sqrt_int((uint32) b); 3257 b = (int32) wlc_phy_sqrt_int((u32) b);
3258 b -= (1 << 10); 3258 b -= (1 << 10);
3259 a0_new = (u16) (a & 0x3ff); 3259 a0_new = (u16) (a & 0x3ff);
3260 b0_new = (u16) (b & 0x3ff); 3260 b0_new = (u16) (b & 0x3ff);
@@ -3286,7 +3286,7 @@ wlc_lcnphy_rx_iq_cal(phy_info_t *pi, const lcnphy_rx_iqcomp_t *iqcomp,
3286 rfoverride3_old, rfoverride3val_old, rfoverride4_old, 3286 rfoverride3_old, rfoverride3val_old, rfoverride4_old,
3287 rfoverride4val_old, afectrlovr_old, afectrlovrval_old; 3287 rfoverride4val_old, afectrlovr_old, afectrlovrval_old;
3288 int tia_gain; 3288 int tia_gain;
3289 uint32 received_power, rx_pwr_threshold; 3289 u32 received_power, rx_pwr_threshold;
3290 u16 old_sslpnCalibClkEnCtrl, old_sslpnRxFeClkEnCtrl; 3290 u16 old_sslpnCalibClkEnCtrl, old_sslpnRxFeClkEnCtrl;
3291 u16 values_to_save[11]; 3291 u16 values_to_save[11];
3292 s16 *ptr; 3292 s16 *ptr;
@@ -3671,7 +3671,7 @@ static void wlc_lcnphy_set_chanspec_tweaks(phy_info_t *pi, chanspec_t chanspec)
3671 3671
3672void 3672void
3673wlc_lcnphy_pktengtx(wlc_phy_t *ppi, wl_pkteng_t *pkteng, u8 rate, 3673wlc_lcnphy_pktengtx(wlc_phy_t *ppi, wl_pkteng_t *pkteng, u8 rate,
3674 struct ether_addr *sa, uint32 wait_delay) 3674 struct ether_addr *sa, u32 wait_delay)
3675{ 3675{
3676} 3676}
3677 3677
@@ -3854,7 +3854,7 @@ static void
3854wlc_lcnphy_samp_cap(phy_info_t *pi, int clip_detect_algo, u16 thresh, 3854wlc_lcnphy_samp_cap(phy_info_t *pi, int clip_detect_algo, u16 thresh,
3855 s16 *ptr, int mode) 3855 s16 *ptr, int mode)
3856{ 3856{
3857 uint32 curval1, curval2, stpptr, curptr, strptr, val; 3857 u32 curval1, curval2, stpptr, curptr, strptr, val;
3858 u16 sslpnCalibClkEnCtrl, timer; 3858 u16 sslpnCalibClkEnCtrl, timer;
3859 u16 old_sslpnCalibClkEnCtrl; 3859 u16 old_sslpnCalibClkEnCtrl;
3860 s16 imag, real; 3860 s16 imag, real;
@@ -3887,7 +3887,7 @@ wlc_lcnphy_samp_cap(phy_info_t *pi, int clip_detect_algo, u16 thresh,
3887 write_phy_reg(pi, 0x580, 0x4501); 3887 write_phy_reg(pi, 0x580, 0x4501);
3888 3888
3889 sslpnCalibClkEnCtrl = read_phy_reg(pi, 0x6da); 3889 sslpnCalibClkEnCtrl = read_phy_reg(pi, 0x6da);
3890 write_phy_reg(pi, 0x6da, (uint32) (sslpnCalibClkEnCtrl | 0x2008)); 3890 write_phy_reg(pi, 0x6da, (u32) (sslpnCalibClkEnCtrl | 0x2008));
3891 stpptr = R_REG(pi->sh->osh, &pi->regs->smpl_clct_stpptr); 3891 stpptr = R_REG(pi->sh->osh, &pi->regs->smpl_clct_stpptr);
3892 curptr = R_REG(pi->sh->osh, &pi->regs->smpl_clct_curptr); 3892 curptr = R_REG(pi->sh->osh, &pi->regs->smpl_clct_curptr);
3893 do { 3893 do {
@@ -4039,7 +4039,7 @@ wlc_lcnphy_a1(phy_info_t *pi, int cal_type, int num_levels, int step_size_lg2)
4039 s16 phy_c10, phy_c11, phy_c12, phy_c13, phy_c14, phy_c15, phy_c16; 4039 s16 phy_c10, phy_c11, phy_c12, phy_c13, phy_c14, phy_c15, phy_c16;
4040 s16 *ptr, phy_c17; 4040 s16 *ptr, phy_c17;
4041 int32 phy_c18, phy_c19; 4041 int32 phy_c18, phy_c19;
4042 uint32 phy_c20, phy_c21; 4042 u32 phy_c20, phy_c21;
4043 bool phy_c22, phy_c23, phy_c24, phy_c25; 4043 bool phy_c22, phy_c23, phy_c24, phy_c25;
4044 u16 phy_c26, phy_c27; 4044 u16 phy_c26, phy_c27;
4045 u16 phy_c28, phy_c29, phy_c30; 4045 u16 phy_c28, phy_c29, phy_c30;
@@ -4244,9 +4244,9 @@ static void
4244WLBANDINITFN(wlc_lcnphy_load_tx_gain_table) (phy_info_t *pi, 4244WLBANDINITFN(wlc_lcnphy_load_tx_gain_table) (phy_info_t *pi,
4245 const lcnphy_tx_gain_tbl_entry * 4245 const lcnphy_tx_gain_tbl_entry *
4246 gain_table) { 4246 gain_table) {
4247 uint32 j; 4247 u32 j;
4248 phytbl_info_t tab; 4248 phytbl_info_t tab;
4249 uint32 val; 4249 u32 val;
4250 u16 pa_gain; 4250 u16 pa_gain;
4251 u16 gm_gain; 4251 u16 gm_gain;
4252 4252
@@ -4264,7 +4264,7 @@ WLBANDINITFN(wlc_lcnphy_load_tx_gain_table) (phy_info_t *pi,
4264 4264
4265 for (j = 0; j < 128; j++) { 4265 for (j = 0; j < 128; j++) {
4266 gm_gain = gain_table[j].gm; 4266 gm_gain = gain_table[j].gm;
4267 val = (((uint32) pa_gain << 24) | 4267 val = (((u32) pa_gain << 24) |
4268 (gain_table[j].pad << 16) | 4268 (gain_table[j].pad << 16) |
4269 (gain_table[j].pga << 8) | gm_gain); 4269 (gain_table[j].pga << 8) | gm_gain);
4270 4270
@@ -4280,7 +4280,7 @@ WLBANDINITFN(wlc_lcnphy_load_tx_gain_table) (phy_info_t *pi,
4280static void wlc_lcnphy_load_rfpower(phy_info_t *pi) 4280static void wlc_lcnphy_load_rfpower(phy_info_t *pi)
4281{ 4281{
4282 phytbl_info_t tab; 4282 phytbl_info_t tab;
4283 uint32 val, bbmult, rfgain; 4283 u32 val, bbmult, rfgain;
4284 u8 index; 4284 u8 index;
4285 u8 scale_factor = 1; 4285 u8 scale_factor = 1;
4286 s16 temp, temp1, temp2, qQ, qQ1, qQ2, shift; 4286 s16 temp, temp1, temp2, qQ, qQ1, qQ2, shift;
@@ -4331,7 +4331,7 @@ static void WLBANDINITFN(wlc_lcnphy_tbl_init) (phy_info_t *pi)
4331 uint idx; 4331 uint idx;
4332 u8 phybw40; 4332 u8 phybw40;
4333 phytbl_info_t tab; 4333 phytbl_info_t tab;
4334 uint32 val; 4334 u32 val;
4335 4335
4336 phybw40 = CHSPEC_IS40(pi->radio_chanspec); 4336 phybw40 = CHSPEC_IS40(pi->radio_chanspec);
4337 4337
@@ -4481,7 +4481,7 @@ static void wlc_lcnphy_agc_temp_init(phy_info_t *pi)
4481{ 4481{
4482 s16 temp; 4482 s16 temp;
4483 phytbl_info_t tab; 4483 phytbl_info_t tab;
4484 uint32 tableBuffer[2]; 4484 u32 tableBuffer[2];
4485 phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy; 4485 phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
4486 4486
4487 if (NORADIO_ENAB(pi->pubpi)) 4487 if (NORADIO_ENAB(pi->pubpi))
@@ -4605,7 +4605,7 @@ static void WLBANDINITFN(wlc_lcnphy_baseband_init) (phy_info_t *pi)
4605 4605
4606static void WLBANDINITFN(wlc_radio_2064_init) (phy_info_t *pi) 4606static void WLBANDINITFN(wlc_radio_2064_init) (phy_info_t *pi)
4607{ 4607{
4608 uint32 i; 4608 u32 i;
4609 lcnphy_radio_regs_t *lcnphyregs = NULL; 4609 lcnphy_radio_regs_t *lcnphyregs = NULL;
4610 4610
4611 lcnphyregs = lcnphy_radio_regs_2064; 4611 lcnphyregs = lcnphy_radio_regs_2064;
@@ -4734,7 +4734,7 @@ static bool BCMATTACHFN(wlc_phy_txpwr_srom_read_lcnphy) (phy_info_t *pi)
4734 4734
4735 if (CHSPEC_IS2G(pi->radio_chanspec)) { 4735 if (CHSPEC_IS2G(pi->radio_chanspec)) {
4736 u16 cckpo = 0; 4736 u16 cckpo = 0;
4737 uint32 offset_ofdm, offset_mcs; 4737 u32 offset_ofdm, offset_mcs;
4738 4738
4739 pi_lcn->lcnphy_tr_isolation_mid = 4739 pi_lcn->lcnphy_tr_isolation_mid =
4740 (u8) PHY_GETINTVAR(pi, "triso2g"); 4740 (u8) PHY_GETINTVAR(pi, "triso2g");
@@ -4781,7 +4781,7 @@ static bool BCMATTACHFN(wlc_phy_txpwr_srom_read_lcnphy) (phy_info_t *pi)
4781 cckpo >>= 4; 4781 cckpo >>= 4;
4782 } 4782 }
4783 4783
4784 offset_ofdm = (uint32) PHY_GETINTVAR(pi, "ofdm2gpo"); 4784 offset_ofdm = (u32) PHY_GETINTVAR(pi, "ofdm2gpo");
4785 for (i = TXP_FIRST_OFDM; i <= TXP_LAST_OFDM; i++) { 4785 for (i = TXP_FIRST_OFDM; i <= TXP_LAST_OFDM; i++) {
4786 pi->tx_srom_max_rate_2g[i] = max_pwr_chan - 4786 pi->tx_srom_max_rate_2g[i] = max_pwr_chan -
4787 ((offset_ofdm & 0xf) * 2); 4787 ((offset_ofdm & 0xf) * 2);
@@ -4796,7 +4796,7 @@ static bool BCMATTACHFN(wlc_phy_txpwr_srom_read_lcnphy) (phy_info_t *pi)
4796 pi->tx_srom_max_rate_2g[i] = txpwr; 4796 pi->tx_srom_max_rate_2g[i] = txpwr;
4797 } 4797 }
4798 4798
4799 offset_ofdm = (uint32) PHY_GETINTVAR(pi, "ofdm2gpo"); 4799 offset_ofdm = (u32) PHY_GETINTVAR(pi, "ofdm2gpo");
4800 4800
4801 for (i = TXP_FIRST_OFDM; i <= TXP_LAST_OFDM; i++) { 4801 for (i = TXP_FIRST_OFDM; i <= TXP_LAST_OFDM; i++) {
4802 pi->tx_srom_max_rate_2g[i] = txpwr - 4802 pi->tx_srom_max_rate_2g[i] = txpwr -
@@ -4872,7 +4872,7 @@ wlc_lcnphy_radio_2064_channel_tune_4313(phy_info_t *pi, u8 channel)
4872 u8 pll_pwrup, pll_pwrup_ovr; 4872 u8 pll_pwrup, pll_pwrup_ovr;
4873 fixed qFxtal, qFref, qFvco, qFcal; 4873 fixed qFxtal, qFref, qFvco, qFcal;
4874 u8 d15, d16, f16, e44, e45; 4874 u8 d15, d16, f16, e44, e45;
4875 uint32 div_int, div_frac, fvco3, fpfd, fref3, fcal_div; 4875 u32 div_int, div_frac, fvco3, fpfd, fref3, fcal_div;
4876 u16 loop_bw, d30, setCount; 4876 u16 loop_bw, d30, setCount;
4877 if (NORADIO_ENAB(pi->pubpi)) 4877 if (NORADIO_ENAB(pi->pubpi))
4878 return; 4878 return;
@@ -5111,11 +5111,11 @@ bool wlc_phy_attach_lcnphy(phy_info_t *pi)
5111 return TRUE; 5111 return TRUE;
5112} 5112}
5113 5113
5114static void wlc_lcnphy_set_rx_gain(phy_info_t *pi, uint32 gain) 5114static void wlc_lcnphy_set_rx_gain(phy_info_t *pi, u32 gain)
5115{ 5115{
5116 u16 trsw, ext_lna, lna1, lna2, tia, biq0, biq1, gain0_15, gain16_19; 5116 u16 trsw, ext_lna, lna1, lna2, tia, biq0, biq1, gain0_15, gain16_19;
5117 5117
5118 trsw = (gain & ((uint32) 1 << 28)) ? 0 : 1; 5118 trsw = (gain & ((u32) 1 << 28)) ? 0 : 1;
5119 ext_lna = (u16) (gain >> 29) & 0x01; 5119 ext_lna = (u16) (gain >> 29) & 0x01;
5120 lna1 = (u16) (gain >> 0) & 0x0f; 5120 lna1 = (u16) (gain >> 0) & 0x0f;
5121 lna2 = (u16) (gain >> 4) & 0x0f; 5121 lna2 = (u16) (gain >> 4) & 0x0f;
@@ -5141,11 +5141,11 @@ static void wlc_lcnphy_set_rx_gain(phy_info_t *pi, uint32 gain)
5141 wlc_lcnphy_rx_gain_override_enable(pi, TRUE); 5141 wlc_lcnphy_rx_gain_override_enable(pi, TRUE);
5142} 5142}
5143 5143
5144static uint32 wlc_lcnphy_get_receive_power(phy_info_t *pi, int32 *gain_index) 5144static u32 wlc_lcnphy_get_receive_power(phy_info_t *pi, int32 *gain_index)
5145{ 5145{
5146 uint32 received_power = 0; 5146 u32 received_power = 0;
5147 int32 max_index = 0; 5147 int32 max_index = 0;
5148 uint32 gain_code = 0; 5148 u32 gain_code = 0;
5149 phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy; 5149 phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
5150 5150
5151 max_index = 36; 5151 max_index = 36;
@@ -5194,8 +5194,8 @@ int32 wlc_lcnphy_rx_signal_power(phy_info_t *pi, int32 gain_index)
5194 nominal_power_db = read_phy_reg(pi, 0x425) >> 8; 5194 nominal_power_db = read_phy_reg(pi, 0x425) >> 8;
5195 5195
5196 { 5196 {
5197 uint32 power = (received_power * 16); 5197 u32 power = (received_power * 16);
5198 uint32 msb1, msb2, val1, val2, diff1, diff2; 5198 u32 msb1, msb2, val1, val2, diff1, diff2;
5199 msb1 = ffs(power) - 1; 5199 msb1 = ffs(power) - 1;
5200 msb2 = msb1 + 1; 5200 msb2 = msb1 + 1;
5201 val1 = 1 << msb1; 5201 val1 = 1 << msb1;
diff --git a/drivers/staging/brcm80211/phy/wlc_phy_lcn.h b/drivers/staging/brcm80211/phy/wlc_phy_lcn.h
index 83351d8d4bd..2b3bbdb71d0 100644
--- a/drivers/staging/brcm80211/phy/wlc_phy_lcn.h
+++ b/drivers/staging/brcm80211/phy/wlc_phy_lcn.h
@@ -27,7 +27,7 @@ struct phy_info_lcnphy {
27 bool lcnphy_recal; 27 bool lcnphy_recal;
28 28
29 u8 lcnphy_rc_cap; 29 u8 lcnphy_rc_cap;
30 uint32 lcnphy_mcs20_po; 30 u32 lcnphy_mcs20_po;
31 31
32 u8 lcnphy_tr_isolation_mid; 32 u8 lcnphy_tr_isolation_mid;
33 u8 lcnphy_tr_isolation_low; 33 u8 lcnphy_tr_isolation_low;
@@ -69,17 +69,17 @@ struct phy_info_lcnphy {
69 s8 lcnphy_tx_power_idx_override; 69 s8 lcnphy_tx_power_idx_override;
70 u16 lcnphy_noise_samples; 70 u16 lcnphy_noise_samples;
71 71
72 uint32 lcnphy_papdRxGnIdx; 72 u32 lcnphy_papdRxGnIdx;
73 uint32 lcnphy_papd_rxGnCtrl_init; 73 u32 lcnphy_papd_rxGnCtrl_init;
74 74
75 uint32 lcnphy_gain_idx_14_lowword; 75 u32 lcnphy_gain_idx_14_lowword;
76 uint32 lcnphy_gain_idx_14_hiword; 76 u32 lcnphy_gain_idx_14_hiword;
77 uint32 lcnphy_gain_idx_27_lowword; 77 u32 lcnphy_gain_idx_27_lowword;
78 uint32 lcnphy_gain_idx_27_hiword; 78 u32 lcnphy_gain_idx_27_hiword;
79 s16 lcnphy_ofdmgainidxtableoffset; 79 s16 lcnphy_ofdmgainidxtableoffset;
80 s16 lcnphy_dsssgainidxtableoffset; 80 s16 lcnphy_dsssgainidxtableoffset;
81 uint32 lcnphy_tr_R_gain_val; 81 u32 lcnphy_tr_R_gain_val;
82 uint32 lcnphy_tr_T_gain_val; 82 u32 lcnphy_tr_T_gain_val;
83 s8 lcnphy_input_pwr_offset_db; 83 s8 lcnphy_input_pwr_offset_db;
84 u16 lcnphy_Med_Low_Gain_db; 84 u16 lcnphy_Med_Low_Gain_db;
85 u16 lcnphy_Very_Low_Gain_db; 85 u16 lcnphy_Very_Low_Gain_db;
diff --git a/drivers/staging/brcm80211/phy/wlc_phy_n.c b/drivers/staging/brcm80211/phy/wlc_phy_n.c
index a335db31540..79322056b9c 100644
--- a/drivers/staging/brcm80211/phy/wlc_phy_n.c
+++ b/drivers/staging/brcm80211/phy/wlc_phy_n.c
@@ -13309,7 +13309,7 @@ static const u16 tbl_iqcal_gainparams_nphy[2][NPHY_IQCAL_NUMGAINS][8] = {
13309 } 13309 }
13310}; 13310};
13311 13311
13312static const uint32 nphy_tpc_txgain[] = { 13312static const u32 nphy_tpc_txgain[] = {
13313 0x03cc2b44, 0x03cc2b42, 0x03cc2a44, 0x03cc2a42, 13313 0x03cc2b44, 0x03cc2b42, 0x03cc2a44, 0x03cc2a42,
13314 0x03cc2944, 0x03c82b44, 0x03c82b42, 0x03c82a44, 13314 0x03cc2944, 0x03c82b44, 0x03c82b42, 0x03c82a44,
13315 0x03c82a42, 0x03c82944, 0x03c82942, 0x03c82844, 13315 0x03c82a42, 0x03c82944, 0x03c82942, 0x03c82844,
@@ -13363,7 +13363,7 @@ static const u16 nphy_tpc_loscale[] = {
13363 858, 908, 908, 962, 962, 1019, 1019, 256 13363 858, 908, 908, 962, 962, 1019, 1019, 256
13364}; 13364};
13365 13365
13366static uint32 nphy_tpc_txgain_ipa[] = { 13366static u32 nphy_tpc_txgain_ipa[] = {
13367 0x5ff7002d, 0x5ff7002b, 0x5ff7002a, 0x5ff70029, 13367 0x5ff7002d, 0x5ff7002b, 0x5ff7002a, 0x5ff70029,
13368 0x5ff70028, 0x5ff70027, 0x5ff70026, 0x5ff70025, 13368 0x5ff70028, 0x5ff70027, 0x5ff70026, 0x5ff70025,
13369 0x5ef7002d, 0x5ef7002b, 0x5ef7002a, 0x5ef70029, 13369 0x5ef7002d, 0x5ef7002b, 0x5ef7002a, 0x5ef70029,
@@ -13398,7 +13398,7 @@ static uint32 nphy_tpc_txgain_ipa[] = {
13398 0x50f70028, 0x50f70027, 0x50f70026, 0x50f70025 13398 0x50f70028, 0x50f70027, 0x50f70026, 0x50f70025
13399}; 13399};
13400 13400
13401static uint32 nphy_tpc_txgain_ipa_rev5[] = { 13401static u32 nphy_tpc_txgain_ipa_rev5[] = {
13402 0x1ff7002d, 0x1ff7002b, 0x1ff7002a, 0x1ff70029, 13402 0x1ff7002d, 0x1ff7002b, 0x1ff7002a, 0x1ff70029,
13403 0x1ff70028, 0x1ff70027, 0x1ff70026, 0x1ff70025, 13403 0x1ff70028, 0x1ff70027, 0x1ff70026, 0x1ff70025,
13404 0x1ef7002d, 0x1ef7002b, 0x1ef7002a, 0x1ef70029, 13404 0x1ef7002d, 0x1ef7002b, 0x1ef7002a, 0x1ef70029,
@@ -13433,7 +13433,7 @@ static uint32 nphy_tpc_txgain_ipa_rev5[] = {
13433 0x10f70028, 0x10f70027, 0x10f70026, 0x10f70025 13433 0x10f70028, 0x10f70027, 0x10f70026, 0x10f70025
13434}; 13434};
13435 13435
13436static uint32 nphy_tpc_txgain_ipa_rev6[] = { 13436static u32 nphy_tpc_txgain_ipa_rev6[] = {
13437 0x0ff7002d, 0x0ff7002b, 0x0ff7002a, 0x0ff70029, 13437 0x0ff7002d, 0x0ff7002b, 0x0ff7002a, 0x0ff70029,
13438 0x0ff70028, 0x0ff70027, 0x0ff70026, 0x0ff70025, 13438 0x0ff70028, 0x0ff70027, 0x0ff70026, 0x0ff70025,
13439 0x0ef7002d, 0x0ef7002b, 0x0ef7002a, 0x0ef70029, 13439 0x0ef7002d, 0x0ef7002b, 0x0ef7002a, 0x0ef70029,
@@ -13468,7 +13468,7 @@ static uint32 nphy_tpc_txgain_ipa_rev6[] = {
13468 0x00f70028, 0x00f70027, 0x00f70026, 0x00f70025 13468 0x00f70028, 0x00f70027, 0x00f70026, 0x00f70025
13469}; 13469};
13470 13470
13471static uint32 nphy_tpc_txgain_ipa_2g_2057rev3[] = { 13471static u32 nphy_tpc_txgain_ipa_2g_2057rev3[] = {
13472 0x70ff0040, 0x70f7003e, 0x70ef003b, 0x70e70039, 13472 0x70ff0040, 0x70f7003e, 0x70ef003b, 0x70e70039,
13473 0x70df0037, 0x70d70036, 0x70cf0033, 0x70c70032, 13473 0x70df0037, 0x70d70036, 0x70cf0033, 0x70c70032,
13474 0x70bf0031, 0x70b7002f, 0x70af002e, 0x70a7002d, 13474 0x70bf0031, 0x70b7002f, 0x70af002e, 0x70a7002d,
@@ -13503,7 +13503,7 @@ static uint32 nphy_tpc_txgain_ipa_2g_2057rev3[] = {
13503 0x700f0001, 0x700f0001, 0x700f0001, 0x700f0001 13503 0x700f0001, 0x700f0001, 0x700f0001, 0x700f0001
13504}; 13504};
13505 13505
13506static uint32 nphy_tpc_txgain_ipa_2g_2057rev4n6[] = { 13506static u32 nphy_tpc_txgain_ipa_2g_2057rev4n6[] = {
13507 0xf0ff0040, 0xf0f7003e, 0xf0ef003b, 0xf0e70039, 13507 0xf0ff0040, 0xf0f7003e, 0xf0ef003b, 0xf0e70039,
13508 0xf0df0037, 0xf0d70036, 0xf0cf0033, 0xf0c70032, 13508 0xf0df0037, 0xf0d70036, 0xf0cf0033, 0xf0c70032,
13509 0xf0bf0031, 0xf0b7002f, 0xf0af002e, 0xf0a7002d, 13509 0xf0bf0031, 0xf0b7002f, 0xf0af002e, 0xf0a7002d,
@@ -13538,7 +13538,7 @@ static uint32 nphy_tpc_txgain_ipa_2g_2057rev4n6[] = {
13538 0xf00f0001, 0xf00f0001, 0xf00f0001, 0xf00f0001 13538 0xf00f0001, 0xf00f0001, 0xf00f0001, 0xf00f0001
13539}; 13539};
13540 13540
13541static uint32 nphy_tpc_txgain_ipa_2g_2057rev5[] = { 13541static u32 nphy_tpc_txgain_ipa_2g_2057rev5[] = {
13542 0x30ff0031, 0x30e70031, 0x30e7002e, 0x30cf002e, 13542 0x30ff0031, 0x30e70031, 0x30e7002e, 0x30cf002e,
13543 0x30bf002e, 0x30af002e, 0x309f002f, 0x307f0033, 13543 0x30bf002e, 0x30af002e, 0x309f002f, 0x307f0033,
13544 0x307f0031, 0x307f002e, 0x3077002e, 0x306f002e, 13544 0x307f0031, 0x307f002e, 0x3077002e, 0x306f002e,
@@ -13573,7 +13573,7 @@ static uint32 nphy_tpc_txgain_ipa_2g_2057rev5[] = {
13573 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715 13573 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715
13574}; 13574};
13575 13575
13576static uint32 nphy_tpc_txgain_ipa_2g_2057rev7[] = { 13576static u32 nphy_tpc_txgain_ipa_2g_2057rev7[] = {
13577 0x30ff0031, 0x30e70031, 0x30e7002e, 0x30cf002e, 13577 0x30ff0031, 0x30e70031, 0x30e7002e, 0x30cf002e,
13578 0x30bf002e, 0x30af002e, 0x309f002f, 0x307f0033, 13578 0x30bf002e, 0x30af002e, 0x309f002f, 0x307f0033,
13579 0x307f0031, 0x307f002e, 0x3077002e, 0x306f002e, 13579 0x307f0031, 0x307f002e, 0x3077002e, 0x306f002e,
@@ -13608,7 +13608,7 @@ static uint32 nphy_tpc_txgain_ipa_2g_2057rev7[] = {
13608 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715 13608 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715
13609}; 13609};
13610 13610
13611static uint32 nphy_tpc_txgain_ipa_5g[] = { 13611static u32 nphy_tpc_txgain_ipa_5g[] = {
13612 0x7ff70035, 0x7ff70033, 0x7ff70032, 0x7ff70031, 13612 0x7ff70035, 0x7ff70033, 0x7ff70032, 0x7ff70031,
13613 0x7ff7002f, 0x7ff7002e, 0x7ff7002d, 0x7ff7002b, 13613 0x7ff7002f, 0x7ff7002e, 0x7ff7002d, 0x7ff7002b,
13614 0x7ff7002a, 0x7ff70029, 0x7ff70028, 0x7ff70027, 13614 0x7ff7002a, 0x7ff70029, 0x7ff70028, 0x7ff70027,
@@ -13643,7 +13643,7 @@ static uint32 nphy_tpc_txgain_ipa_5g[] = {
13643 0x70f70021, 0x70f70020, 0x70f70020, 0x70f7001f 13643 0x70f70021, 0x70f70020, 0x70f70020, 0x70f7001f
13644}; 13644};
13645 13645
13646static uint32 nphy_tpc_txgain_ipa_5g_2057[] = { 13646static u32 nphy_tpc_txgain_ipa_5g_2057[] = {
13647 0x7f7f0044, 0x7f7f0040, 0x7f7f003c, 0x7f7f0039, 13647 0x7f7f0044, 0x7f7f0040, 0x7f7f003c, 0x7f7f0039,
13648 0x7f7f0036, 0x7e7f003c, 0x7e7f0038, 0x7e7f0035, 13648 0x7f7f0036, 0x7e7f003c, 0x7e7f0038, 0x7e7f0035,
13649 0x7d7f003c, 0x7d7f0039, 0x7d7f0036, 0x7d7f0033, 13649 0x7d7f003c, 0x7d7f0039, 0x7d7f0036, 0x7d7f0033,
@@ -13678,7 +13678,7 @@ static uint32 nphy_tpc_txgain_ipa_5g_2057[] = {
13678 0x707f0001, 0x707f0001, 0x707f0001, 0x707f0001 13678 0x707f0001, 0x707f0001, 0x707f0001, 0x707f0001
13679}; 13679};
13680 13680
13681static uint32 nphy_tpc_txgain_ipa_5g_2057rev7[] = { 13681static u32 nphy_tpc_txgain_ipa_5g_2057rev7[] = {
13682 0x6f7f0031, 0x6f7f002e, 0x6f7f002c, 0x6f7f002a, 13682 0x6f7f0031, 0x6f7f002e, 0x6f7f002c, 0x6f7f002a,
13683 0x6f7f0027, 0x6e7f002e, 0x6e7f002c, 0x6e7f002a, 13683 0x6f7f0027, 0x6e7f002e, 0x6e7f002c, 0x6e7f002a,
13684 0x6d7f0030, 0x6d7f002d, 0x6d7f002a, 0x6d7f0028, 13684 0x6d7f0030, 0x6d7f002d, 0x6d7f002a, 0x6d7f0028,
@@ -13775,7 +13775,7 @@ static u8 pga_all_gain_codes_2057[] = {
13775 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 13775 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
13776}; 13776};
13777 13777
13778static uint32 nphy_papd_scaltbl[] = { 13778static u32 nphy_papd_scaltbl[] = {
13779 0x0ae2002f, 0x0a3b0032, 0x09a70035, 0x09220038, 13779 0x0ae2002f, 0x0a3b0032, 0x09a70035, 0x09220038,
13780 0x0887003c, 0x081f003f, 0x07a20043, 0x07340047, 13780 0x0887003c, 0x081f003f, 0x07a20043, 0x07340047,
13781 0x06d2004b, 0x067a004f, 0x06170054, 0x05bf0059, 13781 0x06d2004b, 0x067a004f, 0x06170054, 0x05bf0059,
@@ -13794,7 +13794,7 @@ static uint32 nphy_papd_scaltbl[] = {
13794 0x005805d7, 0x0053062f, 0x004e068d, 0x004a06f1 13794 0x005805d7, 0x0053062f, 0x004e068d, 0x004a06f1
13795}; 13795};
13796 13796
13797static uint32 nphy_tpc_txgain_rev3[] = { 13797static u32 nphy_tpc_txgain_rev3[] = {
13798 0x1f410044, 0x1f410042, 0x1f410040, 0x1f41003e, 13798 0x1f410044, 0x1f410042, 0x1f410040, 0x1f41003e,
13799 0x1f41003c, 0x1f41003b, 0x1f410039, 0x1f410037, 13799 0x1f41003c, 0x1f41003b, 0x1f410039, 0x1f410037,
13800 0x1e410044, 0x1e410042, 0x1e410040, 0x1e41003e, 13800 0x1e410044, 0x1e410042, 0x1e410040, 0x1e41003e,
@@ -13829,7 +13829,7 @@ static uint32 nphy_tpc_txgain_rev3[] = {
13829 0x1041003c, 0x1041003b, 0x10410039, 0x10410037 13829 0x1041003c, 0x1041003b, 0x10410039, 0x10410037
13830}; 13830};
13831 13831
13832static uint32 nphy_tpc_txgain_HiPwrEPA[] = { 13832static u32 nphy_tpc_txgain_HiPwrEPA[] = {
13833 0x0f410044, 0x0f410042, 0x0f410040, 0x0f41003e, 13833 0x0f410044, 0x0f410042, 0x0f410040, 0x0f41003e,
13834 0x0f41003c, 0x0f41003b, 0x0f410039, 0x0f410037, 13834 0x0f41003c, 0x0f41003b, 0x0f410039, 0x0f410037,
13835 0x0e410044, 0x0e410042, 0x0e410040, 0x0e41003e, 13835 0x0e410044, 0x0e410042, 0x0e410040, 0x0e41003e,
@@ -13864,7 +13864,7 @@ static uint32 nphy_tpc_txgain_HiPwrEPA[] = {
13864 0x0041003c, 0x0041003b, 0x00410039, 0x00410037 13864 0x0041003c, 0x0041003b, 0x00410039, 0x00410037
13865}; 13865};
13866 13866
13867static uint32 nphy_tpc_txgain_epa_2057rev3[] = { 13867static u32 nphy_tpc_txgain_epa_2057rev3[] = {
13868 0x80f90040, 0x80e10040, 0x80e1003c, 0x80c9003d, 13868 0x80f90040, 0x80e10040, 0x80e1003c, 0x80c9003d,
13869 0x80b9003c, 0x80a9003d, 0x80a1003c, 0x8099003b, 13869 0x80b9003c, 0x80a9003d, 0x80a1003c, 0x8099003b,
13870 0x8091003b, 0x8089003a, 0x8081003a, 0x80790039, 13870 0x8091003b, 0x8089003a, 0x8081003a, 0x80790039,
@@ -13899,7 +13899,7 @@ static uint32 nphy_tpc_txgain_epa_2057rev3[] = {
13899 0x8009071d, 0x8009071d, 0x8009071d, 0x8009071d 13899 0x8009071d, 0x8009071d, 0x8009071d, 0x8009071d
13900}; 13900};
13901 13901
13902static uint32 nphy_tpc_txgain_epa_2057rev5[] = { 13902static u32 nphy_tpc_txgain_epa_2057rev5[] = {
13903 0x10f90040, 0x10e10040, 0x10e1003c, 0x10c9003d, 13903 0x10f90040, 0x10e10040, 0x10e1003c, 0x10c9003d,
13904 0x10b9003c, 0x10a9003d, 0x10a1003c, 0x1099003b, 13904 0x10b9003c, 0x10a9003d, 0x10a1003c, 0x1099003b,
13905 0x1091003b, 0x1089003a, 0x1081003a, 0x10790039, 13905 0x1091003b, 0x1089003a, 0x1081003a, 0x10790039,
@@ -13934,7 +13934,7 @@ static uint32 nphy_tpc_txgain_epa_2057rev5[] = {
13934 0x10090001, 0x10090001, 0x10090001, 0x10090001 13934 0x10090001, 0x10090001, 0x10090001, 0x10090001
13935}; 13935};
13936 13936
13937static uint32 nphy_tpc_5GHz_txgain_rev3[] = { 13937static u32 nphy_tpc_5GHz_txgain_rev3[] = {
13938 0xcff70044, 0xcff70042, 0xcff70040, 0xcff7003e, 13938 0xcff70044, 0xcff70042, 0xcff70040, 0xcff7003e,
13939 0xcff7003c, 0xcff7003b, 0xcff70039, 0xcff70037, 13939 0xcff7003c, 0xcff7003b, 0xcff70039, 0xcff70037,
13940 0xcef70044, 0xcef70042, 0xcef70040, 0xcef7003e, 13940 0xcef70044, 0xcef70042, 0xcef70040, 0xcef7003e,
@@ -13969,7 +13969,7 @@ static uint32 nphy_tpc_5GHz_txgain_rev3[] = {
13969 0xc0f7003c, 0xc0f7003b, 0xc0f70039, 0xc0f70037 13969 0xc0f7003c, 0xc0f7003b, 0xc0f70039, 0xc0f70037
13970}; 13970};
13971 13971
13972static uint32 nphy_tpc_5GHz_txgain_rev4[] = { 13972static u32 nphy_tpc_5GHz_txgain_rev4[] = {
13973 0x2ff20044, 0x2ff20042, 0x2ff20040, 0x2ff2003e, 13973 0x2ff20044, 0x2ff20042, 0x2ff20040, 0x2ff2003e,
13974 0x2ff2003c, 0x2ff2003b, 0x2ff20039, 0x2ff20037, 13974 0x2ff2003c, 0x2ff2003b, 0x2ff20039, 0x2ff20037,
13975 0x2ef20044, 0x2ef20042, 0x2ef20040, 0x2ef2003e, 13975 0x2ef20044, 0x2ef20042, 0x2ef20040, 0x2ef2003e,
@@ -14004,7 +14004,7 @@ static uint32 nphy_tpc_5GHz_txgain_rev4[] = {
14004 0x20d2003a, 0x20d20038, 0x20d20036, 0x20d20034 14004 0x20d2003a, 0x20d20038, 0x20d20036, 0x20d20034
14005}; 14005};
14006 14006
14007static uint32 nphy_tpc_5GHz_txgain_rev5[] = { 14007static u32 nphy_tpc_5GHz_txgain_rev5[] = {
14008 0x0f62004a, 0x0f620048, 0x0f620046, 0x0f620044, 14008 0x0f62004a, 0x0f620048, 0x0f620046, 0x0f620044,
14009 0x0f620042, 0x0f620040, 0x0f62003e, 0x0f62003c, 14009 0x0f620042, 0x0f620040, 0x0f62003e, 0x0f62003c,
14010 0x0e620044, 0x0e620042, 0x0e620040, 0x0e62003e, 14010 0x0e620044, 0x0e620042, 0x0e620040, 0x0e62003e,
@@ -14039,7 +14039,7 @@ static uint32 nphy_tpc_5GHz_txgain_rev5[] = {
14039 0x0062003b, 0x00620039, 0x00620037, 0x00620035 14039 0x0062003b, 0x00620039, 0x00620037, 0x00620035
14040}; 14040};
14041 14041
14042static uint32 nphy_tpc_5GHz_txgain_HiPwrEPA[] = { 14042static u32 nphy_tpc_5GHz_txgain_HiPwrEPA[] = {
14043 0x2ff10044, 0x2ff10042, 0x2ff10040, 0x2ff1003e, 14043 0x2ff10044, 0x2ff10042, 0x2ff10040, 0x2ff1003e,
14044 0x2ff1003c, 0x2ff1003b, 0x2ff10039, 0x2ff10037, 14044 0x2ff1003c, 0x2ff1003b, 0x2ff10039, 0x2ff10037,
14045 0x2ef10044, 0x2ef10042, 0x2ef10040, 0x2ef1003e, 14045 0x2ef10044, 0x2ef10042, 0x2ef10040, 0x2ef1003e,
@@ -14092,7 +14092,7 @@ static void wlc_phy_chanspec_nphy_setup(phy_info_t *pi, chanspec_t chans,
14092static void wlc_phy_adjust_rx_analpfbw_nphy(phy_info_t *pi, 14092static void wlc_phy_adjust_rx_analpfbw_nphy(phy_info_t *pi,
14093 u16 reduction_factr); 14093 u16 reduction_factr);
14094static void wlc_phy_adjust_min_noisevar_nphy(phy_info_t *pi, int ntones, int *, 14094static void wlc_phy_adjust_min_noisevar_nphy(phy_info_t *pi, int ntones, int *,
14095 uint32 *buf); 14095 u32 *buf);
14096static void wlc_phy_adjust_crsminpwr_nphy(phy_info_t *pi, u8 minpwr); 14096static void wlc_phy_adjust_crsminpwr_nphy(phy_info_t *pi, u8 minpwr);
14097static void wlc_phy_txlpfbw_nphy(phy_info_t *pi); 14097static void wlc_phy_txlpfbw_nphy(phy_info_t *pi);
14098static void wlc_phy_spurwar_nphy(phy_info_t *pi); 14098static void wlc_phy_spurwar_nphy(phy_info_t *pi);
@@ -14133,10 +14133,10 @@ static void wlc_phy_ipa_set_tx_digi_filts_nphy(phy_info_t *pi);
14133static void wlc_phy_ipa_restore_tx_digi_filts_nphy(phy_info_t *pi); 14133static void wlc_phy_ipa_restore_tx_digi_filts_nphy(phy_info_t *pi);
14134static u16 wlc_phy_ipa_get_bbmult_nphy(phy_info_t *pi); 14134static u16 wlc_phy_ipa_get_bbmult_nphy(phy_info_t *pi);
14135static void wlc_phy_ipa_set_bbmult_nphy(phy_info_t *pi, u8 m0, u8 m1); 14135static void wlc_phy_ipa_set_bbmult_nphy(phy_info_t *pi, u8 m0, u8 m1);
14136static uint32 *wlc_phy_get_ipa_gaintbl_nphy(phy_info_t *pi); 14136static u32 *wlc_phy_get_ipa_gaintbl_nphy(phy_info_t *pi);
14137 14137
14138static void wlc_phy_a1_nphy(phy_info_t *pi, u8 core, uint32 winsz, uint32, 14138static void wlc_phy_a1_nphy(phy_info_t *pi, u8 core, u32 winsz, u32,
14139 uint32 e); 14139 u32 e);
14140static u8 wlc_phy_a3_nphy(phy_info_t *pi, u8 start_gain, u8 core); 14140static u8 wlc_phy_a3_nphy(phy_info_t *pi, u8 start_gain, u8 core);
14141static void wlc_phy_a2_nphy(phy_info_t *pi, nphy_ipa_txcalgains_t *, 14141static void wlc_phy_a2_nphy(phy_info_t *pi, nphy_ipa_txcalgains_t *,
14142 phy_cal_mode_t, u8); 14142 phy_cal_mode_t, u8);
@@ -14181,7 +14181,7 @@ static u16 wlc_phy_radio205x_rcal(phy_info_t *pi);
14181 14181
14182static u16 wlc_phy_radio2057_rccal(phy_info_t *pi); 14182static u16 wlc_phy_radio2057_rccal(phy_info_t *pi);
14183 14183
14184static u16 wlc_phy_gen_load_samples_nphy(phy_info_t *pi, uint32 f_kHz, 14184static u16 wlc_phy_gen_load_samples_nphy(phy_info_t *pi, u32 f_kHz,
14185 u16 max_val, 14185 u16 max_val,
14186 u8 dac_test_mode); 14186 u8 dac_test_mode);
14187static void wlc_phy_loadsampletable_nphy(phy_info_t *pi, cint32 *tone_buf, 14187static void wlc_phy_loadsampletable_nphy(phy_info_t *pi, cint32 *tone_buf,
@@ -14193,7 +14193,7 @@ static void wlc_phy_runsamples_nphy(phy_info_t *pi, u16 n, u16 lps,
14193bool wlc_phy_bist_check_phy(wlc_phy_t *pih) 14193bool wlc_phy_bist_check_phy(wlc_phy_t *pih)
14194{ 14194{
14195 phy_info_t *pi = (phy_info_t *) pih; 14195 phy_info_t *pi = (phy_info_t *) pih;
14196 uint32 phybist0, phybist1, phybist2, phybist3, phybist4; 14196 u32 phybist0, phybist1, phybist2, phybist3, phybist4;
14197 14197
14198 if (NREV_GE(pi->pubpi.phy_rev, 16)) 14198 if (NREV_GE(pi->pubpi.phy_rev, 16))
14199 return TRUE; 14199 return TRUE;
@@ -14243,8 +14243,8 @@ static void WLBANDINITFN(wlc_phy_bphy_init_nphy) (phy_info_t *pi)
14243} 14243}
14244 14244
14245void 14245void
14246wlc_phy_table_write_nphy(phy_info_t *pi, uint32 id, uint32 len, uint32 offset, 14246wlc_phy_table_write_nphy(phy_info_t *pi, u32 id, u32 len, u32 offset,
14247 uint32 width, const void *data) 14247 u32 width, const void *data)
14248{ 14248{
14249 mimophytbl_info_t tbl; 14249 mimophytbl_info_t tbl;
14250 14250
@@ -14257,8 +14257,8 @@ wlc_phy_table_write_nphy(phy_info_t *pi, uint32 id, uint32 len, uint32 offset,
14257} 14257}
14258 14258
14259void 14259void
14260wlc_phy_table_read_nphy(phy_info_t *pi, uint32 id, uint32 len, uint32 offset, 14260wlc_phy_table_read_nphy(phy_info_t *pi, u32 id, u32 len, u32 offset,
14261 uint32 width, void *data) 14261 u32 width, void *data)
14262{ 14262{
14263 mimophytbl_info_t tbl; 14263 mimophytbl_info_t tbl;
14264 14264
@@ -14535,7 +14535,7 @@ void WLBANDINITFN(wlc_phy_init_nphy) (phy_info_t *pi)
14535 uint core; 14535 uint core;
14536 uint origidx, intr_val; 14536 uint origidx, intr_val;
14537 d11regs_t *regs; 14537 d11regs_t *regs;
14538 uint32 d11_clk_ctl_st; 14538 u32 d11_clk_ctl_st;
14539 14539
14540 core = 0; 14540 core = 0;
14541 14541
@@ -14703,7 +14703,7 @@ void WLBANDINITFN(wlc_phy_init_nphy) (phy_info_t *pi)
14703 wlc_phy_txpwrctrl_pwr_setup_nphy(pi); 14703 wlc_phy_txpwrctrl_pwr_setup_nphy(pi);
14704 14704
14705 if (NREV_GE(pi->pubpi.phy_rev, 3)) { 14705 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
14706 uint32 *tx_pwrctrl_tbl = NULL; 14706 u32 *tx_pwrctrl_tbl = NULL;
14707 u16 idx; 14707 u16 idx;
14708 s16 pga_gn = 0; 14708 s16 pga_gn = 0;
14709 s16 pad_gn = 0; 14709 s16 pad_gn = 0;
@@ -15330,7 +15330,7 @@ static void wlc_phy_workarounds_nphy(phy_info_t *pi)
15330 15330
15331 s16 alpha0, alpha1, alpha2; 15331 s16 alpha0, alpha1, alpha2;
15332 s16 beta0, beta1, beta2; 15332 s16 beta0, beta1, beta2;
15333 uint32 leg_data_weights, ht_data_weights, nss1_data_weights, 15333 u32 leg_data_weights, ht_data_weights, nss1_data_weights,
15334 stbc_data_weights; 15334 stbc_data_weights;
15335 u8 chan_freq_range = 0; 15335 u8 chan_freq_range = 0;
15336 u16 dac_control = 0x0002; 15336 u16 dac_control = 0x0002;
@@ -17629,7 +17629,7 @@ wlc_phy_chan2freq_nphy(phy_info_t *pi, uint channel, int *f,
17629 chan_info_nphy_radio2057_t *chan_info_tbl_p_0 = NULL; 17629 chan_info_nphy_radio2057_t *chan_info_tbl_p_0 = NULL;
17630 chan_info_nphy_radio205x_t *chan_info_tbl_p_1 = NULL; 17630 chan_info_nphy_radio205x_t *chan_info_tbl_p_1 = NULL;
17631 chan_info_nphy_radio2057_rev5_t *chan_info_tbl_p_2 = NULL; 17631 chan_info_nphy_radio2057_rev5_t *chan_info_tbl_p_2 = NULL;
17632 uint32 tbl_len = 0; 17632 u32 tbl_len = 0;
17633 17633
17634 int freq = 0; 17634 int freq = 0;
17635 17635
@@ -18656,10 +18656,10 @@ wlc_phy_adjust_rx_analpfbw_nphy(phy_info_t *pi, u16 reduction_factr)
18656 18656
18657static void 18657static void
18658wlc_phy_adjust_min_noisevar_nphy(phy_info_t *pi, int ntones, int *tone_id_buf, 18658wlc_phy_adjust_min_noisevar_nphy(phy_info_t *pi, int ntones, int *tone_id_buf,
18659 uint32 *noise_var_buf) 18659 u32 *noise_var_buf)
18660{ 18660{
18661 int i; 18661 int i;
18662 uint32 offset; 18662 u32 offset;
18663 int tone_id; 18663 int tone_id;
18664 int tbllen = 18664 int tbllen =
18665 CHSPEC_IS40(pi-> 18665 CHSPEC_IS40(pi->
@@ -18798,10 +18798,10 @@ static void wlc_phy_spurwar_nphy(phy_info_t *pi)
18798{ 18798{
18799 u16 cur_channel = 0; 18799 u16 cur_channel = 0;
18800 int nphy_adj_tone_id_buf[] = { 57, 58 }; 18800 int nphy_adj_tone_id_buf[] = { 57, 58 };
18801 uint32 nphy_adj_noise_var_buf[] = { 0x3ff, 0x3ff }; 18801 u32 nphy_adj_noise_var_buf[] = { 0x3ff, 0x3ff };
18802 bool isAdjustNoiseVar = FALSE; 18802 bool isAdjustNoiseVar = FALSE;
18803 uint numTonesAdjust = 0; 18803 uint numTonesAdjust = 0;
18804 uint32 tempval = 0; 18804 u32 tempval = 0;
18805 18805
18806 if (NREV_GE(pi->pubpi.phy_rev, 3)) { 18806 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
18807 if (pi->phyhang_avoid) 18807 if (pi->phyhang_avoid)
@@ -19563,7 +19563,7 @@ void wlc_phy_antsel_init(wlc_phy_t *ppi, bool lut_init)
19563{ 19563{
19564 phy_info_t *pi = (phy_info_t *) ppi; 19564 phy_info_t *pi = (phy_info_t *) ppi;
19565 u16 mask = 0xfc00; 19565 u16 mask = 0xfc00;
19566 uint32 mc = 0; 19566 u32 mc = 0;
19567 19567
19568 if (NREV_GE(pi->pubpi.phy_rev, 7)) 19568 if (NREV_GE(pi->pubpi.phy_rev, 7))
19569 return; 19569 return;
@@ -19709,7 +19709,7 @@ static void
19709wlc_phy_set_rfseq_nphy(phy_info_t *pi, u8 cmd, u8 *events, u8 *dlys, 19709wlc_phy_set_rfseq_nphy(phy_info_t *pi, u8 cmd, u8 *events, u8 *dlys,
19710 u8 len) 19710 u8 len)
19711{ 19711{
19712 uint32 t1_offset, t2_offset; 19712 u32 t1_offset, t2_offset;
19713 u8 ctr; 19713 u8 ctr;
19714 u8 end_event = 19714 u8 end_event =
19715 NREV_GE(pi->pubpi.phy_rev, 19715 NREV_GE(pi->pubpi.phy_rev,
@@ -19754,7 +19754,7 @@ static u16 wlc_phy_read_lpf_bw_ctl_nphy(phy_info_t *pi, u16 offset)
19754 rx2tx_lpf_rc_lut_offset = offset; 19754 rx2tx_lpf_rc_lut_offset = offset;
19755 } 19755 }
19756 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_RFSEQ, 1, 19756 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_RFSEQ, 1,
19757 (uint32) rx2tx_lpf_rc_lut_offset, 16, 19757 (u32) rx2tx_lpf_rc_lut_offset, 16,
19758 &lpf_bw_ctl_val); 19758 &lpf_bw_ctl_val);
19759 19759
19760 lpf_bw_ctl_val = lpf_bw_ctl_val & 0x7; 19760 lpf_bw_ctl_val = lpf_bw_ctl_val & 0x7;
@@ -22338,13 +22338,13 @@ static void wlc_phy_restore_rssical_nphy(phy_info_t *pi)
22338} 22338}
22339 22339
22340static u16 22340static u16
22341wlc_phy_gen_load_samples_nphy(phy_info_t *pi, uint32 f_kHz, u16 max_val, 22341wlc_phy_gen_load_samples_nphy(phy_info_t *pi, u32 f_kHz, u16 max_val,
22342 u8 dac_test_mode) 22342 u8 dac_test_mode)
22343{ 22343{
22344 u8 phy_bw, is_phybw40; 22344 u8 phy_bw, is_phybw40;
22345 u16 num_samps, t, spur; 22345 u16 num_samps, t, spur;
22346 fixed theta = 0, rot = 0; 22346 fixed theta = 0, rot = 0;
22347 uint32 tbl_len; 22347 u32 tbl_len;
22348 cint32 *tone_buf = NULL; 22348 cint32 *tone_buf = NULL;
22349 22349
22350 is_phybw40 = CHSPEC_IS40(pi->radio_chanspec); 22350 is_phybw40 = CHSPEC_IS40(pi->radio_chanspec);
@@ -22388,7 +22388,7 @@ wlc_phy_gen_load_samples_nphy(phy_info_t *pi, uint32 f_kHz, u16 max_val,
22388} 22388}
22389 22389
22390int 22390int
22391wlc_phy_tx_tone_nphy(phy_info_t *pi, uint32 f_kHz, u16 max_val, 22391wlc_phy_tx_tone_nphy(phy_info_t *pi, u32 f_kHz, u16 max_val,
22392 u8 iqmode, u8 dac_test_mode, bool modify_bbmult) 22392 u8 iqmode, u8 dac_test_mode, bool modify_bbmult)
22393{ 22393{
22394 u16 num_samps; 22394 u16 num_samps;
@@ -22412,9 +22412,9 @@ wlc_phy_loadsampletable_nphy(phy_info_t *pi, cint32 *tone_buf,
22412 u16 num_samps) 22412 u16 num_samps)
22413{ 22413{
22414 u16 t; 22414 u16 t;
22415 uint32 *data_buf = NULL; 22415 u32 *data_buf = NULL;
22416 22416
22417 data_buf = (uint32 *) MALLOC(pi->sh->osh, sizeof(uint32) * num_samps); 22417 data_buf = (u32 *) MALLOC(pi->sh->osh, sizeof(u32) * num_samps);
22418 if (data_buf == NULL) { 22418 if (data_buf == NULL) {
22419 return; 22419 return;
22420 } 22420 }
@@ -22430,7 +22430,7 @@ wlc_phy_loadsampletable_nphy(phy_info_t *pi, cint32 *tone_buf,
22430 data_buf); 22430 data_buf);
22431 22431
22432 if (data_buf != NULL) 22432 if (data_buf != NULL)
22433 MFREE(pi->sh->osh, data_buf, sizeof(uint32) * num_samps); 22433 MFREE(pi->sh->osh, data_buf, sizeof(u32) * num_samps);
22434 22434
22435 if (pi->phyhang_avoid) 22435 if (pi->phyhang_avoid)
22436 wlc_phy_stay_in_carriersearch_nphy(pi, FALSE); 22436 wlc_phy_stay_in_carriersearch_nphy(pi, FALSE);
@@ -22571,7 +22571,7 @@ nphy_txgains_t wlc_phy_get_tx_gain_nphy(phy_info_t *pi)
22571 u16 base_idx[2], curr_gain[2]; 22571 u16 base_idx[2], curr_gain[2];
22572 u8 core_no; 22572 u8 core_no;
22573 nphy_txgains_t target_gain; 22573 nphy_txgains_t target_gain;
22574 uint32 *tx_pwrctrl_tbl = NULL; 22574 u32 *tx_pwrctrl_tbl = NULL;
22575 22575
22576 if (pi->nphy_txpwrctrl == PHY_TPC_HW_OFF) { 22576 if (pi->nphy_txpwrctrl == PHY_TPC_HW_OFF) {
22577 if (pi->phyhang_avoid) 22577 if (pi->phyhang_avoid)
@@ -23513,9 +23513,9 @@ wlc_phy_est_tonepwr_nphy(phy_info_t *pi, int32 *qdBm_pwrbuf, u8 num_samps)
23513 } 23513 }
23514 23514
23515 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_CORE1TXPWRCTL, 1, 23515 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_CORE1TXPWRCTL, 1,
23516 (uint32) pwrindex[0], 32, &qdBm_pwrbuf[0]); 23516 (u32) pwrindex[0], 32, &qdBm_pwrbuf[0]);
23517 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_CORE2TXPWRCTL, 1, 23517 wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_CORE2TXPWRCTL, 1,
23518 (uint32) pwrindex[1], 32, &qdBm_pwrbuf[1]); 23518 (u32) pwrindex[1], 32, &qdBm_pwrbuf[1]);
23519} 23519}
23520 23520
23521static void wlc_phy_internal_cal_txgain_nphy(phy_info_t *pi) 23521static void wlc_phy_internal_cal_txgain_nphy(phy_info_t *pi)
@@ -23640,7 +23640,7 @@ wlc_phy_cal_txgainctrl_nphy(phy_info_t *pi, int32 dBm_targetpower, bool debug)
23640 int32 qdBm_power[2]; 23640 int32 qdBm_power[2];
23641 u16 orig_BBConfig; 23641 u16 orig_BBConfig;
23642 u16 phy_saveregs[4]; 23642 u16 phy_saveregs[4];
23643 uint32 freq_test; 23643 u32 freq_test;
23644 u16 ampl_test = 250; 23644 u16 ampl_test = 250;
23645 uint stepsize; 23645 uint stepsize;
23646 bool phyhang_avoid_state = FALSE; 23646 bool phyhang_avoid_state = FALSE;
@@ -23800,7 +23800,7 @@ wlc_phy_cal_txgainctrl_nphy(phy_info_t *pi, int32 dBm_targetpower, bool debug)
23800static void wlc_phy_update_txcal_ladder_nphy(phy_info_t *pi, u16 core) 23800static void wlc_phy_update_txcal_ladder_nphy(phy_info_t *pi, u16 core)
23801{ 23801{
23802 int index; 23802 int index;
23803 uint32 bbmult_scale; 23803 u32 bbmult_scale;
23804 u16 bbmult; 23804 u16 bbmult;
23805 u16 tblentry; 23805 u16 tblentry;
23806 23806
@@ -24112,7 +24112,7 @@ wlc_phy_cal_txiqlo_nphy(phy_info_t *pi, nphy_txgains_t target_gain,
24112 u16 gain_save[2]; 24112 u16 gain_save[2];
24113 u16 cal_gain[2]; 24113 u16 cal_gain[2];
24114 nphy_iqcal_params_t cal_params[2]; 24114 nphy_iqcal_params_t cal_params[2];
24115 uint32 tbl_len; 24115 u32 tbl_len;
24116 void *tbl_ptr; 24116 void *tbl_ptr;
24117 bool ladder_updated[2]; 24117 bool ladder_updated[2];
24118 u8 mphase_cal_lastphase = 0; 24118 u8 mphase_cal_lastphase = 0;
@@ -24569,7 +24569,7 @@ static void wlc_phy_calc_rx_iq_comp_nphy(phy_info_t *pi, u8 core_mask)
24569 phy_iq_est_t est[PHY_CORE_MAX]; 24569 phy_iq_est_t est[PHY_CORE_MAX];
24570 nphy_iq_comp_t old_comp, new_comp; 24570 nphy_iq_comp_t old_comp, new_comp;
24571 int32 iq = 0; 24571 int32 iq = 0;
24572 uint32 ii = 0, qq = 0; 24572 u32 ii = 0, qq = 0;
24573 s16 iq_nbits, qq_nbits, brsh, arsh; 24573 s16 iq_nbits, qq_nbits, brsh, arsh;
24574 int32 a, b, temp; 24574 int32 a, b, temp;
24575 int bcmerror = BCME_OK; 24575 int bcmerror = BCME_OK;
@@ -24646,7 +24646,7 @@ static void wlc_phy_calc_rx_iq_comp_nphy(phy_info_t *pi, u8 core_mask)
24646 } 24646 }
24647 b /= temp; 24647 b /= temp;
24648 b -= a * a; 24648 b -= a * a;
24649 b = (int32) wlc_phy_sqrt_int((uint32) b); 24649 b = (int32) wlc_phy_sqrt_int((u32) b);
24650 b -= (1 << 10); 24650 b -= (1 << 10);
24651 24651
24652 if ((curr_core == PHY_CORE_0) && (core_mask & 0x1)) { 24652 if ((curr_core == PHY_CORE_0) && (core_mask & 0x1)) {
@@ -25315,7 +25315,7 @@ wlc_phy_rxcal_gainctrl_nphy_rev5(phy_info_t *pi, u8 rx_core,
25315 phy_iq_est_t est[PHY_CORE_MAX]; 25315 phy_iq_est_t est[PHY_CORE_MAX];
25316 u8 tx_core; 25316 u8 tx_core;
25317 nphy_iq_comp_t save_comp, zero_comp; 25317 nphy_iq_comp_t save_comp, zero_comp;
25318 uint32 i_pwr, q_pwr, curr_pwr, optim_pwr = 0, prev_pwr = 0, thresh_pwr = 25318 u32 i_pwr, q_pwr, curr_pwr, optim_pwr = 0, prev_pwr = 0, thresh_pwr =
25319 10000; 25319 10000;
25320 s16 desired_log2_pwr, actual_log2_pwr, delta_pwr; 25320 s16 desired_log2_pwr, actual_log2_pwr, delta_pwr;
25321 bool gainctrl_done = FALSE; 25321 bool gainctrl_done = FALSE;
@@ -25524,12 +25524,12 @@ wlc_phy_rxcal_gainctrl_nphy(phy_info_t *pi, u8 rx_core, u16 *rxgain,
25524static u8 25524static u8
25525wlc_phy_rc_sweep_nphy(phy_info_t *pi, u8 core_idx, u8 loopback_type) 25525wlc_phy_rc_sweep_nphy(phy_info_t *pi, u8 core_idx, u8 loopback_type)
25526{ 25526{
25527 uint32 target_bws[2] = { 9500, 21000 }; 25527 u32 target_bws[2] = { 9500, 21000 };
25528 uint32 ref_tones[2] = { 3000, 6000 }; 25528 u32 ref_tones[2] = { 3000, 6000 };
25529 uint32 target_bw, ref_tone; 25529 u32 target_bw, ref_tone;
25530 25530
25531 uint32 target_pwr_ratios[2] = { 28606, 18468 }; 25531 u32 target_pwr_ratios[2] = { 28606, 18468 };
25532 uint32 target_pwr_ratio, pwr_ratio, last_pwr_ratio = 0; 25532 u32 target_pwr_ratio, pwr_ratio, last_pwr_ratio = 0;
25533 25533
25534 u16 start_rccal_ovr_val = 128; 25534 u16 start_rccal_ovr_val = 128;
25535 u16 txlpf_rccal_lpc_ovr_val = 128; 25535 u16 txlpf_rccal_lpc_ovr_val = 128;
@@ -25552,7 +25552,7 @@ wlc_phy_rc_sweep_nphy(phy_info_t *pi, u8 core_idx, u8 loopback_type)
25552 25552
25553 s8 rccal_stepsize; 25553 s8 rccal_stepsize;
25554 u16 rccal_val, last_rccal_val = 0, best_rccal_val = 0; 25554 u16 rccal_val, last_rccal_val = 0, best_rccal_val = 0;
25555 uint32 ref_iq_vals = 0, target_iq_vals = 0; 25555 u32 ref_iq_vals = 0, target_iq_vals = 0;
25556 u16 num_samps, log_num_samps = 10; 25556 u16 num_samps, log_num_samps = 10;
25557 phy_iq_est_t est[PHY_CORE_MAX]; 25557 phy_iq_est_t est[PHY_CORE_MAX];
25558 25558
@@ -25933,7 +25933,7 @@ wlc_phy_cal_rxiq_nphy_rev2(phy_info_t *pi, nphy_txgains_t target_gain,
25933 u16 orig_RfseqCoreActv, orig_AfectrlCore, orig_AfectrlOverride; 25933 u16 orig_RfseqCoreActv, orig_AfectrlCore, orig_AfectrlOverride;
25934 u16 orig_RfctrlIntcRx, orig_RfctrlIntcTx; 25934 u16 orig_RfctrlIntcRx, orig_RfctrlIntcTx;
25935 u16 num_samps; 25935 u16 num_samps;
25936 uint32 i_pwr, q_pwr, tot_pwr[3]; 25936 u32 i_pwr, q_pwr, tot_pwr[3];
25937 u8 gain_pass, use_hpf_num; 25937 u8 gain_pass, use_hpf_num;
25938 u16 mask, val1, val2; 25938 u16 mask, val1, val2;
25939 u16 core_no; 25939 u16 core_no;
@@ -26244,9 +26244,9 @@ static void wlc_phy_ipa_set_bbmult_nphy(phy_info_t *pi, u8 m0, u8 m1)
26244 wlc_phy_table_write_nphy(pi, 15, 1, 95, 16, &m0m1); 26244 wlc_phy_table_write_nphy(pi, 15, 1, 95, 16, &m0m1);
26245} 26245}
26246 26246
26247static uint32 *wlc_phy_get_ipa_gaintbl_nphy(phy_info_t *pi) 26247static u32 *wlc_phy_get_ipa_gaintbl_nphy(phy_info_t *pi)
26248{ 26248{
26249 uint32 *tx_pwrctrl_tbl = NULL; 26249 u32 *tx_pwrctrl_tbl = NULL;
26250 26250
26251 if (CHSPEC_IS2G(pi->radio_chanspec)) { 26251 if (CHSPEC_IS2G(pi->radio_chanspec)) {
26252 26252
@@ -26718,16 +26718,16 @@ wlc_phy_papd_cal_cleanup_nphy(phy_info_t *pi, nphy_papd_restore_state *state)
26718} 26718}
26719 26719
26720static void 26720static void
26721wlc_phy_a1_nphy(phy_info_t *pi, u8 core, uint32 winsz, uint32 start, 26721wlc_phy_a1_nphy(phy_info_t *pi, u8 core, u32 winsz, u32 start,
26722 uint32 end) 26722 u32 end)
26723{ 26723{
26724 uint32 *buf, *src, *dst, sz; 26724 u32 *buf, *src, *dst, sz;
26725 26725
26726 sz = end - start + 1; 26726 sz = end - start + 1;
26727 ASSERT(end > start); 26727 ASSERT(end > start);
26728 ASSERT(end < NPHY_PAPD_EPS_TBL_SIZE); 26728 ASSERT(end < NPHY_PAPD_EPS_TBL_SIZE);
26729 26729
26730 buf = MALLOC(pi->sh->osh, 2 * sizeof(uint32) * NPHY_PAPD_EPS_TBL_SIZE); 26730 buf = MALLOC(pi->sh->osh, 2 * sizeof(u32) * NPHY_PAPD_EPS_TBL_SIZE);
26731 if (NULL == buf) { 26731 if (NULL == buf) {
26732 return; 26732 return;
26733 } 26733 }
@@ -26742,7 +26742,7 @@ wlc_phy_a1_nphy(phy_info_t *pi, u8 core, uint32 winsz, uint32 start,
26742 NPHY_PAPD_EPS_TBL_SIZE, 0, 32, src); 26742 NPHY_PAPD_EPS_TBL_SIZE, 0, 32, src);
26743 26743
26744 do { 26744 do {
26745 uint32 phy_a1, phy_a2; 26745 u32 phy_a1, phy_a2;
26746 int32 phy_a3, phy_a4, phy_a5, phy_a6, phy_a7; 26746 int32 phy_a3, phy_a4, phy_a5, phy_a6, phy_a7;
26747 26747
26748 phy_a1 = end - MIN(end, (winsz >> 1)); 26748 phy_a1 = end - MIN(end, (winsz >> 1));
@@ -26760,7 +26760,7 @@ wlc_phy_a1_nphy(phy_info_t *pi, u8 core, uint32 winsz, uint32 start,
26760 26760
26761 phy_a6 /= phy_a3; 26761 phy_a6 /= phy_a3;
26762 phy_a7 /= phy_a3; 26762 phy_a7 /= phy_a3;
26763 dst[end] = ((uint32) phy_a7 << 13) | ((uint32) phy_a6 & 0x1fff); 26763 dst[end] = ((u32) phy_a7 << 13) | ((u32) phy_a6 & 0x1fff);
26764 } while (end-- != start); 26764 } while (end-- != start);
26765 26765
26766 wlc_phy_table_write_nphy(pi, 26766 wlc_phy_table_write_nphy(pi,
@@ -26768,7 +26768,7 @@ wlc_phy_a1_nphy(phy_info_t *pi, u8 core, uint32 winsz, uint32 start,
26768 PHY_CORE_0) ? NPHY_TBL_ID_EPSILONTBL0 : 26768 PHY_CORE_0) ? NPHY_TBL_ID_EPSILONTBL0 :
26769 NPHY_TBL_ID_EPSILONTBL1, sz, start, 32, dst); 26769 NPHY_TBL_ID_EPSILONTBL1, sz, start, 32, dst);
26770 26770
26771 MFREE(pi->sh->osh, buf, 2 * sizeof(uint32) * NPHY_PAPD_EPS_TBL_SIZE); 26771 MFREE(pi->sh->osh, buf, 2 * sizeof(u32) * NPHY_PAPD_EPS_TBL_SIZE);
26772} 26772}
26773 26773
26774static void 26774static void
@@ -26779,7 +26779,7 @@ wlc_phy_a2_nphy(phy_info_t *pi, nphy_ipa_txcalgains_t *txgains,
26779 u16 phy_a4, phy_a5; 26779 u16 phy_a4, phy_a5;
26780 bool phy_a6; 26780 bool phy_a6;
26781 u8 phy_a7, m[2]; 26781 u8 phy_a7, m[2];
26782 uint32 phy_a8 = 0; 26782 u32 phy_a8 = 0;
26783 nphy_txgains_t phy_a9; 26783 nphy_txgains_t phy_a9;
26784 26784
26785 if (NREV_LT(pi->pubpi.phy_rev, 3)) 26785 if (NREV_LT(pi->pubpi.phy_rev, 3))
@@ -27081,7 +27081,7 @@ static u8 wlc_phy_a3_nphy(phy_info_t *pi, u8 start_gain, u8 core)
27081 bool phy_a5 = FALSE; 27081 bool phy_a5 = FALSE;
27082 bool phy_a6 = TRUE; 27082 bool phy_a6 = TRUE;
27083 int32 phy_a7, phy_a8; 27083 int32 phy_a7, phy_a8;
27084 uint32 phy_a9; 27084 u32 phy_a9;
27085 int phy_a10; 27085 int phy_a10;
27086 bool phy_a11 = FALSE; 27086 bool phy_a11 = FALSE;
27087 int phy_a12; 27087 int phy_a12;
@@ -27531,7 +27531,7 @@ static void wlc_phy_a4(phy_info_t *pi, bool full_cal)
27531void wlc_phy_txpwr_fixpower_nphy(phy_info_t *pi) 27531void wlc_phy_txpwr_fixpower_nphy(phy_info_t *pi)
27532{ 27532{
27533 uint core; 27533 uint core;
27534 uint32 txgain; 27534 u32 txgain;
27535 u16 rad_gain, dac_gain, bbmult, m1m2; 27535 u16 rad_gain, dac_gain, bbmult, m1m2;
27536 u8 txpi[2], chan_freq_range; 27536 u8 txpi[2], chan_freq_range;
27537 int32 rfpwr_offset; 27537 int32 rfpwr_offset;
@@ -27590,7 +27590,7 @@ void wlc_phy_txpwr_fixpower_nphy(phy_info_t *pi)
27590 for (core = 0; core < pi->pubpi.phy_corenum; core++) { 27590 for (core = 0; core < pi->pubpi.phy_corenum; core++) {
27591 if (NREV_GE(pi->pubpi.phy_rev, 3)) { 27591 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
27592 if (PHY_IPA(pi)) { 27592 if (PHY_IPA(pi)) {
27593 uint32 *tx_gaintbl = 27593 u32 *tx_gaintbl =
27594 wlc_phy_get_ipa_gaintbl_nphy(pi); 27594 wlc_phy_get_ipa_gaintbl_nphy(pi);
27595 txgain = tx_gaintbl[txpi[core]]; 27595 txgain = tx_gaintbl[txpi[core]];
27596 } else { 27596 } else {
@@ -28005,7 +28005,7 @@ static void BCMATTACHFN(wlc_phy_txpwr_srom_read_ppr_nphy) (phy_info_t *pi)
28005 28005
28006 pi->cck2gpo = (u16) PHY_GETINTVAR(pi, "cck2gpo"); 28006 pi->cck2gpo = (u16) PHY_GETINTVAR(pi, "cck2gpo");
28007 28007
28008 pi->ofdm2gpo = (uint32) PHY_GETINTVAR(pi, "ofdm2gpo"); 28008 pi->ofdm2gpo = (u32) PHY_GETINTVAR(pi, "ofdm2gpo");
28009 28009
28010 pi->mcs2gpo[0] = (u16) PHY_GETINTVAR(pi, "mcs2gpo0"); 28010 pi->mcs2gpo[0] = (u16) PHY_GETINTVAR(pi, "mcs2gpo0");
28011 pi->mcs2gpo[1] = (u16) PHY_GETINTVAR(pi, "mcs2gpo1"); 28011 pi->mcs2gpo[1] = (u16) PHY_GETINTVAR(pi, "mcs2gpo1");
@@ -28043,7 +28043,7 @@ static void BCMATTACHFN(wlc_phy_txpwr_srom_read_ppr_nphy) (phy_info_t *pi)
28043 pi->nphy_pwrctrl_info[PHY_CORE_1].idle_targ_5gm = 28043 pi->nphy_pwrctrl_info[PHY_CORE_1].idle_targ_5gm =
28044 (s8) PHY_GETINTVAR(pi, "itt5ga1"); 28044 (s8) PHY_GETINTVAR(pi, "itt5ga1");
28045 28045
28046 pi->ofdm5gpo = (uint32) PHY_GETINTVAR(pi, "ofdm5gpo"); 28046 pi->ofdm5gpo = (u32) PHY_GETINTVAR(pi, "ofdm5gpo");
28047 28047
28048 pi->mcs5gpo[0] = (u16) PHY_GETINTVAR(pi, "mcs5gpo0"); 28048 pi->mcs5gpo[0] = (u16) PHY_GETINTVAR(pi, "mcs5gpo0");
28049 pi->mcs5gpo[1] = (u16) PHY_GETINTVAR(pi, "mcs5gpo1"); 28049 pi->mcs5gpo[1] = (u16) PHY_GETINTVAR(pi, "mcs5gpo1");
@@ -28079,7 +28079,7 @@ static void BCMATTACHFN(wlc_phy_txpwr_srom_read_ppr_nphy) (phy_info_t *pi)
28079 pi->nphy_pwrctrl_info[0].idle_targ_5gl = 0; 28079 pi->nphy_pwrctrl_info[0].idle_targ_5gl = 0;
28080 pi->nphy_pwrctrl_info[1].idle_targ_5gl = 0; 28080 pi->nphy_pwrctrl_info[1].idle_targ_5gl = 0;
28081 28081
28082 pi->ofdm5glpo = (uint32) PHY_GETINTVAR(pi, "ofdm5glpo"); 28082 pi->ofdm5glpo = (u32) PHY_GETINTVAR(pi, "ofdm5glpo");
28083 28083
28084 pi->mcs5glpo[0] = 28084 pi->mcs5glpo[0] =
28085 (u16) PHY_GETINTVAR(pi, "mcs5glpo0"); 28085 (u16) PHY_GETINTVAR(pi, "mcs5glpo0");
@@ -28123,7 +28123,7 @@ static void BCMATTACHFN(wlc_phy_txpwr_srom_read_ppr_nphy) (phy_info_t *pi)
28123 pi->nphy_pwrctrl_info[0].idle_targ_5gh = 0; 28123 pi->nphy_pwrctrl_info[0].idle_targ_5gh = 0;
28124 pi->nphy_pwrctrl_info[1].idle_targ_5gh = 0; 28124 pi->nphy_pwrctrl_info[1].idle_targ_5gh = 0;
28125 28125
28126 pi->ofdm5ghpo = (uint32) PHY_GETINTVAR(pi, "ofdm5ghpo"); 28126 pi->ofdm5ghpo = (u32) PHY_GETINTVAR(pi, "ofdm5ghpo");
28127 28127
28128 pi->mcs5ghpo[0] = 28128 pi->mcs5ghpo[0] =
28129 (u16) PHY_GETINTVAR(pi, "mcs5ghpo0"); 28129 (u16) PHY_GETINTVAR(pi, "mcs5ghpo0");
@@ -28230,13 +28230,13 @@ void wlc_phy_txpower_recalc_target_nphy(phy_info_t *pi)
28230 28230
28231static void wlc_phy_txpwrctrl_coeff_setup_nphy(phy_info_t *pi) 28231static void wlc_phy_txpwrctrl_coeff_setup_nphy(phy_info_t *pi)
28232{ 28232{
28233 uint32 idx; 28233 u32 idx;
28234 u16 iqloCalbuf[7]; 28234 u16 iqloCalbuf[7];
28235 uint32 iqcomp, locomp, curr_locomp; 28235 u32 iqcomp, locomp, curr_locomp;
28236 s8 locomp_i, locomp_q; 28236 s8 locomp_i, locomp_q;
28237 s8 curr_locomp_i, curr_locomp_q; 28237 s8 curr_locomp_i, curr_locomp_q;
28238 uint32 tbl_id, tbl_len, tbl_offset; 28238 u32 tbl_id, tbl_len, tbl_offset;
28239 uint32 regval[128]; 28239 u32 regval[128];
28240 28240
28241 if (pi->phyhang_avoid) 28241 if (pi->phyhang_avoid)
28242 wlc_phy_stay_in_carriersearch_nphy(pi, TRUE); 28242 wlc_phy_stay_in_carriersearch_nphy(pi, TRUE);
@@ -28249,9 +28249,9 @@ static void wlc_phy_txpwrctrl_coeff_setup_nphy(phy_info_t *pi)
28249 tbl_id <= NPHY_TBL_ID_CORE2TXPWRCTL; tbl_id++) { 28249 tbl_id <= NPHY_TBL_ID_CORE2TXPWRCTL; tbl_id++) {
28250 iqcomp = 28250 iqcomp =
28251 (tbl_id == 28251 (tbl_id ==
28252 26) ? (((uint32) (iqloCalbuf[0] & 0x3ff)) << 10) | 28252 26) ? (((u32) (iqloCalbuf[0] & 0x3ff)) << 10) |
28253 (iqloCalbuf[1] & 0x3ff) 28253 (iqloCalbuf[1] & 0x3ff)
28254 : (((uint32) (iqloCalbuf[2] & 0x3ff)) << 10) | 28254 : (((u32) (iqloCalbuf[2] & 0x3ff)) << 10) |
28255 (iqloCalbuf[3] & 0x3ff); 28255 (iqloCalbuf[3] & 0x3ff);
28256 28256
28257 for (idx = 0; idx < tbl_len; idx++) { 28257 for (idx = 0; idx < tbl_len; idx++) {
@@ -28266,7 +28266,7 @@ static void wlc_phy_txpwrctrl_coeff_setup_nphy(phy_info_t *pi)
28266 tbl_id <= NPHY_TBL_ID_CORE2TXPWRCTL; tbl_id++) { 28266 tbl_id <= NPHY_TBL_ID_CORE2TXPWRCTL; tbl_id++) {
28267 28267
28268 locomp = 28268 locomp =
28269 (uint32) ((tbl_id == 26) ? iqloCalbuf[5] : iqloCalbuf[6]); 28269 (u32) ((tbl_id == 26) ? iqloCalbuf[5] : iqloCalbuf[6]);
28270 locomp_i = (s8) ((locomp >> 8) & 0xff); 28270 locomp_i = (s8) ((locomp >> 8) & 0xff);
28271 locomp_q = (s8) ((locomp) & 0xff); 28271 locomp_q = (s8) ((locomp) & 0xff);
28272 for (idx = 0; idx < tbl_len; idx++) { 28272 for (idx = 0; idx < tbl_len; idx++) {
@@ -28281,8 +28281,8 @@ static void wlc_phy_txpwrctrl_coeff_setup_nphy(phy_info_t *pi)
28281 (s8) ((locomp_q * nphy_tpc_loscale[idx] + 28281 (s8) ((locomp_q * nphy_tpc_loscale[idx] +
28282 128) >> 8); 28282 128) >> 8);
28283 } 28283 }
28284 curr_locomp = (uint32) ((curr_locomp_i & 0xff) << 8); 28284 curr_locomp = (u32) ((curr_locomp_i & 0xff) << 8);
28285 curr_locomp |= (uint32) (curr_locomp_q & 0xff); 28285 curr_locomp |= (u32) (curr_locomp_q & 0xff);
28286 regval[idx] = curr_locomp; 28286 regval[idx] = curr_locomp;
28287 } 28287 }
28288 wlc_phy_table_write_nphy(pi, tbl_id, tbl_len, tbl_offset, 32, 28288 wlc_phy_table_write_nphy(pi, tbl_id, tbl_len, tbl_offset, 32,
@@ -28477,14 +28477,14 @@ static void wlc_phy_txpwrctrl_idle_tssi_nphy(phy_info_t *pi)
28477 28477
28478static void wlc_phy_txpwrctrl_pwr_setup_nphy(phy_info_t *pi) 28478static void wlc_phy_txpwrctrl_pwr_setup_nphy(phy_info_t *pi)
28479{ 28479{
28480 uint32 idx; 28480 u32 idx;
28481 s16 a1[2], b0[2], b1[2]; 28481 s16 a1[2], b0[2], b1[2];
28482 s8 target_pwr_qtrdbm[2]; 28482 s8 target_pwr_qtrdbm[2];
28483 int32 num, den, pwr_est; 28483 int32 num, den, pwr_est;
28484 u8 chan_freq_range; 28484 u8 chan_freq_range;
28485 u8 idle_tssi[2]; 28485 u8 idle_tssi[2];
28486 uint32 tbl_id, tbl_len, tbl_offset; 28486 u32 tbl_id, tbl_len, tbl_offset;
28487 uint32 regval[64]; 28487 u32 regval[64];
28488 u8 core; 28488 u8 core;
28489 28489
28490 if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12)) { 28490 if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12)) {
@@ -28696,7 +28696,7 @@ static void wlc_phy_txpwrctrl_pwr_setup_nphy(phy_info_t *pi)
28696 target_pwr_qtrdbm[tbl_id - 26] + 28696 target_pwr_qtrdbm[tbl_id - 26] +
28697 1); 28697 1);
28698 } 28698 }
28699 regval[idx] = (uint32) pwr_est; 28699 regval[idx] = (u32) pwr_est;
28700 } 28700 }
28701 wlc_phy_table_write_nphy(pi, tbl_id, tbl_len, tbl_offset, 32, 28701 wlc_phy_table_write_nphy(pi, tbl_id, tbl_len, tbl_offset, 32,
28702 regval); 28702 regval);
@@ -28764,10 +28764,10 @@ void wlc_phy_txpwr_papd_cal_nphy(phy_info_t *pi)
28764 && (pi->nphy_force_papd_cal 28764 && (pi->nphy_force_papd_cal
28765 || (wlc_phy_txpwr_ison_nphy(pi) 28765 || (wlc_phy_txpwr_ison_nphy(pi)
28766 && 28766 &&
28767 (((uint32) 28767 (((u32)
28768 ABS(wlc_phy_txpwr_idx_cur_get_nphy(pi, 0) - 28768 ABS(wlc_phy_txpwr_idx_cur_get_nphy(pi, 0) -
28769 pi->nphy_papd_tx_gain_at_last_cal[0]) >= 4) 28769 pi->nphy_papd_tx_gain_at_last_cal[0]) >= 4)
28770 || ((uint32) 28770 || ((u32)
28771 ABS(wlc_phy_txpwr_idx_cur_get_nphy(pi, 1) - 28771 ABS(wlc_phy_txpwr_idx_cur_get_nphy(pi, 1) -
28772 pi->nphy_papd_tx_gain_at_last_cal[1]) >= 4))))) { 28772 pi->nphy_papd_tx_gain_at_last_cal[1]) >= 4))))) {
28773 wlc_phy_a4(pi, TRUE); 28773 wlc_phy_a4(pi, TRUE);
@@ -28779,8 +28779,8 @@ void wlc_phy_txpwrctrl_enable_nphy(phy_info_t *pi, u8 ctrl_type)
28779 u16 mask = 0, val = 0, ishw = 0; 28779 u16 mask = 0, val = 0, ishw = 0;
28780 u8 ctr; 28780 u8 ctr;
28781 uint core; 28781 uint core;
28782 uint32 tbl_offset; 28782 u32 tbl_offset;
28783 uint32 tbl_len; 28783 u32 tbl_len;
28784 u16 regval[84]; 28784 u16 regval[84];
28785 28785
28786 if (pi->phyhang_avoid) 28786 if (pi->phyhang_avoid)
@@ -28926,12 +28926,12 @@ wlc_phy_txpwr_index_nphy(phy_info_t *pi, u8 core_mask, s8 txpwrindex,
28926 u8 core, txpwrctl_tbl; 28926 u8 core, txpwrctl_tbl;
28927 u16 tx_ind0, iq_ind0, lo_ind0; 28927 u16 tx_ind0, iq_ind0, lo_ind0;
28928 u16 m1m2; 28928 u16 m1m2;
28929 uint32 txgain; 28929 u32 txgain;
28930 u16 rad_gain, dac_gain; 28930 u16 rad_gain, dac_gain;
28931 u8 bbmult; 28931 u8 bbmult;
28932 uint32 iqcomp; 28932 u32 iqcomp;
28933 u16 iqcomp_a, iqcomp_b; 28933 u16 iqcomp_a, iqcomp_b;
28934 uint32 locomp; 28934 u32 locomp;
28935 u16 tmpval; 28935 u16 tmpval;
28936 u8 tx_pwr_ctrl_state; 28936 u8 tx_pwr_ctrl_state;
28937 int32 rfpwr_offset; 28937 int32 rfpwr_offset;
diff --git a/drivers/staging/brcm80211/phy/wlc_phytbl_lcn.c b/drivers/staging/brcm80211/phy/wlc_phytbl_lcn.c
index 970a00cfe4f..e3d6dd18379 100644
--- a/drivers/staging/brcm80211/phy/wlc_phytbl_lcn.c
+++ b/drivers/staging/brcm80211/phy/wlc_phytbl_lcn.c
@@ -19,7 +19,7 @@
19#include <wlc_phy_int.h> 19#include <wlc_phy_int.h>
20#include <wlc_phytbl_lcn.h> 20#include <wlc_phytbl_lcn.h>
21 21
22const uint32 dot11lcn_gain_tbl_rev0[] = { 22const u32 dot11lcn_gain_tbl_rev0[] = {
23 0x00000000, 23 0x00000000,
24 0x00000000, 24 0x00000000,
25 0x00000000, 25 0x00000000,
@@ -118,7 +118,7 @@ const uint32 dot11lcn_gain_tbl_rev0[] = {
118 0x00000000, 118 0x00000000,
119}; 119};
120 120
121const uint32 dot11lcn_gain_tbl_rev1[] = { 121const u32 dot11lcn_gain_tbl_rev1[] = {
122 0x00000000, 122 0x00000000,
123 0x00000000, 123 0x00000000,
124 0x00000000, 124 0x00000000,
@@ -258,7 +258,7 @@ const u16 dot11lcn_aux_gain_idx_tbl_rev0[] = {
258 0x0000, 258 0x0000,
259}; 259};
260 260
261const uint32 dot11lcn_gain_idx_tbl_rev0[] = { 261const u32 dot11lcn_gain_idx_tbl_rev0[] = {
262 0x00000000, 262 0x00000000,
263 0x00000000, 263 0x00000000,
264 0x10000000, 264 0x10000000,
@@ -521,7 +521,7 @@ const u8 dot11lcn_gain_val_tbl_2G[] = {
521 0x00 521 0x00
522}; 522};
523 523
524const uint32 dot11lcn_gain_idx_tbl_2G[] = { 524const u32 dot11lcn_gain_idx_tbl_2G[] = {
525 0x00000000, 525 0x00000000,
526 0x00000000, 526 0x00000000,
527 0x00000000, 527 0x00000000,
@@ -676,7 +676,7 @@ const uint32 dot11lcn_gain_idx_tbl_2G[] = {
676 0x00000000 676 0x00000000
677}; 677};
678 678
679const uint32 dot11lcn_gain_tbl_2G[] = { 679const u32 dot11lcn_gain_tbl_2G[] = {
680 0x00000000, 680 0x00000000,
681 0x00000004, 681 0x00000004,
682 0x00000008, 682 0x00000008,
@@ -775,7 +775,7 @@ const uint32 dot11lcn_gain_tbl_2G[] = {
775 0x00000000 775 0x00000000
776}; 776};
777 777
778const uint32 dot11lcn_gain_tbl_extlna_2G[] = { 778const u32 dot11lcn_gain_tbl_extlna_2G[] = {
779 0x00000000, 779 0x00000000,
780 0x00000004, 780 0x00000004,
781 0x00000008, 781 0x00000008,
@@ -986,7 +986,7 @@ const u8 dot11lcn_gain_val_tbl_extlna_2G[] = {
986 0x00 986 0x00
987}; 987};
988 988
989const uint32 dot11lcn_gain_idx_tbl_extlna_2G[] = { 989const u32 dot11lcn_gain_idx_tbl_extlna_2G[] = {
990 0x00000000, 990 0x00000000,
991 0x00000040, 991 0x00000040,
992 0x00000000, 992 0x00000000,
@@ -1141,7 +1141,7 @@ const uint32 dot11lcn_gain_idx_tbl_extlna_2G[] = {
1141 0x00000000 1141 0x00000000
1142}; 1142};
1143 1143
1144const uint32 dot11lcn_aux_gain_idx_tbl_5G[] = { 1144const u32 dot11lcn_aux_gain_idx_tbl_5G[] = {
1145 0x0000, 1145 0x0000,
1146 0x0000, 1146 0x0000,
1147 0x0000, 1147 0x0000,
@@ -1182,7 +1182,7 @@ const uint32 dot11lcn_aux_gain_idx_tbl_5G[] = {
1182 0x0000 1182 0x0000
1183}; 1183};
1184 1184
1185const uint32 dot11lcn_gain_val_tbl_5G[] = { 1185const u32 dot11lcn_gain_val_tbl_5G[] = {
1186 0xf7, 1186 0xf7,
1187 0xfd, 1187 0xfd,
1188 0x00, 1188 0x00,
@@ -1253,7 +1253,7 @@ const uint32 dot11lcn_gain_val_tbl_5G[] = {
1253 0x00 1253 0x00
1254}; 1254};
1255 1255
1256const uint32 dot11lcn_gain_idx_tbl_5G[] = { 1256const u32 dot11lcn_gain_idx_tbl_5G[] = {
1257 0x00000000, 1257 0x00000000,
1258 0x00000000, 1258 0x00000000,
1259 0x00000000, 1259 0x00000000,
@@ -1408,7 +1408,7 @@ const uint32 dot11lcn_gain_idx_tbl_5G[] = {
1408 0x00000000 1408 0x00000000
1409}; 1409};
1410 1410
1411const uint32 dot11lcn_gain_tbl_5G[] = { 1411const u32 dot11lcn_gain_tbl_5G[] = {
1412 0x00000000, 1412 0x00000000,
1413 0x00000040, 1413 0x00000040,
1414 0x00000080, 1414 0x00000080,
@@ -1609,19 +1609,19 @@ const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_extlna_5G_rev2[] = {
1609 17, 0, 8} 1609 17, 0, 8}
1610}; 1610};
1611 1611
1612const uint32 dot11lcnphytbl_rx_gain_info_sz_rev0 = 1612const u32 dot11lcnphytbl_rx_gain_info_sz_rev0 =
1613 sizeof(dot11lcnphytbl_rx_gain_info_rev0) / 1613 sizeof(dot11lcnphytbl_rx_gain_info_rev0) /
1614 sizeof(dot11lcnphytbl_rx_gain_info_rev0[0]); 1614 sizeof(dot11lcnphytbl_rx_gain_info_rev0[0]);
1615 1615
1616const uint32 dot11lcnphytbl_rx_gain_info_sz_rev1 = 1616const u32 dot11lcnphytbl_rx_gain_info_sz_rev1 =
1617 sizeof(dot11lcnphytbl_rx_gain_info_rev1) / 1617 sizeof(dot11lcnphytbl_rx_gain_info_rev1) /
1618 sizeof(dot11lcnphytbl_rx_gain_info_rev1[0]); 1618 sizeof(dot11lcnphytbl_rx_gain_info_rev1[0]);
1619 1619
1620const uint32 dot11lcnphytbl_rx_gain_info_2G_rev2_sz = 1620const u32 dot11lcnphytbl_rx_gain_info_2G_rev2_sz =
1621 sizeof(dot11lcnphytbl_rx_gain_info_2G_rev2) / 1621 sizeof(dot11lcnphytbl_rx_gain_info_2G_rev2) /
1622 sizeof(dot11lcnphytbl_rx_gain_info_2G_rev2[0]); 1622 sizeof(dot11lcnphytbl_rx_gain_info_2G_rev2[0]);
1623 1623
1624const uint32 dot11lcnphytbl_rx_gain_info_5G_rev2_sz = 1624const u32 dot11lcnphytbl_rx_gain_info_5G_rev2_sz =
1625 sizeof(dot11lcnphytbl_rx_gain_info_5G_rev2) / 1625 sizeof(dot11lcnphytbl_rx_gain_info_5G_rev2) /
1626 sizeof(dot11lcnphytbl_rx_gain_info_5G_rev2[0]); 1626 sizeof(dot11lcnphytbl_rx_gain_info_5G_rev2[0]);
1627 1627
@@ -1759,7 +1759,7 @@ const u16 dot11lcn_noise_scale_tbl_rev0[] = {
1759 0x0000, 1759 0x0000,
1760}; 1760};
1761 1761
1762const uint32 dot11lcn_fltr_ctrl_tbl_rev0[] = { 1762const u32 dot11lcn_fltr_ctrl_tbl_rev0[] = {
1763 0x000141f8, 1763 0x000141f8,
1764 0x000021f8, 1764 0x000021f8,
1765 0x000021fb, 1765 0x000021fb,
@@ -1772,7 +1772,7 @@ const uint32 dot11lcn_fltr_ctrl_tbl_rev0[] = {
1772 0x0000024b, 1772 0x0000024b,
1773}; 1773};
1774 1774
1775const uint32 dot11lcn_ps_ctrl_tbl_rev0[] = { 1775const u32 dot11lcn_ps_ctrl_tbl_rev0[] = {
1776 0x00100001, 1776 0x00100001,
1777 0x00200010, 1777 0x00200010,
1778 0x00300001, 1778 0x00300001,
@@ -2612,7 +2612,7 @@ const u16 dot11lcn_iq_local_tbl_rev0[] = {
2612 0x0000, 2612 0x0000,
2613}; 2613};
2614 2614
2615const uint32 dot11lcn_papd_compdelta_tbl_rev0[] = { 2615const u32 dot11lcn_papd_compdelta_tbl_rev0[] = {
2616 0x00080000, 2616 0x00080000,
2617 0x00080000, 2617 0x00080000,
2618 0x00080000, 2618 0x00080000,
@@ -2858,7 +2858,7 @@ const dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313_bt_epa_p250 = {
2858 sizeof(dot11lcn_sw_ctrl_tbl_4313_bt_epa_p250_rev0[0]), 15, 0, 16 2858 sizeof(dot11lcn_sw_ctrl_tbl_4313_bt_epa_p250_rev0[0]), 15, 0, 16
2859}; 2859};
2860 2860
2861const uint32 dot11lcnphytbl_info_sz_rev0 = 2861const u32 dot11lcnphytbl_info_sz_rev0 =
2862 sizeof(dot11lcnphytbl_info_rev0) / sizeof(dot11lcnphytbl_info_rev0[0]); 2862 sizeof(dot11lcnphytbl_info_rev0) / sizeof(dot11lcnphytbl_info_rev0[0]);
2863 2863
2864const lcnphy_tx_gain_tbl_entry dot11lcnphy_2GHz_extPA_gaintable_rev0[128] = { 2864const lcnphy_tx_gain_tbl_entry dot11lcnphy_2GHz_extPA_gaintable_rev0[128] = {
diff --git a/drivers/staging/brcm80211/phy/wlc_phytbl_lcn.h b/drivers/staging/brcm80211/phy/wlc_phytbl_lcn.h
index 49bb00a7834..5a64a988d10 100644
--- a/drivers/staging/brcm80211/phy/wlc_phytbl_lcn.h
+++ b/drivers/staging/brcm80211/phy/wlc_phytbl_lcn.h
@@ -17,19 +17,19 @@
17typedef phytbl_info_t dot11lcnphytbl_info_t; 17typedef phytbl_info_t dot11lcnphytbl_info_t;
18 18
19extern const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_rev0[]; 19extern const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_rev0[];
20extern const uint32 dot11lcnphytbl_rx_gain_info_sz_rev0; 20extern const u32 dot11lcnphytbl_rx_gain_info_sz_rev0;
21extern const dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313; 21extern const dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313;
22extern const dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313_epa; 22extern const dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313_epa;
23extern const dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313_epa_combo; 23extern const dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313_epa_combo;
24 24
25extern const dot11lcnphytbl_info_t dot11lcnphytbl_info_rev0[]; 25extern const dot11lcnphytbl_info_t dot11lcnphytbl_info_rev0[];
26extern const uint32 dot11lcnphytbl_info_sz_rev0; 26extern const u32 dot11lcnphytbl_info_sz_rev0;
27 27
28extern const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_2G_rev2[]; 28extern const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_2G_rev2[];
29extern const uint32 dot11lcnphytbl_rx_gain_info_2G_rev2_sz; 29extern const u32 dot11lcnphytbl_rx_gain_info_2G_rev2_sz;
30 30
31extern const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_5G_rev2[]; 31extern const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_5G_rev2[];
32extern const uint32 dot11lcnphytbl_rx_gain_info_5G_rev2_sz; 32extern const u32 dot11lcnphytbl_rx_gain_info_5G_rev2_sz;
33 33
34extern const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_extlna_2G_rev2[]; 34extern const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_extlna_2G_rev2[];
35 35
diff --git a/drivers/staging/brcm80211/phy/wlc_phytbl_n.c b/drivers/staging/brcm80211/phy/wlc_phytbl_n.c
index 303b4acc2de..bbc4cfae73e 100644
--- a/drivers/staging/brcm80211/phy/wlc_phytbl_n.c
+++ b/drivers/staging/brcm80211/phy/wlc_phytbl_n.c
@@ -19,7 +19,7 @@
19#include <wlc_phy_int.h> 19#include <wlc_phy_int.h>
20#include <wlc_phytbl_n.h> 20#include <wlc_phytbl_n.h>
21 21
22const uint32 frame_struct_rev0[] = { 22const u32 frame_struct_rev0[] = {
23 0x08004a04, 23 0x08004a04,
24 0x00100000, 24 0x00100000,
25 0x01000a05, 25 0x01000a05,
@@ -889,7 +889,7 @@ const u8 frame_lut_rev0[] = {
889 0x2a, 889 0x2a,
890}; 890};
891 891
892const uint32 tmap_tbl_rev0[] = { 892const u32 tmap_tbl_rev0[] = {
893 0x8a88aa80, 893 0x8a88aa80,
894 0x8aaaaa8a, 894 0x8aaaaa8a,
895 0x8a8a8aa8, 895 0x8a8a8aa8,
@@ -1340,7 +1340,7 @@ const uint32 tmap_tbl_rev0[] = {
1340 0x00000000, 1340 0x00000000,
1341}; 1341};
1342 1342
1343const uint32 tdtrn_tbl_rev0[] = { 1343const u32 tdtrn_tbl_rev0[] = {
1344 0x061c061c, 1344 0x061c061c,
1345 0x0050ee68, 1345 0x0050ee68,
1346 0xf592fe36, 1346 0xf592fe36,
@@ -2047,7 +2047,7 @@ const uint32 tdtrn_tbl_rev0[] = {
2047 0x00f006be, 2047 0x00f006be,
2048}; 2048};
2049 2049
2050const uint32 intlv_tbl_rev0[] = { 2050const u32 intlv_tbl_rev0[] = {
2051 0x00802070, 2051 0x00802070,
2052 0x0671188d, 2052 0x0671188d,
2053 0x0a60192c, 2053 0x0a60192c,
@@ -2148,7 +2148,7 @@ const u16 pilot_tbl_rev0[] = {
2148 0xffff, 2148 0xffff,
2149}; 2149};
2150 2150
2151const uint32 pltlut_tbl_rev0[] = { 2151const u32 pltlut_tbl_rev0[] = {
2152 0x76540123, 2152 0x76540123,
2153 0x62407351, 2153 0x62407351,
2154 0x76543201, 2154 0x76543201,
@@ -2157,7 +2157,7 @@ const uint32 pltlut_tbl_rev0[] = {
2157 0x76430521, 2157 0x76430521,
2158}; 2158};
2159 2159
2160const uint32 tdi_tbl20_ant0_rev0[] = { 2160const u32 tdi_tbl20_ant0_rev0[] = {
2161 0x00091226, 2161 0x00091226,
2162 0x000a1429, 2162 0x000a1429,
2163 0x000b56ad, 2163 0x000b56ad,
@@ -2215,7 +2215,7 @@ const uint32 tdi_tbl20_ant0_rev0[] = {
2215 0x00000000, 2215 0x00000000,
2216}; 2216};
2217 2217
2218const uint32 tdi_tbl20_ant1_rev0[] = { 2218const u32 tdi_tbl20_ant1_rev0[] = {
2219 0x00014b26, 2219 0x00014b26,
2220 0x00028d29, 2220 0x00028d29,
2221 0x000393ad, 2221 0x000393ad,
@@ -2273,7 +2273,7 @@ const uint32 tdi_tbl20_ant1_rev0[] = {
2273 0x00000000, 2273 0x00000000,
2274}; 2274};
2275 2275
2276const uint32 tdi_tbl40_ant0_rev0[] = { 2276const u32 tdi_tbl40_ant0_rev0[] = {
2277 0x0011a346, 2277 0x0011a346,
2278 0x00136ccf, 2278 0x00136ccf,
2279 0x0014f5d9, 2279 0x0014f5d9,
@@ -2386,7 +2386,7 @@ const uint32 tdi_tbl40_ant0_rev0[] = {
2386 0x00000000, 2386 0x00000000,
2387}; 2387};
2388 2388
2389const uint32 tdi_tbl40_ant1_rev0[] = { 2389const u32 tdi_tbl40_ant1_rev0[] = {
2390 0x001edb36, 2390 0x001edb36,
2391 0x000129ca, 2391 0x000129ca,
2392 0x0002b353, 2392 0x0002b353,
@@ -2508,7 +2508,7 @@ const u16 bdi_tbl_rev0[] = {
2508 0x04d2, 2508 0x04d2,
2509}; 2509};
2510 2510
2511const uint32 chanest_tbl_rev0[] = { 2511const u32 chanest_tbl_rev0[] = {
2512 0x44444444, 2512 0x44444444,
2513 0x44444444, 2513 0x44444444,
2514 0x44444444, 2514 0x44444444,
@@ -2738,7 +2738,7 @@ const u8 mcs_tbl_rev0[] = {
2738 0x00, 2738 0x00,
2739}; 2739};
2740 2740
2741const uint32 noise_var_tbl0_rev0[] = { 2741const u32 noise_var_tbl0_rev0[] = {
2742 0x020c020c, 2742 0x020c020c,
2743 0x0000014d, 2743 0x0000014d,
2744 0x020c020c, 2744 0x020c020c,
@@ -2997,7 +2997,7 @@ const uint32 noise_var_tbl0_rev0[] = {
2997 0x0000014d, 2997 0x0000014d,
2998}; 2998};
2999 2999
3000const uint32 noise_var_tbl1_rev0[] = { 3000const u32 noise_var_tbl1_rev0[] = {
3001 0x020c020c, 3001 0x020c020c,
3002 0x0000014d, 3002 0x0000014d,
3003 0x020c020c, 3003 0x020c020c,
@@ -3652,7 +3652,7 @@ const u8 adj_pwr_lut_core1_rev0[] = {
3652 0x00, 3652 0x00,
3653}; 3653};
3654 3654
3655const uint32 gainctrl_lut_core0_rev0[] = { 3655const u32 gainctrl_lut_core0_rev0[] = {
3656 0x03cc2b44, 3656 0x03cc2b44,
3657 0x03cc2b42, 3657 0x03cc2b42,
3658 0x03cc2b40, 3658 0x03cc2b40,
@@ -3783,7 +3783,7 @@ const uint32 gainctrl_lut_core0_rev0[] = {
3783 0x00002b00, 3783 0x00002b00,
3784}; 3784};
3785 3785
3786const uint32 gainctrl_lut_core1_rev0[] = { 3786const u32 gainctrl_lut_core1_rev0[] = {
3787 0x03cc2b44, 3787 0x03cc2b44,
3788 0x03cc2b42, 3788 0x03cc2b42,
3789 0x03cc2b40, 3789 0x03cc2b40,
@@ -3914,7 +3914,7 @@ const uint32 gainctrl_lut_core1_rev0[] = {
3914 0x00002b00, 3914 0x00002b00,
3915}; 3915};
3916 3916
3917const uint32 iq_lut_core0_rev0[] = { 3917const u32 iq_lut_core0_rev0[] = {
3918 0x0000007f, 3918 0x0000007f,
3919 0x0000007f, 3919 0x0000007f,
3920 0x0000007f, 3920 0x0000007f,
@@ -4045,7 +4045,7 @@ const uint32 iq_lut_core0_rev0[] = {
4045 0x0000007f, 4045 0x0000007f,
4046}; 4046};
4047 4047
4048const uint32 iq_lut_core1_rev0[] = { 4048const u32 iq_lut_core1_rev0[] = {
4049 0x0000007f, 4049 0x0000007f,
4050 0x0000007f, 4050 0x0000007f,
4051 0x0000007f, 4051 0x0000007f,
@@ -4536,9 +4536,9 @@ const mimophytbl_info_t mimophytbl_info_rev0[] = {
4536 , 4536 ,
4537}; 4537};
4538 4538
4539const uint32 mimophytbl_info_sz_rev0 = 4539const u32 mimophytbl_info_sz_rev0 =
4540 sizeof(mimophytbl_info_rev0) / sizeof(mimophytbl_info_rev0[0]); 4540 sizeof(mimophytbl_info_rev0) / sizeof(mimophytbl_info_rev0[0]);
4541const uint32 mimophytbl_info_sz_rev0_volatile = 4541const u32 mimophytbl_info_sz_rev0_volatile =
4542 sizeof(mimophytbl_info_rev0_volatile) / 4542 sizeof(mimophytbl_info_rev0_volatile) /
4543 sizeof(mimophytbl_info_rev0_volatile[0]); 4543 sizeof(mimophytbl_info_rev0_volatile[0]);
4544 4544
@@ -4682,7 +4682,7 @@ const u16 ant_swctrl_tbl_rev3_3[] = {
4682 0x3cc 4682 0x3cc
4683}; 4683};
4684 4684
4685const uint32 frame_struct_rev3[] = { 4685const u32 frame_struct_rev3[] = {
4686 0x08004a04, 4686 0x08004a04,
4687 0x00100000, 4687 0x00100000,
4688 0x01000a05, 4688 0x01000a05,
@@ -5608,7 +5608,7 @@ const u16 pilot_tbl_rev3[] = {
5608 0xffff, 5608 0xffff,
5609}; 5609};
5610 5610
5611const uint32 tmap_tbl_rev3[] = { 5611const u32 tmap_tbl_rev3[] = {
5612 0x8a88aa80, 5612 0x8a88aa80,
5613 0x8aaaaa8a, 5613 0x8aaaaa8a,
5614 0x8a8a8aa8, 5614 0x8a8a8aa8,
@@ -6059,7 +6059,7 @@ const uint32 tmap_tbl_rev3[] = {
6059 0x00000000, 6059 0x00000000,
6060}; 6060};
6061 6061
6062const uint32 intlv_tbl_rev3[] = { 6062const u32 intlv_tbl_rev3[] = {
6063 0x00802070, 6063 0x00802070,
6064 0x0671188d, 6064 0x0671188d,
6065 0x0a60192c, 6065 0x0a60192c,
@@ -6069,7 +6069,7 @@ const uint32 intlv_tbl_rev3[] = {
6069 0x00000070, 6069 0x00000070,
6070}; 6070};
6071 6071
6072const uint32 tdtrn_tbl_rev3[] = { 6072const u32 tdtrn_tbl_rev3[] = {
6073 0x061c061c, 6073 0x061c061c,
6074 0x0050ee68, 6074 0x0050ee68,
6075 0xf592fe36, 6075 0xf592fe36,
@@ -6776,7 +6776,7 @@ const uint32 tdtrn_tbl_rev3[] = {
6776 0x00f006be, 6776 0x00f006be,
6777}; 6777};
6778 6778
6779const uint32 noise_var_tbl_rev3[] = { 6779const u32 noise_var_tbl_rev3[] = {
6780 0x02110211, 6780 0x02110211,
6781 0x0000014d, 6781 0x0000014d,
6782 0x02110211, 6782 0x02110211,
@@ -7166,7 +7166,7 @@ const u16 mcs_tbl_rev3[] = {
7166 0x0007, 7166 0x0007,
7167}; 7167};
7168 7168
7169const uint32 tdi_tbl20_ant0_rev3[] = { 7169const u32 tdi_tbl20_ant0_rev3[] = {
7170 0x00091226, 7170 0x00091226,
7171 0x000a1429, 7171 0x000a1429,
7172 0x000b56ad, 7172 0x000b56ad,
@@ -7224,7 +7224,7 @@ const uint32 tdi_tbl20_ant0_rev3[] = {
7224 0x00000000, 7224 0x00000000,
7225}; 7225};
7226 7226
7227const uint32 tdi_tbl20_ant1_rev3[] = { 7227const u32 tdi_tbl20_ant1_rev3[] = {
7228 0x00014b26, 7228 0x00014b26,
7229 0x00028d29, 7229 0x00028d29,
7230 0x000393ad, 7230 0x000393ad,
@@ -7282,7 +7282,7 @@ const uint32 tdi_tbl20_ant1_rev3[] = {
7282 0x00000000, 7282 0x00000000,
7283}; 7283};
7284 7284
7285const uint32 tdi_tbl40_ant0_rev3[] = { 7285const u32 tdi_tbl40_ant0_rev3[] = {
7286 0x0011a346, 7286 0x0011a346,
7287 0x00136ccf, 7287 0x00136ccf,
7288 0x0014f5d9, 7288 0x0014f5d9,
@@ -7395,7 +7395,7 @@ const uint32 tdi_tbl40_ant0_rev3[] = {
7395 0x00000000, 7395 0x00000000,
7396}; 7396};
7397 7397
7398const uint32 tdi_tbl40_ant1_rev3[] = { 7398const u32 tdi_tbl40_ant1_rev3[] = {
7399 0x001edb36, 7399 0x001edb36,
7400 0x000129ca, 7400 0x000129ca,
7401 0x0002b353, 7401 0x0002b353,
@@ -7508,7 +7508,7 @@ const uint32 tdi_tbl40_ant1_rev3[] = {
7508 0x00000000, 7508 0x00000000,
7509}; 7509};
7510 7510
7511const uint32 pltlut_tbl_rev3[] = { 7511const u32 pltlut_tbl_rev3[] = {
7512 0x76540213, 7512 0x76540213,
7513 0x62407351, 7513 0x62407351,
7514 0x76543210, 7514 0x76543210,
@@ -7517,7 +7517,7 @@ const uint32 pltlut_tbl_rev3[] = {
7517 0x76430521, 7517 0x76430521,
7518}; 7518};
7519 7519
7520const uint32 chanest_tbl_rev3[] = { 7520const u32 chanest_tbl_rev3[] = {
7521 0x44444444, 7521 0x44444444,
7522 0x44444444, 7522 0x44444444,
7523 0x44444444, 7523 0x44444444,
@@ -8047,7 +8047,7 @@ const u8 adj_pwr_lut_core1_rev3[] = {
8047 0x00, 8047 0x00,
8048}; 8048};
8049 8049
8050const uint32 gainctrl_lut_core0_rev3[] = { 8050const u32 gainctrl_lut_core0_rev3[] = {
8051 0x5bf70044, 8051 0x5bf70044,
8052 0x5bf70042, 8052 0x5bf70042,
8053 0x5bf70040, 8053 0x5bf70040,
@@ -8178,7 +8178,7 @@ const uint32 gainctrl_lut_core0_rev3[] = {
8178 0x5b07001c, 8178 0x5b07001c,
8179}; 8179};
8180 8180
8181const uint32 gainctrl_lut_core1_rev3[] = { 8181const u32 gainctrl_lut_core1_rev3[] = {
8182 0x5bf70044, 8182 0x5bf70044,
8183 0x5bf70042, 8183 0x5bf70042,
8184 0x5bf70040, 8184 0x5bf70040,
@@ -8309,7 +8309,7 @@ const uint32 gainctrl_lut_core1_rev3[] = {
8309 0x5b07001c, 8309 0x5b07001c,
8310}; 8310};
8311 8311
8312const uint32 iq_lut_core0_rev3[] = { 8312const u32 iq_lut_core0_rev3[] = {
8313 0x00000000, 8313 0x00000000,
8314 0x00000000, 8314 0x00000000,
8315 0x00000000, 8315 0x00000000,
@@ -8440,7 +8440,7 @@ const uint32 iq_lut_core0_rev3[] = {
8440 0x00000000, 8440 0x00000000,
8441}; 8441};
8442 8442
8443const uint32 iq_lut_core1_rev3[] = { 8443const u32 iq_lut_core1_rev3[] = {
8444 0x00000000, 8444 0x00000000,
8445 0x00000000, 8445 0x00000000,
8446 0x00000000, 8446 0x00000000,
@@ -9095,7 +9095,7 @@ const u16 papd_comp_rfpwr_tbl_core1_rev3[] = {
9095 0x01d6, 9095 0x01d6,
9096}; 9096};
9097 9097
9098const uint32 papd_comp_epsilon_tbl_core0_rev3[] = { 9098const u32 papd_comp_epsilon_tbl_core0_rev3[] = {
9099 0x00000000, 9099 0x00000000,
9100 0x00001fa0, 9100 0x00001fa0,
9101 0x00019f78, 9101 0x00019f78,
@@ -9162,7 +9162,7 @@ const uint32 papd_comp_epsilon_tbl_core0_rev3[] = {
9162 0x03e38ffe, 9162 0x03e38ffe,
9163}; 9163};
9164 9164
9165const uint32 papd_cal_scalars_tbl_core0_rev3[] = { 9165const u32 papd_cal_scalars_tbl_core0_rev3[] = {
9166 0x05af005a, 9166 0x05af005a,
9167 0x0571005e, 9167 0x0571005e,
9168 0x05040066, 9168 0x05040066,
@@ -9229,7 +9229,7 @@ const uint32 papd_cal_scalars_tbl_core0_rev3[] = {
9229 0x002606a4, 9229 0x002606a4,
9230}; 9230};
9231 9231
9232const uint32 papd_comp_epsilon_tbl_core1_rev3[] = { 9232const u32 papd_comp_epsilon_tbl_core1_rev3[] = {
9233 0x00000000, 9233 0x00000000,
9234 0x00001fa0, 9234 0x00001fa0,
9235 0x00019f78, 9235 0x00019f78,
@@ -9296,7 +9296,7 @@ const uint32 papd_comp_epsilon_tbl_core1_rev3[] = {
9296 0x03e38ffe, 9296 0x03e38ffe,
9297}; 9297};
9298 9298
9299const uint32 papd_cal_scalars_tbl_core1_rev3[] = { 9299const u32 papd_cal_scalars_tbl_core1_rev3[] = {
9300 0x05af005a, 9300 0x05af005a,
9301 0x0571005e, 9301 0x0571005e,
9302 0x05040066, 9302 0x05040066,
@@ -9476,22 +9476,22 @@ const mimophytbl_info_t mimophytbl_info_rev3[] = {
9476 16} 9476 16}
9477}; 9477};
9478 9478
9479const uint32 mimophytbl_info_sz_rev3 = 9479const u32 mimophytbl_info_sz_rev3 =
9480 sizeof(mimophytbl_info_rev3) / sizeof(mimophytbl_info_rev3[0]); 9480 sizeof(mimophytbl_info_rev3) / sizeof(mimophytbl_info_rev3[0]);
9481const uint32 mimophytbl_info_sz_rev3_volatile = 9481const u32 mimophytbl_info_sz_rev3_volatile =
9482 sizeof(mimophytbl_info_rev3_volatile) / 9482 sizeof(mimophytbl_info_rev3_volatile) /
9483 sizeof(mimophytbl_info_rev3_volatile[0]); 9483 sizeof(mimophytbl_info_rev3_volatile[0]);
9484const uint32 mimophytbl_info_sz_rev3_volatile1 = 9484const u32 mimophytbl_info_sz_rev3_volatile1 =
9485 sizeof(mimophytbl_info_rev3_volatile1) / 9485 sizeof(mimophytbl_info_rev3_volatile1) /
9486 sizeof(mimophytbl_info_rev3_volatile1[0]); 9486 sizeof(mimophytbl_info_rev3_volatile1[0]);
9487const uint32 mimophytbl_info_sz_rev3_volatile2 = 9487const u32 mimophytbl_info_sz_rev3_volatile2 =
9488 sizeof(mimophytbl_info_rev3_volatile2) / 9488 sizeof(mimophytbl_info_rev3_volatile2) /
9489 sizeof(mimophytbl_info_rev3_volatile2[0]); 9489 sizeof(mimophytbl_info_rev3_volatile2[0]);
9490const uint32 mimophytbl_info_sz_rev3_volatile3 = 9490const u32 mimophytbl_info_sz_rev3_volatile3 =
9491 sizeof(mimophytbl_info_rev3_volatile3) / 9491 sizeof(mimophytbl_info_rev3_volatile3) /
9492 sizeof(mimophytbl_info_rev3_volatile3[0]); 9492 sizeof(mimophytbl_info_rev3_volatile3[0]);
9493 9493
9494const uint32 tmap_tbl_rev7[] = { 9494const u32 tmap_tbl_rev7[] = {
9495 0x8a88aa80, 9495 0x8a88aa80,
9496 0x8aaaaa8a, 9496 0x8aaaaa8a,
9497 0x8a8a8aa8, 9497 0x8a8a8aa8,
@@ -9942,7 +9942,7 @@ const uint32 tmap_tbl_rev7[] = {
9942 0x00000000, 9942 0x00000000,
9943}; 9943};
9944 9944
9945const uint32 noise_var_tbl_rev7[] = { 9945const u32 noise_var_tbl_rev7[] = {
9946 0x020c020c, 9946 0x020c020c,
9947 0x0000014d, 9947 0x0000014d,
9948 0x020c020c, 9948 0x020c020c,
@@ -10201,7 +10201,7 @@ const uint32 noise_var_tbl_rev7[] = {
10201 0x0000014d, 10201 0x0000014d,
10202}; 10202};
10203 10203
10204const uint32 papd_comp_epsilon_tbl_core0_rev7[] = { 10204const u32 papd_comp_epsilon_tbl_core0_rev7[] = {
10205 0x00000000, 10205 0x00000000,
10206 0x00000000, 10206 0x00000000,
10207 0x00016023, 10207 0x00016023,
@@ -10268,7 +10268,7 @@ const uint32 papd_comp_epsilon_tbl_core0_rev7[] = {
10268 0x0156cfff, 10268 0x0156cfff,
10269}; 10269};
10270 10270
10271const uint32 papd_cal_scalars_tbl_core0_rev7[] = { 10271const u32 papd_cal_scalars_tbl_core0_rev7[] = {
10272 0x0b5e002d, 10272 0x0b5e002d,
10273 0x0ae2002f, 10273 0x0ae2002f,
10274 0x0a3b0032, 10274 0x0a3b0032,
@@ -10335,7 +10335,7 @@ const uint32 papd_cal_scalars_tbl_core0_rev7[] = {
10335 0x004e068c, 10335 0x004e068c,
10336}; 10336};
10337 10337
10338const uint32 papd_comp_epsilon_tbl_core1_rev7[] = { 10338const u32 papd_comp_epsilon_tbl_core1_rev7[] = {
10339 0x00000000, 10339 0x00000000,
10340 0x00000000, 10340 0x00000000,
10341 0x00016023, 10341 0x00016023,
@@ -10402,7 +10402,7 @@ const uint32 papd_comp_epsilon_tbl_core1_rev7[] = {
10402 0x0156cfff, 10402 0x0156cfff,
10403}; 10403};
10404 10404
10405const uint32 papd_cal_scalars_tbl_core1_rev7[] = { 10405const u32 papd_cal_scalars_tbl_core1_rev7[] = {
10406 0x0b5e002d, 10406 0x0b5e002d,
10407 0x0ae2002f, 10407 0x0ae2002f,
10408 0x0a3b0032, 10408 0x0a3b0032,
@@ -10580,7 +10580,7 @@ const mimophytbl_info_t mimophytbl_info_rev7[] = {
10580 , 10580 ,
10581}; 10581};
10582 10582
10583const uint32 mimophytbl_info_sz_rev7 = 10583const u32 mimophytbl_info_sz_rev7 =
10584 sizeof(mimophytbl_info_rev7) / sizeof(mimophytbl_info_rev7[0]); 10584 sizeof(mimophytbl_info_rev7) / sizeof(mimophytbl_info_rev7[0]);
10585 10585
10586const mimophytbl_info_t mimophytbl_info_rev16[] = { 10586const mimophytbl_info_t mimophytbl_info_rev16[] = {
@@ -10627,5 +10627,5 @@ const mimophytbl_info_t mimophytbl_info_rev16[] = {
10627 , 10627 ,
10628}; 10628};
10629 10629
10630const uint32 mimophytbl_info_sz_rev16 = 10630const u32 mimophytbl_info_sz_rev16 =
10631 sizeof(mimophytbl_info_rev16) / sizeof(mimophytbl_info_rev16[0]); 10631 sizeof(mimophytbl_info_rev16) / sizeof(mimophytbl_info_rev16[0]);
diff --git a/drivers/staging/brcm80211/phy/wlc_phytbl_n.h b/drivers/staging/brcm80211/phy/wlc_phytbl_n.h
index 03c34d62c8e..396122f5e50 100644
--- a/drivers/staging/brcm80211/phy/wlc_phytbl_n.h
+++ b/drivers/staging/brcm80211/phy/wlc_phytbl_n.h
@@ -20,20 +20,20 @@ typedef phytbl_info_t mimophytbl_info_t;
20 20
21extern const mimophytbl_info_t mimophytbl_info_rev0[], 21extern const mimophytbl_info_t mimophytbl_info_rev0[],
22 mimophytbl_info_rev0_volatile[]; 22 mimophytbl_info_rev0_volatile[];
23extern const uint32 mimophytbl_info_sz_rev0, mimophytbl_info_sz_rev0_volatile; 23extern const u32 mimophytbl_info_sz_rev0, mimophytbl_info_sz_rev0_volatile;
24 24
25extern const mimophytbl_info_t mimophytbl_info_rev3[], 25extern const mimophytbl_info_t mimophytbl_info_rev3[],
26 mimophytbl_info_rev3_volatile[], mimophytbl_info_rev3_volatile1[], 26 mimophytbl_info_rev3_volatile[], mimophytbl_info_rev3_volatile1[],
27 mimophytbl_info_rev3_volatile2[], mimophytbl_info_rev3_volatile3[]; 27 mimophytbl_info_rev3_volatile2[], mimophytbl_info_rev3_volatile3[];
28extern const uint32 mimophytbl_info_sz_rev3, mimophytbl_info_sz_rev3_volatile, 28extern const u32 mimophytbl_info_sz_rev3, mimophytbl_info_sz_rev3_volatile,
29 mimophytbl_info_sz_rev3_volatile1, mimophytbl_info_sz_rev3_volatile2, 29 mimophytbl_info_sz_rev3_volatile1, mimophytbl_info_sz_rev3_volatile2,
30 mimophytbl_info_sz_rev3_volatile3; 30 mimophytbl_info_sz_rev3_volatile3;
31 31
32extern const uint32 noise_var_tbl_rev3[]; 32extern const u32 noise_var_tbl_rev3[];
33 33
34extern const mimophytbl_info_t mimophytbl_info_rev7[]; 34extern const mimophytbl_info_t mimophytbl_info_rev7[];
35extern const uint32 mimophytbl_info_sz_rev7; 35extern const u32 mimophytbl_info_sz_rev7;
36extern const uint32 noise_var_tbl_rev7[]; 36extern const u32 noise_var_tbl_rev7[];
37 37
38extern const mimophytbl_info_t mimophytbl_info_rev16[]; 38extern const mimophytbl_info_t mimophytbl_info_rev16[];
39extern const uint32 mimophytbl_info_sz_rev16; 39extern const u32 mimophytbl_info_sz_rev16;
diff --git a/drivers/staging/brcm80211/sys/wl_dbg.h b/drivers/staging/brcm80211/sys/wl_dbg.h
index d83244cae44..e63b27ebad5 100644
--- a/drivers/staging/brcm80211/sys/wl_dbg.h
+++ b/drivers/staging/brcm80211/sys/wl_dbg.h
@@ -18,7 +18,7 @@
18#define _wl_dbg_h_ 18#define _wl_dbg_h_
19 19
20/* wl_msg_level is a bit vector with defs in wlioctl.h */ 20/* wl_msg_level is a bit vector with defs in wlioctl.h */
21extern uint32 wl_msg_level; 21extern u32 wl_msg_level;
22 22
23#define WL_PRINT(args) printf args 23#define WL_PRINT(args) printf args
24#define WL_NONE(args) 24#define WL_NONE(args)
@@ -42,7 +42,7 @@ extern uint32 wl_msg_level;
42#define WL_AMPDU_HWTXS_VAL 0x00000040 /* AMPDU_HWTXS */ 42#define WL_AMPDU_HWTXS_VAL 0x00000040 /* AMPDU_HWTXS */
43#define WL_AMPDU_HWDBG_VAL 0x00000080 /* AMPDU_DBG */ 43#define WL_AMPDU_HWDBG_VAL 0x00000080 /* AMPDU_DBG */
44 44
45extern uint32 wl_ampdu_dbg; 45extern u32 wl_ampdu_dbg;
46 46
47#define WL_AMPDU_UPDN(args) do {if (wl_ampdu_dbg & WL_AMPDU_UPDN_VAL) {WL_AMPDU(args); } } while (0) 47#define WL_AMPDU_UPDN(args) do {if (wl_ampdu_dbg & WL_AMPDU_UPDN_VAL) {WL_AMPDU(args); } } while (0)
48#define WL_AMPDU_RX(args) do {if (wl_ampdu_dbg & WL_AMPDU_RX_VAL) {WL_AMPDU(args); } } while (0) 48#define WL_AMPDU_RX(args) do {if (wl_ampdu_dbg & WL_AMPDU_RX_VAL) {WL_AMPDU(args); } } while (0)
diff --git a/drivers/staging/brcm80211/sys/wl_export.h b/drivers/staging/brcm80211/sys/wl_export.h
index 836fb83f790..f382ee9b690 100644
--- a/drivers/staging/brcm80211/sys/wl_export.h
+++ b/drivers/staging/brcm80211/sys/wl_export.h
@@ -24,11 +24,11 @@ struct wlc_if;
24extern void wl_init(struct wl_info *wl); 24extern void wl_init(struct wl_info *wl);
25extern uint wl_reset(struct wl_info *wl); 25extern uint wl_reset(struct wl_info *wl);
26extern void wl_intrson(struct wl_info *wl); 26extern void wl_intrson(struct wl_info *wl);
27extern uint32 wl_intrsoff(struct wl_info *wl); 27extern u32 wl_intrsoff(struct wl_info *wl);
28extern void wl_intrsrestore(struct wl_info *wl, uint32 macintmask); 28extern void wl_intrsrestore(struct wl_info *wl, u32 macintmask);
29extern void wl_event(struct wl_info *wl, char *ifname, wlc_event_t *e); 29extern void wl_event(struct wl_info *wl, char *ifname, wlc_event_t *e);
30extern void wl_event_sendup(struct wl_info *wl, const wlc_event_t *e, 30extern void wl_event_sendup(struct wl_info *wl, const wlc_event_t *e,
31 u8 *data, uint32 len); 31 u8 *data, u32 len);
32extern int wl_up(struct wl_info *wl); 32extern int wl_up(struct wl_info *wl);
33extern void wl_down(struct wl_info *wl); 33extern void wl_down(struct wl_info *wl);
34extern void wl_txflowcontrol(struct wl_info *wl, struct wl_if *wlif, bool state, 34extern void wl_txflowcontrol(struct wl_info *wl, struct wl_if *wlif, bool state,
diff --git a/drivers/staging/brcm80211/sys/wl_mac80211.c b/drivers/staging/brcm80211/sys/wl_mac80211.c
index d7094e06795..0e32209e139 100644
--- a/drivers/staging/brcm80211/sys/wl_mac80211.c
+++ b/drivers/staging/brcm80211/sys/wl_mac80211.c
@@ -475,7 +475,7 @@ wl_ops_bss_info_changed(struct ieee80211_hw *hw,
475 } 475 }
476 if (changed & BSS_CHANGED_BASIC_RATES) { 476 if (changed & BSS_CHANGED_BASIC_RATES) {
477 WL_NONE(("Need to change Basic Rates:\t0x%x! Implement me\n", 477 WL_NONE(("Need to change Basic Rates:\t0x%x! Implement me\n",
478 (uint32) info->basic_rates)); 478 (u32) info->basic_rates));
479 /* Basic rateset changed */ 479 /* Basic rateset changed */
480 } 480 }
481 if (changed & BSS_CHANGED_BEACON_INT) { 481 if (changed & BSS_CHANGED_BEACON_INT) {
@@ -982,8 +982,8 @@ fail1:
982} 982}
983 983
984#ifdef WLC_HIGH_ONLY 984#ifdef WLC_HIGH_ONLY
985static void *wl_dbus_probe_cb(void *arg, const char *desc, uint32 bustype, 985static void *wl_dbus_probe_cb(void *arg, const char *desc, u32 bustype,
986 uint32 hdrlen) 986 u32 hdrlen)
987{ 987{
988 wl_info_t *wl; 988 wl_info_t *wl;
989 WL_ERROR(("%s:\n", __func__)); 989 WL_ERROR(("%s:\n", __func__));
@@ -1305,7 +1305,7 @@ wl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1305 int rc; 1305 int rc;
1306 wl_info_t *wl; 1306 wl_info_t *wl;
1307 struct ieee80211_hw *hw; 1307 struct ieee80211_hw *hw;
1308 uint32 val; 1308 u32 val;
1309 1309
1310 ASSERT(pdev); 1310 ASSERT(pdev);
1311 1311
@@ -1388,7 +1388,7 @@ static int wl_resume(struct pci_dev *pdev)
1388 wl_info_t *wl; 1388 wl_info_t *wl;
1389 struct ieee80211_hw *hw; 1389 struct ieee80211_hw *hw;
1390 int err = 0; 1390 int err = 0;
1391 uint32 val; 1391 u32 val;
1392 1392
1393 WL_TRACE(("wl: wl_resume\n")); 1393 WL_TRACE(("wl: wl_resume\n"));
1394 hw = pci_get_drvdata(pdev); 1394 hw = pci_get_drvdata(pdev);
@@ -1485,7 +1485,7 @@ static int __init wl_module_init(void)
1485 } 1485 }
1486#ifndef WLC_HIGH_ONLY 1486#ifndef WLC_HIGH_ONLY
1487 { 1487 {
1488 extern uint32 phyhal_msg_level; 1488 extern u32 phyhal_msg_level;
1489 1489
1490 if (phymsglevel != 0xdeadbeef) 1490 if (phymsglevel != 0xdeadbeef)
1491 phyhal_msg_level = phymsglevel; 1491 phyhal_msg_level = phymsglevel;
@@ -1727,11 +1727,11 @@ bool wl_alloc_dma_resources(wl_info_t *wl, uint addrwidth)
1727 return TRUE; 1727 return TRUE;
1728} 1728}
1729 1729
1730uint32 BCMFASTPATH wl_intrsoff(wl_info_t *wl) 1730u32 BCMFASTPATH wl_intrsoff(wl_info_t *wl)
1731{ 1731{
1732#if defined(WLC_LOW) 1732#if defined(WLC_LOW)
1733 unsigned long flags; 1733 unsigned long flags;
1734 uint32 status; 1734 u32 status;
1735 1735
1736 INT_LOCK(wl, flags); 1736 INT_LOCK(wl, flags);
1737 status = wlc_intrsoff(wl->wlc); 1737 status = wlc_intrsoff(wl->wlc);
@@ -1742,7 +1742,7 @@ uint32 BCMFASTPATH wl_intrsoff(wl_info_t *wl)
1742#endif /* WLC_LOW */ 1742#endif /* WLC_LOW */
1743} 1743}
1744 1744
1745void wl_intrsrestore(wl_info_t *wl, uint32 macintmask) 1745void wl_intrsrestore(wl_info_t *wl, u32 macintmask)
1746{ 1746{
1747#if defined(WLC_LOW) 1747#if defined(WLC_LOW)
1748 unsigned long flags; 1748 unsigned long flags;
@@ -2052,9 +2052,9 @@ static int wl_linux_watchdog(void *ctx)
2052} 2052}
2053 2053
2054struct wl_fw_hdr { 2054struct wl_fw_hdr {
2055 uint32 offset; 2055 u32 offset;
2056 uint32 len; 2056 u32 len;
2057 uint32 idx; 2057 u32 idx;
2058}; 2058};
2059 2059
2060#ifdef WLC_HIGH_ONLY 2060#ifdef WLC_HIGH_ONLY
@@ -2249,7 +2249,7 @@ static void wl_rpc_dispatch_schedule(void *ctx, struct rpc_buf *buf)
2249 bcm_xdr_buf_init(&b, bcm_rpc_buf_data(wl->rpc_th, buf), 2249 bcm_xdr_buf_init(&b, bcm_rpc_buf_data(wl->rpc_th, buf),
2250 bcm_rpc_buf_len_get(wl->rpc_th, buf)); 2250 bcm_rpc_buf_len_get(wl->rpc_th, buf));
2251 2251
2252 err = bcm_xdr_unpack_uint32(&b, &rpc_id); 2252 err = bcm_xdr_unpack_u32(&b, &rpc_id);
2253 ASSERT(!err); 2253 ASSERT(!err);
2254 WL_TRACE(("%s: Dispatch id %s\n", __func__, 2254 WL_TRACE(("%s: Dispatch id %s\n", __func__,
2255 WLC_RPC_ID_LOOKUP(rpc_name_tbl, rpc_id))); 2255 WLC_RPC_ID_LOOKUP(rpc_name_tbl, rpc_id)));
@@ -2283,7 +2283,7 @@ char *wl_firmwares[WL_MAX_FW] = {
2283}; 2283};
2284 2284
2285#ifdef WLC_LOW 2285#ifdef WLC_LOW
2286int wl_ucode_init_buf(wl_info_t *wl, void **pbuf, uint32 idx) 2286int wl_ucode_init_buf(wl_info_t *wl, void **pbuf, u32 idx)
2287{ 2287{
2288 int i, entry; 2288 int i, entry;
2289 const u8 *pdata; 2289 const u8 *pdata;
@@ -2309,7 +2309,7 @@ int wl_ucode_init_buf(wl_info_t *wl, void **pbuf, uint32 idx)
2309 return -1; 2309 return -1;
2310} 2310}
2311 2311
2312int wl_ucode_init_uint(wl_info_t *wl, uint32 *data, uint32 idx) 2312int wl_ucode_init_uint(wl_info_t *wl, u32 *data, u32 idx)
2313{ 2313{
2314 int i, entry; 2314 int i, entry;
2315 const u8 *pdata; 2315 const u8 *pdata;
@@ -2321,7 +2321,7 @@ int wl_ucode_init_uint(wl_info_t *wl, uint32 *data, uint32 idx)
2321 if (hdr->idx == idx) { 2321 if (hdr->idx == idx) {
2322 pdata = wl->fw.fw_bin[i]->data + hdr->offset; 2322 pdata = wl->fw.fw_bin[i]->data + hdr->offset;
2323 ASSERT(hdr->len == 4); 2323 ASSERT(hdr->len == 4);
2324 *data = *((uint32 *) pdata); 2324 *data = *((u32 *) pdata);
2325 return 0; 2325 return 0;
2326 } 2326 }
2327 } 2327 }
diff --git a/drivers/staging/brcm80211/sys/wl_mac80211.h b/drivers/staging/brcm80211/sys/wl_mac80211.h
index 1618e918e0b..78cee4454b0 100644
--- a/drivers/staging/brcm80211/sys/wl_mac80211.h
+++ b/drivers/staging/brcm80211/sys/wl_mac80211.h
@@ -53,17 +53,17 @@ struct wl_if {
53 53
54#define WL_MAX_FW 4 54#define WL_MAX_FW 4
55struct wl_firmware { 55struct wl_firmware {
56 uint32 fw_cnt; 56 u32 fw_cnt;
57 const struct firmware *fw_bin[WL_MAX_FW]; 57 const struct firmware *fw_bin[WL_MAX_FW];
58 const struct firmware *fw_hdr[WL_MAX_FW]; 58 const struct firmware *fw_hdr[WL_MAX_FW];
59 uint32 hdr_num_entries[WL_MAX_FW]; 59 u32 hdr_num_entries[WL_MAX_FW];
60}; 60};
61 61
62struct wl_info { 62struct wl_info {
63 wlc_pub_t *pub; /* pointer to public wlc state */ 63 wlc_pub_t *pub; /* pointer to public wlc state */
64 void *wlc; /* pointer to private common os-independent data */ 64 void *wlc; /* pointer to private common os-independent data */
65 osl_t *osh; /* pointer to os handler */ 65 osl_t *osh; /* pointer to os handler */
66 uint32 magic; 66 u32 magic;
67 67
68 int irq; 68 int irq;
69 69
@@ -85,7 +85,7 @@ struct wl_info {
85#endif /* BCMSDIO */ 85#endif /* BCMSDIO */
86 bool resched; /* dpc needs to be and is rescheduled */ 86 bool resched; /* dpc needs to be and is rescheduled */
87#ifdef LINUXSTA_PS 87#ifdef LINUXSTA_PS
88 uint32 pci_psstate[16]; /* pci ps-state save/restore */ 88 u32 pci_psstate[16]; /* pci ps-state save/restore */
89#endif 89#endif
90 /* RPC, handle, lock, txq, workitem */ 90 /* RPC, handle, lock, txq, workitem */
91#ifdef WLC_HIGH_ONLY 91#ifdef WLC_HIGH_ONLY
@@ -154,8 +154,8 @@ extern int wl_ucode_data_init(wl_info_t *wl);
154extern void wl_ucode_data_free(void); 154extern void wl_ucode_data_free(void);
155#ifdef WLC_LOW 155#ifdef WLC_LOW
156extern void wl_ucode_free_buf(void *); 156extern void wl_ucode_free_buf(void *);
157extern int wl_ucode_init_buf(wl_info_t *wl, void **pbuf, uint32 idx); 157extern int wl_ucode_init_buf(wl_info_t *wl, void **pbuf, u32 idx);
158extern int wl_ucode_init_uint(wl_info_t *wl, uint32 *data, uint32 idx); 158extern int wl_ucode_init_uint(wl_info_t *wl, u32 *data, u32 idx);
159#endif /* WLC_LOW */ 159#endif /* WLC_LOW */
160 160
161#endif /* _wl_mac80211_h_ */ 161#endif /* _wl_mac80211_h_ */
diff --git a/drivers/staging/brcm80211/sys/wl_ucode.h b/drivers/staging/brcm80211/sys/wl_ucode.h
index 7499cf523e2..3254f5aa46c 100644
--- a/drivers/staging/brcm80211/sys/wl_ucode.h
+++ b/drivers/staging/brcm80211/sys/wl_ucode.h
@@ -18,7 +18,7 @@
18typedef struct d11init { 18typedef struct d11init {
19 u16 addr; 19 u16 addr;
20 u16 size; 20 u16 size;
21 uint32 value; 21 u32 value;
22} d11init_t; 22} d11init_t;
23 23
24extern d11init_t *d11lcn0bsinitvals24; 24extern d11init_t *d11lcn0bsinitvals24;
@@ -30,9 +30,9 @@ extern d11init_t *d11lcn2initvals24;
30extern d11init_t *d11n0absinitvals16; 30extern d11init_t *d11n0absinitvals16;
31extern d11init_t *d11n0bsinitvals16; 31extern d11init_t *d11n0bsinitvals16;
32extern d11init_t *d11n0initvals16; 32extern d11init_t *d11n0initvals16;
33extern uint32 *bcm43xx_16_mimo; 33extern u32 *bcm43xx_16_mimo;
34extern uint32 bcm43xx_16_mimosz; 34extern u32 bcm43xx_16_mimosz;
35extern uint32 *bcm43xx_24_lcn; 35extern u32 *bcm43xx_24_lcn;
36extern uint32 bcm43xx_24_lcnsz; 36extern u32 bcm43xx_24_lcnsz;
37extern uint32 *bcm43xx_bommajor; 37extern u32 *bcm43xx_bommajor;
38extern uint32 *bcm43xx_bomminor; 38extern u32 *bcm43xx_bomminor;
diff --git a/drivers/staging/brcm80211/sys/wl_ucode_loader.c b/drivers/staging/brcm80211/sys/wl_ucode_loader.c
index f99c042c8f4..93a3a016db5 100644
--- a/drivers/staging/brcm80211/sys/wl_ucode_loader.c
+++ b/drivers/staging/brcm80211/sys/wl_ucode_loader.c
@@ -34,12 +34,12 @@ d11init_t *d11lcn2initvals24;
34d11init_t *d11n0absinitvals16; 34d11init_t *d11n0absinitvals16;
35d11init_t *d11n0bsinitvals16; 35d11init_t *d11n0bsinitvals16;
36d11init_t *d11n0initvals16; 36d11init_t *d11n0initvals16;
37uint32 *bcm43xx_16_mimo; 37u32 *bcm43xx_16_mimo;
38uint32 bcm43xx_16_mimosz; 38u32 bcm43xx_16_mimosz;
39uint32 *bcm43xx_24_lcn; 39u32 *bcm43xx_24_lcn;
40uint32 bcm43xx_24_lcnsz; 40u32 bcm43xx_24_lcnsz;
41uint32 *bcm43xx_bommajor; 41u32 *bcm43xx_bommajor;
42uint32 *bcm43xx_bomminor; 42u32 *bcm43xx_bomminor;
43 43
44int wl_ucode_data_init(wl_info_t *wl) 44int wl_ucode_data_init(wl_info_t *wl)
45{ 45{
diff --git a/drivers/staging/brcm80211/sys/wlc_ampdu.c b/drivers/staging/brcm80211/sys/wlc_ampdu.c
index 7fd7a0adb07..a888484906d 100644
--- a/drivers/staging/brcm80211/sys/wlc_ampdu.c
+++ b/drivers/staging/brcm80211/sys/wlc_ampdu.c
@@ -74,7 +74,7 @@
74 + DOT11_A4_HDR_LEN + DOT11_QOS_LEN + DOT11_IV_MAX_LEN) 74 + DOT11_A4_HDR_LEN + DOT11_QOS_LEN + DOT11_IV_MAX_LEN)
75 75
76#ifdef BCMDBG 76#ifdef BCMDBG
77uint32 wl_ampdu_dbg = 77u32 wl_ampdu_dbg =
78 WL_AMPDU_UPDN_VAL | 78 WL_AMPDU_UPDN_VAL |
79 WL_AMPDU_ERR_VAL | 79 WL_AMPDU_ERR_VAL |
80 WL_AMPDU_TX_VAL | 80 WL_AMPDU_TX_VAL |
@@ -93,10 +93,10 @@ typedef struct wlc_fifo_info {
93 u16 ampdu_pld_size; /* number of bytes to be pre-loaded */ 93 u16 ampdu_pld_size; /* number of bytes to be pre-loaded */
94 u8 mcs2ampdu_table[FFPLD_MAX_MCS + 1]; /* per-mcs max # of mpdus in an ampdu */ 94 u8 mcs2ampdu_table[FFPLD_MAX_MCS + 1]; /* per-mcs max # of mpdus in an ampdu */
95 u16 prev_txfunfl; /* num of underflows last read from the HW macstats counter */ 95 u16 prev_txfunfl; /* num of underflows last read from the HW macstats counter */
96 uint32 accum_txfunfl; /* num of underflows since we modified pld params */ 96 u32 accum_txfunfl; /* num of underflows since we modified pld params */
97 uint32 accum_txampdu; /* num of tx ampdu since we modified pld params */ 97 u32 accum_txampdu; /* num of tx ampdu since we modified pld params */
98 uint32 prev_txampdu; /* previous reading of tx ampdu */ 98 u32 prev_txampdu; /* previous reading of tx ampdu */
99 uint32 dmaxferrate; /* estimated dma avg xfer rate in kbits/sec */ 99 u32 dmaxferrate; /* estimated dma avg xfer rate in kbits/sec */
100} wlc_fifo_info_t; 100} wlc_fifo_info_t;
101 101
102/* AMPDU module specific state */ 102/* AMPDU module specific state */
@@ -116,11 +116,11 @@ struct ampdu_info {
116 u8 dur; /* max duration of an ampdu (in msec) */ 116 u8 dur; /* max duration of an ampdu (in msec) */
117 u8 txpkt_weight; /* weight of ampdu in txfifo; reduces rate lag */ 117 u8 txpkt_weight; /* weight of ampdu in txfifo; reduces rate lag */
118 u8 rx_factor; /* maximum rx ampdu factor (0-3) ==> 2^(13+x) bytes */ 118 u8 rx_factor; /* maximum rx ampdu factor (0-3) ==> 2^(13+x) bytes */
119 uint32 ffpld_rsvd; /* number of bytes to reserve for preload */ 119 u32 ffpld_rsvd; /* number of bytes to reserve for preload */
120 uint32 max_txlen[MCS_TABLE_SIZE][2][2]; /* max size of ampdu per mcs, bw and sgi */ 120 u32 max_txlen[MCS_TABLE_SIZE][2][2]; /* max size of ampdu per mcs, bw and sgi */
121 void *ini_free[AMPDU_INI_FREE]; /* array of ini's to be freed on detach */ 121 void *ini_free[AMPDU_INI_FREE]; /* array of ini's to be freed on detach */
122 bool mfbr; /* enable multiple fallback rate */ 122 bool mfbr; /* enable multiple fallback rate */
123 uint32 tx_max_funl; /* underflows should be kept such that 123 u32 tx_max_funl; /* underflows should be kept such that
124 * (tx_max_funfl*underflows) < tx frames 124 * (tx_max_funfl*underflows) < tx frames
125 */ 125 */
126 wlc_fifo_info_t fifo_tb[NUM_FFPLD_FIFO]; /* table of fifo infos */ 126 wlc_fifo_info_t fifo_tb[NUM_FFPLD_FIFO]; /* table of fifo infos */
@@ -155,8 +155,8 @@ static void scb_ampdu_update_config_all(ampdu_info_t *ampdu);
155 155
156static void wlc_ampdu_dotxstatus_complete(ampdu_info_t *ampdu, struct scb *scb, 156static void wlc_ampdu_dotxstatus_complete(ampdu_info_t *ampdu, struct scb *scb,
157 void *p, tx_status_t *txs, 157 void *p, tx_status_t *txs,
158 uint32 frmtxstatus, 158 u32 frmtxstatus,
159 uint32 frmtxstatus2); 159 u32 frmtxstatus2);
160 160
161static inline u16 pkt_txh_seqnum(wlc_info_t *wlc, void *p) 161static inline u16 pkt_txh_seqnum(wlc_info_t *wlc, void *p)
162{ 162{
@@ -335,12 +335,12 @@ static void wlc_ffpld_init(ampdu_info_t *ampdu)
335static int wlc_ffpld_check_txfunfl(wlc_info_t *wlc, int fid) 335static int wlc_ffpld_check_txfunfl(wlc_info_t *wlc, int fid)
336{ 336{
337 ampdu_info_t *ampdu = wlc->ampdu; 337 ampdu_info_t *ampdu = wlc->ampdu;
338 uint32 phy_rate = MCS_RATE(FFPLD_MAX_MCS, TRUE, FALSE); 338 u32 phy_rate = MCS_RATE(FFPLD_MAX_MCS, TRUE, FALSE);
339 uint32 txunfl_ratio; 339 u32 txunfl_ratio;
340 u8 max_mpdu; 340 u8 max_mpdu;
341 uint32 current_ampdu_cnt = 0; 341 u32 current_ampdu_cnt = 0;
342 u16 max_pld_size; 342 u16 max_pld_size;
343 uint32 new_txunfl; 343 u32 new_txunfl;
344 wlc_fifo_info_t *fifo = (ampdu->fifo_tb + fid); 344 wlc_fifo_info_t *fifo = (ampdu->fifo_tb + fid);
345 uint xmtfifo_sz; 345 uint xmtfifo_sz;
346 u16 cur_txunfl; 346 u16 cur_txunfl;
@@ -365,7 +365,7 @@ static int wlc_ffpld_check_txfunfl(wlc_info_t *wlc, int fid)
365 return -1; 365 return -1;
366 } 366 }
367 367
368 if ((TXFIFO_SIZE_UNIT * (uint32) xmtfifo_sz) <= ampdu->ffpld_rsvd) 368 if ((TXFIFO_SIZE_UNIT * (u32) xmtfifo_sz) <= ampdu->ffpld_rsvd)
369 return 1; 369 return 1;
370 370
371 max_pld_size = TXFIFO_SIZE_UNIT * xmtfifo_sz - ampdu->ffpld_rsvd; 371 max_pld_size = TXFIFO_SIZE_UNIT * xmtfifo_sz - ampdu->ffpld_rsvd;
@@ -455,7 +455,7 @@ static int wlc_ffpld_check_txfunfl(wlc_info_t *wlc, int fid)
455static void wlc_ffpld_calc_mcs2ampdu_table(ampdu_info_t *ampdu, int f) 455static void wlc_ffpld_calc_mcs2ampdu_table(ampdu_info_t *ampdu, int f)
456{ 456{
457 int i; 457 int i;
458 uint32 phy_rate, dma_rate, tmp; 458 u32 phy_rate, dma_rate, tmp;
459 u8 max_mpdu; 459 u8 max_mpdu;
460 wlc_fifo_info_t *fifo = (ampdu->fifo_tb + f); 460 wlc_fifo_info_t *fifo = (ampdu->fifo_tb + f);
461 461
@@ -517,7 +517,7 @@ wlc_sendampdu(ampdu_info_t *ampdu, wlc_txq_info_t *qi, void **pdu, int prec)
517 bool rr = TRUE, fbr = FALSE; 517 bool rr = TRUE, fbr = FALSE;
518 uint i, count = 0, fifo, seg_cnt = 0; 518 uint i, count = 0, fifo, seg_cnt = 0;
519 u16 plen, len, seq = 0, mcl, mch, index, frameid, dma_len = 0; 519 u16 plen, len, seq = 0, mcl, mch, index, frameid, dma_len = 0;
520 uint32 ampdu_len, maxlen = 0; 520 u32 ampdu_len, maxlen = 0;
521 d11txh_t *txh = NULL; 521 d11txh_t *txh = NULL;
522 u8 *plcp; 522 u8 *plcp;
523 struct dot11_header *h; 523 struct dot11_header *h;
@@ -914,7 +914,7 @@ wlc_ampdu_dotxstatus(ampdu_info_t *ampdu, struct scb *scb, void *p,
914 scb_ampdu_t *scb_ampdu; 914 scb_ampdu_t *scb_ampdu;
915 wlc_info_t *wlc = ampdu->wlc; 915 wlc_info_t *wlc = ampdu->wlc;
916 scb_ampdu_tid_ini_t *ini; 916 scb_ampdu_tid_ini_t *ini;
917 uint32 s1 = 0, s2 = 0; 917 u32 s1 = 0, s2 = 0;
918 struct ieee80211_tx_info *tx_info; 918 struct ieee80211_tx_info *tx_info;
919 919
920 tx_info = IEEE80211_SKB_CB(p); 920 tx_info = IEEE80211_SKB_CB(p);
@@ -969,7 +969,7 @@ wlc_ampdu_dotxstatus(ampdu_info_t *ampdu, struct scb *scb, void *p,
969} 969}
970 970
971#ifdef WLC_HIGH_ONLY 971#ifdef WLC_HIGH_ONLY
972void wlc_ampdu_txstatus_complete(ampdu_info_t *ampdu, uint32 s1, uint32 s2) 972void wlc_ampdu_txstatus_complete(ampdu_info_t *ampdu, u32 s1, u32 s2)
973{ 973{
974 WL_AMPDU_TX(("wl%d: wlc_ampdu_txstatus_complete: High Recvd 0x%x 0x%x p:%p\n", ampdu->wlc->pub->unit, s1, s2, ampdu->p)); 974 WL_AMPDU_TX(("wl%d: wlc_ampdu_txstatus_complete: High Recvd 0x%x 0x%x p:%p\n", ampdu->wlc->pub->unit, s1, s2, ampdu->p));
975 975
@@ -1017,7 +1017,7 @@ extern void wlc_txq_enq(wlc_info_t *wlc, struct scb *scb, void *sdu,
1017 1017
1018static void BCMFASTPATH 1018static void BCMFASTPATH
1019wlc_ampdu_dotxstatus_complete(ampdu_info_t *ampdu, struct scb *scb, void *p, 1019wlc_ampdu_dotxstatus_complete(ampdu_info_t *ampdu, struct scb *scb, void *p,
1020 tx_status_t *txs, uint32 s1, uint32 s2) 1020 tx_status_t *txs, u32 s1, u32 s2)
1021{ 1021{
1022 scb_ampdu_t *scb_ampdu; 1022 scb_ampdu_t *scb_ampdu;
1023 wlc_info_t *wlc = ampdu->wlc; 1023 wlc_info_t *wlc = ampdu->wlc;
@@ -1325,7 +1325,7 @@ bool wlc_ampdu_cap(ampdu_info_t *ampdu)
1325 1325
1326static void ampdu_update_max_txlen(ampdu_info_t *ampdu, u8 dur) 1326static void ampdu_update_max_txlen(ampdu_info_t *ampdu, u8 dur)
1327{ 1327{
1328 uint32 rate, mcs; 1328 u32 rate, mcs;
1329 1329
1330 for (mcs = 0; mcs < MCS_TABLE_SIZE; mcs++) { 1330 for (mcs = 0; mcs < MCS_TABLE_SIZE; mcs++) {
1331 /* rate is in Kbps; dur is in msec ==> len = (rate * dur) / 8 */ 1331 /* rate is in Kbps; dur is in msec ==> len = (rate * dur) / 8 */
diff --git a/drivers/staging/brcm80211/sys/wlc_ampdu.h b/drivers/staging/brcm80211/sys/wlc_ampdu.h
index 9965e271b5e..c721b16cc70 100644
--- a/drivers/staging/brcm80211/sys/wlc_ampdu.h
+++ b/drivers/staging/brcm80211/sys/wlc_ampdu.h
@@ -33,8 +33,8 @@ extern u8 wlc_ampdu_null_delim_cnt(ampdu_info_t *ampdu, struct scb *scb,
33 ratespec_t rspec, int phylen); 33 ratespec_t rspec, int phylen);
34extern void scb_ampdu_cleanup(ampdu_info_t *ampdu, struct scb *scb); 34extern void scb_ampdu_cleanup(ampdu_info_t *ampdu, struct scb *scb);
35#ifdef WLC_HIGH_ONLY 35#ifdef WLC_HIGH_ONLY
36extern void wlc_ampdu_txstatus_complete(ampdu_info_t *ampdu, uint32 s1, 36extern void wlc_ampdu_txstatus_complete(ampdu_info_t *ampdu, u32 s1,
37 uint32 s2); 37 u32 s2);
38#endif 38#endif
39 39
40#endif /* _wlc_ampdu_h_ */ 40#endif /* _wlc_ampdu_h_ */
diff --git a/drivers/staging/brcm80211/sys/wlc_bmac.c b/drivers/staging/brcm80211/sys/wlc_bmac.c
index 53ac604958f..5e778966f72 100644
--- a/drivers/staging/brcm80211/sys/wlc_bmac.c
+++ b/drivers/staging/brcm80211/sys/wlc_bmac.c
@@ -119,14 +119,14 @@ static void wlc_coreinit(wlc_info_t *wlc);
119 119
120/* used by wlc_wakeucode_init() */ 120/* used by wlc_wakeucode_init() */
121static void wlc_write_inits(wlc_hw_info_t *wlc_hw, const d11init_t *inits); 121static void wlc_write_inits(wlc_hw_info_t *wlc_hw, const d11init_t *inits);
122static void wlc_ucode_write(wlc_hw_info_t *wlc_hw, const uint32 ucode[], 122static void wlc_ucode_write(wlc_hw_info_t *wlc_hw, const u32 ucode[],
123 const uint nbytes); 123 const uint nbytes);
124static void wlc_ucode_download(wlc_hw_info_t *wlc); 124static void wlc_ucode_download(wlc_hw_info_t *wlc);
125static void wlc_ucode_txant_set(wlc_hw_info_t *wlc_hw); 125static void wlc_ucode_txant_set(wlc_hw_info_t *wlc_hw);
126 126
127/* used by wlc_dpc() */ 127/* used by wlc_dpc() */
128static bool wlc_bmac_dotxstatus(wlc_hw_info_t *wlc, tx_status_t *txs, 128static bool wlc_bmac_dotxstatus(wlc_hw_info_t *wlc, tx_status_t *txs,
129 uint32 s2); 129 u32 s2);
130static bool wlc_bmac_txstatus_corerev4(wlc_hw_info_t *wlc); 130static bool wlc_bmac_txstatus_corerev4(wlc_hw_info_t *wlc);
131static bool wlc_bmac_txstatus(wlc_hw_info_t *wlc, bool bound, bool *fatal); 131static bool wlc_bmac_txstatus(wlc_hw_info_t *wlc, bool bound, bool *fatal);
132static bool wlc_bmac_recv(wlc_hw_info_t *wlc_hw, uint fifo, bool bound); 132static bool wlc_bmac_recv(wlc_hw_info_t *wlc_hw, uint fifo, bool bound);
@@ -140,9 +140,9 @@ static void wlc_corerev_fifofixup(wlc_hw_info_t *wlc_hw);
140 140
141/* Low Level Prototypes */ 141/* Low Level Prototypes */
142static u16 wlc_bmac_read_objmem(wlc_hw_info_t *wlc_hw, uint offset, 142static u16 wlc_bmac_read_objmem(wlc_hw_info_t *wlc_hw, uint offset,
143 uint32 sel); 143 u32 sel);
144static void wlc_bmac_write_objmem(wlc_hw_info_t *wlc_hw, uint offset, u16 v, 144static void wlc_bmac_write_objmem(wlc_hw_info_t *wlc_hw, uint offset, u16 v,
145 uint32 sel); 145 u32 sel);
146static bool wlc_bmac_attach_dmapio(wlc_info_t *wlc, uint j, bool wme); 146static bool wlc_bmac_attach_dmapio(wlc_info_t *wlc, uint j, bool wme);
147static void wlc_bmac_detach_dmapio(wlc_hw_info_t *wlc_hw); 147static void wlc_bmac_detach_dmapio(wlc_hw_info_t *wlc_hw);
148static void wlc_ucode_bsinit(wlc_hw_info_t *wlc_hw); 148static void wlc_ucode_bsinit(wlc_hw_info_t *wlc_hw);
@@ -153,15 +153,15 @@ static void wlc_mhfdef(wlc_info_t *wlc, u16 *mhfs, u16 mhf2_init);
153static void wlc_mctrl_write(wlc_hw_info_t *wlc_hw); 153static void wlc_mctrl_write(wlc_hw_info_t *wlc_hw);
154static void wlc_ucode_mute_override_set(wlc_hw_info_t *wlc_hw); 154static void wlc_ucode_mute_override_set(wlc_hw_info_t *wlc_hw);
155static void wlc_ucode_mute_override_clear(wlc_hw_info_t *wlc_hw); 155static void wlc_ucode_mute_override_clear(wlc_hw_info_t *wlc_hw);
156static uint32 wlc_wlintrsoff(wlc_info_t *wlc); 156static u32 wlc_wlintrsoff(wlc_info_t *wlc);
157static void wlc_wlintrsrestore(wlc_info_t *wlc, uint32 macintmask); 157static void wlc_wlintrsrestore(wlc_info_t *wlc, u32 macintmask);
158static void wlc_gpio_init(wlc_info_t *wlc); 158static void wlc_gpio_init(wlc_info_t *wlc);
159static void wlc_write_hw_bcntemplate0(wlc_hw_info_t *wlc_hw, void *bcn, 159static void wlc_write_hw_bcntemplate0(wlc_hw_info_t *wlc_hw, void *bcn,
160 int len); 160 int len);
161static void wlc_write_hw_bcntemplate1(wlc_hw_info_t *wlc_hw, void *bcn, 161static void wlc_write_hw_bcntemplate1(wlc_hw_info_t *wlc_hw, void *bcn,
162 int len); 162 int len);
163static void wlc_bmac_bsinit(wlc_info_t *wlc, chanspec_t chanspec); 163static void wlc_bmac_bsinit(wlc_info_t *wlc, chanspec_t chanspec);
164static uint32 wlc_setband_inact(wlc_info_t *wlc, uint bandunit); 164static u32 wlc_setband_inact(wlc_info_t *wlc, uint bandunit);
165static void wlc_bmac_setband(wlc_hw_info_t *wlc_hw, uint bandunit, 165static void wlc_bmac_setband(wlc_hw_info_t *wlc_hw, uint bandunit,
166 chanspec_t chanspec); 166 chanspec_t chanspec);
167static void wlc_bmac_update_slot_timing(wlc_hw_info_t *wlc_hw, bool shortslot); 167static void wlc_bmac_update_slot_timing(wlc_hw_info_t *wlc_hw, bool shortslot);
@@ -233,11 +233,11 @@ static void WLBANDINITFN(wlc_ucode_bsinit) (wlc_hw_info_t *wlc_hw)
233} 233}
234 234
235/* switch to new band but leave it inactive */ 235/* switch to new band but leave it inactive */
236static uint32 WLBANDINITFN(wlc_setband_inact) (wlc_info_t *wlc, uint bandunit) 236static u32 WLBANDINITFN(wlc_setband_inact) (wlc_info_t *wlc, uint bandunit)
237{ 237{
238 wlc_hw_info_t *wlc_hw = wlc->hw; 238 wlc_hw_info_t *wlc_hw = wlc->hw;
239 uint32 macintmask; 239 u32 macintmask;
240 uint32 tmp; 240 u32 tmp;
241 241
242 WL_TRACE(("wl%d: wlc_setband_inact\n", wlc_hw->unit)); 242 WL_TRACE(("wl%d: wlc_setband_inact\n", wlc_hw->unit));
243 243
@@ -277,7 +277,7 @@ wlc_bmac_recv(wlc_hw_info_t *wlc_hw, uint fifo, bool bound)
277 void *tail = NULL; 277 void *tail = NULL;
278 uint n = 0; 278 uint n = 0;
279 uint bound_limit = bound ? wlc_hw->wlc->pub->tunables->rxbnd : -1; 279 uint bound_limit = bound ? wlc_hw->wlc->pub->tunables->rxbnd : -1;
280 uint32 tsf_h, tsf_l; 280 u32 tsf_h, tsf_l;
281 wlc_d11rxhdr_t *wlc_rxhdr = NULL; 281 wlc_d11rxhdr_t *wlc_rxhdr = NULL;
282 282
283 WL_TRACE(("wl%d: %s\n", wlc_hw->unit, __func__)); 283 WL_TRACE(("wl%d: %s\n", wlc_hw->unit, __func__));
@@ -326,7 +326,7 @@ wlc_bmac_recv(wlc_hw_info_t *wlc_hw, uint fifo, bool bound)
326 */ 326 */
327bool BCMFASTPATH wlc_dpc(wlc_info_t *wlc, bool bounded) 327bool BCMFASTPATH wlc_dpc(wlc_info_t *wlc, bool bounded)
328{ 328{
329 uint32 macintstatus; 329 u32 macintstatus;
330 wlc_hw_info_t *wlc_hw = wlc->hw; 330 wlc_hw_info_t *wlc_hw = wlc->hw;
331 d11regs_t *regs = wlc_hw->regs; 331 d11regs_t *regs = wlc_hw->regs;
332 bool fatal = FALSE; 332 bool fatal = FALSE;
@@ -425,7 +425,7 @@ bool BCMFASTPATH wlc_dpc(wlc_info_t *wlc, bool bounded)
425 425
426 if (macintstatus & MI_RFDISABLE) { 426 if (macintstatus & MI_RFDISABLE) {
427#if defined(BCMDBG) 427#if defined(BCMDBG)
428 uint32 rfd = R_REG(wlc_hw->osh, &regs->phydebug) & PDBG_RFD; 428 u32 rfd = R_REG(wlc_hw->osh, &regs->phydebug) & PDBG_RFD;
429#endif 429#endif
430 430
431 WL_ERROR(("wl%d: MAC Detected a change on the RF Disable Input 0x%x\n", wlc_hw->unit, rfd)); 431 WL_ERROR(("wl%d: MAC Detected a change on the RF Disable Input 0x%x\n", wlc_hw->unit, rfd));
@@ -829,8 +829,8 @@ BCMATTACHFN(wlc_bmac_attach) (wlc_info_t *wlc, u16 vendor, u16 device,
829 goto fail; 829 goto fail;
830 } 830 }
831 wlc_hw->sromrev = (u8) getintvar(vars, "sromrev"); 831 wlc_hw->sromrev = (u8) getintvar(vars, "sromrev");
832 wlc_hw->boardflags = (uint32) getintvar(vars, "boardflags"); 832 wlc_hw->boardflags = (u32) getintvar(vars, "boardflags");
833 wlc_hw->boardflags2 = (uint32) getintvar(vars, "boardflags2"); 833 wlc_hw->boardflags2 = (u32) getintvar(vars, "boardflags2");
834 834
835 if (D11REV_LE(wlc_hw->corerev, 4) 835 if (D11REV_LE(wlc_hw->corerev, 4)
836 || (wlc_hw->boardflags & BFL_NOPLLDOWN)) 836 || (wlc_hw->boardflags & BFL_NOPLLDOWN))
@@ -1140,7 +1140,7 @@ void BCMINITFN(wlc_bmac_reset) (wlc_hw_info_t *wlc_hw)
1140void 1140void
1141BCMINITFN(wlc_bmac_init) (wlc_hw_info_t *wlc_hw, chanspec_t chanspec, 1141BCMINITFN(wlc_bmac_init) (wlc_hw_info_t *wlc_hw, chanspec_t chanspec,
1142 bool mute) { 1142 bool mute) {
1143 uint32 macintmask; 1143 u32 macintmask;
1144 bool fastclk; 1144 bool fastclk;
1145 wlc_info_t *wlc = wlc_hw->wlc; 1145 wlc_info_t *wlc = wlc_hw->wlc;
1146 1146
@@ -1597,10 +1597,10 @@ static void wlc_mctrl_reset(wlc_hw_info_t *wlc_hw)
1597} 1597}
1598 1598
1599/* set or clear maccontrol bits */ 1599/* set or clear maccontrol bits */
1600void wlc_bmac_mctrl(wlc_hw_info_t *wlc_hw, uint32 mask, uint32 val) 1600void wlc_bmac_mctrl(wlc_hw_info_t *wlc_hw, u32 mask, u32 val)
1601{ 1601{
1602 uint32 maccontrol; 1602 u32 maccontrol;
1603 uint32 new_maccontrol; 1603 u32 new_maccontrol;
1604 1604
1605 ASSERT((val & ~mask) == 0); 1605 ASSERT((val & ~mask) == 0);
1606 1606
@@ -1621,7 +1621,7 @@ void wlc_bmac_mctrl(wlc_hw_info_t *wlc_hw, uint32 mask, uint32 val)
1621/* write the software state of maccontrol and overrides to the maccontrol register */ 1621/* write the software state of maccontrol and overrides to the maccontrol register */
1622static void wlc_mctrl_write(wlc_hw_info_t *wlc_hw) 1622static void wlc_mctrl_write(wlc_hw_info_t *wlc_hw)
1623{ 1623{
1624 uint32 maccontrol = wlc_hw->maccontrol; 1624 u32 maccontrol = wlc_hw->maccontrol;
1625 1625
1626 /* OR in the wake bit if overridden */ 1626 /* OR in the wake bit if overridden */
1627 if (wlc_hw->wake_override) 1627 if (wlc_hw->wake_override)
@@ -1636,7 +1636,7 @@ static void wlc_mctrl_write(wlc_hw_info_t *wlc_hw)
1636 W_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol, maccontrol); 1636 W_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol, maccontrol);
1637} 1637}
1638 1638
1639void wlc_ucode_wake_override_set(wlc_hw_info_t *wlc_hw, uint32 override_bit) 1639void wlc_ucode_wake_override_set(wlc_hw_info_t *wlc_hw, u32 override_bit)
1640{ 1640{
1641 ASSERT((wlc_hw->wake_override & override_bit) == 0); 1641 ASSERT((wlc_hw->wake_override & override_bit) == 0);
1642 1642
@@ -1653,7 +1653,7 @@ void wlc_ucode_wake_override_set(wlc_hw_info_t *wlc_hw, uint32 override_bit)
1653 return; 1653 return;
1654} 1654}
1655 1655
1656void wlc_ucode_wake_override_clear(wlc_hw_info_t *wlc_hw, uint32 override_bit) 1656void wlc_ucode_wake_override_clear(wlc_hw_info_t *wlc_hw, u32 override_bit)
1657{ 1657{
1658 ASSERT(wlc_hw->wake_override & override_bit); 1658 ASSERT(wlc_hw->wake_override & override_bit);
1659 1659
@@ -1716,7 +1716,7 @@ wlc_bmac_set_rcmta(wlc_hw_info_t *wlc_hw, int idx,
1716 d11regs_t *regs = wlc_hw->regs; 1716 d11regs_t *regs = wlc_hw->regs;
1717 volatile u16 *objdata16 = 1717 volatile u16 *objdata16 =
1718 (volatile u16 *)(uintptr) & regs->objdata; 1718 (volatile u16 *)(uintptr) & regs->objdata;
1719 uint32 mac_hm; 1719 u32 mac_hm;
1720 u16 mac_l; 1720 u16 mac_l;
1721 osl_t *osh; 1721 osl_t *osh;
1722 1722
@@ -1777,7 +1777,7 @@ wlc_bmac_write_template_ram(wlc_hw_info_t *wlc_hw, int offset, int len,
1777 void *buf) 1777 void *buf)
1778{ 1778{
1779 d11regs_t *regs; 1779 d11regs_t *regs;
1780 uint32 word; 1780 u32 word;
1781 bool be_bit; 1781 bool be_bit;
1782#ifdef IL_BIGENDIAN 1782#ifdef IL_BIGENDIAN
1783 volatile u16 *dptr = NULL; 1783 volatile u16 *dptr = NULL;
@@ -1789,8 +1789,8 @@ wlc_bmac_write_template_ram(wlc_hw_info_t *wlc_hw, int offset, int len,
1789 regs = wlc_hw->regs; 1789 regs = wlc_hw->regs;
1790 osh = wlc_hw->osh; 1790 osh = wlc_hw->osh;
1791 1791
1792 ASSERT(ISALIGNED(offset, sizeof(uint32))); 1792 ASSERT(ISALIGNED(offset, sizeof(u32)));
1793 ASSERT(ISALIGNED(len, sizeof(uint32))); 1793 ASSERT(ISALIGNED(len, sizeof(u32)));
1794 ASSERT((offset & ~0xffff) == 0); 1794 ASSERT((offset & ~0xffff) == 0);
1795 1795
1796 W_REG(osh, &regs->tplatewrptr, offset); 1796 W_REG(osh, &regs->tplatewrptr, offset);
@@ -1802,7 +1802,7 @@ wlc_bmac_write_template_ram(wlc_hw_info_t *wlc_hw, int offset, int len,
1802 be_bit = (R_REG(osh, &regs->maccontrol) & MCTL_BIGEND) != 0; 1802 be_bit = (R_REG(osh, &regs->maccontrol) & MCTL_BIGEND) != 0;
1803 1803
1804 while (len > 0) { 1804 while (len > 0) {
1805 bcopy((u8 *) buf, &word, sizeof(uint32)); 1805 bcopy((u8 *) buf, &word, sizeof(u32));
1806 1806
1807 if (be_bit) 1807 if (be_bit)
1808 word = hton32(word); 1808 word = hton32(word);
@@ -1811,8 +1811,8 @@ wlc_bmac_write_template_ram(wlc_hw_info_t *wlc_hw, int offset, int len,
1811 1811
1812 W_REG(osh, &regs->tplatewrdata, word); 1812 W_REG(osh, &regs->tplatewrdata, word);
1813 1813
1814 buf = (u8 *) buf + sizeof(uint32); 1814 buf = (u8 *) buf + sizeof(u32);
1815 len -= sizeof(uint32); 1815 len -= sizeof(u32);
1816 } 1816 }
1817} 1817}
1818 1818
@@ -1843,7 +1843,7 @@ void wlc_bmac_set_cwmax(wlc_hw_info_t *wlc_hw, u16 newmax)
1843void wlc_bmac_bw_set(wlc_hw_info_t *wlc_hw, u16 bw) 1843void wlc_bmac_bw_set(wlc_hw_info_t *wlc_hw, u16 bw)
1844{ 1844{
1845 bool fastclk; 1845 bool fastclk;
1846 uint32 tmp; 1846 u32 tmp;
1847 1847
1848 /* request FAST clock if not on */ 1848 /* request FAST clock if not on */
1849 fastclk = wlc_hw->forcefastclk; 1849 fastclk = wlc_hw->forcefastclk;
@@ -2043,7 +2043,7 @@ void wlc_bmac_macphyclk_set(wlc_hw_info_t *wlc_hw, bool clk)
2043void wlc_bmac_phy_reset(wlc_hw_info_t *wlc_hw) 2043void wlc_bmac_phy_reset(wlc_hw_info_t *wlc_hw)
2044{ 2044{
2045 wlc_phy_t *pih = wlc_hw->band->pi; 2045 wlc_phy_t *pih = wlc_hw->band->pi;
2046 uint32 phy_bw_clkbits; 2046 u32 phy_bw_clkbits;
2047 bool phy_in_reset = FALSE; 2047 bool phy_in_reset = FALSE;
2048 2048
2049 WL_TRACE(("wl%d: wlc_bmac_phy_reset\n", wlc_hw->unit)); 2049 WL_TRACE(("wl%d: wlc_bmac_phy_reset\n", wlc_hw->unit));
@@ -2087,7 +2087,7 @@ static void
2087WLBANDINITFN(wlc_bmac_setband) (wlc_hw_info_t *wlc_hw, uint bandunit, 2087WLBANDINITFN(wlc_bmac_setband) (wlc_hw_info_t *wlc_hw, uint bandunit,
2088 chanspec_t chanspec) { 2088 chanspec_t chanspec) {
2089 wlc_info_t *wlc = wlc_hw->wlc; 2089 wlc_info_t *wlc = wlc_hw->wlc;
2090 uint32 macintmask; 2090 u32 macintmask;
2091 2091
2092 ASSERT(NBANDS_HW(wlc_hw) > 1); 2092 ASSERT(NBANDS_HW(wlc_hw) > 1);
2093 ASSERT(bandunit != wlc_hw->band->bandunit); 2093 ASSERT(bandunit != wlc_hw->band->bandunit);
@@ -2210,7 +2210,7 @@ static char *BCMINITFN(wlc_get_macaddr) (wlc_hw_info_t *wlc_hw)
2210bool wlc_bmac_radio_read_hwdisabled(wlc_hw_info_t *wlc_hw) 2210bool wlc_bmac_radio_read_hwdisabled(wlc_hw_info_t *wlc_hw)
2211{ 2211{
2212 bool v, clk, xtal; 2212 bool v, clk, xtal;
2213 uint32 resetbits = 0, flags = 0; 2213 u32 resetbits = 0, flags = 0;
2214 2214
2215 xtal = wlc_hw->sbclk; 2215 xtal = wlc_hw->sbclk;
2216 if (!xtal) 2216 if (!xtal)
@@ -2328,12 +2328,12 @@ static bool wlc_dma_rxreset(wlc_hw_info_t *wlc_hw, uint fifo)
2328 * clear software macintstatus for fresh new start 2328 * clear software macintstatus for fresh new start
2329 * one testing hack wlc_hw->noreset will bypass the d11/phy reset 2329 * one testing hack wlc_hw->noreset will bypass the d11/phy reset
2330 */ 2330 */
2331void BCMINITFN(wlc_bmac_corereset) (wlc_hw_info_t *wlc_hw, uint32 flags) 2331void BCMINITFN(wlc_bmac_corereset) (wlc_hw_info_t *wlc_hw, u32 flags)
2332{ 2332{
2333 d11regs_t *regs; 2333 d11regs_t *regs;
2334 uint i; 2334 uint i;
2335 bool fastclk; 2335 bool fastclk;
2336 uint32 resetbits = 0; 2336 u32 resetbits = 0;
2337 2337
2338 if (flags == WLC_USE_COREFLAGS) 2338 if (flags == WLC_USE_COREFLAGS)
2339 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0); 2339 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
@@ -2481,7 +2481,7 @@ static void BCMINITFN(wlc_coreinit) (wlc_info_t *wlc)
2481{ 2481{
2482 wlc_hw_info_t *wlc_hw = wlc->hw; 2482 wlc_hw_info_t *wlc_hw = wlc->hw;
2483 d11regs_t *regs; 2483 d11regs_t *regs;
2484 uint32 sflags; 2484 u32 sflags;
2485 uint bcnint_us; 2485 uint bcnint_us;
2486 uint i = 0; 2486 uint i = 0;
2487 bool fifosz_fixup = FALSE; 2487 bool fifosz_fixup = FALSE;
@@ -2723,7 +2723,7 @@ static void BCMINITFN(wlc_gpio_init) (wlc_info_t *wlc)
2723{ 2723{
2724 wlc_hw_info_t *wlc_hw = wlc->hw; 2724 wlc_hw_info_t *wlc_hw = wlc->hw;
2725 d11regs_t *regs; 2725 d11regs_t *regs;
2726 uint32 gc, gm; 2726 u32 gc, gm;
2727 osl_t *osh; 2727 osl_t *osh;
2728 2728
2729 regs = wlc_hw->regs; 2729 regs = wlc_hw->regs;
@@ -2813,7 +2813,7 @@ static void BCMATTACHFN(wlc_ucode_download) (wlc_hw_info_t *wlc_hw)
2813} 2813}
2814 2814
2815static void 2815static void
2816BCMATTACHFN(wlc_ucode_write) (wlc_hw_info_t *wlc_hw, const uint32 ucode[], 2816BCMATTACHFN(wlc_ucode_write) (wlc_hw_info_t *wlc_hw, const u32 ucode[],
2817 const uint nbytes) { 2817 const uint nbytes) {
2818 osl_t *osh; 2818 osl_t *osh;
2819 d11regs_t *regs = wlc_hw->regs; 2819 d11regs_t *regs = wlc_hw->regs;
@@ -2824,9 +2824,9 @@ BCMATTACHFN(wlc_ucode_write) (wlc_hw_info_t *wlc_hw, const uint32 ucode[],
2824 2824
2825 WL_TRACE(("wl%d: wlc_ucode_write\n", wlc_hw->unit)); 2825 WL_TRACE(("wl%d: wlc_ucode_write\n", wlc_hw->unit));
2826 2826
2827 ASSERT(ISALIGNED(nbytes, sizeof(uint32))); 2827 ASSERT(ISALIGNED(nbytes, sizeof(u32)));
2828 2828
2829 count = (nbytes / sizeof(uint32)); 2829 count = (nbytes / sizeof(u32));
2830 2830
2831 W_REG(osh, &regs->objaddr, (OBJADDR_AUTO_INC | OBJADDR_UCM_SEL)); 2831 W_REG(osh, &regs->objaddr, (OBJADDR_AUTO_INC | OBJADDR_UCM_SEL));
2832 (void)R_REG(osh, &regs->objaddr); 2832 (void)R_REG(osh, &regs->objaddr);
@@ -2852,7 +2852,7 @@ static void wlc_write_inits(wlc_hw_info_t *wlc_hw, const d11init_t *inits)
2852 W_REG(osh, (u16 *) (uintptr) (base + inits[i].addr), 2852 W_REG(osh, (u16 *) (uintptr) (base + inits[i].addr),
2853 inits[i].value); 2853 inits[i].value);
2854 else if (inits[i].size == 4) 2854 else if (inits[i].size == 4)
2855 W_REG(osh, (uint32 *) (uintptr) (base + inits[i].addr), 2855 W_REG(osh, (u32 *) (uintptr) (base + inits[i].addr),
2856 inits[i].value); 2856 inits[i].value);
2857 } 2857 }
2858} 2858}
@@ -2980,7 +2980,7 @@ void wlc_intrson(wlc_info_t *wlc)
2980 * but also because per-port code may require sync with valid interrupt. 2980 * but also because per-port code may require sync with valid interrupt.
2981 */ 2981 */
2982 2982
2983static uint32 wlc_wlintrsoff(wlc_info_t *wlc) 2983static u32 wlc_wlintrsoff(wlc_info_t *wlc)
2984{ 2984{
2985 if (!wlc->hw->up) 2985 if (!wlc->hw->up)
2986 return 0; 2986 return 0;
@@ -2988,7 +2988,7 @@ static uint32 wlc_wlintrsoff(wlc_info_t *wlc)
2988 return wl_intrsoff(wlc->wl); 2988 return wl_intrsoff(wlc->wl);
2989} 2989}
2990 2990
2991static void wlc_wlintrsrestore(wlc_info_t *wlc, uint32 macintmask) 2991static void wlc_wlintrsrestore(wlc_info_t *wlc, u32 macintmask)
2992{ 2992{
2993 if (!wlc->hw->up) 2993 if (!wlc->hw->up)
2994 return; 2994 return;
@@ -2996,10 +2996,10 @@ static void wlc_wlintrsrestore(wlc_info_t *wlc, uint32 macintmask)
2996 wl_intrsrestore(wlc->wl, macintmask); 2996 wl_intrsrestore(wlc->wl, macintmask);
2997} 2997}
2998 2998
2999uint32 wlc_intrsoff(wlc_info_t *wlc) 2999u32 wlc_intrsoff(wlc_info_t *wlc)
3000{ 3000{
3001 wlc_hw_info_t *wlc_hw = wlc->hw; 3001 wlc_hw_info_t *wlc_hw = wlc->hw;
3002 uint32 macintmask; 3002 u32 macintmask;
3003 3003
3004 if (!wlc_hw->clk) 3004 if (!wlc_hw->clk)
3005 return 0; 3005 return 0;
@@ -3015,7 +3015,7 @@ uint32 wlc_intrsoff(wlc_info_t *wlc)
3015 return wlc->macintstatus ? 0 : macintmask; 3015 return wlc->macintstatus ? 0 : macintmask;
3016} 3016}
3017 3017
3018void wlc_intrsrestore(wlc_info_t *wlc, uint32 macintmask) 3018void wlc_intrsrestore(wlc_info_t *wlc, u32 macintmask)
3019{ 3019{
3020 wlc_hw_info_t *wlc_hw = wlc->hw; 3020 wlc_hw_info_t *wlc_hw = wlc->hw;
3021 if (!wlc_hw->clk) 3021 if (!wlc_hw->clk)
@@ -3174,12 +3174,12 @@ void wlc_bmac_tx_fifo_resume(wlc_hw_info_t *wlc_hw, uint tx_fifo)
3174 * 0 if the interrupt is not for us, or we are in some special cases; 3174 * 0 if the interrupt is not for us, or we are in some special cases;
3175 * device interrupt status bits otherwise. 3175 * device interrupt status bits otherwise.
3176 */ 3176 */
3177static inline uint32 wlc_intstatus(wlc_info_t *wlc, bool in_isr) 3177static inline u32 wlc_intstatus(wlc_info_t *wlc, bool in_isr)
3178{ 3178{
3179 wlc_hw_info_t *wlc_hw = wlc->hw; 3179 wlc_hw_info_t *wlc_hw = wlc->hw;
3180 d11regs_t *regs = wlc_hw->regs; 3180 d11regs_t *regs = wlc_hw->regs;
3181 uint32 macintstatus; 3181 u32 macintstatus;
3182 uint32 intstatus_rxfifo, intstatus_txsfifo; 3182 u32 intstatus_rxfifo, intstatus_txsfifo;
3183 osl_t *osh; 3183 osl_t *osh;
3184 3184
3185 osh = wlc_hw->osh; 3185 osh = wlc_hw->osh;
@@ -3268,7 +3268,7 @@ static inline uint32 wlc_intstatus(wlc_info_t *wlc, bool in_isr)
3268/* Return TRUE if they are updated successfully. FALSE otherwise */ 3268/* Return TRUE if they are updated successfully. FALSE otherwise */
3269bool wlc_intrsupd(wlc_info_t *wlc) 3269bool wlc_intrsupd(wlc_info_t *wlc)
3270{ 3270{
3271 uint32 macintstatus; 3271 u32 macintstatus;
3272 3272
3273 ASSERT(wlc->macintstatus != 0); 3273 ASSERT(wlc->macintstatus != 0);
3274 3274
@@ -3294,7 +3294,7 @@ bool wlc_intrsupd(wlc_info_t *wlc)
3294bool BCMFASTPATH wlc_isr(wlc_info_t *wlc, bool *wantdpc) 3294bool BCMFASTPATH wlc_isr(wlc_info_t *wlc, bool *wantdpc)
3295{ 3295{
3296 wlc_hw_info_t *wlc_hw = wlc->hw; 3296 wlc_hw_info_t *wlc_hw = wlc->hw;
3297 uint32 macintstatus; 3297 u32 macintstatus;
3298 3298
3299 *wantdpc = FALSE; 3299 *wantdpc = FALSE;
3300 3300
@@ -3358,7 +3358,7 @@ static bool wlc_bmac_txstatus_corerev4(wlc_hw_info_t *wlc_hw)
3358} 3358}
3359 3359
3360static bool BCMFASTPATH 3360static bool BCMFASTPATH
3361wlc_bmac_dotxstatus(wlc_hw_info_t *wlc_hw, tx_status_t *txs, uint32 s2) 3361wlc_bmac_dotxstatus(wlc_hw_info_t *wlc_hw, tx_status_t *txs, u32 s2)
3362{ 3362{
3363 /* discard intermediate indications for ucode with one legitimate case: 3363 /* discard intermediate indications for ucode with one legitimate case:
3364 * e.g. if "useRTS" is set. ucode did a successful rts/cts exchange, but the subsequent 3364 * e.g. if "useRTS" is set. ucode did a successful rts/cts exchange, but the subsequent
@@ -3395,7 +3395,7 @@ wlc_bmac_txstatus(wlc_hw_info_t *wlc_hw, bool bound, bool *fatal)
3395 d11regs_t *regs; 3395 d11regs_t *regs;
3396 osl_t *osh; 3396 osl_t *osh;
3397 tx_status_t txstatus, *txs; 3397 tx_status_t txstatus, *txs;
3398 uint32 s1, s2; 3398 u32 s1, s2;
3399 uint n = 0; 3399 uint n = 0;
3400 /* Param 'max_tx_num' indicates max. # tx status to process before break out. */ 3400 /* Param 'max_tx_num' indicates max. # tx status to process before break out. */
3401 uint max_tx_num = bound ? wlc->pub->tunables->txsbnd : -1; 3401 uint max_tx_num = bound ? wlc->pub->tunables->txsbnd : -1;
@@ -3445,7 +3445,7 @@ void wlc_suspend_mac_and_wait(wlc_info_t *wlc)
3445{ 3445{
3446 wlc_hw_info_t *wlc_hw = wlc->hw; 3446 wlc_hw_info_t *wlc_hw = wlc->hw;
3447 d11regs_t *regs = wlc_hw->regs; 3447 d11regs_t *regs = wlc_hw->regs;
3448 uint32 mc, mi; 3448 u32 mc, mi;
3449 osl_t *osh; 3449 osl_t *osh;
3450 3450
3451 WL_TRACE(("wl%d: wlc_suspend_mac_and_wait: bandunit %d\n", wlc_hw->unit, 3451 WL_TRACE(("wl%d: wlc_suspend_mac_and_wait: bandunit %d\n", wlc_hw->unit,
@@ -3509,7 +3509,7 @@ void wlc_enable_mac(wlc_info_t *wlc)
3509{ 3509{
3510 wlc_hw_info_t *wlc_hw = wlc->hw; 3510 wlc_hw_info_t *wlc_hw = wlc->hw;
3511 d11regs_t *regs = wlc_hw->regs; 3511 d11regs_t *regs = wlc_hw->regs;
3512 uint32 mc, mi; 3512 u32 mc, mi;
3513 osl_t *osh; 3513 osl_t *osh;
3514 3514
3515 WL_TRACE(("wl%d: wlc_enable_mac: bandunit %d\n", wlc_hw->unit, 3515 WL_TRACE(("wl%d: wlc_enable_mac: bandunit %d\n", wlc_hw->unit,
@@ -3656,8 +3656,8 @@ void wlc_bmac_band_stf_ss_set(wlc_hw_info_t *wlc_hw, u8 stf_mode)
3656} 3656}
3657 3657
3658void BCMFASTPATH 3658void BCMFASTPATH
3659wlc_bmac_read_tsf(wlc_hw_info_t *wlc_hw, uint32 *tsf_l_ptr, 3659wlc_bmac_read_tsf(wlc_hw_info_t *wlc_hw, u32 *tsf_l_ptr,
3660 uint32 *tsf_h_ptr) 3660 u32 *tsf_h_ptr)
3661{ 3661{
3662 d11regs_t *regs = wlc_hw->regs; 3662 d11regs_t *regs = wlc_hw->regs;
3663 3663
@@ -3671,7 +3671,7 @@ wlc_bmac_read_tsf(wlc_hw_info_t *wlc_hw, uint32 *tsf_l_ptr,
3671bool BCMATTACHFN(wlc_bmac_validate_chip_access) (wlc_hw_info_t *wlc_hw) 3671bool BCMATTACHFN(wlc_bmac_validate_chip_access) (wlc_hw_info_t *wlc_hw)
3672{ 3672{
3673 d11regs_t *regs; 3673 d11regs_t *regs;
3674 uint32 w, val; 3674 u32 w, val;
3675 volatile u16 *reg16; 3675 volatile u16 *reg16;
3676 osl_t *osh; 3676 osl_t *osh;
3677 3677
@@ -3689,24 +3689,24 @@ bool BCMATTACHFN(wlc_bmac_validate_chip_access) (wlc_hw_info_t *wlc_hw)
3689 /* Can we write and read back a 32bit register? */ 3689 /* Can we write and read back a 32bit register? */
3690 W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0); 3690 W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3691 (void)R_REG(osh, &regs->objaddr); 3691 (void)R_REG(osh, &regs->objaddr);
3692 W_REG(osh, &regs->objdata, (uint32) 0xaa5555aa); 3692 W_REG(osh, &regs->objdata, (u32) 0xaa5555aa);
3693 3693
3694 W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0); 3694 W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3695 (void)R_REG(osh, &regs->objaddr); 3695 (void)R_REG(osh, &regs->objaddr);
3696 val = R_REG(osh, &regs->objdata); 3696 val = R_REG(osh, &regs->objdata);
3697 if (val != (uint32) 0xaa5555aa) { 3697 if (val != (u32) 0xaa5555aa) {
3698 WL_ERROR(("wl%d: validate_chip_access: SHM = 0x%x, expected 0xaa5555aa\n", wlc_hw->unit, val)); 3698 WL_ERROR(("wl%d: validate_chip_access: SHM = 0x%x, expected 0xaa5555aa\n", wlc_hw->unit, val));
3699 return FALSE; 3699 return FALSE;
3700 } 3700 }
3701 3701
3702 W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0); 3702 W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3703 (void)R_REG(osh, &regs->objaddr); 3703 (void)R_REG(osh, &regs->objaddr);
3704 W_REG(osh, &regs->objdata, (uint32) 0x55aaaa55); 3704 W_REG(osh, &regs->objdata, (u32) 0x55aaaa55);
3705 3705
3706 W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0); 3706 W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3707 (void)R_REG(osh, &regs->objaddr); 3707 (void)R_REG(osh, &regs->objaddr);
3708 val = R_REG(osh, &regs->objdata); 3708 val = R_REG(osh, &regs->objdata);
3709 if (val != (uint32) 0x55aaaa55) { 3709 if (val != (u32) 0x55aaaa55) {
3710 WL_ERROR(("wl%d: validate_chip_access: SHM = 0x%x, expected 0x55aaaa55\n", wlc_hw->unit, val)); 3710 WL_ERROR(("wl%d: validate_chip_access: SHM = 0x%x, expected 0x55aaaa55\n", wlc_hw->unit, val));
3711 return FALSE; 3711 return FALSE;
3712 } 3712 }
@@ -3767,7 +3767,7 @@ void wlc_bmac_core_phypll_ctl(wlc_hw_info_t *wlc_hw, bool on)
3767{ 3767{
3768 d11regs_t *regs; 3768 d11regs_t *regs;
3769 osl_t *osh; 3769 osl_t *osh;
3770 uint32 tmp; 3770 u32 tmp;
3771 3771
3772 WL_TRACE(("wl%d: wlc_bmac_core_phypll_ctl\n", wlc_hw->unit)); 3772 WL_TRACE(("wl%d: wlc_bmac_core_phypll_ctl\n", wlc_hw->unit));
3773 3773
@@ -3934,7 +3934,7 @@ void wlc_bmac_set_shm(wlc_hw_info_t *wlc_hw, uint offset, u16 v, int len)
3934} 3934}
3935 3935
3936static u16 3936static u16
3937wlc_bmac_read_objmem(wlc_hw_info_t *wlc_hw, uint offset, uint32 sel) 3937wlc_bmac_read_objmem(wlc_hw_info_t *wlc_hw, uint offset, u32 sel)
3938{ 3938{
3939 d11regs_t *regs = wlc_hw->regs; 3939 d11regs_t *regs = wlc_hw->regs;
3940 volatile u16 *objdata_lo = 3940 volatile u16 *objdata_lo =
@@ -3956,7 +3956,7 @@ wlc_bmac_read_objmem(wlc_hw_info_t *wlc_hw, uint offset, uint32 sel)
3956} 3956}
3957 3957
3958static void 3958static void
3959wlc_bmac_write_objmem(wlc_hw_info_t *wlc_hw, uint offset, u16 v, uint32 sel) 3959wlc_bmac_write_objmem(wlc_hw_info_t *wlc_hw, uint offset, u16 v, u32 sel)
3960{ 3960{
3961 d11regs_t *regs = wlc_hw->regs; 3961 d11regs_t *regs = wlc_hw->regs;
3962 volatile u16 *objdata_lo = 3962 volatile u16 *objdata_lo =
@@ -3981,7 +3981,7 @@ wlc_bmac_write_objmem(wlc_hw_info_t *wlc_hw, uint offset, u16 v, uint32 sel)
3981 */ 3981 */
3982void 3982void
3983wlc_bmac_copyto_objmem(wlc_hw_info_t *wlc_hw, uint offset, const void *buf, 3983wlc_bmac_copyto_objmem(wlc_hw_info_t *wlc_hw, uint offset, const void *buf,
3984 int len, uint32 sel) 3984 int len, u32 sel)
3985{ 3985{
3986 u16 v; 3986 u16 v;
3987 const u8 *p = (const u8 *)buf; 3987 const u8 *p = (const u8 *)buf;
@@ -4007,7 +4007,7 @@ wlc_bmac_copyto_objmem(wlc_hw_info_t *wlc_hw, uint offset, const void *buf,
4007 */ 4007 */
4008void 4008void
4009wlc_bmac_copyfrom_objmem(wlc_hw_info_t *wlc_hw, uint offset, void *buf, 4009wlc_bmac_copyfrom_objmem(wlc_hw_info_t *wlc_hw, uint offset, void *buf,
4010 int len, uint32 sel) 4010 int len, u32 sel)
4011{ 4011{
4012 u16 v; 4012 u16 v;
4013 u8 *p = (u8 *) buf; 4013 u8 *p = (u8 *) buf;
@@ -4207,7 +4207,7 @@ void wlc_bmac_set_txpwr_percent(wlc_hw_info_t *wlc_hw, u8 val)
4207 wlc_phy_txpwr_percent_set(wlc_hw->band->pi, val); 4207 wlc_phy_txpwr_percent_set(wlc_hw->band->pi, val);
4208} 4208}
4209 4209
4210void wlc_bmac_antsel_set(wlc_hw_info_t *wlc_hw, uint32 antsel_avail) 4210void wlc_bmac_antsel_set(wlc_hw_info_t *wlc_hw, u32 antsel_avail)
4211{ 4211{
4212 wlc_hw->antsel_avail = antsel_avail; 4212 wlc_hw->antsel_avail = antsel_avail;
4213} 4213}
diff --git a/drivers/staging/brcm80211/sys/wlc_bmac.h b/drivers/staging/brcm80211/sys/wlc_bmac.h
index 056d2e4a00d..872bc8d866d 100644
--- a/drivers/staging/brcm80211/sys/wlc_bmac.h
+++ b/drivers/staging/brcm80211/sys/wlc_bmac.h
@@ -41,7 +41,7 @@ typedef struct wlc_bmac_revinfo {
41 uint bustype; /* SB_BUS, PCI_BUS */ 41 uint bustype; /* SB_BUS, PCI_BUS */
42 uint buscoretype; /* PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */ 42 uint buscoretype; /* PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */
43 uint buscorerev; /* buscore rev */ 43 uint buscorerev; /* buscore rev */
44 uint32 issim; /* chip is in simulation or emulation */ 44 u32 issim; /* chip is in simulation or emulation */
45 45
46 uint nbands; 46 uint nbands;
47 47
@@ -59,8 +59,8 @@ typedef struct wlc_bmac_revinfo {
59 59
60/* dup state between BMAC(wlc_hw_info_t) and HIGH(wlc_info_t) driver */ 60/* dup state between BMAC(wlc_hw_info_t) and HIGH(wlc_info_t) driver */
61typedef struct wlc_bmac_state { 61typedef struct wlc_bmac_state {
62 uint32 machwcap; /* mac hw capibility */ 62 u32 machwcap; /* mac hw capibility */
63 uint32 preamble_ovr; /* preamble override */ 63 u32 preamble_ovr; /* preamble override */
64} wlc_bmac_state_t; 64} wlc_bmac_state_t;
65 65
66enum { 66enum {
@@ -144,9 +144,9 @@ extern void wlc_bmac_xtal(wlc_hw_info_t *wlc_hw, bool want);
144 144
145extern void wlc_bmac_copyto_objmem(wlc_hw_info_t *wlc_hw, 145extern void wlc_bmac_copyto_objmem(wlc_hw_info_t *wlc_hw,
146 uint offset, const void *buf, int len, 146 uint offset, const void *buf, int len,
147 uint32 sel); 147 u32 sel);
148extern void wlc_bmac_copyfrom_objmem(wlc_hw_info_t *wlc_hw, uint offset, 148extern void wlc_bmac_copyfrom_objmem(wlc_hw_info_t *wlc_hw, uint offset,
149 void *buf, int len, uint32 sel); 149 void *buf, int len, u32 sel);
150#define wlc_bmac_copyfrom_shm(wlc_hw, offset, buf, len) \ 150#define wlc_bmac_copyfrom_shm(wlc_hw, offset, buf, len) \
151 wlc_bmac_copyfrom_objmem(wlc_hw, offset, buf, len, OBJADDR_SHM_SEL) 151 wlc_bmac_copyfrom_objmem(wlc_hw, offset, buf, len, OBJADDR_SHM_SEL)
152#define wlc_bmac_copyto_shm(wlc_hw, offset, buf, len) \ 152#define wlc_bmac_copyto_shm(wlc_hw, offset, buf, len) \
@@ -158,7 +158,7 @@ extern void wlc_bmac_core_phypll_ctl(wlc_hw_info_t *wlc_hw, bool on);
158extern void wlc_bmac_phyclk_fgc(wlc_hw_info_t *wlc_hw, bool clk); 158extern void wlc_bmac_phyclk_fgc(wlc_hw_info_t *wlc_hw, bool clk);
159extern void wlc_bmac_macphyclk_set(wlc_hw_info_t *wlc_hw, bool clk); 159extern void wlc_bmac_macphyclk_set(wlc_hw_info_t *wlc_hw, bool clk);
160extern void wlc_bmac_phy_reset(wlc_hw_info_t *wlc_hw); 160extern void wlc_bmac_phy_reset(wlc_hw_info_t *wlc_hw);
161extern void wlc_bmac_corereset(wlc_hw_info_t *wlc_hw, uint32 flags); 161extern void wlc_bmac_corereset(wlc_hw_info_t *wlc_hw, u32 flags);
162extern void wlc_bmac_reset(wlc_hw_info_t *wlc_hw); 162extern void wlc_bmac_reset(wlc_hw_info_t *wlc_hw);
163extern void wlc_bmac_init(wlc_hw_info_t *wlc_hw, chanspec_t chanspec, 163extern void wlc_bmac_init(wlc_hw_info_t *wlc_hw, chanspec_t chanspec,
164 bool mute); 164 bool mute);
@@ -166,7 +166,7 @@ extern int wlc_bmac_up_prep(wlc_hw_info_t *wlc_hw);
166extern int wlc_bmac_up_finish(wlc_hw_info_t *wlc_hw); 166extern int wlc_bmac_up_finish(wlc_hw_info_t *wlc_hw);
167extern int wlc_bmac_down_prep(wlc_hw_info_t *wlc_hw); 167extern int wlc_bmac_down_prep(wlc_hw_info_t *wlc_hw);
168extern int wlc_bmac_down_finish(wlc_hw_info_t *wlc_hw); 168extern int wlc_bmac_down_finish(wlc_hw_info_t *wlc_hw);
169extern void wlc_bmac_corereset(wlc_hw_info_t *wlc_hw, uint32 flags); 169extern void wlc_bmac_corereset(wlc_hw_info_t *wlc_hw, u32 flags);
170extern void wlc_bmac_switch_macfreq(wlc_hw_info_t *wlc_hw, u8 spurmode); 170extern void wlc_bmac_switch_macfreq(wlc_hw_info_t *wlc_hw, u8 spurmode);
171 171
172/* chanspec, ucode interface */ 172/* chanspec, ucode interface */
@@ -180,7 +180,7 @@ extern int wlc_bmac_xmtfifo_sz_get(wlc_hw_info_t *wlc_hw, uint fifo,
180 uint *blocks); 180 uint *blocks);
181extern void wlc_bmac_mhf(wlc_hw_info_t *wlc_hw, u8 idx, u16 mask, 181extern void wlc_bmac_mhf(wlc_hw_info_t *wlc_hw, u8 idx, u16 mask,
182 u16 val, int bands); 182 u16 val, int bands);
183extern void wlc_bmac_mctrl(wlc_hw_info_t *wlc_hw, uint32 mask, uint32 val); 183extern void wlc_bmac_mctrl(wlc_hw_info_t *wlc_hw, u32 mask, u32 val);
184extern u16 wlc_bmac_mhf_get(wlc_hw_info_t *wlc_hw, u8 idx, int bands); 184extern u16 wlc_bmac_mhf_get(wlc_hw_info_t *wlc_hw, u8 idx, int bands);
185extern int wlc_bmac_xmtfifo_sz_set(wlc_hw_info_t *wlc_hw, uint fifo, 185extern int wlc_bmac_xmtfifo_sz_set(wlc_hw_info_t *wlc_hw, uint fifo,
186 uint blocks); 186 uint blocks);
@@ -219,9 +219,9 @@ extern void wlc_bmac_tx_fifo_suspend(wlc_hw_info_t *wlc_hw, uint tx_fifo);
219extern void wlc_bmac_tx_fifo_resume(wlc_hw_info_t *wlc_hw, uint tx_fifo); 219extern void wlc_bmac_tx_fifo_resume(wlc_hw_info_t *wlc_hw, uint tx_fifo);
220 220
221extern void wlc_ucode_wake_override_set(wlc_hw_info_t *wlc_hw, 221extern void wlc_ucode_wake_override_set(wlc_hw_info_t *wlc_hw,
222 uint32 override_bit); 222 u32 override_bit);
223extern void wlc_ucode_wake_override_clear(wlc_hw_info_t *wlc_hw, 223extern void wlc_ucode_wake_override_clear(wlc_hw_info_t *wlc_hw,
224 uint32 override_bit); 224 u32 override_bit);
225 225
226extern void wlc_bmac_set_rcmta(wlc_hw_info_t *wlc_hw, int idx, 226extern void wlc_bmac_set_rcmta(wlc_hw_info_t *wlc_hw, int idx,
227 const struct ether_addr *addr); 227 const struct ether_addr *addr);
@@ -230,8 +230,8 @@ extern void wlc_bmac_set_addrmatch(wlc_hw_info_t *wlc_hw, int match_reg_offset,
230extern void wlc_bmac_write_hw_bcntemplates(wlc_hw_info_t *wlc_hw, void *bcn, 230extern void wlc_bmac_write_hw_bcntemplates(wlc_hw_info_t *wlc_hw, void *bcn,
231 int len, bool both); 231 int len, bool both);
232 232
233extern void wlc_bmac_read_tsf(wlc_hw_info_t *wlc_hw, uint32 *tsf_l_ptr, 233extern void wlc_bmac_read_tsf(wlc_hw_info_t *wlc_hw, u32 *tsf_l_ptr,
234 uint32 *tsf_h_ptr); 234 u32 *tsf_h_ptr);
235extern void wlc_bmac_set_cwmin(wlc_hw_info_t *wlc_hw, u16 newmin); 235extern void wlc_bmac_set_cwmin(wlc_hw_info_t *wlc_hw, u16 newmin);
236extern void wlc_bmac_set_cwmax(wlc_hw_info_t *wlc_hw, u16 newmax); 236extern void wlc_bmac_set_cwmax(wlc_hw_info_t *wlc_hw, u16 newmax);
237extern void wlc_bmac_set_noreset(wlc_hw_info_t *wlc, bool noreset_flag); 237extern void wlc_bmac_set_noreset(wlc_hw_info_t *wlc, bool noreset_flag);
@@ -246,10 +246,10 @@ extern void wlc_bmac_fifoerrors(wlc_hw_info_t *wlc_hw);
246extern void wlc_bmac_dngl_reboot(rpc_info_t *); 246extern void wlc_bmac_dngl_reboot(rpc_info_t *);
247extern void wlc_bmac_dngl_rpc_agg(rpc_info_t *, u16 agg); 247extern void wlc_bmac_dngl_rpc_agg(rpc_info_t *, u16 agg);
248extern void wlc_bmac_dngl_rpc_msglevel(rpc_info_t *, u16 level); 248extern void wlc_bmac_dngl_rpc_msglevel(rpc_info_t *, u16 level);
249extern void wlc_bmac_dngl_rpc_txq_wm_set(rpc_info_t *rpc, uint32 wm); 249extern void wlc_bmac_dngl_rpc_txq_wm_set(rpc_info_t *rpc, u32 wm);
250extern void wlc_bmac_dngl_rpc_txq_wm_get(rpc_info_t *rpc, uint32 *wm); 250extern void wlc_bmac_dngl_rpc_txq_wm_get(rpc_info_t *rpc, u32 *wm);
251extern void wlc_bmac_dngl_rpc_agg_limit_set(rpc_info_t *rpc, uint32 val); 251extern void wlc_bmac_dngl_rpc_agg_limit_set(rpc_info_t *rpc, u32 val);
252extern void wlc_bmac_dngl_rpc_agg_limit_get(rpc_info_t *rpc, uint32 *pval); 252extern void wlc_bmac_dngl_rpc_agg_limit_get(rpc_info_t *rpc, u32 *pval);
253extern int wlc_bmac_debug_template(wlc_hw_info_t *wlc_hw); 253extern int wlc_bmac_debug_template(wlc_hw_info_t *wlc_hw);
254#endif 254#endif
255 255
@@ -268,10 +268,10 @@ extern void wlc_gpio_fast_deinit(wlc_hw_info_t *wlc_hw);
268extern bool wlc_bmac_radio_hw(wlc_hw_info_t *wlc_hw, bool enable); 268extern bool wlc_bmac_radio_hw(wlc_hw_info_t *wlc_hw, bool enable);
269extern u16 wlc_bmac_rate_shm_offset(wlc_hw_info_t *wlc_hw, u8 rate); 269extern u16 wlc_bmac_rate_shm_offset(wlc_hw_info_t *wlc_hw, u8 rate);
270 270
271extern void wlc_bmac_assert_type_set(wlc_hw_info_t *wlc_hw, uint32 type); 271extern void wlc_bmac_assert_type_set(wlc_hw_info_t *wlc_hw, u32 type);
272extern void wlc_bmac_set_txpwr_percent(wlc_hw_info_t *wlc_hw, u8 val); 272extern void wlc_bmac_set_txpwr_percent(wlc_hw_info_t *wlc_hw, u8 val);
273extern void wlc_bmac_blink_sync(wlc_hw_info_t *wlc_hw, uint32 led_pins); 273extern void wlc_bmac_blink_sync(wlc_hw_info_t *wlc_hw, u32 led_pins);
274extern void wlc_bmac_ifsctl_edcrs_set(wlc_hw_info_t *wlc_hw, bool abie, 274extern void wlc_bmac_ifsctl_edcrs_set(wlc_hw_info_t *wlc_hw, bool abie,
275 bool isht); 275 bool isht);
276 276
277extern void wlc_bmac_antsel_set(wlc_hw_info_t *wlc_hw, uint32 antsel_avail); 277extern void wlc_bmac_antsel_set(wlc_hw_info_t *wlc_hw, u32 antsel_avail);
diff --git a/drivers/staging/brcm80211/sys/wlc_bsscfg.h b/drivers/staging/brcm80211/sys/wlc_bsscfg.h
index 54e35432f39..a821ff6e4d8 100644
--- a/drivers/staging/brcm80211/sys/wlc_bsscfg.h
+++ b/drivers/staging/brcm80211/sys/wlc_bsscfg.h
@@ -73,7 +73,7 @@ struct wlc_bsscfg {
73 struct ether_addr *maclist; /* list of source MAC addrs to match */ 73 struct ether_addr *maclist; /* list of source MAC addrs to match */
74 74
75 /* security */ 75 /* security */
76 uint32 wsec; /* wireless security bitvec */ 76 u32 wsec; /* wireless security bitvec */
77 s16 auth; /* 802.11 authentication: Open, Shared Key, WPA */ 77 s16 auth; /* 802.11 authentication: Open, Shared Key, WPA */
78 s16 openshared; /* try Open auth first, then Shared Key */ 78 s16 openshared; /* try Open auth first, then Shared Key */
79 bool wsec_restrict; /* drop unencrypted packets if wsec is enabled */ 79 bool wsec_restrict; /* drop unencrypted packets if wsec is enabled */
@@ -87,9 +87,9 @@ struct wlc_bsscfg {
87 87
88 /* TKIP countermeasures */ 88 /* TKIP countermeasures */
89 bool tkip_countermeasures; /* flags TKIP no-assoc period */ 89 bool tkip_countermeasures; /* flags TKIP no-assoc period */
90 uint32 tk_cm_dt; /* detect timer */ 90 u32 tk_cm_dt; /* detect timer */
91 uint32 tk_cm_bt; /* blocking timer */ 91 u32 tk_cm_bt; /* blocking timer */
92 uint32 tk_cm_bt_tmstmp; /* Timestamp when TKIP BT is activated */ 92 u32 tk_cm_bt_tmstmp; /* Timestamp when TKIP BT is activated */
93 bool tk_cm_activate; /* activate countermeasures after EAPOL-Key sent */ 93 bool tk_cm_activate; /* activate countermeasures after EAPOL-Key sent */
94 94
95 struct ether_addr BSSID; /* BSSID (associated) */ 95 struct ether_addr BSSID; /* BSSID (associated) */
@@ -97,7 +97,7 @@ struct wlc_bsscfg {
97 u16 bcmc_fid; /* the last BCMC FID queued to TX_BCMC_FIFO */ 97 u16 bcmc_fid; /* the last BCMC FID queued to TX_BCMC_FIFO */
98 u16 bcmc_fid_shm; /* the last BCMC FID written to shared mem */ 98 u16 bcmc_fid_shm; /* the last BCMC FID written to shared mem */
99 99
100 uint32 flags; /* WLC_BSSCFG flags; see below */ 100 u32 flags; /* WLC_BSSCFG flags; see below */
101 101
102 u8 *bcn; /* AP beacon */ 102 u8 *bcn; /* AP beacon */
103 uint bcn_len; /* AP beacon length */ 103 uint bcn_len; /* AP beacon length */
diff --git a/drivers/staging/brcm80211/sys/wlc_channel.h b/drivers/staging/brcm80211/sys/wlc_channel.h
index e4fc1b82218..1f170aff68f 100644
--- a/drivers/staging/brcm80211/sys/wlc_channel.h
+++ b/drivers/staging/brcm80211/sys/wlc_channel.h
@@ -54,7 +54,7 @@ struct wlc_info;
54 54
55/* locale channel and power info. */ 55/* locale channel and power info. */
56typedef struct { 56typedef struct {
57 uint32 valid_channels; 57 u32 valid_channels;
58 u8 radar_channels; /* List of radar sensitive channels */ 58 u8 radar_channels; /* List of radar sensitive channels */
59 u8 restricted_channels; /* List of channels used only if APs are detected */ 59 u8 restricted_channels; /* List of channels used only if APs are detected */
60 s8 maxpwr[WLC_MAXPWR_TBL_SIZE]; /* Max tx pwr in qdBm for each sub-band */ 60 s8 maxpwr[WLC_MAXPWR_TBL_SIZE]; /* Max tx pwr in qdBm for each sub-band */
diff --git a/drivers/staging/brcm80211/sys/wlc_event.h b/drivers/staging/brcm80211/sys/wlc_event.h
index 5921bba318f..e443dae258b 100644
--- a/drivers/staging/brcm80211/sys/wlc_event.h
+++ b/drivers/staging/brcm80211/sys/wlc_event.h
@@ -40,7 +40,7 @@ extern int wlc_eventq_set_ind(wlc_eventq_t *eq, uint et, bool on);
40extern void wlc_eventq_flush(wlc_eventq_t *eq); 40extern void wlc_eventq_flush(wlc_eventq_t *eq);
41extern void wlc_assign_event_msg(wlc_info_t *wlc, wl_event_msg_t *msg, 41extern void wlc_assign_event_msg(wlc_info_t *wlc, wl_event_msg_t *msg,
42 const wlc_event_t *e, u8 *data, 42 const wlc_event_t *e, u8 *data,
43 uint32 len); 43 u32 len);
44 44
45#ifdef MSGTRACE 45#ifdef MSGTRACE
46extern void wlc_event_sendup_trace(struct wlc_info *wlc, hndrte_dev_t *bus, 46extern void wlc_event_sendup_trace(struct wlc_info *wlc, hndrte_dev_t *bus,
diff --git a/drivers/staging/brcm80211/sys/wlc_key.h b/drivers/staging/brcm80211/sys/wlc_key.h
index ce251c0802c..61dd5e42f72 100644
--- a/drivers/staging/brcm80211/sys/wlc_key.h
+++ b/drivers/staging/brcm80211/sys/wlc_key.h
@@ -80,7 +80,7 @@ struct wlc_bsscfg;
80#define WSEC_BSS_STA_KEY_GROUP_SIZE 5 80#define WSEC_BSS_STA_KEY_GROUP_SIZE 5
81 81
82typedef struct wsec_iv { 82typedef struct wsec_iv {
83 uint32 hi; /* upper 32 bits of IV */ 83 u32 hi; /* upper 32 bits of IV */
84 u16 lo; /* lower 16 bits of IV */ 84 u16 lo; /* lower 16 bits of IV */
85} wsec_iv_t; 85} wsec_iv_t;
86 86
@@ -97,7 +97,7 @@ typedef struct wsec_key {
97 u8 aes_mode; /* cache for hw register */ 97 u8 aes_mode; /* cache for hw register */
98 s8 iv_len; /* IV length */ 98 s8 iv_len; /* IV length */
99 s8 icv_len; /* ICV length */ 99 s8 icv_len; /* ICV length */
100 uint32 len; /* key length..don't move this var */ 100 u32 len; /* key length..don't move this var */
101 /* data is 4byte aligned */ 101 /* data is 4byte aligned */
102 u8 data[DOT11_MAX_KEY_SIZE]; /* key data */ 102 u8 data[DOT11_MAX_KEY_SIZE]; /* key data */
103 wsec_iv_t rxiv[WLC_NUMRXIVS]; /* Rx IV (one per TID) */ 103 wsec_iv_t rxiv[WLC_NUMRXIVS]; /* Rx IV (one per TID) */
diff --git a/drivers/staging/brcm80211/sys/wlc_mac80211.c b/drivers/staging/brcm80211/sys/wlc_mac80211.c
index 15d84cb9c54..f632f35b3b4 100644
--- a/drivers/staging/brcm80211/sys/wlc_mac80211.c
+++ b/drivers/staging/brcm80211/sys/wlc_mac80211.c
@@ -262,12 +262,12 @@ void wlc_wme_setparams(wlc_info_t *wlc, u16 aci, void *arg, bool suspend);
262static void wlc_bss_default_init(wlc_info_t *wlc); 262static void wlc_bss_default_init(wlc_info_t *wlc);
263static void wlc_ucode_mac_upd(wlc_info_t *wlc); 263static void wlc_ucode_mac_upd(wlc_info_t *wlc);
264static ratespec_t mac80211_wlc_set_nrate(wlc_info_t *wlc, wlcband_t *cur_band, 264static ratespec_t mac80211_wlc_set_nrate(wlc_info_t *wlc, wlcband_t *cur_band,
265 uint32 int_val); 265 u32 int_val);
266static void wlc_tx_prec_map_init(wlc_info_t *wlc); 266static void wlc_tx_prec_map_init(wlc_info_t *wlc);
267static void wlc_watchdog(void *arg); 267static void wlc_watchdog(void *arg);
268static void wlc_watchdog_by_timer(void *arg); 268static void wlc_watchdog_by_timer(void *arg);
269static int wlc_set_rateset(wlc_info_t *wlc, wlc_rateset_t *rs_arg); 269static int wlc_set_rateset(wlc_info_t *wlc, wlc_rateset_t *rs_arg);
270static int wlc_iovar_rangecheck(wlc_info_t *wlc, uint32 val, 270static int wlc_iovar_rangecheck(wlc_info_t *wlc, u32 val,
271 const bcm_iovar_t *vi); 271 const bcm_iovar_t *vi);
272static u8 wlc_local_constraint_qdbm(wlc_info_t *wlc); 272static u8 wlc_local_constraint_qdbm(wlc_info_t *wlc);
273 273
@@ -330,7 +330,7 @@ static int _wlc_ioctl(wlc_info_t *wlc, int cmd, void *arg, int len,
330void wlc_get_rcmta(wlc_info_t *wlc, int idx, struct ether_addr *addr) 330void wlc_get_rcmta(wlc_info_t *wlc, int idx, struct ether_addr *addr)
331{ 331{
332 d11regs_t *regs = wlc->regs; 332 d11regs_t *regs = wlc->regs;
333 uint32 v32; 333 u32 v32;
334 osl_t *osh; 334 osl_t *osh;
335 335
336 WL_TRACE(("wl%d: %s\n", WLCWLUNIT(wlc), __func__)); 336 WL_TRACE(("wl%d: %s\n", WLCWLUNIT(wlc), __func__));
@@ -506,7 +506,7 @@ void BCMINITFN(wlc_init) (wlc_info_t *wlc)
506 if (wlc->pub->associated) { 506 if (wlc->pub->associated) {
507 FOREACH_BSS(wlc, i, bsscfg) { 507 FOREACH_BSS(wlc, i, bsscfg) {
508 if (bsscfg->up) { 508 if (bsscfg->up) {
509 uint32 bi; 509 u32 bi;
510 510
511 /* get beacon period from bsscfg and convert to uS */ 511 /* get beacon period from bsscfg and convert to uS */
512 bi = bsscfg->current_bss->beacon_period << 10; 512 bi = bsscfg->current_bss->beacon_period << 10;
@@ -612,7 +612,7 @@ void wlc_mac_bcn_promisc(wlc_info_t *wlc)
612/* set or clear maccontrol bits MCTL_PROMISC and MCTL_KEEPCONTROL */ 612/* set or clear maccontrol bits MCTL_PROMISC and MCTL_KEEPCONTROL */
613void wlc_mac_promisc(wlc_info_t *wlc) 613void wlc_mac_promisc(wlc_info_t *wlc)
614{ 614{
615 uint32 promisc_bits = 0; 615 u32 promisc_bits = 0;
616 616
617 /* promiscuous mode just sets MCTL_PROMISC 617 /* promiscuous mode just sets MCTL_PROMISC
618 * Note: APs get all BSS traffic without the need to set the MCTL_PROMISC bit 618 * Note: APs get all BSS traffic without the need to set the MCTL_PROMISC bit
@@ -639,7 +639,7 @@ bool wlc_ps_check(wlc_info_t *wlc)
639 bool wake_ok; 639 bool wake_ok;
640 640
641 if (!AP_ACTIVE(wlc)) { 641 if (!AP_ACTIVE(wlc)) {
642 volatile uint32 tmp; 642 volatile u32 tmp;
643 tmp = R_REG(wlc->osh, &wlc->regs->maccontrol); 643 tmp = R_REG(wlc->osh, &wlc->regs->maccontrol);
644 644
645 /* If deviceremoved is detected, then don't take any action as this can be called 645 /* If deviceremoved is detected, then don't take any action as this can be called
@@ -692,7 +692,7 @@ bool wlc_ps_check(wlc_info_t *wlc)
692/* push sw hps and wake state through hardware */ 692/* push sw hps and wake state through hardware */
693void wlc_set_ps_ctrl(wlc_info_t *wlc) 693void wlc_set_ps_ctrl(wlc_info_t *wlc)
694{ 694{
695 uint32 v1, v2; 695 u32 v1, v2;
696 bool hps, wake; 696 bool hps, wake;
697 bool awake_before; 697 bool awake_before;
698 698
@@ -1075,9 +1075,9 @@ static int wlc_get_current_txpwr(wlc_info_t *wlc, void *pwr, uint len)
1075} 1075}
1076#endif /* defined(BCMDBG) */ 1076#endif /* defined(BCMDBG) */
1077 1077
1078static uint32 wlc_watchdog_backup_bi(wlc_info_t *wlc) 1078static u32 wlc_watchdog_backup_bi(wlc_info_t *wlc)
1079{ 1079{
1080 uint32 bi; 1080 u32 bi;
1081 bi = 2 * wlc->cfg->current_bss->dtim_period * 1081 bi = 2 * wlc->cfg->current_bss->dtim_period *
1082 wlc->cfg->current_bss->beacon_period; 1082 wlc->cfg->current_bss->beacon_period;
1083 if (wlc->bcn_li_dtim) 1083 if (wlc->bcn_li_dtim)
@@ -1793,7 +1793,7 @@ void *BCMATTACHFN(wlc_attach) (void *wl, u16 vendor, u16 device,
1793 ASSERT(sizeof(ht_cap_ie_t) == HT_CAP_IE_LEN); 1793 ASSERT(sizeof(ht_cap_ie_t) == HT_CAP_IE_LEN);
1794 ASSERT(OFFSETOF(wl_scan_params_t, channel_list) == 1794 ASSERT(OFFSETOF(wl_scan_params_t, channel_list) ==
1795 WL_SCAN_PARAMS_FIXED_SIZE); 1795 WL_SCAN_PARAMS_FIXED_SIZE);
1796 ASSERT(ISALIGNED(OFFSETOF(wsec_key_t, data), sizeof(uint32))); 1796 ASSERT(ISALIGNED(OFFSETOF(wsec_key_t, data), sizeof(u32)));
1797 ASSERT(ISPOWEROF2(MA_WINDOW_SZ)); 1797 ASSERT(ISPOWEROF2(MA_WINDOW_SZ));
1798 1798
1799 ASSERT(sizeof(wlc_d11rxhdr_t) <= WL_HWRXOFF); 1799 ASSERT(sizeof(wlc_d11rxhdr_t) <= WL_HWRXOFF);
@@ -3304,7 +3304,7 @@ _wlc_ioctl(wlc_info_t *wlc, int cmd, void *arg, int len, struct wlc_if *wlcif)
3304 pval = arg ? (int *)arg:NULL; 3304 pval = arg ? (int *)arg:NULL;
3305 3305
3306 /* This will prevent the misaligned access */ 3306 /* This will prevent the misaligned access */
3307 if (pval && (uint32) len >= sizeof(val)) 3307 if (pval && (u32) len >= sizeof(val))
3308 bcopy(pval, &val, sizeof(val)); 3308 bcopy(pval, &val, sizeof(val));
3309 else 3309 else
3310 val = 0; 3310 val = 0;
@@ -3524,10 +3524,10 @@ _wlc_ioctl(wlc_info_t *wlc, int cmd, void *arg, int len, struct wlc_if *wlcif)
3524 bcmerror = BCME_BADADDR; 3524 bcmerror = BCME_BADADDR;
3525 break; 3525 break;
3526 } 3526 }
3527 if (r->size == sizeof(uint32)) 3527 if (r->size == sizeof(u32))
3528 r->val = 3528 r->val =
3529 R_REG(osh, 3529 R_REG(osh,
3530 (uint32 *) ((unsigned char *) (uintptr) regs + 3530 (u32 *) ((unsigned char *) (uintptr) regs +
3531 r->byteoff)); 3531 r->byteoff));
3532 else if (r->size == sizeof(u16)) 3532 else if (r->size == sizeof(u16))
3533 r->val = 3533 r->val =
@@ -3560,9 +3560,9 @@ _wlc_ioctl(wlc_info_t *wlc, int cmd, void *arg, int len, struct wlc_if *wlcif)
3560 bcmerror = BCME_BADADDR; 3560 bcmerror = BCME_BADADDR;
3561 break; 3561 break;
3562 } 3562 }
3563 if (r->size == sizeof(uint32)) 3563 if (r->size == sizeof(u32))
3564 W_REG(osh, 3564 W_REG(osh,
3565 (uint32 *) ((unsigned char *) (uintptr) regs + 3565 (u32 *) ((unsigned char *) (uintptr) regs +
3566 r->byteoff), r->val); 3566 r->byteoff), r->val);
3567 else if (r->size == sizeof(u16)) 3567 else if (r->size == sizeof(u16))
3568 W_REG(osh, 3568 W_REG(osh,
@@ -3846,7 +3846,7 @@ _wlc_ioctl(wlc_info_t *wlc, int cmd, void *arg, int len, struct wlc_if *wlcif)
3846 (key != NULL)) { 3846 (key != NULL)) {
3847 u8 seq[DOT11_WPA_KEY_RSC_LEN]; 3847 u8 seq[DOT11_WPA_KEY_RSC_LEN];
3848 u16 lo; 3848 u16 lo;
3849 uint32 hi; 3849 u32 hi;
3850 /* group keys in WPA-NONE (IBSS only, AES and TKIP) use a global TXIV */ 3850 /* group keys in WPA-NONE (IBSS only, AES and TKIP) use a global TXIV */
3851 if ((bsscfg->WPA_auth & WPA_AUTH_NONE) 3851 if ((bsscfg->WPA_auth & WPA_AUTH_NONE)
3852 && ETHER_ISNULLADDR(&key->ea)) { 3852 && ETHER_ISNULLADDR(&key->ea)) {
@@ -4043,7 +4043,7 @@ _wlc_ioctl(wlc_info_t *wlc, int cmd, void *arg, int len, struct wlc_if *wlcif)
4043 break; 4043 break;
4044 4044
4045 case WLC_SET_ATIM: 4045 case WLC_SET_ATIM:
4046 wlc->default_bss->atim_window = (uint32) val; 4046 wlc->default_bss->atim_window = (u32) val;
4047 break; 4047 break;
4048 4048
4049 case WLC_GET_PKTCNTS:{ 4049 case WLC_GET_PKTCNTS:{
@@ -4603,7 +4603,7 @@ wlc_iovar_op(wlc_info_t *wlc, const char *name,
4603 int err = 0; 4603 int err = 0;
4604 int val_size; 4604 int val_size;
4605 const bcm_iovar_t *vi = NULL; 4605 const bcm_iovar_t *vi = NULL;
4606 uint32 actionid; 4606 u32 actionid;
4607 int i; 4607 int i;
4608 4608
4609 ASSERT(name != NULL); 4609 ASSERT(name != NULL);
@@ -4739,7 +4739,7 @@ wlc_iovar_check(wlc_pub_t *pub, const bcm_iovar_t *vi, void *arg, int len,
4739 * Please use params for additional qualifying parameters. 4739 * Please use params for additional qualifying parameters.
4740 */ 4740 */
4741int 4741int
4742wlc_doiovar(void *hdl, const bcm_iovar_t *vi, uint32 actionid, 4742wlc_doiovar(void *hdl, const bcm_iovar_t *vi, u32 actionid,
4743 const char *name, void *params, uint p_len, void *arg, int len, 4743 const char *name, void *params, uint p_len, void *arg, int len,
4744 int val_size, struct wlc_if *wlcif) 4744 int val_size, struct wlc_if *wlcif)
4745{ 4745{
@@ -4848,11 +4848,11 @@ wlc_doiovar(void *hdl, const bcm_iovar_t *vi, uint32 actionid,
4848} 4848}
4849 4849
4850static int 4850static int
4851wlc_iovar_rangecheck(wlc_info_t *wlc, uint32 val, const bcm_iovar_t *vi) 4851wlc_iovar_rangecheck(wlc_info_t *wlc, u32 val, const bcm_iovar_t *vi)
4852{ 4852{
4853 int err = 0; 4853 int err = 0;
4854 uint32 min_val = 0; 4854 u32 min_val = 0;
4855 uint32 max_val = 0; 4855 u32 max_val = 0;
4856 4856
4857 /* Only ranged integers are checked */ 4857 /* Only ranged integers are checked */
4858 switch (vi->type) { 4858 switch (vi->type) {
@@ -5577,10 +5577,10 @@ static void wlc_compute_mimo_plcp(ratespec_t rspec, uint length, u8 *plcp)
5577 5577
5578/* Rate: 802.11 rate code, length: PSDU length in octets */ 5578/* Rate: 802.11 rate code, length: PSDU length in octets */
5579static void BCMFASTPATH 5579static void BCMFASTPATH
5580wlc_compute_ofdm_plcp(ratespec_t rspec, uint32 length, u8 *plcp) 5580wlc_compute_ofdm_plcp(ratespec_t rspec, u32 length, u8 *plcp)
5581{ 5581{
5582 u8 rate_signal; 5582 u8 rate_signal;
5583 uint32 tmp = 0; 5583 u32 tmp = 0;
5584 int rate = RSPEC2RATE(rspec); 5584 int rate = RSPEC2RATE(rspec);
5585 5585
5586 ASSERT(IS_OFDM(rspec)); 5586 ASSERT(IS_OFDM(rspec));
@@ -5902,7 +5902,7 @@ wlc_d11hdrs_mac80211(wlc_info_t *wlc, struct ieee80211_hw *hw,
5902 struct dot11_rts_frame *rts = NULL; 5902 struct dot11_rts_frame *rts = NULL;
5903 bool qos; 5903 bool qos;
5904 uint ac; 5904 uint ac;
5905 uint32 rate_val[2]; 5905 u32 rate_val[2];
5906 bool hwtkmic = FALSE; 5906 bool hwtkmic = FALSE;
5907 u16 mimo_ctlchbw = PHY_TXC1_BW_20MHZ; 5907 u16 mimo_ctlchbw = PHY_TXC1_BW_20MHZ;
5908#ifdef WLANTSEL 5908#ifdef WLANTSEL
@@ -6559,7 +6559,7 @@ void wlc_tbtt(wlc_info_t *wlc, d11regs_t *regs)
6559 if (BSSCFG_STA(cfg)) { 6559 if (BSSCFG_STA(cfg)) {
6560 /* run watchdog here if the watchdog timer is not armed */ 6560 /* run watchdog here if the watchdog timer is not armed */
6561 if (WLC_WATCHDOG_TBTT(wlc)) { 6561 if (WLC_WATCHDOG_TBTT(wlc)) {
6562 uint32 cur, delta; 6562 u32 cur, delta;
6563 if (wlc->WDarmed) { 6563 if (wlc->WDarmed) {
6564 wl_del_timer(wlc->wl, wlc->wdtimer); 6564 wl_del_timer(wlc->wl, wlc->wdtimer);
6565 wlc->WDarmed = FALSE; 6565 wlc->WDarmed = FALSE;
@@ -6567,7 +6567,7 @@ void wlc_tbtt(wlc_info_t *wlc, d11regs_t *regs)
6567 6567
6568 cur = OSL_SYSUPTIME(); 6568 cur = OSL_SYSUPTIME();
6569 delta = cur > wlc->WDlast ? cur - wlc->WDlast : 6569 delta = cur > wlc->WDlast ? cur - wlc->WDlast :
6570 (uint32) ~0 - wlc->WDlast + cur + 1; 6570 (u32) ~0 - wlc->WDlast + cur + 1;
6571 if (delta >= TIMER_INTERVAL_WATCHDOG) { 6571 if (delta >= TIMER_INTERVAL_WATCHDOG) {
6572 wlc_watchdog((void *)wlc); 6572 wlc_watchdog((void *)wlc);
6573 wlc->WDlast = cur; 6573 wlc->WDlast = cur;
@@ -6611,7 +6611,7 @@ static void wlc_hwtimer_gptimer_cb(wlc_info_t *wlc)
6611 * POLICY: no macinstatus change, no bounding loop. 6611 * POLICY: no macinstatus change, no bounding loop.
6612 * All dpc bounding should be handled in BMAC dpc, like txstatus and rxint 6612 * All dpc bounding should be handled in BMAC dpc, like txstatus and rxint
6613 */ 6613 */
6614void wlc_high_dpc(wlc_info_t *wlc, uint32 macintstatus) 6614void wlc_high_dpc(wlc_info_t *wlc, u32 macintstatus)
6615{ 6615{
6616 d11regs_t *regs = wlc->regs; 6616 d11regs_t *regs = wlc->regs;
6617#ifdef BCMDBG 6617#ifdef BCMDBG
@@ -6752,7 +6752,7 @@ static void wlc_war16165(wlc_info_t *wlc, bool tx)
6752/* process an individual tx_status_t */ 6752/* process an individual tx_status_t */
6753/* WLC_HIGH_API */ 6753/* WLC_HIGH_API */
6754bool BCMFASTPATH 6754bool BCMFASTPATH
6755wlc_dotxstatus(wlc_info_t *wlc, tx_status_t *txs, uint32 frm_tx2) 6755wlc_dotxstatus(wlc_info_t *wlc, tx_status_t *txs, u32 frm_tx2)
6756{ 6756{
6757 void *p; 6757 void *p;
6758 uint queue; 6758 uint queue;
@@ -6953,9 +6953,9 @@ wlc_txfifo_complete(wlc_info_t *wlc, uint fifo, s8 txpktpend)
6953/* Given the beacon interval in kus, and a 64 bit TSF in us, 6953/* Given the beacon interval in kus, and a 64 bit TSF in us,
6954 * return the offset (in us) of the TSF from the last TBTT 6954 * return the offset (in us) of the TSF from the last TBTT
6955 */ 6955 */
6956uint32 wlc_calc_tbtt_offset(uint32 bp, uint32 tsf_h, uint32 tsf_l) 6956u32 wlc_calc_tbtt_offset(u32 bp, u32 tsf_h, u32 tsf_l)
6957{ 6957{
6958 uint32 k, btklo, btkhi, offset; 6958 u32 k, btklo, btkhi, offset;
6959 6959
6960 /* TBTT is always an even multiple of the beacon_interval, 6960 /* TBTT is always an even multiple of the beacon_interval,
6961 * so the TBTT less than or equal to the beacon timestamp is 6961 * so the TBTT less than or equal to the beacon timestamp is
@@ -6970,7 +6970,7 @@ uint32 wlc_calc_tbtt_offset(uint32 bp, uint32 tsf_h, uint32 tsf_l)
6970 * BP = beacon interval (Kusec, 16bits) 6970 * BP = beacon interval (Kusec, 16bits)
6971 * BIu = BP * 2^10 = beacon interval (usec, 26bits) 6971 * BIu = BP * 2^10 = beacon interval (usec, 26bits)
6972 * 6972 *
6973 * To keep the calculations in uint32s, the modulo operation 6973 * To keep the calculations in u32s, the modulo operation
6974 * on the high part of BT needs to be done in parts using the 6974 * on the high part of BT needs to be done in parts using the
6975 * relations: 6975 * relations:
6976 * X*Y mod Z = ((X mod Z) * (Y mod Z)) mod Z 6976 * X*Y mod Z = ((X mod Z) * (Y mod Z)) mod Z
@@ -7003,8 +7003,8 @@ uint32 wlc_calc_tbtt_offset(uint32 bp, uint32 tsf_h, uint32 tsf_l)
7003 offset = btklo % bp; 7003 offset = btklo % bp;
7004 7004
7005 /* K[2] = ((2^16 % BP) * 2^16) % BP */ 7005 /* K[2] = ((2^16 % BP) * 2^16) % BP */
7006 k = (uint32) (1 << 16) % bp; 7006 k = (u32) (1 << 16) % bp;
7007 k = (uint32) (k * 1 << 16) % (uint32) bp; 7007 k = (u32) (k * 1 << 16) % (u32) bp;
7008 7008
7009 /* offset += (BTk[2] * K[2]) % BP */ 7009 /* offset += (BTk[2] * K[2]) % BP */
7010 offset += ((btkhi & 0xffff) * k) % bp; 7010 offset += ((btkhi & 0xffff) * k) % bp;
@@ -7046,7 +7046,7 @@ static void
7046prep_mac80211_status(wlc_info_t *wlc, d11rxhdr_t *rxh, void *p, 7046prep_mac80211_status(wlc_info_t *wlc, d11rxhdr_t *rxh, void *p,
7047 struct ieee80211_rx_status *rx_status) 7047 struct ieee80211_rx_status *rx_status)
7048{ 7048{
7049 uint32 tsf_l, tsf_h; 7049 u32 tsf_l, tsf_h;
7050 wlc_d11rxhdr_t *wlc_rxh = (wlc_d11rxhdr_t *) rxh; 7050 wlc_d11rxhdr_t *wlc_rxh = (wlc_d11rxhdr_t *) rxh;
7051 int preamble; 7051 int preamble;
7052 int channel; 7052 int channel;
@@ -7922,7 +7922,7 @@ void wlc_bss_update_beacon(wlc_info_t *wlc, wlc_bsscfg_t *cfg)
7922 if (MBSS_BCN_ENAB(cfg)) { /* Optimize: Some of if/else could be combined */ 7922 if (MBSS_BCN_ENAB(cfg)) { /* Optimize: Some of if/else could be combined */
7923 } else if (HWBCN_ENAB(cfg)) { /* Hardware beaconing for this config */ 7923 } else if (HWBCN_ENAB(cfg)) { /* Hardware beaconing for this config */
7924 u16 bcn[BCN_TMPL_LEN / 2]; 7924 u16 bcn[BCN_TMPL_LEN / 2];
7925 uint32 both_valid = MCMD_BCN0VLD | MCMD_BCN1VLD; 7925 u32 both_valid = MCMD_BCN0VLD | MCMD_BCN1VLD;
7926 d11regs_t *regs = wlc->regs; 7926 d11regs_t *regs = wlc->regs;
7927 osl_t *osh = NULL; 7927 osl_t *osh = NULL;
7928 7928
@@ -8198,7 +8198,7 @@ static void wlc_process_eventq(void *arg)
8198} 8198}
8199 8199
8200void 8200void
8201wlc_uint64_sub(uint32 *a_high, uint32 *a_low, uint32 b_high, uint32 b_low) 8201wlc_uint64_sub(u32 *a_high, u32 *a_low, u32 b_high, u32 b_low)
8202{ 8202{
8203 if (b_low > *a_low) { 8203 if (b_low > *a_low) {
8204 /* low half needs a carry */ 8204 /* low half needs a carry */
@@ -8209,7 +8209,7 @@ wlc_uint64_sub(uint32 *a_high, uint32 *a_low, uint32 b_high, uint32 b_low)
8209} 8209}
8210 8210
8211static ratespec_t 8211static ratespec_t
8212mac80211_wlc_set_nrate(wlc_info_t *wlc, wlcband_t *cur_band, uint32 int_val) 8212mac80211_wlc_set_nrate(wlc_info_t *wlc, wlcband_t *cur_band, u32 int_val)
8213{ 8213{
8214 u8 stf = (int_val & NRATE_STF_MASK) >> NRATE_STF_SHIFT; 8214 u8 stf = (int_val & NRATE_STF_MASK) >> NRATE_STF_SHIFT;
8215 u8 rate = int_val & NRATE_RATE_MASK; 8215 u8 rate = int_val & NRATE_RATE_MASK;
@@ -8351,7 +8351,7 @@ wlc_duty_cycle_set(wlc_info_t *wlc, int duty_cycle, bool isOFDM,
8351 8351
8352void 8352void
8353wlc_pktengtx(wlc_info_t *wlc, wl_pkteng_t *pkteng, u8 rate, 8353wlc_pktengtx(wlc_info_t *wlc, wl_pkteng_t *pkteng, u8 rate,
8354 struct ether_addr *sa, uint32 wait_delay) 8354 struct ether_addr *sa, u32 wait_delay)
8355{ 8355{
8356 bool suspend; 8356 bool suspend;
8357 u16 val = M_PKTENG_MODE_TX; 8357 u16 val = M_PKTENG_MODE_TX;
@@ -8474,12 +8474,12 @@ void wlc_copyfrom_shm(wlc_info_t *wlc, uint offset, void *buf, int len)
8474} 8474}
8475 8475
8476/* wrapper BMAC functions to for HIGH driver access */ 8476/* wrapper BMAC functions to for HIGH driver access */
8477void wlc_mctrl(wlc_info_t *wlc, uint32 mask, uint32 val) 8477void wlc_mctrl(wlc_info_t *wlc, u32 mask, u32 val)
8478{ 8478{
8479 wlc_bmac_mctrl(wlc->hw, mask, val); 8479 wlc_bmac_mctrl(wlc->hw, mask, val);
8480} 8480}
8481 8481
8482void wlc_corereset(wlc_info_t *wlc, uint32 flags) 8482void wlc_corereset(wlc_info_t *wlc, u32 flags)
8483{ 8483{
8484 wlc_bmac_corereset(wlc->hw, flags); 8484 wlc_bmac_corereset(wlc->hw, flags);
8485} 8485}
@@ -8521,7 +8521,7 @@ void wlc_set_rcmta(wlc_info_t *wlc, int idx, const struct ether_addr *addr)
8521 wlc_bmac_set_rcmta(wlc->hw, idx, addr); 8521 wlc_bmac_set_rcmta(wlc->hw, idx, addr);
8522} 8522}
8523 8523
8524void wlc_read_tsf(wlc_info_t *wlc, uint32 *tsf_l_ptr, uint32 *tsf_h_ptr) 8524void wlc_read_tsf(wlc_info_t *wlc, u32 *tsf_l_ptr, u32 *tsf_h_ptr)
8525{ 8525{
8526 wlc_bmac_read_tsf(wlc->hw, tsf_l_ptr, tsf_h_ptr); 8526 wlc_bmac_read_tsf(wlc->hw, tsf_l_ptr, tsf_h_ptr);
8527} 8527}
diff --git a/drivers/staging/brcm80211/sys/wlc_mac80211.h b/drivers/staging/brcm80211/sys/wlc_mac80211.h
index d06546c5194..5b5375d67fd 100644
--- a/drivers/staging/brcm80211/sys/wlc_mac80211.h
+++ b/drivers/staging/brcm80211/sys/wlc_mac80211.h
@@ -420,7 +420,7 @@ typedef struct wlc_hwband {
420 u8 bandhw_stf_ss_mode; /* HW configured STF type, 0:siso; 1:cdd */ 420 u8 bandhw_stf_ss_mode; /* HW configured STF type, 0:siso; 1:cdd */
421 u16 CWmin; 421 u16 CWmin;
422 u16 CWmax; 422 u16 CWmax;
423 uint32 core_flags; 423 u32 core_flags;
424 424
425 u16 phytype; /* phytype */ 425 u16 phytype; /* phytype */
426 u16 phyrev; 426 u16 phyrev;
@@ -451,10 +451,10 @@ struct wlc_hw_info {
451 uint corerev; /* core revision */ 451 uint corerev; /* core revision */
452 u8 sromrev; /* version # of the srom */ 452 u8 sromrev; /* version # of the srom */
453 u16 boardrev; /* version # of particular board */ 453 u16 boardrev; /* version # of particular board */
454 uint32 boardflags; /* Board specific flags from srom */ 454 u32 boardflags; /* Board specific flags from srom */
455 uint32 boardflags2; /* More board flags if sromrev >= 4 */ 455 u32 boardflags2; /* More board flags if sromrev >= 4 */
456 uint32 machwcap; /* MAC capabilities (corerev >= 13) */ 456 u32 machwcap; /* MAC capabilities (corerev >= 13) */
457 uint32 machwcap_backup; /* backup of machwcap (corerev >= 13) */ 457 u32 machwcap_backup; /* backup of machwcap (corerev >= 13) */
458 u16 ucode_dbgsel; /* dbgsel for ucode debug(config gpio) */ 458 u16 ucode_dbgsel; /* dbgsel for ucode debug(config gpio) */
459 459
460 si_t *sih; /* SB handle (cookie for siutils calls) */ 460 si_t *sih; /* SB handle (cookie for siutils calls) */
@@ -483,12 +483,12 @@ struct wlc_hw_info {
483 mbool pllreq; /* pll requests to keep PLL on */ 483 mbool pllreq; /* pll requests to keep PLL on */
484 484
485 u8 suspended_fifos; /* Which TX fifo to remain awake for */ 485 u8 suspended_fifos; /* Which TX fifo to remain awake for */
486 uint32 maccontrol; /* Cached value of maccontrol */ 486 u32 maccontrol; /* Cached value of maccontrol */
487 uint mac_suspend_depth; /* current depth of mac_suspend levels */ 487 uint mac_suspend_depth; /* current depth of mac_suspend levels */
488 uint32 wake_override; /* Various conditions to force MAC to WAKE mode */ 488 u32 wake_override; /* Various conditions to force MAC to WAKE mode */
489 uint32 mute_override; /* Prevent ucode from sending beacons */ 489 u32 mute_override; /* Prevent ucode from sending beacons */
490 struct ether_addr etheraddr; /* currently configured ethernet address */ 490 struct ether_addr etheraddr; /* currently configured ethernet address */
491 uint32 led_gpio_mask; /* LED GPIO Mask */ 491 u32 led_gpio_mask; /* LED GPIO Mask */
492 bool noreset; /* true= do not reset hw, used by WLC_OUT */ 492 bool noreset; /* true= do not reset hw, used by WLC_OUT */
493 bool forcefastclk; /* true if the h/w is forcing the use of fast clk */ 493 bool forcefastclk; /* true if the h/w is forcing the use of fast clk */
494 bool clk; /* core is out of reset and has clock */ 494 bool clk; /* core is out of reset and has clock */
@@ -506,9 +506,9 @@ struct wlc_hw_info {
506 struct wl_timer *wdtimer; /* timer for watchdog routine */ 506 struct wl_timer *wdtimer; /* timer for watchdog routine */
507 struct ether_addr orig_etheraddr; /* original hw ethernet address */ 507 struct ether_addr orig_etheraddr; /* original hw ethernet address */
508 u16 rpc_dngl_agg; /* rpc agg control for dongle */ 508 u16 rpc_dngl_agg; /* rpc agg control for dongle */
509 uint32 mem_required_def; /* memory required to replenish RX DMA ring */ 509 u32 mem_required_def; /* memory required to replenish RX DMA ring */
510 uint32 mem_required_lower; /* memory required with lower RX bound */ 510 u32 mem_required_lower; /* memory required with lower RX bound */
511 uint32 mem_required_least; /* minimum memory requirement to handle RX */ 511 u32 mem_required_least; /* minimum memory requirement to handle RX */
512 512
513#endif /* WLC_LOW_ONLY */ 513#endif /* WLC_LOW_ONLY */
514 514
@@ -516,7 +516,7 @@ struct wlc_hw_info {
516 u8 antsel_type; /* Type of boardlevel mimo antenna switch-logic 516 u8 antsel_type; /* Type of boardlevel mimo antenna switch-logic
517 * 0 = N/A, 1 = 2x4 board, 2 = 2x3 CB2 board 517 * 0 = N/A, 1 = 2x4 board, 2 = 2x3 CB2 board
518 */ 518 */
519 uint32 antsel_avail; /* put antsel_info_t here if more info is needed */ 519 u32 antsel_avail; /* put antsel_info_t here if more info is needed */
520#endif /* WLC_LOW */ 520#endif /* WLC_LOW */
521}; 521};
522 522
@@ -552,9 +552,9 @@ struct wlc_info {
552 u16 fastpwrup_dly; /* time in us needed to bring up d11 fast clock */ 552 u16 fastpwrup_dly; /* time in us needed to bring up d11 fast clock */
553 553
554 /* interrupt */ 554 /* interrupt */
555 uint32 macintstatus; /* bit channel between isr and dpc */ 555 u32 macintstatus; /* bit channel between isr and dpc */
556 uint32 macintmask; /* sw runtime master macintmask value */ 556 u32 macintmask; /* sw runtime master macintmask value */
557 uint32 defmacintmask; /* default "on" macintmask value */ 557 u32 defmacintmask; /* default "on" macintmask value */
558 558
559 /* up and down */ 559 /* up and down */
560 bool device_present; /* (removable) device is present */ 560 bool device_present; /* (removable) device is present */
@@ -583,8 +583,8 @@ struct wlc_info {
583#ifdef WLC_HIGH_ONLY 583#ifdef WLC_HIGH_ONLY
584 rpctx_info_t *rpctx; /* RPC TX module */ 584 rpctx_info_t *rpctx; /* RPC TX module */
585 bool reset_bmac_pending; /* bmac reset is in progressing */ 585 bool reset_bmac_pending; /* bmac reset is in progressing */
586 uint32 rpc_agg; /* host agg: bit 16-31, bmac agg: bit 0-15 */ 586 u32 rpc_agg; /* host agg: bit 16-31, bmac agg: bit 0-15 */
587 uint32 rpc_msglevel; /* host rpc: bit 16-31, bmac rpc: bit 0-15 */ 587 u32 rpc_msglevel; /* host rpc: bit 16-31, bmac rpc: bit 0-15 */
588#endif 588#endif
589 589
590 ampdu_info_t *ampdu; /* ampdu module handler */ 590 ampdu_info_t *ampdu; /* ampdu module handler */
@@ -599,7 +599,7 @@ struct wlc_info {
599 u16 deviceid; /* PCI device id */ 599 u16 deviceid; /* PCI device id */
600 uint ucode_rev; /* microcode revision */ 600 uint ucode_rev; /* microcode revision */
601 601
602 uint32 machwcap; /* MAC capabilities, BMAC shadow */ 602 u32 machwcap; /* MAC capabilities, BMAC shadow */
603 603
604 struct ether_addr perm_etheraddr; /* original sprom local ethernet address */ 604 struct ether_addr perm_etheraddr; /* original sprom local ethernet address */
605 605
@@ -661,7 +661,7 @@ struct wlc_info {
661 u8 bcn_li_dtim; /* beacon listen interval in # dtims */ 661 u8 bcn_li_dtim; /* beacon listen interval in # dtims */
662 662
663 bool WDarmed; /* watchdog timer is armed */ 663 bool WDarmed; /* watchdog timer is armed */
664 uint32 WDlast; /* last time wlc_watchdog() was called */ 664 u32 WDlast; /* last time wlc_watchdog() was called */
665 665
666 /* WME */ 666 /* WME */
667 ac_bitmap_t wme_dp; /* Discard (oldest first) policy per AC */ 667 ac_bitmap_t wme_dp; /* Discard (oldest first) policy per AC */
@@ -776,13 +776,13 @@ struct wlc_info {
776 776
777 pkt_cb_t *pkt_callback; /* tx completion callback handlers */ 777 pkt_cb_t *pkt_callback; /* tx completion callback handlers */
778 778
779 uint32 txretried; /* tx retried number in one msdu */ 779 u32 txretried; /* tx retried number in one msdu */
780 780
781 ratespec_t bcn_rspec; /* save bcn ratespec purpose */ 781 ratespec_t bcn_rspec; /* save bcn ratespec purpose */
782 782
783 bool apsd_sta_usp; /* Unscheduled Service Period in progress on STA */ 783 bool apsd_sta_usp; /* Unscheduled Service Period in progress on STA */
784 struct wl_timer *apsd_trigger_timer; /* timer for wme apsd trigger frames */ 784 struct wl_timer *apsd_trigger_timer; /* timer for wme apsd trigger frames */
785 uint32 apsd_trigger_timeout; /* timeout value for apsd_trigger_timer (in ms) 785 u32 apsd_trigger_timeout; /* timeout value for apsd_trigger_timer (in ms)
786 * 0 == disable 786 * 0 == disable
787 */ 787 */
788 ac_bitmap_t apsd_trigger_ac; /* Permissible Acess Category in which APSD Null 788 ac_bitmap_t apsd_trigger_ac; /* Permissible Acess Category in which APSD Null
@@ -809,10 +809,10 @@ struct wlc_info {
809 809
810 wlc_if_t *wlcif_list; /* linked list of wlc_if structs */ 810 wlc_if_t *wlcif_list; /* linked list of wlc_if structs */
811 wlc_txq_info_t *active_queue; /* txq for the currently active transmit context */ 811 wlc_txq_info_t *active_queue; /* txq for the currently active transmit context */
812 uint32 mpc_dur; /* total time (ms) in mpc mode except for the 812 u32 mpc_dur; /* total time (ms) in mpc mode except for the
813 * portion since radio is turned off last time 813 * portion since radio is turned off last time
814 */ 814 */
815 uint32 mpc_laston_ts; /* timestamp (ms) when radio is turned off last 815 u32 mpc_laston_ts; /* timestamp (ms) when radio is turned off last
816 * time 816 * time
817 */ 817 */
818 bool pr80838_war; 818 bool pr80838_war;
@@ -870,11 +870,11 @@ struct antsel_info {
870 ((len1 == len2) && !bcmp(ssid1, ssid2, len1)) 870 ((len1 == len2) && !bcmp(ssid1, ssid2, len1))
871 871
872/* API shared by both WLC_HIGH and WLC_LOW driver */ 872/* API shared by both WLC_HIGH and WLC_LOW driver */
873extern void wlc_high_dpc(wlc_info_t *wlc, uint32 macintstatus); 873extern void wlc_high_dpc(wlc_info_t *wlc, u32 macintstatus);
874extern void wlc_fatal_error(wlc_info_t *wlc); 874extern void wlc_fatal_error(wlc_info_t *wlc);
875extern void wlc_bmac_rpc_watchdog(wlc_info_t *wlc); 875extern void wlc_bmac_rpc_watchdog(wlc_info_t *wlc);
876extern void wlc_recv(wlc_info_t *wlc, void *p); 876extern void wlc_recv(wlc_info_t *wlc, void *p);
877extern bool wlc_dotxstatus(wlc_info_t *wlc, tx_status_t *txs, uint32 frm_tx2); 877extern bool wlc_dotxstatus(wlc_info_t *wlc, tx_status_t *txs, u32 frm_tx2);
878extern void wlc_txfifo(wlc_info_t *wlc, uint fifo, void *p, bool commit, 878extern void wlc_txfifo(wlc_info_t *wlc, uint fifo, void *p, bool commit,
879 s8 txpktpend); 879 s8 txpktpend);
880extern void wlc_txfifo_complete(wlc_info_t *wlc, uint fifo, s8 txpktpend); 880extern void wlc_txfifo_complete(wlc_info_t *wlc, uint fifo, s8 txpktpend);
@@ -892,8 +892,8 @@ extern void wlc_set_rcmta(wlc_info_t *wlc, int idx,
892 const struct ether_addr *addr); 892 const struct ether_addr *addr);
893extern void wlc_set_addrmatch(wlc_info_t *wlc, int match_reg_offset, 893extern void wlc_set_addrmatch(wlc_info_t *wlc, int match_reg_offset,
894 const struct ether_addr *addr); 894 const struct ether_addr *addr);
895extern void wlc_read_tsf(wlc_info_t *wlc, uint32 *tsf_l_ptr, 895extern void wlc_read_tsf(wlc_info_t *wlc, u32 *tsf_l_ptr,
896 uint32 *tsf_h_ptr); 896 u32 *tsf_h_ptr);
897extern void wlc_set_cwmin(wlc_info_t *wlc, u16 newmin); 897extern void wlc_set_cwmin(wlc_info_t *wlc, u16 newmin);
898extern void wlc_set_cwmax(wlc_info_t *wlc, u16 newmax); 898extern void wlc_set_cwmax(wlc_info_t *wlc, u16 newmax);
899extern void wlc_fifoerrors(wlc_info_t *wlc); 899extern void wlc_fifoerrors(wlc_info_t *wlc);
@@ -903,7 +903,7 @@ extern void wlc_protection_upd(wlc_info_t *wlc, uint idx, int val);
903extern void wlc_hwtimer_gptimer_set(wlc_info_t *wlc, uint us); 903extern void wlc_hwtimer_gptimer_set(wlc_info_t *wlc, uint us);
904extern void wlc_hwtimer_gptimer_abort(wlc_info_t *wlc); 904extern void wlc_hwtimer_gptimer_abort(wlc_info_t *wlc);
905extern void wlc_pktengtx(wlc_info_t *wlc, wl_pkteng_t *pkteng, u8 rate, 905extern void wlc_pktengtx(wlc_info_t *wlc, wl_pkteng_t *pkteng, u8 rate,
906 struct ether_addr *sa, uint32 wait_delay); 906 struct ether_addr *sa, u32 wait_delay);
907 907
908#if defined(BCMDBG) 908#if defined(BCMDBG)
909extern void wlc_print_rxh(d11rxhdr_t *rxh); 909extern void wlc_print_rxh(d11rxhdr_t *rxh);
@@ -959,9 +959,9 @@ extern void wlc_dump_ie(wlc_info_t *wlc, bcm_tlv_t *ie, struct bcmstrbuf *b);
959extern bool wlc_ps_check(wlc_info_t *wlc); 959extern bool wlc_ps_check(wlc_info_t *wlc);
960extern void wlc_reprate_init(wlc_info_t *wlc); 960extern void wlc_reprate_init(wlc_info_t *wlc);
961extern void wlc_bsscfg_reprate_init(wlc_bsscfg_t *bsscfg); 961extern void wlc_bsscfg_reprate_init(wlc_bsscfg_t *bsscfg);
962extern void wlc_uint64_sub(uint32 *a_high, uint32 *a_low, uint32 b_high, 962extern void wlc_uint64_sub(u32 *a_high, u32 *a_low, u32 b_high,
963 uint32 b_low); 963 u32 b_low);
964extern uint32 wlc_calc_tbtt_offset(uint32 bi, uint32 tsf_h, uint32 tsf_l); 964extern u32 wlc_calc_tbtt_offset(u32 bi, u32 tsf_h, u32 tsf_l);
965 965
966/* Shared memory access */ 966/* Shared memory access */
967extern void wlc_write_shm(wlc_info_t *wlc, uint offset, u16 v); 967extern void wlc_write_shm(wlc_info_t *wlc, uint offset, u16 v);
@@ -996,7 +996,7 @@ extern bool wlc_timers_init(wlc_info_t *wlc, int unit);
996 996
997extern const bcm_iovar_t wlc_iovars[]; 997extern const bcm_iovar_t wlc_iovars[];
998 998
999extern int wlc_doiovar(void *hdl, const bcm_iovar_t *vi, uint32 actionid, 999extern int wlc_doiovar(void *hdl, const bcm_iovar_t *vi, u32 actionid,
1000 const char *name, void *params, uint p_len, void *arg, 1000 const char *name, void *params, uint p_len, void *arg,
1001 int len, int val_size, wlc_if_t *wlcif); 1001 int len, int val_size, wlc_if_t *wlcif);
1002 1002
diff --git a/drivers/staging/brcm80211/sys/wlc_phy_shim.c b/drivers/staging/brcm80211/sys/wlc_phy_shim.c
index d7bc4c82c83..b6f0f1e2d0f 100644
--- a/drivers/staging/brcm80211/sys/wlc_phy_shim.c
+++ b/drivers/staging/brcm80211/sys/wlc_phy_shim.c
@@ -117,12 +117,12 @@ void wlapi_intrson(wlc_phy_shim_info_t *physhim)
117 wl_intrson(physhim->wl); 117 wl_intrson(physhim->wl);
118} 118}
119 119
120uint32 wlapi_intrsoff(wlc_phy_shim_info_t *physhim) 120u32 wlapi_intrsoff(wlc_phy_shim_info_t *physhim)
121{ 121{
122 return wl_intrsoff(physhim->wl); 122 return wl_intrsoff(physhim->wl);
123} 123}
124 124
125void wlapi_intrsrestore(wlc_phy_shim_info_t *physhim, uint32 macintmask) 125void wlapi_intrsrestore(wlc_phy_shim_info_t *physhim, u32 macintmask)
126{ 126{
127 wl_intrsrestore(physhim->wl, macintmask); 127 wl_intrsrestore(physhim->wl, macintmask);
128} 128}
@@ -144,7 +144,7 @@ wlapi_bmac_mhf(wlc_phy_shim_info_t *physhim, u8 idx, u16 mask,
144 wlc_bmac_mhf(physhim->wlc_hw, idx, mask, val, bands); 144 wlc_bmac_mhf(physhim->wlc_hw, idx, mask, val, bands);
145} 145}
146 146
147void wlapi_bmac_corereset(wlc_phy_shim_info_t *physhim, uint32 flags) 147void wlapi_bmac_corereset(wlc_phy_shim_info_t *physhim, u32 flags)
148{ 148{
149 wlc_bmac_corereset(physhim->wlc_hw, flags); 149 wlc_bmac_corereset(physhim->wlc_hw, flags);
150} 150}
@@ -164,7 +164,7 @@ void wlapi_enable_mac(wlc_phy_shim_info_t *physhim)
164 wlc_enable_mac(physhim->wlc); 164 wlc_enable_mac(physhim->wlc);
165} 165}
166 166
167void wlapi_bmac_mctrl(wlc_phy_shim_info_t *physhim, uint32 mask, uint32 val) 167void wlapi_bmac_mctrl(wlc_phy_shim_info_t *physhim, u32 mask, u32 val)
168{ 168{
169 wlc_bmac_mctrl(physhim->wlc_hw, mask, val); 169 wlc_bmac_mctrl(physhim->wlc_hw, mask, val);
170} 170}
@@ -233,21 +233,21 @@ void wlapi_ucode_sample_init(wlc_phy_shim_info_t *physhim)
233 233
234void 234void
235wlapi_copyfrom_objmem(wlc_phy_shim_info_t *physhim, uint offset, void *buf, 235wlapi_copyfrom_objmem(wlc_phy_shim_info_t *physhim, uint offset, void *buf,
236 int len, uint32 sel) 236 int len, u32 sel)
237{ 237{
238 wlc_bmac_copyfrom_objmem(physhim->wlc_hw, offset, buf, len, sel); 238 wlc_bmac_copyfrom_objmem(physhim->wlc_hw, offset, buf, len, sel);
239} 239}
240 240
241void 241void
242wlapi_copyto_objmem(wlc_phy_shim_info_t *physhim, uint offset, const void *buf, 242wlapi_copyto_objmem(wlc_phy_shim_info_t *physhim, uint offset, const void *buf,
243 int l, uint32 sel) 243 int l, u32 sel)
244{ 244{
245 wlc_bmac_copyto_objmem(physhim->wlc_hw, offset, buf, l, sel); 245 wlc_bmac_copyto_objmem(physhim->wlc_hw, offset, buf, l, sel);
246} 246}
247 247
248void 248void
249wlapi_bmac_pktengtx(wlc_phy_shim_info_t *physhim, wl_pkteng_t *pkteng, 249wlapi_bmac_pktengtx(wlc_phy_shim_info_t *physhim, wl_pkteng_t *pkteng,
250 u8 rate, struct ether_addr *sa, uint32 wait_delay) 250 u8 rate, struct ether_addr *sa, u32 wait_delay)
251{ 251{
252 wlc_pktengtx(physhim->wlc, pkteng, rate, sa, wait_delay); 252 wlc_pktengtx(physhim->wlc, pkteng, rate, sa, wait_delay);
253} 253}
diff --git a/drivers/staging/brcm80211/sys/wlc_phy_shim.h b/drivers/staging/brcm80211/sys/wlc_phy_shim.h
index e573fbff6a7..c5d91198460 100644
--- a/drivers/staging/brcm80211/sys/wlc_phy_shim.h
+++ b/drivers/staging/brcm80211/sys/wlc_phy_shim.h
@@ -71,21 +71,21 @@ extern void wlapi_add_timer(wlc_phy_shim_info_t *physhim,
71extern bool wlapi_del_timer(wlc_phy_shim_info_t *physhim, 71extern bool wlapi_del_timer(wlc_phy_shim_info_t *physhim,
72 struct wlapi_timer *t); 72 struct wlapi_timer *t);
73extern void wlapi_intrson(wlc_phy_shim_info_t *physhim); 73extern void wlapi_intrson(wlc_phy_shim_info_t *physhim);
74extern uint32 wlapi_intrsoff(wlc_phy_shim_info_t *physhim); 74extern u32 wlapi_intrsoff(wlc_phy_shim_info_t *physhim);
75extern void wlapi_intrsrestore(wlc_phy_shim_info_t *physhim, 75extern void wlapi_intrsrestore(wlc_phy_shim_info_t *physhim,
76 uint32 macintmask); 76 u32 macintmask);
77 77
78extern void wlapi_bmac_write_shm(wlc_phy_shim_info_t *physhim, uint offset, 78extern void wlapi_bmac_write_shm(wlc_phy_shim_info_t *physhim, uint offset,
79 u16 v); 79 u16 v);
80extern u16 wlapi_bmac_read_shm(wlc_phy_shim_info_t *physhim, uint offset); 80extern u16 wlapi_bmac_read_shm(wlc_phy_shim_info_t *physhim, uint offset);
81extern void wlapi_bmac_mhf(wlc_phy_shim_info_t *physhim, u8 idx, 81extern void wlapi_bmac_mhf(wlc_phy_shim_info_t *physhim, u8 idx,
82 u16 mask, u16 val, int bands); 82 u16 mask, u16 val, int bands);
83extern void wlapi_bmac_corereset(wlc_phy_shim_info_t *physhim, uint32 flags); 83extern void wlapi_bmac_corereset(wlc_phy_shim_info_t *physhim, u32 flags);
84extern void wlapi_suspend_mac_and_wait(wlc_phy_shim_info_t *physhim); 84extern void wlapi_suspend_mac_and_wait(wlc_phy_shim_info_t *physhim);
85extern void wlapi_switch_macfreq(wlc_phy_shim_info_t *physhim, u8 spurmode); 85extern void wlapi_switch_macfreq(wlc_phy_shim_info_t *physhim, u8 spurmode);
86extern void wlapi_enable_mac(wlc_phy_shim_info_t *physhim); 86extern void wlapi_enable_mac(wlc_phy_shim_info_t *physhim);
87extern void wlapi_bmac_mctrl(wlc_phy_shim_info_t *physhim, uint32 mask, 87extern void wlapi_bmac_mctrl(wlc_phy_shim_info_t *physhim, u32 mask,
88 uint32 val); 88 u32 val);
89extern void wlapi_bmac_phy_reset(wlc_phy_shim_info_t *physhim); 89extern void wlapi_bmac_phy_reset(wlc_phy_shim_info_t *physhim);
90extern void wlapi_bmac_bw_set(wlc_phy_shim_info_t *physhim, u16 bw); 90extern void wlapi_bmac_bw_set(wlc_phy_shim_info_t *physhim, u16 bw);
91extern void wlapi_bmac_phyclk_fgc(wlc_phy_shim_info_t *physhim, bool clk); 91extern void wlapi_bmac_phyclk_fgc(wlc_phy_shim_info_t *physhim, bool clk);
@@ -102,14 +102,14 @@ extern u16 wlapi_bmac_rate_shm_offset(wlc_phy_shim_info_t *physhim,
102 u8 rate); 102 u8 rate);
103extern void wlapi_ucode_sample_init(wlc_phy_shim_info_t *physhim); 103extern void wlapi_ucode_sample_init(wlc_phy_shim_info_t *physhim);
104extern void wlapi_copyfrom_objmem(wlc_phy_shim_info_t *physhim, uint, 104extern void wlapi_copyfrom_objmem(wlc_phy_shim_info_t *physhim, uint,
105 void *buf, int, uint32 sel); 105 void *buf, int, u32 sel);
106extern void wlapi_copyto_objmem(wlc_phy_shim_info_t *physhim, uint, 106extern void wlapi_copyto_objmem(wlc_phy_shim_info_t *physhim, uint,
107 const void *buf, int, uint32); 107 const void *buf, int, u32);
108 108
109extern void wlapi_high_update_phy_mode(wlc_phy_shim_info_t *physhim, 109extern void wlapi_high_update_phy_mode(wlc_phy_shim_info_t *physhim,
110 uint32 phy_mode); 110 u32 phy_mode);
111extern void wlapi_bmac_pktengtx(wlc_phy_shim_info_t *physhim, 111extern void wlapi_bmac_pktengtx(wlc_phy_shim_info_t *physhim,
112 wl_pkteng_t *pkteng, u8 rate, 112 wl_pkteng_t *pkteng, u8 rate,
113 struct ether_addr *sa, uint32 wait_delay); 113 struct ether_addr *sa, u32 wait_delay);
114extern u16 wlapi_bmac_get_txant(wlc_phy_shim_info_t *physhim); 114extern u16 wlapi_bmac_get_txant(wlc_phy_shim_info_t *physhim);
115#endif /* _wlc_phy_shim_h_ */ 115#endif /* _wlc_phy_shim_h_ */
diff --git a/drivers/staging/brcm80211/sys/wlc_pub.h b/drivers/staging/brcm80211/sys/wlc_pub.h
index 94338c45cfd..a5735553faa 100644
--- a/drivers/staging/brcm80211/sys/wlc_pub.h
+++ b/drivers/staging/brcm80211/sys/wlc_pub.h
@@ -240,7 +240,7 @@ typedef int (*dump_fn_t) (void *handle, struct bcmstrbuf *b);
240 * All pointers may point into the same buffer. 240 * All pointers may point into the same buffer.
241 */ 241 */
242typedef int (*iovar_fn_t) (void *handle, const bcm_iovar_t *vi, 242typedef int (*iovar_fn_t) (void *handle, const bcm_iovar_t *vi,
243 uint32 actionid, const char *name, void *params, 243 u32 actionid, const char *name, void *params,
244 uint plen, void *arg, int alen, int vsize, 244 uint plen, void *arg, int alen, int vsize,
245 struct wlc_if *wlcif); 245 struct wlc_if *wlcif);
246 246
@@ -296,13 +296,13 @@ typedef struct wlc_pub {
296 struct ether_addr *multicast; /* ptr to list of multicast addresses */ 296 struct ether_addr *multicast; /* ptr to list of multicast addresses */
297 uint nmulticast; /* # enabled multicast addresses */ 297 uint nmulticast; /* # enabled multicast addresses */
298 298
299 uint32 wlfeatureflag; /* Flags to control sw features from registry */ 299 u32 wlfeatureflag; /* Flags to control sw features from registry */
300 int psq_pkts_total; /* total num of ps pkts */ 300 int psq_pkts_total; /* total num of ps pkts */
301 301
302 u16 txmaxpkts; /* max number of large pkts allowed to be pending */ 302 u16 txmaxpkts; /* max number of large pkts allowed to be pending */
303 303
304 /* s/w decryption counters */ 304 /* s/w decryption counters */
305 uint32 swdecrypt; /* s/w decrypt attempts */ 305 u32 swdecrypt; /* s/w decrypt attempts */
306 306
307 int bcmerror; /* last bcm error */ 307 int bcmerror; /* last bcm error */
308 308
@@ -325,8 +325,8 @@ typedef struct wlc_pub {
325 u16 boardrev; /* version # of particular board */ 325 u16 boardrev; /* version # of particular board */
326 u8 sromrev; /* version # of the srom */ 326 u8 sromrev; /* version # of the srom */
327 char srom_ccode[WLC_CNTRY_BUF_SZ]; /* Country Code in SROM */ 327 char srom_ccode[WLC_CNTRY_BUF_SZ]; /* Country Code in SROM */
328 uint32 boardflags; /* Board specific flags from srom */ 328 u32 boardflags; /* Board specific flags from srom */
329 uint32 boardflags2; /* More board flags if sromrev >= 4 */ 329 u32 boardflags2; /* More board flags if sromrev >= 4 */
330 bool tempsense_disable; /* disable periodic tempsense check */ 330 bool tempsense_disable; /* disable periodic tempsense check */
331 331
332 bool _lmac; /* lmac module included and enabled */ 332 bool _lmac; /* lmac module included and enabled */
@@ -343,7 +343,7 @@ typedef struct wl_rxsts {
343 uint datarate; /* rate in 500kbps */ 343 uint datarate; /* rate in 500kbps */
344 uint antenna; /* antenna pkts received on */ 344 uint antenna; /* antenna pkts received on */
345 uint pktlength; /* pkt length minus bcm phy hdr */ 345 uint pktlength; /* pkt length minus bcm phy hdr */
346 uint32 mactime; /* time stamp from mac, count per 1us */ 346 u32 mactime; /* time stamp from mac, count per 1us */
347 uint sq; /* signal quality */ 347 uint sq; /* signal quality */
348 int32 signal; /* in dbm */ 348 int32 signal; /* in dbm */
349 int32 noise; /* in dbm */ 349 int32 noise; /* in dbm */
@@ -512,8 +512,8 @@ extern void wlc_init(struct wlc_info *wlc);
512extern void wlc_reset(struct wlc_info *wlc); 512extern void wlc_reset(struct wlc_info *wlc);
513 513
514extern void wlc_intrson(struct wlc_info *wlc); 514extern void wlc_intrson(struct wlc_info *wlc);
515extern uint32 wlc_intrsoff(struct wlc_info *wlc); 515extern u32 wlc_intrsoff(struct wlc_info *wlc);
516extern void wlc_intrsrestore(struct wlc_info *wlc, uint32 macintmask); 516extern void wlc_intrsrestore(struct wlc_info *wlc, u32 macintmask);
517extern bool wlc_intrsupd(struct wlc_info *wlc); 517extern bool wlc_intrsupd(struct wlc_info *wlc);
518extern bool wlc_isr(struct wlc_info *wlc, bool *wantdpc); 518extern bool wlc_isr(struct wlc_info *wlc, bool *wantdpc);
519extern bool wlc_dpc(struct wlc_info *wlc, bool bounded); 519extern bool wlc_dpc(struct wlc_info *wlc, bool bounded);
@@ -536,19 +536,19 @@ extern int wlc_bmac_up_finish(struct wlc_hw_info *wlc_hw);
536extern int wlc_bmac_down_prep(struct wlc_hw_info *wlc_hw); 536extern int wlc_bmac_down_prep(struct wlc_hw_info *wlc_hw);
537extern int wlc_bmac_down_finish(struct wlc_hw_info *wlc_hw); 537extern int wlc_bmac_down_finish(struct wlc_hw_info *wlc_hw);
538 538
539extern uint32 wlc_reg_read(struct wlc_info *wlc, void *r, uint size); 539extern u32 wlc_reg_read(struct wlc_info *wlc, void *r, uint size);
540extern void wlc_reg_write(struct wlc_info *wlc, void *r, uint32 v, uint size); 540extern void wlc_reg_write(struct wlc_info *wlc, void *r, u32 v, uint size);
541extern void wlc_corereset(struct wlc_info *wlc, uint32 flags); 541extern void wlc_corereset(struct wlc_info *wlc, u32 flags);
542extern void wlc_mhf(struct wlc_info *wlc, u8 idx, u16 mask, u16 val, 542extern void wlc_mhf(struct wlc_info *wlc, u8 idx, u16 mask, u16 val,
543 int bands); 543 int bands);
544extern u16 wlc_mhf_get(struct wlc_info *wlc, u8 idx, int bands); 544extern u16 wlc_mhf_get(struct wlc_info *wlc, u8 idx, int bands);
545extern uint32 wlc_delta_txfunfl(struct wlc_info *wlc, int fifo); 545extern u32 wlc_delta_txfunfl(struct wlc_info *wlc, int fifo);
546extern void wlc_rate_lookup_init(struct wlc_info *wlc, wlc_rateset_t *rateset); 546extern void wlc_rate_lookup_init(struct wlc_info *wlc, wlc_rateset_t *rateset);
547extern void wlc_default_rateset(struct wlc_info *wlc, wlc_rateset_t *rs); 547extern void wlc_default_rateset(struct wlc_info *wlc, wlc_rateset_t *rs);
548 548
549/* wlc_phy.c helper functions */ 549/* wlc_phy.c helper functions */
550extern void wlc_set_ps_ctrl(struct wlc_info *wlc); 550extern void wlc_set_ps_ctrl(struct wlc_info *wlc);
551extern void wlc_mctrl(struct wlc_info *wlc, uint32 mask, uint32 val); 551extern void wlc_mctrl(struct wlc_info *wlc, u32 mask, u32 val);
552extern void wlc_scb_ratesel_init_all(struct wlc_info *wlc); 552extern void wlc_scb_ratesel_init_all(struct wlc_info *wlc);
553 553
554/* ioctl */ 554/* ioctl */
@@ -566,8 +566,8 @@ extern void wlc_event_if(struct wlc_info *wlc, struct wlc_bsscfg *cfg,
566extern void wlc_suspend_mac_and_wait(struct wlc_info *wlc); 566extern void wlc_suspend_mac_and_wait(struct wlc_info *wlc);
567extern void wlc_enable_mac(struct wlc_info *wlc); 567extern void wlc_enable_mac(struct wlc_info *wlc);
568extern u16 wlc_rate_shm_offset(struct wlc_info *wlc, u8 rate); 568extern u16 wlc_rate_shm_offset(struct wlc_info *wlc, u8 rate);
569extern uint32 wlc_get_rspec_history(struct wlc_bsscfg *cfg); 569extern u32 wlc_get_rspec_history(struct wlc_bsscfg *cfg);
570extern uint32 wlc_get_current_highest_rate(struct wlc_bsscfg *cfg); 570extern u32 wlc_get_current_highest_rate(struct wlc_bsscfg *cfg);
571 571
572static inline int wlc_iovar_getuint(struct wlc_info *wlc, const char *name, 572static inline int wlc_iovar_getuint(struct wlc_info *wlc, const char *name,
573 uint *arg) 573 uint *arg)
@@ -621,7 +621,7 @@ extern void wlc_pmkid_event(struct wlc_bsscfg *cfg);
621void wlc_device_removed(void *arg); 621void wlc_device_removed(void *arg);
622#endif 622#endif
623 623
624/* BMAC RPC: 7 uint32 params: pkttotlen, fifo, commit, fid, txpktpend, pktflag, rpc_id */ 624/* BMAC RPC: 7 u32 params: pkttotlen, fifo, commit, fid, txpktpend, pktflag, rpc_id */
625#define WLC_RPCTX_PARAMS 32 625#define WLC_RPCTX_PARAMS 32
626 626
627#endif /* _wlc_pub_h_ */ 627#endif /* _wlc_pub_h_ */
diff --git a/drivers/staging/brcm80211/sys/wlc_rate.c b/drivers/staging/brcm80211/sys/wlc_rate.c
index 346f6502de1..64134d0d9a4 100644
--- a/drivers/staging/brcm80211/sys/wlc_rate.c
+++ b/drivers/staging/brcm80211/sys/wlc_rate.c
@@ -153,7 +153,7 @@ const mcs_info_t mcs_table[MCS_TABLE_SIZE] = {
153 * other fields: refer to table 78 of section 17.3.2.2 of the original .11a standard 153 * other fields: refer to table 78 of section 17.3.2.2 of the original .11a standard
154 */ 154 */
155typedef struct legacy_phycfg { 155typedef struct legacy_phycfg {
156 uint32 rate_ofdm; /* ofdm mac rate */ 156 u32 rate_ofdm; /* ofdm mac rate */
157 u8 tx_phy_ctl3; /* phy ctl byte 3, code rate, modulation type, # of streams */ 157 u8 tx_phy_ctl3; /* phy ctl byte 3, code rate, modulation type, # of streams */
158} legacy_phycfg_t; 158} legacy_phycfg_t;
159 159
diff --git a/drivers/staging/brcm80211/sys/wlc_rate.h b/drivers/staging/brcm80211/sys/wlc_rate.h
index 41359534616..25ba2a42363 100644
--- a/drivers/staging/brcm80211/sys/wlc_rate.h
+++ b/drivers/staging/brcm80211/sys/wlc_rate.h
@@ -28,10 +28,10 @@ extern const struct wlc_rateset wlc_lrs_rates;
28extern const struct wlc_rateset rate_limit_1_2; 28extern const struct wlc_rateset rate_limit_1_2;
29 29
30typedef struct mcs_info { 30typedef struct mcs_info {
31 uint32 phy_rate_20; /* phy rate in kbps [20Mhz] */ 31 u32 phy_rate_20; /* phy rate in kbps [20Mhz] */
32 uint32 phy_rate_40; /* phy rate in kbps [40Mhz] */ 32 u32 phy_rate_40; /* phy rate in kbps [40Mhz] */
33 uint32 phy_rate_20_sgi; /* phy rate in kbps [20Mhz] with SGI */ 33 u32 phy_rate_20_sgi; /* phy rate in kbps [20Mhz] with SGI */
34 uint32 phy_rate_40_sgi; /* phy rate in kbps [40Mhz] with SGI */ 34 u32 phy_rate_40_sgi; /* phy rate in kbps [40Mhz] with SGI */
35 u8 tx_phy_ctl3; /* phy ctl byte 3, code rate, modulation type, # of streams */ 35 u8 tx_phy_ctl3; /* phy ctl byte 3, code rate, modulation type, # of streams */
36 u8 leg_ofdm; /* matching legacy ofdm rate in 500bkps */ 36 u8 leg_ofdm; /* matching legacy ofdm rate in 500bkps */
37} mcs_info_t; 37} mcs_info_t;
@@ -65,7 +65,7 @@ extern const mcs_info_t mcs_table[];
65/* rate spec : holds rate and mode specific information required to generate a tx frame. */ 65/* rate spec : holds rate and mode specific information required to generate a tx frame. */
66/* Legacy CCK and OFDM information is held in the same manner as was done in the past */ 66/* Legacy CCK and OFDM information is held in the same manner as was done in the past */
67/* (in the lower byte) the upper 3 bytes primarily hold MIMO specific information */ 67/* (in the lower byte) the upper 3 bytes primarily hold MIMO specific information */
68typedef uint32 ratespec_t; 68typedef u32 ratespec_t;
69 69
70/* rate spec bit fields */ 70/* rate spec bit fields */
71#define RSPEC_RATE_MASK 0x0000007F /* Either 500Kbps units or MIMO MCS idx */ 71#define RSPEC_RATE_MASK 0x0000007F /* Either 500Kbps units or MIMO MCS idx */
diff --git a/drivers/staging/brcm80211/sys/wlc_rpc.h b/drivers/staging/brcm80211/sys/wlc_rpc.h
index 21ed3355d31..5c09b38721c 100644
--- a/drivers/staging/brcm80211/sys/wlc_rpc.h
+++ b/drivers/staging/brcm80211/sys/wlc_rpc.h
@@ -425,15 +425,15 @@ static inline rpc_buf_t *wlc_rpc_buf_alloc(rpc_info_t *rpc, bcm_xdr_buf_t *b,
425{ 425{
426 rpc_buf_t *rpc_buf; 426 rpc_buf_t *rpc_buf;
427 427
428 rpc_buf = bcm_rpc_buf_alloc(rpc, len + sizeof(uint32)); 428 rpc_buf = bcm_rpc_buf_alloc(rpc, len + sizeof(u32));
429 429
430 if (!rpc_buf) 430 if (!rpc_buf)
431 return NULL; 431 return NULL;
432 432
433 bcm_xdr_buf_init(b, bcm_rpc_buf_data(bcm_rpc_tp_get(rpc), rpc_buf), 433 bcm_xdr_buf_init(b, bcm_rpc_buf_data(bcm_rpc_tp_get(rpc), rpc_buf),
434 len + sizeof(uint32)); 434 len + sizeof(u32));
435 435
436 bcm_xdr_pack_uint32(b, rpc_id); 436 bcm_xdr_pack_u32(b, rpc_id);
437 437
438 return rpc_buf; 438 return rpc_buf;
439} 439}
@@ -446,9 +446,9 @@ wlc_rpc_id_get(struct rpc_info *rpc, rpc_buf_t *buf)
446 bcm_xdr_buf_t b; 446 bcm_xdr_buf_t b;
447 447
448 bcm_xdr_buf_init(&b, bcm_rpc_buf_data(bcm_rpc_tp_get(rpc), buf), 448 bcm_xdr_buf_init(&b, bcm_rpc_buf_data(bcm_rpc_tp_get(rpc), buf),
449 sizeof(uint32)); 449 sizeof(u32));
450 450
451 bcm_xdr_unpack_uint32(&b, (uint32 *) ((uintptr) & rpc_id)); 451 bcm_xdr_unpack_u32(&b, (u32 *) ((uintptr) & rpc_id));
452 return rpc_id; 452 return rpc_id;
453} 453}
454#endif 454#endif
@@ -488,12 +488,12 @@ extern void wlc_rpc_bmac_dump_txfifohist(wlc_hw_info_t *wlc_hw,
488extern void wlc_rpc_high_dispatch(wlc_rpc_ctx_t *ctx, struct rpc_buf *buf); 488extern void wlc_rpc_high_dispatch(wlc_rpc_ctx_t *ctx, struct rpc_buf *buf);
489#endif 489#endif
490 490
491/* Packed structure for ease of transport across RPC bus along uint32 boundary */ 491/* Packed structure for ease of transport across RPC bus along u32 boundary */
492typedef struct wlc_rpc_txstatus { 492typedef struct wlc_rpc_txstatus {
493 uint32 PAD_framelen; 493 u32 PAD_framelen;
494 uint32 status_frameid; 494 u32 status_frameid;
495 uint32 sequence_lasttxtime; 495 u32 sequence_lasttxtime;
496 uint32 ackphyrxsh_phyerr; 496 u32 ackphyrxsh_phyerr;
497} wlc_rpc_txstatus_t; 497} wlc_rpc_txstatus_t;
498 498
499static inline 499static inline
diff --git a/drivers/staging/brcm80211/sys/wlc_scb.h b/drivers/staging/brcm80211/sys/wlc_scb.h
index 388fff4a35f..a4967787c7a 100644
--- a/drivers/staging/brcm80211/sys/wlc_scb.h
+++ b/drivers/staging/brcm80211/sys/wlc_scb.h
@@ -24,7 +24,7 @@ extern bool wlc_aggregatable(wlc_info_t *wlc, u8 tid);
24#define AMPDU_TX_BA_MAX_WSIZE 64 /* max Tx ba window size (in pdu) */ 24#define AMPDU_TX_BA_MAX_WSIZE 64 /* max Tx ba window size (in pdu) */
25/* structure to store per-tid state for the ampdu initiator */ 25/* structure to store per-tid state for the ampdu initiator */
26typedef struct scb_ampdu_tid_ini { 26typedef struct scb_ampdu_tid_ini {
27 uint32 magic; 27 u32 magic;
28 u8 tx_in_transit; /* number of pending mpdus in transit in driver */ 28 u8 tx_in_transit; /* number of pending mpdus in transit in driver */
29 u8 tid; /* initiator tid for easy lookup */ 29 u8 tid; /* initiator tid for easy lookup */
30 u8 txretry[AMPDU_TX_BA_MAX_WSIZE]; /* tx retry count; indexed by seq modulo */ 30 u8 txretry[AMPDU_TX_BA_MAX_WSIZE]; /* tx retry count; indexed by seq modulo */
@@ -39,7 +39,7 @@ typedef struct scb_ampdu {
39 u8 max_pdu; /* max pdus allowed in ampdu */ 39 u8 max_pdu; /* max pdus allowed in ampdu */
40 u8 release; /* # of mpdus released at a time */ 40 u8 release; /* # of mpdus released at a time */
41 u16 min_len; /* min mpdu len to support the density */ 41 u16 min_len; /* min mpdu len to support the density */
42 uint32 max_rxlen; /* max ampdu rcv length; 8k, 16k, 32k, 64k */ 42 u32 max_rxlen; /* max ampdu rcv length; 8k, 16k, 32k, 64k */
43 struct pktq txq; /* sdu transmit queue pending aggregation */ 43 struct pktq txq; /* sdu transmit queue pending aggregation */
44 44
45 /* This could easily be a ini[] pointer and we keep this info in wl itself instead 45 /* This could easily be a ini[] pointer and we keep this info in wl itself instead
@@ -54,9 +54,9 @@ typedef struct scb_ampdu {
54 54
55/* station control block - one per remote MAC address */ 55/* station control block - one per remote MAC address */
56struct scb { 56struct scb {
57 uint32 magic; 57 u32 magic;
58 uint32 flags; /* various bit flags as defined below */ 58 u32 flags; /* various bit flags as defined below */
59 uint32 flags2; /* various bit flags2 as defined below */ 59 u32 flags2; /* various bit flags2 as defined below */
60 u8 state; /* current state bitfield of auth/assoc process */ 60 u8 state; /* current state bitfield of auth/assoc process */
61 struct ether_addr ea; /* station address */ 61 struct ether_addr ea; /* station address */
62 void *fragbuf[NUMPRIO]; /* defragmentation buffer per prio */ 62 void *fragbuf[NUMPRIO]; /* defragmentation buffer per prio */
diff --git a/drivers/staging/brcm80211/util/aiutils.c b/drivers/staging/brcm80211/util/aiutils.c
index 5a020d15219..c8e535ca562 100644
--- a/drivers/staging/brcm80211/util/aiutils.c
+++ b/drivers/staging/brcm80211/util/aiutils.c
@@ -33,10 +33,10 @@
33 33
34/* EROM parsing */ 34/* EROM parsing */
35 35
36static uint32 36static u32
37get_erom_ent(si_t *sih, uint32 **eromptr, uint32 mask, uint32 match) 37get_erom_ent(si_t *sih, u32 **eromptr, u32 mask, u32 match)
38{ 38{
39 uint32 ent; 39 u32 ent;
40 uint inv = 0, nom = 0; 40 uint inv = 0, nom = 0;
41 41
42 while (TRUE) { 42 while (TRUE) {
@@ -68,11 +68,11 @@ get_erom_ent(si_t *sih, uint32 **eromptr, uint32 mask, uint32 match)
68 return ent; 68 return ent;
69} 69}
70 70
71static uint32 71static u32
72get_asd(si_t *sih, uint32 **eromptr, uint sp, uint ad, uint st, 72get_asd(si_t *sih, u32 **eromptr, uint sp, uint ad, uint st,
73 uint32 *addrl, uint32 *addrh, uint32 *sizel, uint32 *sizeh) 73 u32 *addrl, u32 *addrh, u32 *sizel, u32 *sizeh)
74{ 74{
75 uint32 asd, sz, szd; 75 u32 asd, sz, szd;
76 76
77 asd = get_erom_ent(sih, eromptr, ER_VALID, ER_VALID); 77 asd = get_erom_ent(sih, eromptr, ER_VALID, ER_VALID);
78 if (((asd & ER_TAG1) != ER_ADD) || 78 if (((asd & ER_TAG1) != ER_ADD) ||
@@ -112,13 +112,13 @@ void BCMATTACHFN(ai_scan) (si_t *sih, void *regs, uint devid)
112{ 112{
113 si_info_t *sii = SI_INFO(sih); 113 si_info_t *sii = SI_INFO(sih);
114 chipcregs_t *cc = (chipcregs_t *) regs; 114 chipcregs_t *cc = (chipcregs_t *) regs;
115 uint32 erombase, *eromptr, *eromlim; 115 u32 erombase, *eromptr, *eromlim;
116 116
117 erombase = R_REG(sii->osh, &cc->eromptr); 117 erombase = R_REG(sii->osh, &cc->eromptr);
118 118
119 switch (BUSTYPE(sih->bustype)) { 119 switch (BUSTYPE(sih->bustype)) {
120 case SI_BUS: 120 case SI_BUS:
121 eromptr = (uint32 *) REG_MAP(erombase, SI_CORE_SIZE); 121 eromptr = (u32 *) REG_MAP(erombase, SI_CORE_SIZE);
122 break; 122 break;
123 123
124 case PCI_BUS: 124 case PCI_BUS:
@@ -134,7 +134,7 @@ void BCMATTACHFN(ai_scan) (si_t *sih, void *regs, uint devid)
134 case SPI_BUS: 134 case SPI_BUS:
135 case SDIO_BUS: 135 case SDIO_BUS:
136#endif /* BCMSDIO */ 136#endif /* BCMSDIO */
137 eromptr = (uint32 *) (uintptr) erombase; 137 eromptr = (u32 *) (uintptr) erombase;
138 break; 138 break;
139 139
140 default: 140 default:
@@ -143,13 +143,13 @@ void BCMATTACHFN(ai_scan) (si_t *sih, void *regs, uint devid)
143 ASSERT(0); 143 ASSERT(0);
144 return; 144 return;
145 } 145 }
146 eromlim = eromptr + (ER_REMAPCONTROL / sizeof(uint32)); 146 eromlim = eromptr + (ER_REMAPCONTROL / sizeof(u32));
147 147
148 SI_VMSG(("ai_scan: regs = 0x%p, erombase = 0x%08x, eromptr = 0x%p, eromlim = 0x%p\n", regs, erombase, eromptr, eromlim)); 148 SI_VMSG(("ai_scan: regs = 0x%p, erombase = 0x%08x, eromptr = 0x%p, eromlim = 0x%p\n", regs, erombase, eromptr, eromlim));
149 while (eromptr < eromlim) { 149 while (eromptr < eromlim) {
150 uint32 cia, cib, cid, mfg, crev, nmw, nsw, nmp, nsp; 150 u32 cia, cib, cid, mfg, crev, nmw, nsw, nmp, nsp;
151 uint32 mpd, asd, addrl, addrh, sizel, sizeh; 151 u32 mpd, asd, addrl, addrh, sizel, sizeh;
152 uint32 *base; 152 u32 *base;
153 uint i, j, idx; 153 uint i, j, idx;
154 bool br; 154 bool br;
155 155
@@ -317,8 +317,8 @@ void BCMATTACHFN(ai_scan) (si_t *sih, void *regs, uint devid)
317void *ai_setcoreidx(si_t *sih, uint coreidx) 317void *ai_setcoreidx(si_t *sih, uint coreidx)
318{ 318{
319 si_info_t *sii = SI_INFO(sih); 319 si_info_t *sii = SI_INFO(sih);
320 uint32 addr = sii->coresba[coreidx]; 320 u32 addr = sii->coresba[coreidx];
321 uint32 wrap = sii->wrapba[coreidx]; 321 u32 wrap = sii->wrapba[coreidx];
322 void *regs; 322 void *regs;
323 323
324 if (coreidx >= sii->numcores) 324 if (coreidx >= sii->numcores)
@@ -381,7 +381,7 @@ int ai_numaddrspaces(si_t *sih)
381} 381}
382 382
383/* Return the address of the nth address space in the current core */ 383/* Return the address of the nth address space in the current core */
384uint32 ai_addrspace(si_t *sih, uint asidx) 384u32 ai_addrspace(si_t *sih, uint asidx)
385{ 385{
386 si_info_t *sii; 386 si_info_t *sii;
387 uint cidx; 387 uint cidx;
@@ -400,7 +400,7 @@ uint32 ai_addrspace(si_t *sih, uint asidx)
400} 400}
401 401
402/* Return the size of the nth address space in the current core */ 402/* Return the size of the nth address space in the current core */
403uint32 ai_addrspacesize(si_t *sih, uint asidx) 403u32 ai_addrspacesize(si_t *sih, uint asidx)
404{ 404{
405 si_info_t *sii; 405 si_info_t *sii;
406 uint cidx; 406 uint cidx;
@@ -437,10 +437,10 @@ void ai_setint(si_t *sih, int siflag)
437{ 437{
438} 438}
439 439
440void ai_write_wrap_reg(si_t *sih, uint32 offset, uint32 val) 440void ai_write_wrap_reg(si_t *sih, u32 offset, u32 val)
441{ 441{
442 si_info_t *sii = SI_INFO(sih); 442 si_info_t *sii = SI_INFO(sih);
443 uint32 *w = (uint32 *) sii->curwrap; 443 u32 *w = (u32 *) sii->curwrap;
444 W_REG(sii->osh, w + (offset / 4), val); 444 W_REG(sii->osh, w + (offset / 4), val);
445 return; 445 return;
446} 446}
@@ -448,7 +448,7 @@ void ai_write_wrap_reg(si_t *sih, uint32 offset, uint32 val)
448uint ai_corevendor(si_t *sih) 448uint ai_corevendor(si_t *sih)
449{ 449{
450 si_info_t *sii; 450 si_info_t *sii;
451 uint32 cia; 451 u32 cia;
452 452
453 sii = SI_INFO(sih); 453 sii = SI_INFO(sih);
454 cia = sii->cia[sii->curidx]; 454 cia = sii->cia[sii->curidx];
@@ -458,7 +458,7 @@ uint ai_corevendor(si_t *sih)
458uint ai_corerev(si_t *sih) 458uint ai_corerev(si_t *sih)
459{ 459{
460 si_info_t *sii; 460 si_info_t *sii;
461 uint32 cib; 461 u32 cib;
462 462
463 sii = SI_INFO(sih); 463 sii = SI_INFO(sih);
464 cib = sii->cib[sii->curidx]; 464 cib = sii->cib[sii->curidx];
@@ -490,7 +490,7 @@ bool ai_iscoreup(si_t *sih)
490uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val) 490uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
491{ 491{
492 uint origidx = 0; 492 uint origidx = 0;
493 uint32 *r = NULL; 493 u32 *r = NULL;
494 uint w; 494 uint w;
495 uint intr_val = 0; 495 uint intr_val = 0;
496 bool fast = FALSE; 496 bool fast = FALSE;
@@ -514,7 +514,7 @@ uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
514 SI_CORE_SIZE); 514 SI_CORE_SIZE);
515 ASSERT(GOODREGS(sii->regs[coreidx])); 515 ASSERT(GOODREGS(sii->regs[coreidx]));
516 } 516 }
517 r = (uint32 *) ((unsigned char *) sii->regs[coreidx] + regoff); 517 r = (u32 *) ((unsigned char *) sii->regs[coreidx] + regoff);
518 } else if (BUSTYPE(sih->bustype) == PCI_BUS) { 518 } else if (BUSTYPE(sih->bustype) == PCI_BUS) {
519 /* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */ 519 /* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */
520 520
@@ -522,7 +522,7 @@ uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
522 /* Chipc registers are mapped at 12KB */ 522 /* Chipc registers are mapped at 12KB */
523 523
524 fast = TRUE; 524 fast = TRUE;
525 r = (uint32 *) ((char *)sii->curmap + 525 r = (u32 *) ((char *)sii->curmap +
526 PCI_16KB0_CCREGS_OFFSET + regoff); 526 PCI_16KB0_CCREGS_OFFSET + regoff);
527 } else if (sii->pub.buscoreidx == coreidx) { 527 } else if (sii->pub.buscoreidx == coreidx) {
528 /* pci registers are at either in the last 2KB of an 8KB window 528 /* pci registers are at either in the last 2KB of an 8KB window
@@ -530,11 +530,11 @@ uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
530 */ 530 */
531 fast = TRUE; 531 fast = TRUE;
532 if (SI_FAST(sii)) 532 if (SI_FAST(sii))
533 r = (uint32 *) ((char *)sii->curmap + 533 r = (u32 *) ((char *)sii->curmap +
534 PCI_16KB0_PCIREGS_OFFSET + 534 PCI_16KB0_PCIREGS_OFFSET +
535 regoff); 535 regoff);
536 else 536 else
537 r = (uint32 *) ((char *)sii->curmap + 537 r = (u32 *) ((char *)sii->curmap +
538 ((regoff >= SBCONFIGOFF) ? 538 ((regoff >= SBCONFIGOFF) ?
539 PCI_BAR0_PCISBR_OFFSET : 539 PCI_BAR0_PCISBR_OFFSET :
540 PCI_BAR0_PCIREGS_OFFSET) + 540 PCI_BAR0_PCIREGS_OFFSET) +
@@ -549,7 +549,7 @@ uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
549 origidx = si_coreidx(&sii->pub); 549 origidx = si_coreidx(&sii->pub);
550 550
551 /* switch core */ 551 /* switch core */
552 r = (uint32 *) ((unsigned char *) ai_setcoreidx(&sii->pub, coreidx) + 552 r = (u32 *) ((unsigned char *) ai_setcoreidx(&sii->pub, coreidx) +
553 regoff); 553 regoff);
554 } 554 }
555 ASSERT(r != NULL); 555 ASSERT(r != NULL);
@@ -574,10 +574,10 @@ uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
574 return w; 574 return w;
575} 575}
576 576
577void ai_core_disable(si_t *sih, uint32 bits) 577void ai_core_disable(si_t *sih, u32 bits)
578{ 578{
579 si_info_t *sii; 579 si_info_t *sii;
580 volatile uint32 dummy; 580 volatile u32 dummy;
581 aidmp_t *ai; 581 aidmp_t *ai;
582 582
583 sii = SI_INFO(sih); 583 sii = SI_INFO(sih);
@@ -602,11 +602,11 @@ void ai_core_disable(si_t *sih, uint32 bits)
602 * bits - core specific bits that are set during and after reset sequence 602 * bits - core specific bits that are set during and after reset sequence
603 * resetbits - core specific bits that are set only during reset sequence 603 * resetbits - core specific bits that are set only during reset sequence
604 */ 604 */
605void ai_core_reset(si_t *sih, uint32 bits, uint32 resetbits) 605void ai_core_reset(si_t *sih, u32 bits, u32 resetbits)
606{ 606{
607 si_info_t *sii; 607 si_info_t *sii;
608 aidmp_t *ai; 608 aidmp_t *ai;
609 volatile uint32 dummy; 609 volatile u32 dummy;
610 610
611 sii = SI_INFO(sih); 611 sii = SI_INFO(sih);
612 ASSERT(GOODREGS(sii->curwrap)); 612 ASSERT(GOODREGS(sii->curwrap));
@@ -630,11 +630,11 @@ void ai_core_reset(si_t *sih, uint32 bits, uint32 resetbits)
630 OSL_DELAY(1); 630 OSL_DELAY(1);
631} 631}
632 632
633void ai_core_cflags_wo(si_t *sih, uint32 mask, uint32 val) 633void ai_core_cflags_wo(si_t *sih, u32 mask, u32 val)
634{ 634{
635 si_info_t *sii; 635 si_info_t *sii;
636 aidmp_t *ai; 636 aidmp_t *ai;
637 uint32 w; 637 u32 w;
638 638
639 sii = SI_INFO(sih); 639 sii = SI_INFO(sih);
640 640
@@ -655,11 +655,11 @@ void ai_core_cflags_wo(si_t *sih, uint32 mask, uint32 val)
655 } 655 }
656} 656}
657 657
658uint32 ai_core_cflags(si_t *sih, uint32 mask, uint32 val) 658u32 ai_core_cflags(si_t *sih, u32 mask, u32 val)
659{ 659{
660 si_info_t *sii; 660 si_info_t *sii;
661 aidmp_t *ai; 661 aidmp_t *ai;
662 uint32 w; 662 u32 w;
663 663
664 sii = SI_INFO(sih); 664 sii = SI_INFO(sih);
665 if (BCM47162_DMP()) { 665 if (BCM47162_DMP()) {
@@ -681,11 +681,11 @@ uint32 ai_core_cflags(si_t *sih, uint32 mask, uint32 val)
681 return R_REG(sii->osh, &ai->ioctrl); 681 return R_REG(sii->osh, &ai->ioctrl);
682} 682}
683 683
684uint32 ai_core_sflags(si_t *sih, uint32 mask, uint32 val) 684u32 ai_core_sflags(si_t *sih, u32 mask, u32 val)
685{ 685{
686 si_info_t *sii; 686 si_info_t *sii;
687 aidmp_t *ai; 687 aidmp_t *ai;
688 uint32 w; 688 u32 w;
689 689
690 sii = SI_INFO(sih); 690 sii = SI_INFO(sih);
691 if (BCM47162_DMP()) { 691 if (BCM47162_DMP()) {
diff --git a/drivers/staging/brcm80211/util/bcmotp.c b/drivers/staging/brcm80211/util/bcmotp.c
index 5bfc0eeaa58..2a189437329 100644
--- a/drivers/staging/brcm80211/util/bcmotp.c
+++ b/drivers/staging/brcm80211/util/bcmotp.c
@@ -85,7 +85,7 @@ typedef struct {
85 u16 wsize; /* Size of otp in words */ 85 u16 wsize; /* Size of otp in words */
86 u16 rows; /* Geometry */ 86 u16 rows; /* Geometry */
87 u16 cols; /* Geometry */ 87 u16 cols; /* Geometry */
88 uint32 status; /* Flag bits (lock/prog/rv). 88 u32 status; /* Flag bits (lock/prog/rv).
89 * (Reflected only when OTP is power cycled) 89 * (Reflected only when OTP is power cycled)
90 */ 90 */
91 u16 hwbase; /* hardware subregion offset */ 91 u16 hwbase; /* hardware subregion offset */
@@ -189,7 +189,7 @@ static u16 ipxotp_read_bit(void *oh, chipcregs_t *cc, uint off)
189{ 189{
190 otpinfo_t *oi = (otpinfo_t *) oh; 190 otpinfo_t *oi = (otpinfo_t *) oh;
191 uint k, row, col; 191 uint k, row, col;
192 uint32 otpp, st; 192 u32 otpp, st;
193 193
194 row = off / oi->cols; 194 row = off / oi->cols;
195 col = off % oi->cols; 195 col = off % oi->cols;
@@ -240,7 +240,7 @@ static int ipxotp_max_rgnsz(si_t *sih, int osizew)
240static void BCMNMIATTACHFN(_ipxotp_init) (otpinfo_t *oi, chipcregs_t *cc) 240static void BCMNMIATTACHFN(_ipxotp_init) (otpinfo_t *oi, chipcregs_t *cc)
241{ 241{
242 uint k; 242 uint k;
243 uint32 otpp, st; 243 u32 otpp, st;
244 244
245 /* record word offset of General Use Region for various chipcommon revs */ 245 /* record word offset of General Use Region for various chipcommon revs */
246 if (oi->sih->ccrev == 21 || oi->sih->ccrev == 24 246 if (oi->sih->ccrev == 21 || oi->sih->ccrev == 24
@@ -274,7 +274,7 @@ static void BCMNMIATTACHFN(_ipxotp_init) (otpinfo_t *oi, chipcregs_t *cc)
274 274
275 if ((CHIPID(oi->sih->chip) == BCM43224_CHIP_ID) 275 if ((CHIPID(oi->sih->chip) == BCM43224_CHIP_ID)
276 || (CHIPID(oi->sih->chip) == BCM43225_CHIP_ID)) { 276 || (CHIPID(oi->sih->chip) == BCM43225_CHIP_ID)) {
277 uint32 p_bits; 277 u32 p_bits;
278 p_bits = 278 p_bits =
279 (ipxotp_otpr(oi, cc, oi->otpgu_base + OTPGU_P_OFF) & 279 (ipxotp_otpr(oi, cc, oi->otpgu_base + OTPGU_P_OFF) &
280 OTPGU_P_MSK) 280 OTPGU_P_MSK)
@@ -603,7 +603,7 @@ static u16 hndotp_read_bit(void *oh, chipcregs_t *cc, uint idx)
603{ 603{
604 otpinfo_t *oi = (otpinfo_t *) oh; 604 otpinfo_t *oi = (otpinfo_t *) oh;
605 uint k, row, col; 605 uint k, row, col;
606 uint32 otpp, st; 606 u32 otpp, st;
607 osl_t *osh; 607 osl_t *osh;
608 608
609 osh = si_osh(oi->sih); 609 osh = si_osh(oi->sih);
@@ -635,7 +635,7 @@ static void *BCMNMIATTACHFN(hndotp_init) (si_t *sih)
635 uint idx; 635 uint idx;
636 chipcregs_t *cc; 636 chipcregs_t *cc;
637 otpinfo_t *oi; 637 otpinfo_t *oi;
638 uint32 cap = 0, clkdiv, otpdiv = 0; 638 u32 cap = 0, clkdiv, otpdiv = 0;
639 void *ret = NULL; 639 void *ret = NULL;
640 osl_t *osh; 640 osl_t *osh;
641 641
@@ -709,7 +709,7 @@ static void *BCMNMIATTACHFN(hndotp_init) (si_t *sih)
709static int hndotp_read_region(void *oh, int region, u16 *data, uint *wlen) 709static int hndotp_read_region(void *oh, int region, u16 *data, uint *wlen)
710{ 710{
711 otpinfo_t *oi = (otpinfo_t *) oh; 711 otpinfo_t *oi = (otpinfo_t *) oh;
712 uint32 idx, st; 712 u32 idx, st;
713 chipcregs_t *cc; 713 chipcregs_t *cc;
714 int i; 714 int i;
715 715
@@ -740,9 +740,9 @@ static int hndotp_nvread(void *oh, char *data, uint *len)
740{ 740{
741 int rc = 0; 741 int rc = 0;
742 otpinfo_t *oi = (otpinfo_t *) oh; 742 otpinfo_t *oi = (otpinfo_t *) oh;
743 uint32 base, bound, lim = 0, st; 743 u32 base, bound, lim = 0, st;
744 int i, chunk, gchunks, tsz = 0; 744 int i, chunk, gchunks, tsz = 0;
745 uint32 idx; 745 u32 idx;
746 chipcregs_t *cc; 746 chipcregs_t *cc;
747 uint offset; 747 uint offset;
748 u16 *rawotp = NULL; 748 u16 *rawotp = NULL;
diff --git a/drivers/staging/brcm80211/util/bcmsrom.c b/drivers/staging/brcm80211/util/bcmsrom.c
index 73e48a650d8..3b3f3b1955a 100644
--- a/drivers/staging/brcm80211/util/bcmsrom.c
+++ b/drivers/staging/brcm80211/util/bcmsrom.c
@@ -85,7 +85,7 @@ static int sprom_read_pci(osl_t *osh, si_t *sih, u16 *sprom, uint wordoff,
85#if defined(BCMNVRAMR) 85#if defined(BCMNVRAMR)
86static int otp_read_pci(osl_t *osh, si_t *sih, u16 *buf, uint bufsz); 86static int otp_read_pci(osl_t *osh, si_t *sih, u16 *buf, uint bufsz);
87#endif 87#endif
88static u16 srom_cc_cmd(si_t *sih, osl_t *osh, void *ccregs, uint32 cmd, 88static u16 srom_cc_cmd(si_t *sih, osl_t *osh, void *ccregs, u32 cmd,
89 uint wordoff, u16 data); 89 uint wordoff, u16 data);
90 90
91static int initvars_table(osl_t *osh, char *start, char *end, char **vars, 91static int initvars_table(osl_t *osh, char *start, char *end, char **vars,
@@ -388,7 +388,7 @@ BCMATTACHFN(srom_parsecis) (osl_t *osh, u8 *pcis[], uint ciscnt,
388 u8 *cis, tup, tlen, sromrev = 1; 388 u8 *cis, tup, tlen, sromrev = 1;
389 int i, j; 389 int i, j;
390 bool ag_init = FALSE; 390 bool ag_init = FALSE;
391 uint32 w32; 391 u32 w32;
392 uint funcid; 392 uint funcid;
393 uint cisnum; 393 uint cisnum;
394 int32 boardnum; 394 int32 boardnum;
@@ -1413,7 +1413,7 @@ BCMATTACHFN(srom_parsecis) (osl_t *osh, u8 *pcis[], uint ciscnt,
1413 * not in the bus cores. 1413 * not in the bus cores.
1414 */ 1414 */
1415static u16 1415static u16
1416srom_cc_cmd(si_t *sih, osl_t *osh, void *ccregs, uint32 cmd, uint wordoff, 1416srom_cc_cmd(si_t *sih, osl_t *osh, void *ccregs, u32 cmd, uint wordoff,
1417 u16 data) 1417 u16 data)
1418{ 1418{
1419 chipcregs_t *cc = (chipcregs_t *) ccregs; 1419 chipcregs_t *cc = (chipcregs_t *) ccregs;
@@ -1708,11 +1708,11 @@ static void
1708BCMATTACHFN(_initvars_srom_pci) (u8 sromrev, u16 *srom, uint off, 1708BCMATTACHFN(_initvars_srom_pci) (u8 sromrev, u16 *srom, uint off,
1709 varbuf_t *b) { 1709 varbuf_t *b) {
1710 u16 w; 1710 u16 w;
1711 uint32 val; 1711 u32 val;
1712 const sromvar_t *srv; 1712 const sromvar_t *srv;
1713 uint width; 1713 uint width;
1714 uint flags; 1714 uint flags;
1715 uint32 sr = (1 << sromrev); 1715 u32 sr = (1 << sromrev);
1716 1716
1717 varbuf_append(b, "sromrev=%d", sromrev); 1717 varbuf_append(b, "sromrev=%d", sromrev);
1718 1718
@@ -1786,7 +1786,7 @@ BCMATTACHFN(_initvars_srom_pci) (u8 sromrev, u16 *srom, uint off,
1786 *(oncount >> 24) (offcount >> 8) 1786 *(oncount >> 24) (offcount >> 8)
1787 */ 1787 */
1788 else if (flags & SRFL_LEDDC) { 1788 else if (flags & SRFL_LEDDC) {
1789 uint32 w32 = (((val >> 8) & 0xff) << 24) | /* oncount */ 1789 u32 w32 = (((val >> 8) & 0xff) << 24) | /* oncount */
1790 (((val & 0xff)) << 8); /* offcount */ 1790 (((val & 0xff)) << 8); /* offcount */
1791 varbuf_append(b, "leddc=%d", w32); 1791 varbuf_append(b, "leddc=%d", w32);
1792 } else if (flags & SRFL_PRHEX) 1792 } else if (flags & SRFL_PRHEX)
@@ -1858,7 +1858,7 @@ BCMATTACHFN(initvars_srom_pci) (si_t *sih, void *curmap, char **vars,
1858 uint *count) { 1858 uint *count) {
1859 u16 *srom, *sromwindow; 1859 u16 *srom, *sromwindow;
1860 u8 sromrev = 0; 1860 u8 sromrev = 0;
1861 uint32 sr; 1861 u32 sr;
1862 varbuf_t b; 1862 varbuf_t b;
1863 char *vp, *base = NULL; 1863 char *vp, *base = NULL;
1864 osl_t *osh = si_osh(sih); 1864 osl_t *osh = si_osh(sih);
@@ -1922,7 +1922,7 @@ BCMATTACHFN(initvars_srom_pci) (si_t *sih, void *curmap, char **vars,
1922 */ 1922 */
1923 if (err) { 1923 if (err) {
1924 char *value; 1924 char *value;
1925 uint32 val; 1925 u32 val;
1926 val = 0; 1926 val = 0;
1927 1927
1928 value = si_getdevpathvar(sih, "sromrev"); 1928 value = si_getdevpathvar(sih, "sromrev");
diff --git a/drivers/staging/brcm80211/util/bcmutils.c b/drivers/staging/brcm80211/util/bcmutils.c
index e36937a3950..03240ac01d9 100644
--- a/drivers/staging/brcm80211/util/bcmutils.c
+++ b/drivers/staging/brcm80211/util/bcmutils.c
@@ -566,13 +566,13 @@ bcm_tlv_t *BCMROMFN(bcm_parse_tlvs) (void *buf, int buflen, uint key)
566 566
567#if defined(BCMDBG) 567#if defined(BCMDBG)
568int 568int
569bcm_format_flags(const bcm_bit_desc_t *bd, uint32 flags, char *buf, int len) 569bcm_format_flags(const bcm_bit_desc_t *bd, u32 flags, char *buf, int len)
570{ 570{
571 int i; 571 int i;
572 char *p = buf; 572 char *p = buf;
573 char hexstr[16]; 573 char hexstr[16];
574 int slen = 0, nlen = 0; 574 int slen = 0, nlen = 0;
575 uint32 bit; 575 u32 bit;
576 const char *name; 576 const char *name;
577 577
578 if (len < 2 || !buf) 578 if (len < 2 || !buf)
diff --git a/drivers/staging/brcm80211/util/hnddma.c b/drivers/staging/brcm80211/util/hnddma.c
index dd6e0d919f9..6a6bba21fbd 100644
--- a/drivers/staging/brcm80211/util/hnddma.c
+++ b/drivers/staging/brcm80211/util/hnddma.c
@@ -109,8 +109,8 @@ typedef struct dma_info {
109 dmaaddr_t txdpa; /* Aligned physical address of descriptor ring */ 109 dmaaddr_t txdpa; /* Aligned physical address of descriptor ring */
110 dmaaddr_t txdpaorig; /* Original physical address of descriptor ring */ 110 dmaaddr_t txdpaorig; /* Original physical address of descriptor ring */
111 u16 txdalign; /* #bytes added to alloc'd mem to align txd */ 111 u16 txdalign; /* #bytes added to alloc'd mem to align txd */
112 uint32 txdalloc; /* #bytes allocated for the ring */ 112 u32 txdalloc; /* #bytes allocated for the ring */
113 uint32 xmtptrbase; /* When using unaligned descriptors, the ptr register 113 u32 xmtptrbase; /* When using unaligned descriptors, the ptr register
114 * is not just an index, it needs all 13 bits to be 114 * is not just an index, it needs all 13 bits to be
115 * an offset from the addr register. 115 * an offset from the addr register.
116 */ 116 */
@@ -124,8 +124,8 @@ typedef struct dma_info {
124 dmaaddr_t rxdpa; /* Aligned physical address of descriptor ring */ 124 dmaaddr_t rxdpa; /* Aligned physical address of descriptor ring */
125 dmaaddr_t rxdpaorig; /* Original physical address of descriptor ring */ 125 dmaaddr_t rxdpaorig; /* Original physical address of descriptor ring */
126 u16 rxdalign; /* #bytes added to alloc'd mem to align rxd */ 126 u16 rxdalign; /* #bytes added to alloc'd mem to align rxd */
127 uint32 rxdalloc; /* #bytes allocated for the ring */ 127 u32 rxdalloc; /* #bytes allocated for the ring */
128 uint32 rcvptrbase; /* Base for ptr reg when using unaligned descriptors */ 128 u32 rcvptrbase; /* Base for ptr reg when using unaligned descriptors */
129 129
130 /* tunables */ 130 /* tunables */
131 u16 rxbufsize; /* rx buffer size in bytes, 131 u16 rxbufsize; /* rx buffer size in bytes,
@@ -223,7 +223,7 @@ static void _dma_counterreset(dma_info_t *di);
223static void _dma_fifoloopbackenable(dma_info_t *di); 223static void _dma_fifoloopbackenable(dma_info_t *di);
224static uint _dma_ctrlflags(dma_info_t *di, uint mask, uint flags); 224static uint _dma_ctrlflags(dma_info_t *di, uint mask, uint flags);
225static u8 dma_align_sizetobits(uint size); 225static u8 dma_align_sizetobits(uint size);
226static void *dma_ringalloc(osl_t *osh, uint32 boundary, uint size, 226static void *dma_ringalloc(osl_t *osh, u32 boundary, uint size,
227 u16 *alignbits, uint *alloced, 227 u16 *alignbits, uint *alloced,
228 dmaaddr_t *descpa, osldma_t **dmah); 228 dmaaddr_t *descpa, osldma_t **dmah);
229 229
@@ -273,7 +273,7 @@ static bool dma64_rxstopped(dma_info_t *di);
273static bool dma64_rxenabled(dma_info_t *di); 273static bool dma64_rxenabled(dma_info_t *di);
274static bool _dma64_addrext(osl_t *osh, dma64regs_t *dma64regs); 274static bool _dma64_addrext(osl_t *osh, dma64regs_t *dma64regs);
275 275
276static inline uint32 parity32(uint32 data); 276static inline u32 parity32(u32 data);
277 277
278const di_fcn_t dma64proc = { 278const di_fcn_t dma64proc = {
279 (di_detach_t) _dma_detach, 279 (di_detach_t) _dma_detach,
@@ -548,11 +548,11 @@ hnddma_t *dma_attach(osl_t *osh, char *name, si_t *sih, void *dmaregstx,
548 548
549 if ((di->ddoffsetlow != 0) && !di->addrext) { 549 if ((di->ddoffsetlow != 0) && !di->addrext) {
550 if (PHYSADDRLO(di->txdpa) > SI_PCI_DMA_SZ) { 550 if (PHYSADDRLO(di->txdpa) > SI_PCI_DMA_SZ) {
551 DMA_ERROR(("%s: dma_attach: txdpa 0x%x: addrext not supported\n", di->name, (uint32) PHYSADDRLO(di->txdpa))); 551 DMA_ERROR(("%s: dma_attach: txdpa 0x%x: addrext not supported\n", di->name, (u32) PHYSADDRLO(di->txdpa)));
552 goto fail; 552 goto fail;
553 } 553 }
554 if (PHYSADDRLO(di->rxdpa) > SI_PCI_DMA_SZ) { 554 if (PHYSADDRLO(di->rxdpa) > SI_PCI_DMA_SZ) {
555 DMA_ERROR(("%s: dma_attach: rxdpa 0x%x: addrext not supported\n", di->name, (uint32) PHYSADDRLO(di->rxdpa))); 555 DMA_ERROR(("%s: dma_attach: rxdpa 0x%x: addrext not supported\n", di->name, (u32) PHYSADDRLO(di->rxdpa)));
556 goto fail; 556 goto fail;
557 } 557 }
558 } 558 }
@@ -588,7 +588,7 @@ hnddma_t *dma_attach(osl_t *osh, char *name, si_t *sih, void *dmaregstx,
588/* init the tx or rx descriptor */ 588/* init the tx or rx descriptor */
589static inline void 589static inline void
590dma32_dd_upd(dma_info_t *di, dma32dd_t *ddring, dmaaddr_t pa, uint outidx, 590dma32_dd_upd(dma_info_t *di, dma32dd_t *ddring, dmaaddr_t pa, uint outidx,
591 uint32 *flags, uint32 bufcount) 591 u32 *flags, u32 bufcount)
592{ 592{
593 /* dma32 uses 32-bit control to fit both flags and bufcounter */ 593 /* dma32 uses 32-bit control to fit both flags and bufcounter */
594 *flags = *flags | (bufcount & CTRL_BC_MASK); 594 *flags = *flags | (bufcount & CTRL_BC_MASK);
@@ -599,7 +599,7 @@ dma32_dd_upd(dma_info_t *di, dma32dd_t *ddring, dmaaddr_t pa, uint outidx,
599 W_SM(&ddring[outidx].ctrl, BUS_SWAP32(*flags)); 599 W_SM(&ddring[outidx].ctrl, BUS_SWAP32(*flags));
600 } else { 600 } else {
601 /* address extension */ 601 /* address extension */
602 uint32 ae; 602 u32 ae;
603 ASSERT(di->addrext); 603 ASSERT(di->addrext);
604 ae = (PHYSADDRLO(pa) & PCI32ADDR_HIGH) >> PCI32ADDR_HIGH_SHIFT; 604 ae = (PHYSADDRLO(pa) & PCI32ADDR_HIGH) >> PCI32ADDR_HIGH_SHIFT;
605 PHYSADDRLO(pa) &= ~PCI32ADDR_HIGH; 605 PHYSADDRLO(pa) &= ~PCI32ADDR_HIGH;
@@ -612,7 +612,7 @@ dma32_dd_upd(dma_info_t *di, dma32dd_t *ddring, dmaaddr_t pa, uint outidx,
612} 612}
613 613
614/* Check for odd number of 1's */ 614/* Check for odd number of 1's */
615static inline uint32 parity32(uint32 data) 615static inline u32 parity32(u32 data)
616{ 616{
617 data ^= data >> 16; 617 data ^= data >> 16;
618 data ^= data >> 8; 618 data ^= data >> 8;
@@ -627,9 +627,9 @@ static inline uint32 parity32(uint32 data)
627 627
628static inline void 628static inline void
629dma64_dd_upd(dma_info_t *di, dma64dd_t *ddring, dmaaddr_t pa, uint outidx, 629dma64_dd_upd(dma_info_t *di, dma64dd_t *ddring, dmaaddr_t pa, uint outidx,
630 uint32 *flags, uint32 bufcount) 630 u32 *flags, u32 bufcount)
631{ 631{
632 uint32 ctrl2 = bufcount & D64_CTRL2_BC_MASK; 632 u32 ctrl2 = bufcount & D64_CTRL2_BC_MASK;
633 633
634 /* PCI bus with big(>1G) physical address, use address extension */ 634 /* PCI bus with big(>1G) physical address, use address extension */
635#if defined(__mips__) && defined(IL_BIGENDIAN) 635#if defined(__mips__) && defined(IL_BIGENDIAN)
@@ -648,7 +648,7 @@ dma64_dd_upd(dma_info_t *di, dma64dd_t *ddring, dmaaddr_t pa, uint outidx,
648 W_SM(&ddring[outidx].ctrl2, BUS_SWAP32(ctrl2)); 648 W_SM(&ddring[outidx].ctrl2, BUS_SWAP32(ctrl2));
649 } else { 649 } else {
650 /* address extension for 32-bit PCI */ 650 /* address extension for 32-bit PCI */
651 uint32 ae; 651 u32 ae;
652 ASSERT(di->addrext); 652 ASSERT(di->addrext);
653 653
654 ae = (PHYSADDRLO(pa) & PCI32ADDR_HIGH) >> PCI32ADDR_HIGH_SHIFT; 654 ae = (PHYSADDRLO(pa) & PCI32ADDR_HIGH) >> PCI32ADDR_HIGH_SHIFT;
@@ -673,7 +673,7 @@ dma64_dd_upd(dma_info_t *di, dma64dd_t *ddring, dmaaddr_t pa, uint outidx,
673 673
674static bool _dma32_addrext(osl_t *osh, dma32regs_t *dma32regs) 674static bool _dma32_addrext(osl_t *osh, dma32regs_t *dma32regs)
675{ 675{
676 uint32 w; 676 u32 w;
677 677
678 OR_REG(osh, &dma32regs->control, XC_AE); 678 OR_REG(osh, &dma32regs->control, XC_AE);
679 w = R_REG(osh, &dma32regs->control); 679 w = R_REG(osh, &dma32regs->control);
@@ -751,7 +751,7 @@ static void _dma_detach(dma_info_t *di)
751static bool _dma_descriptor_align(dma_info_t *di) 751static bool _dma_descriptor_align(dma_info_t *di)
752{ 752{
753 if (DMA64_ENAB(di) && DMA64_MODE(di)) { 753 if (DMA64_ENAB(di) && DMA64_MODE(di)) {
754 uint32 addrl; 754 u32 addrl;
755 755
756 /* Check to see if the descriptors need to be aligned on 4K/8K or not */ 756 /* Check to see if the descriptors need to be aligned on 4K/8K or not */
757 if (di->d64txregs != NULL) { 757 if (di->d64txregs != NULL) {
@@ -827,7 +827,7 @@ static void _dma_ddtable_init(dma_info_t *di, uint direction, dmaaddr_t pa)
827 } 827 }
828 } else { 828 } else {
829 /* DMA64 32bits address extension */ 829 /* DMA64 32bits address extension */
830 uint32 ae; 830 u32 ae;
831 ASSERT(di->addrext); 831 ASSERT(di->addrext);
832 ASSERT(PHYSADDRHI(pa) == 0); 832 ASSERT(PHYSADDRHI(pa) == 0);
833 833
@@ -865,7 +865,7 @@ static void _dma_ddtable_init(dma_info_t *di, uint direction, dmaaddr_t pa)
865 (PHYSADDRLO(pa) + di->ddoffsetlow)); 865 (PHYSADDRLO(pa) + di->ddoffsetlow));
866 } else { 866 } else {
867 /* dma32 address extension */ 867 /* dma32 address extension */
868 uint32 ae; 868 u32 ae;
869 ASSERT(di->addrext); 869 ASSERT(di->addrext);
870 870
871 /* shift the high bit(s) from pa to ae */ 871 /* shift the high bit(s) from pa to ae */
@@ -941,7 +941,7 @@ static void _dma_rxenable(dma_info_t *di)
941 DMA_TRACE(("%s: dma_rxenable\n", di->name)); 941 DMA_TRACE(("%s: dma_rxenable\n", di->name));
942 942
943 if (DMA64_ENAB(di) && DMA64_MODE(di)) { 943 if (DMA64_ENAB(di) && DMA64_MODE(di)) {
944 uint32 control = 944 u32 control =
945 (R_REG(di->osh, &di->d64rxregs->control) & D64_RC_AE) | 945 (R_REG(di->osh, &di->d64rxregs->control) & D64_RC_AE) |
946 D64_RC_RE; 946 D64_RC_RE;
947 947
@@ -954,7 +954,7 @@ static void _dma_rxenable(dma_info_t *di)
954 W_REG(di->osh, &di->d64rxregs->control, 954 W_REG(di->osh, &di->d64rxregs->control,
955 ((di->rxoffset << D64_RC_RO_SHIFT) | control)); 955 ((di->rxoffset << D64_RC_RO_SHIFT) | control));
956 } else if (DMA32_ENAB(di)) { 956 } else if (DMA32_ENAB(di)) {
957 uint32 control = 957 u32 control =
958 (R_REG(di->osh, &di->d32rxregs->control) & RC_AE) | RC_RE; 958 (R_REG(di->osh, &di->d32rxregs->control) & RC_AE) | RC_RE;
959 959
960 if ((dmactrlflags & DMA_CTRL_PEN) == 0) 960 if ((dmactrlflags & DMA_CTRL_PEN) == 0)
@@ -1065,7 +1065,7 @@ static bool BCMFASTPATH _dma_rxfill(dma_info_t *di)
1065{ 1065{
1066 void *p; 1066 void *p;
1067 u16 rxin, rxout; 1067 u16 rxin, rxout;
1068 uint32 flags = 0; 1068 u32 flags = 0;
1069 uint n; 1069 uint n;
1070 uint i; 1070 uint i;
1071 dmaaddr_t pa; 1071 dmaaddr_t pa;
@@ -1124,7 +1124,7 @@ static bool BCMFASTPATH _dma_rxfill(dma_info_t *di)
1124 /* Do a cached write instead of uncached write since DMA_MAP 1124 /* Do a cached write instead of uncached write since DMA_MAP
1125 * will flush the cache. 1125 * will flush the cache.
1126 */ 1126 */
1127 *(uint32 *) (PKTDATA(p)) = 0; 1127 *(u32 *) (PKTDATA(p)) = 0;
1128 1128
1129 if (DMASGLIST_ENAB) 1129 if (DMASGLIST_ENAB)
1130 bzero(&di->rxp_dmah[rxout], sizeof(hnddma_seg_map_t)); 1130 bzero(&di->rxp_dmah[rxout], sizeof(hnddma_seg_map_t));
@@ -1335,7 +1335,7 @@ static uint _dma_ctrlflags(dma_info_t *di, uint mask, uint flags)
1335 1335
1336 /* If trying to enable parity, check if parity is actually supported */ 1336 /* If trying to enable parity, check if parity is actually supported */
1337 if (dmactrlflags & DMA_CTRL_PEN) { 1337 if (dmactrlflags & DMA_CTRL_PEN) {
1338 uint32 control; 1338 u32 control;
1339 1339
1340 if (DMA64_ENAB(di) && DMA64_MODE(di)) { 1340 if (DMA64_ENAB(di) && DMA64_MODE(di)) {
1341 control = R_REG(di->osh, &di->d64txregs->control); 1341 control = R_REG(di->osh, &di->d64txregs->control);
@@ -1405,20 +1405,20 @@ u8 dma_align_sizetobits(uint size)
1405 * descriptor ring size aligned location. This will ensure that the ring will 1405 * descriptor ring size aligned location. This will ensure that the ring will
1406 * not cross page boundary 1406 * not cross page boundary
1407 */ 1407 */
1408static void *dma_ringalloc(osl_t *osh, uint32 boundary, uint size, 1408static void *dma_ringalloc(osl_t *osh, u32 boundary, uint size,
1409 u16 *alignbits, uint *alloced, 1409 u16 *alignbits, uint *alloced,
1410 dmaaddr_t *descpa, osldma_t **dmah) 1410 dmaaddr_t *descpa, osldma_t **dmah)
1411{ 1411{
1412 void *va; 1412 void *va;
1413 uint32 desc_strtaddr; 1413 u32 desc_strtaddr;
1414 uint32 alignbytes = 1 << *alignbits; 1414 u32 alignbytes = 1 << *alignbits;
1415 1415
1416 va = DMA_ALLOC_CONSISTENT(osh, size, *alignbits, alloced, descpa, 1416 va = DMA_ALLOC_CONSISTENT(osh, size, *alignbits, alloced, descpa,
1417 dmah); 1417 dmah);
1418 if (NULL == va) 1418 if (NULL == va)
1419 return NULL; 1419 return NULL;
1420 1420
1421 desc_strtaddr = (uint32) ROUNDUP((uintptr) va, alignbytes); 1421 desc_strtaddr = (u32) ROUNDUP((uintptr) va, alignbytes);
1422 if (((desc_strtaddr + size - 1) & boundary) != (desc_strtaddr 1422 if (((desc_strtaddr + size - 1) & boundary) != (desc_strtaddr
1423 & boundary)) { 1423 & boundary)) {
1424 *alignbits = dma_align_sizetobits(size); 1424 *alignbits = dma_align_sizetobits(size);
@@ -1433,7 +1433,7 @@ static void *dma_ringalloc(osl_t *osh, uint32 boundary, uint size,
1433 1433
1434static void dma32_txinit(dma_info_t *di) 1434static void dma32_txinit(dma_info_t *di)
1435{ 1435{
1436 uint32 control = XC_XE; 1436 u32 control = XC_XE;
1437 1437
1438 DMA_TRACE(("%s: dma_txinit\n", di->name)); 1438 DMA_TRACE(("%s: dma_txinit\n", di->name));
1439 1439
@@ -1454,7 +1454,7 @@ static void dma32_txinit(dma_info_t *di)
1454 1454
1455static bool dma32_txenabled(dma_info_t *di) 1455static bool dma32_txenabled(dma_info_t *di)
1456{ 1456{
1457 uint32 xc; 1457 u32 xc;
1458 1458
1459 /* If the chip is dead, it is not enabled :-) */ 1459 /* If the chip is dead, it is not enabled :-) */
1460 xc = R_REG(di->osh, &di->d32txregs->control); 1460 xc = R_REG(di->osh, &di->d32txregs->control);
@@ -1581,7 +1581,7 @@ static bool dma32_alloc(dma_info_t *di, uint direction)
1581 1581
1582static bool dma32_txreset(dma_info_t *di) 1582static bool dma32_txreset(dma_info_t *di)
1583{ 1583{
1584 uint32 status; 1584 u32 status;
1585 1585
1586 if (di->ntxd == 0) 1586 if (di->ntxd == 0)
1587 return TRUE; 1587 return TRUE;
@@ -1617,7 +1617,7 @@ static bool dma32_rxidle(dma_info_t *di)
1617 1617
1618static bool dma32_rxreset(dma_info_t *di) 1618static bool dma32_rxreset(dma_info_t *di)
1619{ 1619{
1620 uint32 status; 1620 u32 status;
1621 1621
1622 if (di->nrxd == 0) 1622 if (di->nrxd == 0)
1623 return TRUE; 1623 return TRUE;
@@ -1632,7 +1632,7 @@ static bool dma32_rxreset(dma_info_t *di)
1632 1632
1633static bool dma32_rxenabled(dma_info_t *di) 1633static bool dma32_rxenabled(dma_info_t *di)
1634{ 1634{
1635 uint32 rc; 1635 u32 rc;
1636 1636
1637 rc = R_REG(di->osh, &di->d32rxregs->control); 1637 rc = R_REG(di->osh, &di->d32rxregs->control);
1638 return (rc != 0xffffffff) && (rc & RC_RE); 1638 return (rc != 0xffffffff) && (rc & RC_RE);
@@ -1667,7 +1667,7 @@ static int dma32_txfast(dma_info_t *di, void *p0, bool commit)
1667 unsigned char *data; 1667 unsigned char *data;
1668 uint len; 1668 uint len;
1669 u16 txout; 1669 u16 txout;
1670 uint32 flags = 0; 1670 u32 flags = 0;
1671 dmaaddr_t pa; 1671 dmaaddr_t pa;
1672 1672
1673 DMA_TRACE(("%s: dma_txfast\n", di->name)); 1673 DMA_TRACE(("%s: dma_txfast\n", di->name));
@@ -1922,7 +1922,7 @@ static void dma32_txrotate(dma_info_t *di)
1922 uint nactive; 1922 uint nactive;
1923 uint rot; 1923 uint rot;
1924 u16 old, new; 1924 u16 old, new;
1925 uint32 w; 1925 u32 w;
1926 u16 first, last; 1926 u16 first, last;
1927 1927
1928 ASSERT(dma32_txsuspendedidle(di)); 1928 ASSERT(dma32_txsuspendedidle(di));
@@ -1988,7 +1988,7 @@ static void dma32_txrotate(dma_info_t *di)
1988 1988
1989static void dma64_txinit(dma_info_t *di) 1989static void dma64_txinit(dma_info_t *di)
1990{ 1990{
1991 uint32 control = D64_XC_XE; 1991 u32 control = D64_XC_XE;
1992 1992
1993 DMA_TRACE(("%s: dma_txinit\n", di->name)); 1993 DMA_TRACE(("%s: dma_txinit\n", di->name));
1994 1994
@@ -2020,7 +2020,7 @@ static void dma64_txinit(dma_info_t *di)
2020 2020
2021static bool dma64_txenabled(dma_info_t *di) 2021static bool dma64_txenabled(dma_info_t *di)
2022{ 2022{
2023 uint32 xc; 2023 u32 xc;
2024 2024
2025 /* If the chip is dead, it is not enabled :-) */ 2025 /* If the chip is dead, it is not enabled :-) */
2026 xc = R_REG(di->osh, &di->d64txregs->control); 2026 xc = R_REG(di->osh, &di->d64txregs->control);
@@ -2146,7 +2146,7 @@ static bool dma64_alloc(dma_info_t *di, uint direction)
2146 2146
2147static bool dma64_txreset(dma_info_t *di) 2147static bool dma64_txreset(dma_info_t *di)
2148{ 2148{
2149 uint32 status; 2149 u32 status;
2150 2150
2151 if (di->ntxd == 0) 2151 if (di->ntxd == 0)
2152 return TRUE; 2152 return TRUE;
@@ -2182,7 +2182,7 @@ static bool dma64_rxidle(dma_info_t *di)
2182 2182
2183static bool dma64_rxreset(dma_info_t *di) 2183static bool dma64_rxreset(dma_info_t *di)
2184{ 2184{
2185 uint32 status; 2185 u32 status;
2186 2186
2187 if (di->nrxd == 0) 2187 if (di->nrxd == 0)
2188 return TRUE; 2188 return TRUE;
@@ -2197,7 +2197,7 @@ static bool dma64_rxreset(dma_info_t *di)
2197 2197
2198static bool dma64_rxenabled(dma_info_t *di) 2198static bool dma64_rxenabled(dma_info_t *di)
2199{ 2199{
2200 uint32 rc; 2200 u32 rc;
2201 2201
2202 rc = R_REG(di->osh, &di->d64rxregs->control); 2202 rc = R_REG(di->osh, &di->d64rxregs->control);
2203 return (rc != 0xffffffff) && (rc & D64_RC_RE); 2203 return (rc != 0xffffffff) && (rc & D64_RC_RE);
@@ -2227,7 +2227,7 @@ static void *dma64_getpos(dma_info_t *di, bool direction)
2227{ 2227{
2228 void *va; 2228 void *va;
2229 bool idle; 2229 bool idle;
2230 uint32 cd_offset; 2230 u32 cd_offset;
2231 2231
2232 if (direction == DMA_TX) { 2232 if (direction == DMA_TX) {
2233 cd_offset = 2233 cd_offset =
@@ -2261,7 +2261,7 @@ static void *dma64_getpos(dma_info_t *di, bool direction)
2261static int dma64_txunframed(dma_info_t *di, void *buf, uint len, bool commit) 2261static int dma64_txunframed(dma_info_t *di, void *buf, uint len, bool commit)
2262{ 2262{
2263 u16 txout; 2263 u16 txout;
2264 uint32 flags = 0; 2264 u32 flags = 0;
2265 dmaaddr_t pa; /* phys addr */ 2265 dmaaddr_t pa; /* phys addr */
2266 2266
2267 txout = di->txout; 2267 txout = di->txout;
@@ -2318,7 +2318,7 @@ static int BCMFASTPATH dma64_txfast(dma_info_t *di, void *p0, bool commit)
2318 unsigned char *data; 2318 unsigned char *data;
2319 uint len; 2319 uint len;
2320 u16 txout; 2320 u16 txout;
2321 uint32 flags = 0; 2321 u32 flags = 0;
2322 dmaaddr_t pa; 2322 dmaaddr_t pa;
2323 2323
2324 DMA_TRACE(("%s: dma_txfast\n", di->name)); 2324 DMA_TRACE(("%s: dma_txfast\n", di->name));
@@ -2577,7 +2577,7 @@ static void *BCMFASTPATH dma64_getnextrxp(dma_info_t *di, bool forceall)
2577 2577
2578static bool _dma64_addrext(osl_t *osh, dma64regs_t * dma64regs) 2578static bool _dma64_addrext(osl_t *osh, dma64regs_t * dma64regs)
2579{ 2579{
2580 uint32 w; 2580 u32 w;
2581 OR_REG(osh, &dma64regs->control, D64_XC_AE); 2581 OR_REG(osh, &dma64regs->control, D64_XC_AE);
2582 w = R_REG(osh, &dma64regs->control); 2582 w = R_REG(osh, &dma64regs->control);
2583 AND_REG(osh, &dma64regs->control, ~D64_XC_AE); 2583 AND_REG(osh, &dma64regs->control, ~D64_XC_AE);
@@ -2593,7 +2593,7 @@ static void dma64_txrotate(dma_info_t *di)
2593 uint nactive; 2593 uint nactive;
2594 uint rot; 2594 uint rot;
2595 u16 old, new; 2595 u16 old, new;
2596 uint32 w; 2596 u32 w;
2597 u16 first, last; 2597 u16 first, last;
2598 2598
2599 ASSERT(dma64_txsuspendedidle(di)); 2599 ASSERT(dma64_txsuspendedidle(di));
diff --git a/drivers/staging/brcm80211/util/hndpmu.c b/drivers/staging/brcm80211/util/hndpmu.c
index 4ba758a9a08..1e954c7bd19 100644
--- a/drivers/staging/brcm80211/util/hndpmu.c
+++ b/drivers/staging/brcm80211/util/hndpmu.c
@@ -43,20 +43,20 @@
43 43
44/* PLL controls/clocks */ 44/* PLL controls/clocks */
45static void si_pmu1_pllinit0(si_t *sih, osl_t *osh, chipcregs_t *cc, 45static void si_pmu1_pllinit0(si_t *sih, osl_t *osh, chipcregs_t *cc,
46 uint32 xtal); 46 u32 xtal);
47static uint32 si_pmu1_cpuclk0(si_t *sih, osl_t *osh, chipcregs_t *cc); 47static u32 si_pmu1_cpuclk0(si_t *sih, osl_t *osh, chipcregs_t *cc);
48static uint32 si_pmu1_alpclk0(si_t *sih, osl_t *osh, chipcregs_t *cc); 48static u32 si_pmu1_alpclk0(si_t *sih, osl_t *osh, chipcregs_t *cc);
49 49
50/* PMU resources */ 50/* PMU resources */
51static bool si_pmu_res_depfltr_bb(si_t *sih); 51static bool si_pmu_res_depfltr_bb(si_t *sih);
52static bool si_pmu_res_depfltr_ncb(si_t *sih); 52static bool si_pmu_res_depfltr_ncb(si_t *sih);
53static bool si_pmu_res_depfltr_paldo(si_t *sih); 53static bool si_pmu_res_depfltr_paldo(si_t *sih);
54static bool si_pmu_res_depfltr_npaldo(si_t *sih); 54static bool si_pmu_res_depfltr_npaldo(si_t *sih);
55static uint32 si_pmu_res_deps(si_t *sih, osl_t *osh, chipcregs_t *cc, 55static u32 si_pmu_res_deps(si_t *sih, osl_t *osh, chipcregs_t *cc,
56 uint32 rsrcs, bool all); 56 u32 rsrcs, bool all);
57static uint si_pmu_res_uptime(si_t *sih, osl_t *osh, chipcregs_t *cc, 57static uint si_pmu_res_uptime(si_t *sih, osl_t *osh, chipcregs_t *cc,
58 u8 rsrc); 58 u8 rsrc);
59static void si_pmu_res_masks(si_t *sih, uint32 * pmin, uint32 * pmax); 59static void si_pmu_res_masks(si_t *sih, u32 * pmin, u32 * pmax);
60static void si_pmu_spuravoid_pllupdate(si_t *sih, chipcregs_t *cc, 60static void si_pmu_spuravoid_pllupdate(si_t *sih, chipcregs_t *cc,
61 osl_t *osh, u8 spuravoid); 61 osl_t *osh, u8 spuravoid);
62 62
@@ -69,7 +69,7 @@ static void si_pmu_set_4330_plldivs(si_t *sih);
69#define FVCO_960 960000 /* 960MHz */ 69#define FVCO_960 960000 /* 960MHz */
70 70
71/* Read/write a chipcontrol reg */ 71/* Read/write a chipcontrol reg */
72uint32 si_pmu_chipcontrol(si_t *sih, uint reg, uint32 mask, uint32 val) 72u32 si_pmu_chipcontrol(si_t *sih, uint reg, u32 mask, u32 val)
73{ 73{
74 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, chipcontrol_addr), ~0, 74 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, chipcontrol_addr), ~0,
75 reg); 75 reg);
@@ -78,7 +78,7 @@ uint32 si_pmu_chipcontrol(si_t *sih, uint reg, uint32 mask, uint32 val)
78} 78}
79 79
80/* Read/write a regcontrol reg */ 80/* Read/write a regcontrol reg */
81uint32 si_pmu_regcontrol(si_t *sih, uint reg, uint32 mask, uint32 val) 81u32 si_pmu_regcontrol(si_t *sih, uint reg, u32 mask, u32 val)
82{ 82{
83 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, regcontrol_addr), ~0, 83 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, regcontrol_addr), ~0,
84 reg); 84 reg);
@@ -87,7 +87,7 @@ uint32 si_pmu_regcontrol(si_t *sih, uint reg, uint32 mask, uint32 val)
87} 87}
88 88
89/* Read/write a pllcontrol reg */ 89/* Read/write a pllcontrol reg */
90uint32 si_pmu_pllcontrol(si_t *sih, uint reg, uint32 mask, uint32 val) 90u32 si_pmu_pllcontrol(si_t *sih, uint reg, u32 mask, u32 val)
91{ 91{
92 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, pllcontrol_addr), ~0, 92 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, pllcontrol_addr), ~0,
93 reg); 93 reg);
@@ -117,10 +117,10 @@ BCMATTACHFN(si_pmu_set_switcher_voltage) (si_t *sih, osl_t *osh,
117 ASSERT(cc != NULL); 117 ASSERT(cc != NULL);
118 118
119 W_REG(osh, &cc->regcontrol_addr, 0x01); 119 W_REG(osh, &cc->regcontrol_addr, 0x01);
120 W_REG(osh, &cc->regcontrol_data, (uint32) (bb_voltage & 0x1f) << 22); 120 W_REG(osh, &cc->regcontrol_data, (u32) (bb_voltage & 0x1f) << 22);
121 121
122 W_REG(osh, &cc->regcontrol_addr, 0x00); 122 W_REG(osh, &cc->regcontrol_addr, 0x00);
123 W_REG(osh, &cc->regcontrol_data, (uint32) (rf_voltage & 0x1f) << 14); 123 W_REG(osh, &cc->regcontrol_data, (u32) (rf_voltage & 0x1f) << 14);
124 124
125 /* Return to original core */ 125 /* Return to original core */
126 si_setcoreidx(sih, origidx); 126 si_setcoreidx(sih, origidx);
@@ -218,7 +218,7 @@ u16 BCMINITFN(si_pmu_fast_pwrup_delay) (si_t *sih, osl_t *osh)
218 if (ISSIM_ENAB(sih)) 218 if (ISSIM_ENAB(sih))
219 delay = 70; 219 delay = 70;
220 else { 220 else {
221 uint32 ilp = si_ilp_clock(sih); 221 u32 ilp = si_ilp_clock(sih);
222 delay = 222 delay =
223 (si_pmu_res_uptime(sih, osh, cc, RES4329_HT_AVAIL) + 223 (si_pmu_res_uptime(sih, osh, cc, RES4329_HT_AVAIL) +
224 D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp - 224 D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp -
@@ -233,7 +233,7 @@ u16 BCMINITFN(si_pmu_fast_pwrup_delay) (si_t *sih, osl_t *osh)
233 if (ISSIM_ENAB(sih)) 233 if (ISSIM_ENAB(sih))
234 delay = 70; 234 delay = 70;
235 else { 235 else {
236 uint32 ilp = si_ilp_clock(sih); 236 u32 ilp = si_ilp_clock(sih);
237 delay = 237 delay =
238 (si_pmu_res_uptime(sih, osh, cc, RES4336_HT_AVAIL) + 238 (si_pmu_res_uptime(sih, osh, cc, RES4336_HT_AVAIL) +
239 D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp - 239 D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp -
@@ -245,7 +245,7 @@ u16 BCMINITFN(si_pmu_fast_pwrup_delay) (si_t *sih, osl_t *osh)
245 if (ISSIM_ENAB(sih)) 245 if (ISSIM_ENAB(sih))
246 delay = 70; 246 delay = 70;
247 else { 247 else {
248 uint32 ilp = si_ilp_clock(sih); 248 u32 ilp = si_ilp_clock(sih);
249 delay = 249 delay =
250 (si_pmu_res_uptime(sih, osh, cc, RES4330_HT_AVAIL) + 250 (si_pmu_res_uptime(sih, osh, cc, RES4330_HT_AVAIL) +
251 D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp - 251 D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp -
@@ -262,11 +262,11 @@ u16 BCMINITFN(si_pmu_fast_pwrup_delay) (si_t *sih, osl_t *osh)
262 return (u16) delay; 262 return (u16) delay;
263} 263}
264 264
265uint32 BCMATTACHFN(si_pmu_force_ilp) (si_t *sih, osl_t *osh, bool force) 265u32 BCMATTACHFN(si_pmu_force_ilp) (si_t *sih, osl_t *osh, bool force)
266{ 266{
267 chipcregs_t *cc; 267 chipcregs_t *cc;
268 uint origidx; 268 uint origidx;
269 uint32 oldpmucontrol; 269 u32 oldpmucontrol;
270 270
271 ASSERT(sih->cccaps & CC_CAP_PMU); 271 ASSERT(sih->cccaps & CC_CAP_PMU);
272 272
@@ -297,9 +297,9 @@ typedef struct {
297 297
298/* Change resource dependancies masks */ 298/* Change resource dependancies masks */
299typedef struct { 299typedef struct {
300 uint32 res_mask; /* resources (chip specific) */ 300 u32 res_mask; /* resources (chip specific) */
301 s8 action; /* action */ 301 s8 action; /* action */
302 uint32 depend_mask; /* changes to the dependancies mask */ 302 u32 depend_mask; /* changes to the dependancies mask */
303 bool(*filter) (si_t *sih); /* action is taken when filter is NULL or return TRUE */ 303 bool(*filter) (si_t *sih); /* action is taken when filter is NULL or return TRUE */
304} pmu_res_depend_t; 304} pmu_res_depend_t;
305 305
@@ -592,9 +592,9 @@ static bool BCMATTACHFN(si_pmu_res_depfltr_npaldo) (si_t *sih)
592 sih->boardtype == BCM94325BGABU_BOARD) 592 sih->boardtype == BCM94325BGABU_BOARD)
593 593
594/* Determine min/max rsrc masks. Value 0 leaves hardware at default. */ 594/* Determine min/max rsrc masks. Value 0 leaves hardware at default. */
595static void si_pmu_res_masks(si_t *sih, uint32 * pmin, uint32 * pmax) 595static void si_pmu_res_masks(si_t *sih, u32 * pmin, u32 * pmax)
596{ 596{
597 uint32 min_mask = 0, max_mask = 0; 597 u32 min_mask = 0, max_mask = 0;
598 uint rsrcs; 598 uint rsrcs;
599 char *val; 599 char *val;
600 600
@@ -666,13 +666,13 @@ static void si_pmu_res_masks(si_t *sih, uint32 * pmin, uint32 * pmax)
666 val = getvar(NULL, "rmin"); 666 val = getvar(NULL, "rmin");
667 if (val != NULL) { 667 if (val != NULL) {
668 PMU_MSG(("Applying rmin=%s to min_mask\n", val)); 668 PMU_MSG(("Applying rmin=%s to min_mask\n", val));
669 min_mask = (uint32) simple_strtoul(val, NULL, 0); 669 min_mask = (u32) simple_strtoul(val, NULL, 0);
670 } 670 }
671 /* Apply nvram override to max mask */ 671 /* Apply nvram override to max mask */
672 val = getvar(NULL, "rmax"); 672 val = getvar(NULL, "rmax");
673 if (val != NULL) { 673 if (val != NULL) {
674 PMU_MSG(("Applying rmax=%s to max_mask\n", val)); 674 PMU_MSG(("Applying rmax=%s to max_mask\n", val));
675 max_mask = (uint32) simple_strtoul(val, NULL, 0); 675 max_mask = (u32) simple_strtoul(val, NULL, 0);
676 } 676 }
677 677
678 *pmin = min_mask; 678 *pmin = min_mask;
@@ -688,7 +688,7 @@ void BCMATTACHFN(si_pmu_res_init) (si_t *sih, osl_t *osh)
688 uint pmu_res_updown_table_sz = 0; 688 uint pmu_res_updown_table_sz = 0;
689 const pmu_res_depend_t *pmu_res_depend_table = NULL; 689 const pmu_res_depend_t *pmu_res_depend_table = NULL;
690 uint pmu_res_depend_table_sz = 0; 690 uint pmu_res_depend_table_sz = 0;
691 uint32 min_mask = 0, max_mask = 0; 691 u32 min_mask = 0, max_mask = 0;
692 char name[8], *val; 692 char name[8], *val;
693 uint i, rsrcs; 693 uint i, rsrcs;
694 694
@@ -788,9 +788,9 @@ void BCMATTACHFN(si_pmu_res_init) (si_t *sih, osl_t *osh)
788 continue; 788 continue;
789 PMU_MSG(("Applying %s=%s to rsrc %d res_updn_timer\n", name, 789 PMU_MSG(("Applying %s=%s to rsrc %d res_updn_timer\n", name,
790 val, i)); 790 val, i));
791 W_REG(osh, &cc->res_table_sel, (uint32) i); 791 W_REG(osh, &cc->res_table_sel, (u32) i);
792 W_REG(osh, &cc->res_updn_timer, 792 W_REG(osh, &cc->res_updn_timer,
793 (uint32) simple_strtoul(val, NULL, 0)); 793 (u32) simple_strtoul(val, NULL, 0));
794 } 794 }
795 795
796 /* Program resource dependencies table */ 796 /* Program resource dependencies table */
@@ -839,9 +839,9 @@ void BCMATTACHFN(si_pmu_res_init) (si_t *sih, osl_t *osh)
839 continue; 839 continue;
840 PMU_MSG(("Applying %s=%s to rsrc %d res_dep_mask\n", name, val, 840 PMU_MSG(("Applying %s=%s to rsrc %d res_dep_mask\n", name, val,
841 i)); 841 i));
842 W_REG(osh, &cc->res_table_sel, (uint32) i); 842 W_REG(osh, &cc->res_table_sel, (u32) i);
843 W_REG(osh, &cc->res_dep_mask, 843 W_REG(osh, &cc->res_dep_mask,
844 (uint32) simple_strtoul(val, NULL, 0)); 844 (u32) simple_strtoul(val, NULL, 0));
845 } 845 }
846 846
847 /* Determine min/max rsrc masks */ 847 /* Determine min/max rsrc masks */
@@ -875,7 +875,7 @@ typedef struct {
875 u16 freq; 875 u16 freq;
876 u8 xf; 876 u8 xf;
877 u8 wbint; 877 u8 wbint;
878 uint32 wbfrac; 878 u32 wbfrac;
879} pmu0_xtaltab0_t; 879} pmu0_xtaltab0_t;
880 880
881/* the following table is based on 880Mhz fvco */ 881/* the following table is based on 880Mhz fvco */
@@ -907,7 +907,7 @@ typedef struct {
907 u8 p1div; 907 u8 p1div;
908 u8 p2div; 908 u8 p2div;
909 u8 ndiv_int; 909 u8 ndiv_int;
910 uint32 ndiv_frac; 910 u32 ndiv_frac;
911} pmu1_xtaltab0_t; 911} pmu1_xtaltab0_t;
912 912
913static const pmu1_xtaltab0_t BCMINITDATA(pmu1_xtaltab0_880_4329)[] = { 913static const pmu1_xtaltab0_t BCMINITDATA(pmu1_xtaltab0_880_4329)[] = {
@@ -1152,7 +1152,7 @@ static const pmu1_xtaltab0_t *BCMINITFN(si_pmu1_xtaldef0) (si_t *sih)
1152} 1152}
1153 1153
1154/* select default pll fvco for each chip */ 1154/* select default pll fvco for each chip */
1155static uint32 BCMINITFN(si_pmu1_pllfvco0) (si_t *sih) 1155static u32 BCMINITFN(si_pmu1_pllfvco0) (si_t *sih)
1156{ 1156{
1157#ifdef BCMDBG 1157#ifdef BCMDBG
1158 char chn[8]; 1158 char chn[8];
@@ -1180,11 +1180,11 @@ static uint32 BCMINITFN(si_pmu1_pllfvco0) (si_t *sih)
1180} 1180}
1181 1181
1182/* query alp/xtal clock frequency */ 1182/* query alp/xtal clock frequency */
1183static uint32 1183static u32
1184BCMINITFN(si_pmu1_alpclk0) (si_t *sih, osl_t *osh, chipcregs_t *cc) 1184BCMINITFN(si_pmu1_alpclk0) (si_t *sih, osl_t *osh, chipcregs_t *cc)
1185{ 1185{
1186 const pmu1_xtaltab0_t *xt; 1186 const pmu1_xtaltab0_t *xt;
1187 uint32 xf; 1187 u32 xf;
1188 1188
1189 /* Find the frequency in the table */ 1189 /* Find the frequency in the table */
1190 xf = (R_REG(osh, &cc->pmucontrol) & PCTL_XTALFREQ_MASK) >> 1190 xf = (R_REG(osh, &cc->pmucontrol) & PCTL_XTALFREQ_MASK) >>
@@ -1208,10 +1208,10 @@ BCMINITFN(si_pmu1_alpclk0) (si_t *sih, osl_t *osh, chipcregs_t *cc)
1208 */ 1208 */
1209static void 1209static void
1210BCMATTACHFN(si_pmu1_pllinit0) (si_t *sih, osl_t *osh, chipcregs_t *cc, 1210BCMATTACHFN(si_pmu1_pllinit0) (si_t *sih, osl_t *osh, chipcregs_t *cc,
1211 uint32 xtal) { 1211 u32 xtal) {
1212 const pmu1_xtaltab0_t *xt; 1212 const pmu1_xtaltab0_t *xt;
1213 uint32 tmp; 1213 u32 tmp;
1214 uint32 buf_strength = 0; 1214 u32 buf_strength = 0;
1215 u8 ndiv_mode = 1; 1215 u8 ndiv_mode = 1;
1216 1216
1217 /* Use h/w default PLL config */ 1217 /* Use h/w default PLL config */
@@ -1451,15 +1451,15 @@ BCMATTACHFN(si_pmu1_pllinit0) (si_t *sih, osl_t *osh, chipcregs_t *cc,
1451} 1451}
1452 1452
1453/* query the CPU clock frequency */ 1453/* query the CPU clock frequency */
1454static uint32 1454static u32
1455BCMINITFN(si_pmu1_cpuclk0) (si_t *sih, osl_t *osh, chipcregs_t *cc) 1455BCMINITFN(si_pmu1_cpuclk0) (si_t *sih, osl_t *osh, chipcregs_t *cc)
1456{ 1456{
1457 uint32 tmp, m1div; 1457 u32 tmp, m1div;
1458#ifdef BCMDBG 1458#ifdef BCMDBG
1459 uint32 ndiv_int, ndiv_frac, p2div, p1div, fvco; 1459 u32 ndiv_int, ndiv_frac, p2div, p1div, fvco;
1460 uint32 fref; 1460 u32 fref;
1461#endif 1461#endif
1462 uint32 FVCO = si_pmu1_pllfvco0(sih); 1462 u32 FVCO = si_pmu1_pllfvco0(sih);
1463 1463
1464 /* Read m1div from pllcontrol[1] */ 1464 /* Read m1div from pllcontrol[1] */
1465 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1); 1465 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
@@ -1559,11 +1559,11 @@ void BCMATTACHFN(si_pmu_pll_init) (si_t *sih, osl_t *osh, uint xtalfreq)
1559} 1559}
1560 1560
1561/* query alp/xtal clock frequency */ 1561/* query alp/xtal clock frequency */
1562uint32 BCMINITFN(si_pmu_alp_clock) (si_t *sih, osl_t *osh) 1562u32 BCMINITFN(si_pmu_alp_clock) (si_t *sih, osl_t *osh)
1563{ 1563{
1564 chipcregs_t *cc; 1564 chipcregs_t *cc;
1565 uint origidx; 1565 uint origidx;
1566 uint32 clock = ALP_CLOCK; 1566 u32 clock = ALP_CLOCK;
1567#ifdef BCMDBG 1567#ifdef BCMDBG
1568 char chn[8]; 1568 char chn[8];
1569#endif 1569#endif
@@ -1619,10 +1619,10 @@ uint32 BCMINITFN(si_pmu_alp_clock) (si_t *sih, osl_t *osh)
1619/* Find the output of the "m" pll divider given pll controls that start with 1619/* Find the output of the "m" pll divider given pll controls that start with
1620 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc. 1620 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
1621 */ 1621 */
1622static uint32 1622static u32
1623BCMINITFN(si_pmu5_clock) (si_t *sih, osl_t *osh, chipcregs_t *cc, uint pll0, 1623BCMINITFN(si_pmu5_clock) (si_t *sih, osl_t *osh, chipcregs_t *cc, uint pll0,
1624 uint m) { 1624 uint m) {
1625 uint32 tmp, div, ndiv, p1, p2, fc; 1625 u32 tmp, div, ndiv, p1, p2, fc;
1626 1626
1627 if ((pll0 & 3) || (pll0 > PMU4716_MAINPLL_PLL0)) { 1627 if ((pll0 & 3) || (pll0 > PMU4716_MAINPLL_PLL0)) {
1628 PMU_ERROR(("%s: Bad pll0: %d\n", __func__, pll0)); 1628 PMU_ERROR(("%s: Bad pll0: %d\n", __func__, pll0));
@@ -1673,11 +1673,11 @@ BCMINITFN(si_pmu5_clock) (si_t *sih, osl_t *osh, chipcregs_t *cc, uint pll0,
1673/* For designs that feed the same clock to both backplane 1673/* For designs that feed the same clock to both backplane
1674 * and CPU just return the CPU clock speed. 1674 * and CPU just return the CPU clock speed.
1675 */ 1675 */
1676uint32 BCMINITFN(si_pmu_si_clock) (si_t *sih, osl_t *osh) 1676u32 BCMINITFN(si_pmu_si_clock) (si_t *sih, osl_t *osh)
1677{ 1677{
1678 chipcregs_t *cc; 1678 chipcregs_t *cc;
1679 uint origidx; 1679 uint origidx;
1680 uint32 clock = HT_CLOCK; 1680 u32 clock = HT_CLOCK;
1681#ifdef BCMDBG 1681#ifdef BCMDBG
1682 char chn[8]; 1682 char chn[8];
1683#endif 1683#endif
@@ -1752,11 +1752,11 @@ uint32 BCMINITFN(si_pmu_si_clock) (si_t *sih, osl_t *osh)
1752} 1752}
1753 1753
1754/* query CPU clock frequency */ 1754/* query CPU clock frequency */
1755uint32 BCMINITFN(si_pmu_cpu_clock) (si_t *sih, osl_t *osh) 1755u32 BCMINITFN(si_pmu_cpu_clock) (si_t *sih, osl_t *osh)
1756{ 1756{
1757 chipcregs_t *cc; 1757 chipcregs_t *cc;
1758 uint origidx; 1758 uint origidx;
1759 uint32 clock; 1759 u32 clock;
1760 1760
1761 ASSERT(sih->cccaps & CC_CAP_PMU); 1761 ASSERT(sih->cccaps & CC_CAP_PMU);
1762 1762
@@ -1796,11 +1796,11 @@ uint32 BCMINITFN(si_pmu_cpu_clock) (si_t *sih, osl_t *osh)
1796} 1796}
1797 1797
1798/* query memory clock frequency */ 1798/* query memory clock frequency */
1799uint32 BCMINITFN(si_pmu_mem_clock) (si_t *sih, osl_t *osh) 1799u32 BCMINITFN(si_pmu_mem_clock) (si_t *sih, osl_t *osh)
1800{ 1800{
1801 chipcregs_t *cc; 1801 chipcregs_t *cc;
1802 uint origidx; 1802 uint origidx;
1803 uint32 clock; 1803 u32 clock;
1804 1804
1805 ASSERT(sih->cccaps & CC_CAP_PMU); 1805 ASSERT(sih->cccaps & CC_CAP_PMU);
1806 1806
@@ -1843,16 +1843,16 @@ uint32 BCMINITFN(si_pmu_mem_clock) (si_t *sih, osl_t *osh)
1843/* Measure ILP clock frequency */ 1843/* Measure ILP clock frequency */
1844#define ILP_CALC_DUR 10 /* ms, make sure 1000 can be divided by it. */ 1844#define ILP_CALC_DUR 10 /* ms, make sure 1000 can be divided by it. */
1845 1845
1846static uint32 ilpcycles_per_sec; 1846static u32 ilpcycles_per_sec;
1847 1847
1848uint32 BCMINITFN(si_pmu_ilp_clock) (si_t *sih, osl_t *osh) 1848u32 BCMINITFN(si_pmu_ilp_clock) (si_t *sih, osl_t *osh)
1849{ 1849{
1850 if (ISSIM_ENAB(sih)) 1850 if (ISSIM_ENAB(sih))
1851 return ILP_CLOCK; 1851 return ILP_CLOCK;
1852 1852
1853 if (ilpcycles_per_sec == 0) { 1853 if (ilpcycles_per_sec == 0) {
1854 uint32 start, end, delta; 1854 u32 start, end, delta;
1855 uint32 origidx = si_coreidx(sih); 1855 u32 origidx = si_coreidx(sih);
1856 chipcregs_t *cc = si_setcoreidx(sih, SI_CC_IDX); 1856 chipcregs_t *cc = si_setcoreidx(sih, SI_CC_IDX);
1857 ASSERT(cc != NULL); 1857 ASSERT(cc != NULL);
1858 start = R_REG(osh, &cc->pmutimer); 1858 start = R_REG(osh, &cc->pmutimer);
@@ -1910,12 +1910,12 @@ static const sdiod_drive_str_t BCMINITDATA(sdiod_drive_strength_tab3)[] = {
1910 1910
1911void 1911void
1912BCMINITFN(si_sdiod_drive_strength_init) (si_t *sih, osl_t *osh, 1912BCMINITFN(si_sdiod_drive_strength_init) (si_t *sih, osl_t *osh,
1913 uint32 drivestrength) { 1913 u32 drivestrength) {
1914 chipcregs_t *cc; 1914 chipcregs_t *cc;
1915 uint origidx, intr_val = 0; 1915 uint origidx, intr_val = 0;
1916 sdiod_drive_str_t *str_tab = NULL; 1916 sdiod_drive_str_t *str_tab = NULL;
1917 uint32 str_mask = 0; 1917 u32 str_mask = 0;
1918 uint32 str_shift = 0; 1918 u32 str_shift = 0;
1919#ifdef BCMDBG 1919#ifdef BCMDBG
1920 char chn[8]; 1920 char chn[8];
1921#endif 1921#endif
@@ -1953,8 +1953,8 @@ BCMINITFN(si_sdiod_drive_strength_init) (si_t *sih, osl_t *osh,
1953 } 1953 }
1954 1954
1955 if (str_tab != NULL) { 1955 if (str_tab != NULL) {
1956 uint32 drivestrength_sel = 0; 1956 u32 drivestrength_sel = 0;
1957 uint32 cc_data_temp; 1957 u32 cc_data_temp;
1958 int i; 1958 int i;
1959 1959
1960 for (i = 0; str_tab[i].strength != 0; i++) { 1960 for (i = 0; str_tab[i].strength != 0; i++) {
@@ -2014,9 +2014,9 @@ void BCMATTACHFN(si_pmu_init) (si_t *sih, osl_t *osh)
2014static uint 2014static uint
2015BCMINITFN(si_pmu_res_uptime) (si_t *sih, osl_t *osh, chipcregs_t *cc, 2015BCMINITFN(si_pmu_res_uptime) (si_t *sih, osl_t *osh, chipcregs_t *cc,
2016 u8 rsrc) { 2016 u8 rsrc) {
2017 uint32 deps; 2017 u32 deps;
2018 uint up, i, dup, dmax; 2018 uint up, i, dup, dmax;
2019 uint32 min_mask = 0, max_mask = 0; 2019 u32 min_mask = 0, max_mask = 0;
2020 2020
2021 /* uptime of resource 'rsrc' */ 2021 /* uptime of resource 'rsrc' */
2022 W_REG(osh, &cc->res_table_sel, rsrc); 2022 W_REG(osh, &cc->res_table_sel, rsrc);
@@ -2048,12 +2048,12 @@ BCMINITFN(si_pmu_res_uptime) (si_t *sih, osl_t *osh, chipcregs_t *cc,
2048} 2048}
2049 2049
2050/* Return dependancies (direct or all/indirect) for the given resources */ 2050/* Return dependancies (direct or all/indirect) for the given resources */
2051static uint32 2051static u32
2052si_pmu_res_deps(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 rsrcs, 2052si_pmu_res_deps(si_t *sih, osl_t *osh, chipcregs_t *cc, u32 rsrcs,
2053 bool all) 2053 bool all)
2054{ 2054{
2055 uint32 deps = 0; 2055 u32 deps = 0;
2056 uint32 i; 2056 u32 i;
2057 2057
2058 for (i = 0; i <= PMURES_MAX_RESNUM; i++) { 2058 for (i = 0; i <= PMURES_MAX_RESNUM; i++) {
2059 if (!(rsrcs & PMURES_BIT(i))) 2059 if (!(rsrcs & PMURES_BIT(i)))
@@ -2073,7 +2073,7 @@ void si_pmu_otp_power(si_t *sih, osl_t *osh, bool on)
2073{ 2073{
2074 chipcregs_t *cc; 2074 chipcregs_t *cc;
2075 uint origidx; 2075 uint origidx;
2076 uint32 rsrcs = 0; /* rsrcs to turn on/off OTP power */ 2076 u32 rsrcs = 0; /* rsrcs to turn on/off OTP power */
2077 2077
2078 ASSERT(sih->cccaps & CC_CAP_PMU); 2078 ASSERT(sih->cccaps & CC_CAP_PMU);
2079 2079
@@ -2106,11 +2106,11 @@ void si_pmu_otp_power(si_t *sih, osl_t *osh, bool on)
2106 } 2106 }
2107 2107
2108 if (rsrcs != 0) { 2108 if (rsrcs != 0) {
2109 uint32 otps; 2109 u32 otps;
2110 2110
2111 /* Figure out the dependancies (exclude min_res_mask) */ 2111 /* Figure out the dependancies (exclude min_res_mask) */
2112 uint32 deps = si_pmu_res_deps(sih, osh, cc, rsrcs, TRUE); 2112 u32 deps = si_pmu_res_deps(sih, osh, cc, rsrcs, TRUE);
2113 uint32 min_mask = 0, max_mask = 0; 2113 u32 min_mask = 0, max_mask = 0;
2114 si_pmu_res_masks(sih, &min_mask, &max_mask); 2114 si_pmu_res_masks(sih, &min_mask, &max_mask);
2115 deps &= ~min_mask; 2115 deps &= ~min_mask;
2116 /* Turn on/off the power */ 2116 /* Turn on/off the power */
@@ -2154,7 +2154,7 @@ void si_pmu_rcal(si_t *sih, osl_t *osh)
2154 switch (CHIPID(sih->chip)) { 2154 switch (CHIPID(sih->chip)) {
2155 case BCM4329_CHIP_ID:{ 2155 case BCM4329_CHIP_ID:{
2156 u8 rcal_code; 2156 u8 rcal_code;
2157 uint32 val; 2157 u32 val;
2158 2158
2159 /* Kick RCal */ 2159 /* Kick RCal */
2160 W_REG(osh, &cc->chipcontrol_addr, 1); 2160 W_REG(osh, &cc->chipcontrol_addr, 1);
@@ -2182,12 +2182,12 @@ void si_pmu_rcal(si_t *sih, osl_t *osh)
2182 val = 2182 val =
2183 R_REG(osh, 2183 R_REG(osh,
2184 &cc-> 2184 &cc->
2185 regcontrol_data) & ~((uint32) 0x07 << 29); 2185 regcontrol_data) & ~((u32) 0x07 << 29);
2186 val |= (uint32) (rcal_code & 0x07) << 29; 2186 val |= (u32) (rcal_code & 0x07) << 29;
2187 W_REG(osh, &cc->regcontrol_data, val); 2187 W_REG(osh, &cc->regcontrol_data, val);
2188 W_REG(osh, &cc->regcontrol_addr, 1); 2188 W_REG(osh, &cc->regcontrol_addr, 1);
2189 val = R_REG(osh, &cc->regcontrol_data) & ~(uint32) 0x01; 2189 val = R_REG(osh, &cc->regcontrol_data) & ~(u32) 0x01;
2190 val |= (uint32) ((rcal_code >> 3) & 0x01); 2190 val |= (u32) ((rcal_code >> 3) & 0x01);
2191 W_REG(osh, &cc->regcontrol_data, val); 2191 W_REG(osh, &cc->regcontrol_data, val);
2192 2192
2193 /* Write RCal code into pmu_chip_ctrl[33:30] */ 2193 /* Write RCal code into pmu_chip_ctrl[33:30] */
@@ -2195,13 +2195,13 @@ void si_pmu_rcal(si_t *sih, osl_t *osh)
2195 val = 2195 val =
2196 R_REG(osh, 2196 R_REG(osh,
2197 &cc-> 2197 &cc->
2198 chipcontrol_data) & ~((uint32) 0x03 << 30); 2198 chipcontrol_data) & ~((u32) 0x03 << 30);
2199 val |= (uint32) (rcal_code & 0x03) << 30; 2199 val |= (u32) (rcal_code & 0x03) << 30;
2200 W_REG(osh, &cc->chipcontrol_data, val); 2200 W_REG(osh, &cc->chipcontrol_data, val);
2201 W_REG(osh, &cc->chipcontrol_addr, 1); 2201 W_REG(osh, &cc->chipcontrol_addr, 1);
2202 val = 2202 val =
2203 R_REG(osh, &cc->chipcontrol_data) & ~(uint32) 0x03; 2203 R_REG(osh, &cc->chipcontrol_data) & ~(u32) 0x03;
2204 val |= (uint32) ((rcal_code >> 2) & 0x03); 2204 val |= (u32) ((rcal_code >> 2) & 0x03);
2205 W_REG(osh, &cc->chipcontrol_data, val); 2205 W_REG(osh, &cc->chipcontrol_data, val);
2206 2206
2207 /* Set override in pmu_chip_ctrl[29] */ 2207 /* Set override in pmu_chip_ctrl[29] */
@@ -2226,7 +2226,7 @@ void si_pmu_spuravoid(si_t *sih, osl_t *osh, u8 spuravoid)
2226{ 2226{
2227 chipcregs_t *cc; 2227 chipcregs_t *cc;
2228 uint origidx, intr_val; 2228 uint origidx, intr_val;
2229 uint32 tmp = 0; 2229 u32 tmp = 0;
2230 2230
2231 /* Remember original core before switch to chipc */ 2231 /* Remember original core before switch to chipc */
2232 cc = (chipcregs_t *) si_switch_core(sih, CC_CORE_ID, &origidx, 2232 cc = (chipcregs_t *) si_switch_core(sih, CC_CORE_ID, &origidx,
@@ -2262,7 +2262,7 @@ static void
2262si_pmu_spuravoid_pllupdate(si_t *sih, chipcregs_t *cc, osl_t *osh, 2262si_pmu_spuravoid_pllupdate(si_t *sih, chipcregs_t *cc, osl_t *osh,
2263 u8 spuravoid) 2263 u8 spuravoid)
2264{ 2264{
2265 uint32 tmp = 0; 2265 u32 tmp = 0;
2266 u8 phypll_offset = 0; 2266 u8 phypll_offset = 0;
2267 u8 bcm5357_bcm43236_p1div[] = { 0x1, 0x5, 0x5 }; 2267 u8 bcm5357_bcm43236_p1div[] = { 0x1, 0x5, 0x5 };
2268 u8 bcm5357_bcm43236_ndiv[] = { 0x30, 0xf6, 0xfc }; 2268 u8 bcm5357_bcm43236_ndiv[] = { 0x30, 0xf6, 0xfc };
@@ -2581,18 +2581,18 @@ void si_pmu_radio_enable(si_t *sih, bool enable)
2581 case BCM4319_CHIP_ID: 2581 case BCM4319_CHIP_ID:
2582 if (enable) 2582 if (enable)
2583 si_write_wrapperreg(sih, AI_OOBSELOUTB74, 2583 si_write_wrapperreg(sih, AI_OOBSELOUTB74,
2584 (uint32) 0x868584); 2584 (u32) 0x868584);
2585 else 2585 else
2586 si_write_wrapperreg(sih, AI_OOBSELOUTB74, 2586 si_write_wrapperreg(sih, AI_OOBSELOUTB74,
2587 (uint32) 0x060584); 2587 (u32) 0x060584);
2588 break; 2588 break;
2589 } 2589 }
2590} 2590}
2591 2591
2592/* Wait for a particular clock level to be on the backplane */ 2592/* Wait for a particular clock level to be on the backplane */
2593uint32 2593u32
2594si_pmu_waitforclk_on_backplane(si_t *sih, osl_t *osh, uint32 clk, 2594si_pmu_waitforclk_on_backplane(si_t *sih, osl_t *osh, u32 clk,
2595 uint32 delay) 2595 u32 delay)
2596{ 2596{
2597 chipcregs_t *cc; 2597 chipcregs_t *cc;
2598 uint origidx; 2598 uint origidx;
@@ -2620,11 +2620,11 @@ si_pmu_waitforclk_on_backplane(si_t *sih, osl_t *osh, uint32 clk,
2620 2620
2621#define EXT_ILP_HZ 32768 2621#define EXT_ILP_HZ 32768
2622 2622
2623uint32 BCMATTACHFN(si_pmu_measure_alpclk) (si_t *sih, osl_t *osh) 2623u32 BCMATTACHFN(si_pmu_measure_alpclk) (si_t *sih, osl_t *osh)
2624{ 2624{
2625 chipcregs_t *cc; 2625 chipcregs_t *cc;
2626 uint origidx; 2626 uint origidx;
2627 uint32 alp_khz; 2627 u32 alp_khz;
2628 2628
2629 if (sih->pmurev < 10) 2629 if (sih->pmurev < 10)
2630 return 0; 2630 return 0;
@@ -2637,7 +2637,7 @@ uint32 BCMATTACHFN(si_pmu_measure_alpclk) (si_t *sih, osl_t *osh)
2637 ASSERT(cc != NULL); 2637 ASSERT(cc != NULL);
2638 2638
2639 if (R_REG(osh, &cc->pmustatus) & PST_EXTLPOAVAIL) { 2639 if (R_REG(osh, &cc->pmustatus) & PST_EXTLPOAVAIL) {
2640 uint32 ilp_ctr, alp_hz; 2640 u32 ilp_ctr, alp_hz;
2641 2641
2642 /* Enable the reg to measure the freq, in case disabled before */ 2642 /* Enable the reg to measure the freq, in case disabled before */
2643 W_REG(osh, &cc->pmu_xtalfreq, 2643 W_REG(osh, &cc->pmu_xtalfreq,
@@ -2670,9 +2670,9 @@ uint32 BCMATTACHFN(si_pmu_measure_alpclk) (si_t *sih, osl_t *osh)
2670 2670
2671static void BCMATTACHFN(si_pmu_set_4330_plldivs) (si_t *sih) 2671static void BCMATTACHFN(si_pmu_set_4330_plldivs) (si_t *sih)
2672{ 2672{
2673 uint32 FVCO = si_pmu1_pllfvco0(sih) / 1000; 2673 u32 FVCO = si_pmu1_pllfvco0(sih) / 1000;
2674 uint32 m1div, m2div, m3div, m4div, m5div, m6div; 2674 u32 m1div, m2div, m3div, m4div, m5div, m6div;
2675 uint32 pllc1, pllc2; 2675 u32 pllc1, pllc2;
2676 2676
2677 m2div = m3div = m4div = m6div = FVCO / 80; 2677 m2div = m3div = m4div = m6div = FVCO / 80;
2678 m5div = FVCO / 160; 2678 m5div = FVCO / 160;
diff --git a/drivers/staging/brcm80211/util/linux_osl.c b/drivers/staging/brcm80211/util/linux_osl.c
index b0fb370e246..8ad97d4b001 100644
--- a/drivers/staging/brcm80211/util/linux_osl.c
+++ b/drivers/staging/brcm80211/util/linux_osl.c
@@ -73,7 +73,7 @@ struct osl_info {
73}; 73};
74 74
75/* Global ASSERT type flag */ 75/* Global ASSERT type flag */
76uint32 g_assert_type; 76u32 g_assert_type;
77 77
78#ifdef BRCM_FULLMAC 78#ifdef BRCM_FULLMAC
79static s16 linuxbcmerrormap[] = { 0, /* 0 */ 79static s16 linuxbcmerrormap[] = { 0, /* 0 */
@@ -358,7 +358,7 @@ void osl_pktfree_static(osl_t *osh, void *p, bool send)
358} 358}
359#endif /* defined(BRCM_FULLMAC) && defined(DHD_USE_STATIC_BUF) */ 359#endif /* defined(BRCM_FULLMAC) && defined(DHD_USE_STATIC_BUF) */
360 360
361uint32 osl_pci_read_config(osl_t *osh, uint offset, uint size) 361u32 osl_pci_read_config(osl_t *osh, uint offset, uint size)
362{ 362{
363 uint val = 0; 363 uint val = 0;
364 uint retry = PCI_CFG_RETRY; 364 uint retry = PCI_CFG_RETRY;
@@ -558,7 +558,7 @@ void BCMFASTPATH osl_dma_unmap(osl_t *osh, uint pa, uint size, int direction)
558 558
559 ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC))); 559 ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
560 dir = (direction == DMA_TX) ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE; 560 dir = (direction == DMA_TX) ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE;
561 pci_unmap_single(osh->pdev, (uint32) pa, size, dir); 561 pci_unmap_single(osh->pdev, (u32) pa, size, dir);
562} 562}
563 563
564#if defined(BCMDBG_ASSERT) 564#if defined(BCMDBG_ASSERT)
@@ -636,12 +636,12 @@ u16 osl_readw(osl_t *osh, volatile u16 *r)
636 return (u16) ((rreg) (ctx, (void *)r, sizeof(u16))); 636 return (u16) ((rreg) (ctx, (void *)r, sizeof(u16)));
637} 637}
638 638
639uint32 osl_readl(osl_t *osh, volatile uint32 *r) 639u32 osl_readl(osl_t *osh, volatile u32 *r)
640{ 640{
641 osl_rreg_fn_t rreg = ((osl_pubinfo_t *) osh)->rreg_fn; 641 osl_rreg_fn_t rreg = ((osl_pubinfo_t *) osh)->rreg_fn;
642 void *ctx = ((osl_pubinfo_t *) osh)->reg_ctx; 642 void *ctx = ((osl_pubinfo_t *) osh)->reg_ctx;
643 643
644 return (uint32) ((rreg) (ctx, (void *)r, sizeof(uint32))); 644 return (u32) ((rreg) (ctx, (void *)r, sizeof(u32)));
645} 645}
646 646
647void osl_writeb(osl_t *osh, volatile u8 *r, u8 v) 647void osl_writeb(osl_t *osh, volatile u8 *r, u8 v)
@@ -660,11 +660,11 @@ void osl_writew(osl_t *osh, volatile u16 *r, u16 v)
660 ((wreg) (ctx, (void *)r, v, sizeof(u16))); 660 ((wreg) (ctx, (void *)r, v, sizeof(u16)));
661} 661}
662 662
663void osl_writel(osl_t *osh, volatile uint32 *r, uint32 v) 663void osl_writel(osl_t *osh, volatile u32 *r, u32 v)
664{ 664{
665 osl_wreg_fn_t wreg = ((osl_pubinfo_t *) osh)->wreg_fn; 665 osl_wreg_fn_t wreg = ((osl_pubinfo_t *) osh)->wreg_fn;
666 void *ctx = ((osl_pubinfo_t *) osh)->reg_ctx; 666 void *ctx = ((osl_pubinfo_t *) osh)->reg_ctx;
667 667
668 ((wreg) (ctx, (void *)r, v, sizeof(uint32))); 668 ((wreg) (ctx, (void *)r, v, sizeof(u32)));
669} 669}
670#endif /* BCMSDIO */ 670#endif /* BCMSDIO */
diff --git a/drivers/staging/brcm80211/util/nicpci.c b/drivers/staging/brcm80211/util/nicpci.c
index e6b16ea1386..0a23a4c34f7 100644
--- a/drivers/staging/brcm80211/util/nicpci.c
+++ b/drivers/staging/brcm80211/util/nicpci.c
@@ -89,14 +89,14 @@ static bool pcicore_pmecap(pcicore_info_t *pi);
89 (WORD_VAL(OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4), a) & 0xffff) 89 (WORD_VAL(OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4), a) & 0xffff)
90 90
91#define write_pci_cfg_byte(a, val) do { \ 91#define write_pci_cfg_byte(a, val) do { \
92 uint32 tmpval; \ 92 u32 tmpval; \
93 tmpval = (OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4) & ~0xFF << BYTE_POS(a)) | \ 93 tmpval = (OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4) & ~0xFF << BYTE_POS(a)) | \
94 val << BYTE_POS(a); \ 94 val << BYTE_POS(a); \
95 OSL_PCI_WRITE_CONFIG(osh, DWORD_ALIGN(a), 4, tmpval); \ 95 OSL_PCI_WRITE_CONFIG(osh, DWORD_ALIGN(a), 4, tmpval); \
96 } while (0) 96 } while (0)
97 97
98#define write_pci_cfg_word(a, val) do { \ 98#define write_pci_cfg_word(a, val) do { \
99 uint32 tmpval; \ 99 u32 tmpval; \
100 tmpval = (OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4) & ~0xFFFF << WORD_POS(a)) | \ 100 tmpval = (OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4) & ~0xFFFF << WORD_POS(a)) | \
101 val << WORD_POS(a); \ 101 val << WORD_POS(a); \
102 OSL_PCI_WRITE_CONFIG(osh, DWORD_ALIGN(a), 4, tmpval); \ 102 OSL_PCI_WRITE_CONFIG(osh, DWORD_ALIGN(a), 4, tmpval); \
@@ -154,11 +154,11 @@ void pcicore_deinit(void *pch)
154/* Note that it's caller's responsibility to make sure it's a pci bus */ 154/* Note that it's caller's responsibility to make sure it's a pci bus */
155u8 155u8
156pcicore_find_pci_capability(osl_t *osh, u8 req_cap_id, unsigned char *buf, 156pcicore_find_pci_capability(osl_t *osh, u8 req_cap_id, unsigned char *buf,
157 uint32 *buflen) 157 u32 *buflen)
158{ 158{
159 u8 cap_id; 159 u8 cap_id;
160 u8 cap_ptr = 0; 160 u8 cap_ptr = 0;
161 uint32 bufsize; 161 u32 bufsize;
162 u8 byte_val; 162 u8 byte_val;
163 163
164 /* check for Header type 0 */ 164 /* check for Header type 0 */
@@ -367,25 +367,25 @@ pcie_mdiowrite(pcicore_info_t *pi, uint physmedia, uint regaddr, uint val)
367} 367}
368 368
369/* ***** Support functions ***** */ 369/* ***** Support functions ***** */
370u8 pcie_clkreq(void *pch, uint32 mask, uint32 val) 370u8 pcie_clkreq(void *pch, u32 mask, u32 val)
371{ 371{
372 pcicore_info_t *pi = (pcicore_info_t *) pch; 372 pcicore_info_t *pi = (pcicore_info_t *) pch;
373 uint32 reg_val; 373 u32 reg_val;
374 u8 offset; 374 u8 offset;
375 375
376 offset = pi->pciecap_lcreg_offset; 376 offset = pi->pciecap_lcreg_offset;
377 if (!offset) 377 if (!offset)
378 return 0; 378 return 0;
379 379
380 reg_val = OSL_PCI_READ_CONFIG(pi->osh, offset, sizeof(uint32)); 380 reg_val = OSL_PCI_READ_CONFIG(pi->osh, offset, sizeof(u32));
381 /* set operation */ 381 /* set operation */
382 if (mask) { 382 if (mask) {
383 if (val) 383 if (val)
384 reg_val |= PCIE_CLKREQ_ENAB; 384 reg_val |= PCIE_CLKREQ_ENAB;
385 else 385 else
386 reg_val &= ~PCIE_CLKREQ_ENAB; 386 reg_val &= ~PCIE_CLKREQ_ENAB;
387 OSL_PCI_WRITE_CONFIG(pi->osh, offset, sizeof(uint32), reg_val); 387 OSL_PCI_WRITE_CONFIG(pi->osh, offset, sizeof(u32), reg_val);
388 reg_val = OSL_PCI_READ_CONFIG(pi->osh, offset, sizeof(uint32)); 388 reg_val = OSL_PCI_READ_CONFIG(pi->osh, offset, sizeof(u32));
389 } 389 }
390 if (reg_val & PCIE_CLKREQ_ENAB) 390 if (reg_val & PCIE_CLKREQ_ENAB)
391 return 1; 391 return 1;
@@ -395,7 +395,7 @@ u8 pcie_clkreq(void *pch, uint32 mask, uint32 val)
395 395
396static void pcie_extendL1timer(pcicore_info_t *pi, bool extend) 396static void pcie_extendL1timer(pcicore_info_t *pi, bool extend)
397{ 397{
398 uint32 w; 398 u32 w;
399 si_t *sih = pi->sih; 399 si_t *sih = pi->sih;
400 osl_t *osh = pi->osh; 400 osl_t *osh = pi->osh;
401 sbpcieregs_t *pcieregs = pi->regs.pcieregs; 401 sbpcieregs_t *pcieregs = pi->regs.pcieregs;
@@ -457,7 +457,7 @@ static void pcie_clkreq_upd(pcicore_info_t *pi, uint state)
457/* Done only once at attach time */ 457/* Done only once at attach time */
458static void pcie_war_polarity(pcicore_info_t *pi) 458static void pcie_war_polarity(pcicore_info_t *pi)
459{ 459{
460 uint32 w; 460 u32 w;
461 461
462 if (pi->pcie_polarity != 0) 462 if (pi->pcie_polarity != 0)
463 return; 463 return;
@@ -485,7 +485,7 @@ static void pcie_war_aspm_clkreq(pcicore_info_t *pi)
485 sbpcieregs_t *pcieregs = pi->regs.pcieregs; 485 sbpcieregs_t *pcieregs = pi->regs.pcieregs;
486 si_t *sih = pi->sih; 486 si_t *sih = pi->sih;
487 u16 val16, *reg16; 487 u16 val16, *reg16;
488 uint32 w; 488 u32 w;
489 489
490 if (!PCIE_ASPM(sih)) 490 if (!PCIE_ASPM(sih))
491 return; 491 return;
@@ -507,11 +507,11 @@ static void pcie_war_aspm_clkreq(pcicore_info_t *pi)
507 W_REG(pi->osh, reg16, val16); 507 W_REG(pi->osh, reg16, val16);
508 508
509 w = OSL_PCI_READ_CONFIG(pi->osh, pi->pciecap_lcreg_offset, 509 w = OSL_PCI_READ_CONFIG(pi->osh, pi->pciecap_lcreg_offset,
510 sizeof(uint32)); 510 sizeof(u32));
511 w &= ~PCIE_ASPM_ENAB; 511 w &= ~PCIE_ASPM_ENAB;
512 w |= pi->pcie_war_aspm_ovr; 512 w |= pi->pcie_war_aspm_ovr;
513 OSL_PCI_WRITE_CONFIG(pi->osh, pi->pciecap_lcreg_offset, 513 OSL_PCI_WRITE_CONFIG(pi->osh, pi->pciecap_lcreg_offset,
514 sizeof(uint32), w); 514 sizeof(u32), w);
515 } 515 }
516 516
517 reg16 = &pcieregs->sprom[SRSH_CLKREQ_OFFSET_REV5]; 517 reg16 = &pcieregs->sprom[SRSH_CLKREQ_OFFSET_REV5];
@@ -530,7 +530,7 @@ static void pcie_war_aspm_clkreq(pcicore_info_t *pi)
530/* Needs to happen when coming out of 'standby'/'hibernate' */ 530/* Needs to happen when coming out of 'standby'/'hibernate' */
531static void pcie_war_serdes(pcicore_info_t *pi) 531static void pcie_war_serdes(pcicore_info_t *pi)
532{ 532{
533 uint32 w = 0; 533 u32 w = 0;
534 534
535 if (pi->pcie_polarity != 0) 535 if (pi->pcie_polarity != 0)
536 pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_CTRL, 536 pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_CTRL,
@@ -583,7 +583,7 @@ static void pcie_war_pci_setup(pcicore_info_t *pi)
583 si_t *sih = pi->sih; 583 si_t *sih = pi->sih;
584 osl_t *osh = pi->osh; 584 osl_t *osh = pi->osh;
585 sbpcieregs_t *pcieregs = pi->regs.pcieregs; 585 sbpcieregs_t *pcieregs = pi->regs.pcieregs;
586 uint32 w; 586 u32 w;
587 587
588 if ((sih->buscorerev == 0) || (sih->buscorerev == 1)) { 588 if ((sih->buscorerev == 0) || (sih->buscorerev == 1)) {
589 w = pcie_readreg(osh, pcieregs, PCIE_PCIEREGS, 589 w = pcie_readreg(osh, pcieregs, PCIE_PCIEREGS,
@@ -648,7 +648,7 @@ void BCMATTACHFN(pcicore_attach) (void *pch, char *pvars, int state)
648 648
649 /* Determine if this board needs override */ 649 /* Determine if this board needs override */
650 if (PCIE_ASPM(sih)) { 650 if (PCIE_ASPM(sih)) {
651 if ((uint32) getintvar(pvars, "boardflags2") & BFL2_PCIEWAR_OVR) { 651 if ((u32) getintvar(pvars, "boardflags2") & BFL2_PCIEWAR_OVR) {
652 pi->pcie_war_aspm_ovr = PCIE_ASPM_DISAB; 652 pi->pcie_war_aspm_ovr = PCIE_ASPM_DISAB;
653 } else { 653 } else {
654 pi->pcie_war_aspm_ovr = PCIE_ASPM_ENAB; 654 pi->pcie_war_aspm_ovr = PCIE_ASPM_ENAB;
@@ -693,15 +693,15 @@ void pcicore_up(void *pch, int state)
693void pcicore_sleep(void *pch) 693void pcicore_sleep(void *pch)
694{ 694{
695 pcicore_info_t *pi = (pcicore_info_t *) pch; 695 pcicore_info_t *pi = (pcicore_info_t *) pch;
696 uint32 w; 696 u32 w;
697 697
698 if (!pi || !PCIE_ASPM(pi->sih)) 698 if (!pi || !PCIE_ASPM(pi->sih))
699 return; 699 return;
700 700
701 w = OSL_PCI_READ_CONFIG(pi->osh, pi->pciecap_lcreg_offset, 701 w = OSL_PCI_READ_CONFIG(pi->osh, pi->pciecap_lcreg_offset,
702 sizeof(uint32)); 702 sizeof(u32));
703 w &= ~PCIE_CAP_LCREG_ASPML1; 703 w &= ~PCIE_CAP_LCREG_ASPML1;
704 OSL_PCI_WRITE_CONFIG(pi->osh, pi->pciecap_lcreg_offset, sizeof(uint32), 704 OSL_PCI_WRITE_CONFIG(pi->osh, pi->pciecap_lcreg_offset, sizeof(u32),
705 w); 705 w);
706 706
707 pi->pcie_pr42767 = FALSE; 707 pi->pcie_pr42767 = FALSE;
@@ -725,7 +725,7 @@ void pcicore_down(void *pch, int state)
725bool pcicore_pmecap_fast(osl_t *osh) 725bool pcicore_pmecap_fast(osl_t *osh)
726{ 726{
727 u8 cap_ptr; 727 u8 cap_ptr;
728 uint32 pmecap; 728 u32 pmecap;
729 729
730 cap_ptr = 730 cap_ptr =
731 pcicore_find_pci_capability(osh, PCI_CAP_POWERMGMTCAP_ID, NULL, 731 pcicore_find_pci_capability(osh, PCI_CAP_POWERMGMTCAP_ID, NULL,
@@ -734,7 +734,7 @@ bool pcicore_pmecap_fast(osl_t *osh)
734 if (!cap_ptr) 734 if (!cap_ptr)
735 return FALSE; 735 return FALSE;
736 736
737 pmecap = OSL_PCI_READ_CONFIG(osh, cap_ptr, sizeof(uint32)); 737 pmecap = OSL_PCI_READ_CONFIG(osh, cap_ptr, sizeof(u32));
738 738
739 return (pmecap & PME_CAP_PM_STATES) != 0; 739 return (pmecap & PME_CAP_PM_STATES) != 0;
740} 740}
@@ -745,7 +745,7 @@ bool pcicore_pmecap_fast(osl_t *osh)
745static bool pcicore_pmecap(pcicore_info_t *pi) 745static bool pcicore_pmecap(pcicore_info_t *pi)
746{ 746{
747 u8 cap_ptr; 747 u8 cap_ptr;
748 uint32 pmecap; 748 u32 pmecap;
749 749
750 if (!pi->pmecap_offset) { 750 if (!pi->pmecap_offset) {
751 cap_ptr = 751 cap_ptr =
@@ -759,7 +759,7 @@ static bool pcicore_pmecap(pcicore_info_t *pi)
759 759
760 pmecap = 760 pmecap =
761 OSL_PCI_READ_CONFIG(pi->osh, pi->pmecap_offset, 761 OSL_PCI_READ_CONFIG(pi->osh, pi->pmecap_offset,
762 sizeof(uint32)); 762 sizeof(u32));
763 763
764 /* At least one state can generate PME */ 764 /* At least one state can generate PME */
765 pi->pmecap = (pmecap & PME_CAP_PM_STATES) != 0; 765 pi->pmecap = (pmecap & PME_CAP_PM_STATES) != 0;
@@ -772,17 +772,17 @@ static bool pcicore_pmecap(pcicore_info_t *pi)
772void pcicore_pmeen(void *pch) 772void pcicore_pmeen(void *pch)
773{ 773{
774 pcicore_info_t *pi = (pcicore_info_t *) pch; 774 pcicore_info_t *pi = (pcicore_info_t *) pch;
775 uint32 w; 775 u32 w;
776 776
777 /* if not pmecapable return */ 777 /* if not pmecapable return */
778 if (!pcicore_pmecap(pi)) 778 if (!pcicore_pmecap(pi))
779 return; 779 return;
780 780
781 w = OSL_PCI_READ_CONFIG(pi->osh, pi->pmecap_offset + PME_CSR_OFFSET, 781 w = OSL_PCI_READ_CONFIG(pi->osh, pi->pmecap_offset + PME_CSR_OFFSET,
782 sizeof(uint32)); 782 sizeof(u32));
783 w |= (PME_CSR_PME_EN); 783 w |= (PME_CSR_PME_EN);
784 OSL_PCI_WRITE_CONFIG(pi->osh, pi->pmecap_offset + PME_CSR_OFFSET, 784 OSL_PCI_WRITE_CONFIG(pi->osh, pi->pmecap_offset + PME_CSR_OFFSET,
785 sizeof(uint32), w); 785 sizeof(u32), w);
786} 786}
787 787
788/* 788/*
@@ -791,13 +791,13 @@ void pcicore_pmeen(void *pch)
791bool pcicore_pmestat(void *pch) 791bool pcicore_pmestat(void *pch)
792{ 792{
793 pcicore_info_t *pi = (pcicore_info_t *) pch; 793 pcicore_info_t *pi = (pcicore_info_t *) pch;
794 uint32 w; 794 u32 w;
795 795
796 if (!pcicore_pmecap(pi)) 796 if (!pcicore_pmecap(pi))
797 return FALSE; 797 return FALSE;
798 798
799 w = OSL_PCI_READ_CONFIG(pi->osh, pi->pmecap_offset + PME_CSR_OFFSET, 799 w = OSL_PCI_READ_CONFIG(pi->osh, pi->pmecap_offset + PME_CSR_OFFSET,
800 sizeof(uint32)); 800 sizeof(u32));
801 801
802 return (w & PME_CSR_PME_STAT) == PME_CSR_PME_STAT; 802 return (w & PME_CSR_PME_STAT) == PME_CSR_PME_STAT;
803} 803}
@@ -807,13 +807,13 @@ bool pcicore_pmestat(void *pch)
807void pcicore_pmeclr(void *pch) 807void pcicore_pmeclr(void *pch)
808{ 808{
809 pcicore_info_t *pi = (pcicore_info_t *) pch; 809 pcicore_info_t *pi = (pcicore_info_t *) pch;
810 uint32 w; 810 u32 w;
811 811
812 if (!pcicore_pmecap(pi)) 812 if (!pcicore_pmecap(pi))
813 return; 813 return;
814 814
815 w = OSL_PCI_READ_CONFIG(pi->osh, pi->pmecap_offset + PME_CSR_OFFSET, 815 w = OSL_PCI_READ_CONFIG(pi->osh, pi->pmecap_offset + PME_CSR_OFFSET,
816 sizeof(uint32)); 816 sizeof(u32));
817 817
818 PCI_ERROR(("pcicore_pci_pmeclr PMECSR : 0x%x\n", w)); 818 PCI_ERROR(("pcicore_pci_pmeclr PMECSR : 0x%x\n", w));
819 819
@@ -821,10 +821,10 @@ void pcicore_pmeclr(void *pch)
821 w &= ~(PME_CSR_PME_EN); 821 w &= ~(PME_CSR_PME_EN);
822 822
823 OSL_PCI_WRITE_CONFIG(pi->osh, pi->pmecap_offset + PME_CSR_OFFSET, 823 OSL_PCI_WRITE_CONFIG(pi->osh, pi->pmecap_offset + PME_CSR_OFFSET,
824 sizeof(uint32), w); 824 sizeof(u32), w);
825} 825}
826 826
827uint32 pcie_lcreg(void *pch, uint32 mask, uint32 val) 827u32 pcie_lcreg(void *pch, u32 mask, u32 val)
828{ 828{
829 pcicore_info_t *pi = (pcicore_info_t *) pch; 829 pcicore_info_t *pi = (pcicore_info_t *) pch;
830 u8 offset; 830 u8 offset;
@@ -835,15 +835,15 @@ uint32 pcie_lcreg(void *pch, uint32 mask, uint32 val)
835 835
836 /* set operation */ 836 /* set operation */
837 if (mask) 837 if (mask)
838 OSL_PCI_WRITE_CONFIG(pi->osh, offset, sizeof(uint32), val); 838 OSL_PCI_WRITE_CONFIG(pi->osh, offset, sizeof(u32), val);
839 839
840 return OSL_PCI_READ_CONFIG(pi->osh, offset, sizeof(uint32)); 840 return OSL_PCI_READ_CONFIG(pi->osh, offset, sizeof(u32));
841} 841}
842 842
843uint32 843u32
844pcicore_pciereg(void *pch, uint32 offset, uint32 mask, uint32 val, uint type) 844pcicore_pciereg(void *pch, u32 offset, u32 mask, u32 val, uint type)
845{ 845{
846 uint32 reg_val = 0; 846 u32 reg_val = 0;
847 pcicore_info_t *pi = (pcicore_info_t *) pch; 847 pcicore_info_t *pi = (pcicore_info_t *) pch;
848 sbpcieregs_t *pcieregs = pi->regs.pcieregs; 848 sbpcieregs_t *pcieregs = pi->regs.pcieregs;
849 osl_t *osh = pi->osh; 849 osl_t *osh = pi->osh;
@@ -864,11 +864,11 @@ pcicore_pciereg(void *pch, uint32 offset, uint32 mask, uint32 val, uint type)
864 return reg_val; 864 return reg_val;
865} 865}
866 866
867uint32 867u32
868pcicore_pcieserdesreg(void *pch, uint32 mdioslave, uint32 offset, uint32 mask, 868pcicore_pcieserdesreg(void *pch, u32 mdioslave, u32 offset, u32 mask,
869 uint32 val) 869 u32 val)
870{ 870{
871 uint32 reg_val = 0; 871 u32 reg_val = 0;
872 pcicore_info_t *pi = (pcicore_info_t *) pch; 872 pcicore_info_t *pi = (pcicore_info_t *) pch;
873 873
874 if (mask) { 874 if (mask) {
diff --git a/drivers/staging/brcm80211/util/qmath.c b/drivers/staging/brcm80211/util/qmath.c
index db06ecbbf37..e9b9d210239 100644
--- a/drivers/staging/brcm80211/util/qmath.c
+++ b/drivers/staging/brcm80211/util/qmath.c
@@ -83,7 +83,7 @@ Description: This function make 16 bit unsigned multiplication. To fit the outpu
83*/ 83*/
84u16 qm_mulu16(u16 op1, u16 op2) 84u16 qm_mulu16(u16 op1, u16 op2)
85{ 85{
86 return (u16) (((uint32) op1 * (uint32) op2) >> 16); 86 return (u16) (((u32) op1 * (u32) op2) >> 16);
87} 87}
88 88
89/* 89/*
diff --git a/drivers/staging/brcm80211/util/sbutils.c b/drivers/staging/brcm80211/util/sbutils.c
index 0f0d5a55d27..acb78a01bd3 100644
--- a/drivers/staging/brcm80211/util/sbutils.c
+++ b/drivers/staging/brcm80211/util/sbutils.c
@@ -28,10 +28,10 @@
28#include "siutils_priv.h" 28#include "siutils_priv.h"
29 29
30/* local prototypes */ 30/* local prototypes */
31static uint _sb_coreidx(si_info_t *sii, uint32 sba); 31static uint _sb_coreidx(si_info_t *sii, u32 sba);
32static uint _sb_scan(si_info_t *sii, uint32 sba, void *regs, uint bus, 32static uint _sb_scan(si_info_t *sii, u32 sba, void *regs, uint bus,
33 uint32 sbba, uint ncores); 33 u32 sbba, uint ncores);
34static uint32 _sb_coresba(si_info_t *sii); 34static u32 _sb_coresba(si_info_t *sii);
35static void *_sb_setcoreidx(si_info_t *sii, uint coreidx); 35static void *_sb_setcoreidx(si_info_t *sii, uint coreidx);
36 36
37#define SET_SBREG(sii, r, mask, val) \ 37#define SET_SBREG(sii, r, mask, val) \
@@ -49,12 +49,12 @@ static void *_sb_setcoreidx(si_info_t *sii, uint coreidx);
49#define OR_SBREG(sii, sbr, v) \ 49#define OR_SBREG(sii, sbr, v) \
50 W_SBREG((sii), (sbr), (R_SBREG((sii), (sbr)) | (v))) 50 W_SBREG((sii), (sbr), (R_SBREG((sii), (sbr)) | (v)))
51 51
52static uint32 sb_read_sbreg(si_info_t *sii, volatile uint32 *sbr) 52static u32 sb_read_sbreg(si_info_t *sii, volatile u32 *sbr)
53{ 53{
54 return R_REG(sii->osh, sbr); 54 return R_REG(sii->osh, sbr);
55} 55}
56 56
57static void sb_write_sbreg(si_info_t *sii, volatile uint32 *sbr, uint32 v) 57static void sb_write_sbreg(si_info_t *sii, volatile u32 *sbr, u32 v)
58{ 58{
59 W_REG(sii->osh, sbr, v); 59 W_REG(sii->osh, sbr, v);
60} 60}
@@ -72,7 +72,7 @@ uint sb_coreid(si_t *sih)
72} 72}
73 73
74/* return core index of the core with address 'sba' */ 74/* return core index of the core with address 'sba' */
75static uint BCMATTACHFN(_sb_coreidx) (si_info_t *sii, uint32 sba) 75static uint BCMATTACHFN(_sb_coreidx) (si_info_t *sii, u32 sba)
76{ 76{
77 uint i; 77 uint i;
78 78
@@ -83,14 +83,14 @@ static uint BCMATTACHFN(_sb_coreidx) (si_info_t *sii, uint32 sba)
83} 83}
84 84
85/* return core address of the current core */ 85/* return core address of the current core */
86static uint32 BCMATTACHFN(_sb_coresba) (si_info_t *sii) 86static u32 BCMATTACHFN(_sb_coresba) (si_info_t *sii)
87{ 87{
88 uint32 sbaddr = 0; 88 u32 sbaddr = 0;
89 89
90 switch (BUSTYPE(sii->pub.bustype)) { 90 switch (BUSTYPE(sii->pub.bustype)) {
91 case SPI_BUS: 91 case SPI_BUS:
92 case SDIO_BUS: 92 case SDIO_BUS:
93 sbaddr = (uint32) (uintptr) sii->curmap; 93 sbaddr = (u32) (uintptr) sii->curmap;
94 break; 94 break;
95 default: 95 default:
96 ASSERT(0); 96 ASSERT(0);
@@ -142,7 +142,7 @@ bool sb_iscoreup(si_t *sih)
142uint sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val) 142uint sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
143{ 143{
144 uint origidx = 0; 144 uint origidx = 0;
145 uint32 *r = NULL; 145 u32 *r = NULL;
146 uint w; 146 uint w;
147 uint intr_val = 0; 147 uint intr_val = 0;
148 bool fast = FALSE; 148 bool fast = FALSE;
@@ -164,7 +164,7 @@ uint sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
164 origidx = si_coreidx(&sii->pub); 164 origidx = si_coreidx(&sii->pub);
165 165
166 /* switch core */ 166 /* switch core */
167 r = (uint32 *) ((unsigned char *) sb_setcoreidx(&sii->pub, coreidx) + 167 r = (u32 *) ((unsigned char *) sb_setcoreidx(&sii->pub, coreidx) +
168 regoff); 168 regoff);
169 } 169 }
170 ASSERT(r != NULL); 170 ASSERT(r != NULL);
@@ -206,8 +206,8 @@ uint sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
206 */ 206 */
207#define SB_MAXBUSES 2 207#define SB_MAXBUSES 2
208static uint 208static uint
209BCMATTACHFN(_sb_scan) (si_info_t *sii, uint32 sba, void *regs, uint bus, 209BCMATTACHFN(_sb_scan) (si_info_t *sii, u32 sba, void *regs, uint bus,
210 uint32 sbba, uint numcores) { 210 u32 sbba, uint numcores) {
211 uint next; 211 uint next;
212 uint ncc = 0; 212 uint ncc = 0;
213 uint i; 213 uint i;
@@ -237,7 +237,7 @@ BCMATTACHFN(_sb_scan) (si_info_t *sii, uint32 sba, void *regs, uint bus,
237 /* chipc provides # cores */ 237 /* chipc provides # cores */
238 if (sii->coreid[next] == CC_CORE_ID) { 238 if (sii->coreid[next] == CC_CORE_ID) {
239 chipcregs_t *cc = (chipcregs_t *) sii->curmap; 239 chipcregs_t *cc = (chipcregs_t *) sii->curmap;
240 uint32 ccrev = sb_corerev(&sii->pub); 240 u32 ccrev = sb_corerev(&sii->pub);
241 241
242 /* determine numcores - this is the 242 /* determine numcores - this is the
243 total # cores in the chip */ 243 total # cores in the chip */
@@ -259,7 +259,7 @@ BCMATTACHFN(_sb_scan) (si_info_t *sii, uint32 sba, void *regs, uint bus,
259 /* scan bridged SB(s) and add results to the end of the list */ 259 /* scan bridged SB(s) and add results to the end of the list */
260 else if (sii->coreid[next] == OCP_CORE_ID) { 260 else if (sii->coreid[next] == OCP_CORE_ID) {
261 sbconfig_t *sb = REGS2SB(sii->curmap); 261 sbconfig_t *sb = REGS2SB(sii->curmap);
262 uint32 nsbba = R_SBREG(sii, &sb->sbadmatch1); 262 u32 nsbba = R_SBREG(sii, &sb->sbadmatch1);
263 uint nsbcc; 263 uint nsbcc;
264 264
265 sii->numcores = next + 1; 265 sii->numcores = next + 1;
@@ -290,7 +290,7 @@ BCMATTACHFN(_sb_scan) (si_info_t *sii, uint32 sba, void *regs, uint bus,
290void BCMATTACHFN(sb_scan) (si_t *sih, void *regs, uint devid) 290void BCMATTACHFN(sb_scan) (si_t *sih, void *regs, uint devid)
291{ 291{
292 si_info_t *sii; 292 si_info_t *sii;
293 uint32 origsba; 293 u32 origsba;
294 sbconfig_t *sb; 294 sbconfig_t *sb;
295 295
296 sii = SI_INFO(sih); 296 sii = SI_INFO(sih);
@@ -341,7 +341,7 @@ void *sb_setcoreidx(si_t *sih, uint coreidx)
341 */ 341 */
342static void *_sb_setcoreidx(si_info_t *sii, uint coreidx) 342static void *_sb_setcoreidx(si_info_t *sii, uint coreidx)
343{ 343{
344 uint32 sbaddr = sii->coresba[coreidx]; 344 u32 sbaddr = sii->coresba[coreidx];
345 void *regs; 345 void *regs;
346 346
347 switch (BUSTYPE(sii->pub.bustype)) { 347 switch (BUSTYPE(sii->pub.bustype)) {
@@ -403,9 +403,9 @@ bool sb_taclear(si_t *sih, bool details)
403 uint origidx; 403 uint origidx;
404 uint intr_val = 0; 404 uint intr_val = 0;
405 bool rc = FALSE; 405 bool rc = FALSE;
406 uint32 inband = 0, serror = 0, timeout = 0; 406 u32 inband = 0, serror = 0, timeout = 0;
407 void *corereg = NULL; 407 void *corereg = NULL;
408 volatile uint32 imstate, tmstate; 408 volatile u32 imstate, tmstate;
409 409
410 sii = SI_INFO(sih); 410 sii = SI_INFO(sih);
411 411
@@ -453,10 +453,10 @@ bool sb_taclear(si_t *sih, bool details)
453 return rc; 453 return rc;
454} 454}
455 455
456void sb_core_disable(si_t *sih, uint32 bits) 456void sb_core_disable(si_t *sih, u32 bits)
457{ 457{
458 si_info_t *sii; 458 si_info_t *sii;
459 volatile uint32 dummy; 459 volatile u32 dummy;
460 sbconfig_t *sb; 460 sbconfig_t *sb;
461 461
462 sii = SI_INFO(sih); 462 sii = SI_INFO(sih);
@@ -512,11 +512,11 @@ disable:
512 * bits - core specific bits that are set during and after reset sequence 512 * bits - core specific bits that are set during and after reset sequence
513 * resetbits - core specific bits that are set only during reset sequence 513 * resetbits - core specific bits that are set only during reset sequence
514 */ 514 */
515void sb_core_reset(si_t *sih, uint32 bits, uint32 resetbits) 515void sb_core_reset(si_t *sih, u32 bits, u32 resetbits)
516{ 516{
517 si_info_t *sii; 517 si_info_t *sii;
518 sbconfig_t *sb; 518 sbconfig_t *sb;
519 volatile uint32 dummy; 519 volatile u32 dummy;
520 520
521 sii = SI_INFO(sih); 521 sii = SI_INFO(sih);
522 ASSERT(GOODREGS(sii->curmap)); 522 ASSERT(GOODREGS(sii->curmap));
@@ -561,9 +561,9 @@ void sb_core_reset(si_t *sih, uint32 bits, uint32 resetbits)
561 OSL_DELAY(1); 561 OSL_DELAY(1);
562} 562}
563 563
564uint32 sb_base(uint32 admatch) 564u32 sb_base(u32 admatch)
565{ 565{
566 uint32 base; 566 u32 base;
567 uint type; 567 uint type;
568 568
569 type = admatch & SBAM_TYPE_MASK; 569 type = admatch & SBAM_TYPE_MASK;
diff --git a/drivers/staging/brcm80211/util/siutils.c b/drivers/staging/brcm80211/util/siutils.c
index 9ed6dfe8e4e..42fe899da3b 100644
--- a/drivers/staging/brcm80211/util/siutils.c
+++ b/drivers/staging/brcm80211/util/siutils.c
@@ -60,7 +60,7 @@ static si_info_t *si_doattach(si_info_t *sii, uint devid, osl_t *osh,
60static bool si_buscore_prep(si_info_t *sii, uint bustype, uint devid, 60static bool si_buscore_prep(si_info_t *sii, uint bustype, uint devid,
61 void *sdh); 61 void *sdh);
62static bool si_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype, 62static bool si_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype,
63 uint32 savewin, uint *origidx, void *regs); 63 u32 savewin, uint *origidx, void *regs);
64static void si_nvram_process(si_info_t *sii, char *pvars); 64static void si_nvram_process(si_info_t *sii, char *pvars);
65 65
66/* dev path concatenation util */ 66/* dev path concatenation util */
@@ -71,7 +71,7 @@ static uint BCMINITFN(socram_banksize) (si_info_t *sii, sbsocramregs_t *r,
71 u8 idx, u8 mtype); 71 u8 idx, u8 mtype);
72 72
73/* global variable to indicate reservation/release of gpio's */ 73/* global variable to indicate reservation/release of gpio's */
74static uint32 si_gpioreservation; 74static u32 si_gpioreservation;
75 75
76/* 76/*
77 * Allocate a si handle. 77 * Allocate a si handle.
@@ -167,7 +167,7 @@ BCMATTACHFN(si_buscore_prep) (si_info_t *sii, uint bustype, uint devid,
167 167
168static bool 168static bool
169BCMATTACHFN(si_buscore_setup) (si_info_t *sii, chipcregs_t *cc, uint bustype, 169BCMATTACHFN(si_buscore_setup) (si_info_t *sii, chipcregs_t *cc, uint bustype,
170 uint32 savewin, uint *origidx, void *regs) { 170 u32 savewin, uint *origidx, void *regs) {
171 bool pci, pcie; 171 bool pci, pcie;
172 uint i; 172 uint i;
173 uint pciidx, pcieidx, pcirev, pcierev; 173 uint pciidx, pcieidx, pcirev, pcierev;
@@ -313,7 +313,7 @@ static __used void BCMATTACHFN(si_nvram_process) (si_info_t *sii, char *pvars)
313 switch (BUSTYPE(sii->pub.bustype)) { 313 switch (BUSTYPE(sii->pub.bustype)) {
314 case PCI_BUS: 314 case PCI_BUS:
315 /* do a pci config read to get subsystem id and subvendor id */ 315 /* do a pci config read to get subsystem id and subvendor id */
316 w = OSL_PCI_READ_CONFIG(sii->osh, PCI_CFG_SVID, sizeof(uint32)); 316 w = OSL_PCI_READ_CONFIG(sii->osh, PCI_CFG_SVID, sizeof(u32));
317 /* Let nvram variables override subsystem Vend/ID */ 317 /* Let nvram variables override subsystem Vend/ID */
318 sii->pub.boardvendor = (u16)si_getdevpathintvar(&sii->pub, 318 sii->pub.boardvendor = (u16)si_getdevpathintvar(&sii->pub,
319 "boardvendor"); 319 "boardvendor");
@@ -371,7 +371,7 @@ static si_info_t *BCMATTACHFN(si_doattach) (si_info_t *sii, uint devid,
371 uint bustype, void *sdh, 371 uint bustype, void *sdh,
372 char **vars, uint *varsz) { 372 char **vars, uint *varsz) {
373 struct si_pub *sih = &sii->pub; 373 struct si_pub *sih = &sii->pub;
374 uint32 w, savewin; 374 u32 w, savewin;
375 chipcregs_t *cc; 375 chipcregs_t *cc;
376 char *pvars = NULL; 376 char *pvars = NULL;
377 uint origidx; 377 uint origidx;
@@ -470,7 +470,7 @@ static si_info_t *BCMATTACHFN(si_doattach) (si_info_t *sii, uint devid,
470#ifndef BRCM_FULLMAC 470#ifndef BRCM_FULLMAC
471 /* PMU specific initializations */ 471 /* PMU specific initializations */
472 if (PMUCTL_ENAB(sih)) { 472 if (PMUCTL_ENAB(sih)) {
473 uint32 xtalfreq; 473 u32 xtalfreq;
474 si_pmu_init(sih, sii->osh); 474 si_pmu_init(sih, sii->osh);
475 si_pmu_chip_init(sih, sii->osh); 475 si_pmu_chip_init(sih, sii->osh);
476 xtalfreq = getintvar(pvars, "xtalfreq"); 476 xtalfreq = getintvar(pvars, "xtalfreq");
@@ -506,7 +506,7 @@ static si_info_t *BCMATTACHFN(si_doattach) (si_info_t *sii, uint devid,
506 uint bustype, void *sdh, 506 uint bustype, void *sdh,
507 char **vars, uint *varsz) { 507 char **vars, uint *varsz) {
508 struct si_pub *sih = &sii->pub; 508 struct si_pub *sih = &sii->pub;
509 uint32 w, savewin; 509 u32 w, savewin;
510 chipcregs_t *cc; 510 chipcregs_t *cc;
511 char *pvars = NULL; 511 char *pvars = NULL;
512 uint origidx; 512 uint origidx;
@@ -525,7 +525,7 @@ static si_info_t *BCMATTACHFN(si_doattach) (si_info_t *sii, uint devid,
525 525
526 /* check to see if we are a si core mimic'ing a pci core */ 526 /* check to see if we are a si core mimic'ing a pci core */
527 if ((bustype == PCI_BUS) && 527 if ((bustype == PCI_BUS) &&
528 (OSL_PCI_READ_CONFIG(sii->osh, PCI_SPROM_CONTROL, sizeof(uint32)) == 528 (OSL_PCI_READ_CONFIG(sii->osh, PCI_SPROM_CONTROL, sizeof(u32)) ==
529 0xffffffff)) { 529 0xffffffff)) {
530 SI_ERROR(("%s: incoming bus is PCI but it's a lie, switching to SI " "devid:0x%x\n", __func__, devid)); 530 SI_ERROR(("%s: incoming bus is PCI but it's a lie, switching to SI " "devid:0x%x\n", __func__, devid));
531 bustype = SI_BUS; 531 bustype = SI_BUS;
@@ -534,7 +534,7 @@ static si_info_t *BCMATTACHFN(si_doattach) (si_info_t *sii, uint devid,
534 /* find Chipcommon address */ 534 /* find Chipcommon address */
535 if (bustype == PCI_BUS) { 535 if (bustype == PCI_BUS) {
536 savewin = 536 savewin =
537 OSL_PCI_READ_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(uint32)); 537 OSL_PCI_READ_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(u32));
538 if (!GOODCOREADDR(savewin, SI_ENUM_BASE)) 538 if (!GOODCOREADDR(savewin, SI_ENUM_BASE))
539 savewin = SI_ENUM_BASE; 539 savewin = SI_ENUM_BASE;
540 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, SI_ENUM_BASE); 540 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, SI_ENUM_BASE);
@@ -630,7 +630,7 @@ static si_info_t *BCMATTACHFN(si_doattach) (si_info_t *sii, uint devid,
630 630
631 /* PMU specific initializations */ 631 /* PMU specific initializations */
632 if (PMUCTL_ENAB(sih)) { 632 if (PMUCTL_ENAB(sih)) {
633 uint32 xtalfreq; 633 u32 xtalfreq;
634 si_pmu_init(sih, sii->osh); 634 si_pmu_init(sih, sii->osh);
635 si_pmu_chip_init(sih, sii->osh); 635 si_pmu_chip_init(sih, sii->osh);
636 xtalfreq = getintvar(pvars, "xtalfreq"); 636 xtalfreq = getintvar(pvars, "xtalfreq");
@@ -918,7 +918,7 @@ void si_restore_core(si_t *sih, uint coreid, uint intr_val)
918 INTR_RESTORE(sii, intr_val); 918 INTR_RESTORE(sii, intr_val);
919} 919}
920 920
921uint32 si_core_cflags(si_t *sih, uint32 mask, uint32 val) 921u32 si_core_cflags(si_t *sih, u32 mask, u32 val)
922{ 922{
923 if (CHIPTYPE(sih->socitype) == SOCI_AI) 923 if (CHIPTYPE(sih->socitype) == SOCI_AI)
924 return ai_core_cflags(sih, mask, val); 924 return ai_core_cflags(sih, mask, val);
@@ -928,7 +928,7 @@ uint32 si_core_cflags(si_t *sih, uint32 mask, uint32 val)
928 } 928 }
929} 929}
930 930
931uint32 si_core_sflags(si_t *sih, uint32 mask, uint32 val) 931u32 si_core_sflags(si_t *sih, u32 mask, u32 val)
932{ 932{
933 if (CHIPTYPE(sih->socitype) == SOCI_AI) 933 if (CHIPTYPE(sih->socitype) == SOCI_AI)
934 return ai_core_sflags(sih, mask, val); 934 return ai_core_sflags(sih, mask, val);
@@ -952,7 +952,7 @@ bool si_iscoreup(si_t *sih)
952 } 952 }
953} 953}
954 954
955void si_write_wrapperreg(si_t *sih, uint32 offset, uint32 val) 955void si_write_wrapperreg(si_t *sih, u32 offset, u32 val)
956{ 956{
957 /* only for 4319, no requirement for SOCI_SB */ 957 /* only for 4319, no requirement for SOCI_SB */
958 if (CHIPTYPE(sih->socitype) == SOCI_AI) { 958 if (CHIPTYPE(sih->socitype) == SOCI_AI) {
@@ -975,7 +975,7 @@ uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
975 } 975 }
976} 976}
977 977
978void si_core_disable(si_t *sih, uint32 bits) 978void si_core_disable(si_t *sih, u32 bits)
979{ 979{
980 980
981 if (CHIPTYPE(sih->socitype) == SOCI_AI) 981 if (CHIPTYPE(sih->socitype) == SOCI_AI)
@@ -986,7 +986,7 @@ void si_core_disable(si_t *sih, uint32 bits)
986#endif 986#endif
987} 987}
988 988
989void si_core_reset(si_t *sih, uint32 bits, uint32 resetbits) 989void si_core_reset(si_t *sih, u32 bits, u32 resetbits)
990{ 990{
991 if (CHIPTYPE(sih->socitype) == SOCI_AI) 991 if (CHIPTYPE(sih->socitype) == SOCI_AI)
992 ai_core_reset(sih, bits, resetbits); 992 ai_core_reset(sih, bits, resetbits);
@@ -996,7 +996,7 @@ void si_core_reset(si_t *sih, uint32 bits, uint32 resetbits)
996#endif 996#endif
997} 997}
998 998
999uint32 BCMINITFN(si_alp_clock) (si_t *sih) 999u32 BCMINITFN(si_alp_clock) (si_t *sih)
1000{ 1000{
1001 if (PMUCTL_ENAB(sih)) 1001 if (PMUCTL_ENAB(sih))
1002 return si_pmu_alp_clock(sih, si_osh(sih)); 1002 return si_pmu_alp_clock(sih, si_osh(sih));
@@ -1004,7 +1004,7 @@ uint32 BCMINITFN(si_alp_clock) (si_t *sih)
1004 return ALP_CLOCK; 1004 return ALP_CLOCK;
1005} 1005}
1006 1006
1007uint32 BCMINITFN(si_ilp_clock) (si_t *sih) 1007u32 BCMINITFN(si_ilp_clock) (si_t *sih)
1008{ 1008{
1009 if (PMUCTL_ENAB(sih)) 1009 if (PMUCTL_ENAB(sih))
1010 return si_pmu_ilp_clock(sih, si_osh(sih)); 1010 return si_pmu_ilp_clock(sih, si_osh(sih));
@@ -1092,7 +1092,7 @@ static uint si_slowclk_src(si_info_t *sii)
1092 1092
1093 if (sii->pub.ccrev < 6) { 1093 if (sii->pub.ccrev < 6) {
1094 if ((BUSTYPE(sii->pub.bustype) == PCI_BUS) && 1094 if ((BUSTYPE(sii->pub.bustype) == PCI_BUS) &&
1095 (OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_OUT, sizeof(uint32)) 1095 (OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_OUT, sizeof(u32))
1096 & PCI_CFG_GPIO_SCS)) 1096 & PCI_CFG_GPIO_SCS))
1097 return SCC_SS_PCI; 1097 return SCC_SS_PCI;
1098 else 1098 else
@@ -1107,7 +1107,7 @@ static uint si_slowclk_src(si_info_t *sii)
1107/* return the ILP (slowclock) min or max frequency */ 1107/* return the ILP (slowclock) min or max frequency */
1108static uint si_slowclk_freq(si_info_t *sii, bool max_freq, chipcregs_t *cc) 1108static uint si_slowclk_freq(si_info_t *sii, bool max_freq, chipcregs_t *cc)
1109{ 1109{
1110 uint32 slowclk; 1110 u32 slowclk;
1111 uint div; 1111 uint div;
1112 1112
1113 ASSERT(SI_FAST(sii) || si_coreid(&sii->pub) == CC_CORE_ID); 1113 ASSERT(SI_FAST(sii) || si_coreid(&sii->pub) == CC_CORE_ID);
@@ -1262,7 +1262,7 @@ u16 BCMINITFN(si_clkctl_fast_pwrup_delay) (si_t *sih)
1262int si_clkctl_xtal(si_t *sih, uint what, bool on) 1262int si_clkctl_xtal(si_t *sih, uint what, bool on)
1263{ 1263{
1264 si_info_t *sii; 1264 si_info_t *sii;
1265 uint32 in, out, outen; 1265 u32 in, out, outen;
1266 1266
1267 sii = SI_INFO(sih); 1267 sii = SI_INFO(sih);
1268 1268
@@ -1278,12 +1278,12 @@ int si_clkctl_xtal(si_t *sih, uint what, bool on)
1278 if (PCIE(sii)) 1278 if (PCIE(sii))
1279 return -1; 1279 return -1;
1280 1280
1281 in = OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_IN, sizeof(uint32)); 1281 in = OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_IN, sizeof(u32));
1282 out = 1282 out =
1283 OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_OUT, sizeof(uint32)); 1283 OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_OUT, sizeof(u32));
1284 outen = 1284 outen =
1285 OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_OUTEN, 1285 OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_OUTEN,
1286 sizeof(uint32)); 1286 sizeof(u32));
1287 1287
1288 /* 1288 /*
1289 * Avoid glitching the clock if GPRS is already using it. 1289 * Avoid glitching the clock if GPRS is already using it.
@@ -1305,9 +1305,9 @@ int si_clkctl_xtal(si_t *sih, uint what, bool on)
1305 if (what & PLL) 1305 if (what & PLL)
1306 out |= PCI_CFG_GPIO_PLL; 1306 out |= PCI_CFG_GPIO_PLL;
1307 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUT, 1307 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUT,
1308 sizeof(uint32), out); 1308 sizeof(u32), out);
1309 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUTEN, 1309 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUTEN,
1310 sizeof(uint32), outen); 1310 sizeof(u32), outen);
1311 OSL_DELAY(XTAL_ON_DELAY); 1311 OSL_DELAY(XTAL_ON_DELAY);
1312 } 1312 }
1313 1313
@@ -1315,7 +1315,7 @@ int si_clkctl_xtal(si_t *sih, uint what, bool on)
1315 if (what & PLL) { 1315 if (what & PLL) {
1316 out &= ~PCI_CFG_GPIO_PLL; 1316 out &= ~PCI_CFG_GPIO_PLL;
1317 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUT, 1317 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUT,
1318 sizeof(uint32), out); 1318 sizeof(u32), out);
1319 OSL_DELAY(2000); 1319 OSL_DELAY(2000);
1320 } 1320 }
1321 } else { 1321 } else {
@@ -1324,9 +1324,9 @@ int si_clkctl_xtal(si_t *sih, uint what, bool on)
1324 if (what & PLL) 1324 if (what & PLL)
1325 out |= PCI_CFG_GPIO_PLL; 1325 out |= PCI_CFG_GPIO_PLL;
1326 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUT, 1326 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUT,
1327 sizeof(uint32), out); 1327 sizeof(u32), out);
1328 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUTEN, 1328 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUTEN,
1329 sizeof(uint32), outen); 1329 sizeof(u32), outen);
1330 } 1330 }
1331 1331
1332 default: 1332 default:
@@ -1365,7 +1365,7 @@ static bool _si_clkctl_cc(si_info_t *sii, uint mode)
1365{ 1365{
1366 uint origidx = 0; 1366 uint origidx = 0;
1367 chipcregs_t *cc; 1367 chipcregs_t *cc;
1368 uint32 scc; 1368 u32 scc;
1369 uint intr_val = 0; 1369 uint intr_val = 0;
1370 bool fast = SI_FAST(sii); 1370 bool fast = SI_FAST(sii);
1371 1371
@@ -1411,7 +1411,7 @@ static bool _si_clkctl_cc(si_info_t *sii, uint mode)
1411 1411
1412 /* wait for the PLL */ 1412 /* wait for the PLL */
1413 if (PMUCTL_ENAB(&sii->pub)) { 1413 if (PMUCTL_ENAB(&sii->pub)) {
1414 uint32 htavail = CCS_HTAVAIL; 1414 u32 htavail = CCS_HTAVAIL;
1415 SPINWAIT(((R_REG(sii->osh, &cc->clk_ctl_st) & htavail) 1415 SPINWAIT(((R_REG(sii->osh, &cc->clk_ctl_st) & htavail)
1416 == 0), PMU_MAX_TRANSITION_DLY); 1416 == 0), PMU_MAX_TRANSITION_DLY);
1417 ASSERT(R_REG(sii->osh, &cc->clk_ctl_st) & htavail); 1417 ASSERT(R_REG(sii->osh, &cc->clk_ctl_st) & htavail);
@@ -1666,7 +1666,7 @@ void BCMATTACHFN(si_pci_setup) (si_t *sih, uint coremask)
1666{ 1666{
1667 si_info_t *sii; 1667 si_info_t *sii;
1668 sbpciregs_t *pciregs = NULL; 1668 sbpciregs_t *pciregs = NULL;
1669 uint32 siflag = 0, w; 1669 u32 siflag = 0, w;
1670 uint idx = 0; 1670 uint idx = 0;
1671 1671
1672 sii = SI_INFO(sih); 1672 sii = SI_INFO(sih);
@@ -1695,9 +1695,9 @@ void BCMATTACHFN(si_pci_setup) (si_t *sih, uint coremask)
1695 */ 1695 */
1696 if (PCIE(sii) || (PCI(sii) && ((sii->pub.buscorerev) >= 6))) { 1696 if (PCIE(sii) || (PCI(sii) && ((sii->pub.buscorerev) >= 6))) {
1697 /* pci config write to set this core bit in PCIIntMask */ 1697 /* pci config write to set this core bit in PCIIntMask */
1698 w = OSL_PCI_READ_CONFIG(sii->osh, PCI_INT_MASK, sizeof(uint32)); 1698 w = OSL_PCI_READ_CONFIG(sii->osh, PCI_INT_MASK, sizeof(u32));
1699 w |= (coremask << PCI_SBIM_SHIFT); 1699 w |= (coremask << PCI_SBIM_SHIFT);
1700 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_INT_MASK, sizeof(uint32), w); 1700 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_INT_MASK, sizeof(u32), w);
1701 } else { 1701 } else {
1702 /* set sbintvec bit for our flag number */ 1702 /* set sbintvec bit for our flag number */
1703 si_setint(sih, siflag); 1703 si_setint(sih, siflag);
@@ -1770,7 +1770,7 @@ int si_pci_fixcfg(si_t *sih)
1770} 1770}
1771 1771
1772/* mask&set gpiocontrol bits */ 1772/* mask&set gpiocontrol bits */
1773uint32 si_gpiocontrol(si_t *sih, uint32 mask, uint32 val, u8 priority) 1773u32 si_gpiocontrol(si_t *sih, u32 mask, u32 val, u8 priority)
1774{ 1774{
1775 uint regoff; 1775 uint regoff;
1776 1776
@@ -1808,7 +1808,7 @@ socram_banksize(si_info_t *sii, sbsocramregs_t *regs, u8 index,
1808} 1808}
1809 1809
1810/* Return the RAM size of the SOCRAM core */ 1810/* Return the RAM size of the SOCRAM core */
1811uint32 si_socram_size(si_t *sih) 1811u32 si_socram_size(si_t *sih)
1812{ 1812{
1813 si_info_t *sii; 1813 si_info_t *sii;
1814 uint origidx; 1814 uint origidx;
@@ -1817,7 +1817,7 @@ uint32 si_socram_size(si_t *sih)
1817 sbsocramregs_t *regs; 1817 sbsocramregs_t *regs;
1818 bool wasup; 1818 bool wasup;
1819 uint corerev; 1819 uint corerev;
1820 uint32 coreinfo; 1820 u32 coreinfo;
1821 uint memsize = 0; 1821 uint memsize = 0;
1822 1822
1823 sii = SI_INFO(sih); 1823 sii = SI_INFO(sih);
@@ -1877,7 +1877,7 @@ void si_chipcontrl_epa4331(si_t *sih, bool on)
1877 si_info_t *sii; 1877 si_info_t *sii;
1878 chipcregs_t *cc; 1878 chipcregs_t *cc;
1879 uint origidx; 1879 uint origidx;
1880 uint32 val; 1880 u32 val;
1881 1881
1882 sii = SI_INFO(sih); 1882 sii = SI_INFO(sih);
1883 origidx = si_coreidx(sih); 1883 origidx = si_coreidx(sih);
@@ -1927,7 +1927,7 @@ void si_epa_4313war(si_t *sih)
1927/* check if the device is removed */ 1927/* check if the device is removed */
1928bool si_deviceremoved(si_t *sih) 1928bool si_deviceremoved(si_t *sih)
1929{ 1929{
1930 uint32 w; 1930 u32 w;
1931 si_info_t *sii; 1931 si_info_t *sii;
1932 1932
1933 sii = SI_INFO(sih); 1933 sii = SI_INFO(sih);
@@ -1935,7 +1935,7 @@ bool si_deviceremoved(si_t *sih)
1935 switch (BUSTYPE(sih->bustype)) { 1935 switch (BUSTYPE(sih->bustype)) {
1936 case PCI_BUS: 1936 case PCI_BUS:
1937 ASSERT(sii->osh != NULL); 1937 ASSERT(sii->osh != NULL);
1938 w = OSL_PCI_READ_CONFIG(sii->osh, PCI_CFG_VID, sizeof(uint32)); 1938 w = OSL_PCI_READ_CONFIG(sii->osh, PCI_CFG_VID, sizeof(u32));
1939 if ((w & 0xFFFF) != VENDOR_BROADCOM) 1939 if ((w & 0xFFFF) != VENDOR_BROADCOM)
1940 return TRUE; 1940 return TRUE;
1941 break; 1941 break;
@@ -1949,7 +1949,7 @@ bool si_is_sprom_available(si_t *sih)
1949 si_info_t *sii; 1949 si_info_t *sii;
1950 uint origidx; 1950 uint origidx;
1951 chipcregs_t *cc; 1951 chipcregs_t *cc;
1952 uint32 sromctrl; 1952 u32 sromctrl;
1953 1953
1954 if ((sih->cccaps & CC_CAP_SROM) == 0) 1954 if ((sih->cccaps & CC_CAP_SROM) == 0)
1955 return FALSE; 1955 return FALSE;
diff --git a/drivers/staging/brcm80211/util/siutils_priv.h b/drivers/staging/brcm80211/util/siutils_priv.h
index 51b8803c9ce..02846144148 100644
--- a/drivers/staging/brcm80211/util/siutils_priv.h
+++ b/drivers/staging/brcm80211/util/siutils_priv.h
@@ -25,8 +25,8 @@ extern uint sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask,
25 uint val); 25 uint val);
26extern bool sb_iscoreup(si_t *sih); 26extern bool sb_iscoreup(si_t *sih);
27void *sb_setcoreidx(si_t *sih, uint coreidx); 27void *sb_setcoreidx(si_t *sih, uint coreidx);
28extern uint32 sb_base(uint32 admatch); 28extern u32 sb_base(u32 admatch);
29extern void sb_core_reset(si_t *sih, uint32 bits, uint32 resetbits); 29extern void sb_core_reset(si_t *sih, u32 bits, u32 resetbits);
30extern void sb_core_disable(si_t *sih, uint32 bits); 30extern void sb_core_disable(si_t *sih, u32 bits);
31extern bool sb_taclear(si_t *sih, bool details); 31extern bool sb_taclear(si_t *sih, bool details);
32#endif /* _siutils_priv_h_ */ 32#endif /* _siutils_priv_h_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-21 21:39:22 -0400