ARM: 6431/1: fix isb regression on CPU < v7

The kernel does not compile for my ARM926EJ-S system U300 due to
the isb instruction inserted in generic assember statement from
commit 8925ec4c530094b878e7e28a1fd78e7122afd973, "ARM: 6385/1:
setup: detect aliasing I-cache when D-cache is non-aliasing"
hey the isb is only available when assembling for v7 so let's
use the generic isb() macro from setup.h instead.

Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 5 insertions, 4 deletions

diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 9fc483393ba..e0430d036ce 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -246,11 +246,12 @@ static int cpu_has_aliasing_icache(unsigned int arch)
         /* arch specifies the register format */
         switch (arch) {
         case CPU_ARCH_ARMv7:
-                asm("mcr        p15, 2, %1, c0, c0, 0   @ set CSSELR\n"
-                    "isb\n"
-                    "mrc        p15, 1, %0, c0, c0, 0   @ read CCSIDR"
-                    : "=r" (id_reg)
+                asm("mcr        p15, 2, %0, c0, c0, 0 @ set CSSELR"
+                    : /* No output operands */
                     : "r" (1));
+                isb();
+                asm("mrc        p15, 1, %0, c0, c0, 0 @ read CCSIDR"
+                    : "=r" (id_reg));
                 line_size = 4 << ((id_reg & 0x7) + 2);
                 num_sets = ((id_reg >> 13) & 0x7fff) + 1;
                 aliasing_icache = (line_size * num_sets) > PAGE_SIZE;