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authorKevin Hilman <khilman@deeprootsystems.com>2009-04-14 10:50:37 -0400
committerKevin Hilman <khilman@deeprootsystems.com>2009-04-27 12:49:46 -0400
commit5526b3f7e3317bdd0dcc0483214935ae64236efb (patch)
treeb79862724db5ffec0ffb0bb78c3534e5ffefb1b7
parent617b925f94e0126841164ffd40dd3a8879502b57 (diff)
davinci: update pin-multiplexing support
Update MUX support to be more general and useful across multiple SoCs in the DaVinci family. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
-rw-r--r--arch/arm/mach-davinci/Kconfig26
-rw-r--r--arch/arm/mach-davinci/Makefile4
-rw-r--r--arch/arm/mach-davinci/devices.c5
-rw-r--r--arch/arm/mach-davinci/include/mach/mux.h220
-rw-r--r--arch/arm/mach-davinci/mux.c99
-rw-r--r--arch/arm/mach-davinci/mux.h51
6 files changed, 339 insertions, 66 deletions
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index af886734c73..f18090e78e3 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -18,6 +18,32 @@ config MACH_DAVINCI_EVM
18 Configure this option to specify the whether the board used 18 Configure this option to specify the whether the board used
19 for development is a DaVinci EVM 19 for development is a DaVinci EVM
20 20
21
22config DAVINCI_MUX
23 bool "DAVINCI multiplexing support"
24 depends on ARCH_DAVINCI
25 default y
26 help
27 Pin multiplexing support for DAVINCI boards. If your bootloader
28 sets the multiplexing correctly, say N. Otherwise, or if unsure,
29 say Y.
30
31config DAVINCI_MUX_DEBUG
32 bool "Multiplexing debug output"
33 depends on DAVINCI_MUX
34 help
35 Makes the multiplexing functions print out a lot of debug info.
36 This is useful if you want to find out the correct values of the
37 multiplexing registers.
38
39config DAVINCI_MUX_WARNINGS
40 bool "Warn about pins the bootloader didn't set up"
41 depends on DAVINCI_MUX
42 help
43 Choose Y here to warn whenever driver initialization logic needs
44 to change the pin multiplexing setup. When there are no warnings
45 printed, it's safe to deselect DAVINCI_MUX for your product.
46
21config DAVINCI_RESET_CLOCKS 47config DAVINCI_RESET_CLOCKS
22 bool "Reset unused clocks during boot" 48 bool "Reset unused clocks during boot"
23 depends on ARCH_DAVINCI 49 depends on ARCH_DAVINCI
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 3ee3d73d956..b27871af4fc 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -5,7 +5,9 @@
5 5
6# Common objects 6# Common objects
7obj-y := time.o irq.o clock.o serial.o io.o id.o psc.o \ 7obj-y := time.o irq.o clock.o serial.o io.o id.o psc.o \
8 gpio.o mux.o devices.o dma.o usb.o 8 gpio.o devices.o dma.o usb.o
9
10obj-$(CONFIG_DAVINCI_MUX) += mux.o
9 11
10# Board specific 12# Board specific
11obj-$(CONFIG_MACH_DAVINCI_EVM) += board-evm.o 13obj-$(CONFIG_MACH_DAVINCI_EVM) += board-evm.o
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index 3ea6d477f06..a31370b93dd 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -21,6 +21,8 @@
21#include <mach/hardware.h> 21#include <mach/hardware.h>
22#include <mach/i2c.h> 22#include <mach/i2c.h>
23#include <mach/irqs.h> 23#include <mach/irqs.h>
24#include <mach/cputype.h>
25#include <mach/mux.h>
24 26
25#define DAVINCI_I2C_BASE 0x01C21000 27#define DAVINCI_I2C_BASE 0x01C21000
26 28
@@ -45,6 +47,9 @@ static struct platform_device davinci_i2c_device = {
45 47
46void __init davinci_init_i2c(struct davinci_i2c_platform_data *pdata) 48void __init davinci_init_i2c(struct davinci_i2c_platform_data *pdata)
47{ 49{
50 if (cpu_is_davinci_dm644x())
51 davinci_cfg_reg(DM644X_I2C);
52
48 davinci_i2c_device.dev.platform_data = pdata; 53 davinci_i2c_device.dev.platform_data = pdata;
49 (void) platform_device_register(&davinci_i2c_device); 54 (void) platform_device_register(&davinci_i2c_device);
50} 55}
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index c24b6782804..bae22cb3e27 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -1,55 +1,183 @@
1/* 1/*
2 * DaVinci pin multiplexing defines 2 * Table of the DAVINCI register configurations for the PINMUX combinations
3 * 3 *
4 * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com> 4 * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
5 * 5 *
6 * Based on linux/include/asm-arm/arch-omap/mux.h:
7 * Copyright (C) 2003 - 2005 Nokia Corporation
8 *
9 * Written by Tony Lindgren
10 *
6 * 2007 (c) MontaVista Software, Inc. This file is licensed under 11 * 2007 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program 12 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express 13 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied. 14 * or implied.
15 *
16 * Copyright (C) 2008 Texas Instruments.
10 */ 17 */
11#ifndef __ASM_ARCH_MUX_H 18
12#define __ASM_ARCH_MUX_H 19#ifndef __INC_MACH_MUX_H
13 20#define __INC_MACH_MUX_H
14#define DAVINCI_MUX_AEAW0 0 21
15#define DAVINCI_MUX_AEAW1 1 22/* System module registers */
16#define DAVINCI_MUX_AEAW2 2 23#define PINMUX0 0x00
17#define DAVINCI_MUX_AEAW3 3 24#define PINMUX1 0x04
18#define DAVINCI_MUX_AEAW4 4 25/* dm355 only */
19#define DAVINCI_MUX_AECS4 10 26#define PINMUX2 0x08
20#define DAVINCI_MUX_AECS5 11 27#define PINMUX3 0x0c
21#define DAVINCI_MUX_VLYNQWD0 12 28#define PINMUX4 0x10
22#define DAVINCI_MUX_VLYNQWD1 13 29#define INTMUX 0x18
23#define DAVINCI_MUX_VLSCREN 14 30#define EVTMUX 0x1c
24#define DAVINCI_MUX_VLYNQEN 15 31
25#define DAVINCI_MUX_HDIREN 16 32struct mux_config {
26#define DAVINCI_MUX_ATAEN 17 33 const char *name;
27#define DAVINCI_MUX_RGB666 22 34 const char *mux_reg_name;
28#define DAVINCI_MUX_RGB888 23 35 const unsigned char mux_reg;
29#define DAVINCI_MUX_LOEEN 24 36 const unsigned char mask_offset;
30#define DAVINCI_MUX_LFLDEN 25 37 const unsigned char mask;
31#define DAVINCI_MUX_CWEN 26 38 const unsigned char mode;
32#define DAVINCI_MUX_CFLDEN 27 39 bool debug;
33#define DAVINCI_MUX_HPIEN 29 40};
34#define DAVINCI_MUX_1394EN 30 41
35#define DAVINCI_MUX_EMACEN 31 42enum davinci_dm644x_index {
36 43 /* ATA and HDDIR functions */
37#define DAVINCI_MUX_LEVEL2 32 44 DM644X_HDIREN,
38#define DAVINCI_MUX_UART0 (DAVINCI_MUX_LEVEL2 + 0) 45 DM644X_ATAEN,
39#define DAVINCI_MUX_UART1 (DAVINCI_MUX_LEVEL2 + 1) 46 DM644X_ATAEN_DISABLE,
40#define DAVINCI_MUX_UART2 (DAVINCI_MUX_LEVEL2 + 2) 47
41#define DAVINCI_MUX_U2FLO (DAVINCI_MUX_LEVEL2 + 3) 48 /* HPI functions */
42#define DAVINCI_MUX_PWM0 (DAVINCI_MUX_LEVEL2 + 4) 49 DM644X_HPIEN_DISABLE,
43#define DAVINCI_MUX_PWM1 (DAVINCI_MUX_LEVEL2 + 5) 50
44#define DAVINCI_MUX_PWM2 (DAVINCI_MUX_LEVEL2 + 6) 51 /* AEAW functions */
45#define DAVINCI_MUX_I2C (DAVINCI_MUX_LEVEL2 + 7) 52 DM644X_AEAW,
46#define DAVINCI_MUX_SPI (DAVINCI_MUX_LEVEL2 + 8) 53
47#define DAVINCI_MUX_MSTK (DAVINCI_MUX_LEVEL2 + 9) 54 /* Memory Stick */
48#define DAVINCI_MUX_ASP (DAVINCI_MUX_LEVEL2 + 10) 55 DM644X_MSTK,
49#define DAVINCI_MUX_CLK0 (DAVINCI_MUX_LEVEL2 + 16) 56
50#define DAVINCI_MUX_CLK1 (DAVINCI_MUX_LEVEL2 + 17) 57 /* I2C */
51#define DAVINCI_MUX_TIMIN (DAVINCI_MUX_LEVEL2 + 18) 58 DM644X_I2C,
52 59
53extern void davinci_mux_peripheral(unsigned int mux, unsigned int enable); 60 /* ASP function */
54 61 DM644X_MCBSP,
55#endif /* __ASM_ARCH_MUX_H */ 62
63 /* UART1 */
64 DM644X_UART1,
65
66 /* UART2 */
67 DM644X_UART2,
68
69 /* PWM0 */
70 DM644X_PWM0,
71
72 /* PWM1 */
73 DM644X_PWM1,
74
75 /* PWM2 */
76 DM644X_PWM2,
77
78 /* VLYNQ function */
79 DM644X_VLYNQEN,
80 DM644X_VLSCREN,
81 DM644X_VLYNQWD,
82
83 /* EMAC and MDIO function */
84 DM644X_EMACEN,
85
86 /* GPIO3V[0:16] pins */
87 DM644X_GPIO3V,
88
89 /* GPIO pins */
90 DM644X_GPIO0,
91 DM644X_GPIO3,
92 DM644X_GPIO43_44,
93 DM644X_GPIO46_47,
94
95 /* VPBE */
96 DM644X_RGB666,
97
98 /* LCD */
99 DM644X_LOEEN,
100 DM644X_LFLDEN,
101};
102
103enum davinci_dm646x_index {
104 /* ATA function */
105 DM646X_ATAEN,
106
107 /* AUDIO Clock */
108 DM646X_AUDCK1,
109 DM646X_AUDCK0,
110
111 /* CRGEN Control */
112 DM646X_CRGMUX,
113
114 /* VPIF Control */
115 DM646X_STSOMUX_DISABLE,
116 DM646X_STSIMUX_DISABLE,
117 DM646X_PTSOMUX_DISABLE,
118 DM646X_PTSIMUX_DISABLE,
119
120 /* TSIF Control */
121 DM646X_STSOMUX,
122 DM646X_STSIMUX,
123 DM646X_PTSOMUX_PARALLEL,
124 DM646X_PTSIMUX_PARALLEL,
125 DM646X_PTSOMUX_SERIAL,
126 DM646X_PTSIMUX_SERIAL,
127};
128
129enum davinci_dm355_index {
130 /* MMC/SD 0 */
131 DM355_MMCSD0,
132
133 /* MMC/SD 1 */
134 DM355_SD1_CLK,
135 DM355_SD1_CMD,
136 DM355_SD1_DATA3,
137 DM355_SD1_DATA2,
138 DM355_SD1_DATA1,
139 DM355_SD1_DATA0,
140
141 /* I2C */
142 DM355_I2C_SDA,
143 DM355_I2C_SCL,
144
145 /* ASP0 function */
146 DM355_MCBSP0_BDX,
147 DM355_MCBSP0_X,
148 DM355_MCBSP0_BFSX,
149 DM355_MCBSP0_BDR,
150 DM355_MCBSP0_R,
151 DM355_MCBSP0_BFSR,
152
153 /* SPI0 */
154 DM355_SPI0_SDI,
155 DM355_SPI0_SDENA0,
156 DM355_SPI0_SDENA1,
157
158 /* IRQ muxing */
159 DM355_INT_EDMA_CC,
160 DM355_INT_EDMA_TC0_ERR,
161 DM355_INT_EDMA_TC1_ERR,
162
163 /* EDMA event muxing */
164 DM355_EVT8_ASP1_TX,
165 DM355_EVT9_ASP1_RX,
166 DM355_EVT26_MMC0_RX,
167};
168
169#ifdef CONFIG_DAVINCI_MUX
170/* setup pin muxing */
171extern void davinci_mux_init(void);
172extern int davinci_mux_register(const struct mux_config *pins,
173 unsigned long size);
174extern int davinci_cfg_reg(unsigned long reg_cfg);
175#else
176/* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */
177static inline void davinci_mux_init(void) {}
178static inline int davinci_mux_register(const struct mux_config *pins,
179 unsigned long size) { return 0; }
180static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; }
181#endif
182
183#endif /* __INC_MACH_MUX_H */
diff --git a/arch/arm/mach-davinci/mux.c b/arch/arm/mach-davinci/mux.c
index 53734dee1f9..bbba0b247a4 100644
--- a/arch/arm/mach-davinci/mux.c
+++ b/arch/arm/mach-davinci/mux.c
@@ -1,42 +1,103 @@
1/* 1/*
2 * DaVinci pin multiplexing configurations 2 * Utility to set the DAVINCI MUX register from a table in mux.h
3 * 3 *
4 * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com> 4 * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
5 * 5 *
6 * Based on linux/arch/arm/plat-omap/mux.c:
7 * Copyright (C) 2003 - 2005 Nokia Corporation
8 *
9 * Written by Tony Lindgren
10 *
6 * 2007 (c) MontaVista Software, Inc. This file is licensed under 11 * 2007 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program 12 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express 13 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied. 14 * or implied.
15 *
16 * Copyright (C) 2008 Texas Instruments.
10 */ 17 */
11#include <linux/io.h> 18#include <linux/io.h>
19#include <linux/module.h>
12#include <linux/spinlock.h> 20#include <linux/spinlock.h>
13 21
14#include <mach/hardware.h> 22#include <mach/hardware.h>
15
16#include <mach/mux.h> 23#include <mach/mux.h>
17 24
18/* System control register offsets */ 25static const struct mux_config *mux_table;
19#define PINMUX0 0x00 26static unsigned long pin_table_sz;
20#define PINMUX1 0x04 27
28int __init davinci_mux_register(const struct mux_config *pins,
29 unsigned long size)
30{
31 mux_table = pins;
32 pin_table_sz = size;
21 33
22static DEFINE_SPINLOCK(mux_lock); 34 return 0;
35}
23 36
24void davinci_mux_peripheral(unsigned int mux, unsigned int enable) 37/*
38 * Sets the DAVINCI MUX register based on the table
39 */
40int __init_or_module davinci_cfg_reg(const unsigned long index)
25{ 41{
42 static DEFINE_SPINLOCK(mux_spin_lock);
26 void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE); 43 void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE);
27 u32 pinmux, muxreg = PINMUX0; 44 unsigned long flags;
45 const struct mux_config *cfg;
46 unsigned int reg_orig = 0, reg = 0;
47 unsigned int mask, warn = 0;
48
49 if (!mux_table)
50 BUG();
51
52 if (index >= pin_table_sz) {
53 printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
54 index, pin_table_sz);
55 dump_stack();
56 return -ENODEV;
57 }
58
59 cfg = &mux_table[index];
60
61 if (cfg->name == NULL) {
62 printk(KERN_ERR "No entry for the specified index\n");
63 return -ENODEV;
64 }
65
66 /* Update the mux register in question */
67 if (cfg->mask) {
68 unsigned tmp1, tmp2;
69
70 spin_lock_irqsave(&mux_spin_lock, flags);
71 reg_orig = __raw_readl(base + cfg->mux_reg);
72
73 mask = (cfg->mask << cfg->mask_offset);
74 tmp1 = reg_orig & mask;
75 reg = reg_orig & ~mask;
76
77 tmp2 = (cfg->mode << cfg->mask_offset);
78 reg |= tmp2;
79
80 if (tmp1 != tmp2)
81 warn = 1;
82
83 __raw_writel(reg, base + cfg->mux_reg);
84 spin_unlock_irqrestore(&mux_spin_lock, flags);
85 }
86
87 if (warn) {
88#ifdef CONFIG_DAVINCI_MUX_WARNINGS
89 printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
90#endif
91 }
28 92
29 if (mux >= DAVINCI_MUX_LEVEL2) { 93#ifdef CONFIG_DAVINCI_MUX_DEBUG
30 muxreg = PINMUX1; 94 if (cfg->debug || warn) {
31 mux -= DAVINCI_MUX_LEVEL2; 95 printk(KERN_WARNING "MUX: Setting register %s\n", cfg->name);
96 printk(KERN_WARNING " %s (0x%08x) = 0x%08x -> 0x%08x\n",
97 cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
32 } 98 }
99#endif
33 100
34 spin_lock(&mux_lock); 101 return 0;
35 pinmux = __raw_readl(base + muxreg);
36 if (enable)
37 pinmux |= (1 << mux);
38 else
39 pinmux &= ~(1 << mux);
40 __raw_writel(pinmux, base + muxreg);
41 spin_unlock(&mux_lock);
42} 102}
103EXPORT_SYMBOL(davinci_cfg_reg);
diff --git a/arch/arm/mach-davinci/mux.h b/arch/arm/mach-davinci/mux.h
new file mode 100644
index 00000000000..adc86941337
--- /dev/null
+++ b/arch/arm/mach-davinci/mux.h
@@ -0,0 +1,51 @@
1/*
2 * Pin-multiplex helper macros for TI DaVinci family devices
3 *
4 * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
5 *
6 * 2007 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 *
11 * Copyright (C) 2008 Texas Instruments.
12 */
13#ifndef _MACH_DAVINCI_MUX_H_
14#define _MACH_DAVINCI_MUX_H_
15
16#include <mach/mux.h>
17
18#define MUX_CFG(soc, desc, muxreg, mode_offset, mode_mask, mux_mode, dbg)\
19[soc##_##desc] = { \
20 .name = #desc, \
21 .debug = dbg, \
22 .mux_reg_name = "PINMUX"#muxreg, \
23 .mux_reg = PINMUX##muxreg, \
24 .mask_offset = mode_offset, \
25 .mask = mode_mask, \
26 .mode = mux_mode, \
27 },
28
29#define INT_CFG(soc, desc, mode_offset, mode_mask, mux_mode, dbg) \
30[soc##_##desc] = { \
31 .name = #desc, \
32 .debug = dbg, \
33 .mux_reg_name = "INTMUX", \
34 .mux_reg = INTMUX, \
35 .mask_offset = mode_offset, \
36 .mask = mode_mask, \
37 .mode = mux_mode, \
38 },
39
40#define EVT_CFG(soc, desc, mode_offset, mode_mask, mux_mode, dbg) \
41[soc##_##desc] = { \
42 .name = #desc, \
43 .debug = dbg, \
44 .mux_reg_name = "EVTMUX", \
45 .mux_reg = EVTMUX, \
46 .mask_offset = mode_offset, \
47 .mask = mode_mask, \
48 .mode = mux_mode, \
49 },
50
51#endif /* _MACH_DAVINCI_MUX_H */