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authorShawn Guo <shawn.guo@linaro.org>2012-08-22 09:36:30 -0400
committerShawn Guo <shawn.guo@linaro.org>2012-09-11 02:45:46 -0400
commit53f9443da63db38212e784b0aa205881168757aa (patch)
tree36e142fcd0d290d8a1e1efeffe736ddb476c42dc
parentb598b9f311a604ca533033baa5afcf45beb037d9 (diff)
clk: mxs: replace imx23 clk_register_clkdev with clock DT lookup
It really becomes a maintenance issue that every time a device needs to look up (clk_get) a clock we have to patch kernel clock file to call clk_register_clkdev for that clock. Since clock DT support which is meant to resolve clock lookup in device tree is in place, the patch moves imx23 client devices' clock lookup over to device tree, so that any new lookup to be added at later time can just get done in DT instead of kernel. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
-rw-r--r--Documentation/devicetree/bindings/clock/imx23-clock.txt76
-rw-r--r--arch/arm/boot/dts/imx23.dtsi16
-rw-r--r--drivers/clk/mxs/clk-imx23.c55
3 files changed, 100 insertions, 47 deletions
diff --git a/Documentation/devicetree/bindings/clock/imx23-clock.txt b/Documentation/devicetree/bindings/clock/imx23-clock.txt
new file mode 100644
index 00000000000..a0b867ef8d9
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx23-clock.txt
@@ -0,0 +1,76 @@
1* Clock bindings for Freescale i.MX23
2
3Required properties:
4- compatible: Should be "fsl,imx23-clkctrl"
5- reg: Address and length of the register set
6- #clock-cells: Should be <1>
7
8The clock consumer should specify the desired clock by having the clock
9ID in its "clocks" phandle cell. The following is a full list of i.MX23
10clocks and IDs.
11
12 Clock ID
13 ------------------
14 ref_xtal 0
15 pll 1
16 ref_cpu 2
17 ref_emi 3
18 ref_pix 4
19 ref_io 5
20 saif_sel 6
21 lcdif_sel 7
22 gpmi_sel 8
23 ssp_sel 9
24 emi_sel 10
25 cpu 11
26 etm_sel 12
27 cpu_pll 13
28 cpu_xtal 14
29 hbus 15
30 xbus 16
31 lcdif_div 17
32 ssp_div 18
33 gpmi_div 19
34 emi_pll 20
35 emi_xtal 21
36 etm_div 22
37 saif_div 23
38 clk32k_div 24
39 rtc 25
40 adc 26
41 spdif_div 27
42 clk32k 28
43 dri 29
44 pwm 30
45 filt 31
46 uart 32
47 ssp 33
48 gpmi 34
49 spdif 35
50 emi 36
51 saif 37
52 lcdif 38
53 etm 39
54 usb 40
55 usb_pwr 41
56
57Examples:
58
59clks: clkctrl@80040000 {
60 compatible = "fsl,imx23-clkctrl";
61 reg = <0x80040000 0x2000>;
62 #clock-cells = <1>;
63 clock-output-names =
64 ...
65 "uart", /* 32 */
66 ...
67 "end_of_list";
68};
69
70auart0: serial@8006c000 {
71 compatible = "fsl,imx23-auart";
72 reg = <0x8006c000 0x2000>;
73 interrupts = <24 25 23>;
74 clocks = <&clks 32>;
75 status = "disabled";
76};
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index b00f3cfb3bf..9d0e803e3ec 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -52,6 +52,7 @@
52 dma-apbh@80004000 { 52 dma-apbh@80004000 {
53 compatible = "fsl,imx23-dma-apbh"; 53 compatible = "fsl,imx23-dma-apbh";
54 reg = <0x80004000 0x2000>; 54 reg = <0x80004000 0x2000>;
55 clocks = <&clks 15>;
55 }; 56 };
56 57
57 ecc@80008000 { 58 ecc@80008000 {
@@ -67,6 +68,7 @@
67 reg-names = "gpmi-nand", "bch"; 68 reg-names = "gpmi-nand", "bch";
68 interrupts = <13>, <56>; 69 interrupts = <13>, <56>;
69 interrupt-names = "gpmi-dma", "bch"; 70 interrupt-names = "gpmi-dma", "bch";
71 clocks = <&clks 34>;
70 fsl,gpmi-dma-channel = <4>; 72 fsl,gpmi-dma-channel = <4>;
71 status = "disabled"; 73 status = "disabled";
72 }; 74 };
@@ -74,6 +76,7 @@
74 ssp0: ssp@80010000 { 76 ssp0: ssp@80010000 {
75 reg = <0x80010000 0x2000>; 77 reg = <0x80010000 0x2000>;
76 interrupts = <15 14>; 78 interrupts = <15 14>;
79 clocks = <&clks 33>;
77 fsl,ssp-dma-channel = <1>; 80 fsl,ssp-dma-channel = <1>;
78 status = "disabled"; 81 status = "disabled";
79 }; 82 };
@@ -290,6 +293,7 @@
290 dma-apbx@80024000 { 293 dma-apbx@80024000 {
291 compatible = "fsl,imx23-dma-apbx"; 294 compatible = "fsl,imx23-dma-apbx";
292 reg = <0x80024000 0x2000>; 295 reg = <0x80024000 0x2000>;
296 clocks = <&clks 16>;
293 }; 297 };
294 298
295 dcp@80028000 { 299 dcp@80028000 {
@@ -316,12 +320,14 @@
316 compatible = "fsl,imx23-lcdif"; 320 compatible = "fsl,imx23-lcdif";
317 reg = <0x80030000 2000>; 321 reg = <0x80030000 2000>;
318 interrupts = <46 45>; 322 interrupts = <46 45>;
323 clocks = <&clks 38>;
319 status = "disabled"; 324 status = "disabled";
320 }; 325 };
321 326
322 ssp1: ssp@80034000 { 327 ssp1: ssp@80034000 {
323 reg = <0x80034000 0x2000>; 328 reg = <0x80034000 0x2000>;
324 interrupts = <2 20>; 329 interrupts = <2 20>;
330 clocks = <&clks 33>;
325 fsl,ssp-dma-channel = <2>; 331 fsl,ssp-dma-channel = <2>;
326 status = "disabled"; 332 status = "disabled";
327 }; 333 };
@@ -339,9 +345,10 @@
339 reg = <0x80040000 0x40000>; 345 reg = <0x80040000 0x40000>;
340 ranges; 346 ranges;
341 347
342 clkctl@80040000 { 348 clks: clkctrl@80040000 {
349 compatible = "fsl,imx23-clkctrl";
343 reg = <0x80040000 0x2000>; 350 reg = <0x80040000 0x2000>;
344 status = "disabled"; 351 #clock-cells = <1>;
345 }; 352 };
346 353
347 saif0: saif@80042000 { 354 saif0: saif@80042000 {
@@ -393,6 +400,7 @@
393 pwm: pwm@80064000 { 400 pwm: pwm@80064000 {
394 compatible = "fsl,imx23-pwm"; 401 compatible = "fsl,imx23-pwm";
395 reg = <0x80064000 0x2000>; 402 reg = <0x80064000 0x2000>;
403 clocks = <&clks 30>;
396 #pwm-cells = <2>; 404 #pwm-cells = <2>;
397 fsl,pwm-number = <5>; 405 fsl,pwm-number = <5>;
398 status = "disabled"; 406 status = "disabled";
@@ -407,6 +415,7 @@
407 compatible = "fsl,imx23-auart"; 415 compatible = "fsl,imx23-auart";
408 reg = <0x8006c000 0x2000>; 416 reg = <0x8006c000 0x2000>;
409 interrupts = <24 25 23>; 417 interrupts = <24 25 23>;
418 clocks = <&clks 32>;
410 status = "disabled"; 419 status = "disabled";
411 }; 420 };
412 421
@@ -414,6 +423,7 @@
414 compatible = "fsl,imx23-auart"; 423 compatible = "fsl,imx23-auart";
415 reg = <0x8006e000 0x2000>; 424 reg = <0x8006e000 0x2000>;
416 interrupts = <59 60 58>; 425 interrupts = <59 60 58>;
426 clocks = <&clks 32>;
417 status = "disabled"; 427 status = "disabled";
418 }; 428 };
419 429
@@ -421,6 +431,8 @@
421 compatible = "arm,pl011", "arm,primecell"; 431 compatible = "arm,pl011", "arm,primecell";
422 reg = <0x80070000 0x2000>; 432 reg = <0x80070000 0x2000>;
423 interrupts = <0>; 433 interrupts = <0>;
434 clocks = <&clks 32>, <&clks 16>;
435 clock-names = "uart", "apb_pclk";
424 status = "disabled"; 436 status = "disabled";
425 }; 437 };
426 438
diff --git a/drivers/clk/mxs/clk-imx23.c b/drivers/clk/mxs/clk-imx23.c
index 844043ad0fe..9f6d15546cb 100644
--- a/drivers/clk/mxs/clk-imx23.c
+++ b/drivers/clk/mxs/clk-imx23.c
@@ -14,6 +14,7 @@
14#include <linux/err.h> 14#include <linux/err.h>
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/of.h>
17#include <mach/common.h> 18#include <mach/common.h>
18#include <mach/mx23.h> 19#include <mach/mx23.h>
19#include "clk.h" 20#include "clk.h"
@@ -71,44 +72,6 @@ static void __init clk_misc_init(void)
71 __mxs_setl(30 << BP_FRAC_IOFRAC, FRAC); 72 __mxs_setl(30 << BP_FRAC_IOFRAC, FRAC);
72} 73}
73 74
74static struct clk_lookup uart_lookups[] = {
75 { .dev_id = "duart", },
76 { .dev_id = "mxs-auart.0", },
77 { .dev_id = "mxs-auart.1", },
78 { .dev_id = "8006c000.serial", },
79 { .dev_id = "8006e000.serial", },
80 { .dev_id = "80070000.serial", },
81};
82
83static struct clk_lookup hbus_lookups[] = {
84 { .dev_id = "imx23-dma-apbh", },
85 { .dev_id = "80004000.dma-apbh", },
86};
87
88static struct clk_lookup xbus_lookups[] = {
89 { .dev_id = "duart", .con_id = "apb_pclk"},
90 { .dev_id = "80070000.serial", .con_id = "apb_pclk"},
91 { .dev_id = "imx23-dma-apbx", },
92 { .dev_id = "80024000.dma-apbx", },
93};
94
95static struct clk_lookup ssp_lookups[] = {
96 { .dev_id = "imx23-mmc.0", },
97 { .dev_id = "imx23-mmc.1", },
98 { .dev_id = "80010000.ssp", },
99 { .dev_id = "80034000.ssp", },
100};
101
102static struct clk_lookup lcdif_lookups[] = {
103 { .dev_id = "imx23-fb", },
104 { .dev_id = "80030000.lcdif", },
105};
106
107static struct clk_lookup gpmi_lookups[] = {
108 { .dev_id = "imx23-gpmi-nand", },
109 { .dev_id = "8000c000.gpmi-nand", },
110};
111
112static const char *sel_pll[] __initconst = { "pll", "ref_xtal", }; 75static const char *sel_pll[] __initconst = { "pll", "ref_xtal", };
113static const char *sel_cpu[] __initconst = { "ref_cpu", "ref_xtal", }; 76static const char *sel_cpu[] __initconst = { "ref_cpu", "ref_xtal", };
114static const char *sel_pix[] __initconst = { "ref_pix", "ref_xtal", }; 77static const char *sel_pix[] __initconst = { "ref_pix", "ref_xtal", };
@@ -127,6 +90,7 @@ enum imx23_clk {
127}; 90};
128 91
129static struct clk *clks[clk_max]; 92static struct clk *clks[clk_max];
93static struct clk_onecell_data clk_data;
130 94
131static enum imx23_clk clks_init_on[] __initdata = { 95static enum imx23_clk clks_init_on[] __initdata = {
132 cpu, hbus, xbus, emi, uart, 96 cpu, hbus, xbus, emi, uart,
@@ -134,6 +98,7 @@ static enum imx23_clk clks_init_on[] __initdata = {
134 98
135int __init mx23_clocks_init(void) 99int __init mx23_clocks_init(void)
136{ 100{
101 struct device_node *np;
137 int i; 102 int i;
138 103
139 clk_misc_init(); 104 clk_misc_init();
@@ -188,14 +153,14 @@ int __init mx23_clocks_init(void)
188 return PTR_ERR(clks[i]); 153 return PTR_ERR(clks[i]);
189 } 154 }
190 155
156 np = of_find_compatible_node(NULL, NULL, "fsl,imx23-clkctrl");
157 if (np) {
158 clk_data.clks = clks;
159 clk_data.clk_num = ARRAY_SIZE(clks);
160 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
161 }
162
191 clk_register_clkdev(clks[clk32k], NULL, "timrot"); 163 clk_register_clkdev(clks[clk32k], NULL, "timrot");
192 clk_register_clkdev(clks[pwm], NULL, "80064000.pwm");
193 clk_register_clkdevs(clks[hbus], hbus_lookups, ARRAY_SIZE(hbus_lookups));
194 clk_register_clkdevs(clks[xbus], xbus_lookups, ARRAY_SIZE(xbus_lookups));
195 clk_register_clkdevs(clks[uart], uart_lookups, ARRAY_SIZE(uart_lookups));
196 clk_register_clkdevs(clks[ssp], ssp_lookups, ARRAY_SIZE(ssp_lookups));
197 clk_register_clkdevs(clks[gpmi], gpmi_lookups, ARRAY_SIZE(gpmi_lookups));
198 clk_register_clkdevs(clks[lcdif], lcdif_lookups, ARRAY_SIZE(lcdif_lookups));
199 164
200 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) 165 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
201 clk_prepare_enable(clks[clks_init_on[i]]); 166 clk_prepare_enable(clks[clks_init_on[i]]);