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authorManuel Lauss <manuel.lauss@googlemail.com>2011-12-08 05:42:15 -0500
committerRalf Baechle <ralf@linux-mips.org>2011-12-08 05:42:15 -0500
commit4d2216afeeaa1571f7608107f41cdb2ac6fe30b1 (patch)
treef71ab537c628ea368d4af1672ce579ab772a38c9
parentb67a1a02d463b5b298cc718ca971738fe20f0ab9 (diff)
MIPS: Alchemy: remove unused board headers
The information in those headers is no longer necessary. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2876/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat
-rw-r--r--arch/mips/alchemy/Platform3
-rw-r--r--arch/mips/include/asm/mach-db1x00/db1x00.h63
-rw-r--r--arch/mips/include/asm/mach-pb1x00/pb1550.h73
3 files changed, 0 insertions, 139 deletions
diff --git a/arch/mips/alchemy/Platform b/arch/mips/alchemy/Platform
index 33f80e8cbd6..7956274de15 100644
--- a/arch/mips/alchemy/Platform
+++ b/arch/mips/alchemy/Platform
@@ -8,21 +8,18 @@ platform-$(CONFIG_MIPS_ALCHEMY) += alchemy/common/
8# AMD Alchemy Pb1100 eval board 8# AMD Alchemy Pb1100 eval board
9# 9#
10platform-$(CONFIG_MIPS_PB1100) += alchemy/devboards/ 10platform-$(CONFIG_MIPS_PB1100) += alchemy/devboards/
11cflags-$(CONFIG_MIPS_PB1100) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
12load-$(CONFIG_MIPS_PB1100) += 0xffffffff80100000 11load-$(CONFIG_MIPS_PB1100) += 0xffffffff80100000
13 12
14# 13#
15# AMD Alchemy Pb1500 eval board 14# AMD Alchemy Pb1500 eval board
16# 15#
17platform-$(CONFIG_MIPS_PB1500) += alchemy/devboards/ 16platform-$(CONFIG_MIPS_PB1500) += alchemy/devboards/
18cflags-$(CONFIG_MIPS_PB1500) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
19load-$(CONFIG_MIPS_PB1500) += 0xffffffff80100000 17load-$(CONFIG_MIPS_PB1500) += 0xffffffff80100000
20 18
21# 19#
22# AMD Alchemy Pb1550 eval board 20# AMD Alchemy Pb1550 eval board
23# 21#
24platform-$(CONFIG_MIPS_PB1550) += alchemy/devboards/ 22platform-$(CONFIG_MIPS_PB1550) += alchemy/devboards/
25cflags-$(CONFIG_MIPS_PB1550) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
26load-$(CONFIG_MIPS_PB1550) += 0xffffffff80100000 23load-$(CONFIG_MIPS_PB1550) += 0xffffffff80100000
27 24
28# 25#
diff --git a/arch/mips/include/asm/mach-db1x00/db1x00.h b/arch/mips/include/asm/mach-db1x00/db1x00.h
deleted file mode 100644
index 51f1ebf0df9..00000000000
--- a/arch/mips/include/asm/mach-db1x00/db1x00.h
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * AMD Alchemy DBAu1x00 Reference Boards
3 *
4 * Copyright 2001, 2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. <source@mvista.com>
6 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
7 *
8 * ########################################################################
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
22 *
23 * ########################################################################
24 *
25 *
26 */
27#ifndef __ASM_DB1X00_H
28#define __ASM_DB1X00_H
29
30#include <asm/mach-au1x00/au1xxx_psc.h>
31
32/*
33 * NAND defines
34 *
35 * Timing values as described in databook, * ns value stripped of the
36 * lower 2 bits.
37 * These defines are here rather than an Au1550 generic file because
38 * the parts chosen on another board may be different and may require
39 * different timings.
40 */
41#define NAND_T_H (18 >> 2)
42#define NAND_T_PUL (30 >> 2)
43#define NAND_T_SU (30 >> 2)
44#define NAND_T_WH (30 >> 2)
45
46/* Bitfield shift amounts */
47#define NAND_T_H_SHIFT 0
48#define NAND_T_PUL_SHIFT 4
49#define NAND_T_SU_SHIFT 8
50#define NAND_T_WH_SHIFT 12
51
52#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
53 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
54 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
55 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
56#define NAND_CS 1
57
58/* Should be done by YAMON */
59#define NAND_STCFG 0x00400005 /* 8-bit NAND */
60#define NAND_STTIME 0x00007774 /* valid for 396 MHz SD=2 only */
61#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
62
63#endif /* __ASM_DB1X00_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1550.h b/arch/mips/include/asm/mach-pb1x00/pb1550.h
deleted file mode 100644
index 443b88adebf..00000000000
--- a/arch/mips/include/asm/mach-pb1x00/pb1550.h
+++ /dev/null
@@ -1,73 +0,0 @@
1/*
2 * AMD Alchemy Semi PB1550 Reference Board
3 * Board Registers defines.
4 *
5 * Copyright 2004 Embedded Edge LLC.
6 * Copyright 2005 Ralf Baechle (ralf@linux-mips.org)
7 *
8 * ########################################################################
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
22 *
23 * ########################################################################
24 *
25 *
26 */
27#ifndef __ASM_PB1550_H
28#define __ASM_PB1550_H
29
30#include <linux/types.h>
31#include <asm/mach-au1x00/au1xxx_psc.h>
32
33#define DBDMA_AC97_TX_CHAN AU1550_DSCR_CMD0_PSC1_TX
34#define DBDMA_AC97_RX_CHAN AU1550_DSCR_CMD0_PSC1_RX
35#define DBDMA_I2S_TX_CHAN AU1550_DSCR_CMD0_PSC3_TX
36#define DBDMA_I2S_RX_CHAN AU1550_DSCR_CMD0_PSC3_RX
37
38#define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR
39#define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR
40#define SMBUS_PSC_BASE AU1550_PSC2_PHYS_ADDR
41#define I2S_PSC_BASE AU1550_PSC3_PHYS_ADDR
42
43/*
44 * Timing values as described in databook, * ns value stripped of
45 * lower 2 bits.
46 * These defines are here rather than an SOC1550 generic file because
47 * the parts chosen on another board may be different and may require
48 * different timings.
49 */
50#define NAND_T_H (18 >> 2)
51#define NAND_T_PUL (30 >> 2)
52#define NAND_T_SU (30 >> 2)
53#define NAND_T_WH (30 >> 2)
54
55/* Bitfield shift amounts */
56#define NAND_T_H_SHIFT 0
57#define NAND_T_PUL_SHIFT 4
58#define NAND_T_SU_SHIFT 8
59#define NAND_T_WH_SHIFT 12
60
61#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
62 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
63 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
64 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
65
66#define NAND_CS 1
67
68/* Should be done by YAMON */
69#define NAND_STCFG 0x00400005 /* 8-bit NAND */
70#define NAND_STTIME 0x00007774 /* valid for 396 MHz SD=2 only */
71#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
72
73#endif /* __ASM_PB1550_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-21 18:04:09 -0400