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authorRussell King <rmk+kernel@arm.linux.org.uk>2012-05-21 10:15:33 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2012-05-21 10:15:33 -0400
commit4ab1056766a4e49f6b9ef324313dd1583f8f8f4e (patch)
tree89f975e7e021dd27dc807e45445e963aeb39fcda
parent4175160b065e74572819a320dcd34129224a4e1c (diff)
parent4cdfc2ec72e940abb4322aa1bc14f43a1486fc5d (diff)
Merge branch 'v3-removal' into for-linus
Conflicts: arch/arm/boot/compressed/head.S
Diffstat
-rw-r--r--arch/arm/Makefile2
-rw-r--r--arch/arm/boot/compressed/head.S44
-rw-r--r--arch/arm/configs/rpc_defconfig2
-rw-r--r--arch/arm/include/asm/glue-df.h8
-rw-r--r--arch/arm/include/asm/glue-proc.h18
-rw-r--r--arch/arm/include/asm/page.h9
-rw-r--r--arch/arm/include/asm/tlbflush.h21
-rw-r--r--arch/arm/kernel/entry-armv.S4
-rw-r--r--arch/arm/kernel/entry-common.S28
-rw-r--r--arch/arm/lib/Makefile23
-rw-r--r--arch/arm/lib/io-readsw-armv3.S106
-rw-r--r--arch/arm/lib/io-writesw-armv3.S126
-rw-r--r--arch/arm/lib/uaccess.S564
-rw-r--r--arch/arm/mm/Kconfig46
-rw-r--r--arch/arm/mm/Makefile4
-rw-r--r--arch/arm/mm/copypage-v3.c81
-rw-r--r--arch/arm/mm/fault.c3
-rw-r--r--arch/arm/mm/proc-arm6_7.S327
-rw-r--r--arch/arm/mm/tlb-v3.S48
19 files changed, 10 insertions, 1454 deletions
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 047a20780fc..aaf96bccd4a 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -70,8 +70,6 @@ arch-$(CONFIG_CPU_32v4) :=-D__LINUX_ARM_ARCH__=4 -march=armv4
70arch-$(CONFIG_CPU_32v3) :=-D__LINUX_ARM_ARCH__=3 -march=armv3 70arch-$(CONFIG_CPU_32v3) :=-D__LINUX_ARM_ARCH__=3 -march=armv3
71 71
72# This selects how we optimise for the processor. 72# This selects how we optimise for the processor.
73tune-$(CONFIG_CPU_ARM610) :=-mtune=arm610
74tune-$(CONFIG_CPU_ARM710) :=-mtune=arm710
75tune-$(CONFIG_CPU_ARM7TDMI) :=-mtune=arm7tdmi 73tune-$(CONFIG_CPU_ARM7TDMI) :=-mtune=arm7tdmi
76tune-$(CONFIG_CPU_ARM720T) :=-mtune=arm7tdmi 74tune-$(CONFIG_CPU_ARM720T) :=-mtune=arm7tdmi
77tune-$(CONFIG_CPU_ARM740T) :=-mtune=arm7tdmi 75tune-$(CONFIG_CPU_ARM740T) :=-mtune=arm7tdmi
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 5ad33a4df67..b8c64b80baf 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -686,19 +686,6 @@ __fa526_cache_on:
686 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB 686 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
687 mov pc, r12 687 mov pc, r12
688 688
689__arm6_mmu_cache_on:
690 mov r12, lr
691 mov r6, #CB_BITS | 0x12 @ U
692 bl __setup_mmu
693 mov r0, #0
694 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
695 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
696 mov r0, #0x30
697 bl __common_mmu_cache_on
698 mov r0, #0
699 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
700 mov pc, r12
701
702__common_mmu_cache_on: 689__common_mmu_cache_on:
703#ifndef CONFIG_THUMB2_KERNEL 690#ifndef CONFIG_THUMB2_KERNEL
704#ifndef DEBUG 691#ifndef DEBUG
@@ -763,16 +750,6 @@ call_cache_fn: adr r12, proc_types
763 .align 2 750 .align 2
764 .type proc_types,#object 751 .type proc_types,#object
765proc_types: 752proc_types:
766 .word 0x41560600 @ ARM6/610
767 .word 0xffffffe0
768 W(b) __arm6_mmu_cache_off @ works, but slow
769 W(b) __arm6_mmu_cache_off
770 mov pc, lr
771 THUMB( nop )
772@ b __arm6_mmu_cache_on @ untested
773@ b __arm6_mmu_cache_off
774@ b __armv3_mmu_cache_flush
775
776 .word 0x00000000 @ old ARM ID 753 .word 0x00000000 @ old ARM ID
777 .word 0x0000f000 754 .word 0x0000f000
778 mov pc, lr 755 mov pc, lr
@@ -784,8 +761,10 @@ proc_types:
784 761
785 .word 0x41007000 @ ARM7/710 762 .word 0x41007000 @ ARM7/710
786 .word 0xfff8fe00 763 .word 0xfff8fe00
787 W(b) __arm7_mmu_cache_off 764 mov pc, lr
788 W(b) __arm7_mmu_cache_off 765 THUMB( nop )
766 mov pc, lr
767 THUMB( nop )
789 mov pc, lr 768 mov pc, lr
790 THUMB( nop ) 769 THUMB( nop )
791 770
@@ -984,21 +963,6 @@ __armv7_mmu_cache_off:
984 mcr p15, 0, r0, c7, c5, 4 @ ISB 963 mcr p15, 0, r0, c7, c5, 4 @ ISB
985 mov pc, r12 964 mov pc, r12
986 965
987__arm6_mmu_cache_off:
988 mov r0, #0x00000030 @ ARM6 control reg.
989 b __armv3_mmu_cache_off
990
991__arm7_mmu_cache_off:
992 mov r0, #0x00000070 @ ARM7 control reg.
993 b __armv3_mmu_cache_off
994
995__armv3_mmu_cache_off:
996 mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off
997 mov r0, #0
998 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
999 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
1000 mov pc, lr
1001
1002/* 966/*
1003 * Clean and flush the cache to maintain consistency. 967 * Clean and flush the cache to maintain consistency.
1004 * 968 *
diff --git a/arch/arm/configs/rpc_defconfig b/arch/arm/configs/rpc_defconfig
index af278f7a224..00515ef9782 100644
--- a/arch/arm/configs/rpc_defconfig
+++ b/arch/arm/configs/rpc_defconfig
@@ -8,8 +8,6 @@ CONFIG_MODULES=y
8CONFIG_MODULE_UNLOAD=y 8CONFIG_MODULE_UNLOAD=y
9# CONFIG_BLK_DEV_BSG is not set 9# CONFIG_BLK_DEV_BSG is not set
10CONFIG_ARCH_RPC=y 10CONFIG_ARCH_RPC=y
11CONFIG_CPU_ARM610=y
12CONFIG_CPU_ARM710=y
13CONFIG_CPU_SA110=y 11CONFIG_CPU_SA110=y
14CONFIG_ZBOOT_ROM_TEXT=0x0 12CONFIG_ZBOOT_ROM_TEXT=0x0
15CONFIG_ZBOOT_ROM_BSS=0x0 13CONFIG_ZBOOT_ROM_BSS=0x0
diff --git a/arch/arm/include/asm/glue-df.h b/arch/arm/include/asm/glue-df.h
index 354d571e8bc..8cacbcda76d 100644
--- a/arch/arm/include/asm/glue-df.h
+++ b/arch/arm/include/asm/glue-df.h
@@ -31,14 +31,6 @@
31#undef CPU_DABORT_HANDLER 31#undef CPU_DABORT_HANDLER
32#undef MULTI_DABORT 32#undef MULTI_DABORT
33 33
34#if defined(CONFIG_CPU_ARM610)
35# ifdef CPU_DABORT_HANDLER
36# define MULTI_DABORT 1
37# else
38# define CPU_DABORT_HANDLER cpu_arm6_data_abort
39# endif
40#endif
41
42#if defined(CONFIG_CPU_ARM710) 34#if defined(CONFIG_CPU_ARM710)
43# ifdef CPU_DABORT_HANDLER 35# ifdef CPU_DABORT_HANDLER
44# define MULTI_DABORT 1 36# define MULTI_DABORT 1
diff --git a/arch/arm/include/asm/glue-proc.h b/arch/arm/include/asm/glue-proc.h
index e2be7f14266..ac1dd54724b 100644
--- a/arch/arm/include/asm/glue-proc.h
+++ b/arch/arm/include/asm/glue-proc.h
@@ -23,15 +23,6 @@
23 * CPU_NAME - the prefix for CPU related functions 23 * CPU_NAME - the prefix for CPU related functions
24 */ 24 */
25 25
26#ifdef CONFIG_CPU_ARM610
27# ifdef CPU_NAME
28# undef MULTI_CPU
29# define MULTI_CPU
30# else
31# define CPU_NAME cpu_arm6
32# endif
33#endif
34
35#ifdef CONFIG_CPU_ARM7TDMI 26#ifdef CONFIG_CPU_ARM7TDMI
36# ifdef CPU_NAME 27# ifdef CPU_NAME
37# undef MULTI_CPU 28# undef MULTI_CPU
@@ -41,15 +32,6 @@
41# endif 32# endif
42#endif 33#endif
43 34
44#ifdef CONFIG_CPU_ARM710
45# ifdef CPU_NAME
46# undef MULTI_CPU
47# define MULTI_CPU
48# else
49# define CPU_NAME cpu_arm7
50# endif
51#endif
52
53#ifdef CONFIG_CPU_ARM720T 35#ifdef CONFIG_CPU_ARM720T
54# ifdef CPU_NAME 36# ifdef CPU_NAME
55# undef MULTI_CPU 37# undef MULTI_CPU
diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h
index 5838361c48b..ecf901902e4 100644
--- a/arch/arm/include/asm/page.h
+++ b/arch/arm/include/asm/page.h
@@ -34,7 +34,6 @@
34 * processor(s) we're building for. 34 * processor(s) we're building for.
35 * 35 *
36 * We have the following to choose from: 36 * We have the following to choose from:
37 * v3 - ARMv3
38 * v4wt - ARMv4 with writethrough cache, without minicache 37 * v4wt - ARMv4 with writethrough cache, without minicache
39 * v4wb - ARMv4 with writeback cache, without minicache 38 * v4wb - ARMv4 with writeback cache, without minicache
40 * v4_mc - ARMv4 with minicache 39 * v4_mc - ARMv4 with minicache
@@ -44,14 +43,6 @@
44#undef _USER 43#undef _USER
45#undef MULTI_USER 44#undef MULTI_USER
46 45
47#ifdef CONFIG_CPU_COPY_V3
48# ifdef _USER
49# define MULTI_USER 1
50# else
51# define _USER v3
52# endif
53#endif
54
55#ifdef CONFIG_CPU_COPY_V4WT 46#ifdef CONFIG_CPU_COPY_V4WT
56# ifdef _USER 47# ifdef _USER
57# define MULTI_USER 1 48# define MULTI_USER 1
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index 85fe61e7320..6e924d3a77e 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -65,21 +65,6 @@
65#define MULTI_TLB 1 65#define MULTI_TLB 1
66#endif 66#endif
67 67
68#define v3_tlb_flags (TLB_V3_FULL | TLB_V3_PAGE)
69
70#ifdef CONFIG_CPU_TLB_V3
71# define v3_possible_flags v3_tlb_flags
72# define v3_always_flags v3_tlb_flags
73# ifdef _TLB
74# define MULTI_TLB 1
75# else
76# define _TLB v3
77# endif
78#else
79# define v3_possible_flags 0
80# define v3_always_flags (-1UL)
81#endif
82
83#define v4_tlb_flags (TLB_V4_U_FULL | TLB_V4_U_PAGE) 68#define v4_tlb_flags (TLB_V4_U_FULL | TLB_V4_U_PAGE)
84 69
85#ifdef CONFIG_CPU_TLB_V4WT 70#ifdef CONFIG_CPU_TLB_V4WT
@@ -298,8 +283,7 @@ extern struct cpu_tlb_fns cpu_tlb;
298 * implemented the "%?" method, but this has been discontinued due to too 283 * implemented the "%?" method, but this has been discontinued due to too
299 * many people getting it wrong. 284 * many people getting it wrong.
300 */ 285 */
301#define possible_tlb_flags (v3_possible_flags | \ 286#define possible_tlb_flags (v4_possible_flags | \
302 v4_possible_flags | \
303 v4wbi_possible_flags | \ 287 v4wbi_possible_flags | \
304 fr_possible_flags | \ 288 fr_possible_flags | \
305 v4wb_possible_flags | \ 289 v4wb_possible_flags | \
@@ -307,8 +291,7 @@ extern struct cpu_tlb_fns cpu_tlb;
307 v6wbi_possible_flags | \ 291 v6wbi_possible_flags | \
308 v7wbi_possible_flags) 292 v7wbi_possible_flags)
309 293
310#define always_tlb_flags (v3_always_flags & \ 294#define always_tlb_flags (v4_always_flags & \
311 v4_always_flags & \
312 v4wbi_always_flags & \ 295 v4wbi_always_flags & \
313 fr_always_flags & \ 296 fr_always_flags & \
314 v4wb_always_flags & \ 297 v4wb_always_flags & \
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 7fd3ad048da..437f0c42651 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -556,10 +556,6 @@ call_fpe:
556#endif 556#endif
557 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 557 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
558 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 558 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
559#if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
560 and r8, r0, #0x0f000000 @ mask out op-code bits
561 teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)?
562#endif
563 moveq pc, lr 559 moveq pc, lr
564 get_thread_info r10 @ get current thread 560 get_thread_info r10 @ get current thread
565 and r8, r0, #0x00000f00 @ mask out CP number 561 and r8, r0, #0x00000f00 @ mask out CP number
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 54ee265dd81..7bd2d3cb895 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -335,20 +335,6 @@ ENDPROC(ftrace_stub)
335 *----------------------------------------------------------------------------- 335 *-----------------------------------------------------------------------------
336 */ 336 */
337 337
338 /* If we're optimising for StrongARM the resulting code won't
339 run on an ARM7 and we can save a couple of instructions.
340 --pb */
341#ifdef CONFIG_CPU_ARM710
342#define A710(code...) code
343.Larm710bug:
344 ldmia sp, {r0 - lr}^ @ Get calling r0 - lr
345 mov r0, r0
346 add sp, sp, #S_FRAME_SIZE
347 subs pc, lr, #4
348#else
349#define A710(code...)
350#endif
351
352 .align 5 338 .align 5
353ENTRY(vector_swi) 339ENTRY(vector_swi)
354 sub sp, sp, #S_FRAME_SIZE 340 sub sp, sp, #S_FRAME_SIZE
@@ -379,9 +365,6 @@ ENTRY(vector_swi)
379 ldreq r10, [lr, #-4] @ get SWI instruction 365 ldreq r10, [lr, #-4] @ get SWI instruction
380#else 366#else
381 ldr r10, [lr, #-4] @ get SWI instruction 367 ldr r10, [lr, #-4] @ get SWI instruction
382 A710( and ip, r10, #0x0f000000 @ check for SWI )
383 A710( teq ip, #0x0f000000 )
384 A710( bne .Larm710bug )
385#endif 368#endif
386#ifdef CONFIG_CPU_ENDIAN_BE8 369#ifdef CONFIG_CPU_ENDIAN_BE8
387 rev r10, r10 @ little endian instruction 370 rev r10, r10 @ little endian instruction
@@ -392,26 +375,15 @@ ENTRY(vector_swi)
392 /* 375 /*
393 * Pure EABI user space always put syscall number into scno (r7). 376 * Pure EABI user space always put syscall number into scno (r7).
394 */ 377 */
395 A710( ldr ip, [lr, #-4] @ get SWI instruction )
396 A710( and ip, ip, #0x0f000000 @ check for SWI )
397 A710( teq ip, #0x0f000000 )
398 A710( bne .Larm710bug )
399
400#elif defined(CONFIG_ARM_THUMB) 378#elif defined(CONFIG_ARM_THUMB)
401
402 /* Legacy ABI only, possibly thumb mode. */ 379 /* Legacy ABI only, possibly thumb mode. */
403 tst r8, #PSR_T_BIT @ this is SPSR from save_user_regs 380 tst r8, #PSR_T_BIT @ this is SPSR from save_user_regs
404 addne scno, r7, #__NR_SYSCALL_BASE @ put OS number in 381 addne scno, r7, #__NR_SYSCALL_BASE @ put OS number in
405 ldreq scno, [lr, #-4] 382 ldreq scno, [lr, #-4]
406 383
407#else 384#else
408
409 /* Legacy ABI only. */ 385 /* Legacy ABI only. */
410 ldr scno, [lr, #-4] @ get SWI instruction 386 ldr scno, [lr, #-4] @ get SWI instruction
411 A710( and ip, scno, #0x0f000000 @ check for SWI )
412 A710( teq ip, #0x0f000000 )
413 A710( bne .Larm710bug )
414
415#endif 387#endif
416 388
417#ifdef CONFIG_ALIGNMENT_TRAP 389#ifdef CONFIG_ALIGNMENT_TRAP
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 0ade0acc1ed..992769ae259 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -17,30 +17,13 @@ lib-y := backtrace.o changebit.o csumipv6.o csumpartial.o \
17 call_with_stack.o 17 call_with_stack.o
18 18
19mmu-y := clear_user.o copy_page.o getuser.o putuser.o 19mmu-y := clear_user.o copy_page.o getuser.o putuser.o
20 20mmu-y += copy_from_user.o copy_to_user.o
21# the code in uaccess.S is not preemption safe and
22# probably faster on ARMv3 only
23ifeq ($(CONFIG_PREEMPT),y)
24 mmu-y += copy_from_user.o copy_to_user.o
25else
26ifneq ($(CONFIG_CPU_32v3),y)
27 mmu-y += copy_from_user.o copy_to_user.o
28else
29 mmu-y += uaccess.o
30endif
31endif
32 21
33# using lib_ here won't override already available weak symbols 22# using lib_ here won't override already available weak symbols
34obj-$(CONFIG_UACCESS_WITH_MEMCPY) += uaccess_with_memcpy.o 23obj-$(CONFIG_UACCESS_WITH_MEMCPY) += uaccess_with_memcpy.o
35 24
36lib-$(CONFIG_MMU) += $(mmu-y) 25lib-$(CONFIG_MMU) += $(mmu-y)
37 26lib-y += io-readsw-armv4.o io-writesw-armv4.o
38ifeq ($(CONFIG_CPU_32v3),y)
39 lib-y += io-readsw-armv3.o io-writesw-armv3.o
40else
41 lib-y += io-readsw-armv4.o io-writesw-armv4.o
42endif
43
44lib-$(CONFIG_ARCH_RPC) += ecard.o io-acorn.o floppydma.o 27lib-$(CONFIG_ARCH_RPC) += ecard.o io-acorn.o floppydma.o
45lib-$(CONFIG_ARCH_SHARK) += io-shark.o 28lib-$(CONFIG_ARCH_SHARK) += io-shark.o
46 29
diff --git a/arch/arm/lib/io-readsw-armv3.S b/arch/arm/lib/io-readsw-armv3.S
deleted file mode 100644
index 88487c8c4f2..00000000000
--- a/arch/arm/lib/io-readsw-armv3.S
+++ /dev/null
@@ -1,106 +0,0 @@
1/*
2 * linux/arch/arm/lib/io-readsw-armv3.S
3 *
4 * Copyright (C) 1995-2000 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/linkage.h>
11#include <asm/assembler.h>
12
13.Linsw_bad_alignment:
14 adr r0, .Linsw_bad_align_msg
15 mov r2, lr
16 b panic
17.Linsw_bad_align_msg:
18 .asciz "insw: bad buffer alignment (0x%p, lr=0x%08lX)\n"
19 .align
20
21.Linsw_align: tst r1, #1
22 bne .Linsw_bad_alignment
23
24 ldr r3, [r0]
25 strb r3, [r1], #1
26 mov r3, r3, lsr #8
27 strb r3, [r1], #1
28
29 subs r2, r2, #1
30 moveq pc, lr
31
32ENTRY(__raw_readsw)
33 teq r2, #0 @ do we have to check for the zero len?
34 moveq pc, lr
35 tst r1, #3
36 bne .Linsw_align
37
38.Linsw_aligned: mov ip, #0xff
39 orr ip, ip, ip, lsl #8
40 stmfd sp!, {r4, r5, r6, lr}
41
42 subs r2, r2, #8
43 bmi .Lno_insw_8
44
45.Linsw_8_lp: ldr r3, [r0]
46 and r3, r3, ip
47 ldr r4, [r0]
48 orr r3, r3, r4, lsl #16
49
50 ldr r4, [r0]
51 and r4, r4, ip
52 ldr r5, [r0]
53 orr r4, r4, r5, lsl #16
54
55 ldr r5, [r0]
56 and r5, r5, ip
57 ldr r6, [r0]
58 orr r5, r5, r6, lsl #16
59
60 ldr r6, [r0]
61 and r6, r6, ip
62 ldr lr, [r0]
63 orr r6, r6, lr, lsl #16
64
65 stmia r1!, {r3 - r6}
66
67 subs r2, r2, #8
68 bpl .Linsw_8_lp
69
70 tst r2, #7
71 ldmeqfd sp!, {r4, r5, r6, pc}
72
73.Lno_insw_8: tst r2, #4
74 beq .Lno_insw_4
75
76 ldr r3, [r0]
77 and r3, r3, ip
78 ldr r4, [r0]
79 orr r3, r3, r4, lsl #16
80
81 ldr r4, [r0]
82 and r4, r4, ip
83 ldr r5, [r0]
84 orr r4, r4, r5, lsl #16
85
86 stmia r1!, {r3, r4}
87
88.Lno_insw_4: tst r2, #2
89 beq .Lno_insw_2
90
91 ldr r3, [r0]
92 and r3, r3, ip
93 ldr r4, [r0]
94 orr r3, r3, r4, lsl #16
95
96 str r3, [r1], #4
97
98.Lno_insw_2: tst r2, #1
99 ldrne r3, [r0]
100 strneb r3, [r1], #1
101 movne r3, r3, lsr #8
102 strneb r3, [r1]
103
104 ldmfd sp!, {r4, r5, r6, pc}
105
106
diff --git a/arch/arm/lib/io-writesw-armv3.S b/arch/arm/lib/io-writesw-armv3.S
deleted file mode 100644
index 49b800419e3..00000000000
--- a/arch/arm/lib/io-writesw-armv3.S
+++ /dev/null
@@ -1,126 +0,0 @@
1/*
2 * linux/arch/arm/lib/io-writesw-armv3.S
3 *
4 * Copyright (C) 1995-2000 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/linkage.h>
11#include <asm/assembler.h>
12
13.Loutsw_bad_alignment:
14 adr r0, .Loutsw_bad_align_msg
15 mov r2, lr
16 b panic
17.Loutsw_bad_align_msg:
18 .asciz "outsw: bad buffer alignment (0x%p, lr=0x%08lX)\n"
19 .align
20
21.Loutsw_align: tst r1, #1
22 bne .Loutsw_bad_alignment
23
24 add r1, r1, #2
25
26 ldr r3, [r1, #-4]
27 mov r3, r3, lsr #16
28 orr r3, r3, r3, lsl #16
29 str r3, [r0]
30 subs r2, r2, #1
31 moveq pc, lr
32
33ENTRY(__raw_writesw)
34 teq r2, #0 @ do we have to check for the zero len?
35 moveq pc, lr
36 tst r1, #3
37 bne .Loutsw_align
38
39 stmfd sp!, {r4, r5, r6, lr}
40
41 subs r2, r2, #8
42 bmi .Lno_outsw_8
43
44.Loutsw_8_lp: ldmia r1!, {r3, r4, r5, r6}
45
46 mov ip, r3, lsl #16
47 orr ip, ip, ip, lsr #16
48 str ip, [r0]
49
50 mov ip, r3, lsr #16
51 orr ip, ip, ip, lsl #16
52 str ip, [r0]
53
54 mov ip, r4, lsl #16
55 orr ip, ip, ip, lsr #16
56 str ip, [r0]
57
58 mov ip, r4, lsr #16
59 orr ip, ip, ip, lsl #16
60 str ip, [r0]
61
62 mov ip, r5, lsl #16
63 orr ip, ip, ip, lsr #16
64 str ip, [r0]
65
66 mov ip, r5, lsr #16
67 orr ip, ip, ip, lsl #16
68 str ip, [r0]
69
70 mov ip, r6, lsl #16
71 orr ip, ip, ip, lsr #16
72 str ip, [r0]
73
74 mov ip, r6, lsr #16
75 orr ip, ip, ip, lsl #16
76 str ip, [r0]
77
78 subs r2, r2, #8
79 bpl .Loutsw_8_lp
80
81 tst r2, #7
82 ldmeqfd sp!, {r4, r5, r6, pc}
83
84.Lno_outsw_8: tst r2, #4
85 beq .Lno_outsw_4
86
87 ldmia r1!, {r3, r4}
88
89 mov ip, r3, lsl #16
90 orr ip, ip, ip, lsr #16
91 str ip, [r0]
92
93 mov ip, r3, lsr #16
94 orr ip, ip, ip, lsl #16
95 str ip, [r0]
96
97 mov ip, r4, lsl #16
98 orr ip, ip, ip, lsr #16
99 str ip, [r0]
100
101 mov ip, r4, lsr #16
102 orr ip, ip, ip, lsl #16
103 str ip, [r0]
104
105.Lno_outsw_4: tst r2, #2
106 beq .Lno_outsw_2
107
108 ldr r3, [r1], #4
109
110 mov ip, r3, lsl #16
111 orr ip, ip, ip, lsr #16
112 str ip, [r0]
113
114 mov ip, r3, lsr #16
115 orr ip, ip, ip, lsl #16
116 str ip, [r0]
117
118.Lno_outsw_2: tst r2, #1
119
120 ldrne r3, [r1]
121
122 movne ip, r3, lsl #16
123 orrne ip, ip, ip, lsr #16
124 strne ip, [r0]
125
126 ldmfd sp!, {r4, r5, r6, pc}
diff --git a/arch/arm/lib/uaccess.S b/arch/arm/lib/uaccess.S
deleted file mode 100644
index 5c908b1cb8e..00000000000
--- a/arch/arm/lib/uaccess.S
+++ /dev/null
@@ -1,564 +0,0 @@
1/*
2 * linux/arch/arm/lib/uaccess.S
3 *
4 * Copyright (C) 1995, 1996,1997,1998 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Routines to block copy data to/from user memory
11 * These are highly optimised both for the 4k page size
12 * and for various alignments.
13 */
14#include <linux/linkage.h>
15#include <asm/assembler.h>
16#include <asm/errno.h>
17#include <asm/domain.h>
18
19 .text
20
21#define PAGE_SHIFT 12
22
23/* Prototype: int __copy_to_user(void *to, const char *from, size_t n)
24 * Purpose : copy a block to user memory from kernel memory
25 * Params : to - user memory
26 * : from - kernel memory
27 * : n - number of bytes to copy
28 * Returns : Number of bytes NOT copied.
29 */
30
31.Lc2u_dest_not_aligned:
32 rsb ip, ip, #4
33 cmp ip, #2
34 ldrb r3, [r1], #1
35USER( TUSER( strb) r3, [r0], #1) @ May fault
36 ldrgeb r3, [r1], #1
37USER( TUSER( strgeb) r3, [r0], #1) @ May fault
38 ldrgtb r3, [r1], #1
39USER( TUSER( strgtb) r3, [r0], #1) @ May fault
40 sub r2, r2, ip
41 b .Lc2u_dest_aligned
42
43ENTRY(__copy_to_user)
44 stmfd sp!, {r2, r4 - r7, lr}
45 cmp r2, #4
46 blt .Lc2u_not_enough
47 ands ip, r0, #3
48 bne .Lc2u_dest_not_aligned
49.Lc2u_dest_aligned:
50
51 ands ip, r1, #3
52 bne .Lc2u_src_not_aligned
53/*
54 * Seeing as there has to be at least 8 bytes to copy, we can
55 * copy one word, and force a user-mode page fault...
56 */
57
58.Lc2u_0fupi: subs r2, r2, #4
59 addmi ip, r2, #4
60 bmi .Lc2u_0nowords
61 ldr r3, [r1], #4
62USER( TUSER( str) r3, [r0], #4) @ May fault
63 mov ip, r0, lsl #32 - PAGE_SHIFT @ On each page, use a ld/st??t instruction
64 rsb ip, ip, #0
65 movs ip, ip, lsr #32 - PAGE_SHIFT
66 beq .Lc2u_0fupi
67/*
68 * ip = max no. of bytes to copy before needing another "strt" insn
69 */
70 cmp r2, ip
71 movlt ip, r2
72 sub r2, r2, ip
73 subs ip, ip, #32
74 blt .Lc2u_0rem8lp
75
76.Lc2u_0cpy8lp: ldmia r1!, {r3 - r6}
77 stmia r0!, {r3 - r6} @ Shouldnt fault
78 ldmia r1!, {r3 - r6}
79 subs ip, ip, #32
80 stmia r0!, {r3 - r6} @ Shouldnt fault
81 bpl .Lc2u_0cpy8lp
82
83.Lc2u_0rem8lp: cmn ip, #16
84 ldmgeia r1!, {r3 - r6}
85 stmgeia r0!, {r3 - r6} @ Shouldnt fault
86 tst ip, #8
87 ldmneia r1!, {r3 - r4}
88 stmneia r0!, {r3 - r4} @ Shouldnt fault
89 tst ip, #4
90 ldrne r3, [r1], #4
91 TUSER( strne) r3, [r0], #4 @ Shouldnt fault
92 ands ip, ip, #3
93 beq .Lc2u_0fupi
94.Lc2u_0nowords: teq ip, #0
95 beq .Lc2u_finished
96.Lc2u_nowords: cmp ip, #2
97 ldrb r3, [r1], #1
98USER( TUSER( strb) r3, [r0], #1) @ May fault
99 ldrgeb r3, [r1], #1
100USER( TUSER( strgeb) r3, [r0], #1) @ May fault
101 ldrgtb r3, [r1], #1
102USER( TUSER( strgtb) r3, [r0], #1) @ May fault
103 b .Lc2u_finished
104
105.Lc2u_not_enough:
106 movs ip, r2
107 bne .Lc2u_nowords
108.Lc2u_finished: mov r0, #0
109 ldmfd sp!, {r2, r4 - r7, pc}
110
111.Lc2u_src_not_aligned:
112 bic r1, r1, #3
113 ldr r7, [r1], #4
114 cmp ip, #2
115 bgt .Lc2u_3fupi
116 beq .Lc2u_2fupi
117.Lc2u_1fupi: subs r2, r2, #4
118 addmi ip, r2, #4
119 bmi .Lc2u_1nowords
120 mov r3, r7, pull #8
121 ldr r7, [r1], #4
122 orr r3, r3, r7, push #24
123USER( TUSER( str) r3, [r0], #4) @ May fault
124 mov ip, r0, lsl #32 - PAGE_SHIFT
125 rsb ip, ip, #0
126 movs ip, ip, lsr #32 - PAGE_SHIFT
127 beq .Lc2u_1fupi
128 cmp r2, ip
129 movlt ip, r2
130 sub r2, r2, ip
131 subs ip, ip, #16
132 blt .Lc2u_1rem8lp
133
134.Lc2u_1cpy8lp: mov r3, r7, pull #8
135 ldmia r1!, {r4 - r7}
136 subs ip, ip, #16
137 orr r3, r3, r4, push #24
138 mov r4, r4, pull #8
139 orr r4, r4, r5, push #24
140 mov r5, r5, pull #8
141 orr r5, r5, r6, push #24
142 mov r6, r6, pull #8
143 orr r6, r6, r7, push #24
144 stmia r0!, {r3 - r6} @ Shouldnt fault
145 bpl .Lc2u_1cpy8lp
146
147.Lc2u_1rem8lp: tst ip, #8
148 movne r3, r7, pull #8
149 ldmneia r1!, {r4, r7}
150 orrne r3, r3, r4, push #24
151 movne r4, r4, pull #8
152 orrne r4, r4, r7, push #24
153 stmneia r0!, {r3 - r4} @ Shouldnt fault
154 tst ip, #4
155 movne r3, r7, pull #8
156 ldrne r7, [r1], #4
157 orrne r3, r3, r7, push #24
158 TUSER( strne) r3, [r0], #4 @ Shouldnt fault
159 ands ip, ip, #3
160 beq .Lc2u_1fupi
161.Lc2u_1nowords: mov r3, r7, get_byte_1
162 teq ip, #0
163 beq .Lc2u_finished
164 cmp ip, #2
165USER( TUSER( strb) r3, [r0], #1) @ May fault
166 movge r3, r7, get_byte_2
167USER( TUSER( strgeb) r3, [r0], #1) @ May fault
168 movgt r3, r7, get_byte_3
169USER( TUSER( strgtb) r3, [r0], #1) @ May fault
170 b .Lc2u_finished
171
172.Lc2u_2fupi: subs r2, r2, #4
173 addmi ip, r2, #4
174 bmi .Lc2u_2nowords
175 mov r3, r7, pull #16
176 ldr r7, [r1], #4
177 orr r3, r3, r7, push #16
178USER( TUSER( str) r3, [r0], #4) @ May fault
179 mov ip, r0, lsl #32 - PAGE_SHIFT
180 rsb ip, ip, #0
181 movs ip, ip, lsr #32 - PAGE_SHIFT
182 beq .Lc2u_2fupi
183 cmp r2, ip
184 movlt ip, r2
185 sub r2, r2, ip
186 subs ip, ip, #16
187 blt .Lc2u_2rem8lp
188
189.Lc2u_2cpy8lp: mov r3, r7, pull #16
190 ldmia r1!, {r4 - r7}
191 subs ip, ip, #16
192 orr r3, r3, r4, push #16
193 mov r4, r4, pull #16
194 orr r4, r4, r5, push #16
195 mov r5, r5, pull #16
196 orr r5, r5, r6, push #16
197 mov r6, r6, pull #16
198 orr r6, r6, r7, push #16
199 stmia r0!, {r3 - r6} @ Shouldnt fault
200 bpl .Lc2u_2cpy8lp
201
202.Lc2u_2rem8lp: tst ip, #8
203 movne r3, r7, pull #16
204 ldmneia r1!, {r4, r7}
205 orrne r3, r3, r4, push #16
206 movne r4, r4, pull #16
207 orrne r4, r4, r7, push #16
208 stmneia r0!, {r3 - r4} @ Shouldnt fault
209 tst ip, #4
210 movne r3, r7, pull #16
211 ldrne r7, [r1], #4
212 orrne r3, r3, r7, push #16
213 TUSER( strne) r3, [r0], #4 @ Shouldnt fault
214 ands ip, ip, #3
215 beq .Lc2u_2fupi
216.Lc2u_2nowords: mov r3, r7, get_byte_2
217 teq ip, #0
218 beq .Lc2u_finished
219 cmp ip, #2
220USER( TUSER( strb) r3, [r0], #1) @ May fault
221 movge r3, r7, get_byte_3
222USER( TUSER( strgeb) r3, [r0], #1) @ May fault
223 ldrgtb r3, [r1], #0
224USER( TUSER( strgtb) r3, [r0], #1) @ May fault
225 b .Lc2u_finished
226
227.Lc2u_3fupi: subs r2, r2, #4
228 addmi ip, r2, #4
229 bmi .Lc2u_3nowords
230 mov r3, r7, pull #24
231 ldr r7, [r1], #4
232 orr r3, r3, r7, push #8
233USER( TUSER( str) r3, [r0], #4) @ May fault
234 mov ip, r0, lsl #32 - PAGE_SHIFT
235 rsb ip, ip, #0
236 movs ip, ip, lsr #32 - PAGE_SHIFT
237 beq .Lc2u_3fupi
238 cmp r2, ip
239 movlt ip, r2
240 sub r2, r2, ip
241 subs ip, ip, #16
242 blt .Lc2u_3rem8lp
243
244.Lc2u_3cpy8lp: mov r3, r7, pull #24
245 ldmia r1!, {r4 - r7}
246 subs ip, ip, #16
247 orr r3, r3, r4, push #8
248 mov r4, r4, pull #24
249 orr r4, r4, r5, push #8
250 mov r5, r5, pull #24
251 orr r5, r5, r6, push #8
252 mov r6, r6, pull #24
253 orr r6, r6, r7, push #8
254 stmia r0!, {r3 - r6} @ Shouldnt fault
255 bpl .Lc2u_3cpy8lp
256
257.Lc2u_3rem8lp: tst ip, #8
258 movne r3, r7, pull #24
259 ldmneia r1!, {r4, r7}
260 orrne r3, r3, r4, push #8
261 movne r4, r4, pull #24
262 orrne r4, r4, r7, push #8
263 stmneia r0!, {r3 - r4} @ Shouldnt fault
264 tst ip, #4
265 movne r3, r7, pull #24
266 ldrne r7, [r1], #4
267 orrne r3, r3, r7, push #8
268 TUSER( strne) r3, [r0], #4 @ Shouldnt fault
269 ands ip, ip, #3
270 beq .Lc2u_3fupi
271.Lc2u_3nowords: mov r3, r7, get_byte_3
272 teq ip, #0
273 beq .Lc2u_finished
274 cmp ip, #2
275USER( TUSER( strb) r3, [r0], #1) @ May fault
276 ldrgeb r3, [r1], #1
277USER( TUSER( strgeb) r3, [r0], #1) @ May fault
278 ldrgtb r3, [r1], #0
279USER( TUSER( strgtb) r3, [r0], #1) @ May fault
280 b .Lc2u_finished
281ENDPROC(__copy_to_user)
282
283 .pushsection .fixup,"ax"
284 .align 0
2859001: ldmfd sp!, {r0, r4 - r7, pc}
286 .popsection
287
288/* Prototype: unsigned long __copy_from_user(void *to,const void *from,unsigned long n);
289 * Purpose : copy a block from user memory to kernel memory
290 * Params : to - kernel memory
291 * : from - user memory
292 * : n - number of bytes to copy
293 * Returns : Number of bytes NOT copied.
294 */
295.Lcfu_dest_not_aligned:
296 rsb ip, ip, #4
297 cmp ip, #2
298USER( TUSER( ldrb) r3, [r1], #1) @ May fault
299 strb r3, [r0], #1
300USER( TUSER( ldrgeb) r3, [r1], #1) @ May fault
301 strgeb r3, [r0], #1
302USER( TUSER( ldrgtb) r3, [r1], #1) @ May fault
303 strgtb r3, [r0], #1
304 sub r2, r2, ip
305 b .Lcfu_dest_aligned
306
307ENTRY(__copy_from_user)
308 stmfd sp!, {r0, r2, r4 - r7, lr}
309 cmp r2, #4
310 blt .Lcfu_not_enough
311 ands ip, r0, #3
312 bne .Lcfu_dest_not_aligned
313.Lcfu_dest_aligned:
314 ands ip, r1, #3
315 bne .Lcfu_src_not_aligned
316
317/*
318 * Seeing as there has to be at least 8 bytes to copy, we can
319 * copy one word, and force a user-mode page fault...
320 */
321
322.Lcfu_0fupi: subs r2, r2, #4
323 addmi ip, r2, #4
324 bmi .Lcfu_0nowords
325USER( TUSER( ldr) r3, [r1], #4)
326 str r3, [r0], #4
327 mov ip, r1, lsl #32 - PAGE_SHIFT @ On each page, use a ld/st??t instruction
328 rsb ip, ip, #0
329 movs ip, ip, lsr #32 - PAGE_SHIFT
330 beq .Lcfu_0fupi
331/*
332 * ip = max no. of bytes to copy before needing another "strt" insn
333 */
334 cmp r2, ip
335 movlt ip, r2
336 sub r2, r2, ip
337 subs ip, ip, #32
338 blt .Lcfu_0rem8lp
339
340.Lcfu_0cpy8lp: ldmia r1!, {r3 - r6} @ Shouldnt fault
341 stmia r0!, {r3 - r6}
342 ldmia r1!, {r3 - r6} @ Shouldnt fault
343 subs ip, ip, #32
344 stmia r0!, {r3 - r6}
345 bpl .Lcfu_0cpy8lp
346
347.Lcfu_0rem8lp: cmn ip, #16
348 ldmgeia r1!, {r3 - r6} @ Shouldnt fault
349 stmgeia r0!, {r3 - r6}
350 tst ip, #8
351 ldmneia r1!, {r3 - r4} @ Shouldnt fault
352 stmneia r0!, {r3 - r4}
353 tst ip, #4
354 TUSER( ldrne) r3, [r1], #4 @ Shouldnt fault
355 strne r3, [r0], #4
356 ands ip, ip, #3
357 beq .Lcfu_0fupi
358.Lcfu_0nowords: teq ip, #0
359 beq .Lcfu_finished
360.Lcfu_nowords: cmp ip, #2
361USER( TUSER( ldrb) r3, [r1], #1) @ May fault
362 strb r3, [r0], #1
363USER( TUSER( ldrgeb) r3, [r1], #1) @ May fault
364 strgeb r3, [r0], #1
365USER( TUSER( ldrgtb) r3, [r1], #1) @ May fault
366 strgtb r3, [r0], #1
367 b .Lcfu_finished
368
369.Lcfu_not_enough:
370 movs ip, r2
371 bne .Lcfu_nowords
372.Lcfu_finished: mov r0, #0
373 add sp, sp, #8
374 ldmfd sp!, {r4 - r7, pc}
375
376.Lcfu_src_not_aligned:
377 bic r1, r1, #3
378USER( TUSER( ldr) r7, [r1], #4) @ May fault
379 cmp ip, #2
380 bgt .Lcfu_3fupi
381 beq .Lcfu_2fupi
382.Lcfu_1fupi: subs r2, r2, #4
383 addmi ip, r2, #4
384 bmi .Lcfu_1nowords
385 mov r3, r7, pull #8
386USER( TUSER( ldr) r7, [r1], #4) @ May fault
387 orr r3, r3, r7, push #24
388 str r3, [r0], #4
389 mov ip, r1, lsl #32 - PAGE_SHIFT
390 rsb ip, ip, #0
391 movs ip, ip, lsr #32 - PAGE_SHIFT
392 beq .Lcfu_1fupi
393 cmp r2, ip
394 movlt ip, r2
395 sub r2, r2, ip
396 subs ip, ip, #16
397 blt .Lcfu_1rem8lp
398
399.Lcfu_1cpy8lp: mov r3, r7, pull #8
400 ldmia r1!, {r4 - r7} @ Shouldnt fault
401 subs ip, ip, #16
402 orr r3, r3, r4, push #24
403 mov r4, r4, pull #8
404 orr r4, r4, r5, push #24
405 mov r5, r5, pull #8
406 orr r5, r5, r6, push #24
407 mov r6, r6, pull #8
408 orr r6, r6, r7, push #24
409 stmia r0!, {r3 - r6}
410 bpl .Lcfu_1cpy8lp
411
412.Lcfu_1rem8lp: tst ip, #8
413 movne r3, r7, pull #8
414 ldmneia r1!, {r4, r7} @ Shouldnt fault
415 orrne r3, r3, r4, push #24
416 movne r4, r4, pull #8
417 orrne r4, r4, r7, push #24
418 stmneia r0!, {r3 - r4}
419 tst ip, #4
420 movne r3, r7, pull #8
421USER( TUSER( ldrne) r7, [r1], #4) @ May fault
422 orrne r3, r3, r7, push #24
423 strne r3, [r0], #4
424 ands ip, ip, #3
425 beq .Lcfu_1fupi
426.Lcfu_1nowords: mov r3, r7, get_byte_1
427 teq ip, #0
428 beq .Lcfu_finished
429 cmp ip, #2
430 strb r3, [r0], #1
431 movge r3, r7, get_byte_2
432 strgeb r3, [r0], #1
433 movgt r3, r7, get_byte_3
434 strgtb r3, [r0], #1
435 b .Lcfu_finished
436
437.Lcfu_2fupi: subs r2, r2, #4
438 addmi ip, r2, #4
439 bmi .Lcfu_2nowords
440 mov r3, r7, pull #16
441USER( TUSER( ldr) r7, [r1], #4) @ May fault
442 orr r3, r3, r7, push #16
443 str r3, [r0], #4
444 mov ip, r1, lsl #32 - PAGE_SHIFT
445 rsb ip, ip, #0
446 movs ip, ip, lsr #32 - PAGE_SHIFT
447 beq .Lcfu_2fupi
448 cmp r2, ip
449 movlt ip, r2
450 sub r2, r2, ip
451 subs ip, ip, #16
452 blt .Lcfu_2rem8lp
453
454
455.Lcfu_2cpy8lp: mov r3, r7, pull #16
456 ldmia r1!, {r4 - r7} @ Shouldnt fault
457 subs ip, ip, #16
458 orr r3, r3, r4, push #16
459 mov r4, r4, pull #16
460 orr r4, r4, r5, push #16
461 mov r5, r5, pull #16
462 orr r5, r5, r6, push #16
463 mov r6, r6, pull #16
464 orr r6, r6, r7, push #16
465 stmia r0!, {r3 - r6}
466 bpl .Lcfu_2cpy8lp
467
468.Lcfu_2rem8lp: tst ip, #8
469 movne r3, r7, pull #16
470 ldmneia r1!, {r4, r7} @ Shouldnt fault
471 orrne r3, r3, r4, push #16
472 movne r4, r4, pull #16
473 orrne r4, r4, r7, push #16
474 stmneia r0!, {r3 - r4}
475 tst ip, #4
476 movne r3, r7, pull #16
477USER( TUSER( ldrne) r7, [r1], #4) @ May fault
478 orrne r3, r3, r7, push #16
479 strne r3, [r0], #4
480 ands ip, ip, #3
481 beq .Lcfu_2fupi
482.Lcfu_2nowords: mov r3, r7, get_byte_2
483 teq ip, #0
484 beq .Lcfu_finished
485 cmp ip, #2
486 strb r3, [r0], #1
487 movge r3, r7, get_byte_3
488 strgeb r3, [r0], #1
489USER( TUSER( ldrgtb) r3, [r1], #0) @ May fault
490 strgtb r3, [r0], #1
491 b .Lcfu_finished
492
493.Lcfu_3fupi: subs r2, r2, #4
494 addmi ip, r2, #4
495 bmi .Lcfu_3nowords
496 mov r3, r7, pull #24
497USER( TUSER( ldr) r7, [r1], #4) @ May fault
498 orr r3, r3, r7, push #8
499 str r3, [r0], #4
500 mov ip, r1, lsl #32 - PAGE_SHIFT
501 rsb ip, ip, #0
502 movs ip, ip, lsr #32 - PAGE_SHIFT
503 beq .Lcfu_3fupi
504 cmp r2, ip
505 movlt ip, r2
506 sub r2, r2, ip
507 subs ip, ip, #16
508 blt .Lcfu_3rem8lp
509
510.Lcfu_3cpy8lp: mov r3, r7, pull #24
511 ldmia r1!, {r4 - r7} @ Shouldnt fault
512 orr r3, r3, r4, push #8
513 mov r4, r4, pull #24
514 orr r4, r4, r5, push #8
515 mov r5, r5, pull #24
516 orr r5, r5, r6, push #8
517 mov r6, r6, pull #24
518 orr r6, r6, r7, push #8
519 stmia r0!, {r3 - r6}
520 subs ip, ip, #16
521 bpl .Lcfu_3cpy8lp
522
523.Lcfu_3rem8lp: tst ip, #8
524 movne r3, r7, pull #24
525 ldmneia r1!, {r4, r7} @ Shouldnt fault
526 orrne r3, r3, r4, push #8
527 movne r4, r4, pull #24
528 orrne r4, r4, r7, push #8
529 stmneia r0!, {r3 - r4}
530 tst ip, #4
531 movne r3, r7, pull #24
532USER( TUSER( ldrne) r7, [r1], #4) @ May fault
533 orrne r3, r3, r7, push #8
534 strne r3, [r0], #4
535 ands ip, ip, #3
536 beq .Lcfu_3fupi
537.Lcfu_3nowords: mov r3, r7, get_byte_3
538 teq ip, #0
539 beq .Lcfu_finished
540 cmp ip, #2
541 strb r3, [r0], #1
542USER( TUSER( ldrgeb) r3, [r1], #1) @ May fault
543 strgeb r3, [r0], #1
544USER( TUSER( ldrgtb) r3, [r1], #1) @ May fault
545 strgtb r3, [r0], #1
546 b .Lcfu_finished
547ENDPROC(__copy_from_user)
548
549 .pushsection .fixup,"ax"
550 .align 0
551 /*
552 * We took an exception. r0 contains a pointer to
553 * the byte not copied.
554 */
5559001: ldr r2, [sp], #4 @ void *to
556 sub r2, r0, r2 @ bytes copied
557 ldr r1, [sp], #4 @ unsigned long count
558 subs r4, r1, r2 @ bytes left to copy
559 movne r1, r4
560 blne __memzero
561 mov r0, r4
562 ldmfd sp!, {r4 - r7, pc}
563 .popsection
564
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 7c8a7d8467b..101b9681c08 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -4,23 +4,6 @@ comment "Processor Type"
4# which CPUs we support in the kernel image, and the compiler instruction 4# which CPUs we support in the kernel image, and the compiler instruction
5# optimiser behaviour. 5# optimiser behaviour.
6 6
7# ARM610
8config CPU_ARM610
9 bool "Support ARM610 processor" if ARCH_RPC
10 select CPU_32v3
11 select CPU_CACHE_V3
12 select CPU_CACHE_VIVT
13 select CPU_CP15_MMU
14 select CPU_COPY_V3 if MMU
15 select CPU_TLB_V3 if MMU
16 select CPU_PABRT_LEGACY
17 help
18 The ARM610 is the successor to the ARM3 processor
19 and was produced by VLSI Technology Inc.
20
21 Say Y if you want support for the ARM610 processor.
22 Otherwise, say N.
23
24# ARM7TDMI 7# ARM7TDMI
25config CPU_ARM7TDMI 8config CPU_ARM7TDMI
26 bool "Support ARM7TDMI processor" 9 bool "Support ARM7TDMI processor"
@@ -36,25 +19,6 @@ config CPU_ARM7TDMI
36 Say Y if you want support for the ARM7TDMI processor. 19 Say Y if you want support for the ARM7TDMI processor.
37 Otherwise, say N. 20 Otherwise, say N.
38 21
39# ARM710
40config CPU_ARM710
41 bool "Support ARM710 processor" if ARCH_RPC
42 select CPU_32v3
43 select CPU_CACHE_V3
44 select CPU_CACHE_VIVT
45 select CPU_CP15_MMU
46 select CPU_COPY_V3 if MMU
47 select CPU_TLB_V3 if MMU
48 select CPU_PABRT_LEGACY
49 help
50 A 32-bit RISC microprocessor based on the ARM7 processor core
51 designed by Advanced RISC Machines Ltd. The ARM710 is the
52 successor to the ARM610 processor. It was released in
53 July 1994 by VLSI Technology Inc.
54
55 Say Y if you want support for the ARM710 processor.
56 Otherwise, say N.
57
58# ARM720T 22# ARM720T
59config CPU_ARM720T 23config CPU_ARM720T
60 bool "Support ARM720T processor" if ARCH_INTEGRATOR 24 bool "Support ARM720T processor" if ARCH_INTEGRATOR
@@ -530,9 +494,6 @@ config CPU_CACHE_FA
530 494
531if MMU 495if MMU
532# The copy-page model 496# The copy-page model
533config CPU_COPY_V3
534 bool
535
536config CPU_COPY_V4WT 497config CPU_COPY_V4WT
537 bool 498 bool
538 499
@@ -549,11 +510,6 @@ config CPU_COPY_V6
549 bool 510 bool
550 511
551# This selects the TLB model 512# This selects the TLB model
552config CPU_TLB_V3
553 bool
554 help
555 ARM Architecture Version 3 TLB.
556
557config CPU_TLB_V4WT 513config CPU_TLB_V4WT
558 bool 514 bool
559 help 515 help
@@ -731,7 +687,7 @@ config CPU_HIGH_VECTOR
731 687
732config CPU_ICACHE_DISABLE 688config CPU_ICACHE_DISABLE
733 bool "Disable I-Cache (I-bit)" 689 bool "Disable I-Cache (I-bit)"
734 depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3) 690 depends on CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
735 help 691 help
736 Say Y here to disable the processor instruction cache. Unless 692 Say Y here to disable the processor instruction cache. Unless
737 you have a reason not to or are unsure, say N. 693 you have a reason not to or are unsure, say N.
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index bca7e61928c..8a9c4cb50a9 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -44,7 +44,6 @@ obj-$(CONFIG_CPU_CACHE_FA) += cache-fa.o
44AFLAGS_cache-v6.o :=-Wa,-march=armv6 44AFLAGS_cache-v6.o :=-Wa,-march=armv6
45AFLAGS_cache-v7.o :=-Wa,-march=armv7-a 45AFLAGS_cache-v7.o :=-Wa,-march=armv7-a
46 46
47obj-$(CONFIG_CPU_COPY_V3) += copypage-v3.o
48obj-$(CONFIG_CPU_COPY_V4WT) += copypage-v4wt.o 47obj-$(CONFIG_CPU_COPY_V4WT) += copypage-v4wt.o
49obj-$(CONFIG_CPU_COPY_V4WB) += copypage-v4wb.o 48obj-$(CONFIG_CPU_COPY_V4WB) += copypage-v4wb.o
50obj-$(CONFIG_CPU_COPY_FEROCEON) += copypage-feroceon.o 49obj-$(CONFIG_CPU_COPY_FEROCEON) += copypage-feroceon.o
@@ -54,7 +53,6 @@ obj-$(CONFIG_CPU_XSCALE) += copypage-xscale.o
54obj-$(CONFIG_CPU_XSC3) += copypage-xsc3.o 53obj-$(CONFIG_CPU_XSC3) += copypage-xsc3.o
55obj-$(CONFIG_CPU_COPY_FA) += copypage-fa.o 54obj-$(CONFIG_CPU_COPY_FA) += copypage-fa.o
56 55
57obj-$(CONFIG_CPU_TLB_V3) += tlb-v3.o
58obj-$(CONFIG_CPU_TLB_V4WT) += tlb-v4.o 56obj-$(CONFIG_CPU_TLB_V4WT) += tlb-v4.o
59obj-$(CONFIG_CPU_TLB_V4WB) += tlb-v4wb.o 57obj-$(CONFIG_CPU_TLB_V4WB) += tlb-v4wb.o
60obj-$(CONFIG_CPU_TLB_V4WBI) += tlb-v4wbi.o 58obj-$(CONFIG_CPU_TLB_V4WBI) += tlb-v4wbi.o
@@ -66,8 +64,6 @@ obj-$(CONFIG_CPU_TLB_FA) += tlb-fa.o
66AFLAGS_tlb-v6.o :=-Wa,-march=armv6 64AFLAGS_tlb-v6.o :=-Wa,-march=armv6
67AFLAGS_tlb-v7.o :=-Wa,-march=armv7-a 65AFLAGS_tlb-v7.o :=-Wa,-march=armv7-a
68 66
69obj-$(CONFIG_CPU_ARM610) += proc-arm6_7.o
70obj-$(CONFIG_CPU_ARM710) += proc-arm6_7.o
71obj-$(CONFIG_CPU_ARM7TDMI) += proc-arm7tdmi.o 67obj-$(CONFIG_CPU_ARM7TDMI) += proc-arm7tdmi.o
72obj-$(CONFIG_CPU_ARM720T) += proc-arm720.o 68obj-$(CONFIG_CPU_ARM720T) += proc-arm720.o
73obj-$(CONFIG_CPU_ARM740T) += proc-arm740.o 69obj-$(CONFIG_CPU_ARM740T) += proc-arm740.o
diff --git a/arch/arm/mm/copypage-v3.c b/arch/arm/mm/copypage-v3.c
deleted file mode 100644
index 3935bddd476..00000000000
--- a/arch/arm/mm/copypage-v3.c
+++ /dev/null
@@ -1,81 +0,0 @@
1/*
2 * linux/arch/arm/mm/copypage-v3.c
3 *
4 * Copyright (C) 1995-1999 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/init.h>
11#include <linux/highmem.h>
12
13/*
14 * ARMv3 optimised copy_user_highpage
15 *
16 * FIXME: do we need to handle cache stuff...
17 */
18static void __naked
19v3_copy_user_page(void *kto, const void *kfrom)
20{
21 asm("\n\
22 stmfd sp!, {r4, lr} @ 2\n\
23 mov r2, %2 @ 1\n\
24 ldmia %0!, {r3, r4, ip, lr} @ 4+1\n\
251: stmia %1!, {r3, r4, ip, lr} @ 4\n\
26 ldmia %0!, {r3, r4, ip, lr} @ 4+1\n\
27 stmia %1!, {r3, r4, ip, lr} @ 4\n\
28 ldmia %0!, {r3, r4, ip, lr} @ 4+1\n\
29 stmia %1!, {r3, r4, ip, lr} @ 4\n\
30 ldmia %0!, {r3, r4, ip, lr} @ 4\n\
31 subs r2, r2, #1 @ 1\n\
32 stmia %1!, {r3, r4, ip, lr} @ 4\n\
33 ldmneia %0!, {r3, r4, ip, lr} @ 4\n\
34 bne 1b @ 1\n\
35 ldmfd sp!, {r4, pc} @ 3"
36 :
37 : "r" (kfrom), "r" (kto), "I" (PAGE_SIZE / 64));
38}
39
40void v3_copy_user_highpage(struct page *to, struct page *from,
41 unsigned long vaddr, struct vm_area_struct *vma)
42{
43 void *kto, *kfrom;
44
45 kto = kmap_atomic(to);
46 kfrom = kmap_atomic(from);
47 v3_copy_user_page(kto, kfrom);
48 kunmap_atomic(kfrom);
49 kunmap_atomic(kto);
50}
51
52/*
53 * ARMv3 optimised clear_user_page
54 *
55 * FIXME: do we need to handle cache stuff...
56 */
57void v3_clear_user_highpage(struct page *page, unsigned long vaddr)
58{
59 void *ptr, *kaddr = kmap_atomic(page);
60 asm volatile("\n\
61 mov r1, %2 @ 1\n\
62 mov r2, #0 @ 1\n\
63 mov r3, #0 @ 1\n\
64 mov ip, #0 @ 1\n\
65 mov lr, #0 @ 1\n\
661: stmia %0!, {r2, r3, ip, lr} @ 4\n\
67 stmia %0!, {r2, r3, ip, lr} @ 4\n\
68 stmia %0!, {r2, r3, ip, lr} @ 4\n\
69 stmia %0!, {r2, r3, ip, lr} @ 4\n\
70 subs r1, r1, #1 @ 1\n\
71 bne 1b @ 1"
72 : "=r" (ptr)
73 : "0" (kaddr), "I" (PAGE_SIZE / 64)
74 : "r1", "r2", "r3", "ip", "lr");
75 kunmap_atomic(kaddr);
76}
77
78struct cpu_user_fns v3_user_fns __initdata = {
79 .cpu_clear_user_highpage = v3_clear_user_highpage,
80 .cpu_copy_user_highpage = v3_copy_user_highpage,
81};
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index 5bb48356d21..c3bd8345022 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -432,9 +432,6 @@ do_translation_fault(unsigned long addr, unsigned int fsr,
432 432
433 index = pgd_index(addr); 433 index = pgd_index(addr);
434 434
435 /*
436 * FIXME: CP15 C1 is write only on ARMv3 architectures.
437 */
438 pgd = cpu_get_pgd() + index; 435 pgd = cpu_get_pgd() + index;
439 pgd_k = init_mm.pgd + index; 436 pgd_k = init_mm.pgd + index;
440 437
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
deleted file mode 100644
index 4fbeb5b8e6c..00000000000
--- a/arch/arm/mm/proc-arm6_7.S
+++ /dev/null
@@ -1,327 +0,0 @@
1/*
2 * linux/arch/arm/mm/proc-arm6,7.S
3 *
4 * Copyright (C) 1997-2000 Russell King
5 * hacked for non-paged-MM by Hyok S. Choi, 2003.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * These are the low level assembler for performing cache and TLB
12 * functions on the ARM610 & ARM710.
13 */
14#include <linux/linkage.h>
15#include <linux/init.h>
16#include <asm/assembler.h>
17#include <asm/asm-offsets.h>
18#include <asm/hwcap.h>
19#include <asm/pgtable-hwdef.h>
20#include <asm/pgtable.h>
21#include <asm/ptrace.h>
22
23#include "proc-macros.S"
24
25ENTRY(cpu_arm6_dcache_clean_area)
26ENTRY(cpu_arm7_dcache_clean_area)
27 mov pc, lr
28
29/*
30 * Function: arm6_7_data_abort ()
31 *
32 * Params : r2 = pt_regs
33 * : r4 = aborted context pc
34 * : r5 = aborted context psr
35 *
36 * Purpose : obtain information about current aborted instruction
37 *
38 * Returns : r4-r5, r10-r11, r13 preserved
39 */
40
41ENTRY(cpu_arm7_data_abort)
42 mrc p15, 0, r1, c5, c0, 0 @ get FSR
43 mrc p15, 0, r0, c6, c0, 0 @ get FAR
44 ldr r8, [r4] @ read arm instruction
45 tst r8, #1 << 20 @ L = 0 -> write?
46 orreq r1, r1, #1 << 11 @ yes.
47 and r7, r8, #15 << 24
48 add pc, pc, r7, lsr #22 @ Now branch to the relevant processing routine
49 nop
50
51/* 0 */ b .data_unknown
52/* 1 */ b do_DataAbort @ swp
53/* 2 */ b .data_unknown
54/* 3 */ b .data_unknown
55/* 4 */ b .data_arm_lateldrpostconst @ ldr rd, [rn], #m
56/* 5 */ b .data_arm_lateldrpreconst @ ldr rd, [rn, #m]
57/* 6 */ b .data_arm_lateldrpostreg @ ldr rd, [rn], rm
58/* 7 */ b .data_arm_lateldrprereg @ ldr rd, [rn, rm]
59/* 8 */ b .data_arm_ldmstm @ ldm*a rn, <rlist>
60/* 9 */ b .data_arm_ldmstm @ ldm*b rn, <rlist>
61/* a */ b .data_unknown
62/* b */ b .data_unknown
63/* c */ b do_DataAbort @ ldc rd, [rn], #m @ Same as ldr rd, [rn], #m
64/* d */ b do_DataAbort @ ldc rd, [rn, #m]
65/* e */ b .data_unknown
66/* f */
67.data_unknown: @ Part of jumptable
68 mov r0, r4
69 mov r1, r8
70 b baddataabort
71
72ENTRY(cpu_arm6_data_abort)
73 mrc p15, 0, r1, c5, c0, 0 @ get FSR
74 mrc p15, 0, r0, c6, c0, 0 @ get FAR
75 ldr r8, [r4] @ read arm instruction
76 tst r8, #1 << 20 @ L = 0 -> write?
77 orreq r1, r1, #1 << 11 @ yes.
78 and r7, r8, #14 << 24
79 teq r7, #8 << 24 @ was it ldm/stm
80 bne do_DataAbort
81
82.data_arm_ldmstm:
83 tst r8, #1 << 21 @ check writeback bit
84 beq do_DataAbort @ no writeback -> no fixup
85 mov r7, #0x11
86 orr r7, r7, #0x1100
87 and r6, r8, r7
88 and r9, r8, r7, lsl #1
89 add r6, r6, r9, lsr #1
90 and r9, r8, r7, lsl #2
91 add r6, r6, r9, lsr #2
92 and r9, r8, r7, lsl #3
93 add r6, r6, r9, lsr #3
94 add r6, r6, r6, lsr #8
95 add r6, r6, r6, lsr #4
96 and r6, r6, #15 @ r6 = no. of registers to transfer.
97 and r9, r8, #15 << 16 @ Extract 'n' from instruction
98 ldr r7, [r2, r9, lsr #14] @ Get register 'Rn'
99 tst r8, #1 << 23 @ Check U bit
100 subne r7, r7, r6, lsl #2 @ Undo increment
101 addeq r7, r7, r6, lsl #2 @ Undo decrement
102 str r7, [r2, r9, lsr #14] @ Put register 'Rn'
103 b do_DataAbort
104
105.data_arm_apply_r6_and_rn:
106 and r9, r8, #15 << 16 @ Extract 'n' from instruction
107 ldr r7, [r2, r9, lsr #14] @ Get register 'Rn'
108 tst r8, #1 << 23 @ Check U bit
109 subne r7, r7, r6 @ Undo incrmenet
110 addeq r7, r7, r6 @ Undo decrement
111 str r7, [r2, r9, lsr #14] @ Put register 'Rn'
112 b do_DataAbort
113
114.data_arm_lateldrpreconst:
115 tst r8, #1 << 21 @ check writeback bit
116 beq do_DataAbort @ no writeback -> no fixup
117.data_arm_lateldrpostconst:
118 movs r6, r8, lsl #20 @ Get offset
119 beq do_DataAbort @ zero -> no fixup
120 and r9, r8, #15 << 16 @ Extract 'n' from instruction
121 ldr r7, [r2, r9, lsr #14] @ Get register 'Rn'
122 tst r8, #1 << 23 @ Check U bit
123 subne r7, r7, r6, lsr #20 @ Undo increment
124 addeq r7, r7, r6, lsr #20 @ Undo decrement
125 str r7, [r2, r9, lsr #14] @ Put register 'Rn'
126 b do_DataAbort
127
128.data_arm_lateldrprereg:
129 tst r8, #1 << 21 @ check writeback bit
130 beq do_DataAbort @ no writeback -> no fixup
131.data_arm_lateldrpostreg:
132 and r7, r8, #15 @ Extract 'm' from instruction
133 ldr r6, [r2, r7, lsl #2] @ Get register 'Rm'
134 mov r9, r8, lsr #7 @ get shift count
135 ands r9, r9, #31
136 and r7, r8, #0x70 @ get shift type
137 orreq r7, r7, #8 @ shift count = 0
138 add pc, pc, r7
139 nop
140
141 mov r6, r6, lsl r9 @ 0: LSL #!0
142 b .data_arm_apply_r6_and_rn
143 b .data_arm_apply_r6_and_rn @ 1: LSL #0
144 nop
145 b .data_unknown @ 2: MUL?
146 nop
147 b .data_unknown @ 3: MUL?
148 nop
149 mov r6, r6, lsr r9 @ 4: LSR #!0
150 b .data_arm_apply_r6_and_rn
151 mov r6, r6, lsr #32 @ 5: LSR #32
152 b .data_arm_apply_r6_and_rn
153 b .data_unknown @ 6: MUL?
154 nop
155 b .data_unknown @ 7: MUL?
156 nop
157 mov r6, r6, asr r9 @ 8: ASR #!0
158 b .data_arm_apply_r6_and_rn
159 mov r6, r6, asr #32 @ 9: ASR #32
160 b .data_arm_apply_r6_and_rn
161 b .data_unknown @ A: MUL?
162 nop
163 b .data_unknown @ B: MUL?
164 nop
165 mov r6, r6, ror r9 @ C: ROR #!0
166 b .data_arm_apply_r6_and_rn
167 mov r6, r6, rrx @ D: RRX
168 b .data_arm_apply_r6_and_rn
169 b .data_unknown @ E: MUL?
170 nop
171 b .data_unknown @ F: MUL?
172
173/*
174 * Function: arm6_7_proc_init (void)
175 * : arm6_7_proc_fin (void)
176 *
177 * Notes : This processor does not require these
178 */
179ENTRY(cpu_arm6_proc_init)
180ENTRY(cpu_arm7_proc_init)
181 mov pc, lr
182
183ENTRY(cpu_arm6_proc_fin)
184ENTRY(cpu_arm7_proc_fin)
185 mov r0, #0x31 @ ....S..DP...M
186 mcr p15, 0, r0, c1, c0, 0 @ disable caches
187 mov pc, lr
188
189ENTRY(cpu_arm6_do_idle)
190ENTRY(cpu_arm7_do_idle)
191 mov pc, lr
192
193/*
194 * Function: arm6_7_switch_mm(unsigned long pgd_phys)
195 * Params : pgd_phys Physical address of page table
196 * Purpose : Perform a task switch, saving the old processes state, and restoring
197 * the new.
198 */
199ENTRY(cpu_arm6_switch_mm)
200ENTRY(cpu_arm7_switch_mm)
201#ifdef CONFIG_MMU
202 mov r1, #0
203 mcr p15, 0, r1, c7, c0, 0 @ flush cache
204 mcr p15, 0, r0, c2, c0, 0 @ update page table ptr
205 mcr p15, 0, r1, c5, c0, 0 @ flush TLBs
206#endif
207 mov pc, lr
208
209/*
210 * Function: arm6_7_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext)
211 * Params : r0 = Address to set
212 * : r1 = value to set
213 * Purpose : Set a PTE and flush it out of any WB cache
214 */
215 .align 5
216ENTRY(cpu_arm6_set_pte_ext)
217ENTRY(cpu_arm7_set_pte_ext)
218#ifdef CONFIG_MMU
219 armv3_set_pte_ext wc_disable=0
220#endif /* CONFIG_MMU */
221 mov pc, lr
222
223/*
224 * Function: _arm6_7_reset
225 * Params : r0 = address to jump to
226 * Notes : This sets up everything for a reset
227 */
228 .pushsection .idmap.text, "ax"
229ENTRY(cpu_arm6_reset)
230ENTRY(cpu_arm7_reset)
231 mov r1, #0
232 mcr p15, 0, r1, c7, c0, 0 @ flush cache
233#ifdef CONFIG_MMU
234 mcr p15, 0, r1, c5, c0, 0 @ flush TLB
235#endif
236 mov r1, #0x30
237 mcr p15, 0, r1, c1, c0, 0 @ turn off MMU etc
238 mov pc, r0
239ENDPROC(cpu_arm6_reset)
240ENDPROC(cpu_arm7_reset)
241 .popsection
242
243 __CPUINIT
244
245 .type __arm6_setup, #function
246__arm6_setup: mov r0, #0
247 mcr p15, 0, r0, c7, c0 @ flush caches on v3
248#ifdef CONFIG_MMU
249 mcr p15, 0, r0, c5, c0 @ flush TLBs on v3
250 mov r0, #0x3d @ . ..RS BLDP WCAM
251 orr r0, r0, #0x100 @ . ..01 0011 1101
252#else
253 mov r0, #0x3c @ . ..RS BLDP WCA.
254#endif
255 mov pc, lr
256 .size __arm6_setup, . - __arm6_setup
257
258 .type __arm7_setup, #function
259__arm7_setup: mov r0, #0
260 mcr p15, 0, r0, c7, c0 @ flush caches on v3
261#ifdef CONFIG_MMU
262 mcr p15, 0, r0, c5, c0 @ flush TLBs on v3
263 mcr p15, 0, r0, c3, c0 @ load domain access register
264 mov r0, #0x7d @ . ..RS BLDP WCAM
265 orr r0, r0, #0x100 @ . ..01 0111 1101
266#else
267 mov r0, #0x7c @ . ..RS BLDP WCA.
268#endif
269 mov pc, lr
270 .size __arm7_setup, . - __arm7_setup
271
272 __INITDATA
273
274 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
275 define_processor_functions arm6, dabort=cpu_arm6_data_abort, pabort=legacy_pabort
276 define_processor_functions arm7, dabort=cpu_arm7_data_abort, pabort=legacy_pabort
277
278 .section ".rodata"
279
280 string cpu_arch_name, "armv3"
281 string cpu_elf_name, "v3"
282 string cpu_arm6_name, "ARM6"
283 string cpu_arm610_name, "ARM610"
284 string cpu_arm7_name, "ARM7"
285 string cpu_arm710_name, "ARM710"
286
287 .align
288
289 .section ".proc.info.init", #alloc, #execinstr
290
291.macro arm67_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, \
292 cpu_mm_mmu_flags:req, cpu_flush:req, cpu_proc_funcs:req
293 .type __\name\()_proc_info, #object
294__\name\()_proc_info:
295 .long \cpu_val
296 .long \cpu_mask
297 .long \cpu_mm_mmu_flags
298 .long PMD_TYPE_SECT | \
299 PMD_BIT4 | \
300 PMD_SECT_AP_WRITE | \
301 PMD_SECT_AP_READ
302 b \cpu_flush
303 .long cpu_arch_name
304 .long cpu_elf_name
305 .long HWCAP_SWP | HWCAP_26BIT
306 .long \cpu_name
307 .long \cpu_proc_funcs
308 .long v3_tlb_fns
309 .long v3_user_fns
310 .long v3_cache_fns
311 .size __\name\()_proc_info, . - __\name\()_proc_info
312.endm
313
314 arm67_proc_info arm6, 0x41560600, 0xfffffff0, cpu_arm6_name, \
315 0x00000c1e, __arm6_setup, arm6_processor_functions
316 arm67_proc_info arm610, 0x41560610, 0xfffffff0, cpu_arm610_name, \
317 0x00000c1e, __arm6_setup, arm6_processor_functions
318 arm67_proc_info arm7, 0x41007000, 0xffffff00, cpu_arm7_name, \
319 0x00000c1e, __arm7_setup, arm7_processor_functions
320 arm67_proc_info arm710, 0x41007100, 0xfff8ff00, cpu_arm710_name, \
321 PMD_TYPE_SECT | \
322 PMD_SECT_BUFFERABLE | \
323 PMD_SECT_CACHEABLE | \
324 PMD_BIT4 | \
325 PMD_SECT_AP_WRITE | \
326 PMD_SECT_AP_READ, \
327 __arm7_setup, arm7_processor_functions
diff --git a/arch/arm/mm/tlb-v3.S b/arch/arm/mm/tlb-v3.S
deleted file mode 100644
index d253995ec4c..00000000000
--- a/arch/arm/mm/tlb-v3.S
+++ /dev/null
@@ -1,48 +0,0 @@
1/*
2 * linux/arch/arm/mm/tlbv3.S
3 *
4 * Copyright (C) 1997-2002 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * ARM architecture version 3 TLB handling functions.
11 *
12 * Processors: ARM610, ARM710.
13 */
14#include <linux/linkage.h>
15#include <linux/init.h>
16#include <asm/asm-offsets.h>
17#include <asm/tlbflush.h>
18#include "proc-macros.S"
19
20 .align 5
21/*
22 * v3_flush_user_tlb_range(start, end, mm)
23 *
24 * Invalidate a range of TLB entries in the specified address space.
25 *
26 * - start - range start address
27 * - end - range end address
28 * - mm - mm_struct describing address space
29 */
30 .align 5
31ENTRY(v3_flush_user_tlb_range)
32 vma_vm_mm r2, r2
33 act_mm r3 @ get current->active_mm
34 teq r2, r3 @ == mm ?
35 movne pc, lr @ no, we dont do anything
36ENTRY(v3_flush_kern_tlb_range)
37 bic r0, r0, #0x0ff
38 bic r0, r0, #0xf00
391: mcr p15, 0, r0, c6, c0, 0 @ invalidate TLB entry
40 add r0, r0, #PAGE_SZ
41 cmp r0, r1
42 blo 1b
43 mov pc, lr
44
45 __INITDATA
46
47 /* define struct cpu_tlb_fns (see <asm/tlbflush.h> and proc-macros.S) */
48 define_tlb_functions v3, v3_tlb_flags
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-19 14:52:42 -0500