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authorLinus Torvalds <torvalds@linux-foundation.org>2012-05-21 19:58:23 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-05-21 19:58:23 -0400
commit3d1482fe7a835a18cb45894ed67f15466b60190f (patch)
tree9a97af186208e89f4f60312b3033fedbe6dbfc5c
parentac1806572df55b6125ad9d117906820dacfa3145 (diff)
parent4f6a16bf019cb0bbe1deb7d3a83d3593dcce8706 (diff)
Merge tag 'pinctrl-for-v3.5' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control subsystem changes from Linus Walleij: - Generic Device Tree bindings and hooks for drivers so we can move over modern drivers to using this. - Device Tree bindings for Tegra SoCs. - Funneling some devicetree helper code for the drivers/of subsystem. - New pin control drivers for: * Freescale MXS * Freescale i.MX51 * Freescale i.MX53 All of these use Device Tree bindings. - Dummy pinctrl handles for stepwise migration to pinctrl, akin to dummy regulators. - Minor non-urgent fixes and improvments. Fix up trivial conflicts in Documentation/driver-model/devres.txt and drivers/pinctrl/core.c, * tag 'pinctrl-for-v3.5' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (46 commits) pinctrl: pinctrl-imx: add imx51 pinctrl driver pinctrl: pinctrl-imx: add imx53 pinctrl driver pinctrl: pinctrl-pxa3xx: remove empty pinmux disable function pinctrl: pinctrl-mxs: remove empty pinmux disable function pinctrl: pinctrl-imx: remove empty pinmux disable function pinctrl: make pinmux disable function optional pinctrl: a minor error checking improvement for pinconf pinctrl: mxs: skip gpio nodes for group creation pinctrl: mxs: create group for pin config node pinctrl: (cosmetic) fix two entries in DocBook comments pinctrl: add more info to error msgs in pin_request pinctrl: add pinctrl-mxs support pinctrl: pinctrl-imx: add imx6q pinctrl driver pinctrl: pinctrl-imx: add imx pinctrl core driver dt: add of_get_child_count helper function pinctrl: support gpio request deferred probing pinctrl: add pinctrl_provide_dummies interface for platforms to use pinctrl: enhance reporting of errors when loading from DT pinctrl: add kerneldoc for pinctrl_ops device tree functions pinctrl: propagate map validation errors ...
Diffstat
-rw-r--r--Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt95
-rw-r--r--Documentation/devicetree/bindings/pinctrl/fsl,imx51-pinctrl.txt787
-rw-r--r--Documentation/devicetree/bindings/pinctrl/fsl,imx53-pinctrl.txt1202
-rw-r--r--Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt1628
-rw-r--r--Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt918
-rw-r--r--Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt132
-rw-r--r--Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt132
-rw-r--r--Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt128
-rw-r--r--Documentation/devicetree/bindings/pinmux/pinmux_nvidia.txt5
-rw-r--r--Documentation/driver-model/devres.txt4
-rw-r--r--Documentation/pinctrl.txt94
-rw-r--r--drivers/of/base.c41
-rw-r--r--drivers/pinctrl/Kconfig45
-rw-r--r--drivers/pinctrl/Makefile10
-rw-r--r--drivers/pinctrl/core.c244
-rw-r--r--drivers/pinctrl/core.h12
-rw-r--r--drivers/pinctrl/devicetree.c249
-rw-r--r--drivers/pinctrl/devicetree.h35
-rw-r--r--drivers/pinctrl/pinconf.c56
-rw-r--r--drivers/pinctrl/pinconf.h17
-rw-r--r--drivers/pinctrl/pinctrl-coh901.c4
-rw-r--r--drivers/pinctrl/pinctrl-imx.c620
-rw-r--r--drivers/pinctrl/pinctrl-imx.h106
-rw-r--r--drivers/pinctrl/pinctrl-imx23.c305
-rw-r--r--drivers/pinctrl/pinctrl-imx28.c421
-rw-r--r--drivers/pinctrl/pinctrl-imx51.c1322
-rw-r--r--drivers/pinctrl/pinctrl-imx53.c1649
-rw-r--r--drivers/pinctrl/pinctrl-imx6q.c2331
-rw-r--r--drivers/pinctrl/pinctrl-mxs.c528
-rw-r--r--drivers/pinctrl/pinctrl-mxs.h91
-rw-r--r--drivers/pinctrl/pinctrl-pxa3xx.c30
-rw-r--r--drivers/pinctrl/pinctrl-sirf.c20
-rw-r--r--drivers/pinctrl/pinctrl-tegra.c245
-rw-r--r--drivers/pinctrl/pinctrl-u300.c20
-rw-r--r--drivers/pinctrl/pinmux.c97
-rw-r--r--drivers/pinctrl/pinmux.h18
-rw-r--r--include/linux/of.h51
-rw-r--r--include/linux/pinctrl/consumer.h44
-rw-r--r--include/linux/pinctrl/machine.h7
-rw-r--r--include/linux/pinctrl/pinconf.h6
-rw-r--r--include/linux/pinctrl/pinctrl.h22
-rw-r--r--include/linux/pinctrl/pinmux.h9
42 files changed, 13534 insertions, 246 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
new file mode 100644
index 00000000000..ab19e6bc7d3
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
@@ -0,0 +1,95 @@
1* Freescale IOMUX Controller (IOMUXC) for i.MX
2
3The IOMUX Controller (IOMUXC), together with the IOMUX, enables the IC
4to share one PAD to several functional blocks. The sharing is done by
5multiplexing the PAD input/output signals. For each PAD there are up to
68 muxing options (called ALT modes). Since different modules require
7different PAD settings (like pull up, keeper, etc) the IOMUXC controls
8also the PAD settings parameters.
9
10Please refer to pinctrl-bindings.txt in this directory for details of the
11common pinctrl bindings used by client devices, including the meaning of the
12phrase "pin configuration node".
13
14Freescale IMX pin configuration node is a node of a group of pins which can be
15used for a specific device or function. This node represents both mux and config
16of the pins in that group. The 'mux' selects the function mode(also named mux
17mode) this pin can work on and the 'config' configures various pad settings
18such as pull-up, open drain, drive strength, etc.
19
20Required properties for iomux controller:
21- compatible: "fsl,<soc>-iomuxc"
22 Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
23
24Required properties for pin configuration node:
25- fsl,pins: two integers array, represents a group of pins mux and config
26 setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
27 pin working on a specific function, CONFIG is the pad setting value like
28 pull-up on this pin. Please refer to fsl,<soc>-pinctrl.txt for the valid
29 pins and functions of each SoC.
30
31Bits used for CONFIG:
32NO_PAD_CTL(1 << 31): indicate this pin does not need config.
33
34SION(1 << 30): Software Input On Field.
35Force the selected mux mode input path no matter of MUX_MODE functionality.
36By default the input path is determined by functionality of the selected
37mux mode (regular).
38
39Other bits are used for PAD setting.
40Please refer to each fsl,<soc>-pinctrl,txt binding doc for SoC specific part
41of bits definitions.
42
43NOTE:
44Some requirements for using fsl,imx-pinctrl binding:
451. We have pin function node defined under iomux controller node to represent
46 what pinmux functions this SoC supports.
472. The pin configuration node intends to work on a specific function should
48 to be defined under that specific function node.
49 The function node's name should represent well about what function
50 this group of pins in this pin configuration node are working on.
513. The driver can use the function node's name and pin configuration node's
52 name describe the pin function and group hierarchy.
53 For example, Linux IMX pinctrl driver takes the function node's name
54 as the function name and pin configuration node's name as group name to
55 create the map table.
564. Each pin configuration node should have a phandle, devices can set pins
57 configurations by referring to the phandle of that pin configuration node.
58
59Examples:
60usdhc@0219c000 { /* uSDHC4 */
61 fsl,card-wired;
62 vmmc-supply = <&reg_3p3v>;
63 status = "okay";
64 pinctrl-names = "default";
65 pinctrl-0 = <&pinctrl_usdhc4_1>;
66};
67
68iomuxc@020e0000 {
69 compatible = "fsl,imx6q-iomuxc";
70 reg = <0x020e0000 0x4000>;
71
72 /* shared pinctrl settings */
73 usdhc4 {
74 pinctrl_usdhc4_1: usdhc4grp-1 {
75 fsl,pins = <1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
76 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
77 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
78 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
79 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
80 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
81 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
82 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
83 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
84 1517 0x17059>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
85 };
86 };
87 ....
88};
89Refer to the IOMUXC controller chapter in imx6q datasheet,
900x17059 means enable hysteresis, 47KOhm Pull Up, 50Mhz speed,
9180Ohm driver strength and Fast Slew Rate.
92User should refer to each SoC spec to set the correct value.
93
94TODO: when dtc macro support is available, we can change above raw data
95to dt macro which can get better readability in dts file.
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx51-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx51-pinctrl.txt
new file mode 100644
index 00000000000..b96fa4c3174
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx51-pinctrl.txt
@@ -0,0 +1,787 @@
1* Freescale IMX51 IOMUX Controller
2
3Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
4and usage.
5
6Required properties:
7- compatible: "fsl,imx51-iomuxc"
8- fsl,pins: two integers array, represents a group of pins mux and config
9 setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
10 pin working on a specific function, CONFIG is the pad setting value like
11 pull-up for this pin. Please refer to imx51 datasheet for the valid pad
12 config settings.
13
14CONFIG bits definition:
15PAD_CTL_HVE (1 << 13)
16PAD_CTL_HYS (1 << 8)
17PAD_CTL_PKE (1 << 7)
18PAD_CTL_PUE (1 << 6)
19PAD_CTL_PUS_100K_DOWN (0 << 4)
20PAD_CTL_PUS_47K_UP (1 << 4)
21PAD_CTL_PUS_100K_UP (2 << 4)
22PAD_CTL_PUS_22K_UP (3 << 4)
23PAD_CTL_ODE (1 << 3)
24PAD_CTL_DSE_LOW (0 << 1)
25PAD_CTL_DSE_MED (1 << 1)
26PAD_CTL_DSE_HIGH (2 << 1)
27PAD_CTL_DSE_MAX (3 << 1)
28PAD_CTL_SRE_FAST (1 << 0)
29PAD_CTL_SRE_SLOW (0 << 0)
30
31See below for available PIN_FUNC_ID for imx51:
32MX51_PAD_EIM_D16__AUD4_RXFS 0
33MX51_PAD_EIM_D16__AUD5_TXD 1
34MX51_PAD_EIM_D16__EIM_D16 2
35MX51_PAD_EIM_D16__GPIO2_0 3
36MX51_PAD_EIM_D16__I2C1_SDA 4
37MX51_PAD_EIM_D16__UART2_CTS 5
38MX51_PAD_EIM_D16__USBH2_DATA0 6
39MX51_PAD_EIM_D17__AUD5_RXD 7
40MX51_PAD_EIM_D17__EIM_D17 8
41MX51_PAD_EIM_D17__GPIO2_1 9
42MX51_PAD_EIM_D17__UART2_RXD 10
43MX51_PAD_EIM_D17__UART3_CTS 11
44MX51_PAD_EIM_D17__USBH2_DATA1 12
45MX51_PAD_EIM_D18__AUD5_TXC 13
46MX51_PAD_EIM_D18__EIM_D18 14
47MX51_PAD_EIM_D18__GPIO2_2 15
48MX51_PAD_EIM_D18__UART2_TXD 16
49MX51_PAD_EIM_D18__UART3_RTS 17
50MX51_PAD_EIM_D18__USBH2_DATA2 18
51MX51_PAD_EIM_D19__AUD4_RXC 19
52MX51_PAD_EIM_D19__AUD5_TXFS 20
53MX51_PAD_EIM_D19__EIM_D19 21
54MX51_PAD_EIM_D19__GPIO2_3 22
55MX51_PAD_EIM_D19__I2C1_SCL 23
56MX51_PAD_EIM_D19__UART2_RTS 24
57MX51_PAD_EIM_D19__USBH2_DATA3 25
58MX51_PAD_EIM_D20__AUD4_TXD 26
59MX51_PAD_EIM_D20__EIM_D20 27
60MX51_PAD_EIM_D20__GPIO2_4 28
61MX51_PAD_EIM_D20__SRTC_ALARM_DEB 29
62MX51_PAD_EIM_D20__USBH2_DATA4 30
63MX51_PAD_EIM_D21__AUD4_RXD 31
64MX51_PAD_EIM_D21__EIM_D21 32
65MX51_PAD_EIM_D21__GPIO2_5 33
66MX51_PAD_EIM_D21__SRTC_ALARM_DEB 34
67MX51_PAD_EIM_D21__USBH2_DATA5 35
68MX51_PAD_EIM_D22__AUD4_TXC 36
69MX51_PAD_EIM_D22__EIM_D22 37
70MX51_PAD_EIM_D22__GPIO2_6 38
71MX51_PAD_EIM_D22__USBH2_DATA6 39
72MX51_PAD_EIM_D23__AUD4_TXFS 40
73MX51_PAD_EIM_D23__EIM_D23 41
74MX51_PAD_EIM_D23__GPIO2_7 42
75MX51_PAD_EIM_D23__SPDIF_OUT1 43
76MX51_PAD_EIM_D23__USBH2_DATA7 44
77MX51_PAD_EIM_D24__AUD6_RXFS 45
78MX51_PAD_EIM_D24__EIM_D24 46
79MX51_PAD_EIM_D24__GPIO2_8 47
80MX51_PAD_EIM_D24__I2C2_SDA 48
81MX51_PAD_EIM_D24__UART3_CTS 49
82MX51_PAD_EIM_D24__USBOTG_DATA0 50
83MX51_PAD_EIM_D25__EIM_D25 51
84MX51_PAD_EIM_D25__KEY_COL6 52
85MX51_PAD_EIM_D25__UART2_CTS 53
86MX51_PAD_EIM_D25__UART3_RXD 54
87MX51_PAD_EIM_D25__USBOTG_DATA1 55
88MX51_PAD_EIM_D26__EIM_D26 56
89MX51_PAD_EIM_D26__KEY_COL7 57
90MX51_PAD_EIM_D26__UART2_RTS 58
91MX51_PAD_EIM_D26__UART3_TXD 59
92MX51_PAD_EIM_D26__USBOTG_DATA2 60
93MX51_PAD_EIM_D27__AUD6_RXC 61
94MX51_PAD_EIM_D27__EIM_D27 62
95MX51_PAD_EIM_D27__GPIO2_9 63
96MX51_PAD_EIM_D27__I2C2_SCL 64
97MX51_PAD_EIM_D27__UART3_RTS 65
98MX51_PAD_EIM_D27__USBOTG_DATA3 66
99MX51_PAD_EIM_D28__AUD6_TXD 67
100MX51_PAD_EIM_D28__EIM_D28 68
101MX51_PAD_EIM_D28__KEY_ROW4 69
102MX51_PAD_EIM_D28__USBOTG_DATA4 70
103MX51_PAD_EIM_D29__AUD6_RXD 71
104MX51_PAD_EIM_D29__EIM_D29 72
105MX51_PAD_EIM_D29__KEY_ROW5 73
106MX51_PAD_EIM_D29__USBOTG_DATA5 74
107MX51_PAD_EIM_D30__AUD6_TXC 75
108MX51_PAD_EIM_D30__EIM_D30 76
109MX51_PAD_EIM_D30__KEY_ROW6 77
110MX51_PAD_EIM_D30__USBOTG_DATA6 78
111MX51_PAD_EIM_D31__AUD6_TXFS 79
112MX51_PAD_EIM_D31__EIM_D31 80
113MX51_PAD_EIM_D31__KEY_ROW7 81
114MX51_PAD_EIM_D31__USBOTG_DATA7 82
115MX51_PAD_EIM_A16__EIM_A16 83
116MX51_PAD_EIM_A16__GPIO2_10 84
117MX51_PAD_EIM_A16__OSC_FREQ_SEL0 85
118MX51_PAD_EIM_A17__EIM_A17 86
119MX51_PAD_EIM_A17__GPIO2_11 87
120MX51_PAD_EIM_A17__OSC_FREQ_SEL1 88
121MX51_PAD_EIM_A18__BOOT_LPB0 89
122MX51_PAD_EIM_A18__EIM_A18 90
123MX51_PAD_EIM_A18__GPIO2_12 91
124MX51_PAD_EIM_A19__BOOT_LPB1 92
125MX51_PAD_EIM_A19__EIM_A19 93
126MX51_PAD_EIM_A19__GPIO2_13 94
127MX51_PAD_EIM_A20__BOOT_UART_SRC0 95
128MX51_PAD_EIM_A20__EIM_A20 96
129MX51_PAD_EIM_A20__GPIO2_14 97
130MX51_PAD_EIM_A21__BOOT_UART_SRC1 98
131MX51_PAD_EIM_A21__EIM_A21 99
132MX51_PAD_EIM_A21__GPIO2_15 100
133MX51_PAD_EIM_A22__EIM_A22 101
134MX51_PAD_EIM_A22__GPIO2_16 102
135MX51_PAD_EIM_A23__BOOT_HPN_EN 103
136MX51_PAD_EIM_A23__EIM_A23 104
137MX51_PAD_EIM_A23__GPIO2_17 105
138MX51_PAD_EIM_A24__EIM_A24 106
139MX51_PAD_EIM_A24__GPIO2_18 107
140MX51_PAD_EIM_A24__USBH2_CLK 108
141MX51_PAD_EIM_A25__DISP1_PIN4 109
142MX51_PAD_EIM_A25__EIM_A25 110
143MX51_PAD_EIM_A25__GPIO2_19 111
144MX51_PAD_EIM_A25__USBH2_DIR 112
145MX51_PAD_EIM_A26__CSI1_DATA_EN 113
146MX51_PAD_EIM_A26__DISP2_EXT_CLK 114
147MX51_PAD_EIM_A26__EIM_A26 115
148MX51_PAD_EIM_A26__GPIO2_20 116
149MX51_PAD_EIM_A26__USBH2_STP 117
150MX51_PAD_EIM_A27__CSI2_DATA_EN 118
151MX51_PAD_EIM_A27__DISP1_PIN1 119
152MX51_PAD_EIM_A27__EIM_A27 120
153MX51_PAD_EIM_A27__GPIO2_21 121
154MX51_PAD_EIM_A27__USBH2_NXT 122
155MX51_PAD_EIM_EB0__EIM_EB0 123
156MX51_PAD_EIM_EB1__EIM_EB1 124
157MX51_PAD_EIM_EB2__AUD5_RXFS 125
158MX51_PAD_EIM_EB2__CSI1_D2 126
159MX51_PAD_EIM_EB2__EIM_EB2 127
160MX51_PAD_EIM_EB2__FEC_MDIO 128
161MX51_PAD_EIM_EB2__GPIO2_22 129
162MX51_PAD_EIM_EB2__GPT_CMPOUT1 130
163MX51_PAD_EIM_EB3__AUD5_RXC 131
164MX51_PAD_EIM_EB3__CSI1_D3 132
165MX51_PAD_EIM_EB3__EIM_EB3 133
166MX51_PAD_EIM_EB3__FEC_RDATA1 134
167MX51_PAD_EIM_EB3__GPIO2_23 135
168MX51_PAD_EIM_EB3__GPT_CMPOUT2 136
169MX51_PAD_EIM_OE__EIM_OE 137
170MX51_PAD_EIM_OE__GPIO2_24 138
171MX51_PAD_EIM_CS0__EIM_CS0 139
172MX51_PAD_EIM_CS0__GPIO2_25 140
173MX51_PAD_EIM_CS1__EIM_CS1 141
174MX51_PAD_EIM_CS1__GPIO2_26 142
175MX51_PAD_EIM_CS2__AUD5_TXD 143
176MX51_PAD_EIM_CS2__CSI1_D4 144
177MX51_PAD_EIM_CS2__EIM_CS2 145
178MX51_PAD_EIM_CS2__FEC_RDATA2 146
179MX51_PAD_EIM_CS2__GPIO2_27 147
180MX51_PAD_EIM_CS2__USBOTG_STP 148
181MX51_PAD_EIM_CS3__AUD5_RXD 149
182MX51_PAD_EIM_CS3__CSI1_D5 150
183MX51_PAD_EIM_CS3__EIM_CS3 151
184MX51_PAD_EIM_CS3__FEC_RDATA3 152
185MX51_PAD_EIM_CS3__GPIO2_28 153
186MX51_PAD_EIM_CS3__USBOTG_NXT 154
187MX51_PAD_EIM_CS4__AUD5_TXC 155
188MX51_PAD_EIM_CS4__CSI1_D6 156
189MX51_PAD_EIM_CS4__EIM_CS4 157
190MX51_PAD_EIM_CS4__FEC_RX_ER 158
191MX51_PAD_EIM_CS4__GPIO2_29 159
192MX51_PAD_EIM_CS4__USBOTG_CLK 160
193MX51_PAD_EIM_CS5__AUD5_TXFS 161
194MX51_PAD_EIM_CS5__CSI1_D7 162
195MX51_PAD_EIM_CS5__DISP1_EXT_CLK 163
196MX51_PAD_EIM_CS5__EIM_CS5 164
197MX51_PAD_EIM_CS5__FEC_CRS 165
198MX51_PAD_EIM_CS5__GPIO2_30 166
199MX51_PAD_EIM_CS5__USBOTG_DIR 167
200MX51_PAD_EIM_DTACK__EIM_DTACK 168
201MX51_PAD_EIM_DTACK__GPIO2_31 169
202MX51_PAD_EIM_LBA__EIM_LBA 170
203MX51_PAD_EIM_LBA__GPIO3_1 171
204MX51_PAD_EIM_CRE__EIM_CRE 172
205MX51_PAD_EIM_CRE__GPIO3_2 173
206MX51_PAD_DRAM_CS1__DRAM_CS1 174
207MX51_PAD_NANDF_WE_B__GPIO3_3 175
208MX51_PAD_NANDF_WE_B__NANDF_WE_B 176
209MX51_PAD_NANDF_WE_B__PATA_DIOW 177
210MX51_PAD_NANDF_WE_B__SD3_DATA0 178
211MX51_PAD_NANDF_RE_B__GPIO3_4 179
212MX51_PAD_NANDF_RE_B__NANDF_RE_B 180
213MX51_PAD_NANDF_RE_B__PATA_DIOR 181
214MX51_PAD_NANDF_RE_B__SD3_DATA1 182
215MX51_PAD_NANDF_ALE__GPIO3_5 183
216MX51_PAD_NANDF_ALE__NANDF_ALE 184
217MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 185
218MX51_PAD_NANDF_CLE__GPIO3_6 186
219MX51_PAD_NANDF_CLE__NANDF_CLE 187
220MX51_PAD_NANDF_CLE__PATA_RESET_B 188
221MX51_PAD_NANDF_WP_B__GPIO3_7 189
222MX51_PAD_NANDF_WP_B__NANDF_WP_B 190
223MX51_PAD_NANDF_WP_B__PATA_DMACK 191
224MX51_PAD_NANDF_WP_B__SD3_DATA2 192
225MX51_PAD_NANDF_RB0__ECSPI2_SS1 193
226MX51_PAD_NANDF_RB0__GPIO3_8 194
227MX51_PAD_NANDF_RB0__NANDF_RB0 195
228MX51_PAD_NANDF_RB0__PATA_DMARQ 196
229MX51_PAD_NANDF_RB0__SD3_DATA3 197
230MX51_PAD_NANDF_RB1__CSPI_MOSI 198
231MX51_PAD_NANDF_RB1__ECSPI2_RDY 199
232MX51_PAD_NANDF_RB1__GPIO3_9 200
233MX51_PAD_NANDF_RB1__NANDF_RB1 201
234MX51_PAD_NANDF_RB1__PATA_IORDY 202
235MX51_PAD_NANDF_RB1__SD4_CMD 203
236MX51_PAD_NANDF_RB2__DISP2_WAIT 204
237MX51_PAD_NANDF_RB2__ECSPI2_SCLK 205
238MX51_PAD_NANDF_RB2__FEC_COL 206
239MX51_PAD_NANDF_RB2__GPIO3_10 207
240MX51_PAD_NANDF_RB2__NANDF_RB2 208
241MX51_PAD_NANDF_RB2__USBH3_H3_DP 209
242MX51_PAD_NANDF_RB2__USBH3_NXT 210
243MX51_PAD_NANDF_RB3__DISP1_WAIT 211
244MX51_PAD_NANDF_RB3__ECSPI2_MISO 212
245MX51_PAD_NANDF_RB3__FEC_RX_CLK 213
246MX51_PAD_NANDF_RB3__GPIO3_11 214
247MX51_PAD_NANDF_RB3__NANDF_RB3 215
248MX51_PAD_NANDF_RB3__USBH3_CLK 216
249MX51_PAD_NANDF_RB3__USBH3_H3_DM 217
250MX51_PAD_GPIO_NAND__GPIO_NAND 218
251MX51_PAD_GPIO_NAND__PATA_INTRQ 219
252MX51_PAD_NANDF_CS0__GPIO3_16 220
253MX51_PAD_NANDF_CS0__NANDF_CS0 221
254MX51_PAD_NANDF_CS1__GPIO3_17 222
255MX51_PAD_NANDF_CS1__NANDF_CS1 223
256MX51_PAD_NANDF_CS2__CSPI_SCLK 224
257MX51_PAD_NANDF_CS2__FEC_TX_ER 225
258MX51_PAD_NANDF_CS2__GPIO3_18 226
259MX51_PAD_NANDF_CS2__NANDF_CS2 227
260MX51_PAD_NANDF_CS2__PATA_CS_0 228
261MX51_PAD_NANDF_CS2__SD4_CLK 229
262MX51_PAD_NANDF_CS2__USBH3_H1_DP 230
263MX51_PAD_NANDF_CS3__FEC_MDC 231
264MX51_PAD_NANDF_CS3__GPIO3_19 232
265MX51_PAD_NANDF_CS3__NANDF_CS3 233
266MX51_PAD_NANDF_CS3__PATA_CS_1 234
267MX51_PAD_NANDF_CS3__SD4_DAT0 235
268MX51_PAD_NANDF_CS3__USBH3_H1_DM 236
269MX51_PAD_NANDF_CS4__FEC_TDATA1 237
270MX51_PAD_NANDF_CS4__GPIO3_20 238
271MX51_PAD_NANDF_CS4__NANDF_CS4 239
272MX51_PAD_NANDF_CS4__PATA_DA_0 240
273MX51_PAD_NANDF_CS4__SD4_DAT1 241
274MX51_PAD_NANDF_CS4__USBH3_STP 242
275MX51_PAD_NANDF_CS5__FEC_TDATA2 243
276MX51_PAD_NANDF_CS5__GPIO3_21 244
277MX51_PAD_NANDF_CS5__NANDF_CS5 245
278MX51_PAD_NANDF_CS5__PATA_DA_1 246
279MX51_PAD_NANDF_CS5__SD4_DAT2 247
280MX51_PAD_NANDF_CS5__USBH3_DIR 248
281MX51_PAD_NANDF_CS6__CSPI_SS3 249
282MX51_PAD_NANDF_CS6__FEC_TDATA3 250
283MX51_PAD_NANDF_CS6__GPIO3_22 251
284MX51_PAD_NANDF_CS6__NANDF_CS6 252
285MX51_PAD_NANDF_CS6__PATA_DA_2 253
286MX51_PAD_NANDF_CS6__SD4_DAT3 254
287MX51_PAD_NANDF_CS7__FEC_TX_EN 255
288MX51_PAD_NANDF_CS7__GPIO3_23 256
289MX51_PAD_NANDF_CS7__NANDF_CS7 257
290MX51_PAD_NANDF_CS7__SD3_CLK 258
291MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 259
292MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 260
293MX51_PAD_NANDF_RDY_INT__GPIO3_24 261
294MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT 262
295MX51_PAD_NANDF_RDY_INT__SD3_CMD 263
296MX51_PAD_NANDF_D15__ECSPI2_MOSI 264
297MX51_PAD_NANDF_D15__GPIO3_25 265
298MX51_PAD_NANDF_D15__NANDF_D15 266
299MX51_PAD_NANDF_D15__PATA_DATA15 267
300MX51_PAD_NANDF_D15__SD3_DAT7 268
301MX51_PAD_NANDF_D14__ECSPI2_SS3 269
302MX51_PAD_NANDF_D14__GPIO3_26 270
303MX51_PAD_NANDF_D14__NANDF_D14 271
304MX51_PAD_NANDF_D14__PATA_DATA14 272
305MX51_PAD_NANDF_D14__SD3_DAT6 273
306MX51_PAD_NANDF_D13__ECSPI2_SS2 274
307MX51_PAD_NANDF_D13__GPIO3_27 275
308MX51_PAD_NANDF_D13__NANDF_D13 276
309MX51_PAD_NANDF_D13__PATA_DATA13 277
310MX51_PAD_NANDF_D13__SD3_DAT5 278
311MX51_PAD_NANDF_D12__ECSPI2_SS1 279
312MX51_PAD_NANDF_D12__GPIO3_28 280
313MX51_PAD_NANDF_D12__NANDF_D12 281
314MX51_PAD_NANDF_D12__PATA_DATA12 282
315MX51_PAD_NANDF_D12__SD3_DAT4 283
316MX51_PAD_NANDF_D11__FEC_RX_DV 284
317MX51_PAD_NANDF_D11__GPIO3_29 285
318MX51_PAD_NANDF_D11__NANDF_D11 286
319MX51_PAD_NANDF_D11__PATA_DATA11 287
320MX51_PAD_NANDF_D11__SD3_DATA3 288
321MX51_PAD_NANDF_D10__GPIO3_30 289
322MX51_PAD_NANDF_D10__NANDF_D10 290
323MX51_PAD_NANDF_D10__PATA_DATA10 291
324MX51_PAD_NANDF_D10__SD3_DATA2 292
325MX51_PAD_NANDF_D9__FEC_RDATA0 293
326MX51_PAD_NANDF_D9__GPIO3_31 294
327MX51_PAD_NANDF_D9__NANDF_D9 295
328MX51_PAD_NANDF_D9__PATA_DATA9 296
329MX51_PAD_NANDF_D9__SD3_DATA1 297
330MX51_PAD_NANDF_D8__FEC_TDATA0 298
331MX51_PAD_NANDF_D8__GPIO4_0 299
332MX51_PAD_NANDF_D8__NANDF_D8 300
333MX51_PAD_NANDF_D8__PATA_DATA8 301
334MX51_PAD_NANDF_D8__SD3_DATA0 302
335MX51_PAD_NANDF_D7__GPIO4_1 303
336MX51_PAD_NANDF_D7__NANDF_D7 304
337MX51_PAD_NANDF_D7__PATA_DATA7 305
338MX51_PAD_NANDF_D7__USBH3_DATA0 306
339MX51_PAD_NANDF_D6__GPIO4_2 307
340MX51_PAD_NANDF_D6__NANDF_D6 308
341MX51_PAD_NANDF_D6__PATA_DATA6 309
342MX51_PAD_NANDF_D6__SD4_LCTL 310
343MX51_PAD_NANDF_D6__USBH3_DATA1 311
344MX51_PAD_NANDF_D5__GPIO4_3 312
345MX51_PAD_NANDF_D5__NANDF_D5 313
346MX51_PAD_NANDF_D5__PATA_DATA5 314
347MX51_PAD_NANDF_D5__SD4_WP 315
348MX51_PAD_NANDF_D5__USBH3_DATA2 316
349MX51_PAD_NANDF_D4__GPIO4_4 317
350MX51_PAD_NANDF_D4__NANDF_D4 318
351MX51_PAD_NANDF_D4__PATA_DATA4 319
352MX51_PAD_NANDF_D4__SD4_CD 320
353MX51_PAD_NANDF_D4__USBH3_DATA3 321
354MX51_PAD_NANDF_D3__GPIO4_5 322
355MX51_PAD_NANDF_D3__NANDF_D3 323
356MX51_PAD_NANDF_D3__PATA_DATA3 324
357MX51_PAD_NANDF_D3__SD4_DAT4 325
358MX51_PAD_NANDF_D3__USBH3_DATA4 326
359MX51_PAD_NANDF_D2__GPIO4_6 327
360MX51_PAD_NANDF_D2__NANDF_D2 328
361MX51_PAD_NANDF_D2__PATA_DATA2 329
362MX51_PAD_NANDF_D2__SD4_DAT5 330
363MX51_PAD_NANDF_D2__USBH3_DATA5 331
364MX51_PAD_NANDF_D1__GPIO4_7 332
365MX51_PAD_NANDF_D1__NANDF_D1 333
366MX51_PAD_NANDF_D1__PATA_DATA1 334
367MX51_PAD_NANDF_D1__SD4_DAT6 335
368MX51_PAD_NANDF_D1__USBH3_DATA6 336
369MX51_PAD_NANDF_D0__GPIO4_8 337
370MX51_PAD_NANDF_D0__NANDF_D0 338
371MX51_PAD_NANDF_D0__PATA_DATA0 339
372MX51_PAD_NANDF_D0__SD4_DAT7 340
373MX51_PAD_NANDF_D0__USBH3_DATA7 341
374MX51_PAD_CSI1_D8__CSI1_D8 342
375MX51_PAD_CSI1_D8__GPIO3_12 343
376MX51_PAD_CSI1_D9__CSI1_D9 344
377MX51_PAD_CSI1_D9__GPIO3_13 345
378MX51_PAD_CSI1_D10__CSI1_D10 346
379MX51_PAD_CSI1_D11__CSI1_D11 347
380MX51_PAD_CSI1_D12__CSI1_D12 348
381MX51_PAD_CSI1_D13__CSI1_D13 349
382MX51_PAD_CSI1_D14__CSI1_D14 350
383MX51_PAD_CSI1_D15__CSI1_D15 351
384MX51_PAD_CSI1_D16__CSI1_D16 352
385MX51_PAD_CSI1_D17__CSI1_D17 353
386MX51_PAD_CSI1_D18__CSI1_D18 354
387MX51_PAD_CSI1_D19__CSI1_D19 355
388MX51_PAD_CSI1_VSYNC__CSI1_VSYNC 356
389MX51_PAD_CSI1_VSYNC__GPIO3_14 357
390MX51_PAD_CSI1_HSYNC__CSI1_HSYNC 358
391MX51_PAD_CSI1_HSYNC__GPIO3_15 359
392MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK 360
393MX51_PAD_CSI1_MCLK__CSI1_MCLK 361
394MX51_PAD_CSI2_D12__CSI2_D12 362
395MX51_PAD_CSI2_D12__GPIO4_9 363
396MX51_PAD_CSI2_D13__CSI2_D13 364
397MX51_PAD_CSI2_D13__GPIO4_10 365
398MX51_PAD_CSI2_D14__CSI2_D14 366
399MX51_PAD_CSI2_D15__CSI2_D15 367
400MX51_PAD_CSI2_D16__CSI2_D16 368
401MX51_PAD_CSI2_D17__CSI2_D17 369
402MX51_PAD_CSI2_D18__CSI2_D18 370
403MX51_PAD_CSI2_D18__GPIO4_11 371
404MX51_PAD_CSI2_D19__CSI2_D19 372
405MX51_PAD_CSI2_D19__GPIO4_12 373
406MX51_PAD_CSI2_VSYNC__CSI2_VSYNC 374
407MX51_PAD_CSI2_VSYNC__GPIO4_13 375
408MX51_PAD_CSI2_HSYNC__CSI2_HSYNC 376
409MX51_PAD_CSI2_HSYNC__GPIO4_14 377
410MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK 378
411MX51_PAD_CSI2_PIXCLK__GPIO4_15 379
412MX51_PAD_I2C1_CLK__GPIO4_16 380
413MX51_PAD_I2C1_CLK__I2C1_CLK 381
414MX51_PAD_I2C1_DAT__GPIO4_17 382
415MX51_PAD_I2C1_DAT__I2C1_DAT 383
416MX51_PAD_AUD3_BB_TXD__AUD3_TXD 384
417MX51_PAD_AUD3_BB_TXD__GPIO4_18 385
418MX51_PAD_AUD3_BB_RXD__AUD3_RXD 386
419MX51_PAD_AUD3_BB_RXD__GPIO4_19 387
420MX51_PAD_AUD3_BB_RXD__UART3_RXD 388
421MX51_PAD_AUD3_BB_CK__AUD3_TXC 389
422MX51_PAD_AUD3_BB_CK__GPIO4_20 390
423MX51_PAD_AUD3_BB_FS__AUD3_TXFS 391
424MX51_PAD_AUD3_BB_FS__GPIO4_21 392
425MX51_PAD_AUD3_BB_FS__UART3_TXD 393
426MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 394
427MX51_PAD_CSPI1_MOSI__GPIO4_22 395
428MX51_PAD_CSPI1_MOSI__I2C1_SDA 396
429MX51_PAD_CSPI1_MISO__AUD4_RXD 397
430MX51_PAD_CSPI1_MISO__ECSPI1_MISO 398
431MX51_PAD_CSPI1_MISO__GPIO4_23 399
432MX51_PAD_CSPI1_SS0__AUD4_TXC 400
433MX51_PAD_CSPI1_SS0__ECSPI1_SS0 401
434MX51_PAD_CSPI1_SS0__GPIO4_24 402
435MX51_PAD_CSPI1_SS1__AUD4_TXD 403
436MX51_PAD_CSPI1_SS1__ECSPI1_SS1 404
437MX51_PAD_CSPI1_SS1__GPIO4_25 405
438MX51_PAD_CSPI1_RDY__AUD4_TXFS 406
439MX51_PAD_CSPI1_RDY__ECSPI1_RDY 407
440MX51_PAD_CSPI1_RDY__GPIO4_26 408
441MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 409
442MX51_PAD_CSPI1_SCLK__GPIO4_27 410
443MX51_PAD_CSPI1_SCLK__I2C1_SCL 411
444MX51_PAD_UART1_RXD__GPIO4_28 412
445MX51_PAD_UART1_RXD__UART1_RXD 413
446MX51_PAD_UART1_TXD__GPIO4_29 414
447MX51_PAD_UART1_TXD__PWM2_PWMO 415
448MX51_PAD_UART1_TXD__UART1_TXD 416
449MX51_PAD_UART1_RTS__GPIO4_30 417
450MX51_PAD_UART1_RTS__UART1_RTS 418
451MX51_PAD_UART1_CTS__GPIO4_31 419
452MX51_PAD_UART1_CTS__UART1_CTS 420
453MX51_PAD_UART2_RXD__FIRI_TXD 421
454MX51_PAD_UART2_RXD__GPIO1_20 422
455MX51_PAD_UART2_RXD__UART2_RXD 423
456MX51_PAD_UART2_TXD__FIRI_RXD 424
457MX51_PAD_UART2_TXD__GPIO1_21 425
458MX51_PAD_UART2_TXD__UART2_TXD 426
459MX51_PAD_UART3_RXD__CSI1_D0 427
460MX51_PAD_UART3_RXD__GPIO1_22 428
461MX51_PAD_UART3_RXD__UART1_DTR 429
462MX51_PAD_UART3_RXD__UART3_RXD 430
463MX51_PAD_UART3_TXD__CSI1_D1 431
464MX51_PAD_UART3_TXD__GPIO1_23 432
465MX51_PAD_UART3_TXD__UART1_DSR 433
466MX51_PAD_UART3_TXD__UART3_TXD 434
467MX51_PAD_OWIRE_LINE__GPIO1_24 435
468MX51_PAD_OWIRE_LINE__OWIRE_LINE 436
469MX51_PAD_OWIRE_LINE__SPDIF_OUT 437
470MX51_PAD_KEY_ROW0__KEY_ROW0 438
471MX51_PAD_KEY_ROW1__KEY_ROW1 439
472MX51_PAD_KEY_ROW2__KEY_ROW2 440
473MX51_PAD_KEY_ROW3__KEY_ROW3 441
474MX51_PAD_KEY_COL0__KEY_COL0 442
475MX51_PAD_KEY_COL0__PLL1_BYP 443
476MX51_PAD_KEY_COL1__KEY_COL1 444
477MX51_PAD_KEY_COL1__PLL2_BYP 445
478MX51_PAD_KEY_COL2__KEY_COL2 446
479MX51_PAD_KEY_COL2__PLL3_BYP 447
480MX51_PAD_KEY_COL3__KEY_COL3 448
481MX51_PAD_KEY_COL4__I2C2_SCL 449
482MX51_PAD_KEY_COL4__KEY_COL4 450
483MX51_PAD_KEY_COL4__SPDIF_OUT1 451
484MX51_PAD_KEY_COL4__UART1_RI 452
485MX51_PAD_KEY_COL4__UART3_RTS 453
486MX51_PAD_KEY_COL5__I2C2_SDA 454
487MX51_PAD_KEY_COL5__KEY_COL5 455
488MX51_PAD_KEY_COL5__UART1_DCD 456
489MX51_PAD_KEY_COL5__UART3_CTS 457
490MX51_PAD_USBH1_CLK__CSPI_SCLK 458
491MX51_PAD_USBH1_CLK__GPIO1_25 459
492MX51_PAD_USBH1_CLK__I2C2_SCL 460
493MX51_PAD_USBH1_CLK__USBH1_CLK 461
494MX51_PAD_USBH1_DIR__CSPI_MOSI 462
495MX51_PAD_USBH1_DIR__GPIO1_26 463
496MX51_PAD_USBH1_DIR__I2C2_SDA 464
497MX51_PAD_USBH1_DIR__USBH1_DIR 465
498MX51_PAD_USBH1_STP__CSPI_RDY 466
499MX51_PAD_USBH1_STP__GPIO1_27 467
500MX51_PAD_USBH1_STP__UART3_RXD 468
501MX51_PAD_USBH1_STP__USBH1_STP 469
502MX51_PAD_USBH1_NXT__CSPI_MISO 470
503MX51_PAD_USBH1_NXT__GPIO1_28 471
504MX51_PAD_USBH1_NXT__UART3_TXD 472
505MX51_PAD_USBH1_NXT__USBH1_NXT 473
506MX51_PAD_USBH1_DATA0__GPIO1_11 474
507MX51_PAD_USBH1_DATA0__UART2_CTS 475
508MX51_PAD_USBH1_DATA0__USBH1_DATA0 476
509MX51_PAD_USBH1_DATA1__GPIO1_12 477
510MX51_PAD_USBH1_DATA1__UART2_RXD 478
511MX51_PAD_USBH1_DATA1__USBH1_DATA1 479
512MX51_PAD_USBH1_DATA2__GPIO1_13 480
513MX51_PAD_USBH1_DATA2__UART2_TXD 481
514MX51_PAD_USBH1_DATA2__USBH1_DATA2 482
515MX51_PAD_USBH1_DATA3__GPIO1_14 483
516MX51_PAD_USBH1_DATA3__UART2_RTS 484
517MX51_PAD_USBH1_DATA3__USBH1_DATA3 485
518MX51_PAD_USBH1_DATA4__CSPI_SS0 486
519MX51_PAD_USBH1_DATA4__GPIO1_15 487
520MX51_PAD_USBH1_DATA4__USBH1_DATA4 488
521MX51_PAD_USBH1_DATA5__CSPI_SS1 489
522MX51_PAD_USBH1_DATA5__GPIO1_16 490
523MX51_PAD_USBH1_DATA5__USBH1_DATA5 491
524MX51_PAD_USBH1_DATA6__CSPI_SS3 492
525MX51_PAD_USBH1_DATA6__GPIO1_17 493
526MX51_PAD_USBH1_DATA6__USBH1_DATA6 494
527MX51_PAD_USBH1_DATA7__ECSPI1_SS3 495
528MX51_PAD_USBH1_DATA7__ECSPI2_SS3 496
529MX51_PAD_USBH1_DATA7__GPIO1_18 497
530MX51_PAD_USBH1_DATA7__USBH1_DATA7 498
531MX51_PAD_DI1_PIN11__DI1_PIN11 499
532MX51_PAD_DI1_PIN11__ECSPI1_SS2 500
533MX51_PAD_DI1_PIN11__GPIO3_0 501
534MX51_PAD_DI1_PIN12__DI1_PIN12 502
535MX51_PAD_DI1_PIN12__GPIO3_1 503
536MX51_PAD_DI1_PIN13__DI1_PIN13 504
537MX51_PAD_DI1_PIN13__GPIO3_2 505
538MX51_PAD_DI1_D0_CS__DI1_D0_CS 506
539MX51_PAD_DI1_D0_CS__GPIO3_3 507
540MX51_PAD_DI1_D1_CS__DI1_D1_CS 508
541MX51_PAD_DI1_D1_CS__DISP1_PIN14 509
542MX51_PAD_DI1_D1_CS__DISP1_PIN5 510
543MX51_PAD_DI1_D1_CS__GPIO3_4 511
544MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 512
545MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN 513
546MX51_PAD_DISPB2_SER_DIN__GPIO3_5 514
547MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 515
548MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO 516
549MX51_PAD_DISPB2_SER_DIO__GPIO3_6 517
550MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 518
551MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 519
552MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK 520
553MX51_PAD_DISPB2_SER_CLK__GPIO3_7 521
554MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK 522
555MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 523
556MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 524
557MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS 525
558MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS 526
559MX51_PAD_DISPB2_SER_RS__GPIO3_8 527
560MX51_PAD_DISP1_DAT0__DISP1_DAT0 528
561MX51_PAD_DISP1_DAT1__DISP1_DAT1 529
562MX51_PAD_DISP1_DAT2__DISP1_DAT2 530
563MX51_PAD_DISP1_DAT3__DISP1_DAT3 531
564MX51_PAD_DISP1_DAT4__DISP1_DAT4 532
565MX51_PAD_DISP1_DAT5__DISP1_DAT5 533
566MX51_PAD_DISP1_DAT6__BOOT_USB_SRC 534
567MX51_PAD_DISP1_DAT6__DISP1_DAT6 535
568MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG 536
569MX51_PAD_DISP1_DAT7__DISP1_DAT7 537
570MX51_PAD_DISP1_DAT8__BOOT_SRC0 538
571MX51_PAD_DISP1_DAT8__DISP1_DAT8 539
572MX51_PAD_DISP1_DAT9__BOOT_SRC1 540
573MX51_PAD_DISP1_DAT9__DISP1_DAT9 541
574MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE 542
575MX51_PAD_DISP1_DAT10__DISP1_DAT10 543
576MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 544
577MX51_PAD_DISP1_DAT11__DISP1_DAT11 545
578MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL 546
579MX51_PAD_DISP1_DAT12__DISP1_DAT12 547
580MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 548
581MX51_PAD_DISP1_DAT13__DISP1_DAT13 549
582MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 550
583MX51_PAD_DISP1_DAT14__DISP1_DAT14 551
584MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH 552
585MX51_PAD_DISP1_DAT15__DISP1_DAT15 553
586MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 554
587MX51_PAD_DISP1_DAT16__DISP1_DAT16 555
588MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 556
589MX51_PAD_DISP1_DAT17__DISP1_DAT17 557
590MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 558
591MX51_PAD_DISP1_DAT18__DISP1_DAT18 559
592MX51_PAD_DISP1_DAT18__DISP2_PIN11 560
593MX51_PAD_DISP1_DAT18__DISP2_PIN5 561
594MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 562
595MX51_PAD_DISP1_DAT19__DISP1_DAT19 563
596MX51_PAD_DISP1_DAT19__DISP2_PIN12 564
597MX51_PAD_DISP1_DAT19__DISP2_PIN6 565
598MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 566
599MX51_PAD_DISP1_DAT20__DISP1_DAT20 567
600MX51_PAD_DISP1_DAT20__DISP2_PIN13 568
601MX51_PAD_DISP1_DAT20__DISP2_PIN7 569
602MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 570
603MX51_PAD_DISP1_DAT21__DISP1_DAT21 571
604MX51_PAD_DISP1_DAT21__DISP2_PIN14 572
605MX51_PAD_DISP1_DAT21__DISP2_PIN8 573
606MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 574
607MX51_PAD_DISP1_DAT22__DISP1_DAT22 575
608MX51_PAD_DISP1_DAT22__DISP2_D0_CS 576
609MX51_PAD_DISP1_DAT22__DISP2_DAT16 577
610MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 578
611MX51_PAD_DISP1_DAT23__DISP1_DAT23 579
612MX51_PAD_DISP1_DAT23__DISP2_D1_CS 580
613MX51_PAD_DISP1_DAT23__DISP2_DAT17 581
614MX51_PAD_DISP1_DAT23__DISP2_SER_CS 582
615MX51_PAD_DI1_PIN3__DI1_PIN3 583
616MX51_PAD_DI1_PIN2__DI1_PIN2 584
617MX51_PAD_DI_GP2__DISP1_SER_CLK 585
618MX51_PAD_DI_GP2__DISP2_WAIT 586
619MX51_PAD_DI_GP3__CSI1_DATA_EN 587
620MX51_PAD_DI_GP3__DISP1_SER_DIO 588
621MX51_PAD_DI_GP3__FEC_TX_ER 589
622MX51_PAD_DI2_PIN4__CSI2_DATA_EN 590
623MX51_PAD_DI2_PIN4__DI2_PIN4 591
624MX51_PAD_DI2_PIN4__FEC_CRS 592
625MX51_PAD_DI2_PIN2__DI2_PIN2 593
626MX51_PAD_DI2_PIN2__FEC_MDC 594
627MX51_PAD_DI2_PIN3__DI2_PIN3 595
628MX51_PAD_DI2_PIN3__FEC_MDIO 596
629MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 597
630MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 598
631MX51_PAD_DI_GP4__DI2_PIN15 599
632MX51_PAD_DI_GP4__DISP1_SER_DIN 600
633MX51_PAD_DI_GP4__DISP2_PIN1 601
634MX51_PAD_DI_GP4__FEC_RDATA2 602
635MX51_PAD_DISP2_DAT0__DISP2_DAT0 603
636MX51_PAD_DISP2_DAT0__FEC_RDATA3 604
637MX51_PAD_DISP2_DAT0__KEY_COL6 605
638MX51_PAD_DISP2_DAT0__UART3_RXD 606
639MX51_PAD_DISP2_DAT0__USBH3_CLK 607
640MX51_PAD_DISP2_DAT1__DISP2_DAT1 608
641MX51_PAD_DISP2_DAT1__FEC_RX_ER 609
642MX51_PAD_DISP2_DAT1__KEY_COL7 610
643MX51_PAD_DISP2_DAT1__UART3_TXD 611
644MX51_PAD_DISP2_DAT1__USBH3_DIR 612
645MX51_PAD_DISP2_DAT2__DISP2_DAT2 613
646MX51_PAD_DISP2_DAT3__DISP2_DAT3 614
647MX51_PAD_DISP2_DAT4__DISP2_DAT4 615
648MX51_PAD_DISP2_DAT5__DISP2_DAT5 616
649MX51_PAD_DISP2_DAT6__DISP2_DAT6 617
650MX51_PAD_DISP2_DAT6__FEC_TDATA1 618
651MX51_PAD_DISP2_DAT6__GPIO1_19 619
652MX51_PAD_DISP2_DAT6__KEY_ROW4 620
653MX51_PAD_DISP2_DAT6__USBH3_STP 621
654MX51_PAD_DISP2_DAT7__DISP2_DAT7 622
655MX51_PAD_DISP2_DAT7__FEC_TDATA2 623
656MX51_PAD_DISP2_DAT7__GPIO1_29 624
657MX51_PAD_DISP2_DAT7__KEY_ROW5 625
658MX51_PAD_DISP2_DAT7__USBH3_NXT 626
659MX51_PAD_DISP2_DAT8__DISP2_DAT8 627
660MX51_PAD_DISP2_DAT8__FEC_TDATA3 628
661MX51_PAD_DISP2_DAT8__GPIO1_30 629
662MX51_PAD_DISP2_DAT8__KEY_ROW6 630
663MX51_PAD_DISP2_DAT8__USBH3_DATA0 631
664MX51_PAD_DISP2_DAT9__AUD6_RXC 632
665MX51_PAD_DISP2_DAT9__DISP2_DAT9 633
666MX51_PAD_DISP2_DAT9__FEC_TX_EN 634
667MX51_PAD_DISP2_DAT9__GPIO1_31 635
668MX51_PAD_DISP2_DAT9__USBH3_DATA1 636
669MX51_PAD_DISP2_DAT10__DISP2_DAT10 637
670MX51_PAD_DISP2_DAT10__DISP2_SER_CS 638
671MX51_PAD_DISP2_DAT10__FEC_COL 639
672MX51_PAD_DISP2_DAT10__KEY_ROW7 640
673MX51_PAD_DISP2_DAT10__USBH3_DATA2 641
674MX51_PAD_DISP2_DAT11__AUD6_TXD 642
675MX51_PAD_DISP2_DAT11__DISP2_DAT11 643
676MX51_PAD_DISP2_DAT11__FEC_RX_CLK 644
677MX51_PAD_DISP2_DAT11__GPIO1_10 645
678MX51_PAD_DISP2_DAT11__USBH3_DATA3 646
679MX51_PAD_DISP2_DAT12__AUD6_RXD 647
680MX51_PAD_DISP2_DAT12__DISP2_DAT12 648
681MX51_PAD_DISP2_DAT12__FEC_RX_DV 649
682MX51_PAD_DISP2_DAT12__USBH3_DATA4 650
683MX51_PAD_DISP2_DAT13__AUD6_TXC 651
684MX51_PAD_DISP2_DAT13__DISP2_DAT13 652
685MX51_PAD_DISP2_DAT13__FEC_TX_CLK 653
686MX51_PAD_DISP2_DAT13__USBH3_DATA5 654
687MX51_PAD_DISP2_DAT14__AUD6_TXFS 655
688MX51_PAD_DISP2_DAT14__DISP2_DAT14 656
689MX51_PAD_DISP2_DAT14__FEC_RDATA0 657
690MX51_PAD_DISP2_DAT14__USBH3_DATA6 658
691MX51_PAD_DISP2_DAT15__AUD6_RXFS 659
692MX51_PAD_DISP2_DAT15__DISP1_SER_CS 660
693MX51_PAD_DISP2_DAT15__DISP2_DAT15 661
694MX51_PAD_DISP2_DAT15__FEC_TDATA0 662
695MX51_PAD_DISP2_DAT15__USBH3_DATA7 663
696MX51_PAD_SD1_CMD__AUD5_RXFS 664
697MX51_PAD_SD1_CMD__CSPI_MOSI 665
698MX51_PAD_SD1_CMD__SD1_CMD 666
699MX51_PAD_SD1_CLK__AUD5_RXC 667
700MX51_PAD_SD1_CLK__CSPI_SCLK 668
701MX51_PAD_SD1_CLK__SD1_CLK 669
702MX51_PAD_SD1_DATA0__AUD5_TXD 670
703MX51_PAD_SD1_DATA0__CSPI_MISO 671
704MX51_PAD_SD1_DATA0__SD1_DATA0 672
705MX51_PAD_EIM_DA0__EIM_DA0 673
706MX51_PAD_EIM_DA1__EIM_DA1 674
707MX51_PAD_EIM_DA2__EIM_DA2 675
708MX51_PAD_EIM_DA3__EIM_DA3 676
709MX51_PAD_SD1_DATA1__AUD5_RXD 677
710MX51_PAD_SD1_DATA1__SD1_DATA1 678
711MX51_PAD_EIM_DA4__EIM_DA4 679
712MX51_PAD_EIM_DA5__EIM_DA5 680
713MX51_PAD_EIM_DA6__EIM_DA6 681
714MX51_PAD_EIM_DA7__EIM_DA7 682
715MX51_PAD_SD1_DATA2__AUD5_TXC 683
716MX51_PAD_SD1_DATA2__SD1_DATA2 684
717MX51_PAD_EIM_DA10__EIM_DA10 685
718MX51_PAD_EIM_DA11__EIM_DA11 686
719MX51_PAD_EIM_DA8__EIM_DA8 687
720MX51_PAD_EIM_DA9__EIM_DA9 688
721MX51_PAD_SD1_DATA3__AUD5_TXFS 689
722MX51_PAD_SD1_DATA3__CSPI_SS1 690
723MX51_PAD_SD1_DATA3__SD1_DATA3 691
724MX51_PAD_GPIO1_0__CSPI_SS2 692
725MX51_PAD_GPIO1_0__GPIO1_0 693
726MX51_PAD_GPIO1_0__SD1_CD 694
727MX51_PAD_GPIO1_1__CSPI_MISO 695
728MX51_PAD_GPIO1_1__GPIO1_1 696
729MX51_PAD_GPIO1_1__SD1_WP 697
730MX51_PAD_EIM_DA12__EIM_DA12 698
731MX51_PAD_EIM_DA13__EIM_DA13 699
732MX51_PAD_EIM_DA14__EIM_DA14 700
733MX51_PAD_EIM_DA15__EIM_DA15 701
734MX51_PAD_SD2_CMD__CSPI_MOSI 702
735MX51_PAD_SD2_CMD__I2C1_SCL 703
736MX51_PAD_SD2_CMD__SD2_CMD 704
737MX51_PAD_SD2_CLK__CSPI_SCLK 705
738MX51_PAD_SD2_CLK__I2C1_SDA 706
739MX51_PAD_SD2_CLK__SD2_CLK 707
740MX51_PAD_SD2_DATA0__CSPI_MISO 708
741MX51_PAD_SD2_DATA0__SD1_DAT4 709
742MX51_PAD_SD2_DATA0__SD2_DATA0 710
743MX51_PAD_SD2_DATA1__SD1_DAT5 711
744MX51_PAD_SD2_DATA1__SD2_DATA1 712
745MX51_PAD_SD2_DATA1__USBH3_H2_DP 713
746MX51_PAD_SD2_DATA2__SD1_DAT6 714
747MX51_PAD_SD2_DATA2__SD2_DATA2 715
748MX51_PAD_SD2_DATA2__USBH3_H2_DM 716
749MX51_PAD_SD2_DATA3__CSPI_SS2 717
750MX51_PAD_SD2_DATA3__SD1_DAT7 718
751MX51_PAD_SD2_DATA3__SD2_DATA3 719
752MX51_PAD_GPIO1_2__CCM_OUT_2 720
753MX51_PAD_GPIO1_2__GPIO1_2 721
754MX51_PAD_GPIO1_2__I2C2_SCL 722
755MX51_PAD_GPIO1_2__PLL1_BYP 723
756MX51_PAD_GPIO1_2__PWM1_PWMO 724
757MX51_PAD_GPIO1_3__GPIO1_3 725
758MX51_PAD_GPIO1_3__I2C2_SDA 726
759MX51_PAD_GPIO1_3__PLL2_BYP 727
760MX51_PAD_GPIO1_3__PWM2_PWMO 728
761MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ 729
762MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B 730
763MX51_PAD_GPIO1_4__DISP2_EXT_CLK 731
764MX51_PAD_GPIO1_4__EIM_RDY 732
765MX51_PAD_GPIO1_4__GPIO1_4 733
766MX51_PAD_GPIO1_4__WDOG1_WDOG_B 734
767MX51_PAD_GPIO1_5__CSI2_MCLK 735
768MX51_PAD_GPIO1_5__DISP2_PIN16 736
769MX51_PAD_GPIO1_5__GPIO1_5 737
770MX51_PAD_GPIO1_5__WDOG2_WDOG_B 738
771MX51_PAD_GPIO1_6__DISP2_PIN17 739
772MX51_PAD_GPIO1_6__GPIO1_6 740
773MX51_PAD_GPIO1_6__REF_EN_B 741
774MX51_PAD_GPIO1_7__CCM_OUT_0 742
775MX51_PAD_GPIO1_7__GPIO1_7 743
776MX51_PAD_GPIO1_7__SD2_WP 744
777MX51_PAD_GPIO1_7__SPDIF_OUT1 745
778MX51_PAD_GPIO1_8__CSI2_DATA_EN 746
779MX51_PAD_GPIO1_8__GPIO1_8 747
780MX51_PAD_GPIO1_8__SD2_CD 748
781MX51_PAD_GPIO1_8__USBH3_PWR 749
782MX51_PAD_GPIO1_9__CCM_OUT_1 750
783MX51_PAD_GPIO1_9__DISP2_D1_CS 751
784MX51_PAD_GPIO1_9__DISP2_SER_CS 752
785MX51_PAD_GPIO1_9__GPIO1_9 753
786MX51_PAD_GPIO1_9__SD2_LCTL 754
787MX51_PAD_GPIO1_9__USBH3_OC 755
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx53-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx53-pinctrl.txt
new file mode 100644
index 00000000000..ca85ca432ef
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx53-pinctrl.txt
@@ -0,0 +1,1202 @@
1* Freescale IMX53 IOMUX Controller
2
3Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
4and usage.
5
6Required properties:
7- compatible: "fsl,imx53-iomuxc"
8- fsl,pins: two integers array, represents a group of pins mux and config
9 setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
10 pin working on a specific function, CONFIG is the pad setting value like
11 pull-up for this pin. Please refer to imx53 datasheet for the valid pad
12 config settings.
13
14CONFIG bits definition:
15PAD_CTL_HVE (1 << 13)
16PAD_CTL_HYS (1 << 8)
17PAD_CTL_PKE (1 << 7)
18PAD_CTL_PUE (1 << 6)
19PAD_CTL_PUS_100K_DOWN (0 << 4)
20PAD_CTL_PUS_47K_UP (1 << 4)
21PAD_CTL_PUS_100K_UP (2 << 4)
22PAD_CTL_PUS_22K_UP (3 << 4)
23PAD_CTL_ODE (1 << 3)
24PAD_CTL_DSE_LOW (0 << 1)
25PAD_CTL_DSE_MED (1 << 1)
26PAD_CTL_DSE_HIGH (2 << 1)
27PAD_CTL_DSE_MAX (3 << 1)
28PAD_CTL_SRE_FAST (1 << 0)
29PAD_CTL_SRE_SLOW (0 << 0)
30
31See below for available PIN_FUNC_ID for imx53:
32MX53_PAD_GPIO_19__KPP_COL_5 0
33MX53_PAD_GPIO_19__GPIO4_5 1
34MX53_PAD_GPIO_19__CCM_CLKO 2
35MX53_PAD_GPIO_19__SPDIF_OUT1 3
36MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 4
37MX53_PAD_GPIO_19__ECSPI1_RDY 5
38MX53_PAD_GPIO_19__FEC_TDATA_3 6
39MX53_PAD_GPIO_19__SRC_INT_BOOT 7
40MX53_PAD_KEY_COL0__KPP_COL_0 8
41MX53_PAD_KEY_COL0__GPIO4_6 9
42MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 10
43MX53_PAD_KEY_COL0__UART4_TXD_MUX 11
44MX53_PAD_KEY_COL0__ECSPI1_SCLK 12
45MX53_PAD_KEY_COL0__FEC_RDATA_3 13
46MX53_PAD_KEY_COL0__SRC_ANY_PU_RST 14
47MX53_PAD_KEY_ROW0__KPP_ROW_0 15
48MX53_PAD_KEY_ROW0__GPIO4_7 16
49MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 17
50MX53_PAD_KEY_ROW0__UART4_RXD_MUX 18
51MX53_PAD_KEY_ROW0__ECSPI1_MOSI 19
52MX53_PAD_KEY_ROW0__FEC_TX_ER 20
53MX53_PAD_KEY_COL1__KPP_COL_1 21
54MX53_PAD_KEY_COL1__GPIO4_8 22
55MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 23
56MX53_PAD_KEY_COL1__UART5_TXD_MUX 24
57MX53_PAD_KEY_COL1__ECSPI1_MISO 25
58MX53_PAD_KEY_COL1__FEC_RX_CLK 26
59MX53_PAD_KEY_COL1__USBPHY1_TXREADY 27
60MX53_PAD_KEY_ROW1__KPP_ROW_1 28
61MX53_PAD_KEY_ROW1__GPIO4_9 29
62MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 30
63MX53_PAD_KEY_ROW1__UART5_RXD_MUX 31
64MX53_PAD_KEY_ROW1__ECSPI1_SS0 32
65MX53_PAD_KEY_ROW1__FEC_COL 33
66MX53_PAD_KEY_ROW1__USBPHY1_RXVALID 34
67MX53_PAD_KEY_COL2__KPP_COL_2 35
68MX53_PAD_KEY_COL2__GPIO4_10 36
69MX53_PAD_KEY_COL2__CAN1_TXCAN 37
70MX53_PAD_KEY_COL2__FEC_MDIO 38
71MX53_PAD_KEY_COL2__ECSPI1_SS1 39
72MX53_PAD_KEY_COL2__FEC_RDATA_2 40
73MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE 41
74MX53_PAD_KEY_ROW2__KPP_ROW_2 42
75MX53_PAD_KEY_ROW2__GPIO4_11 43
76MX53_PAD_KEY_ROW2__CAN1_RXCAN 44
77MX53_PAD_KEY_ROW2__FEC_MDC 45
78MX53_PAD_KEY_ROW2__ECSPI1_SS2 46
79MX53_PAD_KEY_ROW2__FEC_TDATA_2 47
80MX53_PAD_KEY_ROW2__USBPHY1_RXERROR 48
81MX53_PAD_KEY_COL3__KPP_COL_3 49
82MX53_PAD_KEY_COL3__GPIO4_12 50
83MX53_PAD_KEY_COL3__USBOH3_H2_DP 51
84MX53_PAD_KEY_COL3__SPDIF_IN1 52
85MX53_PAD_KEY_COL3__I2C2_SCL 53
86MX53_PAD_KEY_COL3__ECSPI1_SS3 54
87MX53_PAD_KEY_COL3__FEC_CRS 55
88MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK 56
89MX53_PAD_KEY_ROW3__KPP_ROW_3 57
90MX53_PAD_KEY_ROW3__GPIO4_13 58
91MX53_PAD_KEY_ROW3__USBOH3_H2_DM 59
92MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK 60
93MX53_PAD_KEY_ROW3__I2C2_SDA 61
94MX53_PAD_KEY_ROW3__OSC32K_32K_OUT 62
95MX53_PAD_KEY_ROW3__CCM_PLL4_BYP 63
96MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 64
97MX53_PAD_KEY_COL4__KPP_COL_4 65
98MX53_PAD_KEY_COL4__GPIO4_14 66
99MX53_PAD_KEY_COL4__CAN2_TXCAN 67
100MX53_PAD_KEY_COL4__IPU_SISG_4 68
101MX53_PAD_KEY_COL4__UART5_RTS 69
102MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC 70
103MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 71
104MX53_PAD_KEY_ROW4__KPP_ROW_4 72
105MX53_PAD_KEY_ROW4__GPIO4_15 73
106MX53_PAD_KEY_ROW4__CAN2_RXCAN 74
107MX53_PAD_KEY_ROW4__IPU_SISG_5 75
108MX53_PAD_KEY_ROW4__UART5_CTS 76
109MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR 77
110MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID 78
111MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 79
112MX53_PAD_DI0_DISP_CLK__GPIO4_16 80
113MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR 81
114MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 82
115MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 83
116MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID 84
117MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 85
118MX53_PAD_DI0_PIN15__GPIO4_17 86
119MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC 87
120MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 88
121MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 89
122MX53_PAD_DI0_PIN15__USBPHY1_BVALID 90
123MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 91
124MX53_PAD_DI0_PIN2__GPIO4_18 92
125MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD 93
126MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 94
127MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 95
128MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION 96
129MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 97
130MX53_PAD_DI0_PIN3__GPIO4_19 98
131MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS 99
132MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 100
133MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 101
134MX53_PAD_DI0_PIN3__USBPHY1_IDDIG 102
135MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 103
136MX53_PAD_DI0_PIN4__GPIO4_20 104
137MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD 105
138MX53_PAD_DI0_PIN4__ESDHC1_WP 106
139MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD 107
140MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 108
141MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT 109
142MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 110
143MX53_PAD_DISP0_DAT0__GPIO4_21 111
144MX53_PAD_DISP0_DAT0__CSPI_SCLK 112
145MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 113
146MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN 114
147MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 115
148MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY 116
149MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 117
150MX53_PAD_DISP0_DAT1__GPIO4_22 118
151MX53_PAD_DISP0_DAT1__CSPI_MOSI 119
152MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 120
153MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL 121
154MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 122
155MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID 123
156MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 124
157MX53_PAD_DISP0_DAT2__GPIO4_23 125
158MX53_PAD_DISP0_DAT2__CSPI_MISO 126
159MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 127
160MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE 128
161MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 129
162MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE 130
163MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 131
164MX53_PAD_DISP0_DAT3__GPIO4_24 132
165MX53_PAD_DISP0_DAT3__CSPI_SS0 133
166MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 134
167MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR 135
168MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 136
169MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR 137
170MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 138
171MX53_PAD_DISP0_DAT4__GPIO4_25 139
172MX53_PAD_DISP0_DAT4__CSPI_SS1 140
173MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 141
174MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB 142
175MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 143
176MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK 144
177MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 145
178MX53_PAD_DISP0_DAT5__GPIO4_26 146
179MX53_PAD_DISP0_DAT5__CSPI_SS2 147
180MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 148
181MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS 149
182MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 150
183MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 151
184MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 152
185MX53_PAD_DISP0_DAT6__GPIO4_27 153
186MX53_PAD_DISP0_DAT6__CSPI_SS3 154
187MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 155
188MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE 156
189MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 157
190MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 158
191MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 159
192MX53_PAD_DISP0_DAT7__GPIO4_28 160
193MX53_PAD_DISP0_DAT7__CSPI_RDY 161
194MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 162
195MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 163
196MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 164
197MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID 165
198MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 166
199MX53_PAD_DISP0_DAT8__GPIO4_29 167
200MX53_PAD_DISP0_DAT8__PWM1_PWMO 168
201MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B 169
202MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 170
203MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 171
204MX53_PAD_DISP0_DAT8__USBPHY2_AVALID 172
205MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 173
206MX53_PAD_DISP0_DAT9__GPIO4_30 174
207MX53_PAD_DISP0_DAT9__PWM2_PWMO 175
208MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B 176
209MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 177
210MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 178
211MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 179
212MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 180
213MX53_PAD_DISP0_DAT10__GPIO4_31 181
214MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP 182
215MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 183
216MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 184
217MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 185
218MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 186
219MX53_PAD_DISP0_DAT11__GPIO5_5 187
220MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT 188
221MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 189
222MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 190
223MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 191
224MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 192
225MX53_PAD_DISP0_DAT12__GPIO5_6 193
226MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK 194
227MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 195
228MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 196
229MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 197
230MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 198
231MX53_PAD_DISP0_DAT13__GPIO5_7 199
232MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS 200
233MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 201
234MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 202
235MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 203
236MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 204
237MX53_PAD_DISP0_DAT14__GPIO5_8 205
238MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC 206
239MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 207
240MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 208
241MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 209
242MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 210
243MX53_PAD_DISP0_DAT15__GPIO5_9 211
244MX53_PAD_DISP0_DAT15__ECSPI1_SS1 212
245MX53_PAD_DISP0_DAT15__ECSPI2_SS1 213
246MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 214
247MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 215
248MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 216
249MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 217
250MX53_PAD_DISP0_DAT16__GPIO5_10 218
251MX53_PAD_DISP0_DAT16__ECSPI2_MOSI 219
252MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC 220
253MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 221
254MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 222
255MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 223
256MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 224
257MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 225
258MX53_PAD_DISP0_DAT17__GPIO5_11 226
259MX53_PAD_DISP0_DAT17__ECSPI2_MISO 227
260MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD 228
261MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 229
262MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 230
263MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 231
264MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 232
265MX53_PAD_DISP0_DAT18__GPIO5_12 233
266MX53_PAD_DISP0_DAT18__ECSPI2_SS0 234
267MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS 235
268MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS 236
269MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 237
270MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 238
271MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 239
272MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 240
273MX53_PAD_DISP0_DAT19__GPIO5_13 241
274MX53_PAD_DISP0_DAT19__ECSPI2_SCLK 242
275MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD 243
276MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC 244
277MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 245
278MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 246
279MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 247
280MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 248
281MX53_PAD_DISP0_DAT20__GPIO5_14 249
282MX53_PAD_DISP0_DAT20__ECSPI1_SCLK 250
283MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC 251
284MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 252
285MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 253
286MX53_PAD_DISP0_DAT20__SATA_PHY_TDI 254
287MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 255
288MX53_PAD_DISP0_DAT21__GPIO5_15 256
289MX53_PAD_DISP0_DAT21__ECSPI1_MOSI 257
290MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD 258
291MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 259
292MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 260
293MX53_PAD_DISP0_DAT21__SATA_PHY_TDO 261
294MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 262
295MX53_PAD_DISP0_DAT22__GPIO5_16 263
296MX53_PAD_DISP0_DAT22__ECSPI1_MISO 264
297MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS 265
298MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 266
299MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 267
300MX53_PAD_DISP0_DAT22__SATA_PHY_TCK 268
301MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 269
302MX53_PAD_DISP0_DAT23__GPIO5_17 270
303MX53_PAD_DISP0_DAT23__ECSPI1_SS0 271
304MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD 272
305MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 273
306MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 274
307MX53_PAD_DISP0_DAT23__SATA_PHY_TMS 275
308MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 276
309MX53_PAD_CSI0_PIXCLK__GPIO5_18 277
310MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 278
311MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 279
312MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 280
313MX53_PAD_CSI0_MCLK__GPIO5_19 281
314MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK 282
315MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 283
316MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 284
317MX53_PAD_CSI0_MCLK__TPIU_TRCTL 285
318MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 286
319MX53_PAD_CSI0_DATA_EN__GPIO5_20 287
320MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 288
321MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 289
322MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK 290
323MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 291
324MX53_PAD_CSI0_VSYNC__GPIO5_21 292
325MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 293
326MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 294
327MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 295
328MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 296
329MX53_PAD_CSI0_DAT4__GPIO5_22 297
330MX53_PAD_CSI0_DAT4__KPP_COL_5 298
331MX53_PAD_CSI0_DAT4__ECSPI1_SCLK 299
332MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP 300
333MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 301
334MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 302
335MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 303
336MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 304
337MX53_PAD_CSI0_DAT5__GPIO5_23 305
338MX53_PAD_CSI0_DAT5__KPP_ROW_5 306
339MX53_PAD_CSI0_DAT5__ECSPI1_MOSI 307
340MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT 308
341MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 309
342MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 310
343MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 311
344MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 312
345MX53_PAD_CSI0_DAT6__GPIO5_24 313
346MX53_PAD_CSI0_DAT6__KPP_COL_6 314
347MX53_PAD_CSI0_DAT6__ECSPI1_MISO 315
348MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK 316
349MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 317
350MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 318
351MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 319
352MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 320
353MX53_PAD_CSI0_DAT7__GPIO5_25 321
354MX53_PAD_CSI0_DAT7__KPP_ROW_6 322
355MX53_PAD_CSI0_DAT7__ECSPI1_SS0 323
356MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR 324
357MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 325
358MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 326
359MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 327
360MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 328
361MX53_PAD_CSI0_DAT8__GPIO5_26 329
362MX53_PAD_CSI0_DAT8__KPP_COL_7 330
363MX53_PAD_CSI0_DAT8__ECSPI2_SCLK 331
364MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC 332
365MX53_PAD_CSI0_DAT8__I2C1_SDA 333
366MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 334
367MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 335
368MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 336
369MX53_PAD_CSI0_DAT9__GPIO5_27 337
370MX53_PAD_CSI0_DAT9__KPP_ROW_7 338
371MX53_PAD_CSI0_DAT9__ECSPI2_MOSI 339
372MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR 340
373MX53_PAD_CSI0_DAT9__I2C1_SCL 341
374MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 342
375MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 343
376MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 344
377MX53_PAD_CSI0_DAT10__GPIO5_28 345
378MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 346
379MX53_PAD_CSI0_DAT10__ECSPI2_MISO 347
380MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC 348
381MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 349
382MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 350
383MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 351
384MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 352
385MX53_PAD_CSI0_DAT11__GPIO5_29 353
386MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 354
387MX53_PAD_CSI0_DAT11__ECSPI2_SS0 355
388MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS 356
389MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 357
390MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 358
391MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 359
392MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 360
393MX53_PAD_CSI0_DAT12__GPIO5_30 361
394MX53_PAD_CSI0_DAT12__UART4_TXD_MUX 362
395MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 363
396MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 364
397MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 365
398MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 366
399MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 367
400MX53_PAD_CSI0_DAT13__GPIO5_31 368
401MX53_PAD_CSI0_DAT13__UART4_RXD_MUX 369
402MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 370
403MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 371
404MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 372
405MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 373
406MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 374
407MX53_PAD_CSI0_DAT14__GPIO6_0 375
408MX53_PAD_CSI0_DAT14__UART5_TXD_MUX 376
409MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 377
410MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 378
411MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 379
412MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 380
413MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 381
414MX53_PAD_CSI0_DAT15__GPIO6_1 382
415MX53_PAD_CSI0_DAT15__UART5_RXD_MUX 383
416MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 384
417MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 385
418MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 386
419MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 387
420MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 388
421MX53_PAD_CSI0_DAT16__GPIO6_2 389
422MX53_PAD_CSI0_DAT16__UART4_RTS 390
423MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 391
424MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 392
425MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 393
426MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 394
427MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 395
428MX53_PAD_CSI0_DAT17__GPIO6_3 396
429MX53_PAD_CSI0_DAT17__UART4_CTS 397
430MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 398
431MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 399
432MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 400
433MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 401
434MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 402
435MX53_PAD_CSI0_DAT18__GPIO6_4 403
436MX53_PAD_CSI0_DAT18__UART5_RTS 404
437MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 405
438MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 406
439MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 407
440MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 408
441MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 409
442MX53_PAD_CSI0_DAT19__GPIO6_5 410
443MX53_PAD_CSI0_DAT19__UART5_CTS 411
444MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 412
445MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 413
446MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 414
447MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK 415
448MX53_PAD_EIM_A25__EMI_WEIM_A_25 416
449MX53_PAD_EIM_A25__GPIO5_2 417
450MX53_PAD_EIM_A25__ECSPI2_RDY 418
451MX53_PAD_EIM_A25__IPU_DI1_PIN12 419
452MX53_PAD_EIM_A25__CSPI_SS1 420
453MX53_PAD_EIM_A25__IPU_DI0_D1_CS 421
454MX53_PAD_EIM_A25__USBPHY1_BISTOK 422
455MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 423
456MX53_PAD_EIM_EB2__GPIO2_30 424
457MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK 425
458MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS 426
459MX53_PAD_EIM_EB2__ECSPI1_SS0 427
460MX53_PAD_EIM_EB2__I2C2_SCL 428
461MX53_PAD_EIM_D16__EMI_WEIM_D_16 429
462MX53_PAD_EIM_D16__GPIO3_16 430
463MX53_PAD_EIM_D16__IPU_DI0_PIN5 431
464MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK 432
465MX53_PAD_EIM_D16__ECSPI1_SCLK 433
466MX53_PAD_EIM_D16__I2C2_SDA 434
467MX53_PAD_EIM_D17__EMI_WEIM_D_17 435
468MX53_PAD_EIM_D17__GPIO3_17 436
469MX53_PAD_EIM_D17__IPU_DI0_PIN6 437
470MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN 438
471MX53_PAD_EIM_D17__ECSPI1_MISO 439
472MX53_PAD_EIM_D17__I2C3_SCL 440
473MX53_PAD_EIM_D18__EMI_WEIM_D_18 441
474MX53_PAD_EIM_D18__GPIO3_18 442
475MX53_PAD_EIM_D18__IPU_DI0_PIN7 443
476MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO 444
477MX53_PAD_EIM_D18__ECSPI1_MOSI 445
478MX53_PAD_EIM_D18__I2C3_SDA 446
479MX53_PAD_EIM_D18__IPU_DI1_D0_CS 447
480MX53_PAD_EIM_D19__EMI_WEIM_D_19 448
481MX53_PAD_EIM_D19__GPIO3_19 449
482MX53_PAD_EIM_D19__IPU_DI0_PIN8 450
483MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS 451
484MX53_PAD_EIM_D19__ECSPI1_SS1 452
485MX53_PAD_EIM_D19__EPIT1_EPITO 453
486MX53_PAD_EIM_D19__UART1_CTS 454
487MX53_PAD_EIM_D19__USBOH3_USBH2_OC 455
488MX53_PAD_EIM_D20__EMI_WEIM_D_20 456
489MX53_PAD_EIM_D20__GPIO3_20 457
490MX53_PAD_EIM_D20__IPU_DI0_PIN16 458
491MX53_PAD_EIM_D20__IPU_SER_DISP0_CS 459
492MX53_PAD_EIM_D20__CSPI_SS0 460
493MX53_PAD_EIM_D20__EPIT2_EPITO 461
494MX53_PAD_EIM_D20__UART1_RTS 462
495MX53_PAD_EIM_D20__USBOH3_USBH2_PWR 463
496MX53_PAD_EIM_D21__EMI_WEIM_D_21 464
497MX53_PAD_EIM_D21__GPIO3_21 465
498MX53_PAD_EIM_D21__IPU_DI0_PIN17 466
499MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK 467
500MX53_PAD_EIM_D21__CSPI_SCLK 468
501MX53_PAD_EIM_D21__I2C1_SCL 469
502MX53_PAD_EIM_D21__USBOH3_USBOTG_OC 470
503MX53_PAD_EIM_D22__EMI_WEIM_D_22 471
504MX53_PAD_EIM_D22__GPIO3_22 472
505MX53_PAD_EIM_D22__IPU_DI0_PIN1 473
506MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN 474
507MX53_PAD_EIM_D22__CSPI_MISO 475
508MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR 476
509MX53_PAD_EIM_D23__EMI_WEIM_D_23 477
510MX53_PAD_EIM_D23__GPIO3_23 478
511MX53_PAD_EIM_D23__UART3_CTS 479
512MX53_PAD_EIM_D23__UART1_DCD 480
513MX53_PAD_EIM_D23__IPU_DI0_D0_CS 481
514MX53_PAD_EIM_D23__IPU_DI1_PIN2 482
515MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN 483
516MX53_PAD_EIM_D23__IPU_DI1_PIN14 484
517MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 485
518MX53_PAD_EIM_EB3__GPIO2_31 486
519MX53_PAD_EIM_EB3__UART3_RTS 487
520MX53_PAD_EIM_EB3__UART1_RI 488
521MX53_PAD_EIM_EB3__IPU_DI1_PIN3 489
522MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC 490
523MX53_PAD_EIM_EB3__IPU_DI1_PIN16 491
524MX53_PAD_EIM_D24__EMI_WEIM_D_24 492
525MX53_PAD_EIM_D24__GPIO3_24 493
526MX53_PAD_EIM_D24__UART3_TXD_MUX 494
527MX53_PAD_EIM_D24__ECSPI1_SS2 495
528MX53_PAD_EIM_D24__CSPI_SS2 496
529MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS 497
530MX53_PAD_EIM_D24__ECSPI2_SS2 498
531MX53_PAD_EIM_D24__UART1_DTR 499
532MX53_PAD_EIM_D25__EMI_WEIM_D_25 500
533MX53_PAD_EIM_D25__GPIO3_25 501
534MX53_PAD_EIM_D25__UART3_RXD_MUX 502
535MX53_PAD_EIM_D25__ECSPI1_SS3 503
536MX53_PAD_EIM_D25__CSPI_SS3 504
537MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC 505
538MX53_PAD_EIM_D25__ECSPI2_SS3 506
539MX53_PAD_EIM_D25__UART1_DSR 507
540MX53_PAD_EIM_D26__EMI_WEIM_D_26 508
541MX53_PAD_EIM_D26__GPIO3_26 509
542MX53_PAD_EIM_D26__UART2_TXD_MUX 510
543MX53_PAD_EIM_D26__FIRI_RXD 511
544MX53_PAD_EIM_D26__IPU_CSI0_D_1 512
545MX53_PAD_EIM_D26__IPU_DI1_PIN11 513
546MX53_PAD_EIM_D26__IPU_SISG_2 514
547MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 515
548MX53_PAD_EIM_D27__EMI_WEIM_D_27 516
549MX53_PAD_EIM_D27__GPIO3_27 517
550MX53_PAD_EIM_D27__UART2_RXD_MUX 518
551MX53_PAD_EIM_D27__FIRI_TXD 519
552MX53_PAD_EIM_D27__IPU_CSI0_D_0 520
553MX53_PAD_EIM_D27__IPU_DI1_PIN13 521
554MX53_PAD_EIM_D27__IPU_SISG_3 522
555MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 523
556MX53_PAD_EIM_D28__EMI_WEIM_D_28 524
557MX53_PAD_EIM_D28__GPIO3_28 525
558MX53_PAD_EIM_D28__UART2_CTS 526
559MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO 527
560MX53_PAD_EIM_D28__CSPI_MOSI 528
561MX53_PAD_EIM_D28__I2C1_SDA 529
562MX53_PAD_EIM_D28__IPU_EXT_TRIG 530
563MX53_PAD_EIM_D28__IPU_DI0_PIN13 531
564MX53_PAD_EIM_D29__EMI_WEIM_D_29 532
565MX53_PAD_EIM_D29__GPIO3_29 533
566MX53_PAD_EIM_D29__UART2_RTS 534
567MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS 535
568MX53_PAD_EIM_D29__CSPI_SS0 536
569MX53_PAD_EIM_D29__IPU_DI1_PIN15 537
570MX53_PAD_EIM_D29__IPU_CSI1_VSYNC 538
571MX53_PAD_EIM_D29__IPU_DI0_PIN14 539
572MX53_PAD_EIM_D30__EMI_WEIM_D_30 540
573MX53_PAD_EIM_D30__GPIO3_30 541
574MX53_PAD_EIM_D30__UART3_CTS 542
575MX53_PAD_EIM_D30__IPU_CSI0_D_3 543
576MX53_PAD_EIM_D30__IPU_DI0_PIN11 544
577MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 545
578MX53_PAD_EIM_D30__USBOH3_USBH1_OC 546
579MX53_PAD_EIM_D30__USBOH3_USBH2_OC 547
580MX53_PAD_EIM_D31__EMI_WEIM_D_31 548
581MX53_PAD_EIM_D31__GPIO3_31 549
582MX53_PAD_EIM_D31__UART3_RTS 550
583MX53_PAD_EIM_D31__IPU_CSI0_D_2 551
584MX53_PAD_EIM_D31__IPU_DI0_PIN12 552
585MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 553
586MX53_PAD_EIM_D31__USBOH3_USBH1_PWR 554
587MX53_PAD_EIM_D31__USBOH3_USBH2_PWR 555
588MX53_PAD_EIM_A24__EMI_WEIM_A_24 556
589MX53_PAD_EIM_A24__GPIO5_4 557
590MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 558
591MX53_PAD_EIM_A24__IPU_CSI1_D_19 559
592MX53_PAD_EIM_A24__IPU_SISG_2 560
593MX53_PAD_EIM_A24__USBPHY2_BVALID 561
594MX53_PAD_EIM_A23__EMI_WEIM_A_23 562
595MX53_PAD_EIM_A23__GPIO6_6 563
596MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 564
597MX53_PAD_EIM_A23__IPU_CSI1_D_18 565
598MX53_PAD_EIM_A23__IPU_SISG_3 566
599MX53_PAD_EIM_A23__USBPHY2_ENDSESSION 567
600MX53_PAD_EIM_A22__EMI_WEIM_A_22 568
601MX53_PAD_EIM_A22__GPIO2_16 569
602MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 570
603MX53_PAD_EIM_A22__IPU_CSI1_D_17 571
604MX53_PAD_EIM_A22__SRC_BT_CFG1_7 572
605MX53_PAD_EIM_A21__EMI_WEIM_A_21 573
606MX53_PAD_EIM_A21__GPIO2_17 574
607MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 575
608MX53_PAD_EIM_A21__IPU_CSI1_D_16 576
609MX53_PAD_EIM_A21__SRC_BT_CFG1_6 577
610MX53_PAD_EIM_A20__EMI_WEIM_A_20 578
611MX53_PAD_EIM_A20__GPIO2_18 579
612MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 580
613MX53_PAD_EIM_A20__IPU_CSI1_D_15 581
614MX53_PAD_EIM_A20__SRC_BT_CFG1_5 582
615MX53_PAD_EIM_A19__EMI_WEIM_A_19 583
616MX53_PAD_EIM_A19__GPIO2_19 584
617MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 585
618MX53_PAD_EIM_A19__IPU_CSI1_D_14 586
619MX53_PAD_EIM_A19__SRC_BT_CFG1_4 587
620MX53_PAD_EIM_A18__EMI_WEIM_A_18 588
621MX53_PAD_EIM_A18__GPIO2_20 589
622MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 590
623MX53_PAD_EIM_A18__IPU_CSI1_D_13 591
624MX53_PAD_EIM_A18__SRC_BT_CFG1_3 592
625MX53_PAD_EIM_A17__EMI_WEIM_A_17 593
626MX53_PAD_EIM_A17__GPIO2_21 594
627MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 595
628MX53_PAD_EIM_A17__IPU_CSI1_D_12 596
629MX53_PAD_EIM_A17__SRC_BT_CFG1_2 597
630MX53_PAD_EIM_A16__EMI_WEIM_A_16 598
631MX53_PAD_EIM_A16__GPIO2_22 599
632MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 600
633MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK 601
634MX53_PAD_EIM_A16__SRC_BT_CFG1_1 602
635MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 603
636MX53_PAD_EIM_CS0__GPIO2_23 604
637MX53_PAD_EIM_CS0__ECSPI2_SCLK 605
638MX53_PAD_EIM_CS0__IPU_DI1_PIN5 606
639MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 607
640MX53_PAD_EIM_CS1__GPIO2_24 608
641MX53_PAD_EIM_CS1__ECSPI2_MOSI 609
642MX53_PAD_EIM_CS1__IPU_DI1_PIN6 610
643MX53_PAD_EIM_OE__EMI_WEIM_OE 611
644MX53_PAD_EIM_OE__GPIO2_25 612
645MX53_PAD_EIM_OE__ECSPI2_MISO 613
646MX53_PAD_EIM_OE__IPU_DI1_PIN7 614
647MX53_PAD_EIM_OE__USBPHY2_IDDIG 615
648MX53_PAD_EIM_RW__EMI_WEIM_RW 616
649MX53_PAD_EIM_RW__GPIO2_26 617
650MX53_PAD_EIM_RW__ECSPI2_SS0 618
651MX53_PAD_EIM_RW__IPU_DI1_PIN8 619
652MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT 620
653MX53_PAD_EIM_LBA__EMI_WEIM_LBA 621
654MX53_PAD_EIM_LBA__GPIO2_27 622
655MX53_PAD_EIM_LBA__ECSPI2_SS1 623
656MX53_PAD_EIM_LBA__IPU_DI1_PIN17 624
657MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 625
658MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 626
659MX53_PAD_EIM_EB0__GPIO2_28 627
660MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 628
661MX53_PAD_EIM_EB0__IPU_CSI1_D_11 629
662MX53_PAD_EIM_EB0__GPC_PMIC_RDY 630
663MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 631
664MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 632
665MX53_PAD_EIM_EB1__GPIO2_29 633
666MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 634
667MX53_PAD_EIM_EB1__IPU_CSI1_D_10 635
668MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 636
669MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 637
670MX53_PAD_EIM_DA0__GPIO3_0 638
671MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 639
672MX53_PAD_EIM_DA0__IPU_CSI1_D_9 640
673MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 641
674MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 642
675MX53_PAD_EIM_DA1__GPIO3_1 643
676MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 644
677MX53_PAD_EIM_DA1__IPU_CSI1_D_8 645
678MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 646
679MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 647
680MX53_PAD_EIM_DA2__GPIO3_2 648
681MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 649
682MX53_PAD_EIM_DA2__IPU_CSI1_D_7 650
683MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 651
684MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 652
685MX53_PAD_EIM_DA3__GPIO3_3 653
686MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 654
687MX53_PAD_EIM_DA3__IPU_CSI1_D_6 655
688MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 656
689MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 657
690MX53_PAD_EIM_DA4__GPIO3_4 658
691MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 659
692MX53_PAD_EIM_DA4__IPU_CSI1_D_5 660
693MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 661
694MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 662
695MX53_PAD_EIM_DA5__GPIO3_5 663
696MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 664
697MX53_PAD_EIM_DA5__IPU_CSI1_D_4 665
698MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 666
699MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 667
700MX53_PAD_EIM_DA6__GPIO3_6 668
701MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 669
702MX53_PAD_EIM_DA6__IPU_CSI1_D_3 670
703MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 671
704MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 672
705MX53_PAD_EIM_DA7__GPIO3_7 673
706MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 674
707MX53_PAD_EIM_DA7__IPU_CSI1_D_2 675
708MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 676
709MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 677
710MX53_PAD_EIM_DA8__GPIO3_8 678
711MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 679
712MX53_PAD_EIM_DA8__IPU_CSI1_D_1 680
713MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 681
714MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 682
715MX53_PAD_EIM_DA9__GPIO3_9 683
716MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 684
717MX53_PAD_EIM_DA9__IPU_CSI1_D_0 685
718MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 686
719MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 687
720MX53_PAD_EIM_DA10__GPIO3_10 688
721MX53_PAD_EIM_DA10__IPU_DI1_PIN15 689
722MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN 690
723MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 691
724MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 692
725MX53_PAD_EIM_DA11__GPIO3_11 693
726MX53_PAD_EIM_DA11__IPU_DI1_PIN2 694
727MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC 695
728MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 696
729MX53_PAD_EIM_DA12__GPIO3_12 697
730MX53_PAD_EIM_DA12__IPU_DI1_PIN3 698
731MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC 699
732MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 700
733MX53_PAD_EIM_DA13__GPIO3_13 701
734MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 702
735MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK 703
736MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 704
737MX53_PAD_EIM_DA14__GPIO3_14 705
738MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 706
739MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK 707
740MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 708
741MX53_PAD_EIM_DA15__GPIO3_15 709
742MX53_PAD_EIM_DA15__IPU_DI1_PIN1 710
743MX53_PAD_EIM_DA15__IPU_DI1_PIN4 711
744MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 712
745MX53_PAD_NANDF_WE_B__GPIO6_12 713
746MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 714
747MX53_PAD_NANDF_RE_B__GPIO6_13 715
748MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT 716
749MX53_PAD_EIM_WAIT__GPIO5_0 717
750MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B 718
751MX53_PAD_LVDS1_TX3_P__GPIO6_22 719
752MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 720
753MX53_PAD_LVDS1_TX2_P__GPIO6_24 721
754MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 722
755MX53_PAD_LVDS1_CLK_P__GPIO6_26 723
756MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 724
757MX53_PAD_LVDS1_TX1_P__GPIO6_28 725
758MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 726
759MX53_PAD_LVDS1_TX0_P__GPIO6_30 727
760MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 728
761MX53_PAD_LVDS0_TX3_P__GPIO7_22 729
762MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 730
763MX53_PAD_LVDS0_CLK_P__GPIO7_24 731
764MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 732
765MX53_PAD_LVDS0_TX2_P__GPIO7_26 733
766MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 734
767MX53_PAD_LVDS0_TX1_P__GPIO7_28 735
768MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 736
769MX53_PAD_LVDS0_TX0_P__GPIO7_30 737
770MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 738
771MX53_PAD_GPIO_10__GPIO4_0 739
772MX53_PAD_GPIO_10__OSC32k_32K_OUT 740
773MX53_PAD_GPIO_11__GPIO4_1 741
774MX53_PAD_GPIO_12__GPIO4_2 742
775MX53_PAD_GPIO_13__GPIO4_3 743
776MX53_PAD_GPIO_14__GPIO4_4 744
777MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 745
778MX53_PAD_NANDF_CLE__GPIO6_7 746
779MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 747
780MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 748
781MX53_PAD_NANDF_ALE__GPIO6_8 749
782MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 750
783MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 751
784MX53_PAD_NANDF_WP_B__GPIO6_9 752
785MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 753
786MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 754
787MX53_PAD_NANDF_RB0__GPIO6_10 755
788MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 756
789MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 757
790MX53_PAD_NANDF_CS0__GPIO6_11 758
791MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 759
792MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 760
793MX53_PAD_NANDF_CS1__GPIO6_14 761
794MX53_PAD_NANDF_CS1__MLB_MLBCLK 762
795MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 763
796MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 764
797MX53_PAD_NANDF_CS2__GPIO6_15 765
798MX53_PAD_NANDF_CS2__IPU_SISG_0 766
799MX53_PAD_NANDF_CS2__ESAI1_TX0 767
800MX53_PAD_NANDF_CS2__EMI_WEIM_CRE 768
801MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK 769
802MX53_PAD_NANDF_CS2__MLB_MLBSIG 770
803MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 771
804MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 772
805MX53_PAD_NANDF_CS3__GPIO6_16 773
806MX53_PAD_NANDF_CS3__IPU_SISG_1 774
807MX53_PAD_NANDF_CS3__ESAI1_TX1 775
808MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 776
809MX53_PAD_NANDF_CS3__MLB_MLBDAT 777
810MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 778
811MX53_PAD_FEC_MDIO__FEC_MDIO 779
812MX53_PAD_FEC_MDIO__GPIO1_22 780
813MX53_PAD_FEC_MDIO__ESAI1_SCKR 781
814MX53_PAD_FEC_MDIO__FEC_COL 782
815MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 783
816MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 784
817MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 785
818MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 786
819MX53_PAD_FEC_REF_CLK__GPIO1_23 787
820MX53_PAD_FEC_REF_CLK__ESAI1_FSR 788
821MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 789
822MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 790
823MX53_PAD_FEC_RX_ER__FEC_RX_ER 791
824MX53_PAD_FEC_RX_ER__GPIO1_24 792
825MX53_PAD_FEC_RX_ER__ESAI1_HCKR 793
826MX53_PAD_FEC_RX_ER__FEC_RX_CLK 794
827MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 795
828MX53_PAD_FEC_CRS_DV__FEC_RX_DV 796
829MX53_PAD_FEC_CRS_DV__GPIO1_25 797
830MX53_PAD_FEC_CRS_DV__ESAI1_SCKT 798
831MX53_PAD_FEC_RXD1__FEC_RDATA_1 799
832MX53_PAD_FEC_RXD1__GPIO1_26 800
833MX53_PAD_FEC_RXD1__ESAI1_FST 801
834MX53_PAD_FEC_RXD1__MLB_MLBSIG 802
835MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 803
836MX53_PAD_FEC_RXD0__FEC_RDATA_0 804
837MX53_PAD_FEC_RXD0__GPIO1_27 805
838MX53_PAD_FEC_RXD0__ESAI1_HCKT 806
839MX53_PAD_FEC_RXD0__OSC32k_32K_OUT 807
840MX53_PAD_FEC_TX_EN__FEC_TX_EN 808
841MX53_PAD_FEC_TX_EN__GPIO1_28 809
842MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 810
843MX53_PAD_FEC_TXD1__FEC_TDATA_1 811
844MX53_PAD_FEC_TXD1__GPIO1_29 812
845MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 813
846MX53_PAD_FEC_TXD1__MLB_MLBCLK 814
847MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK 815
848MX53_PAD_FEC_TXD0__FEC_TDATA_0 816
849MX53_PAD_FEC_TXD0__GPIO1_30 817
850MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 818
851MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 819
852MX53_PAD_FEC_MDC__FEC_MDC 820
853MX53_PAD_FEC_MDC__GPIO1_31 821
854MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 822
855MX53_PAD_FEC_MDC__MLB_MLBDAT 823
856MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG 824
857MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 825
858MX53_PAD_PATA_DIOW__PATA_DIOW 826
859MX53_PAD_PATA_DIOW__GPIO6_17 827
860MX53_PAD_PATA_DIOW__UART1_TXD_MUX 828
861MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 829
862MX53_PAD_PATA_DMACK__PATA_DMACK 830
863MX53_PAD_PATA_DMACK__GPIO6_18 831
864MX53_PAD_PATA_DMACK__UART1_RXD_MUX 832
865MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 833
866MX53_PAD_PATA_DMARQ__PATA_DMARQ 834
867MX53_PAD_PATA_DMARQ__GPIO7_0 835
868MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 836
869MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 837
870MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 838
871MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN 839
872MX53_PAD_PATA_BUFFER_EN__GPIO7_1 840
873MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 841
874MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 842
875MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 843
876MX53_PAD_PATA_INTRQ__PATA_INTRQ 844
877MX53_PAD_PATA_INTRQ__GPIO7_2 845
878MX53_PAD_PATA_INTRQ__UART2_CTS 846
879MX53_PAD_PATA_INTRQ__CAN1_TXCAN 847
880MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 848
881MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 849
882MX53_PAD_PATA_DIOR__PATA_DIOR 850
883MX53_PAD_PATA_DIOR__GPIO7_3 851
884MX53_PAD_PATA_DIOR__UART2_RTS 852
885MX53_PAD_PATA_DIOR__CAN1_RXCAN 853
886MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 854
887MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B 855
888MX53_PAD_PATA_RESET_B__GPIO7_4 856
889MX53_PAD_PATA_RESET_B__ESDHC3_CMD 857
890MX53_PAD_PATA_RESET_B__UART1_CTS 858
891MX53_PAD_PATA_RESET_B__CAN2_TXCAN 859
892MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 860
893MX53_PAD_PATA_IORDY__PATA_IORDY 861
894MX53_PAD_PATA_IORDY__GPIO7_5 862
895MX53_PAD_PATA_IORDY__ESDHC3_CLK 863
896MX53_PAD_PATA_IORDY__UART1_RTS 864
897MX53_PAD_PATA_IORDY__CAN2_RXCAN 865
898MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 866
899MX53_PAD_PATA_DA_0__PATA_DA_0 867
900MX53_PAD_PATA_DA_0__GPIO7_6 868
901MX53_PAD_PATA_DA_0__ESDHC3_RST 869
902MX53_PAD_PATA_DA_0__OWIRE_LINE 870
903MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 871
904MX53_PAD_PATA_DA_1__PATA_DA_1 872
905MX53_PAD_PATA_DA_1__GPIO7_7 873
906MX53_PAD_PATA_DA_1__ESDHC4_CMD 874
907MX53_PAD_PATA_DA_1__UART3_CTS 875
908MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 876
909MX53_PAD_PATA_DA_2__PATA_DA_2 877
910MX53_PAD_PATA_DA_2__GPIO7_8 878
911MX53_PAD_PATA_DA_2__ESDHC4_CLK 879
912MX53_PAD_PATA_DA_2__UART3_RTS 880
913MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 881
914MX53_PAD_PATA_CS_0__PATA_CS_0 882
915MX53_PAD_PATA_CS_0__GPIO7_9 883
916MX53_PAD_PATA_CS_0__UART3_TXD_MUX 884
917MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 885
918MX53_PAD_PATA_CS_1__PATA_CS_1 886
919MX53_PAD_PATA_CS_1__GPIO7_10 887
920MX53_PAD_PATA_CS_1__UART3_RXD_MUX 888
921MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 889
922MX53_PAD_PATA_DATA0__PATA_DATA_0 890
923MX53_PAD_PATA_DATA0__GPIO2_0 891
924MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 892
925MX53_PAD_PATA_DATA0__ESDHC3_DAT4 893
926MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 894
927MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 895
928MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 896
929MX53_PAD_PATA_DATA1__PATA_DATA_1 897
930MX53_PAD_PATA_DATA1__GPIO2_1 898
931MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 899
932MX53_PAD_PATA_DATA1__ESDHC3_DAT5 900
933MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 901
934MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 902
935MX53_PAD_PATA_DATA2__PATA_DATA_2 903
936MX53_PAD_PATA_DATA2__GPIO2_2 904
937MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 905
938MX53_PAD_PATA_DATA2__ESDHC3_DAT6 906
939MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 907
940MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 908
941MX53_PAD_PATA_DATA3__PATA_DATA_3 909
942MX53_PAD_PATA_DATA3__GPIO2_3 910
943MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 911
944MX53_PAD_PATA_DATA3__ESDHC3_DAT7 912
945MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 913
946MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 914
947MX53_PAD_PATA_DATA4__PATA_DATA_4 915
948MX53_PAD_PATA_DATA4__GPIO2_4 916
949MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 917
950MX53_PAD_PATA_DATA4__ESDHC4_DAT4 918
951MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 919
952MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 920
953MX53_PAD_PATA_DATA5__PATA_DATA_5 921
954MX53_PAD_PATA_DATA5__GPIO2_5 922
955MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 923
956MX53_PAD_PATA_DATA5__ESDHC4_DAT5 924
957MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 925
958MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 926
959MX53_PAD_PATA_DATA6__PATA_DATA_6 927
960MX53_PAD_PATA_DATA6__GPIO2_6 928
961MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 929
962MX53_PAD_PATA_DATA6__ESDHC4_DAT6 930
963MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 931
964MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 932
965MX53_PAD_PATA_DATA7__PATA_DATA_7 933
966MX53_PAD_PATA_DATA7__GPIO2_7 934
967MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 935
968MX53_PAD_PATA_DATA7__ESDHC4_DAT7 936
969MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 937
970MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 938
971MX53_PAD_PATA_DATA8__PATA_DATA_8 939
972MX53_PAD_PATA_DATA8__GPIO2_8 940
973MX53_PAD_PATA_DATA8__ESDHC1_DAT4 941
974MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 942
975MX53_PAD_PATA_DATA8__ESDHC3_DAT0 943
976MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 944
977MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 945
978MX53_PAD_PATA_DATA9__PATA_DATA_9 946
979MX53_PAD_PATA_DATA9__GPIO2_9 947
980MX53_PAD_PATA_DATA9__ESDHC1_DAT5 948
981MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 949
982MX53_PAD_PATA_DATA9__ESDHC3_DAT1 950
983MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 951
984MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 952
985MX53_PAD_PATA_DATA10__PATA_DATA_10 953
986MX53_PAD_PATA_DATA10__GPIO2_10 954
987MX53_PAD_PATA_DATA10__ESDHC1_DAT6 955
988MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 956
989MX53_PAD_PATA_DATA10__ESDHC3_DAT2 957
990MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 958
991MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 959
992MX53_PAD_PATA_DATA11__PATA_DATA_11 960
993MX53_PAD_PATA_DATA11__GPIO2_11 961
994MX53_PAD_PATA_DATA11__ESDHC1_DAT7 962
995MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 963
996MX53_PAD_PATA_DATA11__ESDHC3_DAT3 964
997MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 965
998MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 966
999MX53_PAD_PATA_DATA12__PATA_DATA_12 967
1000MX53_PAD_PATA_DATA12__GPIO2_12 968
1001MX53_PAD_PATA_DATA12__ESDHC2_DAT4 969
1002MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 970
1003MX53_PAD_PATA_DATA12__ESDHC4_DAT0 971
1004MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 972
1005MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 973
1006MX53_PAD_PATA_DATA13__PATA_DATA_13 974
1007MX53_PAD_PATA_DATA13__GPIO2_13 975
1008MX53_PAD_PATA_DATA13__ESDHC2_DAT5 976
1009MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 977
1010MX53_PAD_PATA_DATA13__ESDHC4_DAT1 978
1011MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 979
1012MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 980
1013MX53_PAD_PATA_DATA14__PATA_DATA_14 981
1014MX53_PAD_PATA_DATA14__GPIO2_14 982
1015MX53_PAD_PATA_DATA14__ESDHC2_DAT6 983
1016MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 984
1017MX53_PAD_PATA_DATA14__ESDHC4_DAT2 985
1018MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 986
1019MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 987
1020MX53_PAD_PATA_DATA15__PATA_DATA_15 988
1021MX53_PAD_PATA_DATA15__GPIO2_15 989
1022MX53_PAD_PATA_DATA15__ESDHC2_DAT7 990
1023MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 991
1024MX53_PAD_PATA_DATA15__ESDHC4_DAT3 992
1025MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 993
1026MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 994
1027MX53_PAD_SD1_DATA0__ESDHC1_DAT0 995
1028MX53_PAD_SD1_DATA0__GPIO1_16 996
1029MX53_PAD_SD1_DATA0__GPT_CAPIN1 997
1030MX53_PAD_SD1_DATA0__CSPI_MISO 998
1031MX53_PAD_SD1_DATA0__CCM_PLL3_BYP 999
1032MX53_PAD_SD1_DATA1__ESDHC1_DAT1 1000
1033MX53_PAD_SD1_DATA1__GPIO1_17 1001
1034MX53_PAD_SD1_DATA1__GPT_CAPIN2 1002
1035MX53_PAD_SD1_DATA1__CSPI_SS0 1003
1036MX53_PAD_SD1_DATA1__CCM_PLL4_BYP 1004
1037MX53_PAD_SD1_CMD__ESDHC1_CMD 1005
1038MX53_PAD_SD1_CMD__GPIO1_18 1006
1039MX53_PAD_SD1_CMD__GPT_CMPOUT1 1007
1040MX53_PAD_SD1_CMD__CSPI_MOSI 1008
1041MX53_PAD_SD1_CMD__CCM_PLL1_BYP 1009
1042MX53_PAD_SD1_DATA2__ESDHC1_DAT2 1010
1043MX53_PAD_SD1_DATA2__GPIO1_19 1011
1044MX53_PAD_SD1_DATA2__GPT_CMPOUT2 1012
1045MX53_PAD_SD1_DATA2__PWM2_PWMO 1013
1046MX53_PAD_SD1_DATA2__WDOG1_WDOG_B 1014
1047MX53_PAD_SD1_DATA2__CSPI_SS1 1015
1048MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB 1016
1049MX53_PAD_SD1_DATA2__CCM_PLL2_BYP 1017
1050MX53_PAD_SD1_CLK__ESDHC1_CLK 1018
1051MX53_PAD_SD1_CLK__GPIO1_20 1019
1052MX53_PAD_SD1_CLK__OSC32k_32K_OUT 1020
1053MX53_PAD_SD1_CLK__GPT_CLKIN 1021
1054MX53_PAD_SD1_CLK__CSPI_SCLK 1022
1055MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 1023
1056MX53_PAD_SD1_DATA3__ESDHC1_DAT3 1024
1057MX53_PAD_SD1_DATA3__GPIO1_21 1025
1058MX53_PAD_SD1_DATA3__GPT_CMPOUT3 1026
1059MX53_PAD_SD1_DATA3__PWM1_PWMO 1027
1060MX53_PAD_SD1_DATA3__WDOG2_WDOG_B 1028
1061MX53_PAD_SD1_DATA3__CSPI_SS2 1029
1062MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB 1030
1063MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 1031
1064MX53_PAD_SD2_CLK__ESDHC2_CLK 1032
1065MX53_PAD_SD2_CLK__GPIO1_10 1033
1066MX53_PAD_SD2_CLK__KPP_COL_5 1034
1067MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS 1035
1068MX53_PAD_SD2_CLK__CSPI_SCLK 1036
1069MX53_PAD_SD2_CLK__SCC_RANDOM_V 1037
1070MX53_PAD_SD2_CMD__ESDHC2_CMD 1038
1071MX53_PAD_SD2_CMD__GPIO1_11 1039
1072MX53_PAD_SD2_CMD__KPP_ROW_5 1040
1073MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC 1041
1074MX53_PAD_SD2_CMD__CSPI_MOSI 1042
1075MX53_PAD_SD2_CMD__SCC_RANDOM 1043
1076MX53_PAD_SD2_DATA3__ESDHC2_DAT3 1044
1077MX53_PAD_SD2_DATA3__GPIO1_12 1045
1078MX53_PAD_SD2_DATA3__KPP_COL_6 1046
1079MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 1047
1080MX53_PAD_SD2_DATA3__CSPI_SS2 1048
1081MX53_PAD_SD2_DATA3__SJC_DONE 1049
1082MX53_PAD_SD2_DATA2__ESDHC2_DAT2 1050
1083MX53_PAD_SD2_DATA2__GPIO1_13 1051
1084MX53_PAD_SD2_DATA2__KPP_ROW_6 1052
1085MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 1053
1086MX53_PAD_SD2_DATA2__CSPI_SS1 1054
1087MX53_PAD_SD2_DATA2__SJC_FAIL 1055
1088MX53_PAD_SD2_DATA1__ESDHC2_DAT1 1056
1089MX53_PAD_SD2_DATA1__GPIO1_14 1057
1090MX53_PAD_SD2_DATA1__KPP_COL_7 1058
1091MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 1059
1092MX53_PAD_SD2_DATA1__CSPI_SS0 1060
1093MX53_PAD_SD2_DATA1__RTIC_SEC_VIO 1061
1094MX53_PAD_SD2_DATA0__ESDHC2_DAT0 1062
1095MX53_PAD_SD2_DATA0__GPIO1_15 1063
1096MX53_PAD_SD2_DATA0__KPP_ROW_7 1064
1097MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 1065
1098MX53_PAD_SD2_DATA0__CSPI_MISO 1066
1099MX53_PAD_SD2_DATA0__RTIC_DONE_INT 1067
1100MX53_PAD_GPIO_0__CCM_CLKO 1068
1101MX53_PAD_GPIO_0__GPIO1_0 1069
1102MX53_PAD_GPIO_0__KPP_COL_5 1070
1103MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 1071
1104MX53_PAD_GPIO_0__EPIT1_EPITO 1072
1105MX53_PAD_GPIO_0__SRTC_ALARM_DEB 1073
1106MX53_PAD_GPIO_0__USBOH3_USBH1_PWR 1074
1107MX53_PAD_GPIO_0__CSU_TD 1075
1108MX53_PAD_GPIO_1__ESAI1_SCKR 1076
1109MX53_PAD_GPIO_1__GPIO1_1 1077
1110MX53_PAD_GPIO_1__KPP_ROW_5 1078
1111MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK 1079
1112MX53_PAD_GPIO_1__PWM2_PWMO 1080
1113MX53_PAD_GPIO_1__WDOG2_WDOG_B 1081
1114MX53_PAD_GPIO_1__ESDHC1_CD 1082
1115MX53_PAD_GPIO_1__SRC_TESTER_ACK 1083
1116MX53_PAD_GPIO_9__ESAI1_FSR 1084
1117MX53_PAD_GPIO_9__GPIO1_9 1085
1118MX53_PAD_GPIO_9__KPP_COL_6 1086
1119MX53_PAD_GPIO_9__CCM_REF_EN_B 1087
1120MX53_PAD_GPIO_9__PWM1_PWMO 1088
1121MX53_PAD_GPIO_9__WDOG1_WDOG_B 1089
1122MX53_PAD_GPIO_9__ESDHC1_WP 1090
1123MX53_PAD_GPIO_9__SCC_FAIL_STATE 1091
1124MX53_PAD_GPIO_3__ESAI1_HCKR 1092
1125MX53_PAD_GPIO_3__GPIO1_3 1093
1126MX53_PAD_GPIO_3__I2C3_SCL 1094
1127MX53_PAD_GPIO_3__DPLLIP1_TOG_EN 1095
1128MX53_PAD_GPIO_3__CCM_CLKO2 1096
1129MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 1097
1130MX53_PAD_GPIO_3__USBOH3_USBH1_OC 1098
1131MX53_PAD_GPIO_3__MLB_MLBCLK 1099
1132MX53_PAD_GPIO_6__ESAI1_SCKT 1100
1133MX53_PAD_GPIO_6__GPIO1_6 1101
1134MX53_PAD_GPIO_6__I2C3_SDA 1102
1135MX53_PAD_GPIO_6__CCM_CCM_OUT_0 1103
1136MX53_PAD_GPIO_6__CSU_CSU_INT_DEB 1104
1137MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 1105
1138MX53_PAD_GPIO_6__ESDHC2_LCTL 1106
1139MX53_PAD_GPIO_6__MLB_MLBSIG 1107
1140MX53_PAD_GPIO_2__ESAI1_FST 1108
1141MX53_PAD_GPIO_2__GPIO1_2 1109
1142MX53_PAD_GPIO_2__KPP_ROW_6 1110
1143MX53_PAD_GPIO_2__CCM_CCM_OUT_1 1111
1144MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 1112
1145MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 1113
1146MX53_PAD_GPIO_2__ESDHC2_WP 1114
1147MX53_PAD_GPIO_2__MLB_MLBDAT 1115
1148MX53_PAD_GPIO_4__ESAI1_HCKT 1116
1149MX53_PAD_GPIO_4__GPIO1_4 1117
1150MX53_PAD_GPIO_4__KPP_COL_7 1118
1151MX53_PAD_GPIO_4__CCM_CCM_OUT_2 1119
1152MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 1120
1153MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 1121
1154MX53_PAD_GPIO_4__ESDHC2_CD 1122
1155MX53_PAD_GPIO_4__SCC_SEC_STATE 1123
1156MX53_PAD_GPIO_5__ESAI1_TX2_RX3 1124
1157MX53_PAD_GPIO_5__GPIO1_5 1125
1158MX53_PAD_GPIO_5__KPP_ROW_7 1126
1159MX53_PAD_GPIO_5__CCM_CLKO 1127
1160MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 1128
1161MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 1129
1162MX53_PAD_GPIO_5__I2C3_SCL 1130
1163MX53_PAD_GPIO_5__CCM_PLL1_BYP 1131
1164MX53_PAD_GPIO_7__ESAI1_TX4_RX1 1132
1165MX53_PAD_GPIO_7__GPIO1_7 1133
1166MX53_PAD_GPIO_7__EPIT1_EPITO 1134
1167MX53_PAD_GPIO_7__CAN1_TXCAN 1135
1168MX53_PAD_GPIO_7__UART2_TXD_MUX 1136
1169MX53_PAD_GPIO_7__FIRI_RXD 1137
1170MX53_PAD_GPIO_7__SPDIF_PLOCK 1138
1171MX53_PAD_GPIO_7__CCM_PLL2_BYP 1139
1172MX53_PAD_GPIO_8__ESAI1_TX5_RX0 1140
1173MX53_PAD_GPIO_8__GPIO1_8 1141
1174MX53_PAD_GPIO_8__EPIT2_EPITO 1142
1175MX53_PAD_GPIO_8__CAN1_RXCAN 1143
1176MX53_PAD_GPIO_8__UART2_RXD_MUX 1144
1177MX53_PAD_GPIO_8__FIRI_TXD 1145
1178MX53_PAD_GPIO_8__SPDIF_SRCLK 1146
1179MX53_PAD_GPIO_8__CCM_PLL3_BYP 1147
1180MX53_PAD_GPIO_16__ESAI1_TX3_RX2 1148
1181MX53_PAD_GPIO_16__GPIO7_11 1149
1182MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT 1150
1183MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 1151
1184MX53_PAD_GPIO_16__SPDIF_IN1 1152
1185MX53_PAD_GPIO_16__I2C3_SDA 1153
1186MX53_PAD_GPIO_16__SJC_DE_B 1154
1187MX53_PAD_GPIO_17__ESAI1_TX0 1155
1188MX53_PAD_GPIO_17__GPIO7_12 1156
1189MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 1157
1190MX53_PAD_GPIO_17__GPC_PMIC_RDY 1158
1191MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG 1159
1192MX53_PAD_GPIO_17__SPDIF_OUT1 1160
1193MX53_PAD_GPIO_17__IPU_SNOOP2 1161
1194MX53_PAD_GPIO_17__SJC_JTAG_ACT 1162
1195MX53_PAD_GPIO_18__ESAI1_TX1 1163
1196MX53_PAD_GPIO_18__GPIO7_13 1164
1197MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 1165
1198MX53_PAD_GPIO_18__OWIRE_LINE 1166
1199MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG 1167
1200MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK 1168
1201MX53_PAD_GPIO_18__ESDHC1_LCTL 1169
1202MX53_PAD_GPIO_18__SRC_SYSTEM_RST 1170
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt
new file mode 100644
index 00000000000..82b43f91585
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt
@@ -0,0 +1,1628 @@
1* Freescale IMX6Q IOMUX Controller
2
3Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
4and usage.
5
6Required properties:
7- compatible: "fsl,imx6q-iomuxc"
8- fsl,pins: two integers array, represents a group of pins mux and config
9 setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
10 pin working on a specific function, CONFIG is the pad setting value like
11 pull-up for this pin. Please refer to imx6q datasheet for the valid pad
12 config settings.
13
14CONFIG bits definition:
15PAD_CTL_HYS (1 << 16)
16PAD_CTL_PUS_100K_DOWN (0 << 14)
17PAD_CTL_PUS_47K_UP (1 << 14)
18PAD_CTL_PUS_100K_UP (2 << 14)
19PAD_CTL_PUS_22K_UP (3 << 14)
20PAD_CTL_PUE (1 << 13)
21PAD_CTL_PKE (1 << 12)
22PAD_CTL_ODE (1 << 11)
23PAD_CTL_SPEED_LOW (1 << 6)
24PAD_CTL_SPEED_MED (2 << 6)
25PAD_CTL_SPEED_HIGH (3 << 6)
26PAD_CTL_DSE_DISABLE (0 << 3)
27PAD_CTL_DSE_240ohm (1 << 3)
28PAD_CTL_DSE_120ohm (2 << 3)
29PAD_CTL_DSE_80ohm (3 << 3)
30PAD_CTL_DSE_60ohm (4 << 3)
31PAD_CTL_DSE_48ohm (5 << 3)
32PAD_CTL_DSE_40ohm (6 << 3)
33PAD_CTL_DSE_34ohm (7 << 3)
34PAD_CTL_SRE_FAST (1 << 0)
35PAD_CTL_SRE_SLOW (0 << 0)
36
37See below for available PIN_FUNC_ID for imx6q:
38MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 0
39MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 1
40MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 2
41MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS 3
42MX6Q_PAD_SD2_DAT1__KPP_COL_7 4
43MX6Q_PAD_SD2_DAT1__GPIO_1_14 5
44MX6Q_PAD_SD2_DAT1__CCM_WAIT 6
45MX6Q_PAD_SD2_DAT1__ANATOP_TESTO_0 7
46MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 8
47MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 9
48MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 10
49MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD 11
50MX6Q_PAD_SD2_DAT2__KPP_ROW_6 12
51MX6Q_PAD_SD2_DAT2__GPIO_1_13 13
52MX6Q_PAD_SD2_DAT2__CCM_STOP 14
53MX6Q_PAD_SD2_DAT2__ANATOP_TESTO_1 15
54MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 16
55MX6Q_PAD_SD2_DAT0__ECSPI5_MISO 17
56MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD 18
57MX6Q_PAD_SD2_DAT0__KPP_ROW_7 19
58MX6Q_PAD_SD2_DAT0__GPIO_1_15 20
59MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT 21
60MX6Q_PAD_SD2_DAT0__TESTO_2 22
61MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA 23
62MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC 24
63MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK 25
64MX6Q_PAD_RGMII_TXC__GPIO_6_19 26
65MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_IN_0 27
66MX6Q_PAD_RGMII_TXC__ANATOP_24M_OUT 28
67MX6Q_PAD_RGMII_TD0__MIPI_HSI_CRL_TX_RDY 29
68MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 30
69MX6Q_PAD_RGMII_TD0__GPIO_6_20 31
70MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_IN_1 32
71MX6Q_PAD_RGMII_TD1__MIPI_HSI_CRL_RX_FLG 33
72MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 34
73MX6Q_PAD_RGMII_TD1__GPIO_6_21 35
74MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_IN_2 36
75MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP 37
76MX6Q_PAD_RGMII_TD2__MIPI_HSI_CRL_RX_DTA 38
77MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 39
78MX6Q_PAD_RGMII_TD2__GPIO_6_22 40
79MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_IN_3 41
80MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP 42
81MX6Q_PAD_RGMII_TD3__MIPI_HSI_CRL_RX_WAK 43
82MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 44
83MX6Q_PAD_RGMII_TD3__GPIO_6_23 45
84MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_IN_4 46
85MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA 47
86MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 48
87MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 49
88MX6Q_PAD_RGMII_RX_CTL__MIPI_DPHY_IN_5 50
89MX6Q_PAD_RGMII_RD0__MIPI_HSI_CRL_RX_RDY 51
90MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 52
91MX6Q_PAD_RGMII_RD0__GPIO_6_25 53
92MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_IN_6 54
93MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE 55
94MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 56
95MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 57
96MX6Q_PAD_RGMII_TX_CTL__CORE_DPHY_IN_7 58
97MX6Q_PAD_RGMII_TX_CTL__ANATOP_REF_OUT 59
98MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FL 60
99MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 61
100MX6Q_PAD_RGMII_RD1__GPIO_6_27 62
101MX6Q_PAD_RGMII_RD1__CORE_DPHY_TEST_IN_8 63
102MX6Q_PAD_RGMII_RD1__SJC_FAIL 64
103MX6Q_PAD_RGMII_RD2__MIPI_HSI_CRL_TX_DTA 65
104MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 66
105MX6Q_PAD_RGMII_RD2__GPIO_6_28 67
106MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_IN_9 68
107MX6Q_PAD_RGMII_RD3__MIPI_HSI_CRL_TX_WAK 69
108MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 70
109MX6Q_PAD_RGMII_RD3__GPIO_6_29 71
110MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_IN10 72
111MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE 73
112MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC 74
113MX6Q_PAD_RGMII_RXC__GPIO_6_30 75
114MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_IN11 76
115MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 77
116MX6Q_PAD_EIM_A25__ECSPI4_SS1 78
117MX6Q_PAD_EIM_A25__ECSPI2_RDY 79
118MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 80
119MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS 81
120MX6Q_PAD_EIM_A25__GPIO_5_2 82
121MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE 83
122MX6Q_PAD_EIM_A25__PL301_PER1_HBURST_0 84
123MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 85
124MX6Q_PAD_EIM_EB2__ECSPI1_SS0 86
125MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK 87
126MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 88
127MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL 89
128MX6Q_PAD_EIM_EB2__GPIO_2_30 90
129MX6Q_PAD_EIM_EB2__I2C2_SCL 91
130MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 92
131MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 93
132MX6Q_PAD_EIM_D16__ECSPI1_SCLK 94
133MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 95
134MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 96
135MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA 97
136MX6Q_PAD_EIM_D16__GPIO_3_16 98
137MX6Q_PAD_EIM_D16__I2C2_SDA 99
138MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 100
139MX6Q_PAD_EIM_D17__ECSPI1_MISO 101
140MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 102
141MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK 103
142MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT 104
143MX6Q_PAD_EIM_D17__GPIO_3_17 105
144MX6Q_PAD_EIM_D17__I2C3_SCL 106
145MX6Q_PAD_EIM_D17__PL301_PER1_HBURST_1 107
146MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 108
147MX6Q_PAD_EIM_D18__ECSPI1_MOSI 109
148MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 110
149MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 111
150MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS 112
151MX6Q_PAD_EIM_D18__GPIO_3_18 113
152MX6Q_PAD_EIM_D18__I2C3_SDA 114
153MX6Q_PAD_EIM_D18__PL301_PER1_HBURST_2 115
154MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 116
155MX6Q_PAD_EIM_D19__ECSPI1_SS1 117
156MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 118
157MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 119
158MX6Q_PAD_EIM_D19__UART1_CTS 120
159MX6Q_PAD_EIM_D19__GPIO_3_19 121
160MX6Q_PAD_EIM_D19__EPIT1_EPITO 122
161MX6Q_PAD_EIM_D19__PL301_PER1_HRESP 123
162MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 124
163MX6Q_PAD_EIM_D20__ECSPI4_SS0 125
164MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 126
165MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 127
166MX6Q_PAD_EIM_D20__UART1_RTS 128
167MX6Q_PAD_EIM_D20__GPIO_3_20 129
168MX6Q_PAD_EIM_D20__EPIT2_EPITO 130
169MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 131
170MX6Q_PAD_EIM_D21__ECSPI4_SCLK 132
171MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 133
172MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 134
173MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC 135
174MX6Q_PAD_EIM_D21__GPIO_3_21 136
175MX6Q_PAD_EIM_D21__I2C1_SCL 137
176MX6Q_PAD_EIM_D21__SPDIF_IN1 138
177MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 139
178MX6Q_PAD_EIM_D22__ECSPI4_MISO 140
179MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 141
180MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 142
181MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR 143
182MX6Q_PAD_EIM_D22__GPIO_3_22 144
183MX6Q_PAD_EIM_D22__SPDIF_OUT1 145
184MX6Q_PAD_EIM_D22__PL301_PER1_HWRITE 146
185MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 147
186MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS 148
187MX6Q_PAD_EIM_D23__UART3_CTS 149
188MX6Q_PAD_EIM_D23__UART1_DCD 150
189MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN 151
190MX6Q_PAD_EIM_D23__GPIO_3_23 152
191MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 153
192MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 154
193MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 155
194MX6Q_PAD_EIM_EB3__ECSPI4_RDY 156
195MX6Q_PAD_EIM_EB3__UART3_RTS 157
196MX6Q_PAD_EIM_EB3__UART1_RI 158
197MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC 159
198MX6Q_PAD_EIM_EB3__GPIO_2_31 160
199MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 161
200MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 162
201MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 163
202MX6Q_PAD_EIM_D24__ECSPI4_SS2 164
203MX6Q_PAD_EIM_D24__UART3_TXD 165
204MX6Q_PAD_EIM_D24__ECSPI1_SS2 166
205MX6Q_PAD_EIM_D24__ECSPI2_SS2 167
206MX6Q_PAD_EIM_D24__GPIO_3_24 168
207MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS 169
208MX6Q_PAD_EIM_D24__UART1_DTR 170
209MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 171
210MX6Q_PAD_EIM_D25__ECSPI4_SS3 172
211MX6Q_PAD_EIM_D25__UART3_RXD 173
212MX6Q_PAD_EIM_D25__ECSPI1_SS3 174
213MX6Q_PAD_EIM_D25__ECSPI2_SS3 175
214MX6Q_PAD_EIM_D25__GPIO_3_25 176
215MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC 177
216MX6Q_PAD_EIM_D25__UART1_DSR 178
217MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 179
218MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 180
219MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 181
220MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 182
221MX6Q_PAD_EIM_D26__UART2_TXD 183
222MX6Q_PAD_EIM_D26__GPIO_3_26 184
223MX6Q_PAD_EIM_D26__IPU1_SISG_2 185
224MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 186
225MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 187
226MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 188
227MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 189
228MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 190
229MX6Q_PAD_EIM_D27__UART2_RXD 191
230MX6Q_PAD_EIM_D27__GPIO_3_27 192
231MX6Q_PAD_EIM_D27__IPU1_SISG_3 193
232MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 194
233MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 195
234MX6Q_PAD_EIM_D28__I2C1_SDA 196
235MX6Q_PAD_EIM_D28__ECSPI4_MOSI 197
236MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 198
237MX6Q_PAD_EIM_D28__UART2_CTS 199
238MX6Q_PAD_EIM_D28__GPIO_3_28 200
239MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG 201
240MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 202
241MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 203
242MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 204
243MX6Q_PAD_EIM_D29__ECSPI4_SS0 205
244MX6Q_PAD_EIM_D29__UART2_RTS 206
245MX6Q_PAD_EIM_D29__GPIO_3_29 207
246MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC 208
247MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 209
248MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 210
249MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 211
250MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 212
251MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 213
252MX6Q_PAD_EIM_D30__UART3_CTS 214
253MX6Q_PAD_EIM_D30__GPIO_3_30 215
254MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC 216
255MX6Q_PAD_EIM_D30__PL301_PER1_HPROT_0 217
256MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 218
257MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 219
258MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 220
259MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 221
260MX6Q_PAD_EIM_D31__UART3_RTS 222
261MX6Q_PAD_EIM_D31__GPIO_3_31 223
262MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR 224
263MX6Q_PAD_EIM_D31__PL301_PER1_HPROT_1 225
264MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 226
265MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 227
266MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 228
267MX6Q_PAD_EIM_A24__IPU2_SISG_2 229
268MX6Q_PAD_EIM_A24__IPU1_SISG_2 230
269MX6Q_PAD_EIM_A24__GPIO_5_4 231
270MX6Q_PAD_EIM_A24__PL301_PER1_HPROT_2 232
271MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 233
272MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 234
273MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 235
274MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 236
275MX6Q_PAD_EIM_A23__IPU2_SISG_3 237
276MX6Q_PAD_EIM_A23__IPU1_SISG_3 238
277MX6Q_PAD_EIM_A23__GPIO_6_6 239
278MX6Q_PAD_EIM_A23__PL301_PER1_HPROT_3 240
279MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 241
280MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 242
281MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 243
282MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 244
283MX6Q_PAD_EIM_A22__GPIO_2_16 245
284MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 246
285MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 247
286MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 248
287MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 249
288MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 250
289MX6Q_PAD_EIM_A21__RESERVED_RESERVED 251
290MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_OUT_18 252
291MX6Q_PAD_EIM_A21__GPIO_2_17 253
292MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 254
293MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 255
294MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 256
295MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 257
296MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 258
297MX6Q_PAD_EIM_A20__RESERVED_RESERVED 259
298MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_OUT_19 260
299MX6Q_PAD_EIM_A20__GPIO_2_18 261
300MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 262
301MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 263
302MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 264
303MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 265
304MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 266
305MX6Q_PAD_EIM_A19__RESERVED_RESERVED 267
306MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_OUT_20 268
307MX6Q_PAD_EIM_A19__GPIO_2_19 269
308MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 270
309MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 271
310MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 272
311MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 273
312MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 274
313MX6Q_PAD_EIM_A18__RESERVED_RESERVED 275
314MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_OUT_21 276
315MX6Q_PAD_EIM_A18__GPIO_2_20 277
316MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 278
317MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 279
318MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 280
319MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 281
320MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 282
321MX6Q_PAD_EIM_A17__RESERVED_RESERVED 283
322MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_OUT_22 284
323MX6Q_PAD_EIM_A17__GPIO_2_21 285
324MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 286
325MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 287
326MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 288
327MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK 289
328MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK 290
329MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_OUT_23 291
330MX6Q_PAD_EIM_A16__GPIO_2_22 292
331MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 293
332MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 294
333MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 295
334MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 296
335MX6Q_PAD_EIM_CS0__ECSPI2_SCLK 297
336MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_OUT_24 298
337MX6Q_PAD_EIM_CS0__GPIO_2_23 299
338MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 300
339MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 301
340MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 302
341MX6Q_PAD_EIM_CS1__ECSPI2_MOSI 303
342MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_OUT_25 304
343MX6Q_PAD_EIM_CS1__GPIO_2_24 305
344MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 306
345MX6Q_PAD_EIM_OE__WEIM_WEIM_OE 307
346MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 308
347MX6Q_PAD_EIM_OE__ECSPI2_MISO 309
348MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_OUT_26 310
349MX6Q_PAD_EIM_OE__GPIO_2_25 311
350MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 312
351MX6Q_PAD_EIM_RW__WEIM_WEIM_RW 313
352MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 314
353MX6Q_PAD_EIM_RW__ECSPI2_SS0 315
354MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_OUT_27 316
355MX6Q_PAD_EIM_RW__GPIO_2_26 317
356MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 318
357MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 319
358MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA 320
359MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 321
360MX6Q_PAD_EIM_LBA__ECSPI2_SS1 322
361MX6Q_PAD_EIM_LBA__GPIO_2_27 323
362MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 324
363MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 325
364MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 326
365MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 327
366MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 328
367MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_OUT_0 329
368MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY 330
369MX6Q_PAD_EIM_EB0__GPIO_2_28 331
370MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 332
371MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 333
372MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 334
373MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 335
374MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 336
375MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY__OUT_1 337
376MX6Q_PAD_EIM_EB1__GPIO_2_29 338
377MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 339
378MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 340
379MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 341
380MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 342
381MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 343
382MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY__OUT_2 344
383MX6Q_PAD_EIM_DA0__GPIO_3_0 345
384MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 346
385MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 347
386MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 348
387MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 349
388MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 350
389MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_OUT_3 351
390MX6Q_PAD_EIM_DA1__USBPHY1_TX_LS_MODE 352
391MX6Q_PAD_EIM_DA1__GPIO_3_1 353
392MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 354
393MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 355
394MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 356
395MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 357
396MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 358
397MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_OUT_4 359
398MX6Q_PAD_EIM_DA2__USBPHY1_TX_HS_MODE 360
399MX6Q_PAD_EIM_DA2__GPIO_3_2 361
400MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 362
401MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 363
402MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 364
403MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 365
404MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 366
405MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_OUT_5 367
406MX6Q_PAD_EIM_DA3__USBPHY1_TX_HIZ 368
407MX6Q_PAD_EIM_DA3__GPIO_3_3 369
408MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 370
409MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 371
410MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 372
411MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 373
412MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 374
413MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_OUT_6 375
414MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TX_EN 376
415MX6Q_PAD_EIM_DA4__GPIO_3_4 377
416MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 378
417MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 379
418MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 380
419MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 381
420MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 382
421MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_OUT_7 383
422MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TX_DP 384
423MX6Q_PAD_EIM_DA5__GPIO_3_5 385
424MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 386
425MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 387
426MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 388
427MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 389
428MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 390
429MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_OUT_8 391
430MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TX_DN 392
431MX6Q_PAD_EIM_DA6__GPIO_3_6 393
432MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 394
433MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 395
434MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 396
435MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 397
436MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 398
437MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_OUT_9 399
438MX6Q_PAD_EIM_DA7__GPIO_3_7 400
439MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 401
440MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 402
441MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 403
442MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 404
443MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 405
444MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_OUT_10 406
445MX6Q_PAD_EIM_DA8__GPIO_3_8 407
446MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 408
447MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 409
448MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 410
449MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 411
450MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 412
451MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_OUT_11 413
452MX6Q_PAD_EIM_DA9__GPIO_3_9 414
453MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 415
454MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 416
455MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 417
456MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 418
457MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 419
458MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_OUT12 420
459MX6Q_PAD_EIM_DA10__GPIO_3_10 421
460MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 422
461MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 423
462MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 424
463MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 425
464MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC 426
465MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_OUT13 427
466MX6Q_PAD_EIM_DA11__SDMA_DBG_EVT_CHN_6 428
467MX6Q_PAD_EIM_DA11__GPIO_3_11 429
468MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 430
469MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 431
470MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 432
471MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 433
472MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC 434
473MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_OUT14 435
474MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_3 436
475MX6Q_PAD_EIM_DA12__GPIO_3_12 437
476MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 438
477MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 439
478MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 440
479MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS 441
480MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK 442
481MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_OUT15 443
482MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_4 444
483MX6Q_PAD_EIM_DA13__GPIO_3_13 445
484MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 446
485MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 447
486MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 448
487MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS 449
488MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK 450
489MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_OUT16 451
490MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_5 452
491MX6Q_PAD_EIM_DA14__GPIO_3_14 453
492MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 454
493MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 455
494MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 456
495MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 457
496MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 458
497MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_OUT17 459
498MX6Q_PAD_EIM_DA15__GPIO_3_15 460
499MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 461
500MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 462
501MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT 463
502MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B 464
503MX6Q_PAD_EIM_WAIT__GPIO_5_0 465
504MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 466
505MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 467
506MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK 468
507MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 469
508MX6Q_PAD_EIM_BCLK__GPIO_6_31 470
509MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 471
510MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DSP_CLK 472
511MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DSP_CLK 473
512MX6Q_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 474
513MX6Q_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 475
514MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 476
515MX6Q_PAD_DI0_DISP_CLK__MMDC_DEBUG_0 477
516MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 478
517MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 479
518MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC 480
519MX6Q_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29 481
520MX6Q_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1 482
521MX6Q_PAD_DI0_PIN15__GPIO_4_17 483
522MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 484
523MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 485
524MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 486
525MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD 487
526MX6Q_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30 488
527MX6Q_PAD_DI0_PIN2__SDMA_DBG_CORE_STA_2 489
528MX6Q_PAD_DI0_PIN2__GPIO_4_18 490
529MX6Q_PAD_DI0_PIN2__MMDC_DEBUG_2 491
530MX6Q_PAD_DI0_PIN2__PL301_PER1_HADDR_9 492
531MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 493
532MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 494
533MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS 495
534MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31 496
535MX6Q_PAD_DI0_PIN3__SDMA_DBG_CORE_STA_3 497
536MX6Q_PAD_DI0_PIN3__GPIO_4_19 498
537MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 499
538MX6Q_PAD_DI0_PIN3__PL301_PER1_HADDR_10 500
539MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 501
540MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 502
541MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD 503
542MX6Q_PAD_DI0_PIN4__USDHC1_WP 504
543MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD 505
544MX6Q_PAD_DI0_PIN4__GPIO_4_20 506
545MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 507
546MX6Q_PAD_DI0_PIN4__PL301_PER1_HADDR_11 508
547MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 509
548MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 510
549MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK 511
550MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0 512
551MX6Q_PAD_DISP0_DAT0__SDMA_DBG_CORE_RUN 513
552MX6Q_PAD_DISP0_DAT0__GPIO_4_21 514
553MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 515
554MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 516
555MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 517
556MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI 518
557MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1 519
558MX6Q_PAD_DISP0_DAT1__SDMA_DBG_EVT_CHNSL 520
559MX6Q_PAD_DISP0_DAT1__GPIO_4_22 521
560MX6Q_PAD_DISP0_DAT1__MMDC_DEBUG_6 522
561MX6Q_PAD_DISP0_DAT1__PL301_PER1_HADR_12 523
562MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 524
563MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 525
564MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO 526
565MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2 527
566MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE 528
567MX6Q_PAD_DISP0_DAT2__GPIO_4_23 529
568MX6Q_PAD_DISP0_DAT2__MMDC_DEBUG_7 530
569MX6Q_PAD_DISP0_DAT2__PL301_PER1_HADR_13 531
570MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 532
571MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 533
572MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 534
573MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3 535
574MX6Q_PAD_DISP0_DAT3__SDMA_DBG_BUS_ERROR 536
575MX6Q_PAD_DISP0_DAT3__GPIO_4_24 537
576MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8 538
577MX6Q_PAD_DISP0_DAT3__PL301_PER1_HADR_14 539
578MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 540
579MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 541
580MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 542
581MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DBG_4 543
582MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB 544
583MX6Q_PAD_DISP0_DAT4__GPIO_4_25 545
584MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 546
585MX6Q_PAD_DISP0_DAT4__PL301_PER1_HADR_15 547
586MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 548
587MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 549
588MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 550
589MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS 551
590MX6Q_PAD_DISP0_DAT5__SDMA_DBG_MCH_DMBUS 552
591MX6Q_PAD_DISP0_DAT5__GPIO_4_26 553
592MX6Q_PAD_DISP0_DAT5__MMDC_DEBUG_10 554
593MX6Q_PAD_DISP0_DAT5__PL301_PER1_HADR_16 555
594MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 556
595MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 557
596MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 558
597MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC 559
598MX6Q_PAD_DISP0_DAT6__SDMA_DBG_RTBUF_WRT 560
599MX6Q_PAD_DISP0_DAT6__GPIO_4_27 561
600MX6Q_PAD_DISP0_DAT6__MMDC_DEBUG_11 562
601MX6Q_PAD_DISP0_DAT6__PL301_PER1_HADR_17 563
602MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 564
603MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 565
604MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY 566
605MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5 567
606MX6Q_PAD_DISP0_DAT7__SDMA_DBG_EVT_CHN_0 568
607MX6Q_PAD_DISP0_DAT7__GPIO_4_28 569
608MX6Q_PAD_DISP0_DAT7__MMDC_DEBUG_12 570
609MX6Q_PAD_DISP0_DAT7__PL301_PER1_HADR_18 571
610MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 572
611MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 573
612MX6Q_PAD_DISP0_DAT8__PWM1_PWMO 574
613MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B 575
614MX6Q_PAD_DISP0_DAT8__SDMA_DBG_EVT_CHN_1 576
615MX6Q_PAD_DISP0_DAT8__GPIO_4_29 577
616MX6Q_PAD_DISP0_DAT8__MMDC_DEBUG_13 578
617MX6Q_PAD_DISP0_DAT8__PL301_PER1_HADR_19 579
618MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 580
619MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 581
620MX6Q_PAD_DISP0_DAT9__PWM2_PWMO 582
621MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B 583
622MX6Q_PAD_DISP0_DAT9__SDMA_DBG_EVT_CHN_2 584
623MX6Q_PAD_DISP0_DAT9__GPIO_4_30 585
624MX6Q_PAD_DISP0_DAT9__MMDC_DEBUG_14 586
625MX6Q_PAD_DISP0_DAT9__PL301_PER1_HADR_20 587
626MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 588
627MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 589
628MX6Q_PAD_DISP0_DAT10__USDHC1_DBG_6 590
629MX6Q_PAD_DISP0_DAT10__SDMA_DBG_EVT_CHN3 591
630MX6Q_PAD_DISP0_DAT10__GPIO_4_31 592
631MX6Q_PAD_DISP0_DAT10__MMDC_DEBUG_15 593
632MX6Q_PAD_DISP0_DAT10__PL301_PER1_HADR21 594
633MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 595
634MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 596
635MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7 597
636MX6Q_PAD_DISP0_DAT11__SDMA_DBG_EVT_CHN4 598
637MX6Q_PAD_DISP0_DAT11__GPIO_5_5 599
638MX6Q_PAD_DISP0_DAT11__MMDC_DEBUG_16 600
639MX6Q_PAD_DISP0_DAT11__PL301_PER1_HADR22 601
640MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 602
641MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 603
642MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED 604
643MX6Q_PAD_DISP0_DAT12__SDMA_DBG_EVT_CHN5 605
644MX6Q_PAD_DISP0_DAT12__GPIO_5_6 606
645MX6Q_PAD_DISP0_DAT12__MMDC_DEBUG_17 607
646MX6Q_PAD_DISP0_DAT12__PL301_PER1_HADR23 608
647MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 609
648MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 610
649MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS 611
650MX6Q_PAD_DISP0_DAT13__SDMA_DBG_EVT_CHN0 612
651MX6Q_PAD_DISP0_DAT13__GPIO_5_7 613
652MX6Q_PAD_DISP0_DAT13__MMDC_DEBUG_18 614
653MX6Q_PAD_DISP0_DAT13__PL301_PER1_HADR24 615
654MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 616
655MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 617
656MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC 618
657MX6Q_PAD_DISP0_DAT14__SDMA_DBG_EVT_CHN1 619
658MX6Q_PAD_DISP0_DAT14__GPIO_5_8 620
659MX6Q_PAD_DISP0_DAT14__MMDC_DEBUG_19 621
660MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 622
661MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 623
662MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 624
663MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 625
664MX6Q_PAD_DISP0_DAT15__SDMA_DBG_EVT_CHN2 626
665MX6Q_PAD_DISP0_DAT15__GPIO_5_9 627
666MX6Q_PAD_DISP0_DAT15__MMDC_DEBUG_20 628
667MX6Q_PAD_DISP0_DAT15__PL301_PER1_HADR25 629
668MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 630
669MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 631
670MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI 632
671MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC 633
672MX6Q_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 634
673MX6Q_PAD_DISP0_DAT16__GPIO_5_10 635
674MX6Q_PAD_DISP0_DAT16__MMDC_DEBUG_21 636
675MX6Q_PAD_DISP0_DAT16__PL301_PER1_HADR26 637
676MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 638
677MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 639
678MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO 640
679MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD 641
680MX6Q_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 642
681MX6Q_PAD_DISP0_DAT17__GPIO_5_11 643
682MX6Q_PAD_DISP0_DAT17__MMDC_DEBUG_22 644
683MX6Q_PAD_DISP0_DAT17__PL301_PER1_HADR27 645
684MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 646
685MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 647
686MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 648
687MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS 649
688MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS 650
689MX6Q_PAD_DISP0_DAT18__GPIO_5_12 651
690MX6Q_PAD_DISP0_DAT18__MMDC_DEBUG_23 652
691MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 653
692MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 654
693MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 655
694MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK 656
695MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD 657
696MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC 658
697MX6Q_PAD_DISP0_DAT19__GPIO_5_13 659
698MX6Q_PAD_DISP0_DAT19__MMDC_DEBUG_24 660
699MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 661
700MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 662
701MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 663
702MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK 664
703MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC 665
704MX6Q_PAD_DISP0_DAT20__SDMA_DBG_EVT_CHN7 666
705MX6Q_PAD_DISP0_DAT20__GPIO_5_14 667
706MX6Q_PAD_DISP0_DAT20__MMDC_DEBUG_25 668
707MX6Q_PAD_DISP0_DAT20__PL301_PER1_HADR28 669
708MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 670
709MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 671
710MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI 672
711MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD 673
712MX6Q_PAD_DISP0_DAT21__SDMA_DBG_BUS_DEV0 674
713MX6Q_PAD_DISP0_DAT21__GPIO_5_15 675
714MX6Q_PAD_DISP0_DAT21__MMDC_DEBUG_26 676
715MX6Q_PAD_DISP0_DAT21__PL301_PER1_HADR29 677
716MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 678
717MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 679
718MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO 680
719MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS 681
720MX6Q_PAD_DISP0_DAT22__SDMA_DBG_BUS_DEV1 682
721MX6Q_PAD_DISP0_DAT22__GPIO_5_16 683
722MX6Q_PAD_DISP0_DAT22__MMDC_DEBUG_27 684
723MX6Q_PAD_DISP0_DAT22__PL301_PER1_HADR30 685
724MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 686
725MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 687
726MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 688
727MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD 689
728MX6Q_PAD_DISP0_DAT23__SDMA_DBG_BUS_DEV2 690
729MX6Q_PAD_DISP0_DAT23__GPIO_5_17 691
730MX6Q_PAD_DISP0_DAT23__MMDC_DEBUG_28 692
731MX6Q_PAD_DISP0_DAT23__PL301_PER1_HADR31 693
732MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED 694
733MX6Q_PAD_ENET_MDIO__ENET_MDIO 695
734MX6Q_PAD_ENET_MDIO__ESAI1_SCKR 696
735MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEV3 697
736MX6Q_PAD_ENET_MDIO__ENET_1588_EVT1_OUT 698
737MX6Q_PAD_ENET_MDIO__GPIO_1_22 699
738MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK 700
739MX6Q_PAD_ENET_REF_CLK__RESERVED_RSRVED 701
740MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 702
741MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR 703
742MX6Q_PAD_ENET_REF_CLK__SDMA_DBGBUS_DEV4 704
743MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 705
744MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK 706
745MX6Q_PAD_ENET_REF_CLK__USBPHY1_RX_SQH 707
746MX6Q_PAD_ENET_RX_ER__ENET_RX_ER 708
747MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR 709
748MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 710
749MX6Q_PAD_ENET_RX_ER__ENET_1588_EVT2_OUT 711
750MX6Q_PAD_ENET_RX_ER__GPIO_1_24 712
751MX6Q_PAD_ENET_RX_ER__PHY_TDI 713
752MX6Q_PAD_ENET_RX_ER__USBPHY1_RX_HS_RXD 714
753MX6Q_PAD_ENET_CRS_DV__RESERVED_RSRVED 715
754MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN 716
755MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT 717
756MX6Q_PAD_ENET_CRS_DV__SPDIF_EXTCLK 718
757MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 719
758MX6Q_PAD_ENET_CRS_DV__PHY_TDO 720
759MX6Q_PAD_ENET_CRS_DV__USBPHY1_RX_FS_RXD 721
760MX6Q_PAD_ENET_RXD1__MLB_MLBSIG 722
761MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 723
762MX6Q_PAD_ENET_RXD1__ESAI1_FST 724
763MX6Q_PAD_ENET_RXD1__ENET_1588_EVT3_OUT 725
764MX6Q_PAD_ENET_RXD1__GPIO_1_26 726
765MX6Q_PAD_ENET_RXD1__PHY_TCK 727
766MX6Q_PAD_ENET_RXD1__USBPHY1_RX_DISCON 728
767MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT 729
768MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 730
769MX6Q_PAD_ENET_RXD0__ESAI1_HCKT 731
770MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 732
771MX6Q_PAD_ENET_RXD0__GPIO_1_27 733
772MX6Q_PAD_ENET_RXD0__PHY_TMS 734
773MX6Q_PAD_ENET_RXD0__USBPHY1_PLL_CK20DIV 735
774MX6Q_PAD_ENET_TX_EN__RESERVED_RSRVED 736
775MX6Q_PAD_ENET_TX_EN__ENET_TX_EN 737
776MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 738
777MX6Q_PAD_ENET_TX_EN__GPIO_1_28 739
778MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI 740
779MX6Q_PAD_ENET_TX_EN__USBPHY2_RX_SQH 741
780MX6Q_PAD_ENET_TXD1__MLB_MLBCLK 742
781MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 743
782MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 744
783MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 745
784MX6Q_PAD_ENET_TXD1__GPIO_1_29 746
785MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO 747
786MX6Q_PAD_ENET_TXD1__USBPHY2_RX_HS_RXD 748
787MX6Q_PAD_ENET_TXD0__RESERVED_RSRVED 749
788MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 750
789MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 751
790MX6Q_PAD_ENET_TXD0__GPIO_1_30 752
791MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK 753
792MX6Q_PAD_ENET_TXD0__USBPHY2_RX_FS_RXD 754
793MX6Q_PAD_ENET_MDC__MLB_MLBDAT 755
794MX6Q_PAD_ENET_MDC__ENET_MDC 756
795MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 757
796MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN 758
797MX6Q_PAD_ENET_MDC__GPIO_1_31 759
798MX6Q_PAD_ENET_MDC__SATA_PHY_TMS 760
799MX6Q_PAD_ENET_MDC__USBPHY2_RX_DISCON 761
800MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 762
801MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 763
802MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 764
803MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 765
804MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 766
805MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 767
806MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 768
807MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 769
808MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 770
809MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 771
810MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 772
811MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 773
812MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 774
813MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 775
814MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 776
815MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 777
816MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 778
817MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 779
818MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 780
819MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 781
820MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 782
821MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 783
822MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 784
823MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 785
824MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 786
825MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 787
826MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 788
827MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 789
828MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 790
829MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 791
830MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 792
831MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 793
832MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 794
833MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 795
834MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 796
835MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 797
836MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 798
837MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 799
838MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 800
839MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 801
840MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 802
841MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 803
842MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 804
843MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 805
844MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 806
845MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 807
846MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 808
847MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 809
848MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 810
849MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 811
850MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 812
851MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 813
852MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 814
853MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 815
854MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 816
855MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 817
856MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS 818
857MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 819
858MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 820
859MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS 821
860MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET 822
861MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 823
862MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 824
863MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 825
864MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 826
865MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 827
866MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 828
867MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 829
868MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 830
869MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 831
870MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE 832
871MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 833
872MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 834
873MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 835
874MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 836
875MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 837
876MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 838
877MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 839
878MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 840
879MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 841
880MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 842
881MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 843
882MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 844
883MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 845
884MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 846
885MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 847
886MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 848
887MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 849
888MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 850
889MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 851
890MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 852
891MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 853
892MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 854
893MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 855
894MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 856
895MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 857
896MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 858
897MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 859
898MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 860
899MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 861
900MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 862
901MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 863
902MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 864
903MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 865
904MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 866
905MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 867
906MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 868
907MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 869
908MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 870
909MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 871
910MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 872
911MX6Q_PAD_KEY_COL0__ECSPI1_SCLK 873
912MX6Q_PAD_KEY_COL0__ENET_RDATA_3 874
913MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC 875
914MX6Q_PAD_KEY_COL0__KPP_COL_0 876
915MX6Q_PAD_KEY_COL0__UART4_TXD 877
916MX6Q_PAD_KEY_COL0__GPIO_4_6 878
917MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT 879
918MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST 880
919MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI 881
920MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 882
921MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 883
922MX6Q_PAD_KEY_ROW0__KPP_ROW_0 884
923MX6Q_PAD_KEY_ROW0__UART4_RXD 885
924MX6Q_PAD_KEY_ROW0__GPIO_4_7 886
925MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT 887
926MX6Q_PAD_KEY_ROW0__PL301_PER1_HADR_0 888
927MX6Q_PAD_KEY_COL1__ECSPI1_MISO 889
928MX6Q_PAD_KEY_COL1__ENET_MDIO 890
929MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 891
930MX6Q_PAD_KEY_COL1__KPP_COL_1 892
931MX6Q_PAD_KEY_COL1__UART5_TXD 893
932MX6Q_PAD_KEY_COL1__GPIO_4_8 894
933MX6Q_PAD_KEY_COL1__USDHC1_VSELECT 895
934MX6Q_PAD_KEY_COL1__PL301MX_PER1_HADR_1 896
935MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 897
936MX6Q_PAD_KEY_ROW1__ENET_COL 898
937MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 899
938MX6Q_PAD_KEY_ROW1__KPP_ROW_1 900
939MX6Q_PAD_KEY_ROW1__UART5_RXD 901
940MX6Q_PAD_KEY_ROW1__GPIO_4_9 902
941MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT 903
942MX6Q_PAD_KEY_ROW1__PL301_PER1_HADDR_2 904
943MX6Q_PAD_KEY_COL2__ECSPI1_SS1 905
944MX6Q_PAD_KEY_COL2__ENET_RDATA_2 906
945MX6Q_PAD_KEY_COL2__CAN1_TXCAN 907
946MX6Q_PAD_KEY_COL2__KPP_COL_2 908
947MX6Q_PAD_KEY_COL2__ENET_MDC 909
948MX6Q_PAD_KEY_COL2__GPIO_4_10 910
949MX6Q_PAD_KEY_COL2__USBOH3_H1_PWRCTL_WKP 911
950MX6Q_PAD_KEY_COL2__PL301_PER1_HADDR_3 912
951MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 913
952MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 914
953MX6Q_PAD_KEY_ROW2__CAN1_RXCAN 915
954MX6Q_PAD_KEY_ROW2__KPP_ROW_2 916
955MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT 917
956MX6Q_PAD_KEY_ROW2__GPIO_4_11 918
957MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 919
958MX6Q_PAD_KEY_ROW2__PL301_PER1_HADR_4 920
959MX6Q_PAD_KEY_COL3__ECSPI1_SS3 921
960MX6Q_PAD_KEY_COL3__ENET_CRS 922
961MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL 923
962MX6Q_PAD_KEY_COL3__KPP_COL_3 924
963MX6Q_PAD_KEY_COL3__I2C2_SCL 925
964MX6Q_PAD_KEY_COL3__GPIO_4_12 926
965MX6Q_PAD_KEY_COL3__SPDIF_IN1 927
966MX6Q_PAD_KEY_COL3__PL301_PER1_HADR_5 928
967MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT 929
968MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK 930
969MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 931
970MX6Q_PAD_KEY_ROW3__KPP_ROW_3 932
971MX6Q_PAD_KEY_ROW3__I2C2_SDA 933
972MX6Q_PAD_KEY_ROW3__GPIO_4_13 934
973MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT 935
974MX6Q_PAD_KEY_ROW3__PL301_PER1_HADR_6 936
975MX6Q_PAD_KEY_COL4__CAN2_TXCAN 937
976MX6Q_PAD_KEY_COL4__IPU1_SISG_4 938
977MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC 939
978MX6Q_PAD_KEY_COL4__KPP_COL_4 940
979MX6Q_PAD_KEY_COL4__UART5_RTS 941
980MX6Q_PAD_KEY_COL4__GPIO_4_14 942
981MX6Q_PAD_KEY_COL4__MMDC_DEBUG_49 943
982MX6Q_PAD_KEY_COL4__PL301_PER1_HADDR_7 944
983MX6Q_PAD_KEY_ROW4__CAN2_RXCAN 945
984MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 946
985MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR 947
986MX6Q_PAD_KEY_ROW4__KPP_ROW_4 948
987MX6Q_PAD_KEY_ROW4__UART5_CTS 949
988MX6Q_PAD_KEY_ROW4__GPIO_4_15 950
989MX6Q_PAD_KEY_ROW4__MMDC_DEBUG_50 951
990MX6Q_PAD_KEY_ROW4__PL301_PER1_HADR_8 952
991MX6Q_PAD_GPIO_0__CCM_CLKO 953
992MX6Q_PAD_GPIO_0__KPP_COL_5 954
993MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK 955
994MX6Q_PAD_GPIO_0__EPIT1_EPITO 956
995MX6Q_PAD_GPIO_0__GPIO_1_0 957
996MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR 958
997MX6Q_PAD_GPIO_0__SNVS_HP_WRAP_SNVS_VIO5 959
998MX6Q_PAD_GPIO_1__ESAI1_SCKR 960
999MX6Q_PAD_GPIO_1__WDOG2_WDOG_B 961
1000MX6Q_PAD_GPIO_1__KPP_ROW_5 962
1001MX6Q_PAD_GPIO_1__PWM2_PWMO 963
1002MX6Q_PAD_GPIO_1__GPIO_1_1 964
1003MX6Q_PAD_GPIO_1__USDHC1_CD 965
1004MX6Q_PAD_GPIO_1__SRC_TESTER_ACK 966
1005MX6Q_PAD_GPIO_9__ESAI1_FSR 967
1006MX6Q_PAD_GPIO_9__WDOG1_WDOG_B 968
1007MX6Q_PAD_GPIO_9__KPP_COL_6 969
1008MX6Q_PAD_GPIO_9__CCM_REF_EN_B 970
1009MX6Q_PAD_GPIO_9__PWM1_PWMO 971
1010MX6Q_PAD_GPIO_9__GPIO_1_9 972
1011MX6Q_PAD_GPIO_9__USDHC1_WP 973
1012MX6Q_PAD_GPIO_9__SRC_EARLY_RST 974
1013MX6Q_PAD_GPIO_3__ESAI1_HCKR 975
1014MX6Q_PAD_GPIO_3__OBSERVE_MUX_INT_OUT0 976
1015MX6Q_PAD_GPIO_3__I2C3_SCL 977
1016MX6Q_PAD_GPIO_3__ANATOP_24M_OUT 978
1017MX6Q_PAD_GPIO_3__CCM_CLKO2 979
1018MX6Q_PAD_GPIO_3__GPIO_1_3 980
1019MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC 981
1020MX6Q_PAD_GPIO_3__MLB_MLBCLK 982
1021MX6Q_PAD_GPIO_6__ESAI1_SCKT 983
1022MX6Q_PAD_GPIO_6__OBSERVE_MUX_INT_OUT1 984
1023MX6Q_PAD_GPIO_6__I2C3_SDA 985
1024MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 986
1025MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB 987
1026MX6Q_PAD_GPIO_6__GPIO_1_6 988
1027MX6Q_PAD_GPIO_6__USDHC2_LCTL 989
1028MX6Q_PAD_GPIO_6__MLB_MLBSIG 990
1029MX6Q_PAD_GPIO_2__ESAI1_FST 991
1030MX6Q_PAD_GPIO_2__OBSERVE_MUX_INT_OUT2 992
1031MX6Q_PAD_GPIO_2__KPP_ROW_6 993
1032MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 994
1033MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 995
1034MX6Q_PAD_GPIO_2__GPIO_1_2 996
1035MX6Q_PAD_GPIO_2__USDHC2_WP 997
1036MX6Q_PAD_GPIO_2__MLB_MLBDAT 998
1037MX6Q_PAD_GPIO_4__ESAI1_HCKT 999
1038MX6Q_PAD_GPIO_4__OBSERVE_MUX_INT_OUT3 1000
1039MX6Q_PAD_GPIO_4__KPP_COL_7 1001
1040MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 1002
1041MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 1003
1042MX6Q_PAD_GPIO_4__GPIO_1_4 1004
1043MX6Q_PAD_GPIO_4__USDHC2_CD 1005
1044MX6Q_PAD_GPIO_4__OCOTP_CRL_WRAR_FUSE_LA 1006
1045MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 1007
1046MX6Q_PAD_GPIO_5__OBSERVE_MUX_INT_OUT4 1008
1047MX6Q_PAD_GPIO_5__KPP_ROW_7 1009
1048MX6Q_PAD_GPIO_5__CCM_CLKO 1010
1049MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 1011
1050MX6Q_PAD_GPIO_5__GPIO_1_5 1012
1051MX6Q_PAD_GPIO_5__I2C3_SCL 1013
1052MX6Q_PAD_GPIO_5__CHEETAH_EVENTI 1014
1053MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 1015
1054MX6Q_PAD_GPIO_7__ECSPI5_RDY 1016
1055MX6Q_PAD_GPIO_7__EPIT1_EPITO 1017
1056MX6Q_PAD_GPIO_7__CAN1_TXCAN 1018
1057MX6Q_PAD_GPIO_7__UART2_TXD 1019
1058MX6Q_PAD_GPIO_7__GPIO_1_7 1020
1059MX6Q_PAD_GPIO_7__SPDIF_PLOCK 1021
1060MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HST_MODE 1022
1061MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 1023
1062MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT 1024
1063MX6Q_PAD_GPIO_8__EPIT2_EPITO 1025
1064MX6Q_PAD_GPIO_8__CAN1_RXCAN 1026
1065MX6Q_PAD_GPIO_8__UART2_RXD 1027
1066MX6Q_PAD_GPIO_8__GPIO_1_8 1028
1067MX6Q_PAD_GPIO_8__SPDIF_SRCLK 1029
1068MX6Q_PAD_GPIO_8__USBOH3_OTG_PWRCTL_WAK 1030
1069MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 1031
1070MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN 1032
1071MX6Q_PAD_GPIO_16__ENET_ETHERNET_REF_OUT 1033
1072MX6Q_PAD_GPIO_16__USDHC1_LCTL 1034
1073MX6Q_PAD_GPIO_16__SPDIF_IN1 1035
1074MX6Q_PAD_GPIO_16__GPIO_7_11 1036
1075MX6Q_PAD_GPIO_16__I2C3_SDA 1037
1076MX6Q_PAD_GPIO_16__SJC_DE_B 1038
1077MX6Q_PAD_GPIO_17__ESAI1_TX0 1039
1078MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN 1040
1079MX6Q_PAD_GPIO_17__CCM_PMIC_RDY 1041
1080MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 1042
1081MX6Q_PAD_GPIO_17__SPDIF_OUT1 1043
1082MX6Q_PAD_GPIO_17__GPIO_7_12 1044
1083MX6Q_PAD_GPIO_17__SJC_JTAG_ACT 1045
1084MX6Q_PAD_GPIO_18__ESAI1_TX1 1046
1085MX6Q_PAD_GPIO_18__ENET_RX_CLK 1047
1086MX6Q_PAD_GPIO_18__USDHC3_VSELECT 1048
1087MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 1049
1088MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK 1050
1089MX6Q_PAD_GPIO_18__GPIO_7_13 1051
1090MX6Q_PAD_GPIO_18__SNVS_HP_WRA_SNVS_VIO5 1052
1091MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST 1053
1092MX6Q_PAD_GPIO_19__KPP_COL_5 1054
1093MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT 1055
1094MX6Q_PAD_GPIO_19__SPDIF_OUT1 1056
1095MX6Q_PAD_GPIO_19__CCM_CLKO 1057
1096MX6Q_PAD_GPIO_19__ECSPI1_RDY 1058
1097MX6Q_PAD_GPIO_19__GPIO_4_5 1059
1098MX6Q_PAD_GPIO_19__ENET_TX_ER 1060
1099MX6Q_PAD_GPIO_19__SRC_INT_BOOT 1061
1100MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 1062
1101MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_MUX_12 1063
1102MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 1064
1103MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 1065
1104MX6Q_PAD_CSI0_PIXCLK___MMDC_DEBUG_29 1066
1105MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO 1067
1106MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 1068
1107MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_MUX_13 1069
1108MX6Q_PAD_CSI0_MCLK__CCM_CLKO 1070
1109MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 1071
1110MX6Q_PAD_CSI0_MCLK__GPIO_5_19 1072
1111MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 1073
1112MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL 1074
1113MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DA_EN 1075
1114MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 1076
1115MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_MUX_14 1077
1116MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 1078
1117MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 1079
1118MX6Q_PAD_CSI0_DATA_EN__MMDC_DEBUG_31 1080
1119MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK 1081
1120MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 1082
1121MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 1083
1122MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_MUX_15 1084
1123MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 1085
1124MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 1086
1125MX6Q_PAD_CSI0_VSYNC__MMDC_DEBUG_32 1087
1126MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 1088
1127MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 1089
1128MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 1090
1129MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK 1091
1130MX6Q_PAD_CSI0_DAT4__KPP_COL_5 1092
1131MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 1093
1132MX6Q_PAD_CSI0_DAT4__GPIO_5_22 1094
1133MX6Q_PAD_CSI0_DAT4__MMDC_DEBUG_43 1095
1134MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 1096
1135MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 1097
1136MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 1098
1137MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI 1099
1138MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 1100
1139MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 1101
1140MX6Q_PAD_CSI0_DAT5__GPIO_5_23 1102
1141MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 1103
1142MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 1104
1143MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 1105
1144MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 1106
1145MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO 1107
1146MX6Q_PAD_CSI0_DAT6__KPP_COL_6 1108
1147MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 1109
1148MX6Q_PAD_CSI0_DAT6__GPIO_5_24 1110
1149MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 1111
1150MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 1112
1151MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 1113
1152MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 1114
1153MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 1115
1154MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 1116
1155MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 1117
1156MX6Q_PAD_CSI0_DAT7__GPIO_5_25 1118
1157MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 1119
1158MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 1120
1159MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 1121
1160MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 1122
1161MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK 1123
1162MX6Q_PAD_CSI0_DAT8__KPP_COL_7 1124
1163MX6Q_PAD_CSI0_DAT8__I2C1_SDA 1125
1164MX6Q_PAD_CSI0_DAT8__GPIO_5_26 1126
1165MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 1127
1166MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 1128
1167MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 1129
1168MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 1130
1169MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI 1131
1170MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 1132
1171MX6Q_PAD_CSI0_DAT9__I2C1_SCL 1133
1172MX6Q_PAD_CSI0_DAT9__GPIO_5_27 1134
1173MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 1135
1174MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 1136
1175MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 1137
1176MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC 1138
1177MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO 1139
1178MX6Q_PAD_CSI0_DAT10__UART1_TXD 1140
1179MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 1141
1180MX6Q_PAD_CSI0_DAT10__GPIO_5_28 1142
1181MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 1143
1182MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 1144
1183MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 1145
1184MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS 1146
1185MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 1147
1186MX6Q_PAD_CSI0_DAT11__UART1_RXD 1148
1187MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 1149
1188MX6Q_PAD_CSI0_DAT11__GPIO_5_29 1150
1189MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 1151
1190MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 1152
1191MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 1153
1192MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 1154
1193MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_MUX_16 1155
1194MX6Q_PAD_CSI0_DAT12__UART4_TXD 1156
1195MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 1157
1196MX6Q_PAD_CSI0_DAT12__GPIO_5_30 1158
1197MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 1159
1198MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 1160
1199MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 1161
1200MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 1162
1201MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_MUX_17 1163
1202MX6Q_PAD_CSI0_DAT13__UART4_RXD 1164
1203MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 1165
1204MX6Q_PAD_CSI0_DAT13__GPIO_5_31 1166
1205MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 1167
1206MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 1168
1207MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 1169
1208MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 1170
1209MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_MUX_18 1171
1210MX6Q_PAD_CSI0_DAT14__UART5_TXD 1172
1211MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 1173
1212MX6Q_PAD_CSI0_DAT14__GPIO_6_0 1174
1213MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 1175
1214MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 1176
1215MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 1177
1216MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 1178
1217MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_MUX_19 1179
1218MX6Q_PAD_CSI0_DAT15__UART5_RXD 1180
1219MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 1181
1220MX6Q_PAD_CSI0_DAT15__GPIO_6_1 1182
1221MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 1183
1222MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 1184
1223MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 1185
1224MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 1186
1225MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_MUX_20 1187
1226MX6Q_PAD_CSI0_DAT16__UART4_RTS 1188
1227MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 1189
1228MX6Q_PAD_CSI0_DAT16__GPIO_6_2 1190
1229MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 1191
1230MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 1192
1231MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 1193
1232MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 1194
1233MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_MUX_21 1195
1234MX6Q_PAD_CSI0_DAT17__UART4_CTS 1196
1235MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 1197
1236MX6Q_PAD_CSI0_DAT17__GPIO_6_3 1198
1237MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 1199
1238MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 1200
1239MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 1201
1240MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 1202
1241MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_MUX_22 1203
1242MX6Q_PAD_CSI0_DAT18__UART5_RTS 1204
1243MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 1205
1244MX6Q_PAD_CSI0_DAT18__GPIO_6_4 1206
1245MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 1207
1246MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 1208
1247MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 1209
1248MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 1210
1249MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_MUX_23 1211
1250MX6Q_PAD_CSI0_DAT19__UART5_CTS 1212
1251MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 1213
1252MX6Q_PAD_CSI0_DAT19__GPIO_6_5 1214
1253MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 1215
1254MX6Q_PAD_CSI0_DAT19__ANATOP_TESTO_9 1216
1255MX6Q_PAD_JTAG_TMS__SJC_TMS 1217
1256MX6Q_PAD_JTAG_MOD__SJC_MOD 1218
1257MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB 1219
1258MX6Q_PAD_JTAG_TDI__SJC_TDI 1220
1259MX6Q_PAD_JTAG_TCK__SJC_TCK 1221
1260MX6Q_PAD_JTAG_TDO__SJC_TDO 1222
1261MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 1223
1262MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 1224
1263MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 1225
1264MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 1226
1265MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 1227
1266MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 1228
1267MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 1229
1268MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 1230
1269MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 1231
1270MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 1232
1271MX6Q_PAD_TAMPER__SNVS_LP_WRAP_SNVS_TD1 1233
1272MX6Q_PAD_PMIC_ON_REQ__SNVS_LPWRAP_WKALM 1234
1273MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_STBYRQ 1235
1274MX6Q_PAD_POR_B__SRC_POR_B 1236
1275MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 1237
1276MX6Q_PAD_RESET_IN_B__SRC_RESET_B 1238
1277MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 1239
1278MX6Q_PAD_TEST_MODE__TCU_TEST_MODE 1240
1279MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 1241
1280MX6Q_PAD_SD3_DAT7__UART1_TXD 1242
1281MX6Q_PAD_SD3_DAT7__PCIE_CTRL_MUX_24 1243
1282MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 1244
1283MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 1245
1284MX6Q_PAD_SD3_DAT7__GPIO_6_17 1246
1285MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_IN_12 1247
1286MX6Q_PAD_SD3_DAT7__USBPHY2_CLK20DIV 1248
1287MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 1249
1288MX6Q_PAD_SD3_DAT6__UART1_RXD 1250
1289MX6Q_PAD_SD3_DAT6__PCIE_CTRL_MUX_25 1251
1290MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 1252
1291MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 1253
1292MX6Q_PAD_SD3_DAT6__GPIO_6_18 1254
1293MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_IN_13 1255
1294MX6Q_PAD_SD3_DAT6__ANATOP_TESTO_10 1256
1295MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 1257
1296MX6Q_PAD_SD3_DAT5__UART2_TXD 1258
1297MX6Q_PAD_SD3_DAT5__PCIE_CTRL_MUX_26 1259
1298MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 1260
1299MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 1261
1300MX6Q_PAD_SD3_DAT5__GPIO_7_0 1262
1301MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_IN_14 1263
1302MX6Q_PAD_SD3_DAT5__ANATOP_TESTO_11 1264
1303MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 1265
1304MX6Q_PAD_SD3_DAT4__UART2_RXD 1266
1305MX6Q_PAD_SD3_DAT4__PCIE_CTRL_MUX_27 1267
1306MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 1268
1307MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 1269
1308MX6Q_PAD_SD3_DAT4__GPIO_7_1 1270
1309MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_IN_15 1271
1310MX6Q_PAD_SD3_DAT4__ANATOP_TESTO_12 1272
1311MX6Q_PAD_SD3_CMD__USDHC3_CMD 1273
1312MX6Q_PAD_SD3_CMD__UART2_CTS 1274
1313MX6Q_PAD_SD3_CMD__CAN1_TXCAN 1275
1314MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 1276
1315MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 1277
1316MX6Q_PAD_SD3_CMD__GPIO_7_2 1278
1317MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_IN_16 1279
1318MX6Q_PAD_SD3_CMD__ANATOP_TESTO_13 1280
1319MX6Q_PAD_SD3_CLK__USDHC3_CLK 1281
1320MX6Q_PAD_SD3_CLK__UART2_RTS 1282
1321MX6Q_PAD_SD3_CLK__CAN1_RXCAN 1283
1322MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 1284
1323MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 1285
1324MX6Q_PAD_SD3_CLK__GPIO_7_3 1286
1325MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_IN_17 1287
1326MX6Q_PAD_SD3_CLK__ANATOP_TESTO_14 1288
1327MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 1289
1328MX6Q_PAD_SD3_DAT0__UART1_CTS 1290
1329MX6Q_PAD_SD3_DAT0__CAN2_TXCAN 1291
1330MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 1292
1331MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 1293
1332MX6Q_PAD_SD3_DAT0__GPIO_7_4 1294
1333MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_IN_18 1295
1334MX6Q_PAD_SD3_DAT0__ANATOP_TESTO_15 1296
1335MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 1297
1336MX6Q_PAD_SD3_DAT1__UART1_RTS 1298
1337MX6Q_PAD_SD3_DAT1__CAN2_RXCAN 1299
1338MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 1300
1339MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 1301
1340MX6Q_PAD_SD3_DAT1__GPIO_7_5 1302
1341MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_IN_19 1303
1342MX6Q_PAD_SD3_DAT1__ANATOP_TESTI_0 1304
1343MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 1305
1344MX6Q_PAD_SD3_DAT2__PCIE_CTRL_MUX_28 1306
1345MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 1307
1346MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 1308
1347MX6Q_PAD_SD3_DAT2__GPIO_7_6 1309
1348MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_IN_20 1310
1349MX6Q_PAD_SD3_DAT2__ANATOP_TESTI_1 1311
1350MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 1312
1351MX6Q_PAD_SD3_DAT3__UART3_CTS 1313
1352MX6Q_PAD_SD3_DAT3__PCIE_CTRL_MUX_29 1314
1353MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 1315
1354MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 1316
1355MX6Q_PAD_SD3_DAT3__GPIO_7_7 1317
1356MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_IN_21 1318
1357MX6Q_PAD_SD3_DAT3__ANATOP_TESTI_2 1319
1358MX6Q_PAD_SD3_RST__USDHC3_RST 1320
1359MX6Q_PAD_SD3_RST__UART3_RTS 1321
1360MX6Q_PAD_SD3_RST__PCIE_CTRL_MUX_30 1322
1361MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 1323
1362MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 1324
1363MX6Q_PAD_SD3_RST__GPIO_7_8 1325
1364MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_IN_22 1326
1365MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 1327
1366MX6Q_PAD_NANDF_CLE__RAWNAND_CLE 1328
1367MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 1329
1368MX6Q_PAD_NANDF_CLE__PCIE_CTRL_MUX_31 1330
1369MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OT11 1331
1370MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OT11 1332
1371MX6Q_PAD_NANDF_CLE__GPIO_6_7 1333
1372MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_IN23 1334
1373MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 1335
1374MX6Q_PAD_NANDF_ALE__RAWNAND_ALE 1336
1375MX6Q_PAD_NANDF_ALE__USDHC4_RST 1337
1376MX6Q_PAD_NANDF_ALE__PCIE_CTRL_MUX_0 1338
1377MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OT12 1339
1378MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OT12 1340
1379MX6Q_PAD_NANDF_ALE__GPIO_6_8 1341
1380MX6Q_PAD_NANDF_ALE__MIPI_CR_DPHY_IN_24 1342
1381MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 1343
1382MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN 1344
1383MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 1345
1384MX6Q_PAD_NANDF_WP_B__PCIE_CTRL__MUX_1 1346
1385MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFDOT13 1347
1386MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFDOT13 1348
1387MX6Q_PAD_NANDF_WP_B__GPIO_6_9 1349
1388MX6Q_PAD_NANDF_WP_B__MIPI_CR_DPHY_OUT32 1350
1389MX6Q_PAD_NANDF_WP_B__PL301_PER1_HSIZE_0 1351
1390MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 1352
1391MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 1353
1392MX6Q_PAD_NANDF_RB0__PCIE_CTRL_MUX_2 1354
1393MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OT14 1355
1394MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OT14 1356
1395MX6Q_PAD_NANDF_RB0__GPIO_6_10 1357
1396MX6Q_PAD_NANDF_RB0__MIPI_CR_DPHY_OUT_33 1358
1397MX6Q_PAD_NANDF_RB0__PL301_PER1_HSIZE_1 1359
1398MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N 1360
1399MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OT15 1361
1400MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OT15 1362
1401MX6Q_PAD_NANDF_CS0__GPIO_6_11 1363
1402MX6Q_PAD_NANDF_CS0__PL301_PER1_HSIZE_2 1364
1403MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N 1365
1404MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT 1366
1405MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT 1367
1406MX6Q_PAD_NANDF_CS1__PCIE_CTRL_MUX_3 1368
1407MX6Q_PAD_NANDF_CS1__GPIO_6_14 1369
1408MX6Q_PAD_NANDF_CS1__PL301_PER1_HRDYOUT 1370
1409MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N 1371
1410MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 1372
1411MX6Q_PAD_NANDF_CS2__ESAI1_TX0 1373
1412MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE 1374
1413MX6Q_PAD_NANDF_CS2__CCM_CLKO2 1375
1414MX6Q_PAD_NANDF_CS2__GPIO_6_15 1376
1415MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 1377
1416MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N 1378
1417MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 1379
1418MX6Q_PAD_NANDF_CS3__ESAI1_TX1 1380
1419MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 1381
1420MX6Q_PAD_NANDF_CS3__PCIE_CTRL_MUX_4 1382
1421MX6Q_PAD_NANDF_CS3__GPIO_6_16 1383
1422MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 1384
1423MX6Q_PAD_NANDF_CS3__TPSMP_CLK 1385
1424MX6Q_PAD_SD4_CMD__USDHC4_CMD 1386
1425MX6Q_PAD_SD4_CMD__RAWNAND_RDN 1387
1426MX6Q_PAD_SD4_CMD__UART3_TXD 1388
1427MX6Q_PAD_SD4_CMD__PCIE_CTRL_MUX_5 1389
1428MX6Q_PAD_SD4_CMD__GPIO_7_9 1390
1429MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR 1391
1430MX6Q_PAD_SD4_CLK__USDHC4_CLK 1392
1431MX6Q_PAD_SD4_CLK__RAWNAND_WRN 1393
1432MX6Q_PAD_SD4_CLK__UART3_RXD 1394
1433MX6Q_PAD_SD4_CLK__PCIE_CTRL_MUX_6 1395
1434MX6Q_PAD_SD4_CLK__GPIO_7_10 1396
1435MX6Q_PAD_NANDF_D0__RAWNAND_D0 1397
1436MX6Q_PAD_NANDF_D0__USDHC1_DAT4 1398
1437MX6Q_PAD_NANDF_D0__GPU3D_GPU_DBG_OUT_0 1399
1438MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT16 1400
1439MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT16 1401
1440MX6Q_PAD_NANDF_D0__GPIO_2_0 1402
1441MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 1403
1442MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 1404
1443MX6Q_PAD_NANDF_D1__RAWNAND_D1 1405
1444MX6Q_PAD_NANDF_D1__USDHC1_DAT5 1406
1445MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT1 1407
1446MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT17 1408
1447MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT17 1409
1448MX6Q_PAD_NANDF_D1__GPIO_2_1 1410
1449MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 1411
1450MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 1412
1451MX6Q_PAD_NANDF_D2__RAWNAND_D2 1413
1452MX6Q_PAD_NANDF_D2__USDHC1_DAT6 1414
1453MX6Q_PAD_NANDF_D2__GPU3D_GPU_DBG_OUT_2 1415
1454MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT18 1416
1455MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT18 1417
1456MX6Q_PAD_NANDF_D2__GPIO_2_2 1418
1457MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 1419
1458MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 1420
1459MX6Q_PAD_NANDF_D3__RAWNAND_D3 1421
1460MX6Q_PAD_NANDF_D3__USDHC1_DAT7 1422
1461MX6Q_PAD_NANDF_D3__GPU3D_GPU_DBG_OUT_3 1423
1462MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT19 1424
1463MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT19 1425
1464MX6Q_PAD_NANDF_D3__GPIO_2_3 1426
1465MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 1427
1466MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 1428
1467MX6Q_PAD_NANDF_D4__RAWNAND_D4 1429
1468MX6Q_PAD_NANDF_D4__USDHC2_DAT4 1430
1469MX6Q_PAD_NANDF_D4__GPU3D_GPU_DBG_OUT_4 1431
1470MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT20 1432
1471MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT20 1433
1472MX6Q_PAD_NANDF_D4__GPIO_2_4 1434
1473MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 1435
1474MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 1436
1475MX6Q_PAD_NANDF_D5__RAWNAND_D5 1437
1476MX6Q_PAD_NANDF_D5__USDHC2_DAT5 1438
1477MX6Q_PAD_NANDF_D5__GPU3D_GPU_DBG_OUT_5 1439
1478MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT21 1440
1479MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT21 1441
1480MX6Q_PAD_NANDF_D5__GPIO_2_5 1442
1481MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 1443
1482MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 1444
1483MX6Q_PAD_NANDF_D6__RAWNAND_D6 1445
1484MX6Q_PAD_NANDF_D6__USDHC2_DAT6 1446
1485MX6Q_PAD_NANDF_D6__GPU3D_GPU_DBG_OUT_6 1447
1486MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT22 1448
1487MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT22 1449
1488MX6Q_PAD_NANDF_D6__GPIO_2_6 1450
1489MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 1451
1490MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 1452
1491MX6Q_PAD_NANDF_D7__RAWNAND_D7 1453
1492MX6Q_PAD_NANDF_D7__USDHC2_DAT7 1454
1493MX6Q_PAD_NANDF_D7__GPU3D_GPU_DBG_OUT_7 1455
1494MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT23 1456
1495MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT23 1457
1496MX6Q_PAD_NANDF_D7__GPIO_2_7 1458
1497MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 1459
1498MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 1460
1499MX6Q_PAD_SD4_DAT0__RAWNAND_D8 1461
1500MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 1462
1501MX6Q_PAD_SD4_DAT0__RAWNAND_DQS 1463
1502MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT24 1464
1503MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT24 1465
1504MX6Q_PAD_SD4_DAT0__GPIO_2_8 1466
1505MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 1467
1506MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 1468
1507MX6Q_PAD_SD4_DAT1__RAWNAND_D9 1469
1508MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 1470
1509MX6Q_PAD_SD4_DAT1__PWM3_PWMO 1471
1510MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT25 1472
1511MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT25 1473
1512MX6Q_PAD_SD4_DAT1__GPIO_2_9 1474
1513MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 1475
1514MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 1476
1515MX6Q_PAD_SD4_DAT2__RAWNAND_D10 1477
1516MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 1478
1517MX6Q_PAD_SD4_DAT2__PWM4_PWMO 1479
1518MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT26 1480
1519MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT26 1481
1520MX6Q_PAD_SD4_DAT2__GPIO_2_10 1482
1521MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 1483
1522MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 1484
1523MX6Q_PAD_SD4_DAT3__RAWNAND_D11 1485
1524MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 1486
1525MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT27 1487
1526MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT27 1488
1527MX6Q_PAD_SD4_DAT3__GPIO_2_11 1489
1528MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 1490
1529MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 1491
1530MX6Q_PAD_SD4_DAT4__RAWNAND_D12 1492
1531MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 1493
1532MX6Q_PAD_SD4_DAT4__UART2_RXD 1494
1533MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT28 1495
1534MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT28 1496
1535MX6Q_PAD_SD4_DAT4__GPIO_2_12 1497
1536MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 1498
1537MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 1499
1538MX6Q_PAD_SD4_DAT5__RAWNAND_D13 1500
1539MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 1501
1540MX6Q_PAD_SD4_DAT5__UART2_RTS 1502
1541MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT29 1503
1542MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT29 1504
1543MX6Q_PAD_SD4_DAT5__GPIO_2_13 1505
1544MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 1506
1545MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 1507
1546MX6Q_PAD_SD4_DAT6__RAWNAND_D14 1508
1547MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 1509
1548MX6Q_PAD_SD4_DAT6__UART2_CTS 1510
1549MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT30 1511
1550MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT30 1512
1551MX6Q_PAD_SD4_DAT6__GPIO_2_14 1513
1552MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 1514
1553MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 1515
1554MX6Q_PAD_SD4_DAT7__RAWNAND_D15 1516
1555MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 1517
1556MX6Q_PAD_SD4_DAT7__UART2_TXD 1518
1557MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT31 1519
1558MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT31 1520
1559MX6Q_PAD_SD4_DAT7__GPIO_2_15 1521
1560MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 1522
1561MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 1523
1562MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 1524
1563MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 1525
1564MX6Q_PAD_SD1_DAT1__PWM3_PWMO 1526
1565MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 1527
1566MX6Q_PAD_SD1_DAT1__PCIE_CTRL_MUX_7 1528
1567MX6Q_PAD_SD1_DAT1__GPIO_1_17 1529
1568MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 1530
1569MX6Q_PAD_SD1_DAT1__ANATOP_TESTO_8 1531
1570MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 1532
1571MX6Q_PAD_SD1_DAT0__ECSPI5_MISO 1533
1572MX6Q_PAD_SD1_DAT0__CAAM_WRAP_RNG_OSCOBS 1534
1573MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 1535
1574MX6Q_PAD_SD1_DAT0__PCIE_CTRL_MUX_8 1536
1575MX6Q_PAD_SD1_DAT0__GPIO_1_16 1537
1576MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 1538
1577MX6Q_PAD_SD1_DAT0__ANATOP_TESTO_7 1539
1578MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 1540
1579MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 1541
1580MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 1542
1581MX6Q_PAD_SD1_DAT3__PWM1_PWMO 1543
1582MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B 1544
1583MX6Q_PAD_SD1_DAT3__GPIO_1_21 1545
1584MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB 1546
1585MX6Q_PAD_SD1_DAT3__ANATOP_TESTO_6 1547
1586MX6Q_PAD_SD1_CMD__USDHC1_CMD 1548
1587MX6Q_PAD_SD1_CMD__ECSPI5_MOSI 1549
1588MX6Q_PAD_SD1_CMD__PWM4_PWMO 1550
1589MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 1551
1590MX6Q_PAD_SD1_CMD__GPIO_1_18 1552
1591MX6Q_PAD_SD1_CMD__ANATOP_TESTO_5 1553
1592MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 1554
1593MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 1555
1594MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 1556
1595MX6Q_PAD_SD1_DAT2__PWM2_PWMO 1557
1596MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B 1558
1597MX6Q_PAD_SD1_DAT2__GPIO_1_19 1559
1598MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB 1560
1599MX6Q_PAD_SD1_DAT2__ANATOP_TESTO_4 1561
1600MX6Q_PAD_SD1_CLK__USDHC1_CLK 1562
1601MX6Q_PAD_SD1_CLK__ECSPI5_SCLK 1563
1602MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT 1564
1603MX6Q_PAD_SD1_CLK__GPT_CLKIN 1565
1604MX6Q_PAD_SD1_CLK__GPIO_1_20 1566
1605MX6Q_PAD_SD1_CLK__PHY_DTB_0 1567
1606MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 1568
1607MX6Q_PAD_SD2_CLK__USDHC2_CLK 1569
1608MX6Q_PAD_SD2_CLK__ECSPI5_SCLK 1570
1609MX6Q_PAD_SD2_CLK__KPP_COL_5 1571
1610MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS 1572
1611MX6Q_PAD_SD2_CLK__PCIE_CTRL_MUX_9 1573
1612MX6Q_PAD_SD2_CLK__GPIO_1_10 1574
1613MX6Q_PAD_SD2_CLK__PHY_DTB_1 1575
1614MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 1576
1615MX6Q_PAD_SD2_CMD__USDHC2_CMD 1577
1616MX6Q_PAD_SD2_CMD__ECSPI5_MOSI 1578
1617MX6Q_PAD_SD2_CMD__KPP_ROW_5 1579
1618MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC 1580
1619MX6Q_PAD_SD2_CMD__PCIE_CTRL_MUX_10 1581
1620MX6Q_PAD_SD2_CMD__GPIO_1_11 1582
1621MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 1583
1622MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 1584
1623MX6Q_PAD_SD2_DAT3__KPP_COL_6 1585
1624MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC 1586
1625MX6Q_PAD_SD2_DAT3__PCIE_CTRL_MUX_11 1587
1626MX6Q_PAD_SD2_DAT3__GPIO_1_12 1588
1627MX6Q_PAD_SD2_DAT3__SJC_DONE 1589
1628MX6Q_PAD_SD2_DAT3__ANATOP_TESTO_3 1590
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt
new file mode 100644
index 00000000000..f7e8e8f4d9a
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt
@@ -0,0 +1,918 @@
1* Freescale MXS Pin Controller
2
3The pins controlled by mxs pin controller are organized in banks, each bank
4has 32 pins. Each pin has 4 multiplexing functions, and generally, the 4th
5function is GPIO. The configuration on the pins includes drive strength,
6voltage and pull-up.
7
8Required properties:
9- compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl"
10- reg: Should contain the register physical address and length for the
11 pin controller.
12
13Please refer to pinctrl-bindings.txt in this directory for details of the
14common pinctrl bindings used by client devices.
15
16The node of mxs pin controller acts as a container for an arbitrary number of
17subnodes. Each of these subnodes represents some desired configuration for
18a group of pins, and only affects those parameters that are explicitly listed.
19In other words, a subnode that describes a drive strength parameter implies no
20information about pull-up. For this reason, even seemingly boolean values are
21actually tristates in this binding: unspecified, off, or on. Unspecified is
22represented as an absent property, and off/on are represented as integer
23values 0 and 1.
24
25Those subnodes under mxs pin controller node will fall into two categories.
26One is to set up a group of pins for a function, both mux selection and pin
27configurations, and it's called group node in the binding document. The other
28one is to adjust the pin configuration for some particular pins that need a
29different configuration than what is defined in group node. The binding
30document calls this type of node config node.
31
32On mxs, there is no hardware pin group. The pin group in this binding only
33means a group of pins put together for particular peripheral to work in
34particular function, like SSP0 functioning as mmc0-8bit. That said, the
35group node should include all the pins needed for one function rather than
36having these pins defined in several group nodes. It also means each of
37"pinctrl-*" phandle in client device node should only have one group node
38pointed in there, while the phandle can have multiple config node referenced
39there to adjust configurations for some pins in the group.
40
41Required subnode-properties:
42- fsl,pinmux-ids: An integer array. Each integer in the array specify a pin
43 with given mux function, with bank, pin and mux packed as below.
44
45 [15..12] : bank number
46 [11..4] : pin number
47 [3..0] : mux selection
48
49 This integer with mux selection packed is used as an entity by both group
50 and config nodes to identify a pin. The mux selection in the integer takes
51 effects only on group node, and will get ignored by driver with config node,
52 since config node is only meant to set up pin configurations.
53
54 Valid values for these integers are listed below.
55
56- reg: Should be the index of the group nodes for same function. This property
57 is required only for group nodes, and should not be present in any config
58 nodes.
59
60Optional subnode-properties:
61- fsl,drive-strength: Integer.
62 0: 4 mA
63 1: 8 mA
64 2: 12 mA
65 3: 16 mA
66- fsl,voltage: Integer.
67 0: 1.8 V
68 1: 3.3 V
69- fsl,pull-up: Integer.
70 0: Disable the internal pull-up
71 1: Enable the internal pull-up
72
73Examples:
74
75pinctrl@80018000 {
76 #address-cells = <1>;
77 #size-cells = <0>;
78 compatible = "fsl,imx28-pinctrl";
79 reg = <0x80018000 2000>;
80
81 mmc0_8bit_pins_a: mmc0-8bit@0 {
82 reg = <0>;
83 fsl,pinmux-ids = <
84 0x2000 0x2010 0x2020 0x2030
85 0x2040 0x2050 0x2060 0x2070
86 0x2080 0x2090 0x20a0>;
87 fsl,drive-strength = <1>;
88 fsl,voltage = <1>;
89 fsl,pull-up = <1>;
90 };
91
92 mmc_cd_cfg: mmc-cd-cfg {
93 fsl,pinmux-ids = <0x2090>;
94 fsl,pull-up = <0>;
95 };
96
97 mmc_sck_cfg: mmc-sck-cfg {
98 fsl,pinmux-ids = <0x20a0>;
99 fsl,drive-strength = <2>;
100 fsl,pull-up = <0>;
101 };
102};
103
104In this example, group node mmc0-8bit defines a group of pins for mxs SSP0
105to function as a 8-bit mmc device, with 8mA, 3.3V and pull-up configurations
106applied on all these pins. And config nodes mmc-cd-cfg and mmc-sck-cfg are
107adjusting the configuration for pins card-detection and clock from what group
108node mmc0-8bit defines. Only the configuration properties to be adjusted need
109to be listed in the config nodes.
110
111Valid values for i.MX28 pinmux-id:
112
113pinmux id
114------ --
115MX28_PAD_GPMI_D00__GPMI_D0 0x0000
116MX28_PAD_GPMI_D01__GPMI_D1 0x0010
117MX28_PAD_GPMI_D02__GPMI_D2 0x0020
118MX28_PAD_GPMI_D03__GPMI_D3 0x0030
119MX28_PAD_GPMI_D04__GPMI_D4 0x0040
120MX28_PAD_GPMI_D05__GPMI_D5 0x0050
121MX28_PAD_GPMI_D06__GPMI_D6 0x0060
122MX28_PAD_GPMI_D07__GPMI_D7 0x0070
123MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100
124MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110
125MX28_PAD_GPMI_CE2N__GPMI_CE2N 0x0120
126MX28_PAD_GPMI_CE3N__GPMI_CE3N 0x0130
127MX28_PAD_GPMI_RDY0__GPMI_READY0 0x0140
128MX28_PAD_GPMI_RDY1__GPMI_READY1 0x0150
129MX28_PAD_GPMI_RDY2__GPMI_READY2 0x0160
130MX28_PAD_GPMI_RDY3__GPMI_READY3 0x0170
131MX28_PAD_GPMI_RDN__GPMI_RDN 0x0180
132MX28_PAD_GPMI_WRN__GPMI_WRN 0x0190
133MX28_PAD_GPMI_ALE__GPMI_ALE 0x01a0
134MX28_PAD_GPMI_CLE__GPMI_CLE 0x01b0
135MX28_PAD_GPMI_RESETN__GPMI_RESETN 0x01c0
136MX28_PAD_LCD_D00__LCD_D0 0x1000
137MX28_PAD_LCD_D01__LCD_D1 0x1010
138MX28_PAD_LCD_D02__LCD_D2 0x1020
139MX28_PAD_LCD_D03__LCD_D3 0x1030
140MX28_PAD_LCD_D04__LCD_D4 0x1040
141MX28_PAD_LCD_D05__LCD_D5 0x1050
142MX28_PAD_LCD_D06__LCD_D6 0x1060
143MX28_PAD_LCD_D07__LCD_D7 0x1070
144MX28_PAD_LCD_D08__LCD_D8 0x1080
145MX28_PAD_LCD_D09__LCD_D9 0x1090
146MX28_PAD_LCD_D10__LCD_D10 0x10a0
147MX28_PAD_LCD_D11__LCD_D11 0x10b0
148MX28_PAD_LCD_D12__LCD_D12 0x10c0
149MX28_PAD_LCD_D13__LCD_D13 0x10d0
150MX28_PAD_LCD_D14__LCD_D14 0x10e0
151MX28_PAD_LCD_D15__LCD_D15 0x10f0
152MX28_PAD_LCD_D16__LCD_D16 0x1100
153MX28_PAD_LCD_D17__LCD_D17 0x1110
154MX28_PAD_LCD_D18__LCD_D18 0x1120
155MX28_PAD_LCD_D19__LCD_D19 0x1130
156MX28_PAD_LCD_D20__LCD_D20 0x1140
157MX28_PAD_LCD_D21__LCD_D21 0x1150
158MX28_PAD_LCD_D22__LCD_D22 0x1160
159MX28_PAD_LCD_D23__LCD_D23 0x1170
160MX28_PAD_LCD_RD_E__LCD_RD_E 0x1180
161MX28_PAD_LCD_WR_RWN__LCD_WR_RWN 0x1190
162MX28_PAD_LCD_RS__LCD_RS 0x11a0
163MX28_PAD_LCD_CS__LCD_CS 0x11b0
164MX28_PAD_LCD_VSYNC__LCD_VSYNC 0x11c0
165MX28_PAD_LCD_HSYNC__LCD_HSYNC 0x11d0
166MX28_PAD_LCD_DOTCLK__LCD_DOTCLK 0x11e0
167MX28_PAD_LCD_ENABLE__LCD_ENABLE 0x11f0
168MX28_PAD_SSP0_DATA0__SSP0_D0 0x2000
169MX28_PAD_SSP0_DATA1__SSP0_D1 0x2010
170MX28_PAD_SSP0_DATA2__SSP0_D2 0x2020
171MX28_PAD_SSP0_DATA3__SSP0_D3 0x2030
172MX28_PAD_SSP0_DATA4__SSP0_D4 0x2040
173MX28_PAD_SSP0_DATA5__SSP0_D5 0x2050
174MX28_PAD_SSP0_DATA6__SSP0_D6 0x2060
175MX28_PAD_SSP0_DATA7__SSP0_D7 0x2070
176MX28_PAD_SSP0_CMD__SSP0_CMD 0x2080
177MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT 0x2090
178MX28_PAD_SSP0_SCK__SSP0_SCK 0x20a0
179MX28_PAD_SSP1_SCK__SSP1_SCK 0x20c0
180MX28_PAD_SSP1_CMD__SSP1_CMD 0x20d0
181MX28_PAD_SSP1_DATA0__SSP1_D0 0x20e0
182MX28_PAD_SSP1_DATA3__SSP1_D3 0x20f0
183MX28_PAD_SSP2_SCK__SSP2_SCK 0x2100
184MX28_PAD_SSP2_MOSI__SSP2_CMD 0x2110
185MX28_PAD_SSP2_MISO__SSP2_D0 0x2120
186MX28_PAD_SSP2_SS0__SSP2_D3 0x2130
187MX28_PAD_SSP2_SS1__SSP2_D4 0x2140
188MX28_PAD_SSP2_SS2__SSP2_D5 0x2150
189MX28_PAD_SSP3_SCK__SSP3_SCK 0x2180
190MX28_PAD_SSP3_MOSI__SSP3_CMD 0x2190
191MX28_PAD_SSP3_MISO__SSP3_D0 0x21a0
192MX28_PAD_SSP3_SS0__SSP3_D3 0x21b0
193MX28_PAD_AUART0_RX__AUART0_RX 0x3000
194MX28_PAD_AUART0_TX__AUART0_TX 0x3010
195MX28_PAD_AUART0_CTS__AUART0_CTS 0x3020
196MX28_PAD_AUART0_RTS__AUART0_RTS 0x3030
197MX28_PAD_AUART1_RX__AUART1_RX 0x3040
198MX28_PAD_AUART1_TX__AUART1_TX 0x3050
199MX28_PAD_AUART1_CTS__AUART1_CTS 0x3060
200MX28_PAD_AUART1_RTS__AUART1_RTS 0x3070
201MX28_PAD_AUART2_RX__AUART2_RX 0x3080
202MX28_PAD_AUART2_TX__AUART2_TX 0x3090
203MX28_PAD_AUART2_CTS__AUART2_CTS 0x30a0
204MX28_PAD_AUART2_RTS__AUART2_RTS 0x30b0
205MX28_PAD_AUART3_RX__AUART3_RX 0x30c0
206MX28_PAD_AUART3_TX__AUART3_TX 0x30d0
207MX28_PAD_AUART3_CTS__AUART3_CTS 0x30e0
208MX28_PAD_AUART3_RTS__AUART3_RTS 0x30f0
209MX28_PAD_PWM0__PWM_0 0x3100
210MX28_PAD_PWM1__PWM_1 0x3110
211MX28_PAD_PWM2__PWM_2 0x3120
212MX28_PAD_SAIF0_MCLK__SAIF0_MCLK 0x3140
213MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK 0x3150
214MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK 0x3160
215MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 0x3170
216MX28_PAD_I2C0_SCL__I2C0_SCL 0x3180
217MX28_PAD_I2C0_SDA__I2C0_SDA 0x3190
218MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 0x31a0
219MX28_PAD_SPDIF__SPDIF_TX 0x31b0
220MX28_PAD_PWM3__PWM_3 0x31c0
221MX28_PAD_PWM4__PWM_4 0x31d0
222MX28_PAD_LCD_RESET__LCD_RESET 0x31e0
223MX28_PAD_ENET0_MDC__ENET0_MDC 0x4000
224MX28_PAD_ENET0_MDIO__ENET0_MDIO 0x4010
225MX28_PAD_ENET0_RX_EN__ENET0_RX_EN 0x4020
226MX28_PAD_ENET0_RXD0__ENET0_RXD0 0x4030
227MX28_PAD_ENET0_RXD1__ENET0_RXD1 0x4040
228MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK 0x4050
229MX28_PAD_ENET0_TX_EN__ENET0_TX_EN 0x4060
230MX28_PAD_ENET0_TXD0__ENET0_TXD0 0x4070
231MX28_PAD_ENET0_TXD1__ENET0_TXD1 0x4080
232MX28_PAD_ENET0_RXD2__ENET0_RXD2 0x4090
233MX28_PAD_ENET0_RXD3__ENET0_RXD3 0x40a0
234MX28_PAD_ENET0_TXD2__ENET0_TXD2 0x40b0
235MX28_PAD_ENET0_TXD3__ENET0_TXD3 0x40c0
236MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK 0x40d0
237MX28_PAD_ENET0_COL__ENET0_COL 0x40e0
238MX28_PAD_ENET0_CRS__ENET0_CRS 0x40f0
239MX28_PAD_ENET_CLK__CLKCTRL_ENET 0x4100
240MX28_PAD_JTAG_RTCK__JTAG_RTCK 0x4140
241MX28_PAD_EMI_D00__EMI_DATA0 0x5000
242MX28_PAD_EMI_D01__EMI_DATA1 0x5010
243MX28_PAD_EMI_D02__EMI_DATA2 0x5020
244MX28_PAD_EMI_D03__EMI_DATA3 0x5030
245MX28_PAD_EMI_D04__EMI_DATA4 0x5040
246MX28_PAD_EMI_D05__EMI_DATA5 0x5050
247MX28_PAD_EMI_D06__EMI_DATA6 0x5060
248MX28_PAD_EMI_D07__EMI_DATA7 0x5070
249MX28_PAD_EMI_D08__EMI_DATA8 0x5080
250MX28_PAD_EMI_D09__EMI_DATA9 0x5090
251MX28_PAD_EMI_D10__EMI_DATA10 0x50a0
252MX28_PAD_EMI_D11__EMI_DATA11 0x50b0
253MX28_PAD_EMI_D12__EMI_DATA12 0x50c0
254MX28_PAD_EMI_D13__EMI_DATA13 0x50d0
255MX28_PAD_EMI_D14__EMI_DATA14 0x50e0
256MX28_PAD_EMI_D15__EMI_DATA15 0x50f0
257MX28_PAD_EMI_ODT0__EMI_ODT0 0x5100
258MX28_PAD_EMI_DQM0__EMI_DQM0 0x5110
259MX28_PAD_EMI_ODT1__EMI_ODT1 0x5120
260MX28_PAD_EMI_DQM1__EMI_DQM1 0x5130
261MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK 0x5140
262MX28_PAD_EMI_CLK__EMI_CLK 0x5150
263MX28_PAD_EMI_DQS0__EMI_DQS0 0x5160
264MX28_PAD_EMI_DQS1__EMI_DQS1 0x5170
265MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN 0x51a0
266MX28_PAD_EMI_A00__EMI_ADDR0 0x6000
267MX28_PAD_EMI_A01__EMI_ADDR1 0x6010
268MX28_PAD_EMI_A02__EMI_ADDR2 0x6020
269MX28_PAD_EMI_A03__EMI_ADDR3 0x6030
270MX28_PAD_EMI_A04__EMI_ADDR4 0x6040
271MX28_PAD_EMI_A05__EMI_ADDR5 0x6050
272MX28_PAD_EMI_A06__EMI_ADDR6 0x6060
273MX28_PAD_EMI_A07__EMI_ADDR7 0x6070
274MX28_PAD_EMI_A08__EMI_ADDR8 0x6080
275MX28_PAD_EMI_A09__EMI_ADDR9 0x6090
276MX28_PAD_EMI_A10__EMI_ADDR10 0x60a0
277MX28_PAD_EMI_A11__EMI_ADDR11 0x60b0
278MX28_PAD_EMI_A12__EMI_ADDR12 0x60c0
279MX28_PAD_EMI_A13__EMI_ADDR13 0x60d0
280MX28_PAD_EMI_A14__EMI_ADDR14 0x60e0
281MX28_PAD_EMI_BA0__EMI_BA0 0x6100
282MX28_PAD_EMI_BA1__EMI_BA1 0x6110
283MX28_PAD_EMI_BA2__EMI_BA2 0x6120
284MX28_PAD_EMI_CASN__EMI_CASN 0x6130
285MX28_PAD_EMI_RASN__EMI_RASN 0x6140
286MX28_PAD_EMI_WEN__EMI_WEN 0x6150
287MX28_PAD_EMI_CE0N__EMI_CE0N 0x6160
288MX28_PAD_EMI_CE1N__EMI_CE1N 0x6170
289MX28_PAD_EMI_CKE__EMI_CKE 0x6180
290MX28_PAD_GPMI_D00__SSP1_D0 0x0001
291MX28_PAD_GPMI_D01__SSP1_D1 0x0011
292MX28_PAD_GPMI_D02__SSP1_D2 0x0021
293MX28_PAD_GPMI_D03__SSP1_D3 0x0031
294MX28_PAD_GPMI_D04__SSP1_D4 0x0041
295MX28_PAD_GPMI_D05__SSP1_D5 0x0051
296MX28_PAD_GPMI_D06__SSP1_D6 0x0061
297MX28_PAD_GPMI_D07__SSP1_D7 0x0071
298MX28_PAD_GPMI_CE0N__SSP3_D0 0x0101
299MX28_PAD_GPMI_CE1N__SSP3_D3 0x0111
300MX28_PAD_GPMI_CE2N__CAN1_TX 0x0121
301MX28_PAD_GPMI_CE3N__CAN1_RX 0x0131
302MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT 0x0141
303MX28_PAD_GPMI_RDY1__SSP1_CMD 0x0151
304MX28_PAD_GPMI_RDY2__CAN0_TX 0x0161
305MX28_PAD_GPMI_RDY3__CAN0_RX 0x0171
306MX28_PAD_GPMI_RDN__SSP3_SCK 0x0181
307MX28_PAD_GPMI_WRN__SSP1_SCK 0x0191
308MX28_PAD_GPMI_ALE__SSP3_D1 0x01a1
309MX28_PAD_GPMI_CLE__SSP3_D2 0x01b1
310MX28_PAD_GPMI_RESETN__SSP3_CMD 0x01c1
311MX28_PAD_LCD_D03__ETM_DA8 0x1031
312MX28_PAD_LCD_D04__ETM_DA9 0x1041
313MX28_PAD_LCD_D08__ETM_DA3 0x1081
314MX28_PAD_LCD_D09__ETM_DA4 0x1091
315MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT 0x1141
316MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN 0x1151
317MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT 0x1161
318MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN 0x1171
319MX28_PAD_LCD_RD_E__LCD_VSYNC 0x1181
320MX28_PAD_LCD_WR_RWN__LCD_HSYNC 0x1191
321MX28_PAD_LCD_RS__LCD_DOTCLK 0x11a1
322MX28_PAD_LCD_CS__LCD_ENABLE 0x11b1
323MX28_PAD_LCD_VSYNC__SAIF1_SDATA0 0x11c1
324MX28_PAD_LCD_HSYNC__SAIF1_SDATA1 0x11d1
325MX28_PAD_LCD_DOTCLK__SAIF1_MCLK 0x11e1
326MX28_PAD_SSP0_DATA4__SSP2_D0 0x2041
327MX28_PAD_SSP0_DATA5__SSP2_D3 0x2051
328MX28_PAD_SSP0_DATA6__SSP2_CMD 0x2061
329MX28_PAD_SSP0_DATA7__SSP2_SCK 0x2071
330MX28_PAD_SSP1_SCK__SSP2_D1 0x20c1
331MX28_PAD_SSP1_CMD__SSP2_D2 0x20d1
332MX28_PAD_SSP1_DATA0__SSP2_D6 0x20e1
333MX28_PAD_SSP1_DATA3__SSP2_D7 0x20f1
334MX28_PAD_SSP2_SCK__AUART2_RX 0x2101
335MX28_PAD_SSP2_MOSI__AUART2_TX 0x2111
336MX28_PAD_SSP2_MISO__AUART3_RX 0x2121
337MX28_PAD_SSP2_SS0__AUART3_TX 0x2131
338MX28_PAD_SSP2_SS1__SSP2_D1 0x2141
339MX28_PAD_SSP2_SS2__SSP2_D2 0x2151
340MX28_PAD_SSP3_SCK__AUART4_TX 0x2181
341MX28_PAD_SSP3_MOSI__AUART4_RX 0x2191
342MX28_PAD_SSP3_MISO__AUART4_RTS 0x21a1
343MX28_PAD_SSP3_SS0__AUART4_CTS 0x21b1
344MX28_PAD_AUART0_RX__I2C0_SCL 0x3001
345MX28_PAD_AUART0_TX__I2C0_SDA 0x3011
346MX28_PAD_AUART0_CTS__AUART4_RX 0x3021
347MX28_PAD_AUART0_RTS__AUART4_TX 0x3031
348MX28_PAD_AUART1_RX__SSP2_CARD_DETECT 0x3041
349MX28_PAD_AUART1_TX__SSP3_CARD_DETECT 0x3051
350MX28_PAD_AUART1_CTS__USB0_OVERCURRENT 0x3061
351MX28_PAD_AUART1_RTS__USB0_ID 0x3071
352MX28_PAD_AUART2_RX__SSP3_D1 0x3081
353MX28_PAD_AUART2_TX__SSP3_D2 0x3091
354MX28_PAD_AUART2_CTS__I2C1_SCL 0x30a1
355MX28_PAD_AUART2_RTS__I2C1_SDA 0x30b1
356MX28_PAD_AUART3_RX__CAN0_TX 0x30c1
357MX28_PAD_AUART3_TX__CAN0_RX 0x30d1
358MX28_PAD_AUART3_CTS__CAN1_TX 0x30e1
359MX28_PAD_AUART3_RTS__CAN1_RX 0x30f1
360MX28_PAD_PWM0__I2C1_SCL 0x3101
361MX28_PAD_PWM1__I2C1_SDA 0x3111
362MX28_PAD_PWM2__USB0_ID 0x3121
363MX28_PAD_SAIF0_MCLK__PWM_3 0x3141
364MX28_PAD_SAIF0_LRCLK__PWM_4 0x3151
365MX28_PAD_SAIF0_BITCLK__PWM_5 0x3161
366MX28_PAD_SAIF0_SDATA0__PWM_6 0x3171
367MX28_PAD_I2C0_SCL__TIMROT_ROTARYA 0x3181
368MX28_PAD_I2C0_SDA__TIMROT_ROTARYB 0x3191
369MX28_PAD_SAIF1_SDATA0__PWM_7 0x31a1
370MX28_PAD_LCD_RESET__LCD_VSYNC 0x31e1
371MX28_PAD_ENET0_MDC__GPMI_CE4N 0x4001
372MX28_PAD_ENET0_MDIO__GPMI_CE5N 0x4011
373MX28_PAD_ENET0_RX_EN__GPMI_CE6N 0x4021
374MX28_PAD_ENET0_RXD0__GPMI_CE7N 0x4031
375MX28_PAD_ENET0_RXD1__GPMI_READY4 0x4041
376MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER 0x4051
377MX28_PAD_ENET0_TX_EN__GPMI_READY5 0x4061
378MX28_PAD_ENET0_TXD0__GPMI_READY6 0x4071
379MX28_PAD_ENET0_TXD1__GPMI_READY7 0x4081
380MX28_PAD_ENET0_RXD2__ENET1_RXD0 0x4091
381MX28_PAD_ENET0_RXD3__ENET1_RXD1 0x40a1
382MX28_PAD_ENET0_TXD2__ENET1_TXD0 0x40b1
383MX28_PAD_ENET0_TXD3__ENET1_TXD1 0x40c1
384MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER 0x40d1
385MX28_PAD_ENET0_COL__ENET1_TX_EN 0x40e1
386MX28_PAD_ENET0_CRS__ENET1_RX_EN 0x40f1
387MX28_PAD_GPMI_CE2N__ENET0_RX_ER 0x0122
388MX28_PAD_GPMI_CE3N__SAIF1_MCLK 0x0132
389MX28_PAD_GPMI_RDY0__USB0_ID 0x0142
390MX28_PAD_GPMI_RDY2__ENET0_TX_ER 0x0162
391MX28_PAD_GPMI_RDY3__HSADC_TRIGGER 0x0172
392MX28_PAD_GPMI_ALE__SSP3_D4 0x01a2
393MX28_PAD_GPMI_CLE__SSP3_D5 0x01b2
394MX28_PAD_LCD_D00__ETM_DA0 0x1002
395MX28_PAD_LCD_D01__ETM_DA1 0x1012
396MX28_PAD_LCD_D02__ETM_DA2 0x1022
397MX28_PAD_LCD_D03__ETM_DA3 0x1032
398MX28_PAD_LCD_D04__ETM_DA4 0x1042
399MX28_PAD_LCD_D05__ETM_DA5 0x1052
400MX28_PAD_LCD_D06__ETM_DA6 0x1062
401MX28_PAD_LCD_D07__ETM_DA7 0x1072
402MX28_PAD_LCD_D08__ETM_DA8 0x1082
403MX28_PAD_LCD_D09__ETM_DA9 0x1092
404MX28_PAD_LCD_D10__ETM_DA10 0x10a2
405MX28_PAD_LCD_D11__ETM_DA11 0x10b2
406MX28_PAD_LCD_D12__ETM_DA12 0x10c2
407MX28_PAD_LCD_D13__ETM_DA13 0x10d2
408MX28_PAD_LCD_D14__ETM_DA14 0x10e2
409MX28_PAD_LCD_D15__ETM_DA15 0x10f2
410MX28_PAD_LCD_D16__ETM_DA7 0x1102
411MX28_PAD_LCD_D17__ETM_DA6 0x1112
412MX28_PAD_LCD_D18__ETM_DA5 0x1122
413MX28_PAD_LCD_D19__ETM_DA4 0x1132
414MX28_PAD_LCD_D20__ETM_DA3 0x1142
415MX28_PAD_LCD_D21__ETM_DA2 0x1152
416MX28_PAD_LCD_D22__ETM_DA1 0x1162
417MX28_PAD_LCD_D23__ETM_DA0 0x1172
418MX28_PAD_LCD_RD_E__ETM_TCTL 0x1182
419MX28_PAD_LCD_WR_RWN__ETM_TCLK 0x1192
420MX28_PAD_LCD_HSYNC__ETM_TCTL 0x11d2
421MX28_PAD_LCD_DOTCLK__ETM_TCLK 0x11e2
422MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT 0x20c2
423MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN 0x20d2
424MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT 0x20e2
425MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN 0x20f2
426MX28_PAD_SSP2_SCK__SAIF0_SDATA1 0x2102
427MX28_PAD_SSP2_MOSI__SAIF0_SDATA2 0x2112
428MX28_PAD_SSP2_MISO__SAIF1_SDATA1 0x2122
429MX28_PAD_SSP2_SS0__SAIF1_SDATA2 0x2132
430MX28_PAD_SSP2_SS1__USB1_OVERCURRENT 0x2142
431MX28_PAD_SSP2_SS2__USB0_OVERCURRENT 0x2152
432MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT 0x2182
433MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN 0x2192
434MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT 0x21a2
435MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN 0x21b2
436MX28_PAD_AUART0_RX__DUART_CTS 0x3002
437MX28_PAD_AUART0_TX__DUART_RTS 0x3012
438MX28_PAD_AUART0_CTS__DUART_RX 0x3022
439MX28_PAD_AUART0_RTS__DUART_TX 0x3032
440MX28_PAD_AUART1_RX__PWM_0 0x3042
441MX28_PAD_AUART1_TX__PWM_1 0x3052
442MX28_PAD_AUART1_CTS__TIMROT_ROTARYA 0x3062
443MX28_PAD_AUART1_RTS__TIMROT_ROTARYB 0x3072
444MX28_PAD_AUART2_RX__SSP3_D4 0x3082
445MX28_PAD_AUART2_TX__SSP3_D5 0x3092
446MX28_PAD_AUART2_CTS__SAIF1_BITCLK 0x30a2
447MX28_PAD_AUART2_RTS__SAIF1_LRCLK 0x30b2
448MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT 0x30c2
449MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN 0x30d2
450MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT 0x30e2
451MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN 0x30f2
452MX28_PAD_PWM0__DUART_RX 0x3102
453MX28_PAD_PWM1__DUART_TX 0x3112
454MX28_PAD_PWM2__USB1_OVERCURRENT 0x3122
455MX28_PAD_SAIF0_MCLK__AUART4_CTS 0x3142
456MX28_PAD_SAIF0_LRCLK__AUART4_RTS 0x3152
457MX28_PAD_SAIF0_BITCLK__AUART4_RX 0x3162
458MX28_PAD_SAIF0_SDATA0__AUART4_TX 0x3172
459MX28_PAD_I2C0_SCL__DUART_RX 0x3182
460MX28_PAD_I2C0_SDA__DUART_TX 0x3192
461MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1 0x31a2
462MX28_PAD_SPDIF__ENET1_RX_ER 0x31b2
463MX28_PAD_ENET0_MDC__SAIF0_SDATA1 0x4002
464MX28_PAD_ENET0_MDIO__SAIF0_SDATA2 0x4012
465MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1 0x4022
466MX28_PAD_ENET0_RXD0__SAIF1_SDATA2 0x4032
467MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT 0x4052
468MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT 0x4092
469MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN 0x40a2
470MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT 0x40b2
471MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN 0x40c2
472MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN 0x40d2
473MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT 0x40e2
474MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN 0x40f2
475MX28_PAD_GPMI_D00__GPIO_0_0 0x0003
476MX28_PAD_GPMI_D01__GPIO_0_1 0x0013
477MX28_PAD_GPMI_D02__GPIO_0_2 0x0023
478MX28_PAD_GPMI_D03__GPIO_0_3 0x0033
479MX28_PAD_GPMI_D04__GPIO_0_4 0x0043
480MX28_PAD_GPMI_D05__GPIO_0_5 0x0053
481MX28_PAD_GPMI_D06__GPIO_0_6 0x0063
482MX28_PAD_GPMI_D07__GPIO_0_7 0x0073
483MX28_PAD_GPMI_CE0N__GPIO_0_16 0x0103
484MX28_PAD_GPMI_CE1N__GPIO_0_17 0x0113
485MX28_PAD_GPMI_CE2N__GPIO_0_18 0x0123
486MX28_PAD_GPMI_CE3N__GPIO_0_19 0x0133
487MX28_PAD_GPMI_RDY0__GPIO_0_20 0x0143
488MX28_PAD_GPMI_RDY1__GPIO_0_21 0x0153
489MX28_PAD_GPMI_RDY2__GPIO_0_22 0x0163
490MX28_PAD_GPMI_RDY3__GPIO_0_23 0x0173
491MX28_PAD_GPMI_RDN__GPIO_0_24 0x0183
492MX28_PAD_GPMI_WRN__GPIO_0_25 0x0193
493MX28_PAD_GPMI_ALE__GPIO_0_26 0x01a3
494MX28_PAD_GPMI_CLE__GPIO_0_27 0x01b3
495MX28_PAD_GPMI_RESETN__GPIO_0_28 0x01c3
496MX28_PAD_LCD_D00__GPIO_1_0 0x1003
497MX28_PAD_LCD_D01__GPIO_1_1 0x1013
498MX28_PAD_LCD_D02__GPIO_1_2 0x1023
499MX28_PAD_LCD_D03__GPIO_1_3 0x1033
500MX28_PAD_LCD_D04__GPIO_1_4 0x1043
501MX28_PAD_LCD_D05__GPIO_1_5 0x1053
502MX28_PAD_LCD_D06__GPIO_1_6 0x1063
503MX28_PAD_LCD_D07__GPIO_1_7 0x1073
504MX28_PAD_LCD_D08__GPIO_1_8 0x1083
505MX28_PAD_LCD_D09__GPIO_1_9 0x1093
506MX28_PAD_LCD_D10__GPIO_1_10 0x10a3
507MX28_PAD_LCD_D11__GPIO_1_11 0x10b3
508MX28_PAD_LCD_D12__GPIO_1_12 0x10c3
509MX28_PAD_LCD_D13__GPIO_1_13 0x10d3
510MX28_PAD_LCD_D14__GPIO_1_14 0x10e3
511MX28_PAD_LCD_D15__GPIO_1_15 0x10f3
512MX28_PAD_LCD_D16__GPIO_1_16 0x1103
513MX28_PAD_LCD_D17__GPIO_1_17 0x1113
514MX28_PAD_LCD_D18__GPIO_1_18 0x1123
515MX28_PAD_LCD_D19__GPIO_1_19 0x1133
516MX28_PAD_LCD_D20__GPIO_1_20 0x1143
517MX28_PAD_LCD_D21__GPIO_1_21 0x1153
518MX28_PAD_LCD_D22__GPIO_1_22 0x1163
519MX28_PAD_LCD_D23__GPIO_1_23 0x1173
520MX28_PAD_LCD_RD_E__GPIO_1_24 0x1183
521MX28_PAD_LCD_WR_RWN__GPIO_1_25 0x1193
522MX28_PAD_LCD_RS__GPIO_1_26 0x11a3
523MX28_PAD_LCD_CS__GPIO_1_27 0x11b3
524MX28_PAD_LCD_VSYNC__GPIO_1_28 0x11c3
525MX28_PAD_LCD_HSYNC__GPIO_1_29 0x11d3
526MX28_PAD_LCD_DOTCLK__GPIO_1_30 0x11e3
527MX28_PAD_LCD_ENABLE__GPIO_1_31 0x11f3
528MX28_PAD_SSP0_DATA0__GPIO_2_0 0x2003
529MX28_PAD_SSP0_DATA1__GPIO_2_1 0x2013
530MX28_PAD_SSP0_DATA2__GPIO_2_2 0x2023
531MX28_PAD_SSP0_DATA3__GPIO_2_3 0x2033
532MX28_PAD_SSP0_DATA4__GPIO_2_4 0x2043
533MX28_PAD_SSP0_DATA5__GPIO_2_5 0x2053
534MX28_PAD_SSP0_DATA6__GPIO_2_6 0x2063
535MX28_PAD_SSP0_DATA7__GPIO_2_7 0x2073
536MX28_PAD_SSP0_CMD__GPIO_2_8 0x2083
537MX28_PAD_SSP0_DETECT__GPIO_2_9 0x2093
538MX28_PAD_SSP0_SCK__GPIO_2_10 0x20a3
539MX28_PAD_SSP1_SCK__GPIO_2_12 0x20c3
540MX28_PAD_SSP1_CMD__GPIO_2_13 0x20d3
541MX28_PAD_SSP1_DATA0__GPIO_2_14 0x20e3
542MX28_PAD_SSP1_DATA3__GPIO_2_15 0x20f3
543MX28_PAD_SSP2_SCK__GPIO_2_16 0x2103
544MX28_PAD_SSP2_MOSI__GPIO_2_17 0x2113
545MX28_PAD_SSP2_MISO__GPIO_2_18 0x2123
546MX28_PAD_SSP2_SS0__GPIO_2_19 0x2133
547MX28_PAD_SSP2_SS1__GPIO_2_20 0x2143
548MX28_PAD_SSP2_SS2__GPIO_2_21 0x2153
549MX28_PAD_SSP3_SCK__GPIO_2_24 0x2183
550MX28_PAD_SSP3_MOSI__GPIO_2_25 0x2193
551MX28_PAD_SSP3_MISO__GPIO_2_26 0x21a3
552MX28_PAD_SSP3_SS0__GPIO_2_27 0x21b3
553MX28_PAD_AUART0_RX__GPIO_3_0 0x3003
554MX28_PAD_AUART0_TX__GPIO_3_1 0x3013
555MX28_PAD_AUART0_CTS__GPIO_3_2 0x3023
556MX28_PAD_AUART0_RTS__GPIO_3_3 0x3033
557MX28_PAD_AUART1_RX__GPIO_3_4 0x3043
558MX28_PAD_AUART1_TX__GPIO_3_5 0x3053
559MX28_PAD_AUART1_CTS__GPIO_3_6 0x3063
560MX28_PAD_AUART1_RTS__GPIO_3_7 0x3073
561MX28_PAD_AUART2_RX__GPIO_3_8 0x3083
562MX28_PAD_AUART2_TX__GPIO_3_9 0x3093
563MX28_PAD_AUART2_CTS__GPIO_3_10 0x30a3
564MX28_PAD_AUART2_RTS__GPIO_3_11 0x30b3
565MX28_PAD_AUART3_RX__GPIO_3_12 0x30c3
566MX28_PAD_AUART3_TX__GPIO_3_13 0x30d3
567MX28_PAD_AUART3_CTS__GPIO_3_14 0x30e3
568MX28_PAD_AUART3_RTS__GPIO_3_15 0x30f3
569MX28_PAD_PWM0__GPIO_3_16 0x3103
570MX28_PAD_PWM1__GPIO_3_17 0x3113
571MX28_PAD_PWM2__GPIO_3_18 0x3123
572MX28_PAD_SAIF0_MCLK__GPIO_3_20 0x3143
573MX28_PAD_SAIF0_LRCLK__GPIO_3_21 0x3153
574MX28_PAD_SAIF0_BITCLK__GPIO_3_22 0x3163
575MX28_PAD_SAIF0_SDATA0__GPIO_3_23 0x3173
576MX28_PAD_I2C0_SCL__GPIO_3_24 0x3183
577MX28_PAD_I2C0_SDA__GPIO_3_25 0x3193
578MX28_PAD_SAIF1_SDATA0__GPIO_3_26 0x31a3
579MX28_PAD_SPDIF__GPIO_3_27 0x31b3
580MX28_PAD_PWM3__GPIO_3_28 0x31c3
581MX28_PAD_PWM4__GPIO_3_29 0x31d3
582MX28_PAD_LCD_RESET__GPIO_3_30 0x31e3
583MX28_PAD_ENET0_MDC__GPIO_4_0 0x4003
584MX28_PAD_ENET0_MDIO__GPIO_4_1 0x4013
585MX28_PAD_ENET0_RX_EN__GPIO_4_2 0x4023
586MX28_PAD_ENET0_RXD0__GPIO_4_3 0x4033
587MX28_PAD_ENET0_RXD1__GPIO_4_4 0x4043
588MX28_PAD_ENET0_TX_CLK__GPIO_4_5 0x4053
589MX28_PAD_ENET0_TX_EN__GPIO_4_6 0x4063
590MX28_PAD_ENET0_TXD0__GPIO_4_7 0x4073
591MX28_PAD_ENET0_TXD1__GPIO_4_8 0x4083
592MX28_PAD_ENET0_RXD2__GPIO_4_9 0x4093
593MX28_PAD_ENET0_RXD3__GPIO_4_10 0x40a3
594MX28_PAD_ENET0_TXD2__GPIO_4_11 0x40b3
595MX28_PAD_ENET0_TXD3__GPIO_4_12 0x40c3
596MX28_PAD_ENET0_RX_CLK__GPIO_4_13 0x40d3
597MX28_PAD_ENET0_COL__GPIO_4_14 0x40e3
598MX28_PAD_ENET0_CRS__GPIO_4_15 0x40f3
599MX28_PAD_ENET_CLK__GPIO_4_16 0x4103
600MX28_PAD_JTAG_RTCK__GPIO_4_20 0x4143
601
602Valid values for i.MX23 pinmux-id:
603
604pinmux id
605------ --
606MX23_PAD_GPMI_D00__GPMI_D00 0x0000
607MX23_PAD_GPMI_D01__GPMI_D01 0x0010
608MX23_PAD_GPMI_D02__GPMI_D02 0x0020
609MX23_PAD_GPMI_D03__GPMI_D03 0x0030
610MX23_PAD_GPMI_D04__GPMI_D04 0x0040
611MX23_PAD_GPMI_D05__GPMI_D05 0x0050
612MX23_PAD_GPMI_D06__GPMI_D06 0x0060
613MX23_PAD_GPMI_D07__GPMI_D07 0x0070
614MX23_PAD_GPMI_D08__GPMI_D08 0x0080
615MX23_PAD_GPMI_D09__GPMI_D09 0x0090
616MX23_PAD_GPMI_D10__GPMI_D10 0x00a0
617MX23_PAD_GPMI_D11__GPMI_D11 0x00b0
618MX23_PAD_GPMI_D12__GPMI_D12 0x00c0
619MX23_PAD_GPMI_D13__GPMI_D13 0x00d0
620MX23_PAD_GPMI_D14__GPMI_D14 0x00e0
621MX23_PAD_GPMI_D15__GPMI_D15 0x00f0
622MX23_PAD_GPMI_CLE__GPMI_CLE 0x0100
623MX23_PAD_GPMI_ALE__GPMI_ALE 0x0110
624MX23_PAD_GPMI_CE2N__GPMI_CE2N 0x0120
625MX23_PAD_GPMI_RDY0__GPMI_RDY0 0x0130
626MX23_PAD_GPMI_RDY1__GPMI_RDY1 0x0140
627MX23_PAD_GPMI_RDY2__GPMI_RDY2 0x0150
628MX23_PAD_GPMI_RDY3__GPMI_RDY3 0x0160
629MX23_PAD_GPMI_WPN__GPMI_WPN 0x0170
630MX23_PAD_GPMI_WRN__GPMI_WRN 0x0180
631MX23_PAD_GPMI_RDN__GPMI_RDN 0x0190
632MX23_PAD_AUART1_CTS__AUART1_CTS 0x01a0
633MX23_PAD_AUART1_RTS__AUART1_RTS 0x01b0
634MX23_PAD_AUART1_RX__AUART1_RX 0x01c0
635MX23_PAD_AUART1_TX__AUART1_TX 0x01d0
636MX23_PAD_I2C_SCL__I2C_SCL 0x01e0
637MX23_PAD_I2C_SDA__I2C_SDA 0x01f0
638MX23_PAD_LCD_D00__LCD_D00 0x1000
639MX23_PAD_LCD_D01__LCD_D01 0x1010
640MX23_PAD_LCD_D02__LCD_D02 0x1020
641MX23_PAD_LCD_D03__LCD_D03 0x1030
642MX23_PAD_LCD_D04__LCD_D04 0x1040
643MX23_PAD_LCD_D05__LCD_D05 0x1050
644MX23_PAD_LCD_D06__LCD_D06 0x1060
645MX23_PAD_LCD_D07__LCD_D07 0x1070
646MX23_PAD_LCD_D08__LCD_D08 0x1080
647MX23_PAD_LCD_D09__LCD_D09 0x1090
648MX23_PAD_LCD_D10__LCD_D10 0x10a0
649MX23_PAD_LCD_D11__LCD_D11 0x10b0
650MX23_PAD_LCD_D12__LCD_D12 0x10c0
651MX23_PAD_LCD_D13__LCD_D13 0x10d0
652MX23_PAD_LCD_D14__LCD_D14 0x10e0
653MX23_PAD_LCD_D15__LCD_D15 0x10f0
654MX23_PAD_LCD_D16__LCD_D16 0x1100
655MX23_PAD_LCD_D17__LCD_D17 0x1110
656MX23_PAD_LCD_RESET__LCD_RESET 0x1120
657MX23_PAD_LCD_RS__LCD_RS 0x1130
658MX23_PAD_LCD_WR__LCD_WR 0x1140
659MX23_PAD_LCD_CS__LCD_CS 0x1150
660MX23_PAD_LCD_DOTCK__LCD_DOTCK 0x1160
661MX23_PAD_LCD_ENABLE__LCD_ENABLE 0x1170
662MX23_PAD_LCD_HSYNC__LCD_HSYNC 0x1180
663MX23_PAD_LCD_VSYNC__LCD_VSYNC 0x1190
664MX23_PAD_PWM0__PWM0 0x11a0
665MX23_PAD_PWM1__PWM1 0x11b0
666MX23_PAD_PWM2__PWM2 0x11c0
667MX23_PAD_PWM3__PWM3 0x11d0
668MX23_PAD_PWM4__PWM4 0x11e0
669MX23_PAD_SSP1_CMD__SSP1_CMD 0x2000
670MX23_PAD_SSP1_DETECT__SSP1_DETECT 0x2010
671MX23_PAD_SSP1_DATA0__SSP1_DATA0 0x2020
672MX23_PAD_SSP1_DATA1__SSP1_DATA1 0x2030
673MX23_PAD_SSP1_DATA2__SSP1_DATA2 0x2040
674MX23_PAD_SSP1_DATA3__SSP1_DATA3 0x2050
675MX23_PAD_SSP1_SCK__SSP1_SCK 0x2060
676MX23_PAD_ROTARYA__ROTARYA 0x2070
677MX23_PAD_ROTARYB__ROTARYB 0x2080
678MX23_PAD_EMI_A00__EMI_A00 0x2090
679MX23_PAD_EMI_A01__EMI_A01 0x20a0
680MX23_PAD_EMI_A02__EMI_A02 0x20b0
681MX23_PAD_EMI_A03__EMI_A03 0x20c0
682MX23_PAD_EMI_A04__EMI_A04 0x20d0
683MX23_PAD_EMI_A05__EMI_A05 0x20e0
684MX23_PAD_EMI_A06__EMI_A06 0x20f0
685MX23_PAD_EMI_A07__EMI_A07 0x2100
686MX23_PAD_EMI_A08__EMI_A08 0x2110
687MX23_PAD_EMI_A09__EMI_A09 0x2120
688MX23_PAD_EMI_A10__EMI_A10 0x2130
689MX23_PAD_EMI_A11__EMI_A11 0x2140
690MX23_PAD_EMI_A12__EMI_A12 0x2150
691MX23_PAD_EMI_BA0__EMI_BA0 0x2160
692MX23_PAD_EMI_BA1__EMI_BA1 0x2170
693MX23_PAD_EMI_CASN__EMI_CASN 0x2180
694MX23_PAD_EMI_CE0N__EMI_CE0N 0x2190
695MX23_PAD_EMI_CE1N__EMI_CE1N 0x21a0
696MX23_PAD_GPMI_CE1N__GPMI_CE1N 0x21b0
697MX23_PAD_GPMI_CE0N__GPMI_CE0N 0x21c0
698MX23_PAD_EMI_CKE__EMI_CKE 0x21d0
699MX23_PAD_EMI_RASN__EMI_RASN 0x21e0
700MX23_PAD_EMI_WEN__EMI_WEN 0x21f0
701MX23_PAD_EMI_D00__EMI_D00 0x3000
702MX23_PAD_EMI_D01__EMI_D01 0x3010
703MX23_PAD_EMI_D02__EMI_D02 0x3020
704MX23_PAD_EMI_D03__EMI_D03 0x3030
705MX23_PAD_EMI_D04__EMI_D04 0x3040
706MX23_PAD_EMI_D05__EMI_D05 0x3050
707MX23_PAD_EMI_D06__EMI_D06 0x3060
708MX23_PAD_EMI_D07__EMI_D07 0x3070
709MX23_PAD_EMI_D08__EMI_D08 0x3080
710MX23_PAD_EMI_D09__EMI_D09 0x3090
711MX23_PAD_EMI_D10__EMI_D10 0x30a0
712MX23_PAD_EMI_D11__EMI_D11 0x30b0
713MX23_PAD_EMI_D12__EMI_D12 0x30c0
714MX23_PAD_EMI_D13__EMI_D13 0x30d0
715MX23_PAD_EMI_D14__EMI_D14 0x30e0
716MX23_PAD_EMI_D15__EMI_D15 0x30f0
717MX23_PAD_EMI_DQM0__EMI_DQM0 0x3100
718MX23_PAD_EMI_DQM1__EMI_DQM1 0x3110
719MX23_PAD_EMI_DQS0__EMI_DQS0 0x3120
720MX23_PAD_EMI_DQS1__EMI_DQS1 0x3130
721MX23_PAD_EMI_CLK__EMI_CLK 0x3140
722MX23_PAD_EMI_CLKN__EMI_CLKN 0x3150
723MX23_PAD_GPMI_D00__LCD_D8 0x0001
724MX23_PAD_GPMI_D01__LCD_D9 0x0011
725MX23_PAD_GPMI_D02__LCD_D10 0x0021
726MX23_PAD_GPMI_D03__LCD_D11 0x0031
727MX23_PAD_GPMI_D04__LCD_D12 0x0041
728MX23_PAD_GPMI_D05__LCD_D13 0x0051
729MX23_PAD_GPMI_D06__LCD_D14 0x0061
730MX23_PAD_GPMI_D07__LCD_D15 0x0071
731MX23_PAD_GPMI_D08__LCD_D18 0x0081
732MX23_PAD_GPMI_D09__LCD_D19 0x0091
733MX23_PAD_GPMI_D10__LCD_D20 0x00a1
734MX23_PAD_GPMI_D11__LCD_D21 0x00b1
735MX23_PAD_GPMI_D12__LCD_D22 0x00c1
736MX23_PAD_GPMI_D13__LCD_D23 0x00d1
737MX23_PAD_GPMI_D14__AUART2_RX 0x00e1
738MX23_PAD_GPMI_D15__AUART2_TX 0x00f1
739MX23_PAD_GPMI_CLE__LCD_D16 0x0101
740MX23_PAD_GPMI_ALE__LCD_D17 0x0111
741MX23_PAD_GPMI_CE2N__ATA_A2 0x0121
742MX23_PAD_AUART1_RTS__IR_CLK 0x01b1
743MX23_PAD_AUART1_RX__IR_RX 0x01c1
744MX23_PAD_AUART1_TX__IR_TX 0x01d1
745MX23_PAD_I2C_SCL__GPMI_RDY2 0x01e1
746MX23_PAD_I2C_SDA__GPMI_CE2N 0x01f1
747MX23_PAD_LCD_D00__ETM_DA8 0x1001
748MX23_PAD_LCD_D01__ETM_DA9 0x1011
749MX23_PAD_LCD_D02__ETM_DA10 0x1021
750MX23_PAD_LCD_D03__ETM_DA11 0x1031
751MX23_PAD_LCD_D04__ETM_DA12 0x1041
752MX23_PAD_LCD_D05__ETM_DA13 0x1051
753MX23_PAD_LCD_D06__ETM_DA14 0x1061
754MX23_PAD_LCD_D07__ETM_DA15 0x1071
755MX23_PAD_LCD_D08__ETM_DA0 0x1081
756MX23_PAD_LCD_D09__ETM_DA1 0x1091
757MX23_PAD_LCD_D10__ETM_DA2 0x10a1
758MX23_PAD_LCD_D11__ETM_DA3 0x10b1
759MX23_PAD_LCD_D12__ETM_DA4 0x10c1
760MX23_PAD_LCD_D13__ETM_DA5 0x10d1
761MX23_PAD_LCD_D14__ETM_DA6 0x10e1
762MX23_PAD_LCD_D15__ETM_DA7 0x10f1
763MX23_PAD_LCD_RESET__ETM_TCTL 0x1121
764MX23_PAD_LCD_RS__ETM_TCLK 0x1131
765MX23_PAD_LCD_DOTCK__GPMI_RDY3 0x1161
766MX23_PAD_LCD_ENABLE__I2C_SCL 0x1171
767MX23_PAD_LCD_HSYNC__I2C_SDA 0x1181
768MX23_PAD_LCD_VSYNC__LCD_BUSY 0x1191
769MX23_PAD_PWM0__ROTARYA 0x11a1
770MX23_PAD_PWM1__ROTARYB 0x11b1
771MX23_PAD_PWM2__GPMI_RDY3 0x11c1
772MX23_PAD_PWM3__ETM_TCTL 0x11d1
773MX23_PAD_PWM4__ETM_TCLK 0x11e1
774MX23_PAD_SSP1_DETECT__GPMI_CE3N 0x2011
775MX23_PAD_SSP1_DATA1__I2C_SCL 0x2031
776MX23_PAD_SSP1_DATA2__I2C_SDA 0x2041
777MX23_PAD_ROTARYA__AUART2_RTS 0x2071
778MX23_PAD_ROTARYB__AUART2_CTS 0x2081
779MX23_PAD_GPMI_D00__SSP2_DATA0 0x0002
780MX23_PAD_GPMI_D01__SSP2_DATA1 0x0012
781MX23_PAD_GPMI_D02__SSP2_DATA2 0x0022
782MX23_PAD_GPMI_D03__SSP2_DATA3 0x0032
783MX23_PAD_GPMI_D04__SSP2_DATA4 0x0042
784MX23_PAD_GPMI_D05__SSP2_DATA5 0x0052
785MX23_PAD_GPMI_D06__SSP2_DATA6 0x0062
786MX23_PAD_GPMI_D07__SSP2_DATA7 0x0072
787MX23_PAD_GPMI_D08__SSP1_DATA4 0x0082
788MX23_PAD_GPMI_D09__SSP1_DATA5 0x0092
789MX23_PAD_GPMI_D10__SSP1_DATA6 0x00a2
790MX23_PAD_GPMI_D11__SSP1_DATA7 0x00b2
791MX23_PAD_GPMI_D15__GPMI_CE3N 0x00f2
792MX23_PAD_GPMI_RDY0__SSP2_DETECT 0x0132
793MX23_PAD_GPMI_RDY1__SSP2_CMD 0x0142
794MX23_PAD_GPMI_WRN__SSP2_SCK 0x0182
795MX23_PAD_AUART1_CTS__SSP1_DATA4 0x01a2
796MX23_PAD_AUART1_RTS__SSP1_DATA5 0x01b2
797MX23_PAD_AUART1_RX__SSP1_DATA6 0x01c2
798MX23_PAD_AUART1_TX__SSP1_DATA7 0x01d2
799MX23_PAD_I2C_SCL__AUART1_TX 0x01e2
800MX23_PAD_I2C_SDA__AUART1_RX 0x01f2
801MX23_PAD_LCD_D08__SAIF2_SDATA0 0x1082
802MX23_PAD_LCD_D09__SAIF1_SDATA0 0x1092
803MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK 0x10a2
804MX23_PAD_LCD_D11__SAIF_LRCLK 0x10b2
805MX23_PAD_LCD_D12__SAIF2_SDATA1 0x10c2
806MX23_PAD_LCD_D13__SAIF2_SDATA2 0x10d2
807MX23_PAD_LCD_D14__SAIF1_SDATA2 0x10e2
808MX23_PAD_LCD_D15__SAIF1_SDATA1 0x10f2
809MX23_PAD_LCD_D16__SAIF_ALT_BITCLK 0x1102
810MX23_PAD_LCD_RESET__GPMI_CE3N 0x1122
811MX23_PAD_PWM0__DUART_RX 0x11a2
812MX23_PAD_PWM1__DUART_TX 0x11b2
813MX23_PAD_PWM3__AUART1_CTS 0x11d2
814MX23_PAD_PWM4__AUART1_RTS 0x11e2
815MX23_PAD_SSP1_CMD__JTAG_TDO 0x2002
816MX23_PAD_SSP1_DETECT__USB_OTG_ID 0x2012
817MX23_PAD_SSP1_DATA0__JTAG_TDI 0x2022
818MX23_PAD_SSP1_DATA1__JTAG_TCLK 0x2032
819MX23_PAD_SSP1_DATA2__JTAG_RTCK 0x2042
820MX23_PAD_SSP1_DATA3__JTAG_TMS 0x2052
821MX23_PAD_SSP1_SCK__JTAG_TRST 0x2062
822MX23_PAD_ROTARYA__SPDIF 0x2072
823MX23_PAD_ROTARYB__GPMI_CE3N 0x2082
824MX23_PAD_GPMI_D00__GPIO_0_0 0x0003
825MX23_PAD_GPMI_D01__GPIO_0_1 0x0013
826MX23_PAD_GPMI_D02__GPIO_0_2 0x0023
827MX23_PAD_GPMI_D03__GPIO_0_3 0x0033
828MX23_PAD_GPMI_D04__GPIO_0_4 0x0043
829MX23_PAD_GPMI_D05__GPIO_0_5 0x0053
830MX23_PAD_GPMI_D06__GPIO_0_6 0x0063
831MX23_PAD_GPMI_D07__GPIO_0_7 0x0073
832MX23_PAD_GPMI_D08__GPIO_0_8 0x0083
833MX23_PAD_GPMI_D09__GPIO_0_9 0x0093
834MX23_PAD_GPMI_D10__GPIO_0_10 0x00a3
835MX23_PAD_GPMI_D11__GPIO_0_11 0x00b3
836MX23_PAD_GPMI_D12__GPIO_0_12 0x00c3
837MX23_PAD_GPMI_D13__GPIO_0_13 0x00d3
838MX23_PAD_GPMI_D14__GPIO_0_14 0x00e3
839MX23_PAD_GPMI_D15__GPIO_0_15 0x00f3
840MX23_PAD_GPMI_CLE__GPIO_0_16 0x0103
841MX23_PAD_GPMI_ALE__GPIO_0_17 0x0113
842MX23_PAD_GPMI_CE2N__GPIO_0_18 0x0123
843MX23_PAD_GPMI_RDY0__GPIO_0_19 0x0133
844MX23_PAD_GPMI_RDY1__GPIO_0_20 0x0143
845MX23_PAD_GPMI_RDY2__GPIO_0_21 0x0153
846MX23_PAD_GPMI_RDY3__GPIO_0_22 0x0163
847MX23_PAD_GPMI_WPN__GPIO_0_23 0x0173
848MX23_PAD_GPMI_WRN__GPIO_0_24 0x0183
849MX23_PAD_GPMI_RDN__GPIO_0_25 0x0193
850MX23_PAD_AUART1_CTS__GPIO_0_26 0x01a3
851MX23_PAD_AUART1_RTS__GPIO_0_27 0x01b3
852MX23_PAD_AUART1_RX__GPIO_0_28 0x01c3
853MX23_PAD_AUART1_TX__GPIO_0_29 0x01d3
854MX23_PAD_I2C_SCL__GPIO_0_30 0x01e3
855MX23_PAD_I2C_SDA__GPIO_0_31 0x01f3
856MX23_PAD_LCD_D00__GPIO_1_0 0x1003
857MX23_PAD_LCD_D01__GPIO_1_1 0x1013
858MX23_PAD_LCD_D02__GPIO_1_2 0x1023
859MX23_PAD_LCD_D03__GPIO_1_3 0x1033
860MX23_PAD_LCD_D04__GPIO_1_4 0x1043
861MX23_PAD_LCD_D05__GPIO_1_5 0x1053
862MX23_PAD_LCD_D06__GPIO_1_6 0x1063
863MX23_PAD_LCD_D07__GPIO_1_7 0x1073
864MX23_PAD_LCD_D08__GPIO_1_8 0x1083
865MX23_PAD_LCD_D09__GPIO_1_9 0x1093
866MX23_PAD_LCD_D10__GPIO_1_10 0x10a3
867MX23_PAD_LCD_D11__GPIO_1_11 0x10b3
868MX23_PAD_LCD_D12__GPIO_1_12 0x10c3
869MX23_PAD_LCD_D13__GPIO_1_13 0x10d3
870MX23_PAD_LCD_D14__GPIO_1_14 0x10e3
871MX23_PAD_LCD_D15__GPIO_1_15 0x10f3
872MX23_PAD_LCD_D16__GPIO_1_16 0x1103
873MX23_PAD_LCD_D17__GPIO_1_17 0x1113
874MX23_PAD_LCD_RESET__GPIO_1_18 0x1123
875MX23_PAD_LCD_RS__GPIO_1_19 0x1133
876MX23_PAD_LCD_WR__GPIO_1_20 0x1143
877MX23_PAD_LCD_CS__GPIO_1_21 0x1153
878MX23_PAD_LCD_DOTCK__GPIO_1_22 0x1163
879MX23_PAD_LCD_ENABLE__GPIO_1_23 0x1173
880MX23_PAD_LCD_HSYNC__GPIO_1_24 0x1183
881MX23_PAD_LCD_VSYNC__GPIO_1_25 0x1193
882MX23_PAD_PWM0__GPIO_1_26 0x11a3
883MX23_PAD_PWM1__GPIO_1_27 0x11b3
884MX23_PAD_PWM2__GPIO_1_28 0x11c3
885MX23_PAD_PWM3__GPIO_1_29 0x11d3
886MX23_PAD_PWM4__GPIO_1_30 0x11e3
887MX23_PAD_SSP1_CMD__GPIO_2_0 0x2003
888MX23_PAD_SSP1_DETECT__GPIO_2_1 0x2013
889MX23_PAD_SSP1_DATA0__GPIO_2_2 0x2023
890MX23_PAD_SSP1_DATA1__GPIO_2_3 0x2033
891MX23_PAD_SSP1_DATA2__GPIO_2_4 0x2043
892MX23_PAD_SSP1_DATA3__GPIO_2_5 0x2053
893MX23_PAD_SSP1_SCK__GPIO_2_6 0x2063
894MX23_PAD_ROTARYA__GPIO_2_7 0x2073
895MX23_PAD_ROTARYB__GPIO_2_8 0x2083
896MX23_PAD_EMI_A00__GPIO_2_9 0x2093
897MX23_PAD_EMI_A01__GPIO_2_10 0x20a3
898MX23_PAD_EMI_A02__GPIO_2_11 0x20b3
899MX23_PAD_EMI_A03__GPIO_2_12 0x20c3
900MX23_PAD_EMI_A04__GPIO_2_13 0x20d3
901MX23_PAD_EMI_A05__GPIO_2_14 0x20e3
902MX23_PAD_EMI_A06__GPIO_2_15 0x20f3
903MX23_PAD_EMI_A07__GPIO_2_16 0x2103
904MX23_PAD_EMI_A08__GPIO_2_17 0x2113
905MX23_PAD_EMI_A09__GPIO_2_18 0x2123
906MX23_PAD_EMI_A10__GPIO_2_19 0x2133
907MX23_PAD_EMI_A11__GPIO_2_20 0x2143
908MX23_PAD_EMI_A12__GPIO_2_21 0x2153
909MX23_PAD_EMI_BA0__GPIO_2_22 0x2163
910MX23_PAD_EMI_BA1__GPIO_2_23 0x2173
911MX23_PAD_EMI_CASN__GPIO_2_24 0x2183
912MX23_PAD_EMI_CE0N__GPIO_2_25 0x2193
913MX23_PAD_EMI_CE1N__GPIO_2_26 0x21a3
914MX23_PAD_GPMI_CE1N__GPIO_2_27 0x21b3
915MX23_PAD_GPMI_CE0N__GPIO_2_28 0x21c3
916MX23_PAD_EMI_CKE__GPIO_2_29 0x21d3
917MX23_PAD_EMI_RASN__GPIO_2_30 0x21e3
918MX23_PAD_EMI_WEN__GPIO_2_31 0x21f3
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt
new file mode 100644
index 00000000000..c8e578263ce
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt
@@ -0,0 +1,132 @@
1NVIDIA Tegra20 pinmux controller
2
3Required properties:
4- compatible: "nvidia,tegra20-pinmux"
5- reg: Should contain the register physical address and length for each of
6 the tri-state, mux, pull-up/down, and pad control register sets.
7
8Please refer to pinctrl-bindings.txt in this directory for details of the
9common pinctrl bindings used by client devices, including the meaning of the
10phrase "pin configuration node".
11
12Tegra's pin configuration nodes act as a container for an abitrary number of
13subnodes. Each of these subnodes represents some desired configuration for a
14pin, a group, or a list of pins or groups. This configuration can include the
15mux function to select on those pin(s)/group(s), and various pin configuration
16parameters, such as pull-up, tristate, drive strength, etc.
17
18The name of each subnode is not important; all subnodes should be enumerated
19and processed purely based on their content.
20
21Each subnode only affects those parameters that are explicitly listed. In
22other words, a subnode that lists a mux function but no pin configuration
23parameters implies no information about any pin configuration parameters.
24Similarly, a pin subnode that describes a pullup parameter implies no
25information about e.g. the mux function or tristate parameter. For this
26reason, even seemingly boolean values are actually tristates in this binding:
27unspecified, off, or on. Unspecified is represented as an absent property,
28and off/on are represented as integer values 0 and 1.
29
30Required subnode-properties:
31- nvidia,pins : An array of strings. Each string contains the name of a pin or
32 group. Valid values for these names are listed below.
33
34Optional subnode-properties:
35- nvidia,function: A string containing the name of the function to mux to the
36 pin or group. Valid values for function names are listed below. See the Tegra
37 TRM to determine which are valid for each pin or group.
38- nvidia,pull: Integer, representing the pull-down/up to apply to the pin.
39 0: none, 1: down, 2: up.
40- nvidia,tristate: Integer.
41 0: drive, 1: tristate.
42- nvidia,high-speed-mode: Integer. Enable high speed mode the pins.
43 0: no, 1: yes.
44- nvidia,schmitt: Integer. Enables Schmitt Trigger on the input.
45 0: no, 1: yes.
46- nvidia,low-power-mode: Integer. Valid values 0-3. 0 is least power, 3 is
47 most power. Controls the drive power or current. See "Low Power Mode"
48 or "LPMD1" and "LPMD0" in the Tegra TRM.
49- nvidia,pull-down-strength: Integer. Controls drive strength. 0 is weakest.
50 The range of valid values depends on the pingroup. See "CAL_DRVDN" in the
51 Tegra TRM.
52- nvidia,pull-up-strength: Integer. Controls drive strength. 0 is weakest.
53 The range of valid values depends on the pingroup. See "CAL_DRVUP" in the
54 Tegra TRM.
55- nvidia,slew-rate-rising: Integer. Controls rising signal slew rate. 0 is
56 fastest. The range of valid values depends on the pingroup. See
57 "DRVDN_SLWR" in the Tegra TRM.
58- nvidia,slew-rate-falling: Integer. Controls falling signal slew rate. 0 is
59 fastest. The range of valid values depends on the pingroup. See
60 "DRVUP_SLWF" in the Tegra TRM.
61
62Note that many of these properties are only valid for certain specific pins
63or groups. See the Tegra TRM and various pinmux spreadsheets for complete
64details regarding which groups support which functionality. The Linux pinctrl
65driver may also be a useful reference, since it consolidates, disambiguates,
66and corrects data from all those sources.
67
68Valid values for pin and group names are:
69
70 mux groups:
71
72 These all support nvidia,function, nvidia,tristate, and many support
73 nvidia,pull.
74
75 ata, atb, atc, atd, ate, cdev1, cdev2, crtp, csus, dap1, dap2, dap3, dap4,
76 ddc, dta, dtb, dtc, dtd, dte, dtf, gma, gmb, gmc, gmd, gme, gpu, gpu7,
77 gpv, hdint, i2cp, irrx, irtx, kbca, kbcb, kbcc, kbcd, kbce, kbcf, lcsn,
78 ld0, ld1, ld2, ld3, ld4, ld5, ld6, ld7, ld8, ld9, ld10, ld11, ld12, ld13,
79 ld14, ld15, ld16, ld17, ldc, ldi, lhp0, lhp1, lhp2, lhs, lm0, lm1, lpp,
80 lpw0, lpw1, lpw2, lsc0, lsc1, lsck, lsda, lsdi, lspi, lvp0, lvp1, lvs,
81 owc, pmc, pta, rm, sdb, sdc, sdd, sdio1, slxa, slxc, slxd, slxk, spdi,
82 spdo, spia, spib, spic, spid, spie, spif, spig, spih, uaa, uab, uac, uad,
83 uca, ucb, uda.
84
85 tristate groups:
86
87 These only support nvidia,pull.
88
89 ck32, ddrc, pmca, pmcb, pmcc, pmcd, pmce, xm2c, xm2d, ls, lc, ld17_0,
90 ld19_18, ld21_20, ld23_22.
91
92 drive groups:
93
94 With some exceptions, these support nvidia,high-speed-mode,
95 nvidia,schmitt, nvidia,low-power-mode, nvidia,pull-down-strength,
96 nvidia,pull-up-strength, nvidia,slew_rate-rising, nvidia,slew_rate-falling.
97
98 drive_ao1, drive_ao2, drive_at1, drive_at2, drive_cdev1, drive_cdev2,
99 drive_csus, drive_dap1, drive_dap2, drive_dap3, drive_dap4, drive_dbg,
100 drive_lcd1, drive_lcd2, drive_sdmmc2, drive_sdmmc3, drive_spi, drive_uaa,
101 drive_uab, drive_uart2, drive_uart3, drive_vi1, drive_vi2, drive_xm2a,
102 drive_xm2c, drive_xm2d, drive_xm2clk, drive_sdio1, drive_crt, drive_ddc,
103 drive_gma, drive_gmb, drive_gmc, drive_gmd, drive_gme, drive_owr,
104 drive_uda.
105
106Example:
107
108 pinctrl@70000000 {
109 compatible = "nvidia,tegra20-pinmux";
110 reg = < 0x70000014 0x10 /* Tri-state registers */
111 0x70000080 0x20 /* Mux registers */
112 0x700000a0 0x14 /* Pull-up/down registers */
113 0x70000868 0xa8 >; /* Pad control registers */
114 };
115
116Example board file extract:
117
118 pinctrl@70000000 {
119 sdio4_default: sdio4_default {
120 atb {
121 nvidia,pins = "atb", "gma", "gme";
122 nvidia,function = "sdio4";
123 nvidia,pull = <0>;
124 nvidia,tristate = <0>;
125 };
126 };
127 };
128
129 sdhci@c8000600 {
130 pinctrl-names = "default";
131 pinctrl-0 = <&sdio4_default>;
132 };
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt
new file mode 100644
index 00000000000..c275b70349c
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt
@@ -0,0 +1,132 @@
1NVIDIA Tegra30 pinmux controller
2
3The Tegra30 pinctrl binding is very similar to the Tegra20 pinctrl binding,
4as described in nvidia,tegra20-pinmux.txt. In fact, this document assumes
5that binding as a baseline, and only documents the differences between the
6two bindings.
7
8Required properties:
9- compatible: "nvidia,tegra30-pinmux"
10- reg: Should contain the register physical address and length for each of
11 the pad control and mux registers.
12
13Tegra30 adds the following optional properties for pin configuration subnodes:
14- nvidia,enable-input: Integer. Enable the pin's input path. 0: no, 1: yes.
15- nvidia,open-drain: Integer. Enable open drain mode. 0: no, 1: yes.
16- nvidia,lock: Integer. Lock the pin configuration against further changes
17 until reset. 0: no, 1: yes.
18- nvidia,io-reset: Integer. Reset the IO path. 0: no, 1: yes.
19
20As with Tegra20, see the Tegra TRM for complete details regarding which groups
21support which functionality.
22
23Valid values for pin and group names are:
24
25 per-pin mux groups:
26
27 These all support nvidia,function, nvidia,tristate, nvidia,pull,
28 nvidia,enable-input, nvidia,lock. Some support nvidia,open-drain,
29 nvidia,io-reset.
30
31 clk_32k_out_pa0, uart3_cts_n_pa1, dap2_fs_pa2, dap2_sclk_pa3,
32 dap2_din_pa4, dap2_dout_pa5, sdmmc3_clk_pa6, sdmmc3_cmd_pa7, gmi_a17_pb0,
33 gmi_a18_pb1, lcd_pwr0_pb2, lcd_pclk_pb3, sdmmc3_dat3_pb4, sdmmc3_dat2_pb5,
34 sdmmc3_dat1_pb6, sdmmc3_dat0_pb7, uart3_rts_n_pc0, lcd_pwr1_pc1,
35 uart2_txd_pc2, uart2_rxd_pc3, gen1_i2c_scl_pc4, gen1_i2c_sda_pc5,
36 lcd_pwr2_pc6, gmi_wp_n_pc7, sdmmc3_dat5_pd0, sdmmc3_dat4_pd1, lcd_dc1_pd2,
37 sdmmc3_dat6_pd3, sdmmc3_dat7_pd4, vi_d1_pd5, vi_vsync_pd6, vi_hsync_pd7,
38 lcd_d0_pe0, lcd_d1_pe1, lcd_d2_pe2, lcd_d3_pe3, lcd_d4_pe4, lcd_d5_pe5,
39 lcd_d6_pe6, lcd_d7_pe7, lcd_d8_pf0, lcd_d9_pf1, lcd_d10_pf2, lcd_d11_pf3,
40 lcd_d12_pf4, lcd_d13_pf5, lcd_d14_pf6, lcd_d15_pf7, gmi_ad0_pg0,
41 gmi_ad1_pg1, gmi_ad2_pg2, gmi_ad3_pg3, gmi_ad4_pg4, gmi_ad5_pg5,
42 gmi_ad6_pg6, gmi_ad7_pg7, gmi_ad8_ph0, gmi_ad9_ph1, gmi_ad10_ph2,
43 gmi_ad11_ph3, gmi_ad12_ph4, gmi_ad13_ph5, gmi_ad14_ph6, gmi_ad15_ph7,
44 gmi_wr_n_pi0, gmi_oe_n_pi1, gmi_dqs_pi2, gmi_cs6_n_pi3, gmi_rst_n_pi4,
45 gmi_iordy_pi5, gmi_cs7_n_pi6, gmi_wait_pi7, gmi_cs0_n_pj0, lcd_de_pj1,
46 gmi_cs1_n_pj2, lcd_hsync_pj3, lcd_vsync_pj4, uart2_cts_n_pj5,
47 uart2_rts_n_pj6, gmi_a16_pj7, gmi_adv_n_pk0, gmi_clk_pk1, gmi_cs4_n_pk2,
48 gmi_cs2_n_pk3, gmi_cs3_n_pk4, spdif_out_pk5, spdif_in_pk6, gmi_a19_pk7,
49 vi_d2_pl0, vi_d3_pl1, vi_d4_pl2, vi_d5_pl3, vi_d6_pl4, vi_d7_pl5,
50 vi_d8_pl6, vi_d9_pl7, lcd_d16_pm0, lcd_d17_pm1, lcd_d18_pm2, lcd_d19_pm3,
51 lcd_d20_pm4, lcd_d21_pm5, lcd_d22_pm6, lcd_d23_pm7, dap1_fs_pn0,
52 dap1_din_pn1, dap1_dout_pn2, dap1_sclk_pn3, lcd_cs0_n_pn4, lcd_sdout_pn5,
53 lcd_dc0_pn6, hdmi_int_pn7, ulpi_data7_po0, ulpi_data0_po1, ulpi_data1_po2,
54 ulpi_data2_po3, ulpi_data3_po4, ulpi_data4_po5, ulpi_data5_po6,
55 ulpi_data6_po7, dap3_fs_pp0, dap3_din_pp1, dap3_dout_pp2, dap3_sclk_pp3,
56 dap4_fs_pp4, dap4_din_pp5, dap4_dout_pp6, dap4_sclk_pp7, kb_col0_pq0,
57 kb_col1_pq1, kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5,
58 kb_col6_pq6, kb_col7_pq7, kb_row0_pr0, kb_row1_pr1, kb_row2_pr2,
59 kb_row3_pr3, kb_row4_pr4, kb_row5_pr5, kb_row6_pr6, kb_row7_pr7,
60 kb_row8_ps0, kb_row9_ps1, kb_row10_ps2, kb_row11_ps3, kb_row12_ps4,
61 kb_row13_ps5, kb_row14_ps6, kb_row15_ps7, vi_pclk_pt0, vi_mclk_pt1,
62 vi_d10_pt2, vi_d11_pt3, vi_d0_pt4, gen2_i2c_scl_pt5, gen2_i2c_sda_pt6,
63 sdmmc4_cmd_pt7, pu0, pu1, pu2, pu3, pu4, pu5, pu6, jtag_rtck_pu7, pv0,
64 pv1, pv2, pv3, ddc_scl_pv4, ddc_sda_pv5, crt_hsync_pv6, crt_vsync_pv7,
65 lcd_cs1_n_pw0, lcd_m1_pw1, spi2_cs1_n_pw2, spi2_cs2_n_pw3, clk1_out_pw4,
66 clk2_out_pw5, uart3_txd_pw6, uart3_rxd_pw7, spi2_mosi_px0, spi2_miso_px1,
67 spi2_sck_px2, spi2_cs0_n_px3, spi1_mosi_px4, spi1_sck_px5, spi1_cs0_n_px6,
68 spi1_miso_px7, ulpi_clk_py0, ulpi_dir_py1, ulpi_nxt_py2, ulpi_stp_py3,
69 sdmmc1_dat3_py4, sdmmc1_dat2_py5, sdmmc1_dat1_py6, sdmmc1_dat0_py7,
70 sdmmc1_clk_pz0, sdmmc1_cmd_pz1, lcd_sdin_pz2, lcd_wr_n_pz3, lcd_sck_pz4,
71 sys_clk_req_pz5, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, sdmmc4_dat0_paa0,
72 sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, sdmmc4_dat3_paa3, sdmmc4_dat4_paa4,
73 sdmmc4_dat5_paa5, sdmmc4_dat6_paa6, sdmmc4_dat7_paa7, pbb0,
74 cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6, pbb7,
75 cam_mclk_pcc0, pcc1, pcc2, sdmmc4_rst_n_pcc3, sdmmc4_clk_pcc4,
76 clk2_req_pcc5, pex_l2_rst_n_pcc6, pex_l2_clkreq_n_pcc7,
77 pex_l0_prsnt_n_pdd0, pex_l0_rst_n_pdd1, pex_l0_clkreq_n_pdd2,
78 pex_wake_n_pdd3, pex_l1_prsnt_n_pdd4, pex_l1_rst_n_pdd5,
79 pex_l1_clkreq_n_pdd6, pex_l2_prsnt_n_pdd7, clk3_out_pee0, clk3_req_pee1,
80 clk1_req_pee2, hdmi_cec_pee3, clk_32k_in, core_pwr_req, cpu_pwr_req, owr,
81 pwr_int_n.
82
83 drive groups:
84
85 These all support nvidia,pull-down-strength, nvidia,pull-up-strength,
86 nvidia,slew_rate-rising, nvidia,slew_rate-falling. Most but not all
87 support nvidia,high-speed-mode, nvidia,schmitt, nvidia,low-power-mode.
88
89 ao1, ao2, at1, at2, at3, at4, at5, cdev1, cdev2, cec, crt, csus, dap1,
90 dap2, dap3, dap4, dbg, ddc, dev3, gma, gmb, gmc, gmd, gme, gmf, gmg,
91 gmh, gpv, lcd1, lcd2, owr, sdio1, sdio2, sdio3, spi, uaa, uab, uart2,
92 uart3, uda, vi1.
93
94Example:
95
96 pinctrl@70000000 {
97 compatible = "nvidia,tegra30-pinmux";
98 reg = < 0x70000868 0xd0 /* Pad control registers */
99 0x70003000 0x3e0 >; /* Mux registers */
100 };
101
102Example board file extract:
103
104 pinctrl@70000000 {
105 sdmmc4_default: pinmux {
106 sdmmc4_clk_pcc4 {
107 nvidia,pins = "sdmmc4_clk_pcc4",
108 "sdmmc4_rst_n_pcc3";
109 nvidia,function = "sdmmc4";
110 nvidia,pull = <0>;
111 nvidia,tristate = <0>;
112 };
113 sdmmc4_dat0_paa0 {
114 nvidia,pins = "sdmmc4_dat0_paa0",
115 "sdmmc4_dat1_paa1",
116 "sdmmc4_dat2_paa2",
117 "sdmmc4_dat3_paa3",
118 "sdmmc4_dat4_paa4",
119 "sdmmc4_dat5_paa5",
120 "sdmmc4_dat6_paa6",
121 "sdmmc4_dat7_paa7";
122 nvidia,function = "sdmmc4";
123 nvidia,pull = <2>;
124 nvidia,tristate = <0>;
125 };
126 };
127 };
128
129 sdhci@78000400 {
130 pinctrl-names = "default";
131 pinctrl-0 = <&sdmmc4_default>;
132 };
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
new file mode 100644
index 00000000000..c95ea8278f8
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
@@ -0,0 +1,128 @@
1== Introduction ==
2
3Hardware modules that control pin multiplexing or configuration parameters
4such as pull-up/down, tri-state, drive-strength etc are designated as pin
5controllers. Each pin controller must be represented as a node in device tree,
6just like any other hardware module.
7
8Hardware modules whose signals are affected by pin configuration are
9designated client devices. Again, each client device must be represented as a
10node in device tree, just like any other hardware module.
11
12For a client device to operate correctly, certain pin controllers must
13set up certain specific pin configurations. Some client devices need a
14single static pin configuration, e.g. set up during initialization. Others
15need to reconfigure pins at run-time, for example to tri-state pins when the
16device is inactive. Hence, each client device can define a set of named
17states. The number and names of those states is defined by the client device's
18own binding.
19
20The common pinctrl bindings defined in this file provide an infrastructure
21for client device device tree nodes to map those state names to the pin
22configuration used by those states.
23
24Note that pin controllers themselves may also be client devices of themselves.
25For example, a pin controller may set up its own "active" state when the
26driver loads. This would allow representing a board's static pin configuration
27in a single place, rather than splitting it across multiple client device
28nodes. The decision to do this or not somewhat rests with the author of
29individual board device tree files, and any requirements imposed by the
30bindings for the individual client devices in use by that board, i.e. whether
31they require certain specific named states for dynamic pin configuration.
32
33== Pinctrl client devices ==
34
35For each client device individually, every pin state is assigned an integer
36ID. These numbers start at 0, and are contiguous. For each state ID, a unique
37property exists to define the pin configuration. Each state may also be
38assigned a name. When names are used, another property exists to map from
39those names to the integer IDs.
40
41Each client device's own binding determines the set of states the must be
42defined in its device tree node, and whether to define the set of state
43IDs that must be provided, or whether to define the set of state names that
44must be provided.
45
46Required properties:
47pinctrl-0: List of phandles, each pointing at a pin configuration
48 node. These referenced pin configuration nodes must be child
49 nodes of the pin controller that they configure. Multiple
50 entries may exist in this list so that multiple pin
51 controllers may be configured, or so that a state may be built
52 from multiple nodes for a single pin controller, each
53 contributing part of the overall configuration. See the next
54 section of this document for details of the format of these
55 pin configuration nodes.
56
57 In some cases, it may be useful to define a state, but for it
58 to be empty. This may be required when a common IP block is
59 used in an SoC either without a pin controller, or where the
60 pin controller does not affect the HW module in question. If
61 the binding for that IP block requires certain pin states to
62 exist, they must still be defined, but may be left empty.
63
64Optional properties:
65pinctrl-1: List of phandles, each pointing at a pin configuration
66 node within a pin controller.
67...
68pinctrl-n: List of phandles, each pointing at a pin configuration
69 node within a pin controller.
70pinctrl-names: The list of names to assign states. List entry 0 defines the
71 name for integer state ID 0, list entry 1 for state ID 1, and
72 so on.
73
74For example:
75
76 /* For a client device requiring named states */
77 device {
78 pinctrl-names = "active", "idle";
79 pinctrl-0 = <&state_0_node_a>;
80 pinctrl-1 = <&state_1_node_a &state_1_node_b>;
81 };
82
83 /* For the same device if using state IDs */
84 device {
85 pinctrl-0 = <&state_0_node_a>;
86 pinctrl-1 = <&state_1_node_a &state_1_node_b>;
87 };
88
89 /*
90 * For an IP block whose binding supports pin configuration,
91 * but in use on an SoC that doesn't have any pin control hardware
92 */
93 device {
94 pinctrl-names = "active", "idle";
95 pinctrl-0 = <>;
96 pinctrl-1 = <>;
97 };
98
99== Pin controller devices ==
100
101Pin controller devices should contain the pin configuration nodes that client
102devices reference.
103
104For example:
105
106 pincontroller {
107 ... /* Standard DT properties for the device itself elided */
108
109 state_0_node_a {
110 ...
111 };
112 state_1_node_a {
113 ...
114 };
115 state_1_node_b {
116 ...
117 };
118 }
119
120The contents of each of those pin configuration child nodes is defined
121entirely by the binding for the individual pin controller device. There
122exists no common standard for this content.
123
124The pin configuration nodes need not be direct children of the pin controller
125device; they may be grandchildren, for example. Whether this is legal, and
126whether there is any interaction between the child and intermediate parent
127nodes, is again defined entirely by the binding for the individual pin
128controller device.
diff --git a/Documentation/devicetree/bindings/pinmux/pinmux_nvidia.txt b/Documentation/devicetree/bindings/pinmux/pinmux_nvidia.txt
deleted file mode 100644
index 36f82dbdd14..00000000000
--- a/Documentation/devicetree/bindings/pinmux/pinmux_nvidia.txt
+++ /dev/null
@@ -1,5 +0,0 @@
1NVIDIA Tegra 2 pinmux controller
2
3Required properties:
4- compatible : "nvidia,tegra20-pinmux"
5
diff --git a/Documentation/driver-model/devres.txt b/Documentation/driver-model/devres.txt
index 9faac6ae352..950856bd2e3 100644
--- a/Documentation/driver-model/devres.txt
+++ b/Documentation/driver-model/devres.txt
@@ -280,3 +280,7 @@ REGULATOR
280CLOCK 280CLOCK
281 devm_clk_get() 281 devm_clk_get()
282 devm_clk_put() 282 devm_clk_put()
283
284PINCTRL
285 devm_pinctrl_get()
286 devm_pinctrl_put()
diff --git a/Documentation/pinctrl.txt b/Documentation/pinctrl.txt
index d97bccf4614..e40f4b4e197 100644
--- a/Documentation/pinctrl.txt
+++ b/Documentation/pinctrl.txt
@@ -152,11 +152,9 @@ static const struct foo_group foo_groups[] = {
152}; 152};
153 153
154 154
155static int foo_list_groups(struct pinctrl_dev *pctldev, unsigned selector) 155static int foo_get_groups_count(struct pinctrl_dev *pctldev)
156{ 156{
157 if (selector >= ARRAY_SIZE(foo_groups)) 157 return ARRAY_SIZE(foo_groups);
158 return -EINVAL;
159 return 0;
160} 158}
161 159
162static const char *foo_get_group_name(struct pinctrl_dev *pctldev, 160static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
@@ -175,7 +173,7 @@ static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
175} 173}
176 174
177static struct pinctrl_ops foo_pctrl_ops = { 175static struct pinctrl_ops foo_pctrl_ops = {
178 .list_groups = foo_list_groups, 176 .get_groups_count = foo_get_groups_count,
179 .get_group_name = foo_get_group_name, 177 .get_group_name = foo_get_group_name,
180 .get_group_pins = foo_get_group_pins, 178 .get_group_pins = foo_get_group_pins,
181}; 179};
@@ -186,13 +184,12 @@ static struct pinctrl_desc foo_desc = {
186 .pctlops = &foo_pctrl_ops, 184 .pctlops = &foo_pctrl_ops,
187}; 185};
188 186
189The pin control subsystem will call the .list_groups() function repeatedly 187The pin control subsystem will call the .get_groups_count() function to
190beginning on 0 until it returns non-zero to determine legal selectors, then 188determine total number of legal selectors, then it will call the other functions
191it will call the other functions to retrieve the name and pins of the group. 189to retrieve the name and pins of the group. Maintaining the data structure of
192Maintaining the data structure of the groups is up to the driver, this is 190the groups is up to the driver, this is just a simple example - in practice you
193just a simple example - in practice you may need more entries in your group 191may need more entries in your group structure, for example specific register
194structure, for example specific register ranges associated with each group 192ranges associated with each group and so on.
195and so on.
196 193
197 194
198Pin configuration 195Pin configuration
@@ -606,11 +603,9 @@ static const struct foo_group foo_groups[] = {
606}; 603};
607 604
608 605
609static int foo_list_groups(struct pinctrl_dev *pctldev, unsigned selector) 606static int foo_get_groups_count(struct pinctrl_dev *pctldev)
610{ 607{
611 if (selector >= ARRAY_SIZE(foo_groups)) 608 return ARRAY_SIZE(foo_groups);
612 return -EINVAL;
613 return 0;
614} 609}
615 610
616static const char *foo_get_group_name(struct pinctrl_dev *pctldev, 611static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
@@ -629,7 +624,7 @@ static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
629} 624}
630 625
631static struct pinctrl_ops foo_pctrl_ops = { 626static struct pinctrl_ops foo_pctrl_ops = {
632 .list_groups = foo_list_groups, 627 .get_groups_count = foo_get_groups_count,
633 .get_group_name = foo_get_group_name, 628 .get_group_name = foo_get_group_name,
634 .get_group_pins = foo_get_group_pins, 629 .get_group_pins = foo_get_group_pins,
635}; 630};
@@ -640,7 +635,7 @@ struct foo_pmx_func {
640 const unsigned num_groups; 635 const unsigned num_groups;
641}; 636};
642 637
643static const char * const spi0_groups[] = { "spi0_1_grp" }; 638static const char * const spi0_groups[] = { "spi0_0_grp", "spi0_1_grp" };
644static const char * const i2c0_groups[] = { "i2c0_grp" }; 639static const char * const i2c0_groups[] = { "i2c0_grp" };
645static const char * const mmc0_groups[] = { "mmc0_1_grp", "mmc0_2_grp", 640static const char * const mmc0_groups[] = { "mmc0_1_grp", "mmc0_2_grp",
646 "mmc0_3_grp" }; 641 "mmc0_3_grp" };
@@ -663,11 +658,9 @@ static const struct foo_pmx_func foo_functions[] = {
663 }, 658 },
664}; 659};
665 660
666int foo_list_funcs(struct pinctrl_dev *pctldev, unsigned selector) 661int foo_get_functions_count(struct pinctrl_dev *pctldev)
667{ 662{
668 if (selector >= ARRAY_SIZE(foo_functions)) 663 return ARRAY_SIZE(foo_functions);
669 return -EINVAL;
670 return 0;
671} 664}
672 665
673const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned selector) 666const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned selector)
@@ -703,7 +696,7 @@ void foo_disable(struct pinctrl_dev *pctldev, unsigned selector,
703} 696}
704 697
705struct pinmux_ops foo_pmxops = { 698struct pinmux_ops foo_pmxops = {
706 .list_functions = foo_list_funcs, 699 .get_functions_count = foo_get_functions_count,
707 .get_function_name = foo_get_fname, 700 .get_function_name = foo_get_fname,
708 .get_function_groups = foo_get_groups, 701 .get_function_groups = foo_get_groups,
709 .enable = foo_enable, 702 .enable = foo_enable,
@@ -786,7 +779,7 @@ and spi on the second function mapping:
786 779
787#include <linux/pinctrl/machine.h> 780#include <linux/pinctrl/machine.h>
788 781
789static const struct pinctrl_map __initdata mapping[] = { 782static const struct pinctrl_map mapping[] __initconst = {
790 { 783 {
791 .dev_name = "foo-spi.0", 784 .dev_name = "foo-spi.0",
792 .name = PINCTRL_STATE_DEFAULT, 785 .name = PINCTRL_STATE_DEFAULT,
@@ -952,13 +945,13 @@ case), we define a mapping like this:
952The result of grabbing this mapping from the device with something like 945The result of grabbing this mapping from the device with something like
953this (see next paragraph): 946this (see next paragraph):
954 947
955 p = pinctrl_get(dev); 948 p = devm_pinctrl_get(dev);
956 s = pinctrl_lookup_state(p, "8bit"); 949 s = pinctrl_lookup_state(p, "8bit");
957 ret = pinctrl_select_state(p, s); 950 ret = pinctrl_select_state(p, s);
958 951
959or more simply: 952or more simply:
960 953
961 p = pinctrl_get_select(dev, "8bit"); 954 p = devm_pinctrl_get_select(dev, "8bit");
962 955
963Will be that you activate all the three bottom records in the mapping at 956Will be that you activate all the three bottom records in the mapping at
964once. Since they share the same name, pin controller device, function and 957once. Since they share the same name, pin controller device, function and
@@ -992,7 +985,7 @@ foo_probe()
992 /* Allocate a state holder named "foo" etc */ 985 /* Allocate a state holder named "foo" etc */
993 struct foo_state *foo = ...; 986 struct foo_state *foo = ...;
994 987
995 foo->p = pinctrl_get(&device); 988 foo->p = devm_pinctrl_get(&device);
996 if (IS_ERR(foo->p)) { 989 if (IS_ERR(foo->p)) {
997 /* FIXME: clean up "foo" here */ 990 /* FIXME: clean up "foo" here */
998 return PTR_ERR(foo->p); 991 return PTR_ERR(foo->p);
@@ -1000,24 +993,17 @@ foo_probe()
1000 993
1001 foo->s = pinctrl_lookup_state(foo->p, PINCTRL_STATE_DEFAULT); 994 foo->s = pinctrl_lookup_state(foo->p, PINCTRL_STATE_DEFAULT);
1002 if (IS_ERR(foo->s)) { 995 if (IS_ERR(foo->s)) {
1003 pinctrl_put(foo->p);
1004 /* FIXME: clean up "foo" here */ 996 /* FIXME: clean up "foo" here */
1005 return PTR_ERR(s); 997 return PTR_ERR(s);
1006 } 998 }
1007 999
1008 ret = pinctrl_select_state(foo->s); 1000 ret = pinctrl_select_state(foo->s);
1009 if (ret < 0) { 1001 if (ret < 0) {
1010 pinctrl_put(foo->p);
1011 /* FIXME: clean up "foo" here */ 1002 /* FIXME: clean up "foo" here */
1012 return ret; 1003 return ret;
1013 } 1004 }
1014} 1005}
1015 1006
1016foo_remove()
1017{
1018 pinctrl_put(state->p);
1019}
1020
1021This get/lookup/select/put sequence can just as well be handled by bus drivers 1007This get/lookup/select/put sequence can just as well be handled by bus drivers
1022if you don't want each and every driver to handle it and you know the 1008if you don't want each and every driver to handle it and you know the
1023arrangement on your bus. 1009arrangement on your bus.
@@ -1029,6 +1015,11 @@ The semantics of the pinctrl APIs are:
1029 kernel memory to hold the pinmux state. All mapping table parsing or similar 1015 kernel memory to hold the pinmux state. All mapping table parsing or similar
1030 slow operations take place within this API. 1016 slow operations take place within this API.
1031 1017
1018- devm_pinctrl_get() is a variant of pinctrl_get() that causes pinctrl_put()
1019 to be called automatically on the retrieved pointer when the associated
1020 device is removed. It is recommended to use this function over plain
1021 pinctrl_get().
1022
1032- pinctrl_lookup_state() is called in process context to obtain a handle to a 1023- pinctrl_lookup_state() is called in process context to obtain a handle to a
1033 specific state for a the client device. This operation may be slow too. 1024 specific state for a the client device. This operation may be slow too.
1034 1025
@@ -1041,14 +1032,30 @@ The semantics of the pinctrl APIs are:
1041 1032
1042- pinctrl_put() frees all information associated with a pinctrl handle. 1033- pinctrl_put() frees all information associated with a pinctrl handle.
1043 1034
1035- devm_pinctrl_put() is a variant of pinctrl_put() that may be used to
1036 explicitly destroy a pinctrl object returned by devm_pinctrl_get().
1037 However, use of this function will be rare, due to the automatic cleanup
1038 that will occur even without calling it.
1039
1040 pinctrl_get() must be paired with a plain pinctrl_put().
1041 pinctrl_get() may not be paired with devm_pinctrl_put().
1042 devm_pinctrl_get() can optionally be paired with devm_pinctrl_put().
1043 devm_pinctrl_get() may not be paired with plain pinctrl_put().
1044
1044Usually the pin control core handled the get/put pair and call out to the 1045Usually the pin control core handled the get/put pair and call out to the
1045device drivers bookkeeping operations, like checking available functions and 1046device drivers bookkeeping operations, like checking available functions and
1046the associated pins, whereas the enable/disable pass on to the pin controller 1047the associated pins, whereas the enable/disable pass on to the pin controller
1047driver which takes care of activating and/or deactivating the mux setting by 1048driver which takes care of activating and/or deactivating the mux setting by
1048quickly poking some registers. 1049quickly poking some registers.
1049 1050
1050The pins are allocated for your device when you issue the pinctrl_get() call, 1051The pins are allocated for your device when you issue the devm_pinctrl_get()
1051after this you should be able to see this in the debugfs listing of all pins. 1052call, after this you should be able to see this in the debugfs listing of all
1053pins.
1054
1055NOTE: the pinctrl system will return -EPROBE_DEFER if it cannot find the
1056requested pinctrl handles, for example if the pinctrl driver has not yet
1057registered. Thus make sure that the error path in your driver gracefully
1058cleans up and is ready to retry the probing later in the startup process.
1052 1059
1053 1060
1054System pin control hogging 1061System pin control hogging
@@ -1094,13 +1101,13 @@ it, disables and releases it, and muxes it in on the pins defined by group B:
1094 1101
1095#include <linux/pinctrl/consumer.h> 1102#include <linux/pinctrl/consumer.h>
1096 1103
1097foo_switch() 1104struct pinctrl *p;
1098{ 1105struct pinctrl_state *s1, *s2;
1099 struct pinctrl *p;
1100 struct pinctrl_state *s1, *s2;
1101 1106
1107foo_probe()
1108{
1102 /* Setup */ 1109 /* Setup */
1103 p = pinctrl_get(&device); 1110 p = devm_pinctrl_get(&device);
1104 if (IS_ERR(p)) 1111 if (IS_ERR(p))
1105 ... 1112 ...
1106 1113
@@ -1111,7 +1118,10 @@ foo_switch()
1111 s2 = pinctrl_lookup_state(foo->p, "pos-B"); 1118 s2 = pinctrl_lookup_state(foo->p, "pos-B");
1112 if (IS_ERR(s2)) 1119 if (IS_ERR(s2))
1113 ... 1120 ...
1121}
1114 1122
1123foo_switch()
1124{
1115 /* Enable on position A */ 1125 /* Enable on position A */
1116 ret = pinctrl_select_state(s1); 1126 ret = pinctrl_select_state(s1);
1117 if (ret < 0) 1127 if (ret < 0)
@@ -1125,8 +1135,6 @@ foo_switch()
1125 ... 1135 ...
1126 1136
1127 ... 1137 ...
1128
1129 pinctrl_put(p);
1130} 1138}
1131 1139
1132The above has to be done from process context. 1140The above has to be done from process context.
diff --git a/drivers/of/base.c b/drivers/of/base.c
index 58064498694..d9bfd49b193 100644
--- a/drivers/of/base.c
+++ b/drivers/of/base.c
@@ -1260,3 +1260,44 @@ int of_alias_get_id(struct device_node *np, const char *stem)
1260 return id; 1260 return id;
1261} 1261}
1262EXPORT_SYMBOL_GPL(of_alias_get_id); 1262EXPORT_SYMBOL_GPL(of_alias_get_id);
1263
1264const __be32 *of_prop_next_u32(struct property *prop, const __be32 *cur,
1265 u32 *pu)
1266{
1267 const void *curv = cur;
1268
1269 if (!prop)
1270 return NULL;
1271
1272 if (!cur) {
1273 curv = prop->value;
1274 goto out_val;
1275 }
1276
1277 curv += sizeof(*cur);
1278 if (curv >= prop->value + prop->length)
1279 return NULL;
1280
1281out_val:
1282 *pu = be32_to_cpup(curv);
1283 return curv;
1284}
1285EXPORT_SYMBOL_GPL(of_prop_next_u32);
1286
1287const char *of_prop_next_string(struct property *prop, const char *cur)
1288{
1289 const void *curv = cur;
1290
1291 if (!prop)
1292 return NULL;
1293
1294 if (!cur)
1295 return prop->value;
1296
1297 curv += strlen(cur) + 1;
1298 if (curv >= prop->value + prop->length)
1299 return NULL;
1300
1301 return curv;
1302}
1303EXPORT_SYMBOL_GPL(of_prop_next_string);
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index abfb9640877..91c1f64102f 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -4,7 +4,6 @@
4 4
5config PINCTRL 5config PINCTRL
6 bool 6 bool
7 depends on EXPERIMENTAL
8 7
9if PINCTRL 8if PINCTRL
10 9
@@ -27,6 +26,35 @@ config DEBUG_PINCTRL
27 help 26 help
28 Say Y here to add some extra checks and diagnostics to PINCTRL calls. 27 Say Y here to add some extra checks and diagnostics to PINCTRL calls.
29 28
29config PINCTRL_IMX
30 bool
31 select PINMUX
32 select PINCONF
33
34config PINCTRL_IMX51
35 bool "IMX51 pinctrl driver"
36 depends on OF
37 depends on SOC_IMX51
38 select PINCTRL_IMX
39 help
40 Say Y here to enable the imx51 pinctrl driver
41
42config PINCTRL_IMX53
43 bool "IMX53 pinctrl driver"
44 depends on OF
45 depends on SOC_IMX53
46 select PINCTRL_IMX
47 help
48 Say Y here to enable the imx53 pinctrl driver
49
50config PINCTRL_IMX6Q
51 bool "IMX6Q pinctrl driver"
52 depends on OF
53 depends on SOC_IMX6Q
54 select PINCTRL_IMX
55 help
56 Say Y here to enable the imx6q pinctrl driver
57
30config PINCTRL_PXA3xx 58config PINCTRL_PXA3xx
31 bool 59 bool
32 select PINMUX 60 select PINMUX
@@ -37,6 +65,21 @@ config PINCTRL_MMP2
37 select PINCTRL_PXA3xx 65 select PINCTRL_PXA3xx
38 select PINCONF 66 select PINCONF
39 67
68config PINCTRL_MXS
69 bool
70
71config PINCTRL_IMX23
72 bool
73 select PINMUX
74 select PINCONF
75 select PINCTRL_MXS
76
77config PINCTRL_IMX28
78 bool
79 select PINMUX
80 select PINCONF
81 select PINCTRL_MXS
82
40config PINCTRL_PXA168 83config PINCTRL_PXA168
41 bool "PXA168 pin controller driver" 84 bool "PXA168 pin controller driver"
42 depends on ARCH_MMP 85 depends on ARCH_MMP
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 6d4150b4ece..515e32ff159 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -5,9 +5,19 @@ ccflags-$(CONFIG_DEBUG_PINCTRL) += -DDEBUG
5obj-$(CONFIG_PINCTRL) += core.o 5obj-$(CONFIG_PINCTRL) += core.o
6obj-$(CONFIG_PINMUX) += pinmux.o 6obj-$(CONFIG_PINMUX) += pinmux.o
7obj-$(CONFIG_PINCONF) += pinconf.o 7obj-$(CONFIG_PINCONF) += pinconf.o
8ifeq ($(CONFIG_OF),y)
9obj-$(CONFIG_PINCTRL) += devicetree.o
10endif
8obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o 11obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o
12obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
13obj-$(CONFIG_PINCTRL_IMX51) += pinctrl-imx51.o
14obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o
15obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o
9obj-$(CONFIG_PINCTRL_PXA3xx) += pinctrl-pxa3xx.o 16obj-$(CONFIG_PINCTRL_PXA3xx) += pinctrl-pxa3xx.o
10obj-$(CONFIG_PINCTRL_MMP2) += pinctrl-mmp2.o 17obj-$(CONFIG_PINCTRL_MMP2) += pinctrl-mmp2.o
18obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
19obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
20obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o
11obj-$(CONFIG_PINCTRL_PXA168) += pinctrl-pxa168.o 21obj-$(CONFIG_PINCTRL_PXA168) += pinctrl-pxa168.o
12obj-$(CONFIG_PINCTRL_PXA910) += pinctrl-pxa910.o 22obj-$(CONFIG_PINCTRL_PXA910) += pinctrl-pxa910.o
13obj-$(CONFIG_PINCTRL_SIRF) += pinctrl-sirf.o 23obj-$(CONFIG_PINCTRL_SIRF) += pinctrl-sirf.o
diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
index df6296c5f47..c3b331b74fa 100644
--- a/drivers/pinctrl/core.c
+++ b/drivers/pinctrl/core.c
@@ -23,9 +23,11 @@
23#include <linux/sysfs.h> 23#include <linux/sysfs.h>
24#include <linux/debugfs.h> 24#include <linux/debugfs.h>
25#include <linux/seq_file.h> 25#include <linux/seq_file.h>
26#include <linux/pinctrl/consumer.h>
26#include <linux/pinctrl/pinctrl.h> 27#include <linux/pinctrl/pinctrl.h>
27#include <linux/pinctrl/machine.h> 28#include <linux/pinctrl/machine.h>
28#include "core.h" 29#include "core.h"
30#include "devicetree.h"
29#include "pinmux.h" 31#include "pinmux.h"
30#include "pinconf.h" 32#include "pinconf.h"
31 33
@@ -41,11 +43,13 @@ struct pinctrl_maps {
41 unsigned num_maps; 43 unsigned num_maps;
42}; 44};
43 45
46static bool pinctrl_dummy_state;
47
44/* Mutex taken by all entry points */ 48/* Mutex taken by all entry points */
45DEFINE_MUTEX(pinctrl_mutex); 49DEFINE_MUTEX(pinctrl_mutex);
46 50
47/* Global list of pin control devices (struct pinctrl_dev) */ 51/* Global list of pin control devices (struct pinctrl_dev) */
48static LIST_HEAD(pinctrldev_list); 52LIST_HEAD(pinctrldev_list);
49 53
50/* List of pin controller handles (struct pinctrl) */ 54/* List of pin controller handles (struct pinctrl) */
51static LIST_HEAD(pinctrl_list); 55static LIST_HEAD(pinctrl_list);
@@ -59,6 +63,19 @@ static LIST_HEAD(pinctrl_maps);
59 _i_ < _maps_node_->num_maps; \ 63 _i_ < _maps_node_->num_maps; \
60 i++, _map_ = &_maps_node_->maps[_i_]) 64 i++, _map_ = &_maps_node_->maps[_i_])
61 65
66/**
67 * pinctrl_provide_dummies() - indicate if pinctrl provides dummy state support
68 *
69 * Usually this function is called by platforms without pinctrl driver support
70 * but run with some shared drivers using pinctrl APIs.
71 * After calling this function, the pinctrl core will return successfully
72 * with creating a dummy state for the driver to keep going smoothly.
73 */
74void pinctrl_provide_dummies(void)
75{
76 pinctrl_dummy_state = true;
77}
78
62const char *pinctrl_dev_get_name(struct pinctrl_dev *pctldev) 79const char *pinctrl_dev_get_name(struct pinctrl_dev *pctldev)
63{ 80{
64 /* We're not allowed to register devices without name */ 81 /* We're not allowed to register devices without name */
@@ -124,6 +141,25 @@ int pin_get_from_name(struct pinctrl_dev *pctldev, const char *name)
124} 141}
125 142
126/** 143/**
144 * pin_get_name_from_id() - look up a pin name from a pin id
145 * @pctldev: the pin control device to lookup the pin on
146 * @name: the name of the pin to look up
147 */
148const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned pin)
149{
150 const struct pin_desc *desc;
151
152 desc = pin_desc_get(pctldev, pin);
153 if (desc == NULL) {
154 dev_err(pctldev->dev, "failed to get pin(%d) name\n",
155 pin);
156 return NULL;
157 }
158
159 return desc->name;
160}
161
162/**
127 * pin_is_valid() - check if pin exists on controller 163 * pin_is_valid() - check if pin exists on controller
128 * @pctldev: the pin control device to check the pin on 164 * @pctldev: the pin control device to check the pin on
129 * @pin: pin to check, use the local pin controller index number 165 * @pin: pin to check, use the local pin controller index number
@@ -255,7 +291,8 @@ pinctrl_match_gpio_range(struct pinctrl_dev *pctldev, unsigned gpio)
255 * 291 *
256 * Find the pin controller handling a certain GPIO pin from the pinspace of 292 * Find the pin controller handling a certain GPIO pin from the pinspace of
257 * the GPIO subsystem, return the device and the matching GPIO range. Returns 293 * the GPIO subsystem, return the device and the matching GPIO range. Returns
258 * negative if the GPIO range could not be found in any device. 294 * -EPROBE_DEFER if the GPIO range could not be found in any device since it
295 * may still have not been registered.
259 */ 296 */
260static int pinctrl_get_device_gpio_range(unsigned gpio, 297static int pinctrl_get_device_gpio_range(unsigned gpio,
261 struct pinctrl_dev **outdev, 298 struct pinctrl_dev **outdev,
@@ -275,7 +312,7 @@ static int pinctrl_get_device_gpio_range(unsigned gpio,
275 } 312 }
276 } 313 }
277 314
278 return -EINVAL; 315 return -EPROBE_DEFER;
279} 316}
280 317
281/** 318/**
@@ -318,9 +355,10 @@ int pinctrl_get_group_selector(struct pinctrl_dev *pctldev,
318 const char *pin_group) 355 const char *pin_group)
319{ 356{
320 const struct pinctrl_ops *pctlops = pctldev->desc->pctlops; 357 const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
358 unsigned ngroups = pctlops->get_groups_count(pctldev);
321 unsigned group_selector = 0; 359 unsigned group_selector = 0;
322 360
323 while (pctlops->list_groups(pctldev, group_selector) >= 0) { 361 while (group_selector < ngroups) {
324 const char *gname = pctlops->get_group_name(pctldev, 362 const char *gname = pctlops->get_group_name(pctldev,
325 group_selector); 363 group_selector);
326 if (!strcmp(gname, pin_group)) { 364 if (!strcmp(gname, pin_group)) {
@@ -360,7 +398,7 @@ int pinctrl_request_gpio(unsigned gpio)
360 ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range); 398 ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range);
361 if (ret) { 399 if (ret) {
362 mutex_unlock(&pinctrl_mutex); 400 mutex_unlock(&pinctrl_mutex);
363 return -EINVAL; 401 return ret;
364 } 402 }
365 403
366 /* Convert to the pin controllers number space */ 404 /* Convert to the pin controllers number space */
@@ -516,11 +554,14 @@ static int add_setting(struct pinctrl *p, struct pinctrl_map const *map)
516 554
517 setting->pctldev = get_pinctrl_dev_from_devname(map->ctrl_dev_name); 555 setting->pctldev = get_pinctrl_dev_from_devname(map->ctrl_dev_name);
518 if (setting->pctldev == NULL) { 556 if (setting->pctldev == NULL) {
519 dev_err(p->dev, "unknown pinctrl device %s in map entry", 557 dev_info(p->dev, "unknown pinctrl device %s in map entry, deferring probe",
520 map->ctrl_dev_name); 558 map->ctrl_dev_name);
521 kfree(setting); 559 kfree(setting);
522 /* Eventually, this should trigger deferred probe */ 560 /*
523 return -ENODEV; 561 * OK let us guess that the driver is not there yet, and
562 * let's defer obtaining this pinctrl handle to later...
563 */
564 return -EPROBE_DEFER;
524 } 565 }
525 566
526 switch (map->type) { 567 switch (map->type) {
@@ -579,6 +620,13 @@ static struct pinctrl *create_pinctrl(struct device *dev)
579 } 620 }
580 p->dev = dev; 621 p->dev = dev;
581 INIT_LIST_HEAD(&p->states); 622 INIT_LIST_HEAD(&p->states);
623 INIT_LIST_HEAD(&p->dt_maps);
624
625 ret = pinctrl_dt_to_map(p);
626 if (ret < 0) {
627 kfree(p);
628 return ERR_PTR(ret);
629 }
582 630
583 devname = dev_name(dev); 631 devname = dev_name(dev);
584 632
@@ -662,6 +710,8 @@ static void pinctrl_put_locked(struct pinctrl *p, bool inlist)
662 kfree(state); 710 kfree(state);
663 } 711 }
664 712
713 pinctrl_dt_free_maps(p);
714
665 if (inlist) 715 if (inlist)
666 list_del(&p->node); 716 list_del(&p->node);
667 kfree(p); 717 kfree(p);
@@ -685,8 +735,18 @@ static struct pinctrl_state *pinctrl_lookup_state_locked(struct pinctrl *p,
685 struct pinctrl_state *state; 735 struct pinctrl_state *state;
686 736
687 state = find_state(p, name); 737 state = find_state(p, name);
688 if (!state) 738 if (!state) {
689 return ERR_PTR(-ENODEV); 739 if (pinctrl_dummy_state) {
740 /* create dummy state */
741 dev_dbg(p->dev, "using pinctrl dummy state (%s)\n",
742 name);
743 state = create_state(p, name);
744 if (IS_ERR(state))
745 return state;
746 } else {
747 return ERR_PTR(-ENODEV);
748 }
749 }
690 750
691 return state; 751 return state;
692} 752}
@@ -787,15 +847,63 @@ int pinctrl_select_state(struct pinctrl *p, struct pinctrl_state *state)
787} 847}
788EXPORT_SYMBOL_GPL(pinctrl_select_state); 848EXPORT_SYMBOL_GPL(pinctrl_select_state);
789 849
850static void devm_pinctrl_release(struct device *dev, void *res)
851{
852 pinctrl_put(*(struct pinctrl **)res);
853}
854
790/** 855/**
791 * pinctrl_register_mappings() - register a set of pin controller mappings 856 * struct devm_pinctrl_get() - Resource managed pinctrl_get()
792 * @maps: the pincontrol mappings table to register. This should probably be 857 * @dev: the device to obtain the handle for
793 * marked with __initdata so it can be discarded after boot. This 858 *
794 * function will perform a shallow copy for the mapping entries. 859 * If there is a need to explicitly destroy the returned struct pinctrl,
795 * @num_maps: the number of maps in the mapping table 860 * devm_pinctrl_put() should be used, rather than plain pinctrl_put().
796 */ 861 */
797int pinctrl_register_mappings(struct pinctrl_map const *maps, 862struct pinctrl *devm_pinctrl_get(struct device *dev)
798 unsigned num_maps) 863{
864 struct pinctrl **ptr, *p;
865
866 ptr = devres_alloc(devm_pinctrl_release, sizeof(*ptr), GFP_KERNEL);
867 if (!ptr)
868 return ERR_PTR(-ENOMEM);
869
870 p = pinctrl_get(dev);
871 if (!IS_ERR(p)) {
872 *ptr = p;
873 devres_add(dev, ptr);
874 } else {
875 devres_free(ptr);
876 }
877
878 return p;
879}
880EXPORT_SYMBOL_GPL(devm_pinctrl_get);
881
882static int devm_pinctrl_match(struct device *dev, void *res, void *data)
883{
884 struct pinctrl **p = res;
885
886 return *p == data;
887}
888
889/**
890 * devm_pinctrl_put() - Resource managed pinctrl_put()
891 * @p: the pinctrl handle to release
892 *
893 * Deallocate a struct pinctrl obtained via devm_pinctrl_get(). Normally
894 * this function will not need to be called and the resource management
895 * code will ensure that the resource is freed.
896 */
897void devm_pinctrl_put(struct pinctrl *p)
898{
899 WARN_ON(devres_destroy(p->dev, devm_pinctrl_release,
900 devm_pinctrl_match, p));
901 pinctrl_put(p);
902}
903EXPORT_SYMBOL_GPL(devm_pinctrl_put);
904
905int pinctrl_register_map(struct pinctrl_map const *maps, unsigned num_maps,
906 bool dup, bool locked)
799{ 907{
800 int i, ret; 908 int i, ret;
801 struct pinctrl_maps *maps_node; 909 struct pinctrl_maps *maps_node;
@@ -829,13 +937,13 @@ int pinctrl_register_mappings(struct pinctrl_map const *maps,
829 case PIN_MAP_TYPE_MUX_GROUP: 937 case PIN_MAP_TYPE_MUX_GROUP:
830 ret = pinmux_validate_map(&maps[i], i); 938 ret = pinmux_validate_map(&maps[i], i);
831 if (ret < 0) 939 if (ret < 0)
832 return 0; 940 return ret;
833 break; 941 break;
834 case PIN_MAP_TYPE_CONFIGS_PIN: 942 case PIN_MAP_TYPE_CONFIGS_PIN:
835 case PIN_MAP_TYPE_CONFIGS_GROUP: 943 case PIN_MAP_TYPE_CONFIGS_GROUP:
836 ret = pinconf_validate_map(&maps[i], i); 944 ret = pinconf_validate_map(&maps[i], i);
837 if (ret < 0) 945 if (ret < 0)
838 return 0; 946 return ret;
839 break; 947 break;
840 default: 948 default:
841 pr_err("failed to register map %s (%d): invalid type given\n", 949 pr_err("failed to register map %s (%d): invalid type given\n",
@@ -851,20 +959,52 @@ int pinctrl_register_mappings(struct pinctrl_map const *maps,
851 } 959 }
852 960
853 maps_node->num_maps = num_maps; 961 maps_node->num_maps = num_maps;
854 maps_node->maps = kmemdup(maps, sizeof(*maps) * num_maps, GFP_KERNEL); 962 if (dup) {
855 if (!maps_node->maps) { 963 maps_node->maps = kmemdup(maps, sizeof(*maps) * num_maps,
856 pr_err("failed to duplicate mapping table\n"); 964 GFP_KERNEL);
857 kfree(maps_node); 965 if (!maps_node->maps) {
858 return -ENOMEM; 966 pr_err("failed to duplicate mapping table\n");
967 kfree(maps_node);
968 return -ENOMEM;
969 }
970 } else {
971 maps_node->maps = maps;
859 } 972 }
860 973
861 mutex_lock(&pinctrl_mutex); 974 if (!locked)
975 mutex_lock(&pinctrl_mutex);
862 list_add_tail(&maps_node->node, &pinctrl_maps); 976 list_add_tail(&maps_node->node, &pinctrl_maps);
863 mutex_unlock(&pinctrl_mutex); 977 if (!locked)
978 mutex_unlock(&pinctrl_mutex);
864 979
865 return 0; 980 return 0;
866} 981}
867 982
983/**
984 * pinctrl_register_mappings() - register a set of pin controller mappings
985 * @maps: the pincontrol mappings table to register. This should probably be
986 * marked with __initdata so it can be discarded after boot. This
987 * function will perform a shallow copy for the mapping entries.
988 * @num_maps: the number of maps in the mapping table
989 */
990int pinctrl_register_mappings(struct pinctrl_map const *maps,
991 unsigned num_maps)
992{
993 return pinctrl_register_map(maps, num_maps, true, false);
994}
995
996void pinctrl_unregister_map(struct pinctrl_map const *map)
997{
998 struct pinctrl_maps *maps_node;
999
1000 list_for_each_entry(maps_node, &pinctrl_maps, node) {
1001 if (maps_node->maps == map) {
1002 list_del(&maps_node->node);
1003 return;
1004 }
1005 }
1006}
1007
868#ifdef CONFIG_DEBUG_FS 1008#ifdef CONFIG_DEBUG_FS
869 1009
870static int pinctrl_pins_show(struct seq_file *s, void *what) 1010static int pinctrl_pins_show(struct seq_file *s, void *what)
@@ -906,15 +1046,17 @@ static int pinctrl_groups_show(struct seq_file *s, void *what)
906{ 1046{
907 struct pinctrl_dev *pctldev = s->private; 1047 struct pinctrl_dev *pctldev = s->private;
908 const struct pinctrl_ops *ops = pctldev->desc->pctlops; 1048 const struct pinctrl_ops *ops = pctldev->desc->pctlops;
909 unsigned selector = 0; 1049 unsigned ngroups, selector = 0;
910 1050
1051 ngroups = ops->get_groups_count(pctldev);
911 mutex_lock(&pinctrl_mutex); 1052 mutex_lock(&pinctrl_mutex);
912 1053
913 seq_puts(s, "registered pin groups:\n"); 1054 seq_puts(s, "registered pin groups:\n");
914 while (ops->list_groups(pctldev, selector) >= 0) { 1055 while (selector < ngroups) {
915 const unsigned *pins; 1056 const unsigned *pins;
916 unsigned num_pins; 1057 unsigned num_pins;
917 const char *gname = ops->get_group_name(pctldev, selector); 1058 const char *gname = ops->get_group_name(pctldev, selector);
1059 const char *pname;
918 int ret; 1060 int ret;
919 int i; 1061 int i;
920 1062
@@ -924,10 +1066,14 @@ static int pinctrl_groups_show(struct seq_file *s, void *what)
924 seq_printf(s, "%s [ERROR GETTING PINS]\n", 1066 seq_printf(s, "%s [ERROR GETTING PINS]\n",
925 gname); 1067 gname);
926 else { 1068 else {
927 seq_printf(s, "group: %s, pins = [ ", gname); 1069 seq_printf(s, "group: %s\n", gname);
928 for (i = 0; i < num_pins; i++) 1070 for (i = 0; i < num_pins; i++) {
929 seq_printf(s, "%d ", pins[i]); 1071 pname = pin_get_name(pctldev, pins[i]);
930 seq_puts(s, "]\n"); 1072 if (WARN_ON(!pname))
1073 return -EINVAL;
1074 seq_printf(s, "pin %d (%s)\n", pins[i], pname);
1075 }
1076 seq_puts(s, "\n");
931 } 1077 }
932 selector++; 1078 selector++;
933 } 1079 }
@@ -1226,11 +1372,14 @@ static int pinctrl_check_ops(struct pinctrl_dev *pctldev)
1226 const struct pinctrl_ops *ops = pctldev->desc->pctlops; 1372 const struct pinctrl_ops *ops = pctldev->desc->pctlops;
1227 1373
1228 if (!ops || 1374 if (!ops ||
1229 !ops->list_groups || 1375 !ops->get_groups_count ||
1230 !ops->get_group_name || 1376 !ops->get_group_name ||
1231 !ops->get_group_pins) 1377 !ops->get_group_pins)
1232 return -EINVAL; 1378 return -EINVAL;
1233 1379
1380 if (ops->dt_node_to_map && !ops->dt_free_map)
1381 return -EINVAL;
1382
1234 return 0; 1383 return 0;
1235} 1384}
1236 1385
@@ -1268,37 +1417,29 @@ struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc,
1268 /* check core ops for sanity */ 1417 /* check core ops for sanity */
1269 ret = pinctrl_check_ops(pctldev); 1418 ret = pinctrl_check_ops(pctldev);
1270 if (ret) { 1419 if (ret) {
1271 pr_err("%s pinctrl ops lacks necessary functions\n", 1420 dev_err(dev, "pinctrl ops lacks necessary functions\n");
1272 pctldesc->name);
1273 goto out_err; 1421 goto out_err;
1274 } 1422 }
1275 1423
1276 /* If we're implementing pinmuxing, check the ops for sanity */ 1424 /* If we're implementing pinmuxing, check the ops for sanity */
1277 if (pctldesc->pmxops) { 1425 if (pctldesc->pmxops) {
1278 ret = pinmux_check_ops(pctldev); 1426 ret = pinmux_check_ops(pctldev);
1279 if (ret) { 1427 if (ret)
1280 pr_err("%s pinmux ops lacks necessary functions\n",
1281 pctldesc->name);
1282 goto out_err; 1428 goto out_err;
1283 }
1284 } 1429 }
1285 1430
1286 /* If we're implementing pinconfig, check the ops for sanity */ 1431 /* If we're implementing pinconfig, check the ops for sanity */
1287 if (pctldesc->confops) { 1432 if (pctldesc->confops) {
1288 ret = pinconf_check_ops(pctldev); 1433 ret = pinconf_check_ops(pctldev);
1289 if (ret) { 1434 if (ret)
1290 pr_err("%s pin config ops lacks necessary functions\n",
1291 pctldesc->name);
1292 goto out_err; 1435 goto out_err;
1293 }
1294 } 1436 }
1295 1437
1296 /* Register all the pins */ 1438 /* Register all the pins */
1297 pr_debug("try to register %d pins on %s...\n", 1439 dev_dbg(dev, "try to register %d pins ...\n", pctldesc->npins);
1298 pctldesc->npins, pctldesc->name);
1299 ret = pinctrl_register_pins(pctldev, pctldesc->pins, pctldesc->npins); 1440 ret = pinctrl_register_pins(pctldev, pctldesc->pins, pctldesc->npins);
1300 if (ret) { 1441 if (ret) {
1301 pr_err("error during pin registration\n"); 1442 dev_err(dev, "error during pin registration\n");
1302 pinctrl_free_pindescs(pctldev, pctldesc->pins, 1443 pinctrl_free_pindescs(pctldev, pctldesc->pins,
1303 pctldesc->npins); 1444 pctldesc->npins);
1304 goto out_err; 1445 goto out_err;
@@ -1313,8 +1454,15 @@ struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc,
1313 struct pinctrl_state *s = 1454 struct pinctrl_state *s =
1314 pinctrl_lookup_state_locked(pctldev->p, 1455 pinctrl_lookup_state_locked(pctldev->p,
1315 PINCTRL_STATE_DEFAULT); 1456 PINCTRL_STATE_DEFAULT);
1316 if (!IS_ERR(s)) 1457 if (IS_ERR(s)) {
1317 pinctrl_select_state_locked(pctldev->p, s); 1458 dev_dbg(dev, "failed to lookup the default state\n");
1459 } else {
1460 ret = pinctrl_select_state_locked(pctldev->p, s);
1461 if (ret) {
1462 dev_err(dev,
1463 "failed to select default state\n");
1464 }
1465 }
1318 } 1466 }
1319 1467
1320 mutex_unlock(&pinctrl_mutex); 1468 mutex_unlock(&pinctrl_mutex);
diff --git a/drivers/pinctrl/core.h b/drivers/pinctrl/core.h
index 17ecf651b12..1f40ff68a8c 100644
--- a/drivers/pinctrl/core.h
+++ b/drivers/pinctrl/core.h
@@ -52,12 +52,15 @@ struct pinctrl_dev {
52 * @dev: the device using this pin control handle 52 * @dev: the device using this pin control handle
53 * @states: a list of states for this device 53 * @states: a list of states for this device
54 * @state: the current state 54 * @state: the current state
55 * @dt_maps: the mapping table chunks dynamically parsed from device tree for
56 * this device, if any
55 */ 57 */
56struct pinctrl { 58struct pinctrl {
57 struct list_head node; 59 struct list_head node;
58 struct device *dev; 60 struct device *dev;
59 struct list_head states; 61 struct list_head states;
60 struct pinctrl_state *state; 62 struct pinctrl_state *state;
63 struct list_head dt_maps;
61}; 64};
62 65
63/** 66/**
@@ -100,7 +103,8 @@ struct pinctrl_setting_configs {
100 * struct pinctrl_setting - an individual mux or config setting 103 * struct pinctrl_setting - an individual mux or config setting
101 * @node: list node for struct pinctrl_settings's @settings field 104 * @node: list node for struct pinctrl_settings's @settings field
102 * @type: the type of setting 105 * @type: the type of setting
103 * @pctldev: pin control device handling to be programmed 106 * @pctldev: pin control device handling to be programmed. Not used for
107 * PIN_MAP_TYPE_DUMMY_STATE.
104 * @data: Data specific to the setting type 108 * @data: Data specific to the setting type
105 */ 109 */
106struct pinctrl_setting { 110struct pinctrl_setting {
@@ -144,6 +148,7 @@ struct pin_desc {
144 148
145struct pinctrl_dev *get_pinctrl_dev_from_devname(const char *dev_name); 149struct pinctrl_dev *get_pinctrl_dev_from_devname(const char *dev_name);
146int pin_get_from_name(struct pinctrl_dev *pctldev, const char *name); 150int pin_get_from_name(struct pinctrl_dev *pctldev, const char *name);
151const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned pin);
147int pinctrl_get_group_selector(struct pinctrl_dev *pctldev, 152int pinctrl_get_group_selector(struct pinctrl_dev *pctldev,
148 const char *pin_group); 153 const char *pin_group);
149 154
@@ -153,4 +158,9 @@ static inline struct pin_desc *pin_desc_get(struct pinctrl_dev *pctldev,
153 return radix_tree_lookup(&pctldev->pin_desc_tree, pin); 158 return radix_tree_lookup(&pctldev->pin_desc_tree, pin);
154} 159}
155 160
161int pinctrl_register_map(struct pinctrl_map const *maps, unsigned num_maps,
162 bool dup, bool locked);
163void pinctrl_unregister_map(struct pinctrl_map const *map);
164
156extern struct mutex pinctrl_mutex; 165extern struct mutex pinctrl_mutex;
166extern struct list_head pinctrldev_list;
diff --git a/drivers/pinctrl/devicetree.c b/drivers/pinctrl/devicetree.c
new file mode 100644
index 00000000000..fcb1de45473
--- /dev/null
+++ b/drivers/pinctrl/devicetree.c
@@ -0,0 +1,249 @@
1/*
2 * Device tree integration for the pin control subsystem
3 *
4 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include <linux/device.h>
20#include <linux/of.h>
21#include <linux/pinctrl/pinctrl.h>
22#include <linux/slab.h>
23
24#include "core.h"
25#include "devicetree.h"
26
27/**
28 * struct pinctrl_dt_map - mapping table chunk parsed from device tree
29 * @node: list node for struct pinctrl's @dt_maps field
30 * @pctldev: the pin controller that allocated this struct, and will free it
31 * @maps: the mapping table entries
32 */
33struct pinctrl_dt_map {
34 struct list_head node;
35 struct pinctrl_dev *pctldev;
36 struct pinctrl_map *map;
37 unsigned num_maps;
38};
39
40static void dt_free_map(struct pinctrl_dev *pctldev,
41 struct pinctrl_map *map, unsigned num_maps)
42{
43 if (pctldev) {
44 struct pinctrl_ops *ops = pctldev->desc->pctlops;
45 ops->dt_free_map(pctldev, map, num_maps);
46 } else {
47 /* There is no pctldev for PIN_MAP_TYPE_DUMMY_STATE */
48 kfree(map);
49 }
50}
51
52void pinctrl_dt_free_maps(struct pinctrl *p)
53{
54 struct pinctrl_dt_map *dt_map, *n1;
55
56 list_for_each_entry_safe(dt_map, n1, &p->dt_maps, node) {
57 pinctrl_unregister_map(dt_map->map);
58 list_del(&dt_map->node);
59 dt_free_map(dt_map->pctldev, dt_map->map,
60 dt_map->num_maps);
61 kfree(dt_map);
62 }
63
64 of_node_put(p->dev->of_node);
65}
66
67static int dt_remember_or_free_map(struct pinctrl *p, const char *statename,
68 struct pinctrl_dev *pctldev,
69 struct pinctrl_map *map, unsigned num_maps)
70{
71 int i;
72 struct pinctrl_dt_map *dt_map;
73
74 /* Initialize common mapping table entry fields */
75 for (i = 0; i < num_maps; i++) {
76 map[i].dev_name = dev_name(p->dev);
77 map[i].name = statename;
78 if (pctldev)
79 map[i].ctrl_dev_name = dev_name(pctldev->dev);
80 }
81
82 /* Remember the converted mapping table entries */
83 dt_map = kzalloc(sizeof(*dt_map), GFP_KERNEL);
84 if (!dt_map) {
85 dev_err(p->dev, "failed to alloc struct pinctrl_dt_map\n");
86 dt_free_map(pctldev, map, num_maps);
87 return -ENOMEM;
88 }
89
90 dt_map->pctldev = pctldev;
91 dt_map->map = map;
92 dt_map->num_maps = num_maps;
93 list_add_tail(&dt_map->node, &p->dt_maps);
94
95 return pinctrl_register_map(map, num_maps, false, true);
96}
97
98static struct pinctrl_dev *find_pinctrl_by_of_node(struct device_node *np)
99{
100 struct pinctrl_dev *pctldev;
101
102 list_for_each_entry(pctldev, &pinctrldev_list, node)
103 if (pctldev->dev->of_node == np)
104 return pctldev;
105
106 return NULL;
107}
108
109static int dt_to_map_one_config(struct pinctrl *p, const char *statename,
110 struct device_node *np_config)
111{
112 struct device_node *np_pctldev;
113 struct pinctrl_dev *pctldev;
114 struct pinctrl_ops *ops;
115 int ret;
116 struct pinctrl_map *map;
117 unsigned num_maps;
118
119 /* Find the pin controller containing np_config */
120 np_pctldev = of_node_get(np_config);
121 for (;;) {
122 np_pctldev = of_get_next_parent(np_pctldev);
123 if (!np_pctldev || of_node_is_root(np_pctldev)) {
124 dev_info(p->dev, "could not find pctldev for node %s, deferring probe\n",
125 np_config->full_name);
126 of_node_put(np_pctldev);
127 /* OK let's just assume this will appear later then */
128 return -EPROBE_DEFER;
129 }
130 pctldev = find_pinctrl_by_of_node(np_pctldev);
131 if (pctldev)
132 break;
133 }
134 of_node_put(np_pctldev);
135
136 /*
137 * Call pinctrl driver to parse device tree node, and
138 * generate mapping table entries
139 */
140 ops = pctldev->desc->pctlops;
141 if (!ops->dt_node_to_map) {
142 dev_err(p->dev, "pctldev %s doesn't support DT\n",
143 dev_name(pctldev->dev));
144 return -ENODEV;
145 }
146 ret = ops->dt_node_to_map(pctldev, np_config, &map, &num_maps);
147 if (ret < 0)
148 return ret;
149
150 /* Stash the mapping table chunk away for later use */
151 return dt_remember_or_free_map(p, statename, pctldev, map, num_maps);
152}
153
154static int dt_remember_dummy_state(struct pinctrl *p, const char *statename)
155{
156 struct pinctrl_map *map;
157
158 map = kzalloc(sizeof(*map), GFP_KERNEL);
159 if (!map) {
160 dev_err(p->dev, "failed to alloc struct pinctrl_map\n");
161 return -ENOMEM;
162 }
163
164 /* There is no pctldev for PIN_MAP_TYPE_DUMMY_STATE */
165 map->type = PIN_MAP_TYPE_DUMMY_STATE;
166
167 return dt_remember_or_free_map(p, statename, NULL, map, 1);
168}
169
170int pinctrl_dt_to_map(struct pinctrl *p)
171{
172 struct device_node *np = p->dev->of_node;
173 int state, ret;
174 char *propname;
175 struct property *prop;
176 const char *statename;
177 const __be32 *list;
178 int size, config;
179 phandle phandle;
180 struct device_node *np_config;
181
182 /* CONFIG_OF enabled, p->dev not instantiated from DT */
183 if (!np) {
184 dev_dbg(p->dev, "no of_node; not parsing pinctrl DT\n");
185 return 0;
186 }
187
188 /* We may store pointers to property names within the node */
189 of_node_get(np);
190
191 /* For each defined state ID */
192 for (state = 0; ; state++) {
193 /* Retrieve the pinctrl-* property */
194 propname = kasprintf(GFP_KERNEL, "pinctrl-%d", state);
195 prop = of_find_property(np, propname, &size);
196 kfree(propname);
197 if (!prop)
198 break;
199 list = prop->value;
200 size /= sizeof(*list);
201
202 /* Determine whether pinctrl-names property names the state */
203 ret = of_property_read_string_index(np, "pinctrl-names",
204 state, &statename);
205 /*
206 * If not, statename is just the integer state ID. But rather
207 * than dynamically allocate it and have to free it later,
208 * just point part way into the property name for the string.
209 */
210 if (ret < 0) {
211 /* strlen("pinctrl-") == 8 */
212 statename = prop->name + 8;
213 }
214
215 /* For every referenced pin configuration node in it */
216 for (config = 0; config < size; config++) {
217 phandle = be32_to_cpup(list++);
218
219 /* Look up the pin configuration node */
220 np_config = of_find_node_by_phandle(phandle);
221 if (!np_config) {
222 dev_err(p->dev,
223 "prop %s index %i invalid phandle\n",
224 prop->name, config);
225 ret = -EINVAL;
226 goto err;
227 }
228
229 /* Parse the node */
230 ret = dt_to_map_one_config(p, statename, np_config);
231 of_node_put(np_config);
232 if (ret < 0)
233 goto err;
234 }
235
236 /* No entries in DT? Generate a dummy state table entry */
237 if (!size) {
238 ret = dt_remember_dummy_state(p, statename);
239 if (ret < 0)
240 goto err;
241 }
242 }
243
244 return 0;
245
246err:
247 pinctrl_dt_free_maps(p);
248 return ret;
249}
diff --git a/drivers/pinctrl/devicetree.h b/drivers/pinctrl/devicetree.h
new file mode 100644
index 00000000000..760bc4960f5
--- /dev/null
+++ b/drivers/pinctrl/devicetree.h
@@ -0,0 +1,35 @@
1/*
2 * Internal interface to pinctrl device tree integration
3 *
4 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#ifdef CONFIG_OF
20
21void pinctrl_dt_free_maps(struct pinctrl *p);
22int pinctrl_dt_to_map(struct pinctrl *p);
23
24#else
25
26static inline int pinctrl_dt_to_map(struct pinctrl *p)
27{
28 return 0;
29}
30
31static inline void pinctrl_dt_free_maps(struct pinctrl *p)
32{
33}
34
35#endif
diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c
index 7321e860129..43f474cdc11 100644
--- a/drivers/pinctrl/pinconf.c
+++ b/drivers/pinctrl/pinconf.c
@@ -28,11 +28,17 @@ int pinconf_check_ops(struct pinctrl_dev *pctldev)
28 const struct pinconf_ops *ops = pctldev->desc->confops; 28 const struct pinconf_ops *ops = pctldev->desc->confops;
29 29
30 /* We must be able to read out pin status */ 30 /* We must be able to read out pin status */
31 if (!ops->pin_config_get && !ops->pin_config_group_get) 31 if (!ops->pin_config_get && !ops->pin_config_group_get) {
32 dev_err(pctldev->dev,
33 "pinconf must be able to read out pin status\n");
32 return -EINVAL; 34 return -EINVAL;
35 }
33 /* We have to be able to config the pins in SOME way */ 36 /* We have to be able to config the pins in SOME way */
34 if (!ops->pin_config_set && !ops->pin_config_group_set) 37 if (!ops->pin_config_set && !ops->pin_config_group_set) {
38 dev_err(pctldev->dev,
39 "pinconf has to be able to set a pins config\n");
35 return -EINVAL; 40 return -EINVAL;
41 }
36 return 0; 42 return 0;
37} 43}
38 44
@@ -44,9 +50,9 @@ int pinconf_validate_map(struct pinctrl_map const *map, int i)
44 return -EINVAL; 50 return -EINVAL;
45 } 51 }
46 52
47 if (map->data.configs.num_configs && 53 if (!map->data.configs.num_configs ||
48 !map->data.configs.configs) { 54 !map->data.configs.configs) {
49 pr_err("failed to register map %s (%d): no configs ptr given\n", 55 pr_err("failed to register map %s (%d): no configs given\n",
50 map->name, i); 56 map->name, i);
51 return -EINVAL; 57 return -EINVAL;
52 } 58 }
@@ -379,8 +385,16 @@ int pinconf_apply_setting(struct pinctrl_setting const *setting)
379 385
380void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map) 386void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map)
381{ 387{
388 struct pinctrl_dev *pctldev;
389 const struct pinconf_ops *confops;
382 int i; 390 int i;
383 391
392 pctldev = get_pinctrl_dev_from_devname(map->ctrl_dev_name);
393 if (pctldev)
394 confops = pctldev->desc->confops;
395 else
396 confops = NULL;
397
384 switch (map->type) { 398 switch (map->type) {
385 case PIN_MAP_TYPE_CONFIGS_PIN: 399 case PIN_MAP_TYPE_CONFIGS_PIN:
386 seq_printf(s, "pin "); 400 seq_printf(s, "pin ");
@@ -394,8 +408,15 @@ void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map)
394 408
395 seq_printf(s, "%s\n", map->data.configs.group_or_pin); 409 seq_printf(s, "%s\n", map->data.configs.group_or_pin);
396 410
397 for (i = 0; i < map->data.configs.num_configs; i++) 411 for (i = 0; i < map->data.configs.num_configs; i++) {
398 seq_printf(s, "config %08lx\n", map->data.configs.configs[i]); 412 seq_printf(s, "config ");
413 if (confops && confops->pin_config_config_dbg_show)
414 confops->pin_config_config_dbg_show(pctldev, s,
415 map->data.configs.configs[i]);
416 else
417 seq_printf(s, "%08lx", map->data.configs.configs[i]);
418 seq_printf(s, "\n");
419 }
399} 420}
400 421
401void pinconf_show_setting(struct seq_file *s, 422void pinconf_show_setting(struct seq_file *s,
@@ -403,6 +424,7 @@ void pinconf_show_setting(struct seq_file *s,
403{ 424{
404 struct pinctrl_dev *pctldev = setting->pctldev; 425 struct pinctrl_dev *pctldev = setting->pctldev;
405 const struct pinctrl_ops *pctlops = pctldev->desc->pctlops; 426 const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
427 const struct pinconf_ops *confops = pctldev->desc->confops;
406 struct pin_desc *desc; 428 struct pin_desc *desc;
407 int i; 429 int i;
408 430
@@ -428,8 +450,15 @@ void pinconf_show_setting(struct seq_file *s,
428 * FIXME: We should really get the pin controler to dump the config 450 * FIXME: We should really get the pin controler to dump the config
429 * values, so they can be decoded to something meaningful. 451 * values, so they can be decoded to something meaningful.
430 */ 452 */
431 for (i = 0; i < setting->data.configs.num_configs; i++) 453 for (i = 0; i < setting->data.configs.num_configs; i++) {
432 seq_printf(s, " %08lx", setting->data.configs.configs[i]); 454 seq_printf(s, " ");
455 if (confops && confops->pin_config_config_dbg_show)
456 confops->pin_config_config_dbg_show(pctldev, s,
457 setting->data.configs.configs[i]);
458 else
459 seq_printf(s, "%08lx",
460 setting->data.configs.configs[i]);
461 }
433 462
434 seq_printf(s, "\n"); 463 seq_printf(s, "\n");
435} 464}
@@ -448,10 +477,14 @@ static void pinconf_dump_pin(struct pinctrl_dev *pctldev,
448static int pinconf_pins_show(struct seq_file *s, void *what) 477static int pinconf_pins_show(struct seq_file *s, void *what)
449{ 478{
450 struct pinctrl_dev *pctldev = s->private; 479 struct pinctrl_dev *pctldev = s->private;
480 const struct pinconf_ops *ops = pctldev->desc->confops;
451 unsigned i, pin; 481 unsigned i, pin;
452 482
483 if (!ops || !ops->pin_config_get)
484 return 0;
485
453 seq_puts(s, "Pin config settings per pin\n"); 486 seq_puts(s, "Pin config settings per pin\n");
454 seq_puts(s, "Format: pin (name): pinmux setting array\n"); 487 seq_puts(s, "Format: pin (name): configs\n");
455 488
456 mutex_lock(&pinctrl_mutex); 489 mutex_lock(&pinctrl_mutex);
457 490
@@ -495,17 +528,18 @@ static int pinconf_groups_show(struct seq_file *s, void *what)
495 struct pinctrl_dev *pctldev = s->private; 528 struct pinctrl_dev *pctldev = s->private;
496 const struct pinctrl_ops *pctlops = pctldev->desc->pctlops; 529 const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
497 const struct pinconf_ops *ops = pctldev->desc->confops; 530 const struct pinconf_ops *ops = pctldev->desc->confops;
531 unsigned ngroups = pctlops->get_groups_count(pctldev);
498 unsigned selector = 0; 532 unsigned selector = 0;
499 533
500 if (!ops || !ops->pin_config_group_get) 534 if (!ops || !ops->pin_config_group_get)
501 return 0; 535 return 0;
502 536
503 seq_puts(s, "Pin config settings per pin group\n"); 537 seq_puts(s, "Pin config settings per pin group\n");
504 seq_puts(s, "Format: group (name): pinmux setting array\n"); 538 seq_puts(s, "Format: group (name): configs\n");
505 539
506 mutex_lock(&pinctrl_mutex); 540 mutex_lock(&pinctrl_mutex);
507 541
508 while (pctlops->list_groups(pctldev, selector) >= 0) { 542 while (selector < ngroups) {
509 const char *gname = pctlops->get_group_name(pctldev, selector); 543 const char *gname = pctlops->get_group_name(pctldev, selector);
510 544
511 seq_printf(s, "%u (%s):", selector, gname); 545 seq_printf(s, "%u (%s):", selector, gname);
diff --git a/drivers/pinctrl/pinconf.h b/drivers/pinctrl/pinconf.h
index 54510de5e8c..e3ed8cb072a 100644
--- a/drivers/pinctrl/pinconf.h
+++ b/drivers/pinctrl/pinconf.h
@@ -19,11 +19,6 @@ int pinconf_map_to_setting(struct pinctrl_map const *map,
19 struct pinctrl_setting *setting); 19 struct pinctrl_setting *setting);
20void pinconf_free_setting(struct pinctrl_setting const *setting); 20void pinconf_free_setting(struct pinctrl_setting const *setting);
21int pinconf_apply_setting(struct pinctrl_setting const *setting); 21int pinconf_apply_setting(struct pinctrl_setting const *setting);
22void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map);
23void pinconf_show_setting(struct seq_file *s,
24 struct pinctrl_setting const *setting);
25void pinconf_init_device_debugfs(struct dentry *devroot,
26 struct pinctrl_dev *pctldev);
27 22
28/* 23/*
29 * You will only be interested in these if you're using PINCONF 24 * You will only be interested in these if you're using PINCONF
@@ -61,6 +56,18 @@ static inline int pinconf_apply_setting(struct pinctrl_setting const *setting)
61 return 0; 56 return 0;
62} 57}
63 58
59#endif
60
61#if defined(CONFIG_PINCONF) && defined(CONFIG_DEBUG_FS)
62
63void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map);
64void pinconf_show_setting(struct seq_file *s,
65 struct pinctrl_setting const *setting);
66void pinconf_init_device_debugfs(struct dentry *devroot,
67 struct pinctrl_dev *pctldev);
68
69#else
70
64static inline void pinconf_show_map(struct seq_file *s, 71static inline void pinconf_show_map(struct seq_file *s,
65 struct pinctrl_map const *map) 72 struct pinctrl_map const *map)
66{ 73{
diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c
index 0797eba3e33..55697a5d748 100644
--- a/drivers/pinctrl/pinctrl-coh901.c
+++ b/drivers/pinctrl/pinctrl-coh901.c
@@ -174,7 +174,7 @@ struct u300_gpio_confdata {
174 174
175 175
176/* Initial configuration */ 176/* Initial configuration */
177static const struct __initdata u300_gpio_confdata 177static const struct __initconst u300_gpio_confdata
178bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = { 178bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
179 /* Port 0, pins 0-7 */ 179 /* Port 0, pins 0-7 */
180 { 180 {
@@ -255,7 +255,7 @@ bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
255 } 255 }
256}; 256};
257 257
258static const struct __initdata u300_gpio_confdata 258static const struct __initconst u300_gpio_confdata
259bs365_gpio_config[BS365_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = { 259bs365_gpio_config[BS365_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
260 /* Port 0, pins 0-7 */ 260 /* Port 0, pins 0-7 */
261 { 261 {
diff --git a/drivers/pinctrl/pinctrl-imx.c b/drivers/pinctrl/pinctrl-imx.c
new file mode 100644
index 00000000000..f6e7c670906
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx.c
@@ -0,0 +1,620 @@
1/*
2 * Core driver for the imx pin controller
3 *
4 * Copyright (C) 2012 Freescale Semiconductor, Inc.
5 * Copyright (C) 2012 Linaro Ltd.
6 *
7 * Author: Dong Aisheng <dong.aisheng@linaro.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#include <linux/err.h>
16#include <linux/init.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/pinctrl/machine.h>
22#include <linux/pinctrl/pinconf.h>
23#include <linux/pinctrl/pinctrl.h>
24#include <linux/pinctrl/pinmux.h>
25#include <linux/slab.h>
26
27#include "core.h"
28#include "pinctrl-imx.h"
29
30#define IMX_PMX_DUMP(info, p, m, c, n) \
31{ \
32 int i, j; \
33 printk("Format: Pin Mux Config\n"); \
34 for (i = 0; i < n; i++) { \
35 j = p[i]; \
36 printk("%s %d 0x%lx\n", \
37 info->pins[j].name, \
38 m[i], c[i]); \
39 } \
40}
41
42/* The bits in CONFIG cell defined in binding doc*/
43#define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */
44#define IMX_PAD_SION 0x40000000 /* set SION */
45
46/**
47 * @dev: a pointer back to containing device
48 * @base: the offset to the controller in virtual memory
49 */
50struct imx_pinctrl {
51 struct device *dev;
52 struct pinctrl_dev *pctl;
53 void __iomem *base;
54 const struct imx_pinctrl_soc_info *info;
55};
56
57static const struct imx_pin_reg *imx_find_pin_reg(
58 const struct imx_pinctrl_soc_info *info,
59 unsigned pin, bool is_mux, unsigned mux)
60{
61 const struct imx_pin_reg *pin_reg = NULL;
62 int i;
63
64 for (i = 0; i < info->npin_regs; i++) {
65 pin_reg = &info->pin_regs[i];
66 if (pin_reg->pid != pin)
67 continue;
68 if (!is_mux)
69 break;
70 else if (pin_reg->mux_mode == (mux & IMX_MUX_MASK))
71 break;
72 }
73
74 if (!pin_reg) {
75 dev_err(info->dev, "Pin(%s): unable to find pin reg map\n",
76 info->pins[pin].name);
77 return NULL;
78 }
79
80 return pin_reg;
81}
82
83static const inline struct imx_pin_group *imx_pinctrl_find_group_by_name(
84 const struct imx_pinctrl_soc_info *info,
85 const char *name)
86{
87 const struct imx_pin_group *grp = NULL;
88 int i;
89
90 for (i = 0; i < info->ngroups; i++) {
91 if (!strcmp(info->groups[i].name, name)) {
92 grp = &info->groups[i];
93 break;
94 }
95 }
96
97 return grp;
98}
99
100static int imx_get_groups_count(struct pinctrl_dev *pctldev)
101{
102 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
103 const struct imx_pinctrl_soc_info *info = ipctl->info;
104
105 return info->ngroups;
106}
107
108static const char *imx_get_group_name(struct pinctrl_dev *pctldev,
109 unsigned selector)
110{
111 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
112 const struct imx_pinctrl_soc_info *info = ipctl->info;
113
114 return info->groups[selector].name;
115}
116
117static int imx_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
118 const unsigned **pins,
119 unsigned *npins)
120{
121 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
122 const struct imx_pinctrl_soc_info *info = ipctl->info;
123
124 if (selector >= info->ngroups)
125 return -EINVAL;
126
127 *pins = info->groups[selector].pins;
128 *npins = info->groups[selector].npins;
129
130 return 0;
131}
132
133static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
134 unsigned offset)
135{
136 seq_printf(s, "%s", dev_name(pctldev->dev));
137}
138
139static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
140 struct device_node *np,
141 struct pinctrl_map **map, unsigned *num_maps)
142{
143 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
144 const struct imx_pinctrl_soc_info *info = ipctl->info;
145 const struct imx_pin_group *grp;
146 struct pinctrl_map *new_map;
147 struct device_node *parent;
148 int map_num = 1;
149 int i;
150
151 /*
152 * first find the group of this node and check if we need create
153 * config maps for pins
154 */
155 grp = imx_pinctrl_find_group_by_name(info, np->name);
156 if (!grp) {
157 dev_err(info->dev, "unable to find group for node %s\n",
158 np->name);
159 return -EINVAL;
160 }
161
162 for (i = 0; i < grp->npins; i++) {
163 if (!(grp->configs[i] & IMX_NO_PAD_CTL))
164 map_num++;
165 }
166
167 new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL);
168 if (!new_map)
169 return -ENOMEM;
170
171 *map = new_map;
172 *num_maps = map_num;
173
174 /* create mux map */
175 parent = of_get_parent(np);
176 if (!parent)
177 return -EINVAL;
178 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
179 new_map[0].data.mux.function = parent->name;
180 new_map[0].data.mux.group = np->name;
181 of_node_put(parent);
182
183 /* create config map */
184 new_map++;
185 for (i = 0; i < grp->npins; i++) {
186 if (!(grp->configs[i] & IMX_NO_PAD_CTL)) {
187 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
188 new_map[i].data.configs.group_or_pin =
189 pin_get_name(pctldev, grp->pins[i]);
190 new_map[i].data.configs.configs = &grp->configs[i];
191 new_map[i].data.configs.num_configs = 1;
192 }
193 }
194
195 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
196 new_map->data.mux.function, new_map->data.mux.group, map_num);
197
198 return 0;
199}
200
201static void imx_dt_free_map(struct pinctrl_dev *pctldev,
202 struct pinctrl_map *map, unsigned num_maps)
203{
204 int i;
205
206 for (i = 0; i < num_maps; i++)
207 kfree(map);
208}
209
210static struct pinctrl_ops imx_pctrl_ops = {
211 .get_groups_count = imx_get_groups_count,
212 .get_group_name = imx_get_group_name,
213 .get_group_pins = imx_get_group_pins,
214 .pin_dbg_show = imx_pin_dbg_show,
215 .dt_node_to_map = imx_dt_node_to_map,
216 .dt_free_map = imx_dt_free_map,
217
218};
219
220static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
221 unsigned group)
222{
223 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
224 const struct imx_pinctrl_soc_info *info = ipctl->info;
225 const struct imx_pin_reg *pin_reg;
226 const unsigned *pins, *mux;
227 unsigned int npins, pin_id;
228 int i;
229
230 /*
231 * Configure the mux mode for each pin in the group for a specific
232 * function.
233 */
234 pins = info->groups[group].pins;
235 npins = info->groups[group].npins;
236 mux = info->groups[group].mux_mode;
237
238 WARN_ON(!pins || !npins || !mux);
239
240 dev_dbg(ipctl->dev, "enable function %s group %s\n",
241 info->functions[selector].name, info->groups[group].name);
242
243 for (i = 0; i < npins; i++) {
244 pin_id = pins[i];
245
246 pin_reg = imx_find_pin_reg(info, pin_id, 1, mux[i]);
247 if (!pin_reg)
248 return -EINVAL;
249
250 if (!pin_reg->mux_reg) {
251 dev_err(ipctl->dev, "Pin(%s) does not support mux function\n",
252 info->pins[pin_id].name);
253 return -EINVAL;
254 }
255
256 writel(mux[i], ipctl->base + pin_reg->mux_reg);
257 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
258 pin_reg->mux_reg, mux[i]);
259
260 /* some pins also need select input setting, set it if found */
261 if (pin_reg->input_reg) {
262 writel(pin_reg->input_val, ipctl->base + pin_reg->input_reg);
263 dev_dbg(ipctl->dev,
264 "==>select_input: offset 0x%x val 0x%x\n",
265 pin_reg->input_reg, pin_reg->input_val);
266 }
267 }
268
269 return 0;
270}
271
272static int imx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
273{
274 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
275 const struct imx_pinctrl_soc_info *info = ipctl->info;
276
277 return info->nfunctions;
278}
279
280static const char *imx_pmx_get_func_name(struct pinctrl_dev *pctldev,
281 unsigned selector)
282{
283 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
284 const struct imx_pinctrl_soc_info *info = ipctl->info;
285
286 return info->functions[selector].name;
287}
288
289static int imx_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
290 const char * const **groups,
291 unsigned * const num_groups)
292{
293 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
294 const struct imx_pinctrl_soc_info *info = ipctl->info;
295
296 *groups = info->functions[selector].groups;
297 *num_groups = info->functions[selector].num_groups;
298
299 return 0;
300}
301
302static struct pinmux_ops imx_pmx_ops = {
303 .get_functions_count = imx_pmx_get_funcs_count,
304 .get_function_name = imx_pmx_get_func_name,
305 .get_function_groups = imx_pmx_get_groups,
306 .enable = imx_pmx_enable,
307};
308
309static int imx_pinconf_get(struct pinctrl_dev *pctldev,
310 unsigned pin_id, unsigned long *config)
311{
312 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
313 const struct imx_pinctrl_soc_info *info = ipctl->info;
314 const struct imx_pin_reg *pin_reg;
315
316 pin_reg = imx_find_pin_reg(info, pin_id, 0, 0);
317 if (!pin_reg)
318 return -EINVAL;
319
320 if (!pin_reg->conf_reg) {
321 dev_err(info->dev, "Pin(%s) does not support config function\n",
322 info->pins[pin_id].name);
323 return -EINVAL;
324 }
325
326 *config = readl(ipctl->base + pin_reg->conf_reg);
327
328 return 0;
329}
330
331static int imx_pinconf_set(struct pinctrl_dev *pctldev,
332 unsigned pin_id, unsigned long config)
333{
334 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
335 const struct imx_pinctrl_soc_info *info = ipctl->info;
336 const struct imx_pin_reg *pin_reg;
337
338 pin_reg = imx_find_pin_reg(info, pin_id, 0, 0);
339 if (!pin_reg)
340 return -EINVAL;
341
342 if (!pin_reg->conf_reg) {
343 dev_err(info->dev, "Pin(%s) does not support config function\n",
344 info->pins[pin_id].name);
345 return -EINVAL;
346 }
347
348 dev_dbg(ipctl->dev, "pinconf set pin %s\n",
349 info->pins[pin_id].name);
350
351 writel(config, ipctl->base + pin_reg->conf_reg);
352 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
353 pin_reg->conf_reg, config);
354
355 return 0;
356}
357
358static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
359 struct seq_file *s, unsigned pin_id)
360{
361 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
362 const struct imx_pinctrl_soc_info *info = ipctl->info;
363 const struct imx_pin_reg *pin_reg;
364 unsigned long config;
365
366 pin_reg = imx_find_pin_reg(info, pin_id, 0, 0);
367 if (!pin_reg || !pin_reg->conf_reg) {
368 seq_printf(s, "N/A");
369 return;
370 }
371
372 config = readl(ipctl->base + pin_reg->conf_reg);
373 seq_printf(s, "0x%lx", config);
374}
375
376static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
377 struct seq_file *s, unsigned group)
378{
379 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
380 const struct imx_pinctrl_soc_info *info = ipctl->info;
381 struct imx_pin_group *grp;
382 unsigned long config;
383 const char *name;
384 int i, ret;
385
386 if (group > info->ngroups)
387 return;
388
389 seq_printf(s, "\n");
390 grp = &info->groups[group];
391 for (i = 0; i < grp->npins; i++) {
392 name = pin_get_name(pctldev, grp->pins[i]);
393 ret = imx_pinconf_get(pctldev, grp->pins[i], &config);
394 if (ret)
395 return;
396 seq_printf(s, "%s: 0x%lx", name, config);
397 }
398}
399
400struct pinconf_ops imx_pinconf_ops = {
401 .pin_config_get = imx_pinconf_get,
402 .pin_config_set = imx_pinconf_set,
403 .pin_config_dbg_show = imx_pinconf_dbg_show,
404 .pin_config_group_dbg_show = imx_pinconf_group_dbg_show,
405};
406
407static struct pinctrl_desc imx_pinctrl_desc = {
408 .pctlops = &imx_pctrl_ops,
409 .pmxops = &imx_pmx_ops,
410 .confops = &imx_pinconf_ops,
411 .owner = THIS_MODULE,
412};
413
414/* decode pin id and mux from pin function id got from device tree*/
415static int imx_pinctrl_get_pin_id_and_mux(const struct imx_pinctrl_soc_info *info,
416 unsigned int pin_func_id, unsigned int *pin_id,
417 unsigned int *mux)
418{
419 if (pin_func_id > info->npin_regs)
420 return -EINVAL;
421
422 *pin_id = info->pin_regs[pin_func_id].pid;
423 *mux = info->pin_regs[pin_func_id].mux_mode;
424
425 return 0;
426}
427
428static int __devinit imx_pinctrl_parse_groups(struct device_node *np,
429 struct imx_pin_group *grp,
430 struct imx_pinctrl_soc_info *info,
431 u32 index)
432{
433 unsigned int pin_func_id;
434 int ret, size;
435 const const __be32 *list;
436 int i, j;
437 u32 config;
438
439 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
440
441 /* Initialise group */
442 grp->name = np->name;
443
444 /*
445 * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>,
446 * do sanity check and calculate pins number
447 */
448 list = of_get_property(np, "fsl,pins", &size);
449 /* we do not check return since it's safe node passed down */
450 size /= sizeof(*list);
451 if (!size || size % 2) {
452 dev_err(info->dev, "wrong pins number or pins and configs should be pairs\n");
453 return -EINVAL;
454 }
455
456 grp->npins = size / 2;
457 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
458 GFP_KERNEL);
459 grp->mux_mode = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
460 GFP_KERNEL);
461 grp->configs = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned long),
462 GFP_KERNEL);
463 for (i = 0, j = 0; i < size; i += 2, j++) {
464 pin_func_id = be32_to_cpu(*list++);
465 ret = imx_pinctrl_get_pin_id_and_mux(info, pin_func_id,
466 &grp->pins[j], &grp->mux_mode[j]);
467 if (ret) {
468 dev_err(info->dev, "get invalid pin function id\n");
469 return -EINVAL;
470 }
471 /* SION bit is in mux register */
472 config = be32_to_cpu(*list++);
473 if (config & IMX_PAD_SION)
474 grp->mux_mode[j] |= IOMUXC_CONFIG_SION;
475 grp->configs[j] = config & ~IMX_PAD_SION;
476 }
477
478#ifdef DEBUG
479 IMX_PMX_DUMP(info, grp->pins, grp->mux_mode, grp->configs, grp->npins);
480#endif
481 return 0;
482}
483
484static int __devinit imx_pinctrl_parse_functions(struct device_node *np,
485 struct imx_pinctrl_soc_info *info, u32 index)
486{
487 struct device_node *child;
488 struct imx_pmx_func *func;
489 struct imx_pin_group *grp;
490 int ret;
491 static u32 grp_index;
492 u32 i = 0;
493
494 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
495
496 func = &info->functions[index];
497
498 /* Initialise function */
499 func->name = np->name;
500 func->num_groups = of_get_child_count(np);
501 if (func->num_groups <= 0) {
502 dev_err(info->dev, "no groups defined\n");
503 return -EINVAL;
504 }
505 func->groups = devm_kzalloc(info->dev,
506 func->num_groups * sizeof(char *), GFP_KERNEL);
507
508 for_each_child_of_node(np, child) {
509 func->groups[i] = child->name;
510 grp = &info->groups[grp_index++];
511 ret = imx_pinctrl_parse_groups(child, grp, info, i++);
512 if (ret)
513 return ret;
514 }
515
516 return 0;
517}
518
519static int __devinit imx_pinctrl_probe_dt(struct platform_device *pdev,
520 struct imx_pinctrl_soc_info *info)
521{
522 struct device_node *np = pdev->dev.of_node;
523 struct device_node *child;
524 int ret;
525 u32 nfuncs = 0;
526 u32 i = 0;
527
528 if (!np)
529 return -ENODEV;
530
531 nfuncs = of_get_child_count(np);
532 if (nfuncs <= 0) {
533 dev_err(&pdev->dev, "no functions defined\n");
534 return -EINVAL;
535 }
536
537 info->nfunctions = nfuncs;
538 info->functions = devm_kzalloc(&pdev->dev, nfuncs * sizeof(struct imx_pmx_func),
539 GFP_KERNEL);
540 if (!info->functions)
541 return -ENOMEM;
542
543 info->ngroups = 0;
544 for_each_child_of_node(np, child)
545 info->ngroups += of_get_child_count(child);
546 info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct imx_pin_group),
547 GFP_KERNEL);
548 if (!info->groups)
549 return -ENOMEM;
550
551 for_each_child_of_node(np, child) {
552 ret = imx_pinctrl_parse_functions(child, info, i++);
553 if (ret) {
554 dev_err(&pdev->dev, "failed to parse function\n");
555 return ret;
556 }
557 }
558
559 return 0;
560}
561
562int __devinit imx_pinctrl_probe(struct platform_device *pdev,
563 struct imx_pinctrl_soc_info *info)
564{
565 struct imx_pinctrl *ipctl;
566 struct resource *res;
567 int ret;
568
569 if (!info || !info->pins || !info->npins
570 || !info->pin_regs || !info->npin_regs) {
571 dev_err(&pdev->dev, "wrong pinctrl info\n");
572 return -EINVAL;
573 }
574 info->dev = &pdev->dev;
575
576 /* Create state holders etc for this driver */
577 ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
578 if (!ipctl)
579 return -ENOMEM;
580
581 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
582 if (!res)
583 return -ENOENT;
584
585 ipctl->base = devm_request_and_ioremap(&pdev->dev, res);
586 if (!ipctl->base)
587 return -EBUSY;
588
589 imx_pinctrl_desc.name = dev_name(&pdev->dev);
590 imx_pinctrl_desc.pins = info->pins;
591 imx_pinctrl_desc.npins = info->npins;
592
593 ret = imx_pinctrl_probe_dt(pdev, info);
594 if (ret) {
595 dev_err(&pdev->dev, "fail to probe dt properties\n");
596 return ret;
597 }
598
599 ipctl->info = info;
600 ipctl->dev = info->dev;
601 platform_set_drvdata(pdev, ipctl);
602 ipctl->pctl = pinctrl_register(&imx_pinctrl_desc, &pdev->dev, ipctl);
603 if (!ipctl->pctl) {
604 dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
605 return -EINVAL;
606 }
607
608 dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
609
610 return 0;
611}
612
613int __devexit imx_pinctrl_remove(struct platform_device *pdev)
614{
615 struct imx_pinctrl *ipctl = platform_get_drvdata(pdev);
616
617 pinctrl_unregister(ipctl->pctl);
618
619 return 0;
620}
diff --git a/drivers/pinctrl/pinctrl-imx.h b/drivers/pinctrl/pinctrl-imx.h
new file mode 100644
index 00000000000..9b65e7828f1
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx.h
@@ -0,0 +1,106 @@
1/*
2 * IMX pinmux core definitions
3 *
4 * Copyright (C) 2012 Freescale Semiconductor, Inc.
5 * Copyright (C) 2012 Linaro Ltd.
6 *
7 * Author: Dong Aisheng <dong.aisheng@linaro.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef __DRIVERS_PINCTRL_IMX_H
16#define __DRIVERS_PINCTRL_IMX_H
17
18struct platform_device;
19
20/**
21 * struct imx_pin_group - describes an IMX pin group
22 * @name: the name of this specific pin group
23 * @pins: an array of discrete physical pins used in this group, taken
24 * from the driver-local pin enumeration space
25 * @npins: the number of pins in this group array, i.e. the number of
26 * elements in .pins so we can iterate over that array
27 * @mux_mode: the mux mode for each pin in this group. The size of this
28 * array is the same as pins.
29 * @configs: the config for each pin in this group. The size of this
30 * array is the same as pins.
31 */
32struct imx_pin_group {
33 const char *name;
34 unsigned int *pins;
35 unsigned npins;
36 unsigned int *mux_mode;
37 unsigned long *configs;
38};
39
40/**
41 * struct imx_pmx_func - describes IMX pinmux functions
42 * @name: the name of this specific function
43 * @groups: corresponding pin groups
44 * @num_groups: the number of groups
45 */
46struct imx_pmx_func {
47 const char *name;
48 const char **groups;
49 unsigned num_groups;
50};
51
52/**
53 * struct imx_pin_reg - describe a pin reg map
54 * The last 3 members are used for select input setting
55 * @pid: pin id
56 * @mux_reg: mux register offset
57 * @conf_reg: config register offset
58 * @mux_mode: mux mode
59 * @input_reg: select input register offset for this mux if any
60 * 0 if no select input setting needed.
61 * @input_val: the value set to select input register
62 */
63struct imx_pin_reg {
64 u16 pid;
65 u16 mux_reg;
66 u16 conf_reg;
67 u8 mux_mode;
68 u16 input_reg;
69 u8 input_val;
70};
71
72struct imx_pinctrl_soc_info {
73 struct device *dev;
74 const struct pinctrl_pin_desc *pins;
75 unsigned int npins;
76 const struct imx_pin_reg *pin_regs;
77 unsigned int npin_regs;
78 struct imx_pin_group *groups;
79 unsigned int ngroups;
80 struct imx_pmx_func *functions;
81 unsigned int nfunctions;
82};
83
84#define NO_MUX 0x0
85#define NO_PAD 0x0
86
87#define IMX_PIN_REG(id, conf, mux, mode, input, val) \
88 { \
89 .pid = id, \
90 .conf_reg = conf, \
91 .mux_reg = mux, \
92 .mux_mode = mode, \
93 .input_reg = input, \
94 .input_val = val, \
95 }
96
97#define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
98
99#define PAD_CTL_MASK(len) ((1 << len) - 1)
100#define IMX_MUX_MASK 0x7
101#define IOMUXC_CONFIG_SION (0x1 << 4)
102
103int imx_pinctrl_probe(struct platform_device *pdev,
104 struct imx_pinctrl_soc_info *info);
105int imx_pinctrl_remove(struct platform_device *pdev);
106#endif /* __DRIVERS_PINCTRL_IMX_H */
diff --git a/drivers/pinctrl/pinctrl-imx23.c b/drivers/pinctrl/pinctrl-imx23.c
new file mode 100644
index 00000000000..75d3eff9429
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx23.c
@@ -0,0 +1,305 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/of_device.h>
15#include <linux/pinctrl/pinctrl.h>
16#include "pinctrl-mxs.h"
17
18enum imx23_pin_enum {
19 GPMI_D00 = PINID(0, 0),
20 GPMI_D01 = PINID(0, 1),
21 GPMI_D02 = PINID(0, 2),
22 GPMI_D03 = PINID(0, 3),
23 GPMI_D04 = PINID(0, 4),
24 GPMI_D05 = PINID(0, 5),
25 GPMI_D06 = PINID(0, 6),
26 GPMI_D07 = PINID(0, 7),
27 GPMI_D08 = PINID(0, 8),
28 GPMI_D09 = PINID(0, 9),
29 GPMI_D10 = PINID(0, 10),
30 GPMI_D11 = PINID(0, 11),
31 GPMI_D12 = PINID(0, 12),
32 GPMI_D13 = PINID(0, 13),
33 GPMI_D14 = PINID(0, 14),
34 GPMI_D15 = PINID(0, 15),
35 GPMI_CLE = PINID(0, 16),
36 GPMI_ALE = PINID(0, 17),
37 GPMI_CE2N = PINID(0, 18),
38 GPMI_RDY0 = PINID(0, 19),
39 GPMI_RDY1 = PINID(0, 20),
40 GPMI_RDY2 = PINID(0, 21),
41 GPMI_RDY3 = PINID(0, 22),
42 GPMI_WPN = PINID(0, 23),
43 GPMI_WRN = PINID(0, 24),
44 GPMI_RDN = PINID(0, 25),
45 AUART1_CTS = PINID(0, 26),
46 AUART1_RTS = PINID(0, 27),
47 AUART1_RX = PINID(0, 28),
48 AUART1_TX = PINID(0, 29),
49 I2C_SCL = PINID(0, 30),
50 I2C_SDA = PINID(0, 31),
51 LCD_D00 = PINID(1, 0),
52 LCD_D01 = PINID(1, 1),
53 LCD_D02 = PINID(1, 2),
54 LCD_D03 = PINID(1, 3),
55 LCD_D04 = PINID(1, 4),
56 LCD_D05 = PINID(1, 5),
57 LCD_D06 = PINID(1, 6),
58 LCD_D07 = PINID(1, 7),
59 LCD_D08 = PINID(1, 8),
60 LCD_D09 = PINID(1, 9),
61 LCD_D10 = PINID(1, 10),
62 LCD_D11 = PINID(1, 11),
63 LCD_D12 = PINID(1, 12),
64 LCD_D13 = PINID(1, 13),
65 LCD_D14 = PINID(1, 14),
66 LCD_D15 = PINID(1, 15),
67 LCD_D16 = PINID(1, 16),
68 LCD_D17 = PINID(1, 17),
69 LCD_RESET = PINID(1, 18),
70 LCD_RS = PINID(1, 19),
71 LCD_WR = PINID(1, 20),
72 LCD_CS = PINID(1, 21),
73 LCD_DOTCK = PINID(1, 22),
74 LCD_ENABLE = PINID(1, 23),
75 LCD_HSYNC = PINID(1, 24),
76 LCD_VSYNC = PINID(1, 25),
77 PWM0 = PINID(1, 26),
78 PWM1 = PINID(1, 27),
79 PWM2 = PINID(1, 28),
80 PWM3 = PINID(1, 29),
81 PWM4 = PINID(1, 30),
82 SSP1_CMD = PINID(2, 0),
83 SSP1_DETECT = PINID(2, 1),
84 SSP1_DATA0 = PINID(2, 2),
85 SSP1_DATA1 = PINID(2, 3),
86 SSP1_DATA2 = PINID(2, 4),
87 SSP1_DATA3 = PINID(2, 5),
88 SSP1_SCK = PINID(2, 6),
89 ROTARYA = PINID(2, 7),
90 ROTARYB = PINID(2, 8),
91 EMI_A00 = PINID(2, 9),
92 EMI_A01 = PINID(2, 10),
93 EMI_A02 = PINID(2, 11),
94 EMI_A03 = PINID(2, 12),
95 EMI_A04 = PINID(2, 13),
96 EMI_A05 = PINID(2, 14),
97 EMI_A06 = PINID(2, 15),
98 EMI_A07 = PINID(2, 16),
99 EMI_A08 = PINID(2, 17),
100 EMI_A09 = PINID(2, 18),
101 EMI_A10 = PINID(2, 19),
102 EMI_A11 = PINID(2, 20),
103 EMI_A12 = PINID(2, 21),
104 EMI_BA0 = PINID(2, 22),
105 EMI_BA1 = PINID(2, 23),
106 EMI_CASN = PINID(2, 24),
107 EMI_CE0N = PINID(2, 25),
108 EMI_CE1N = PINID(2, 26),
109 GPMI_CE1N = PINID(2, 27),
110 GPMI_CE0N = PINID(2, 28),
111 EMI_CKE = PINID(2, 29),
112 EMI_RASN = PINID(2, 30),
113 EMI_WEN = PINID(2, 31),
114 EMI_D00 = PINID(3, 0),
115 EMI_D01 = PINID(3, 1),
116 EMI_D02 = PINID(3, 2),
117 EMI_D03 = PINID(3, 3),
118 EMI_D04 = PINID(3, 4),
119 EMI_D05 = PINID(3, 5),
120 EMI_D06 = PINID(3, 6),
121 EMI_D07 = PINID(3, 7),
122 EMI_D08 = PINID(3, 8),
123 EMI_D09 = PINID(3, 9),
124 EMI_D10 = PINID(3, 10),
125 EMI_D11 = PINID(3, 11),
126 EMI_D12 = PINID(3, 12),
127 EMI_D13 = PINID(3, 13),
128 EMI_D14 = PINID(3, 14),
129 EMI_D15 = PINID(3, 15),
130 EMI_DQM0 = PINID(3, 16),
131 EMI_DQM1 = PINID(3, 17),
132 EMI_DQS0 = PINID(3, 18),
133 EMI_DQS1 = PINID(3, 19),
134 EMI_CLK = PINID(3, 20),
135 EMI_CLKN = PINID(3, 21),
136};
137
138static const struct pinctrl_pin_desc imx23_pins[] = {
139 MXS_PINCTRL_PIN(GPMI_D00),
140 MXS_PINCTRL_PIN(GPMI_D01),
141 MXS_PINCTRL_PIN(GPMI_D02),
142 MXS_PINCTRL_PIN(GPMI_D03),
143 MXS_PINCTRL_PIN(GPMI_D04),
144 MXS_PINCTRL_PIN(GPMI_D05),
145 MXS_PINCTRL_PIN(GPMI_D06),
146 MXS_PINCTRL_PIN(GPMI_D07),
147 MXS_PINCTRL_PIN(GPMI_D08),
148 MXS_PINCTRL_PIN(GPMI_D09),
149 MXS_PINCTRL_PIN(GPMI_D10),
150 MXS_PINCTRL_PIN(GPMI_D11),
151 MXS_PINCTRL_PIN(GPMI_D12),
152 MXS_PINCTRL_PIN(GPMI_D13),
153 MXS_PINCTRL_PIN(GPMI_D14),
154 MXS_PINCTRL_PIN(GPMI_D15),
155 MXS_PINCTRL_PIN(GPMI_CLE),
156 MXS_PINCTRL_PIN(GPMI_ALE),
157 MXS_PINCTRL_PIN(GPMI_CE2N),
158 MXS_PINCTRL_PIN(GPMI_RDY0),
159 MXS_PINCTRL_PIN(GPMI_RDY1),
160 MXS_PINCTRL_PIN(GPMI_RDY2),
161 MXS_PINCTRL_PIN(GPMI_RDY3),
162 MXS_PINCTRL_PIN(GPMI_WPN),
163 MXS_PINCTRL_PIN(GPMI_WRN),
164 MXS_PINCTRL_PIN(GPMI_RDN),
165 MXS_PINCTRL_PIN(AUART1_CTS),
166 MXS_PINCTRL_PIN(AUART1_RTS),
167 MXS_PINCTRL_PIN(AUART1_RX),
168 MXS_PINCTRL_PIN(AUART1_TX),
169 MXS_PINCTRL_PIN(I2C_SCL),
170 MXS_PINCTRL_PIN(I2C_SDA),
171 MXS_PINCTRL_PIN(LCD_D00),
172 MXS_PINCTRL_PIN(LCD_D01),
173 MXS_PINCTRL_PIN(LCD_D02),
174 MXS_PINCTRL_PIN(LCD_D03),
175 MXS_PINCTRL_PIN(LCD_D04),
176 MXS_PINCTRL_PIN(LCD_D05),
177 MXS_PINCTRL_PIN(LCD_D06),
178 MXS_PINCTRL_PIN(LCD_D07),
179 MXS_PINCTRL_PIN(LCD_D08),
180 MXS_PINCTRL_PIN(LCD_D09),
181 MXS_PINCTRL_PIN(LCD_D10),
182 MXS_PINCTRL_PIN(LCD_D11),
183 MXS_PINCTRL_PIN(LCD_D12),
184 MXS_PINCTRL_PIN(LCD_D13),
185 MXS_PINCTRL_PIN(LCD_D14),
186 MXS_PINCTRL_PIN(LCD_D15),
187 MXS_PINCTRL_PIN(LCD_D16),
188 MXS_PINCTRL_PIN(LCD_D17),
189 MXS_PINCTRL_PIN(LCD_RESET),
190 MXS_PINCTRL_PIN(LCD_RS),
191 MXS_PINCTRL_PIN(LCD_WR),
192 MXS_PINCTRL_PIN(LCD_CS),
193 MXS_PINCTRL_PIN(LCD_DOTCK),
194 MXS_PINCTRL_PIN(LCD_ENABLE),
195 MXS_PINCTRL_PIN(LCD_HSYNC),
196 MXS_PINCTRL_PIN(LCD_VSYNC),
197 MXS_PINCTRL_PIN(PWM0),
198 MXS_PINCTRL_PIN(PWM1),
199 MXS_PINCTRL_PIN(PWM2),
200 MXS_PINCTRL_PIN(PWM3),
201 MXS_PINCTRL_PIN(PWM4),
202 MXS_PINCTRL_PIN(SSP1_CMD),
203 MXS_PINCTRL_PIN(SSP1_DETECT),
204 MXS_PINCTRL_PIN(SSP1_DATA0),
205 MXS_PINCTRL_PIN(SSP1_DATA1),
206 MXS_PINCTRL_PIN(SSP1_DATA2),
207 MXS_PINCTRL_PIN(SSP1_DATA3),
208 MXS_PINCTRL_PIN(SSP1_SCK),
209 MXS_PINCTRL_PIN(ROTARYA),
210 MXS_PINCTRL_PIN(ROTARYB),
211 MXS_PINCTRL_PIN(EMI_A00),
212 MXS_PINCTRL_PIN(EMI_A01),
213 MXS_PINCTRL_PIN(EMI_A02),
214 MXS_PINCTRL_PIN(EMI_A03),
215 MXS_PINCTRL_PIN(EMI_A04),
216 MXS_PINCTRL_PIN(EMI_A05),
217 MXS_PINCTRL_PIN(EMI_A06),
218 MXS_PINCTRL_PIN(EMI_A07),
219 MXS_PINCTRL_PIN(EMI_A08),
220 MXS_PINCTRL_PIN(EMI_A09),
221 MXS_PINCTRL_PIN(EMI_A10),
222 MXS_PINCTRL_PIN(EMI_A11),
223 MXS_PINCTRL_PIN(EMI_A12),
224 MXS_PINCTRL_PIN(EMI_BA0),
225 MXS_PINCTRL_PIN(EMI_BA1),
226 MXS_PINCTRL_PIN(EMI_CASN),
227 MXS_PINCTRL_PIN(EMI_CE0N),
228 MXS_PINCTRL_PIN(EMI_CE1N),
229 MXS_PINCTRL_PIN(GPMI_CE1N),
230 MXS_PINCTRL_PIN(GPMI_CE0N),
231 MXS_PINCTRL_PIN(EMI_CKE),
232 MXS_PINCTRL_PIN(EMI_RASN),
233 MXS_PINCTRL_PIN(EMI_WEN),
234 MXS_PINCTRL_PIN(EMI_D00),
235 MXS_PINCTRL_PIN(EMI_D01),
236 MXS_PINCTRL_PIN(EMI_D02),
237 MXS_PINCTRL_PIN(EMI_D03),
238 MXS_PINCTRL_PIN(EMI_D04),
239 MXS_PINCTRL_PIN(EMI_D05),
240 MXS_PINCTRL_PIN(EMI_D06),
241 MXS_PINCTRL_PIN(EMI_D07),
242 MXS_PINCTRL_PIN(EMI_D08),
243 MXS_PINCTRL_PIN(EMI_D09),
244 MXS_PINCTRL_PIN(EMI_D10),
245 MXS_PINCTRL_PIN(EMI_D11),
246 MXS_PINCTRL_PIN(EMI_D12),
247 MXS_PINCTRL_PIN(EMI_D13),
248 MXS_PINCTRL_PIN(EMI_D14),
249 MXS_PINCTRL_PIN(EMI_D15),
250 MXS_PINCTRL_PIN(EMI_DQM0),
251 MXS_PINCTRL_PIN(EMI_DQM1),
252 MXS_PINCTRL_PIN(EMI_DQS0),
253 MXS_PINCTRL_PIN(EMI_DQS1),
254 MXS_PINCTRL_PIN(EMI_CLK),
255 MXS_PINCTRL_PIN(EMI_CLKN),
256};
257
258static struct mxs_regs imx23_regs = {
259 .muxsel = 0x100,
260 .drive = 0x200,
261 .pull = 0x400,
262};
263
264static struct mxs_pinctrl_soc_data imx23_pinctrl_data = {
265 .regs = &imx23_regs,
266 .pins = imx23_pins,
267 .npins = ARRAY_SIZE(imx23_pins),
268};
269
270static int __devinit imx23_pinctrl_probe(struct platform_device *pdev)
271{
272 return mxs_pinctrl_probe(pdev, &imx23_pinctrl_data);
273}
274
275static struct of_device_id imx23_pinctrl_of_match[] __devinitdata = {
276 { .compatible = "fsl,imx23-pinctrl", },
277 { /* sentinel */ }
278};
279MODULE_DEVICE_TABLE(of, imx23_pinctrl_of_match);
280
281static struct platform_driver imx23_pinctrl_driver = {
282 .driver = {
283 .name = "imx23-pinctrl",
284 .owner = THIS_MODULE,
285 .of_match_table = imx23_pinctrl_of_match,
286 },
287 .probe = imx23_pinctrl_probe,
288 .remove = __devexit_p(mxs_pinctrl_remove),
289};
290
291static int __init imx23_pinctrl_init(void)
292{
293 return platform_driver_register(&imx23_pinctrl_driver);
294}
295arch_initcall(imx23_pinctrl_init);
296
297static void __exit imx23_pinctrl_exit(void)
298{
299 platform_driver_unregister(&imx23_pinctrl_driver);
300}
301module_exit(imx23_pinctrl_exit);
302
303MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
304MODULE_DESCRIPTION("Freescale i.MX23 pinctrl driver");
305MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-imx28.c b/drivers/pinctrl/pinctrl-imx28.c
new file mode 100644
index 00000000000..b973026811a
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx28.c
@@ -0,0 +1,421 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/of_device.h>
15#include <linux/pinctrl/pinctrl.h>
16#include "pinctrl-mxs.h"
17
18enum imx28_pin_enum {
19 GPMI_D00 = PINID(0, 0),
20 GPMI_D01 = PINID(0, 1),
21 GPMI_D02 = PINID(0, 2),
22 GPMI_D03 = PINID(0, 3),
23 GPMI_D04 = PINID(0, 4),
24 GPMI_D05 = PINID(0, 5),
25 GPMI_D06 = PINID(0, 6),
26 GPMI_D07 = PINID(0, 7),
27 GPMI_CE0N = PINID(0, 16),
28 GPMI_CE1N = PINID(0, 17),
29 GPMI_CE2N = PINID(0, 18),
30 GPMI_CE3N = PINID(0, 19),
31 GPMI_RDY0 = PINID(0, 20),
32 GPMI_RDY1 = PINID(0, 21),
33 GPMI_RDY2 = PINID(0, 22),
34 GPMI_RDY3 = PINID(0, 23),
35 GPMI_RDN = PINID(0, 24),
36 GPMI_WRN = PINID(0, 25),
37 GPMI_ALE = PINID(0, 26),
38 GPMI_CLE = PINID(0, 27),
39 GPMI_RESETN = PINID(0, 28),
40 LCD_D00 = PINID(1, 0),
41 LCD_D01 = PINID(1, 1),
42 LCD_D02 = PINID(1, 2),
43 LCD_D03 = PINID(1, 3),
44 LCD_D04 = PINID(1, 4),
45 LCD_D05 = PINID(1, 5),
46 LCD_D06 = PINID(1, 6),
47 LCD_D07 = PINID(1, 7),
48 LCD_D08 = PINID(1, 8),
49 LCD_D09 = PINID(1, 9),
50 LCD_D10 = PINID(1, 10),
51 LCD_D11 = PINID(1, 11),
52 LCD_D12 = PINID(1, 12),
53 LCD_D13 = PINID(1, 13),
54 LCD_D14 = PINID(1, 14),
55 LCD_D15 = PINID(1, 15),
56 LCD_D16 = PINID(1, 16),
57 LCD_D17 = PINID(1, 17),
58 LCD_D18 = PINID(1, 18),
59 LCD_D19 = PINID(1, 19),
60 LCD_D20 = PINID(1, 20),
61 LCD_D21 = PINID(1, 21),
62 LCD_D22 = PINID(1, 22),
63 LCD_D23 = PINID(1, 23),
64 LCD_RD_E = PINID(1, 24),
65 LCD_WR_RWN = PINID(1, 25),
66 LCD_RS = PINID(1, 26),
67 LCD_CS = PINID(1, 27),
68 LCD_VSYNC = PINID(1, 28),
69 LCD_HSYNC = PINID(1, 29),
70 LCD_DOTCLK = PINID(1, 30),
71 LCD_ENABLE = PINID(1, 31),
72 SSP0_DATA0 = PINID(2, 0),
73 SSP0_DATA1 = PINID(2, 1),
74 SSP0_DATA2 = PINID(2, 2),
75 SSP0_DATA3 = PINID(2, 3),
76 SSP0_DATA4 = PINID(2, 4),
77 SSP0_DATA5 = PINID(2, 5),
78 SSP0_DATA6 = PINID(2, 6),
79 SSP0_DATA7 = PINID(2, 7),
80 SSP0_CMD = PINID(2, 8),
81 SSP0_DETECT = PINID(2, 9),
82 SSP0_SCK = PINID(2, 10),
83 SSP1_SCK = PINID(2, 12),
84 SSP1_CMD = PINID(2, 13),
85 SSP1_DATA0 = PINID(2, 14),
86 SSP1_DATA3 = PINID(2, 15),
87 SSP2_SCK = PINID(2, 16),
88 SSP2_MOSI = PINID(2, 17),
89 SSP2_MISO = PINID(2, 18),
90 SSP2_SS0 = PINID(2, 19),
91 SSP2_SS1 = PINID(2, 20),
92 SSP2_SS2 = PINID(2, 21),
93 SSP3_SCK = PINID(2, 24),
94 SSP3_MOSI = PINID(2, 25),
95 SSP3_MISO = PINID(2, 26),
96 SSP3_SS0 = PINID(2, 27),
97 AUART0_RX = PINID(3, 0),
98 AUART0_TX = PINID(3, 1),
99 AUART0_CTS = PINID(3, 2),
100 AUART0_RTS = PINID(3, 3),
101 AUART1_RX = PINID(3, 4),
102 AUART1_TX = PINID(3, 5),
103 AUART1_CTS = PINID(3, 6),
104 AUART1_RTS = PINID(3, 7),
105 AUART2_RX = PINID(3, 8),
106 AUART2_TX = PINID(3, 9),
107 AUART2_CTS = PINID(3, 10),
108 AUART2_RTS = PINID(3, 11),
109 AUART3_RX = PINID(3, 12),
110 AUART3_TX = PINID(3, 13),
111 AUART3_CTS = PINID(3, 14),
112 AUART3_RTS = PINID(3, 15),
113 PWM0 = PINID(3, 16),
114 PWM1 = PINID(3, 17),
115 PWM2 = PINID(3, 18),
116 SAIF0_MCLK = PINID(3, 20),
117 SAIF0_LRCLK = PINID(3, 21),
118 SAIF0_BITCLK = PINID(3, 22),
119 SAIF0_SDATA0 = PINID(3, 23),
120 I2C0_SCL = PINID(3, 24),
121 I2C0_SDA = PINID(3, 25),
122 SAIF1_SDATA0 = PINID(3, 26),
123 SPDIF = PINID(3, 27),
124 PWM3 = PINID(3, 28),
125 PWM4 = PINID(3, 29),
126 LCD_RESET = PINID(3, 30),
127 ENET0_MDC = PINID(4, 0),
128 ENET0_MDIO = PINID(4, 1),
129 ENET0_RX_EN = PINID(4, 2),
130 ENET0_RXD0 = PINID(4, 3),
131 ENET0_RXD1 = PINID(4, 4),
132 ENET0_TX_CLK = PINID(4, 5),
133 ENET0_TX_EN = PINID(4, 6),
134 ENET0_TXD0 = PINID(4, 7),
135 ENET0_TXD1 = PINID(4, 8),
136 ENET0_RXD2 = PINID(4, 9),
137 ENET0_RXD3 = PINID(4, 10),
138 ENET0_TXD2 = PINID(4, 11),
139 ENET0_TXD3 = PINID(4, 12),
140 ENET0_RX_CLK = PINID(4, 13),
141 ENET0_COL = PINID(4, 14),
142 ENET0_CRS = PINID(4, 15),
143 ENET_CLK = PINID(4, 16),
144 JTAG_RTCK = PINID(4, 20),
145 EMI_D00 = PINID(5, 0),
146 EMI_D01 = PINID(5, 1),
147 EMI_D02 = PINID(5, 2),
148 EMI_D03 = PINID(5, 3),
149 EMI_D04 = PINID(5, 4),
150 EMI_D05 = PINID(5, 5),
151 EMI_D06 = PINID(5, 6),
152 EMI_D07 = PINID(5, 7),
153 EMI_D08 = PINID(5, 8),
154 EMI_D09 = PINID(5, 9),
155 EMI_D10 = PINID(5, 10),
156 EMI_D11 = PINID(5, 11),
157 EMI_D12 = PINID(5, 12),
158 EMI_D13 = PINID(5, 13),
159 EMI_D14 = PINID(5, 14),
160 EMI_D15 = PINID(5, 15),
161 EMI_ODT0 = PINID(5, 16),
162 EMI_DQM0 = PINID(5, 17),
163 EMI_ODT1 = PINID(5, 18),
164 EMI_DQM1 = PINID(5, 19),
165 EMI_DDR_OPEN_FB = PINID(5, 20),
166 EMI_CLK = PINID(5, 21),
167 EMI_DQS0 = PINID(5, 22),
168 EMI_DQS1 = PINID(5, 23),
169 EMI_DDR_OPEN = PINID(5, 26),
170 EMI_A00 = PINID(6, 0),
171 EMI_A01 = PINID(6, 1),
172 EMI_A02 = PINID(6, 2),
173 EMI_A03 = PINID(6, 3),
174 EMI_A04 = PINID(6, 4),
175 EMI_A05 = PINID(6, 5),
176 EMI_A06 = PINID(6, 6),
177 EMI_A07 = PINID(6, 7),
178 EMI_A08 = PINID(6, 8),
179 EMI_A09 = PINID(6, 9),
180 EMI_A10 = PINID(6, 10),
181 EMI_A11 = PINID(6, 11),
182 EMI_A12 = PINID(6, 12),
183 EMI_A13 = PINID(6, 13),
184 EMI_A14 = PINID(6, 14),
185 EMI_BA0 = PINID(6, 16),
186 EMI_BA1 = PINID(6, 17),
187 EMI_BA2 = PINID(6, 18),
188 EMI_CASN = PINID(6, 19),
189 EMI_RASN = PINID(6, 20),
190 EMI_WEN = PINID(6, 21),
191 EMI_CE0N = PINID(6, 22),
192 EMI_CE1N = PINID(6, 23),
193 EMI_CKE = PINID(6, 24),
194};
195
196static const struct pinctrl_pin_desc imx28_pins[] = {
197 MXS_PINCTRL_PIN(GPMI_D00),
198 MXS_PINCTRL_PIN(GPMI_D01),
199 MXS_PINCTRL_PIN(GPMI_D02),
200 MXS_PINCTRL_PIN(GPMI_D03),
201 MXS_PINCTRL_PIN(GPMI_D04),
202 MXS_PINCTRL_PIN(GPMI_D05),
203 MXS_PINCTRL_PIN(GPMI_D06),
204 MXS_PINCTRL_PIN(GPMI_D07),
205 MXS_PINCTRL_PIN(GPMI_CE0N),
206 MXS_PINCTRL_PIN(GPMI_CE1N),
207 MXS_PINCTRL_PIN(GPMI_CE2N),
208 MXS_PINCTRL_PIN(GPMI_CE3N),
209 MXS_PINCTRL_PIN(GPMI_RDY0),
210 MXS_PINCTRL_PIN(GPMI_RDY1),
211 MXS_PINCTRL_PIN(GPMI_RDY2),
212 MXS_PINCTRL_PIN(GPMI_RDY3),
213 MXS_PINCTRL_PIN(GPMI_RDN),
214 MXS_PINCTRL_PIN(GPMI_WRN),
215 MXS_PINCTRL_PIN(GPMI_ALE),
216 MXS_PINCTRL_PIN(GPMI_CLE),
217 MXS_PINCTRL_PIN(GPMI_RESETN),
218 MXS_PINCTRL_PIN(LCD_D00),
219 MXS_PINCTRL_PIN(LCD_D01),
220 MXS_PINCTRL_PIN(LCD_D02),
221 MXS_PINCTRL_PIN(LCD_D03),
222 MXS_PINCTRL_PIN(LCD_D04),
223 MXS_PINCTRL_PIN(LCD_D05),
224 MXS_PINCTRL_PIN(LCD_D06),
225 MXS_PINCTRL_PIN(LCD_D07),
226 MXS_PINCTRL_PIN(LCD_D08),
227 MXS_PINCTRL_PIN(LCD_D09),
228 MXS_PINCTRL_PIN(LCD_D10),
229 MXS_PINCTRL_PIN(LCD_D11),
230 MXS_PINCTRL_PIN(LCD_D12),
231 MXS_PINCTRL_PIN(LCD_D13),
232 MXS_PINCTRL_PIN(LCD_D14),
233 MXS_PINCTRL_PIN(LCD_D15),
234 MXS_PINCTRL_PIN(LCD_D16),
235 MXS_PINCTRL_PIN(LCD_D17),
236 MXS_PINCTRL_PIN(LCD_D18),
237 MXS_PINCTRL_PIN(LCD_D19),
238 MXS_PINCTRL_PIN(LCD_D20),
239 MXS_PINCTRL_PIN(LCD_D21),
240 MXS_PINCTRL_PIN(LCD_D22),
241 MXS_PINCTRL_PIN(LCD_D23),
242 MXS_PINCTRL_PIN(LCD_RD_E),
243 MXS_PINCTRL_PIN(LCD_WR_RWN),
244 MXS_PINCTRL_PIN(LCD_RS),
245 MXS_PINCTRL_PIN(LCD_CS),
246 MXS_PINCTRL_PIN(LCD_VSYNC),
247 MXS_PINCTRL_PIN(LCD_HSYNC),
248 MXS_PINCTRL_PIN(LCD_DOTCLK),
249 MXS_PINCTRL_PIN(LCD_ENABLE),
250 MXS_PINCTRL_PIN(SSP0_DATA0),
251 MXS_PINCTRL_PIN(SSP0_DATA1),
252 MXS_PINCTRL_PIN(SSP0_DATA2),
253 MXS_PINCTRL_PIN(SSP0_DATA3),
254 MXS_PINCTRL_PIN(SSP0_DATA4),
255 MXS_PINCTRL_PIN(SSP0_DATA5),
256 MXS_PINCTRL_PIN(SSP0_DATA6),
257 MXS_PINCTRL_PIN(SSP0_DATA7),
258 MXS_PINCTRL_PIN(SSP0_CMD),
259 MXS_PINCTRL_PIN(SSP0_DETECT),
260 MXS_PINCTRL_PIN(SSP0_SCK),
261 MXS_PINCTRL_PIN(SSP1_SCK),
262 MXS_PINCTRL_PIN(SSP1_CMD),
263 MXS_PINCTRL_PIN(SSP1_DATA0),
264 MXS_PINCTRL_PIN(SSP1_DATA3),
265 MXS_PINCTRL_PIN(SSP2_SCK),
266 MXS_PINCTRL_PIN(SSP2_MOSI),
267 MXS_PINCTRL_PIN(SSP2_MISO),
268 MXS_PINCTRL_PIN(SSP2_SS0),
269 MXS_PINCTRL_PIN(SSP2_SS1),
270 MXS_PINCTRL_PIN(SSP2_SS2),
271 MXS_PINCTRL_PIN(SSP3_SCK),
272 MXS_PINCTRL_PIN(SSP3_MOSI),
273 MXS_PINCTRL_PIN(SSP3_MISO),
274 MXS_PINCTRL_PIN(SSP3_SS0),
275 MXS_PINCTRL_PIN(AUART0_RX),
276 MXS_PINCTRL_PIN(AUART0_TX),
277 MXS_PINCTRL_PIN(AUART0_CTS),
278 MXS_PINCTRL_PIN(AUART0_RTS),
279 MXS_PINCTRL_PIN(AUART1_RX),
280 MXS_PINCTRL_PIN(AUART1_TX),
281 MXS_PINCTRL_PIN(AUART1_CTS),
282 MXS_PINCTRL_PIN(AUART1_RTS),
283 MXS_PINCTRL_PIN(AUART2_RX),
284 MXS_PINCTRL_PIN(AUART2_TX),
285 MXS_PINCTRL_PIN(AUART2_CTS),
286 MXS_PINCTRL_PIN(AUART2_RTS),
287 MXS_PINCTRL_PIN(AUART3_RX),
288 MXS_PINCTRL_PIN(AUART3_TX),
289 MXS_PINCTRL_PIN(AUART3_CTS),
290 MXS_PINCTRL_PIN(AUART3_RTS),
291 MXS_PINCTRL_PIN(PWM0),
292 MXS_PINCTRL_PIN(PWM1),
293 MXS_PINCTRL_PIN(PWM2),
294 MXS_PINCTRL_PIN(SAIF0_MCLK),
295 MXS_PINCTRL_PIN(SAIF0_LRCLK),
296 MXS_PINCTRL_PIN(SAIF0_BITCLK),
297 MXS_PINCTRL_PIN(SAIF0_SDATA0),
298 MXS_PINCTRL_PIN(I2C0_SCL),
299 MXS_PINCTRL_PIN(I2C0_SDA),
300 MXS_PINCTRL_PIN(SAIF1_SDATA0),
301 MXS_PINCTRL_PIN(SPDIF),
302 MXS_PINCTRL_PIN(PWM3),
303 MXS_PINCTRL_PIN(PWM4),
304 MXS_PINCTRL_PIN(LCD_RESET),
305 MXS_PINCTRL_PIN(ENET0_MDC),
306 MXS_PINCTRL_PIN(ENET0_MDIO),
307 MXS_PINCTRL_PIN(ENET0_RX_EN),
308 MXS_PINCTRL_PIN(ENET0_RXD0),
309 MXS_PINCTRL_PIN(ENET0_RXD1),
310 MXS_PINCTRL_PIN(ENET0_TX_CLK),
311 MXS_PINCTRL_PIN(ENET0_TX_EN),
312 MXS_PINCTRL_PIN(ENET0_TXD0),
313 MXS_PINCTRL_PIN(ENET0_TXD1),
314 MXS_PINCTRL_PIN(ENET0_RXD2),
315 MXS_PINCTRL_PIN(ENET0_RXD3),
316 MXS_PINCTRL_PIN(ENET0_TXD2),
317 MXS_PINCTRL_PIN(ENET0_TXD3),
318 MXS_PINCTRL_PIN(ENET0_RX_CLK),
319 MXS_PINCTRL_PIN(ENET0_COL),
320 MXS_PINCTRL_PIN(ENET0_CRS),
321 MXS_PINCTRL_PIN(ENET_CLK),
322 MXS_PINCTRL_PIN(JTAG_RTCK),
323 MXS_PINCTRL_PIN(EMI_D00),
324 MXS_PINCTRL_PIN(EMI_D01),
325 MXS_PINCTRL_PIN(EMI_D02),
326 MXS_PINCTRL_PIN(EMI_D03),
327 MXS_PINCTRL_PIN(EMI_D04),
328 MXS_PINCTRL_PIN(EMI_D05),
329 MXS_PINCTRL_PIN(EMI_D06),
330 MXS_PINCTRL_PIN(EMI_D07),
331 MXS_PINCTRL_PIN(EMI_D08),
332 MXS_PINCTRL_PIN(EMI_D09),
333 MXS_PINCTRL_PIN(EMI_D10),
334 MXS_PINCTRL_PIN(EMI_D11),
335 MXS_PINCTRL_PIN(EMI_D12),
336 MXS_PINCTRL_PIN(EMI_D13),
337 MXS_PINCTRL_PIN(EMI_D14),
338 MXS_PINCTRL_PIN(EMI_D15),
339 MXS_PINCTRL_PIN(EMI_ODT0),
340 MXS_PINCTRL_PIN(EMI_DQM0),
341 MXS_PINCTRL_PIN(EMI_ODT1),
342 MXS_PINCTRL_PIN(EMI_DQM1),
343 MXS_PINCTRL_PIN(EMI_DDR_OPEN_FB),
344 MXS_PINCTRL_PIN(EMI_CLK),
345 MXS_PINCTRL_PIN(EMI_DQS0),
346 MXS_PINCTRL_PIN(EMI_DQS1),
347 MXS_PINCTRL_PIN(EMI_DDR_OPEN),
348 MXS_PINCTRL_PIN(EMI_A00),
349 MXS_PINCTRL_PIN(EMI_A01),
350 MXS_PINCTRL_PIN(EMI_A02),
351 MXS_PINCTRL_PIN(EMI_A03),
352 MXS_PINCTRL_PIN(EMI_A04),
353 MXS_PINCTRL_PIN(EMI_A05),
354 MXS_PINCTRL_PIN(EMI_A06),
355 MXS_PINCTRL_PIN(EMI_A07),
356 MXS_PINCTRL_PIN(EMI_A08),
357 MXS_PINCTRL_PIN(EMI_A09),
358 MXS_PINCTRL_PIN(EMI_A10),
359 MXS_PINCTRL_PIN(EMI_A11),
360 MXS_PINCTRL_PIN(EMI_A12),
361 MXS_PINCTRL_PIN(EMI_A13),
362 MXS_PINCTRL_PIN(EMI_A14),
363 MXS_PINCTRL_PIN(EMI_BA0),
364 MXS_PINCTRL_PIN(EMI_BA1),
365 MXS_PINCTRL_PIN(EMI_BA2),
366 MXS_PINCTRL_PIN(EMI_CASN),
367 MXS_PINCTRL_PIN(EMI_RASN),
368 MXS_PINCTRL_PIN(EMI_WEN),
369 MXS_PINCTRL_PIN(EMI_CE0N),
370 MXS_PINCTRL_PIN(EMI_CE1N),
371 MXS_PINCTRL_PIN(EMI_CKE),
372};
373
374static struct mxs_regs imx28_regs = {
375 .muxsel = 0x100,
376 .drive = 0x300,
377 .pull = 0x600,
378};
379
380static struct mxs_pinctrl_soc_data imx28_pinctrl_data = {
381 .regs = &imx28_regs,
382 .pins = imx28_pins,
383 .npins = ARRAY_SIZE(imx28_pins),
384};
385
386static int __devinit imx28_pinctrl_probe(struct platform_device *pdev)
387{
388 return mxs_pinctrl_probe(pdev, &imx28_pinctrl_data);
389}
390
391static struct of_device_id imx28_pinctrl_of_match[] __devinitdata = {
392 { .compatible = "fsl,imx28-pinctrl", },
393 { /* sentinel */ }
394};
395MODULE_DEVICE_TABLE(of, imx28_pinctrl_of_match);
396
397static struct platform_driver imx28_pinctrl_driver = {
398 .driver = {
399 .name = "imx28-pinctrl",
400 .owner = THIS_MODULE,
401 .of_match_table = imx28_pinctrl_of_match,
402 },
403 .probe = imx28_pinctrl_probe,
404 .remove = __devexit_p(mxs_pinctrl_remove),
405};
406
407static int __init imx28_pinctrl_init(void)
408{
409 return platform_driver_register(&imx28_pinctrl_driver);
410}
411arch_initcall(imx28_pinctrl_init);
412
413static void __exit imx28_pinctrl_exit(void)
414{
415 platform_driver_unregister(&imx28_pinctrl_driver);
416}
417module_exit(imx28_pinctrl_exit);
418
419MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
420MODULE_DESCRIPTION("Freescale i.MX28 pinctrl driver");
421MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-imx51.c b/drivers/pinctrl/pinctrl-imx51.c
new file mode 100644
index 00000000000..689b3c88dd2
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx51.c
@@ -0,0 +1,1322 @@
1/*
2 * imx51 pinctrl driver based on imx pinmux core
3 *
4 * Copyright (C) 2012 Freescale Semiconductor, Inc.
5 * Copyright (C) 2012 Linaro, Inc.
6 *
7 * Author: Dong Aisheng <dong.aisheng@linaro.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#include <linux/err.h>
16#include <linux/init.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/pinctrl/pinctrl.h>
22
23#include "pinctrl-imx.h"
24
25enum imx51_pads {
26 MX51_PAD_EIM_D16 = 1,
27 MX51_PAD_EIM_D17 = 2,
28 MX51_PAD_EIM_D18 = 3,
29 MX51_PAD_EIM_D19 = 4,
30 MX51_PAD_EIM_D20 = 5,
31 MX51_PAD_EIM_D21 = 6,
32 MX51_PAD_EIM_D22 = 7,
33 MX51_PAD_EIM_D23 = 8,
34 MX51_PAD_EIM_D24 = 9,
35 MX51_PAD_EIM_D25 = 10,
36 MX51_PAD_EIM_D26 = 11,
37 MX51_PAD_EIM_D27 = 12,
38 MX51_PAD_EIM_D28 = 13,
39 MX51_PAD_EIM_D29 = 14,
40 MX51_PAD_EIM_D30 = 15,
41 MX51_PAD_EIM_D31 = 16,
42 MX51_PAD_EIM_A16 = 17,
43 MX51_PAD_EIM_A17 = 18,
44 MX51_PAD_EIM_A18 = 19,
45 MX51_PAD_EIM_A19 = 20,
46 MX51_PAD_EIM_A20 = 21,
47 MX51_PAD_EIM_A21 = 22,
48 MX51_PAD_EIM_A22 = 23,
49 MX51_PAD_EIM_A23 = 24,
50 MX51_PAD_EIM_A24 = 25,
51 MX51_PAD_EIM_A25 = 26,
52 MX51_PAD_EIM_A26 = 27,
53 MX51_PAD_EIM_A27 = 28,
54 MX51_PAD_EIM_EB0 = 29,
55 MX51_PAD_EIM_EB1 = 30,
56 MX51_PAD_EIM_EB2 = 31,
57 MX51_PAD_EIM_EB3 = 32,
58 MX51_PAD_EIM_OE = 33,
59 MX51_PAD_EIM_CS0 = 34,
60 MX51_PAD_EIM_CS1 = 35,
61 MX51_PAD_EIM_CS2 = 36,
62 MX51_PAD_EIM_CS3 = 37,
63 MX51_PAD_EIM_CS4 = 38,
64 MX51_PAD_EIM_CS5 = 39,
65 MX51_PAD_EIM_DTACK = 40,
66 MX51_PAD_EIM_LBA = 41,
67 MX51_PAD_EIM_CRE = 42,
68 MX51_PAD_DRAM_CS1 = 43,
69 MX51_PAD_NANDF_WE_B = 44,
70 MX51_PAD_NANDF_RE_B = 45,
71 MX51_PAD_NANDF_ALE = 46,
72 MX51_PAD_NANDF_CLE = 47,
73 MX51_PAD_NANDF_WP_B = 48,
74 MX51_PAD_NANDF_RB0 = 49,
75 MX51_PAD_NANDF_RB1 = 50,
76 MX51_PAD_NANDF_RB2 = 51,
77 MX51_PAD_NANDF_RB3 = 52,
78 MX51_PAD_GPIO_NAND = 53,
79 MX51_PAD_NANDF_CS0 = 54,
80 MX51_PAD_NANDF_CS1 = 55,
81 MX51_PAD_NANDF_CS2 = 56,
82 MX51_PAD_NANDF_CS3 = 57,
83 MX51_PAD_NANDF_CS4 = 58,
84 MX51_PAD_NANDF_CS5 = 59,
85 MX51_PAD_NANDF_CS6 = 60,
86 MX51_PAD_NANDF_CS7 = 61,
87 MX51_PAD_NANDF_RDY_INT = 62,
88 MX51_PAD_NANDF_D15 = 63,
89 MX51_PAD_NANDF_D14 = 64,
90 MX51_PAD_NANDF_D13 = 65,
91 MX51_PAD_NANDF_D12 = 66,
92 MX51_PAD_NANDF_D11 = 67,
93 MX51_PAD_NANDF_D10 = 68,
94 MX51_PAD_NANDF_D9 = 69,
95 MX51_PAD_NANDF_D8 = 70,
96 MX51_PAD_NANDF_D7 = 71,
97 MX51_PAD_NANDF_D6 = 72,
98 MX51_PAD_NANDF_D5 = 73,
99 MX51_PAD_NANDF_D4 = 74,
100 MX51_PAD_NANDF_D3 = 75,
101 MX51_PAD_NANDF_D2 = 76,
102 MX51_PAD_NANDF_D1 = 77,
103 MX51_PAD_NANDF_D0 = 78,
104 MX51_PAD_CSI1_D8 = 79,
105 MX51_PAD_CSI1_D9 = 80,
106 MX51_PAD_CSI1_D10 = 81,
107 MX51_PAD_CSI1_D11 = 82,
108 MX51_PAD_CSI1_D12 = 83,
109 MX51_PAD_CSI1_D13 = 84,
110 MX51_PAD_CSI1_D14 = 85,
111 MX51_PAD_CSI1_D15 = 86,
112 MX51_PAD_CSI1_D16 = 87,
113 MX51_PAD_CSI1_D17 = 88,
114 MX51_PAD_CSI1_D18 = 89,
115 MX51_PAD_CSI1_D19 = 90,
116 MX51_PAD_CSI1_VSYNC = 91,
117 MX51_PAD_CSI1_HSYNC = 92,
118 MX51_PAD_CSI1_PIXCLK = 93,
119 MX51_PAD_CSI1_MCLK = 94,
120 MX51_PAD_CSI2_D12 = 95,
121 MX51_PAD_CSI2_D13 = 96,
122 MX51_PAD_CSI2_D14 = 97,
123 MX51_PAD_CSI2_D15 = 98,
124 MX51_PAD_CSI2_D16 = 99,
125 MX51_PAD_CSI2_D17 = 100,
126 MX51_PAD_CSI2_D18 = 101,
127 MX51_PAD_CSI2_D19 = 102,
128 MX51_PAD_CSI2_VSYNC = 103,
129 MX51_PAD_CSI2_HSYNC = 104,
130 MX51_PAD_CSI2_PIXCLK = 105,
131 MX51_PAD_I2C1_CLK = 106,
132 MX51_PAD_I2C1_DAT = 107,
133 MX51_PAD_AUD3_BB_TXD = 108,
134 MX51_PAD_AUD3_BB_RXD = 109,
135 MX51_PAD_AUD3_BB_CK = 110,
136 MX51_PAD_AUD3_BB_FS = 111,
137 MX51_PAD_CSPI1_MOSI = 112,
138 MX51_PAD_CSPI1_MISO = 113,
139 MX51_PAD_CSPI1_SS0 = 114,
140 MX51_PAD_CSPI1_SS1 = 115,
141 MX51_PAD_CSPI1_RDY = 116,
142 MX51_PAD_CSPI1_SCLK = 117,
143 MX51_PAD_UART1_RXD = 118,
144 MX51_PAD_UART1_TXD = 119,
145 MX51_PAD_UART1_RTS = 120,
146 MX51_PAD_UART1_CTS = 121,
147 MX51_PAD_UART2_RXD = 122,
148 MX51_PAD_UART2_TXD = 123,
149 MX51_PAD_UART3_RXD = 124,
150 MX51_PAD_UART3_TXD = 125,
151 MX51_PAD_OWIRE_LINE = 126,
152 MX51_PAD_KEY_ROW0 = 127,
153 MX51_PAD_KEY_ROW1 = 128,
154 MX51_PAD_KEY_ROW2 = 129,
155 MX51_PAD_KEY_ROW3 = 130,
156 MX51_PAD_KEY_COL0 = 131,
157 MX51_PAD_KEY_COL1 = 132,
158 MX51_PAD_KEY_COL2 = 133,
159 MX51_PAD_KEY_COL3 = 134,
160 MX51_PAD_KEY_COL4 = 135,
161 MX51_PAD_KEY_COL5 = 136,
162 MX51_PAD_USBH1_CLK = 137,
163 MX51_PAD_USBH1_DIR = 138,
164 MX51_PAD_USBH1_STP = 139,
165 MX51_PAD_USBH1_NXT = 140,
166 MX51_PAD_USBH1_DATA0 = 141,
167 MX51_PAD_USBH1_DATA1 = 142,
168 MX51_PAD_USBH1_DATA2 = 143,
169 MX51_PAD_USBH1_DATA3 = 144,
170 MX51_PAD_USBH1_DATA4 = 145,
171 MX51_PAD_USBH1_DATA5 = 146,
172 MX51_PAD_USBH1_DATA6 = 147,
173 MX51_PAD_USBH1_DATA7 = 148,
174 MX51_PAD_DI1_PIN11 = 149,
175 MX51_PAD_DI1_PIN12 = 150,
176 MX51_PAD_DI1_PIN13 = 151,
177 MX51_PAD_DI1_D0_CS = 152,
178 MX51_PAD_DI1_D1_CS = 153,
179 MX51_PAD_DISPB2_SER_DIN = 154,
180 MX51_PAD_DISPB2_SER_DIO = 155,
181 MX51_PAD_DISPB2_SER_CLK = 156,
182 MX51_PAD_DISPB2_SER_RS = 157,
183 MX51_PAD_DISP1_DAT0 = 158,
184 MX51_PAD_DISP1_DAT1 = 159,
185 MX51_PAD_DISP1_DAT2 = 160,
186 MX51_PAD_DISP1_DAT3 = 161,
187 MX51_PAD_DISP1_DAT4 = 162,
188 MX51_PAD_DISP1_DAT5 = 163,
189 MX51_PAD_DISP1_DAT6 = 164,
190 MX51_PAD_DISP1_DAT7 = 165,
191 MX51_PAD_DISP1_DAT8 = 166,
192 MX51_PAD_DISP1_DAT9 = 167,
193 MX51_PAD_DISP1_DAT10 = 168,
194 MX51_PAD_DISP1_DAT11 = 169,
195 MX51_PAD_DISP1_DAT12 = 170,
196 MX51_PAD_DISP1_DAT13 = 171,
197 MX51_PAD_DISP1_DAT14 = 172,
198 MX51_PAD_DISP1_DAT15 = 173,
199 MX51_PAD_DISP1_DAT16 = 174,
200 MX51_PAD_DISP1_DAT17 = 175,
201 MX51_PAD_DISP1_DAT18 = 176,
202 MX51_PAD_DISP1_DAT19 = 177,
203 MX51_PAD_DISP1_DAT20 = 178,
204 MX51_PAD_DISP1_DAT21 = 179,
205 MX51_PAD_DISP1_DAT22 = 180,
206 MX51_PAD_DISP1_DAT23 = 181,
207 MX51_PAD_DI1_PIN3 = 182,
208 MX51_PAD_DI1_PIN2 = 183,
209 MX51_PAD_DI_GP2 = 184,
210 MX51_PAD_DI_GP3 = 185,
211 MX51_PAD_DI2_PIN4 = 186,
212 MX51_PAD_DI2_PIN2 = 187,
213 MX51_PAD_DI2_PIN3 = 188,
214 MX51_PAD_DI2_DISP_CLK = 189,
215 MX51_PAD_DI_GP4 = 190,
216 MX51_PAD_DISP2_DAT0 = 191,
217 MX51_PAD_DISP2_DAT1 = 192,
218 MX51_PAD_DISP2_DAT2 = 193,
219 MX51_PAD_DISP2_DAT3 = 194,
220 MX51_PAD_DISP2_DAT4 = 195,
221 MX51_PAD_DISP2_DAT5 = 196,
222 MX51_PAD_DISP2_DAT6 = 197,
223 MX51_PAD_DISP2_DAT7 = 198,
224 MX51_PAD_DISP2_DAT8 = 199,
225 MX51_PAD_DISP2_DAT9 = 200,
226 MX51_PAD_DISP2_DAT10 = 201,
227 MX51_PAD_DISP2_DAT11 = 202,
228 MX51_PAD_DISP2_DAT12 = 203,
229 MX51_PAD_DISP2_DAT13 = 204,
230 MX51_PAD_DISP2_DAT14 = 205,
231 MX51_PAD_DISP2_DAT15 = 206,
232 MX51_PAD_SD1_CMD = 207,
233 MX51_PAD_SD1_CLK = 208,
234 MX51_PAD_SD1_DATA0 = 209,
235 MX51_PAD_EIM_DA0 = 210,
236 MX51_PAD_EIM_DA1 = 211,
237 MX51_PAD_EIM_DA2 = 212,
238 MX51_PAD_EIM_DA3 = 213,
239 MX51_PAD_SD1_DATA1 = 214,
240 MX51_PAD_EIM_DA4 = 215,
241 MX51_PAD_EIM_DA5 = 216,
242 MX51_PAD_EIM_DA6 = 217,
243 MX51_PAD_EIM_DA7 = 218,
244 MX51_PAD_SD1_DATA2 = 219,
245 MX51_PAD_EIM_DA10 = 220,
246 MX51_PAD_EIM_DA11 = 221,
247 MX51_PAD_EIM_DA8 = 222,
248 MX51_PAD_EIM_DA9 = 223,
249 MX51_PAD_SD1_DATA3 = 224,
250 MX51_PAD_GPIO1_0 = 225,
251 MX51_PAD_GPIO1_1 = 226,
252 MX51_PAD_EIM_DA12 = 227,
253 MX51_PAD_EIM_DA13 = 228,
254 MX51_PAD_EIM_DA14 = 229,
255 MX51_PAD_EIM_DA15 = 230,
256 MX51_PAD_SD2_CMD = 231,
257 MX51_PAD_SD2_CLK = 232,
258 MX51_PAD_SD2_DATA0 = 233,
259 MX51_PAD_SD2_DATA1 = 234,
260 MX51_PAD_SD2_DATA2 = 235,
261 MX51_PAD_SD2_DATA3 = 236,
262 MX51_PAD_GPIO1_2 = 237,
263 MX51_PAD_GPIO1_3 = 238,
264 MX51_PAD_PMIC_INT_REQ = 239,
265 MX51_PAD_GPIO1_4 = 240,
266 MX51_PAD_GPIO1_5 = 241,
267 MX51_PAD_GPIO1_6 = 242,
268 MX51_PAD_GPIO1_7 = 243,
269 MX51_PAD_GPIO1_8 = 244,
270 MX51_PAD_GPIO1_9 = 245,
271};
272
273/* imx51 register maps */
274static struct imx_pin_reg imx51_pin_regs[] = {
275 IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 5, 0x000, 0), /* MX51_PAD_EIM_D16__AUD4_RXFS */
276 IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 7, 0x8d8, 0), /* MX51_PAD_EIM_D16__AUD5_TXD */
277 IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 0, 0x000, 0), /* MX51_PAD_EIM_D16__EIM_D16 */
278 IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 1, 0x000, 0), /* MX51_PAD_EIM_D16__GPIO2_0 */
279 IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 4, 0x9b4, 0), /* MX51_PAD_EIM_D16__I2C1_SDA */
280 IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 3, 0x000, 0), /* MX51_PAD_EIM_D16__UART2_CTS */
281 IMX_PIN_REG(MX51_PAD_EIM_D16, 0x3f0, 0x05c, 2, 0x000, 0), /* MX51_PAD_EIM_D16__USBH2_DATA0 */
282 IMX_PIN_REG(MX51_PAD_EIM_D17, 0x3f4, 0x060, 7, 0x8d4, 0), /* MX51_PAD_EIM_D17__AUD5_RXD */
283 IMX_PIN_REG(MX51_PAD_EIM_D17, 0x3f4, 0x060, 0, 0x000, 0), /* MX51_PAD_EIM_D17__EIM_D17 */
284 IMX_PIN_REG(MX51_PAD_EIM_D17, 0x3f4, 0x060, 1, 0x000, 0), /* MX51_PAD_EIM_D17__GPIO2_1 */
285 IMX_PIN_REG(MX51_PAD_EIM_D17, 0x3f4, 0x060, 3, 0x9ec, 0), /* MX51_PAD_EIM_D17__UART2_RXD */
286 IMX_PIN_REG(MX51_PAD_EIM_D17, 0x3f4, 0x060, 4, 0x000, 0), /* MX51_PAD_EIM_D17__UART3_CTS */
287 IMX_PIN_REG(MX51_PAD_EIM_D17, 0x3f4, 0x060, 2, 0x000, 0), /* MX51_PAD_EIM_D17__USBH2_DATA1 */
288 IMX_PIN_REG(MX51_PAD_EIM_D18, 0x3f8, 0x064, 7, 0x8e4, 0), /* MX51_PAD_EIM_D18__AUD5_TXC */
289 IMX_PIN_REG(MX51_PAD_EIM_D18, 0x3f8, 0x064, 0, 0x000, 0), /* MX51_PAD_EIM_D18__EIM_D18 */
290 IMX_PIN_REG(MX51_PAD_EIM_D18, 0x3f8, 0x064, 1, 0x000, 0), /* MX51_PAD_EIM_D18__GPIO2_2 */
291 IMX_PIN_REG(MX51_PAD_EIM_D18, 0x3f8, 0x064, 3, 0x000, 0), /* MX51_PAD_EIM_D18__UART2_TXD */
292 IMX_PIN_REG(MX51_PAD_EIM_D18, 0x3f8, 0x064, 4, 0x9f0, 1), /* MX51_PAD_EIM_D18__UART3_RTS */
293 IMX_PIN_REG(MX51_PAD_EIM_D18, 0x3f8, 0x064, 2, 0x000, 0), /* MX51_PAD_EIM_D18__USBH2_DATA2 */
294 IMX_PIN_REG(MX51_PAD_EIM_D19, 0x3fc, 0x068, 5, 0x000, 0), /* MX51_PAD_EIM_D19__AUD4_RXC */
295 IMX_PIN_REG(MX51_PAD_EIM_D19, 0x3fc, 0x068, 7, 0x8e8, 0), /* MX51_PAD_EIM_D19__AUD5_TXFS */
296 IMX_PIN_REG(MX51_PAD_EIM_D19, 0x3fc, 0x068, 0, 0x000, 0), /* MX51_PAD_EIM_D19__EIM_D19 */
297 IMX_PIN_REG(MX51_PAD_EIM_D19, 0x3fc, 0x068, 1, 0x000, 0), /* MX51_PAD_EIM_D19__GPIO2_3 */
298 IMX_PIN_REG(MX51_PAD_EIM_D19, 0x3fc, 0x068, 4, 0x9b0, 0), /* MX51_PAD_EIM_D19__I2C1_SCL */
299 IMX_PIN_REG(MX51_PAD_EIM_D19, 0x3fc, 0x068, 3, 0x9e8, 1), /* MX51_PAD_EIM_D19__UART2_RTS */
300 IMX_PIN_REG(MX51_PAD_EIM_D19, 0x3fc, 0x068, 2, 0x000, 0), /* MX51_PAD_EIM_D19__USBH2_DATA3 */
301 IMX_PIN_REG(MX51_PAD_EIM_D20, 0x400, 0x06c, 5, 0x8c8, 0), /* MX51_PAD_EIM_D20__AUD4_TXD */
302 IMX_PIN_REG(MX51_PAD_EIM_D20, 0x400, 0x06c, 0, 0x000, 0), /* MX51_PAD_EIM_D20__EIM_D20 */
303 IMX_PIN_REG(MX51_PAD_EIM_D20, 0x400, 0x06c, 1, 0x000, 0), /* MX51_PAD_EIM_D20__GPIO2_4 */
304 IMX_PIN_REG(MX51_PAD_EIM_D20, 0x400, 0x06c, 4, 0x000, 0), /* MX51_PAD_EIM_D20__SRTC_ALARM_DEB */
305 IMX_PIN_REG(MX51_PAD_EIM_D20, 0x400, 0x06c, 2, 0x000, 0), /* MX51_PAD_EIM_D20__USBH2_DATA4 */
306 IMX_PIN_REG(MX51_PAD_EIM_D21, 0x404, 0x070, 5, 0x8c4, 0), /* MX51_PAD_EIM_D21__AUD4_RXD */
307 IMX_PIN_REG(MX51_PAD_EIM_D21, 0x404, 0x070, 0, 0x000, 0), /* MX51_PAD_EIM_D21__EIM_D21 */
308 IMX_PIN_REG(MX51_PAD_EIM_D21, 0x404, 0x070, 1, 0x000, 0), /* MX51_PAD_EIM_D21__GPIO2_5 */
309 IMX_PIN_REG(MX51_PAD_EIM_D21, 0x404, 0x070, 3, 0x000, 0), /* MX51_PAD_EIM_D21__SRTC_ALARM_DEB */
310 IMX_PIN_REG(MX51_PAD_EIM_D21, 0x404, 0x070, 2, 0x000, 0), /* MX51_PAD_EIM_D21__USBH2_DATA5 */
311 IMX_PIN_REG(MX51_PAD_EIM_D22, 0x408, 0x074, 5, 0x8cc, 0), /* MX51_PAD_EIM_D22__AUD4_TXC */
312 IMX_PIN_REG(MX51_PAD_EIM_D22, 0x408, 0x074, 0, 0x000, 0), /* MX51_PAD_EIM_D22__EIM_D22 */
313 IMX_PIN_REG(MX51_PAD_EIM_D22, 0x408, 0x074, 1, 0x000, 0), /* MX51_PAD_EIM_D22__GPIO2_6 */
314 IMX_PIN_REG(MX51_PAD_EIM_D22, 0x408, 0x074, 2, 0x000, 0), /* MX51_PAD_EIM_D22__USBH2_DATA6 */
315 IMX_PIN_REG(MX51_PAD_EIM_D23, 0x40c, 0x078, 5, 0x8d0, 0), /* MX51_PAD_EIM_D23__AUD4_TXFS */
316 IMX_PIN_REG(MX51_PAD_EIM_D23, 0x40c, 0x078, 0, 0x000, 0), /* MX51_PAD_EIM_D23__EIM_D23 */
317 IMX_PIN_REG(MX51_PAD_EIM_D23, 0x40c, 0x078, 1, 0x000, 0), /* MX51_PAD_EIM_D23__GPIO2_7 */
318 IMX_PIN_REG(MX51_PAD_EIM_D23, 0x40c, 0x078, 4, 0x000, 0), /* MX51_PAD_EIM_D23__SPDIF_OUT1 */
319 IMX_PIN_REG(MX51_PAD_EIM_D23, 0x40c, 0x078, 2, 0x000, 0), /* MX51_PAD_EIM_D23__USBH2_DATA7 */
320 IMX_PIN_REG(MX51_PAD_EIM_D24, 0x410, 0x07c, 5, 0x8f8, 0), /* MX51_PAD_EIM_D24__AUD6_RXFS */
321 IMX_PIN_REG(MX51_PAD_EIM_D24, 0x410, 0x07c, 0, 0x000, 0), /* MX51_PAD_EIM_D24__EIM_D24 */
322 IMX_PIN_REG(MX51_PAD_EIM_D24, 0x410, 0x07c, 1, 0x000, 0), /* MX51_PAD_EIM_D24__GPIO2_8 */
323 IMX_PIN_REG(MX51_PAD_EIM_D24, 0x410, 0x07c, 4, 0x9bc, 0), /* MX51_PAD_EIM_D24__I2C2_SDA */
324 IMX_PIN_REG(MX51_PAD_EIM_D24, 0x410, 0x07c, 3, 0x000, 0), /* MX51_PAD_EIM_D24__UART3_CTS */
325 IMX_PIN_REG(MX51_PAD_EIM_D24, 0x410, 0x07c, 2, 0x000, 0), /* MX51_PAD_EIM_D24__USBOTG_DATA0 */
326 IMX_PIN_REG(MX51_PAD_EIM_D25, 0x414, 0x080, 0, 0x000, 0), /* MX51_PAD_EIM_D25__EIM_D25 */
327 IMX_PIN_REG(MX51_PAD_EIM_D25, 0x414, 0x080, 1, 0x9c8, 0), /* MX51_PAD_EIM_D25__KEY_COL6 */
328 IMX_PIN_REG(MX51_PAD_EIM_D25, 0x414, 0x080, 4, 0x000, 0), /* MX51_PAD_EIM_D25__UART2_CTS */
329 IMX_PIN_REG(MX51_PAD_EIM_D25, 0x414, 0x080, 3, 0x9f4, 0), /* MX51_PAD_EIM_D25__UART3_RXD */
330 IMX_PIN_REG(MX51_PAD_EIM_D25, 0x414, 0x080, 2, 0x000, 0), /* MX51_PAD_EIM_D25__USBOTG_DATA1 */
331 IMX_PIN_REG(MX51_PAD_EIM_D26, 0x418, 0x084, 0, 0x000, 0), /* MX51_PAD_EIM_D26__EIM_D26 */
332 IMX_PIN_REG(MX51_PAD_EIM_D26, 0x418, 0x084, 1, 0x9cc, 0), /* MX51_PAD_EIM_D26__KEY_COL7 */
333 IMX_PIN_REG(MX51_PAD_EIM_D26, 0x418, 0x084, 4, 0x9e8, 3), /* MX51_PAD_EIM_D26__UART2_RTS */
334 IMX_PIN_REG(MX51_PAD_EIM_D26, 0x418, 0x084, 3, 0x000, 0), /* MX51_PAD_EIM_D26__UART3_TXD */
335 IMX_PIN_REG(MX51_PAD_EIM_D26, 0x418, 0x084, 2, 0x000, 0), /* MX51_PAD_EIM_D26__USBOTG_DATA2 */
336 IMX_PIN_REG(MX51_PAD_EIM_D27, 0x41c, 0x088, 5, 0x8f4, 0), /* MX51_PAD_EIM_D27__AUD6_RXC */
337 IMX_PIN_REG(MX51_PAD_EIM_D27, 0x41c, 0x088, 0, 0x000, 0), /* MX51_PAD_EIM_D27__EIM_D27 */
338 IMX_PIN_REG(MX51_PAD_EIM_D27, 0x41c, 0x088, 1, 0x000, 0), /* MX51_PAD_EIM_D27__GPIO2_9 */
339 IMX_PIN_REG(MX51_PAD_EIM_D27, 0x41c, 0x088, 4, 0x9b8, 0), /* MX51_PAD_EIM_D27__I2C2_SCL */
340 IMX_PIN_REG(MX51_PAD_EIM_D27, 0x41c, 0x088, 3, 0x9f0, 3), /* MX51_PAD_EIM_D27__UART3_RTS */
341 IMX_PIN_REG(MX51_PAD_EIM_D27, 0x41c, 0x088, 2, 0x000, 0), /* MX51_PAD_EIM_D27__USBOTG_DATA3 */
342 IMX_PIN_REG(MX51_PAD_EIM_D28, 0x420, 0x08c, 5, 0x8f0, 0), /* MX51_PAD_EIM_D28__AUD6_TXD */
343 IMX_PIN_REG(MX51_PAD_EIM_D28, 0x420, 0x08c, 0, 0x000, 0), /* MX51_PAD_EIM_D28__EIM_D28 */
344 IMX_PIN_REG(MX51_PAD_EIM_D28, 0x420, 0x08c, 1, 0x9d0, 0), /* MX51_PAD_EIM_D28__KEY_ROW4 */
345 IMX_PIN_REG(MX51_PAD_EIM_D28, 0x420, 0x08c, 2, 0x000, 0), /* MX51_PAD_EIM_D28__USBOTG_DATA4 */
346 IMX_PIN_REG(MX51_PAD_EIM_D29, 0x424, 0x090, 5, 0x8ec, 0), /* MX51_PAD_EIM_D29__AUD6_RXD */
347 IMX_PIN_REG(MX51_PAD_EIM_D29, 0x424, 0x090, 0, 0x000, 0), /* MX51_PAD_EIM_D29__EIM_D29 */
348 IMX_PIN_REG(MX51_PAD_EIM_D29, 0x424, 0x090, 1, 0x9d4, 0), /* MX51_PAD_EIM_D29__KEY_ROW5 */
349 IMX_PIN_REG(MX51_PAD_EIM_D29, 0x424, 0x090, 2, 0x000, 0), /* MX51_PAD_EIM_D29__USBOTG_DATA5 */
350 IMX_PIN_REG(MX51_PAD_EIM_D30, 0x428, 0x094, 5, 0x8fc, 0), /* MX51_PAD_EIM_D30__AUD6_TXC */
351 IMX_PIN_REG(MX51_PAD_EIM_D30, 0x428, 0x094, 0, 0x000, 0), /* MX51_PAD_EIM_D30__EIM_D30 */
352 IMX_PIN_REG(MX51_PAD_EIM_D30, 0x428, 0x094, 1, 0x9d8, 0), /* MX51_PAD_EIM_D30__KEY_ROW6 */
353 IMX_PIN_REG(MX51_PAD_EIM_D30, 0x428, 0x094, 2, 0x000, 0), /* MX51_PAD_EIM_D30__USBOTG_DATA6 */
354 IMX_PIN_REG(MX51_PAD_EIM_D31, 0x42c, 0x098, 5, 0x900, 0), /* MX51_PAD_EIM_D31__AUD6_TXFS */
355 IMX_PIN_REG(MX51_PAD_EIM_D31, 0x42c, 0x098, 0, 0x000, 0), /* MX51_PAD_EIM_D31__EIM_D31 */
356 IMX_PIN_REG(MX51_PAD_EIM_D31, 0x42c, 0x098, 1, 0x9dc, 0), /* MX51_PAD_EIM_D31__KEY_ROW7 */
357 IMX_PIN_REG(MX51_PAD_EIM_D31, 0x42c, 0x098, 2, 0x000, 0), /* MX51_PAD_EIM_D31__USBOTG_DATA7 */
358 IMX_PIN_REG(MX51_PAD_EIM_A16, 0x430, 0x09c, 0, 0x000, 0), /* MX51_PAD_EIM_A16__EIM_A16 */
359 IMX_PIN_REG(MX51_PAD_EIM_A16, 0x430, 0x09c, 1, 0x000, 0), /* MX51_PAD_EIM_A16__GPIO2_10 */
360 IMX_PIN_REG(MX51_PAD_EIM_A16, 0x430, 0x09c, 7, 0x000, 0), /* MX51_PAD_EIM_A16__OSC_FREQ_SEL0 */
361 IMX_PIN_REG(MX51_PAD_EIM_A17, 0x434, 0x0a0, 0, 0x000, 0), /* MX51_PAD_EIM_A17__EIM_A17 */
362 IMX_PIN_REG(MX51_PAD_EIM_A17, 0x434, 0x0a0, 1, 0x000, 0), /* MX51_PAD_EIM_A17__GPIO2_11 */
363 IMX_PIN_REG(MX51_PAD_EIM_A17, 0x434, 0x0a0, 7, 0x000, 0), /* MX51_PAD_EIM_A17__OSC_FREQ_SEL1 */
364 IMX_PIN_REG(MX51_PAD_EIM_A18, 0x438, 0x0a4, 7, 0x000, 0), /* MX51_PAD_EIM_A18__BOOT_LPB0 */
365 IMX_PIN_REG(MX51_PAD_EIM_A18, 0x438, 0x0a4, 0, 0x000, 0), /* MX51_PAD_EIM_A18__EIM_A18 */
366 IMX_PIN_REG(MX51_PAD_EIM_A18, 0x438, 0x0a4, 1, 0x000, 0), /* MX51_PAD_EIM_A18__GPIO2_12 */
367 IMX_PIN_REG(MX51_PAD_EIM_A19, 0x43c, 0x0a8, 7, 0x000, 0), /* MX51_PAD_EIM_A19__BOOT_LPB1 */
368 IMX_PIN_REG(MX51_PAD_EIM_A19, 0x43c, 0x0a8, 0, 0x000, 0), /* MX51_PAD_EIM_A19__EIM_A19 */
369 IMX_PIN_REG(MX51_PAD_EIM_A19, 0x43c, 0x0a8, 1, 0x000, 0), /* MX51_PAD_EIM_A19__GPIO2_13 */
370 IMX_PIN_REG(MX51_PAD_EIM_A20, 0x440, 0x0ac, 7, 0x000, 0), /* MX51_PAD_EIM_A20__BOOT_UART_SRC0 */
371 IMX_PIN_REG(MX51_PAD_EIM_A20, 0x440, 0x0ac, 0, 0x000, 0), /* MX51_PAD_EIM_A20__EIM_A20 */
372 IMX_PIN_REG(MX51_PAD_EIM_A20, 0x440, 0x0ac, 1, 0x000, 0), /* MX51_PAD_EIM_A20__GPIO2_14 */
373 IMX_PIN_REG(MX51_PAD_EIM_A21, 0x444, 0x0b0, 7, 0x000, 0), /* MX51_PAD_EIM_A21__BOOT_UART_SRC1 */
374 IMX_PIN_REG(MX51_PAD_EIM_A21, 0x444, 0x0b0, 0, 0x000, 0), /* MX51_PAD_EIM_A21__EIM_A21 */
375 IMX_PIN_REG(MX51_PAD_EIM_A21, 0x444, 0x0b0, 1, 0x000, 0), /* MX51_PAD_EIM_A21__GPIO2_15 */
376 IMX_PIN_REG(MX51_PAD_EIM_A22, 0x448, 0x0b4, 0, 0x000, 0), /* MX51_PAD_EIM_A22__EIM_A22 */
377 IMX_PIN_REG(MX51_PAD_EIM_A22, 0x448, 0x0b4, 1, 0x000, 0), /* MX51_PAD_EIM_A22__GPIO2_16 */
378 IMX_PIN_REG(MX51_PAD_EIM_A23, 0x44c, 0x0b8, 7, 0x000, 0), /* MX51_PAD_EIM_A23__BOOT_HPN_EN */
379 IMX_PIN_REG(MX51_PAD_EIM_A23, 0x44c, 0x0b8, 0, 0x000, 0), /* MX51_PAD_EIM_A23__EIM_A23 */
380 IMX_PIN_REG(MX51_PAD_EIM_A23, 0x44c, 0x0b8, 1, 0x000, 0), /* MX51_PAD_EIM_A23__GPIO2_17 */
381 IMX_PIN_REG(MX51_PAD_EIM_A24, 0x450, 0x0bc, 0, 0x000, 0), /* MX51_PAD_EIM_A24__EIM_A24 */
382 IMX_PIN_REG(MX51_PAD_EIM_A24, 0x450, 0x0bc, 1, 0x000, 0), /* MX51_PAD_EIM_A24__GPIO2_18 */
383 IMX_PIN_REG(MX51_PAD_EIM_A24, 0x450, 0x0bc, 2, 0x000, 0), /* MX51_PAD_EIM_A24__USBH2_CLK */
384 IMX_PIN_REG(MX51_PAD_EIM_A25, 0x454, 0x0c0, 6, 0x000, 0), /* MX51_PAD_EIM_A25__DISP1_PIN4 */
385 IMX_PIN_REG(MX51_PAD_EIM_A25, 0x454, 0x0c0, 0, 0x000, 0), /* MX51_PAD_EIM_A25__EIM_A25 */
386 IMX_PIN_REG(MX51_PAD_EIM_A25, 0x454, 0x0c0, 1, 0x000, 0), /* MX51_PAD_EIM_A25__GPIO2_19 */
387 IMX_PIN_REG(MX51_PAD_EIM_A25, 0x454, 0x0c0, 2, 0x000, 0), /* MX51_PAD_EIM_A25__USBH2_DIR */
388 IMX_PIN_REG(MX51_PAD_EIM_A26, 0x458, 0x0c4, 5, 0x9a0, 0), /* MX51_PAD_EIM_A26__CSI1_DATA_EN */
389 IMX_PIN_REG(MX51_PAD_EIM_A26, 0x458, 0x0c4, 6, 0x908, 0), /* MX51_PAD_EIM_A26__DISP2_EXT_CLK */
390 IMX_PIN_REG(MX51_PAD_EIM_A26, 0x458, 0x0c4, 0, 0x000, 0), /* MX51_PAD_EIM_A26__EIM_A26 */
391 IMX_PIN_REG(MX51_PAD_EIM_A26, 0x458, 0x0c4, 1, 0x000, 0), /* MX51_PAD_EIM_A26__GPIO2_20 */
392 IMX_PIN_REG(MX51_PAD_EIM_A26, 0x458, 0x0c4, 2, 0x000, 0), /* MX51_PAD_EIM_A26__USBH2_STP */
393 IMX_PIN_REG(MX51_PAD_EIM_A27, 0x45c, 0x0c8, 5, 0x99c, 0), /* MX51_PAD_EIM_A27__CSI2_DATA_EN */
394 IMX_PIN_REG(MX51_PAD_EIM_A27, 0x45c, 0x0c8, 6, 0x9a4, 0), /* MX51_PAD_EIM_A27__DISP1_PIN1 */
395 IMX_PIN_REG(MX51_PAD_EIM_A27, 0x45c, 0x0c8, 0, 0x000, 0), /* MX51_PAD_EIM_A27__EIM_A27 */
396 IMX_PIN_REG(MX51_PAD_EIM_A27, 0x45c, 0x0c8, 1, 0x000, 0), /* MX51_PAD_EIM_A27__GPIO2_21 */
397 IMX_PIN_REG(MX51_PAD_EIM_A27, 0x45c, 0x0c8, 2, 0x000, 0), /* MX51_PAD_EIM_A27__USBH2_NXT */
398 IMX_PIN_REG(MX51_PAD_EIM_EB0, 0x460, 0x0cc, 0, 0x000, 0), /* MX51_PAD_EIM_EB0__EIM_EB0 */
399 IMX_PIN_REG(MX51_PAD_EIM_EB1, 0x464, 0x0d0, 0, 0x000, 0), /* MX51_PAD_EIM_EB1__EIM_EB1 */
400 IMX_PIN_REG(MX51_PAD_EIM_EB2, 0x468, 0x0d4, 6, 0x8e0, 0), /* MX51_PAD_EIM_EB2__AUD5_RXFS */
401 IMX_PIN_REG(MX51_PAD_EIM_EB2, 0x468, 0x0d4, 5, 0x000, 0), /* MX51_PAD_EIM_EB2__CSI1_D2 */
402 IMX_PIN_REG(MX51_PAD_EIM_EB2, 0x468, 0x0d4, 0, 0x000, 0), /* MX51_PAD_EIM_EB2__EIM_EB2 */
403 IMX_PIN_REG(MX51_PAD_EIM_EB2, 0x468, 0x0d4, 3, 0x954, 0), /* MX51_PAD_EIM_EB2__FEC_MDIO */
404 IMX_PIN_REG(MX51_PAD_EIM_EB2, 0x468, 0x0d4, 1, 0x000, 0), /* MX51_PAD_EIM_EB2__GPIO2_22 */
405 IMX_PIN_REG(MX51_PAD_EIM_EB2, 0x468, 0x0d4, 7, 0x000, 0), /* MX51_PAD_EIM_EB2__GPT_CMPOUT1 */
406 IMX_PIN_REG(MX51_PAD_EIM_EB3, 0x46c, 0x0d8, 6, 0x8dc, 0), /* MX51_PAD_EIM_EB3__AUD5_RXC */
407 IMX_PIN_REG(MX51_PAD_EIM_EB3, 0x46c, 0x0d8, 5, 0x000, 0), /* MX51_PAD_EIM_EB3__CSI1_D3 */
408 IMX_PIN_REG(MX51_PAD_EIM_EB3, 0x46c, 0x0d8, 0, 0x000, 0), /* MX51_PAD_EIM_EB3__EIM_EB3 */
409 IMX_PIN_REG(MX51_PAD_EIM_EB3, 0x46c, 0x0d8, 3, 0x95c, 0), /* MX51_PAD_EIM_EB3__FEC_RDATA1 */
410 IMX_PIN_REG(MX51_PAD_EIM_EB3, 0x46c, 0x0d8, 1, 0x000, 0), /* MX51_PAD_EIM_EB3__GPIO2_23 */
411 IMX_PIN_REG(MX51_PAD_EIM_EB3, 0x46c, 0x0d8, 7, 0x000, 0), /* MX51_PAD_EIM_EB3__GPT_CMPOUT2 */
412 IMX_PIN_REG(MX51_PAD_EIM_OE, 0x470, 0x0dc, 0, 0x000, 0), /* MX51_PAD_EIM_OE__EIM_OE */
413 IMX_PIN_REG(MX51_PAD_EIM_OE, 0x470, 0x0dc, 1, 0x000, 0), /* MX51_PAD_EIM_OE__GPIO2_24 */
414 IMX_PIN_REG(MX51_PAD_EIM_CS0, 0x474, 0x0e0, 0, 0x000, 0), /* MX51_PAD_EIM_CS0__EIM_CS0 */
415 IMX_PIN_REG(MX51_PAD_EIM_CS0, 0x474, 0x0e0, 1, 0x000, 0), /* MX51_PAD_EIM_CS0__GPIO2_25 */
416 IMX_PIN_REG(MX51_PAD_EIM_CS1, 0x478, 0x0e4, 0, 0x000, 0), /* MX51_PAD_EIM_CS1__EIM_CS1 */
417 IMX_PIN_REG(MX51_PAD_EIM_CS1, 0x478, 0x0e4, 1, 0x000, 0), /* MX51_PAD_EIM_CS1__GPIO2_26 */
418 IMX_PIN_REG(MX51_PAD_EIM_CS2, 0x47c, 0x0e8, 6, 0x8d8, 1), /* MX51_PAD_EIM_CS2__AUD5_TXD */
419 IMX_PIN_REG(MX51_PAD_EIM_CS2, 0x47c, 0x0e8, 5, 0x000, 0), /* MX51_PAD_EIM_CS2__CSI1_D4 */
420 IMX_PIN_REG(MX51_PAD_EIM_CS2, 0x47c, 0x0e8, 0, 0x000, 0), /* MX51_PAD_EIM_CS2__EIM_CS2 */
421 IMX_PIN_REG(MX51_PAD_EIM_CS2, 0x47c, 0x0e8, 3, 0x960, 0), /* MX51_PAD_EIM_CS2__FEC_RDATA2 */
422 IMX_PIN_REG(MX51_PAD_EIM_CS2, 0x47c, 0x0e8, 1, 0x000, 0), /* MX51_PAD_EIM_CS2__GPIO2_27 */
423 IMX_PIN_REG(MX51_PAD_EIM_CS2, 0x47c, 0x0e8, 2, 0x000, 0), /* MX51_PAD_EIM_CS2__USBOTG_STP */
424 IMX_PIN_REG(MX51_PAD_EIM_CS3, 0x480, 0x0ec, 6, 0x8d4, 1), /* MX51_PAD_EIM_CS3__AUD5_RXD */
425 IMX_PIN_REG(MX51_PAD_EIM_CS3, 0x480, 0x0ec, 5, 0x000, 0), /* MX51_PAD_EIM_CS3__CSI1_D5 */
426 IMX_PIN_REG(MX51_PAD_EIM_CS3, 0x480, 0x0ec, 0, 0x000, 0), /* MX51_PAD_EIM_CS3__EIM_CS3 */
427 IMX_PIN_REG(MX51_PAD_EIM_CS3, 0x480, 0x0ec, 3, 0x964, 0), /* MX51_PAD_EIM_CS3__FEC_RDATA3 */
428 IMX_PIN_REG(MX51_PAD_EIM_CS3, 0x480, 0x0ec, 1, 0x000, 0), /* MX51_PAD_EIM_CS3__GPIO2_28 */
429 IMX_PIN_REG(MX51_PAD_EIM_CS3, 0x480, 0x0ec, 2, 0x000, 0), /* MX51_PAD_EIM_CS3__USBOTG_NXT */
430 IMX_PIN_REG(MX51_PAD_EIM_CS4, 0x484, 0x0f0, 6, 0x8e4, 1), /* MX51_PAD_EIM_CS4__AUD5_TXC */
431 IMX_PIN_REG(MX51_PAD_EIM_CS4, 0x484, 0x0f0, 5, 0x000, 0), /* MX51_PAD_EIM_CS4__CSI1_D6 */
432 IMX_PIN_REG(MX51_PAD_EIM_CS4, 0x484, 0x0f0, 0, 0x000, 0), /* MX51_PAD_EIM_CS4__EIM_CS4 */
433 IMX_PIN_REG(MX51_PAD_EIM_CS4, 0x484, 0x0f0, 3, 0x970, 0), /* MX51_PAD_EIM_CS4__FEC_RX_ER */
434 IMX_PIN_REG(MX51_PAD_EIM_CS4, 0x484, 0x0f0, 1, 0x000, 0), /* MX51_PAD_EIM_CS4__GPIO2_29 */
435 IMX_PIN_REG(MX51_PAD_EIM_CS4, 0x484, 0x0f0, 2, 0x000, 0), /* MX51_PAD_EIM_CS4__USBOTG_CLK */
436 IMX_PIN_REG(MX51_PAD_EIM_CS5, 0x488, 0x0f4, 6, 0x8e8, 1), /* MX51_PAD_EIM_CS5__AUD5_TXFS */
437 IMX_PIN_REG(MX51_PAD_EIM_CS5, 0x488, 0x0f4, 5, 0x000, 0), /* MX51_PAD_EIM_CS5__CSI1_D7 */
438 IMX_PIN_REG(MX51_PAD_EIM_CS5, 0x488, 0x0f4, 4, 0x904, 0), /* MX51_PAD_EIM_CS5__DISP1_EXT_CLK */
439 IMX_PIN_REG(MX51_PAD_EIM_CS5, 0x488, 0x0f4, 0, 0x000, 0), /* MX51_PAD_EIM_CS5__EIM_CS5 */
440 IMX_PIN_REG(MX51_PAD_EIM_CS5, 0x488, 0x0f4, 3, 0x950, 0), /* MX51_PAD_EIM_CS5__FEC_CRS */
441 IMX_PIN_REG(MX51_PAD_EIM_CS5, 0x488, 0x0f4, 1, 0x000, 0), /* MX51_PAD_EIM_CS5__GPIO2_30 */
442 IMX_PIN_REG(MX51_PAD_EIM_CS5, 0x488, 0x0f4, 2, 0x000, 0), /* MX51_PAD_EIM_CS5__USBOTG_DIR */
443 IMX_PIN_REG(MX51_PAD_EIM_DTACK, 0x48c, 0x0f8, 0, 0x000, 0), /* MX51_PAD_EIM_DTACK__EIM_DTACK */
444 IMX_PIN_REG(MX51_PAD_EIM_DTACK, 0x48c, 0x0f8, 1, 0x000, 0), /* MX51_PAD_EIM_DTACK__GPIO2_31 */
445 IMX_PIN_REG(MX51_PAD_EIM_LBA, 0x494, 0x0fc, 0, 0x000, 0), /* MX51_PAD_EIM_LBA__EIM_LBA */
446 IMX_PIN_REG(MX51_PAD_EIM_LBA, 0x494, 0x0fc, 1, 0x978, 0), /* MX51_PAD_EIM_LBA__GPIO3_1 */
447 IMX_PIN_REG(MX51_PAD_EIM_CRE, 0x4a0, 0x100, 0, 0x000, 0), /* MX51_PAD_EIM_CRE__EIM_CRE */
448 IMX_PIN_REG(MX51_PAD_EIM_CRE, 0x4a0, 0x100, 1, 0x97c, 0), /* MX51_PAD_EIM_CRE__GPIO3_2 */
449 IMX_PIN_REG(MX51_PAD_DRAM_CS1, 0x4d0, 0x104, 0, 0x000, 0), /* MX51_PAD_DRAM_CS1__DRAM_CS1 */
450 IMX_PIN_REG(MX51_PAD_NANDF_WE_B, 0x4e4, 0x108, 3, 0x980, 0), /* MX51_PAD_NANDF_WE_B__GPIO3_3 */
451 IMX_PIN_REG(MX51_PAD_NANDF_WE_B, 0x4e4, 0x108, 0, 0x000, 0), /* MX51_PAD_NANDF_WE_B__NANDF_WE_B */
452 IMX_PIN_REG(MX51_PAD_NANDF_WE_B, 0x4e4, 0x108, 1, 0x000, 0), /* MX51_PAD_NANDF_WE_B__PATA_DIOW */
453 IMX_PIN_REG(MX51_PAD_NANDF_WE_B, 0x4e4, 0x108, 2, 0x93c, 0), /* MX51_PAD_NANDF_WE_B__SD3_DATA0 */
454 IMX_PIN_REG(MX51_PAD_NANDF_RE_B, 0x4e8, 0x10c, 3, 0x984, 0), /* MX51_PAD_NANDF_RE_B__GPIO3_4 */
455 IMX_PIN_REG(MX51_PAD_NANDF_RE_B, 0x4e8, 0x10c, 0, 0x000, 0), /* MX51_PAD_NANDF_RE_B__NANDF_RE_B */
456 IMX_PIN_REG(MX51_PAD_NANDF_RE_B, 0x4e8, 0x10c, 1, 0x000, 0), /* MX51_PAD_NANDF_RE_B__PATA_DIOR */
457 IMX_PIN_REG(MX51_PAD_NANDF_RE_B, 0x4e8, 0x10c, 2, 0x940, 0), /* MX51_PAD_NANDF_RE_B__SD3_DATA1 */
458 IMX_PIN_REG(MX51_PAD_NANDF_ALE, 0x4ec, 0x110, 3, 0x988, 0), /* MX51_PAD_NANDF_ALE__GPIO3_5 */
459 IMX_PIN_REG(MX51_PAD_NANDF_ALE, 0x4ec, 0x110, 0, 0x000, 0), /* MX51_PAD_NANDF_ALE__NANDF_ALE */
460 IMX_PIN_REG(MX51_PAD_NANDF_ALE, 0x4ec, 0x110, 1, 0x000, 0), /* MX51_PAD_NANDF_ALE__PATA_BUFFER_EN */
461 IMX_PIN_REG(MX51_PAD_NANDF_CLE, 0x4f0, 0x114, 3, 0x98c, 0), /* MX51_PAD_NANDF_CLE__GPIO3_6 */
462 IMX_PIN_REG(MX51_PAD_NANDF_CLE, 0x4f0, 0x114, 0, 0x000, 0), /* MX51_PAD_NANDF_CLE__NANDF_CLE */
463 IMX_PIN_REG(MX51_PAD_NANDF_CLE, 0x4f0, 0x114, 1, 0x000, 0), /* MX51_PAD_NANDF_CLE__PATA_RESET_B */
464 IMX_PIN_REG(MX51_PAD_NANDF_WP_B, 0x4f4, 0x118, 3, 0x990, 0), /* MX51_PAD_NANDF_WP_B__GPIO3_7 */
465 IMX_PIN_REG(MX51_PAD_NANDF_WP_B, 0x4f4, 0x118, 0, 0x000, 0), /* MX51_PAD_NANDF_WP_B__NANDF_WP_B */
466 IMX_PIN_REG(MX51_PAD_NANDF_WP_B, 0x4f4, 0x118, 1, 0x000, 0), /* MX51_PAD_NANDF_WP_B__PATA_DMACK */
467 IMX_PIN_REG(MX51_PAD_NANDF_WP_B, 0x4f4, 0x118, 2, 0x944, 0), /* MX51_PAD_NANDF_WP_B__SD3_DATA2 */
468 IMX_PIN_REG(MX51_PAD_NANDF_RB0, 0x4f8, 0x11c, 5, 0x930, 0), /* MX51_PAD_NANDF_RB0__ECSPI2_SS1 */
469 IMX_PIN_REG(MX51_PAD_NANDF_RB0, 0x4f8, 0x11c, 3, 0x994, 0), /* MX51_PAD_NANDF_RB0__GPIO3_8 */
470 IMX_PIN_REG(MX51_PAD_NANDF_RB0, 0x4f8, 0x11c, 0, 0x000, 0), /* MX51_PAD_NANDF_RB0__NANDF_RB0 */
471 IMX_PIN_REG(MX51_PAD_NANDF_RB0, 0x4f8, 0x11c, 1, 0x000, 0), /* MX51_PAD_NANDF_RB0__PATA_DMARQ */
472 IMX_PIN_REG(MX51_PAD_NANDF_RB0, 0x4f8, 0x11c, 2, 0x948, 0), /* MX51_PAD_NANDF_RB0__SD3_DATA3 */
473 IMX_PIN_REG(MX51_PAD_NANDF_RB1, 0x4fc, 0x120, 6, 0x91c, 0), /* MX51_PAD_NANDF_RB1__CSPI_MOSI */
474 IMX_PIN_REG(MX51_PAD_NANDF_RB1, 0x4fc, 0x120, 2, 0x000, 0), /* MX51_PAD_NANDF_RB1__ECSPI2_RDY */
475 IMX_PIN_REG(MX51_PAD_NANDF_RB1, 0x4fc, 0x120, 3, 0x000, 0), /* MX51_PAD_NANDF_RB1__GPIO3_9 */
476 IMX_PIN_REG(MX51_PAD_NANDF_RB1, 0x4fc, 0x120, 0, 0x000, 0), /* MX51_PAD_NANDF_RB1__NANDF_RB1 */
477 IMX_PIN_REG(MX51_PAD_NANDF_RB1, 0x4fc, 0x120, 1, 0x000, 0), /* MX51_PAD_NANDF_RB1__PATA_IORDY */
478 IMX_PIN_REG(MX51_PAD_NANDF_RB1, 0x4fc, 0x120, 5, 0x000, 0), /* MX51_PAD_NANDF_RB1__SD4_CMD */
479 IMX_PIN_REG(MX51_PAD_NANDF_RB2, 0x500, 0x124, 5, 0x9a8, 0), /* MX51_PAD_NANDF_RB2__DISP2_WAIT */
480 IMX_PIN_REG(MX51_PAD_NANDF_RB2, 0x500, 0x124, 2, 0x000, 0), /* MX51_PAD_NANDF_RB2__ECSPI2_SCLK */
481 IMX_PIN_REG(MX51_PAD_NANDF_RB2, 0x500, 0x124, 1, 0x94c, 0), /* MX51_PAD_NANDF_RB2__FEC_COL */
482 IMX_PIN_REG(MX51_PAD_NANDF_RB2, 0x500, 0x124, 3, 0x000, 0), /* MX51_PAD_NANDF_RB2__GPIO3_10 */
483 IMX_PIN_REG(MX51_PAD_NANDF_RB2, 0x500, 0x124, 0, 0x000, 0), /* MX51_PAD_NANDF_RB2__NANDF_RB2 */
484 IMX_PIN_REG(MX51_PAD_NANDF_RB2, 0x500, 0x124, 7, 0x000, 0), /* MX51_PAD_NANDF_RB2__USBH3_H3_DP */
485 IMX_PIN_REG(MX51_PAD_NANDF_RB2, 0x500, 0x124, 6, 0xa20, 0), /* MX51_PAD_NANDF_RB2__USBH3_NXT */
486 IMX_PIN_REG(MX51_PAD_NANDF_RB3, 0x504, 0x128, 5, 0x000, 0), /* MX51_PAD_NANDF_RB3__DISP1_WAIT */
487 IMX_PIN_REG(MX51_PAD_NANDF_RB3, 0x504, 0x128, 2, 0x000, 0), /* MX51_PAD_NANDF_RB3__ECSPI2_MISO */
488 IMX_PIN_REG(MX51_PAD_NANDF_RB3, 0x504, 0x128, 1, 0x968, 0), /* MX51_PAD_NANDF_RB3__FEC_RX_CLK */
489 IMX_PIN_REG(MX51_PAD_NANDF_RB3, 0x504, 0x128, 3, 0x000, 0), /* MX51_PAD_NANDF_RB3__GPIO3_11 */
490 IMX_PIN_REG(MX51_PAD_NANDF_RB3, 0x504, 0x128, 0, 0x000, 0), /* MX51_PAD_NANDF_RB3__NANDF_RB3 */
491 IMX_PIN_REG(MX51_PAD_NANDF_RB3, 0x504, 0x128, 6, 0x9f8, 0), /* MX51_PAD_NANDF_RB3__USBH3_CLK */
492 IMX_PIN_REG(MX51_PAD_NANDF_RB3, 0x504, 0x128, 7, 0x000, 0), /* MX51_PAD_NANDF_RB3__USBH3_H3_DM */
493 IMX_PIN_REG(MX51_PAD_GPIO_NAND, 0x514, 0x12c, 0, 0x998, 0), /* MX51_PAD_GPIO_NAND__GPIO_NAND */
494 IMX_PIN_REG(MX51_PAD_GPIO_NAND, 0x514, 0x12c, 1, 0x000, 0), /* MX51_PAD_GPIO_NAND__PATA_INTRQ */
495 IMX_PIN_REG(MX51_PAD_NANDF_CS0, 0x518, 0x130, 3, 0x000, 0), /* MX51_PAD_NANDF_CS0__GPIO3_16 */
496 IMX_PIN_REG(MX51_PAD_NANDF_CS0, 0x518, 0x130, 0, 0x000, 0), /* MX51_PAD_NANDF_CS0__NANDF_CS0 */
497 IMX_PIN_REG(MX51_PAD_NANDF_CS1, 0x51c, 0x134, 3, 0x000, 0), /* MX51_PAD_NANDF_CS1__GPIO3_17 */
498 IMX_PIN_REG(MX51_PAD_NANDF_CS1, 0x51c, 0x134, 0, 0x000, 0), /* MX51_PAD_NANDF_CS1__NANDF_CS1 */
499 IMX_PIN_REG(MX51_PAD_NANDF_CS2, 0x520, 0x138, 6, 0x914, 0), /* MX51_PAD_NANDF_CS2__CSPI_SCLK */
500 IMX_PIN_REG(MX51_PAD_NANDF_CS2, 0x520, 0x138, 2, 0x000, 0), /* MX51_PAD_NANDF_CS2__FEC_TX_ER */
501 IMX_PIN_REG(MX51_PAD_NANDF_CS2, 0x520, 0x138, 3, 0x000, 0), /* MX51_PAD_NANDF_CS2__GPIO3_18 */
502 IMX_PIN_REG(MX51_PAD_NANDF_CS2, 0x520, 0x138, 0, 0x000, 0), /* MX51_PAD_NANDF_CS2__NANDF_CS2 */
503 IMX_PIN_REG(MX51_PAD_NANDF_CS2, 0x520, 0x138, 1, 0x000, 0), /* MX51_PAD_NANDF_CS2__PATA_CS_0 */
504 IMX_PIN_REG(MX51_PAD_NANDF_CS2, 0x520, 0x138, 5, 0x000, 0), /* MX51_PAD_NANDF_CS2__SD4_CLK */
505 IMX_PIN_REG(MX51_PAD_NANDF_CS2, 0x520, 0x138, 7, 0x000, 0), /* MX51_PAD_NANDF_CS2__USBH3_H1_DP */
506 IMX_PIN_REG(MX51_PAD_NANDF_CS3, 0x524, 0x13c, 2, 0x000, 0), /* MX51_PAD_NANDF_CS3__FEC_MDC */
507 IMX_PIN_REG(MX51_PAD_NANDF_CS3, 0x524, 0x13c, 3, 0x000, 0), /* MX51_PAD_NANDF_CS3__GPIO3_19 */
508 IMX_PIN_REG(MX51_PAD_NANDF_CS3, 0x524, 0x13c, 0, 0x000, 0), /* MX51_PAD_NANDF_CS3__NANDF_CS3 */
509 IMX_PIN_REG(MX51_PAD_NANDF_CS3, 0x524, 0x13c, 1, 0x000, 0), /* MX51_PAD_NANDF_CS3__PATA_CS_1 */
510 IMX_PIN_REG(MX51_PAD_NANDF_CS3, 0x524, 0x13c, 5, 0x000, 0), /* MX51_PAD_NANDF_CS3__SD4_DAT0 */
511 IMX_PIN_REG(MX51_PAD_NANDF_CS3, 0x524, 0x13c, 7, 0x000, 0), /* MX51_PAD_NANDF_CS3__USBH3_H1_DM */
512 IMX_PIN_REG(MX51_PAD_NANDF_CS4, 0x528, 0x140, 2, 0x000, 0), /* MX51_PAD_NANDF_CS4__FEC_TDATA1 */
513 IMX_PIN_REG(MX51_PAD_NANDF_CS4, 0x528, 0x140, 3, 0x000, 0), /* MX51_PAD_NANDF_CS4__GPIO3_20 */
514 IMX_PIN_REG(MX51_PAD_NANDF_CS4, 0x528, 0x140, 0, 0x000, 0), /* MX51_PAD_NANDF_CS4__NANDF_CS4 */
515 IMX_PIN_REG(MX51_PAD_NANDF_CS4, 0x528, 0x140, 1, 0x000, 0), /* MX51_PAD_NANDF_CS4__PATA_DA_0 */
516 IMX_PIN_REG(MX51_PAD_NANDF_CS4, 0x528, 0x140, 5, 0x000, 0), /* MX51_PAD_NANDF_CS4__SD4_DAT1 */
517 IMX_PIN_REG(MX51_PAD_NANDF_CS4, 0x528, 0x140, 7, 0xa24, 0), /* MX51_PAD_NANDF_CS4__USBH3_STP */
518 IMX_PIN_REG(MX51_PAD_NANDF_CS5, 0x52c, 0x144, 2, 0x000, 0), /* MX51_PAD_NANDF_CS5__FEC_TDATA2 */
519 IMX_PIN_REG(MX51_PAD_NANDF_CS5, 0x52c, 0x144, 3, 0x000, 0), /* MX51_PAD_NANDF_CS5__GPIO3_21 */
520 IMX_PIN_REG(MX51_PAD_NANDF_CS5, 0x52c, 0x144, 0, 0x000, 0), /* MX51_PAD_NANDF_CS5__NANDF_CS5 */
521 IMX_PIN_REG(MX51_PAD_NANDF_CS5, 0x52c, 0x144, 1, 0x000, 0), /* MX51_PAD_NANDF_CS5__PATA_DA_1 */
522 IMX_PIN_REG(MX51_PAD_NANDF_CS5, 0x52c, 0x144, 5, 0x000, 0), /* MX51_PAD_NANDF_CS5__SD4_DAT2 */
523 IMX_PIN_REG(MX51_PAD_NANDF_CS5, 0x52c, 0x144, 7, 0xa1c, 0), /* MX51_PAD_NANDF_CS5__USBH3_DIR */
524 IMX_PIN_REG(MX51_PAD_NANDF_CS6, 0x530, 0x148, 7, 0x928, 0), /* MX51_PAD_NANDF_CS6__CSPI_SS3 */
525 IMX_PIN_REG(MX51_PAD_NANDF_CS6, 0x530, 0x148, 2, 0x000, 0), /* MX51_PAD_NANDF_CS6__FEC_TDATA3 */
526 IMX_PIN_REG(MX51_PAD_NANDF_CS6, 0x530, 0x148, 3, 0x000, 0), /* MX51_PAD_NANDF_CS6__GPIO3_22 */
527 IMX_PIN_REG(MX51_PAD_NANDF_CS6, 0x530, 0x148, 0, 0x000, 0), /* MX51_PAD_NANDF_CS6__NANDF_CS6 */
528 IMX_PIN_REG(MX51_PAD_NANDF_CS6, 0x530, 0x148, 1, 0x000, 0), /* MX51_PAD_NANDF_CS6__PATA_DA_2 */
529 IMX_PIN_REG(MX51_PAD_NANDF_CS6, 0x530, 0x148, 5, 0x000, 0), /* MX51_PAD_NANDF_CS6__SD4_DAT3 */
530 IMX_PIN_REG(MX51_PAD_NANDF_CS7, 0x534, 0x14c, 1, 0x000, 0), /* MX51_PAD_NANDF_CS7__FEC_TX_EN */
531 IMX_PIN_REG(MX51_PAD_NANDF_CS7, 0x534, 0x14c, 3, 0x000, 0), /* MX51_PAD_NANDF_CS7__GPIO3_23 */
532 IMX_PIN_REG(MX51_PAD_NANDF_CS7, 0x534, 0x14c, 0, 0x000, 0), /* MX51_PAD_NANDF_CS7__NANDF_CS7 */
533 IMX_PIN_REG(MX51_PAD_NANDF_CS7, 0x534, 0x14c, 5, 0x000, 0), /* MX51_PAD_NANDF_CS7__SD3_CLK */
534 IMX_PIN_REG(MX51_PAD_NANDF_RDY_INT, 0x538, 0x150, 2, 0x000, 0), /* MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 */
535 IMX_PIN_REG(MX51_PAD_NANDF_RDY_INT, 0x538, 0x150, 1, 0x974, 0), /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */
536 IMX_PIN_REG(MX51_PAD_NANDF_RDY_INT, 0x538, 0x150, 3, 0x000, 0), /* MX51_PAD_NANDF_RDY_INT__GPIO3_24 */
537 IMX_PIN_REG(MX51_PAD_NANDF_RDY_INT, 0x538, 0x150, 0, 0x938, 0), /* MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT */
538 IMX_PIN_REG(MX51_PAD_NANDF_RDY_INT, 0x538, 0x150, 5, 0x000, 0), /* MX51_PAD_NANDF_RDY_INT__SD3_CMD */
539 IMX_PIN_REG(MX51_PAD_NANDF_D15, 0x53c, 0x154, 2, 0x000, 0), /* MX51_PAD_NANDF_D15__ECSPI2_MOSI */
540 IMX_PIN_REG(MX51_PAD_NANDF_D15, 0x53c, 0x154, 3, 0x000, 0), /* MX51_PAD_NANDF_D15__GPIO3_25 */
541 IMX_PIN_REG(MX51_PAD_NANDF_D15, 0x53c, 0x154, 0, 0x000, 0), /* MX51_PAD_NANDF_D15__NANDF_D15 */
542 IMX_PIN_REG(MX51_PAD_NANDF_D15, 0x53c, 0x154, 1, 0x000, 0), /* MX51_PAD_NANDF_D15__PATA_DATA15 */
543 IMX_PIN_REG(MX51_PAD_NANDF_D15, 0x53c, 0x154, 5, 0x000, 0), /* MX51_PAD_NANDF_D15__SD3_DAT7 */
544 IMX_PIN_REG(MX51_PAD_NANDF_D14, 0x540, 0x158, 2, 0x934, 0), /* MX51_PAD_NANDF_D14__ECSPI2_SS3 */
545 IMX_PIN_REG(MX51_PAD_NANDF_D14, 0x540, 0x158, 3, 0x000, 0), /* MX51_PAD_NANDF_D14__GPIO3_26 */
546 IMX_PIN_REG(MX51_PAD_NANDF_D14, 0x540, 0x158, 0, 0x000, 0), /* MX51_PAD_NANDF_D14__NANDF_D14 */
547 IMX_PIN_REG(MX51_PAD_NANDF_D14, 0x540, 0x158, 1, 0x000, 0), /* MX51_PAD_NANDF_D14__PATA_DATA14 */
548 IMX_PIN_REG(MX51_PAD_NANDF_D14, 0x540, 0x158, 5, 0x000, 0), /* MX51_PAD_NANDF_D14__SD3_DAT6 */
549 IMX_PIN_REG(MX51_PAD_NANDF_D13, 0x544, 0x15c, 2, 0x000, 0), /* MX51_PAD_NANDF_D13__ECSPI2_SS2 */
550 IMX_PIN_REG(MX51_PAD_NANDF_D13, 0x544, 0x15c, 3, 0x000, 0), /* MX51_PAD_NANDF_D13__GPIO3_27 */
551 IMX_PIN_REG(MX51_PAD_NANDF_D13, 0x544, 0x15c, 0, 0x000, 0), /* MX51_PAD_NANDF_D13__NANDF_D13 */
552 IMX_PIN_REG(MX51_PAD_NANDF_D13, 0x544, 0x15c, 1, 0x000, 0), /* MX51_PAD_NANDF_D13__PATA_DATA13 */
553 IMX_PIN_REG(MX51_PAD_NANDF_D13, 0x544, 0x15c, 5, 0x000, 0), /* MX51_PAD_NANDF_D13__SD3_DAT5 */
554 IMX_PIN_REG(MX51_PAD_NANDF_D12, 0x548, 0x160, 2, 0x930, 1), /* MX51_PAD_NANDF_D12__ECSPI2_SS1 */
555 IMX_PIN_REG(MX51_PAD_NANDF_D12, 0x548, 0x160, 3, 0x000, 0), /* MX51_PAD_NANDF_D12__GPIO3_28 */
556 IMX_PIN_REG(MX51_PAD_NANDF_D12, 0x548, 0x160, 0, 0x000, 0), /* MX51_PAD_NANDF_D12__NANDF_D12 */
557 IMX_PIN_REG(MX51_PAD_NANDF_D12, 0x548, 0x160, 1, 0x000, 0), /* MX51_PAD_NANDF_D12__PATA_DATA12 */
558 IMX_PIN_REG(MX51_PAD_NANDF_D12, 0x548, 0x160, 5, 0x000, 0), /* MX51_PAD_NANDF_D12__SD3_DAT4 */
559 IMX_PIN_REG(MX51_PAD_NANDF_D11, 0x54c, 0x164, 2, 0x96c, 0), /* MX51_PAD_NANDF_D11__FEC_RX_DV */
560 IMX_PIN_REG(MX51_PAD_NANDF_D11, 0x54c, 0x164, 3, 0x000, 0), /* MX51_PAD_NANDF_D11__GPIO3_29 */
561 IMX_PIN_REG(MX51_PAD_NANDF_D11, 0x54c, 0x164, 0, 0x000, 0), /* MX51_PAD_NANDF_D11__NANDF_D11 */
562 IMX_PIN_REG(MX51_PAD_NANDF_D11, 0x54c, 0x164, 1, 0x000, 0), /* MX51_PAD_NANDF_D11__PATA_DATA11 */
563 IMX_PIN_REG(MX51_PAD_NANDF_D11, 0x54c, 0x164, 5, 0x948, 1), /* MX51_PAD_NANDF_D11__SD3_DATA3 */
564 IMX_PIN_REG(MX51_PAD_NANDF_D10, 0x550, 0x168, 3, 0x000, 0), /* MX51_PAD_NANDF_D10__GPIO3_30 */
565 IMX_PIN_REG(MX51_PAD_NANDF_D10, 0x550, 0x168, 0, 0x000, 0), /* MX51_PAD_NANDF_D10__NANDF_D10 */
566 IMX_PIN_REG(MX51_PAD_NANDF_D10, 0x550, 0x168, 1, 0x000, 0), /* MX51_PAD_NANDF_D10__PATA_DATA10 */
567 IMX_PIN_REG(MX51_PAD_NANDF_D10, 0x550, 0x168, 5, 0x944, 1), /* MX51_PAD_NANDF_D10__SD3_DATA2 */
568 IMX_PIN_REG(MX51_PAD_NANDF_D9, 0x554, 0x16c, 2, 0x958, 0), /* MX51_PAD_NANDF_D9__FEC_RDATA0 */
569 IMX_PIN_REG(MX51_PAD_NANDF_D9, 0x554, 0x16c, 3, 0x000, 0), /* MX51_PAD_NANDF_D9__GPIO3_31 */
570 IMX_PIN_REG(MX51_PAD_NANDF_D9, 0x554, 0x16c, 0, 0x000, 0), /* MX51_PAD_NANDF_D9__NANDF_D9 */
571 IMX_PIN_REG(MX51_PAD_NANDF_D9, 0x554, 0x16c, 1, 0x000, 0), /* MX51_PAD_NANDF_D9__PATA_DATA9 */
572 IMX_PIN_REG(MX51_PAD_NANDF_D9, 0x554, 0x16c, 5, 0x940, 1), /* MX51_PAD_NANDF_D9__SD3_DATA1 */
573 IMX_PIN_REG(MX51_PAD_NANDF_D8, 0x558, 0x170, 2, 0x000, 0), /* MX51_PAD_NANDF_D8__FEC_TDATA0 */
574 IMX_PIN_REG(MX51_PAD_NANDF_D8, 0x558, 0x170, 3, 0x000, 0), /* MX51_PAD_NANDF_D8__GPIO4_0 */
575 IMX_PIN_REG(MX51_PAD_NANDF_D8, 0x558, 0x170, 0, 0x000, 0), /* MX51_PAD_NANDF_D8__NANDF_D8 */
576 IMX_PIN_REG(MX51_PAD_NANDF_D8, 0x558, 0x170, 1, 0x000, 0), /* MX51_PAD_NANDF_D8__PATA_DATA8 */
577 IMX_PIN_REG(MX51_PAD_NANDF_D8, 0x558, 0x170, 5, 0x93c, 1), /* MX51_PAD_NANDF_D8__SD3_DATA0 */
578 IMX_PIN_REG(MX51_PAD_NANDF_D7, 0x55c, 0x174, 3, 0x000, 0), /* MX51_PAD_NANDF_D7__GPIO4_1 */
579 IMX_PIN_REG(MX51_PAD_NANDF_D7, 0x55c, 0x174, 0, 0x000, 0), /* MX51_PAD_NANDF_D7__NANDF_D7 */
580 IMX_PIN_REG(MX51_PAD_NANDF_D7, 0x55c, 0x174, 1, 0x000, 0), /* MX51_PAD_NANDF_D7__PATA_DATA7 */
581 IMX_PIN_REG(MX51_PAD_NANDF_D7, 0x55c, 0x174, 5, 0x9fc, 0), /* MX51_PAD_NANDF_D7__USBH3_DATA0 */
582 IMX_PIN_REG(MX51_PAD_NANDF_D6, 0x560, 0x178, 3, 0x000, 0), /* MX51_PAD_NANDF_D6__GPIO4_2 */
583 IMX_PIN_REG(MX51_PAD_NANDF_D6, 0x560, 0x178, 0, 0x000, 0), /* MX51_PAD_NANDF_D6__NANDF_D6 */
584 IMX_PIN_REG(MX51_PAD_NANDF_D6, 0x560, 0x178, 1, 0x000, 0), /* MX51_PAD_NANDF_D6__PATA_DATA6 */
585 IMX_PIN_REG(MX51_PAD_NANDF_D6, 0x560, 0x178, 2, 0x000, 0), /* MX51_PAD_NANDF_D6__SD4_LCTL */
586 IMX_PIN_REG(MX51_PAD_NANDF_D6, 0x560, 0x178, 5, 0xa00, 0), /* MX51_PAD_NANDF_D6__USBH3_DATA1 */
587 IMX_PIN_REG(MX51_PAD_NANDF_D5, 0x564, 0x17c, 3, 0x000, 0), /* MX51_PAD_NANDF_D5__GPIO4_3 */
588 IMX_PIN_REG(MX51_PAD_NANDF_D5, 0x564, 0x17c, 0, 0x000, 0), /* MX51_PAD_NANDF_D5__NANDF_D5 */
589 IMX_PIN_REG(MX51_PAD_NANDF_D5, 0x564, 0x17c, 1, 0x000, 0), /* MX51_PAD_NANDF_D5__PATA_DATA5 */
590 IMX_PIN_REG(MX51_PAD_NANDF_D5, 0x564, 0x17c, 2, 0x000, 0), /* MX51_PAD_NANDF_D5__SD4_WP */
591 IMX_PIN_REG(MX51_PAD_NANDF_D5, 0x564, 0x17c, 5, 0xa04, 0), /* MX51_PAD_NANDF_D5__USBH3_DATA2 */
592 IMX_PIN_REG(MX51_PAD_NANDF_D4, 0x568, 0x180, 3, 0x000, 0), /* MX51_PAD_NANDF_D4__GPIO4_4 */
593 IMX_PIN_REG(MX51_PAD_NANDF_D4, 0x568, 0x180, 0, 0x000, 0), /* MX51_PAD_NANDF_D4__NANDF_D4 */
594 IMX_PIN_REG(MX51_PAD_NANDF_D4, 0x568, 0x180, 1, 0x000, 0), /* MX51_PAD_NANDF_D4__PATA_DATA4 */
595 IMX_PIN_REG(MX51_PAD_NANDF_D4, 0x568, 0x180, 2, 0x000, 0), /* MX51_PAD_NANDF_D4__SD4_CD */
596 IMX_PIN_REG(MX51_PAD_NANDF_D4, 0x568, 0x180, 5, 0xa08, 0), /* MX51_PAD_NANDF_D4__USBH3_DATA3 */
597 IMX_PIN_REG(MX51_PAD_NANDF_D3, 0x56c, 0x184, 3, 0x000, 0), /* MX51_PAD_NANDF_D3__GPIO4_5 */
598 IMX_PIN_REG(MX51_PAD_NANDF_D3, 0x56c, 0x184, 0, 0x000, 0), /* MX51_PAD_NANDF_D3__NANDF_D3 */
599 IMX_PIN_REG(MX51_PAD_NANDF_D3, 0x56c, 0x184, 1, 0x000, 0), /* MX51_PAD_NANDF_D3__PATA_DATA3 */
600 IMX_PIN_REG(MX51_PAD_NANDF_D3, 0x56c, 0x184, 2, 0x000, 0), /* MX51_PAD_NANDF_D3__SD4_DAT4 */
601 IMX_PIN_REG(MX51_PAD_NANDF_D3, 0x56c, 0x184, 5, 0xa0c, 0), /* MX51_PAD_NANDF_D3__USBH3_DATA4 */
602 IMX_PIN_REG(MX51_PAD_NANDF_D2, 0x570, 0x188, 3, 0x000, 0), /* MX51_PAD_NANDF_D2__GPIO4_6 */
603 IMX_PIN_REG(MX51_PAD_NANDF_D2, 0x570, 0x188, 0, 0x000, 0), /* MX51_PAD_NANDF_D2__NANDF_D2 */
604 IMX_PIN_REG(MX51_PAD_NANDF_D2, 0x570, 0x188, 1, 0x000, 0), /* MX51_PAD_NANDF_D2__PATA_DATA2 */
605 IMX_PIN_REG(MX51_PAD_NANDF_D2, 0x570, 0x188, 2, 0x000, 0), /* MX51_PAD_NANDF_D2__SD4_DAT5 */
606 IMX_PIN_REG(MX51_PAD_NANDF_D2, 0x570, 0x188, 5, 0xa10, 0), /* MX51_PAD_NANDF_D2__USBH3_DATA5 */
607 IMX_PIN_REG(MX51_PAD_NANDF_D1, 0x574, 0x18c, 3, 0x000, 0), /* MX51_PAD_NANDF_D1__GPIO4_7 */
608 IMX_PIN_REG(MX51_PAD_NANDF_D1, 0x574, 0x18c, 0, 0x000, 0), /* MX51_PAD_NANDF_D1__NANDF_D1 */
609 IMX_PIN_REG(MX51_PAD_NANDF_D1, 0x574, 0x18c, 1, 0x000, 0), /* MX51_PAD_NANDF_D1__PATA_DATA1 */
610 IMX_PIN_REG(MX51_PAD_NANDF_D1, 0x574, 0x18c, 2, 0x000, 0), /* MX51_PAD_NANDF_D1__SD4_DAT6 */
611 IMX_PIN_REG(MX51_PAD_NANDF_D1, 0x574, 0x18c, 5, 0xa14, 0), /* MX51_PAD_NANDF_D1__USBH3_DATA6 */
612 IMX_PIN_REG(MX51_PAD_NANDF_D0, 0x578, 0x190, 3, 0x000, 0), /* MX51_PAD_NANDF_D0__GPIO4_8 */
613 IMX_PIN_REG(MX51_PAD_NANDF_D0, 0x578, 0x190, 0, 0x000, 0), /* MX51_PAD_NANDF_D0__NANDF_D0 */
614 IMX_PIN_REG(MX51_PAD_NANDF_D0, 0x578, 0x190, 1, 0x000, 0), /* MX51_PAD_NANDF_D0__PATA_DATA0 */
615 IMX_PIN_REG(MX51_PAD_NANDF_D0, 0x578, 0x190, 2, 0x000, 0), /* MX51_PAD_NANDF_D0__SD4_DAT7 */
616 IMX_PIN_REG(MX51_PAD_NANDF_D0, 0x578, 0x190, 5, 0xa18, 0), /* MX51_PAD_NANDF_D0__USBH3_DATA7 */
617 IMX_PIN_REG(MX51_PAD_CSI1_D8, 0x57c, 0x194, 0, 0x000, 0), /* MX51_PAD_CSI1_D8__CSI1_D8 */
618 IMX_PIN_REG(MX51_PAD_CSI1_D8, 0x57c, 0x194, 3, 0x998, 1), /* MX51_PAD_CSI1_D8__GPIO3_12 */
619 IMX_PIN_REG(MX51_PAD_CSI1_D9, 0x580, 0x198, 0, 0x000, 0), /* MX51_PAD_CSI1_D9__CSI1_D9 */
620 IMX_PIN_REG(MX51_PAD_CSI1_D9, 0x580, 0x198, 3, 0x000, 0), /* MX51_PAD_CSI1_D9__GPIO3_13 */
621 IMX_PIN_REG(MX51_PAD_CSI1_D10, 0x584, 0x19c, 0, 0x000, 0), /* MX51_PAD_CSI1_D10__CSI1_D10 */
622 IMX_PIN_REG(MX51_PAD_CSI1_D11, 0x588, 0x1a0, 0, 0x000, 0), /* MX51_PAD_CSI1_D11__CSI1_D11 */
623 IMX_PIN_REG(MX51_PAD_CSI1_D12, 0x58c, 0x1a4, 0, 0x000, 0), /* MX51_PAD_CSI1_D12__CSI1_D12 */
624 IMX_PIN_REG(MX51_PAD_CSI1_D13, 0x590, 0x1a8, 0, 0x000, 0), /* MX51_PAD_CSI1_D13__CSI1_D13 */
625 IMX_PIN_REG(MX51_PAD_CSI1_D14, 0x594, 0x1ac, 0, 0x000, 0), /* MX51_PAD_CSI1_D14__CSI1_D14 */
626 IMX_PIN_REG(MX51_PAD_CSI1_D15, 0x598, 0x1b0, 0, 0x000, 0), /* MX51_PAD_CSI1_D15__CSI1_D15 */
627 IMX_PIN_REG(MX51_PAD_CSI1_D16, 0x59c, 0x1b4, 0, 0x000, 0), /* MX51_PAD_CSI1_D16__CSI1_D16 */
628 IMX_PIN_REG(MX51_PAD_CSI1_D17, 0x5a0, 0x1b8, 0, 0x000, 0), /* MX51_PAD_CSI1_D17__CSI1_D17 */
629 IMX_PIN_REG(MX51_PAD_CSI1_D18, 0x5a4, 0x1bc, 0, 0x000, 0), /* MX51_PAD_CSI1_D18__CSI1_D18 */
630 IMX_PIN_REG(MX51_PAD_CSI1_D19, 0x5a8, 0x1c0, 0, 0x000, 0), /* MX51_PAD_CSI1_D19__CSI1_D19 */
631 IMX_PIN_REG(MX51_PAD_CSI1_VSYNC, 0x5ac, 0x1c4, 0, 0x000, 0), /* MX51_PAD_CSI1_VSYNC__CSI1_VSYNC */
632 IMX_PIN_REG(MX51_PAD_CSI1_VSYNC, 0x5ac, 0x1c4, 3, 0x000, 0), /* MX51_PAD_CSI1_VSYNC__GPIO3_14 */
633 IMX_PIN_REG(MX51_PAD_CSI1_HSYNC, 0x5b0, 0x1c8, 0, 0x000, 0), /* MX51_PAD_CSI1_HSYNC__CSI1_HSYNC */
634 IMX_PIN_REG(MX51_PAD_CSI1_HSYNC, 0x5b0, 0x1c8, 3, 0x000, 0), /* MX51_PAD_CSI1_HSYNC__GPIO3_15 */
635 IMX_PIN_REG(MX51_PAD_CSI1_PIXCLK, 0x5b4, NO_MUX, 0, 0x000, 0), /* MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK */
636 IMX_PIN_REG(MX51_PAD_CSI1_MCLK, 0x5b8, NO_MUX, 0, 0x000, 0), /* MX51_PAD_CSI1_MCLK__CSI1_MCLK */
637 IMX_PIN_REG(MX51_PAD_CSI2_D12, 0x5bc, 0x1cc, 0, 0x000, 0), /* MX51_PAD_CSI2_D12__CSI2_D12 */
638 IMX_PIN_REG(MX51_PAD_CSI2_D12, 0x5bc, 0x1cc, 3, 0x000, 0), /* MX51_PAD_CSI2_D12__GPIO4_9 */
639 IMX_PIN_REG(MX51_PAD_CSI2_D13, 0x5c0, 0x1d0, 0, 0x000, 0), /* MX51_PAD_CSI2_D13__CSI2_D13 */
640 IMX_PIN_REG(MX51_PAD_CSI2_D13, 0x5c0, 0x1d0, 3, 0x000, 0), /* MX51_PAD_CSI2_D13__GPIO4_10 */
641 IMX_PIN_REG(MX51_PAD_CSI2_D14, 0x5c4, 0x1d4, 0, 0x000, 0), /* MX51_PAD_CSI2_D14__CSI2_D14 */
642 IMX_PIN_REG(MX51_PAD_CSI2_D15, 0x5c8, 0x1d8, 0, 0x000, 0), /* MX51_PAD_CSI2_D15__CSI2_D15 */
643 IMX_PIN_REG(MX51_PAD_CSI2_D16, 0x5cc, 0x1dc, 0, 0x000, 0), /* MX51_PAD_CSI2_D16__CSI2_D16 */
644 IMX_PIN_REG(MX51_PAD_CSI2_D17, 0x5d0, 0x1e0, 0, 0x000, 0), /* MX51_PAD_CSI2_D17__CSI2_D17 */
645 IMX_PIN_REG(MX51_PAD_CSI2_D18, 0x5d4, 0x1e4, 0, 0x000, 0), /* MX51_PAD_CSI2_D18__CSI2_D18 */
646 IMX_PIN_REG(MX51_PAD_CSI2_D18, 0x5d4, 0x1e4, 3, 0x000, 0), /* MX51_PAD_CSI2_D18__GPIO4_11 */
647 IMX_PIN_REG(MX51_PAD_CSI2_D19, 0x5d8, 0x1e8, 0, 0x000, 0), /* MX51_PAD_CSI2_D19__CSI2_D19 */
648 IMX_PIN_REG(MX51_PAD_CSI2_D19, 0x5d8, 0x1e8, 3, 0x000, 0), /* MX51_PAD_CSI2_D19__GPIO4_12 */
649 IMX_PIN_REG(MX51_PAD_CSI2_VSYNC, 0x5dc, 0x1ec, 0, 0x000, 0), /* MX51_PAD_CSI2_VSYNC__CSI2_VSYNC */
650 IMX_PIN_REG(MX51_PAD_CSI2_VSYNC, 0x5dc, 0x1ec, 3, 0x000, 0), /* MX51_PAD_CSI2_VSYNC__GPIO4_13 */
651 IMX_PIN_REG(MX51_PAD_CSI2_HSYNC, 0x5e0, 0x1f0, 0, 0x000, 0), /* MX51_PAD_CSI2_HSYNC__CSI2_HSYNC */
652 IMX_PIN_REG(MX51_PAD_CSI2_HSYNC, 0x5e0, 0x1f0, 3, 0x000, 0), /* MX51_PAD_CSI2_HSYNC__GPIO4_14 */
653 IMX_PIN_REG(MX51_PAD_CSI2_PIXCLK, 0x5e4, 0x1f4, 0, 0x000, 0), /* MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK */
654 IMX_PIN_REG(MX51_PAD_CSI2_PIXCLK, 0x5e4, 0x1f4, 3, 0x000, 0), /* MX51_PAD_CSI2_PIXCLK__GPIO4_15 */
655 IMX_PIN_REG(MX51_PAD_I2C1_CLK, 0x5e8, 0x1f8, 3, 0x000, 0), /* MX51_PAD_I2C1_CLK__GPIO4_16 */
656 IMX_PIN_REG(MX51_PAD_I2C1_CLK, 0x5e8, 0x1f8, 0, 0x000, 0), /* MX51_PAD_I2C1_CLK__I2C1_CLK */
657 IMX_PIN_REG(MX51_PAD_I2C1_DAT, 0x5ec, 0x1fc, 3, 0x000, 0), /* MX51_PAD_I2C1_DAT__GPIO4_17 */
658 IMX_PIN_REG(MX51_PAD_I2C1_DAT, 0x5ec, 0x1fc, 0, 0x000, 0), /* MX51_PAD_I2C1_DAT__I2C1_DAT */
659 IMX_PIN_REG(MX51_PAD_AUD3_BB_TXD, 0x5f0, 0x200, 0, 0x000, 0), /* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */
660 IMX_PIN_REG(MX51_PAD_AUD3_BB_TXD, 0x5f0, 0x200, 3, 0x000, 0), /* MX51_PAD_AUD3_BB_TXD__GPIO4_18 */
661 IMX_PIN_REG(MX51_PAD_AUD3_BB_RXD, 0x5f4, 0x204, 0, 0x000, 0), /* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */
662 IMX_PIN_REG(MX51_PAD_AUD3_BB_RXD, 0x5f4, 0x204, 3, 0x000, 0), /* MX51_PAD_AUD3_BB_RXD__GPIO4_19 */
663 IMX_PIN_REG(MX51_PAD_AUD3_BB_RXD, 0x5f4, 0x204, 1, 0x9f4, 2), /* MX51_PAD_AUD3_BB_RXD__UART3_RXD */
664 IMX_PIN_REG(MX51_PAD_AUD3_BB_CK, 0x5f8, 0x208, 0, 0x000, 0), /* MX51_PAD_AUD3_BB_CK__AUD3_TXC */
665 IMX_PIN_REG(MX51_PAD_AUD3_BB_CK, 0x5f8, 0x208, 3, 0x000, 0), /* MX51_PAD_AUD3_BB_CK__GPIO4_20 */
666 IMX_PIN_REG(MX51_PAD_AUD3_BB_FS, 0x5fc, 0x20c, 0, 0x000, 0), /* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */
667 IMX_PIN_REG(MX51_PAD_AUD3_BB_FS, 0x5fc, 0x20c, 3, 0x000, 0), /* MX51_PAD_AUD3_BB_FS__GPIO4_21 */
668 IMX_PIN_REG(MX51_PAD_AUD3_BB_FS, 0x5fc, 0x20c, 1, 0x000, 0), /* MX51_PAD_AUD3_BB_FS__UART3_TXD */
669 IMX_PIN_REG(MX51_PAD_CSPI1_MOSI, 0x600, 0x210, 0, 0x000, 0), /* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */
670 IMX_PIN_REG(MX51_PAD_CSPI1_MOSI, 0x600, 0x210, 3, 0x000, 0), /* MX51_PAD_CSPI1_MOSI__GPIO4_22 */
671 IMX_PIN_REG(MX51_PAD_CSPI1_MOSI, 0x600, 0x210, 1, 0x9b4, 1), /* MX51_PAD_CSPI1_MOSI__I2C1_SDA */
672 IMX_PIN_REG(MX51_PAD_CSPI1_MISO, 0x604, 0x214, 1, 0x8c4, 1), /* MX51_PAD_CSPI1_MISO__AUD4_RXD */
673 IMX_PIN_REG(MX51_PAD_CSPI1_MISO, 0x604, 0x214, 0, 0x000, 0), /* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */
674 IMX_PIN_REG(MX51_PAD_CSPI1_MISO, 0x604, 0x214, 3, 0x000, 0), /* MX51_PAD_CSPI1_MISO__GPIO4_23 */
675 IMX_PIN_REG(MX51_PAD_CSPI1_SS0, 0x608, 0x218, 1, 0x8cc, 1), /* MX51_PAD_CSPI1_SS0__AUD4_TXC */
676 IMX_PIN_REG(MX51_PAD_CSPI1_SS0, 0x608, 0x218, 0, 0x000, 0), /* MX51_PAD_CSPI1_SS0__ECSPI1_SS0 */
677 IMX_PIN_REG(MX51_PAD_CSPI1_SS0, 0x608, 0x218, 3, 0x000, 0), /* MX51_PAD_CSPI1_SS0__GPIO4_24 */
678 IMX_PIN_REG(MX51_PAD_CSPI1_SS1, 0x60c, 0x21c, 1, 0x8c8, 1), /* MX51_PAD_CSPI1_SS1__AUD4_TXD */
679 IMX_PIN_REG(MX51_PAD_CSPI1_SS1, 0x60c, 0x21c, 0, 0x000, 0), /* MX51_PAD_CSPI1_SS1__ECSPI1_SS1 */
680 IMX_PIN_REG(MX51_PAD_CSPI1_SS1, 0x60c, 0x21c, 3, 0x000, 0), /* MX51_PAD_CSPI1_SS1__GPIO4_25 */
681 IMX_PIN_REG(MX51_PAD_CSPI1_RDY, 0x610, 0x220, 1, 0x8d0, 1), /* MX51_PAD_CSPI1_RDY__AUD4_TXFS */
682 IMX_PIN_REG(MX51_PAD_CSPI1_RDY, 0x610, 0x220, 0, 0x000, 0), /* MX51_PAD_CSPI1_RDY__ECSPI1_RDY */
683 IMX_PIN_REG(MX51_PAD_CSPI1_RDY, 0x610, 0x220, 3, 0x000, 0), /* MX51_PAD_CSPI1_RDY__GPIO4_26 */
684 IMX_PIN_REG(MX51_PAD_CSPI1_SCLK, 0x614, 0x224, 0, 0x000, 0), /* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */
685 IMX_PIN_REG(MX51_PAD_CSPI1_SCLK, 0x614, 0x224, 3, 0x000, 0), /* MX51_PAD_CSPI1_SCLK__GPIO4_27 */
686 IMX_PIN_REG(MX51_PAD_CSPI1_SCLK, 0x614, 0x224, 1, 0x9b0, 1), /* MX51_PAD_CSPI1_SCLK__I2C1_SCL */
687 IMX_PIN_REG(MX51_PAD_UART1_RXD, 0x618, 0x228, 3, 0x000, 0), /* MX51_PAD_UART1_RXD__GPIO4_28 */
688 IMX_PIN_REG(MX51_PAD_UART1_RXD, 0x618, 0x228, 0, 0x9e4, 0), /* MX51_PAD_UART1_RXD__UART1_RXD */
689 IMX_PIN_REG(MX51_PAD_UART1_TXD, 0x61c, 0x22c, 3, 0x000, 0), /* MX51_PAD_UART1_TXD__GPIO4_29 */
690 IMX_PIN_REG(MX51_PAD_UART1_TXD, 0x61c, 0x22c, 1, 0x000, 0), /* MX51_PAD_UART1_TXD__PWM2_PWMO */
691 IMX_PIN_REG(MX51_PAD_UART1_TXD, 0x61c, 0x22c, 0, 0x000, 0), /* MX51_PAD_UART1_TXD__UART1_TXD */
692 IMX_PIN_REG(MX51_PAD_UART1_RTS, 0x620, 0x230, 3, 0x000, 0), /* MX51_PAD_UART1_RTS__GPIO4_30 */
693 IMX_PIN_REG(MX51_PAD_UART1_RTS, 0x620, 0x230, 0, 0x9e0, 0), /* MX51_PAD_UART1_RTS__UART1_RTS */
694 IMX_PIN_REG(MX51_PAD_UART1_CTS, 0x624, 0x234, 3, 0x000, 0), /* MX51_PAD_UART1_CTS__GPIO4_31 */
695 IMX_PIN_REG(MX51_PAD_UART1_CTS, 0x624, 0x234, 0, 0x000, 0), /* MX51_PAD_UART1_CTS__UART1_CTS */
696 IMX_PIN_REG(MX51_PAD_UART2_RXD, 0x628, 0x238, 1, 0x000, 0), /* MX51_PAD_UART2_RXD__FIRI_TXD */
697 IMX_PIN_REG(MX51_PAD_UART2_RXD, 0x628, 0x238, 3, 0x000, 0), /* MX51_PAD_UART2_RXD__GPIO1_20 */
698 IMX_PIN_REG(MX51_PAD_UART2_RXD, 0x628, 0x238, 0, 0x9ec, 2), /* MX51_PAD_UART2_RXD__UART2_RXD */
699 IMX_PIN_REG(MX51_PAD_UART2_TXD, 0x62c, 0x23c, 1, 0x000, 0), /* MX51_PAD_UART2_TXD__FIRI_RXD */
700 IMX_PIN_REG(MX51_PAD_UART2_TXD, 0x62c, 0x23c, 3, 0x000, 0), /* MX51_PAD_UART2_TXD__GPIO1_21 */
701 IMX_PIN_REG(MX51_PAD_UART2_TXD, 0x62c, 0x23c, 0, 0x000, 0), /* MX51_PAD_UART2_TXD__UART2_TXD */
702 IMX_PIN_REG(MX51_PAD_UART3_RXD, 0x630, 0x240, 2, 0x000, 0), /* MX51_PAD_UART3_RXD__CSI1_D0 */
703 IMX_PIN_REG(MX51_PAD_UART3_RXD, 0x630, 0x240, 3, 0x000, 0), /* MX51_PAD_UART3_RXD__GPIO1_22 */
704 IMX_PIN_REG(MX51_PAD_UART3_RXD, 0x630, 0x240, 0, 0x000, 0), /* MX51_PAD_UART3_RXD__UART1_DTR */
705 IMX_PIN_REG(MX51_PAD_UART3_RXD, 0x630, 0x240, 1, 0x9f4, 4), /* MX51_PAD_UART3_RXD__UART3_RXD */
706 IMX_PIN_REG(MX51_PAD_UART3_TXD, 0x634, 0x244, 2, 0x000, 0), /* MX51_PAD_UART3_TXD__CSI1_D1 */
707 IMX_PIN_REG(MX51_PAD_UART3_TXD, 0x634, 0x244, 3, 0x000, 0), /* MX51_PAD_UART3_TXD__GPIO1_23 */
708 IMX_PIN_REG(MX51_PAD_UART3_TXD, 0x634, 0x244, 0, 0x000, 0), /* MX51_PAD_UART3_TXD__UART1_DSR */
709 IMX_PIN_REG(MX51_PAD_UART3_TXD, 0x634, 0x244, 1, 0x000, 0), /* MX51_PAD_UART3_TXD__UART3_TXD */
710 IMX_PIN_REG(MX51_PAD_OWIRE_LINE, 0x638, 0x248, 3, 0x000, 0), /* MX51_PAD_OWIRE_LINE__GPIO1_24 */
711 IMX_PIN_REG(MX51_PAD_OWIRE_LINE, 0x638, 0x248, 0, 0x000, 0), /* MX51_PAD_OWIRE_LINE__OWIRE_LINE */
712 IMX_PIN_REG(MX51_PAD_OWIRE_LINE, 0x638, 0x248, 6, 0x000, 0), /* MX51_PAD_OWIRE_LINE__SPDIF_OUT */
713 IMX_PIN_REG(MX51_PAD_KEY_ROW0, 0x63c, 0x24c, 0, 0x000, 0), /* MX51_PAD_KEY_ROW0__KEY_ROW0 */
714 IMX_PIN_REG(MX51_PAD_KEY_ROW1, 0x640, 0x250, 0, 0x000, 0), /* MX51_PAD_KEY_ROW1__KEY_ROW1 */
715 IMX_PIN_REG(MX51_PAD_KEY_ROW2, 0x644, 0x254, 0, 0x000, 0), /* MX51_PAD_KEY_ROW2__KEY_ROW2 */
716 IMX_PIN_REG(MX51_PAD_KEY_ROW3, 0x648, 0x258, 0, 0x000, 0), /* MX51_PAD_KEY_ROW3__KEY_ROW3 */
717 IMX_PIN_REG(MX51_PAD_KEY_COL0, 0x64c, 0x25c, 0, 0x000, 0), /* MX51_PAD_KEY_COL0__KEY_COL0 */
718 IMX_PIN_REG(MX51_PAD_KEY_COL0, 0x64c, 0x25c, 7, 0x90c, 0), /* MX51_PAD_KEY_COL0__PLL1_BYP */
719 IMX_PIN_REG(MX51_PAD_KEY_COL1, 0x650, 0x260, 0, 0x000, 0), /* MX51_PAD_KEY_COL1__KEY_COL1 */
720 IMX_PIN_REG(MX51_PAD_KEY_COL1, 0x650, 0x260, 7, 0x910, 0), /* MX51_PAD_KEY_COL1__PLL2_BYP */
721 IMX_PIN_REG(MX51_PAD_KEY_COL2, 0x654, 0x264, 0, 0x000, 0), /* MX51_PAD_KEY_COL2__KEY_COL2 */
722 IMX_PIN_REG(MX51_PAD_KEY_COL2, 0x654, 0x264, 7, 0x000, 0), /* MX51_PAD_KEY_COL2__PLL3_BYP */
723 IMX_PIN_REG(MX51_PAD_KEY_COL3, 0x658, 0x268, 0, 0x000, 0), /* MX51_PAD_KEY_COL3__KEY_COL3 */
724 IMX_PIN_REG(MX51_PAD_KEY_COL4, 0x65c, 0x26c, 3, 0x9b8, 1), /* MX51_PAD_KEY_COL4__I2C2_SCL */
725 IMX_PIN_REG(MX51_PAD_KEY_COL4, 0x65c, 0x26c, 0, 0x000, 0), /* MX51_PAD_KEY_COL4__KEY_COL4 */
726 IMX_PIN_REG(MX51_PAD_KEY_COL4, 0x65c, 0x26c, 6, 0x000, 0), /* MX51_PAD_KEY_COL4__SPDIF_OUT1 */
727 IMX_PIN_REG(MX51_PAD_KEY_COL4, 0x65c, 0x26c, 1, 0x000, 0), /* MX51_PAD_KEY_COL4__UART1_RI */
728 IMX_PIN_REG(MX51_PAD_KEY_COL4, 0x65c, 0x26c, 2, 0x9f0, 4), /* MX51_PAD_KEY_COL4__UART3_RTS */
729 IMX_PIN_REG(MX51_PAD_KEY_COL5, 0x660, 0x270, 3, 0x9bc, 1), /* MX51_PAD_KEY_COL5__I2C2_SDA */
730 IMX_PIN_REG(MX51_PAD_KEY_COL5, 0x660, 0x270, 0, 0x000, 0), /* MX51_PAD_KEY_COL5__KEY_COL5 */
731 IMX_PIN_REG(MX51_PAD_KEY_COL5, 0x660, 0x270, 1, 0x000, 0), /* MX51_PAD_KEY_COL5__UART1_DCD */
732 IMX_PIN_REG(MX51_PAD_KEY_COL5, 0x660, 0x270, 2, 0x000, 0), /* MX51_PAD_KEY_COL5__UART3_CTS */
733 IMX_PIN_REG(MX51_PAD_USBH1_CLK, 0x678, 0x278, 1, 0x914, 1), /* MX51_PAD_USBH1_CLK__CSPI_SCLK */
734 IMX_PIN_REG(MX51_PAD_USBH1_CLK, 0x678, 0x278, 2, 0x000, 0), /* MX51_PAD_USBH1_CLK__GPIO1_25 */
735 IMX_PIN_REG(MX51_PAD_USBH1_CLK, 0x678, 0x278, 5, 0x9b8, 2), /* MX51_PAD_USBH1_CLK__I2C2_SCL */
736 IMX_PIN_REG(MX51_PAD_USBH1_CLK, 0x678, 0x278, 0, 0x000, 0), /* MX51_PAD_USBH1_CLK__USBH1_CLK */
737 IMX_PIN_REG(MX51_PAD_USBH1_DIR, 0x67c, 0x27c, 1, 0x91c, 1), /* MX51_PAD_USBH1_DIR__CSPI_MOSI */
738 IMX_PIN_REG(MX51_PAD_USBH1_DIR, 0x67c, 0x27c, 2, 0x000, 0), /* MX51_PAD_USBH1_DIR__GPIO1_26 */
739 IMX_PIN_REG(MX51_PAD_USBH1_DIR, 0x67c, 0x27c, 5, 0x9bc, 2), /* MX51_PAD_USBH1_DIR__I2C2_SDA */
740 IMX_PIN_REG(MX51_PAD_USBH1_DIR, 0x67c, 0x27c, 0, 0x000, 0), /* MX51_PAD_USBH1_DIR__USBH1_DIR */
741 IMX_PIN_REG(MX51_PAD_USBH1_STP, 0x680, 0x280, 1, 0x000, 0), /* MX51_PAD_USBH1_STP__CSPI_RDY */
742 IMX_PIN_REG(MX51_PAD_USBH1_STP, 0x680, 0x280, 2, 0x000, 0), /* MX51_PAD_USBH1_STP__GPIO1_27 */
743 IMX_PIN_REG(MX51_PAD_USBH1_STP, 0x680, 0x280, 5, 0x9f4, 6), /* MX51_PAD_USBH1_STP__UART3_RXD */
744 IMX_PIN_REG(MX51_PAD_USBH1_STP, 0x680, 0x280, 0, 0x000, 0), /* MX51_PAD_USBH1_STP__USBH1_STP */
745 IMX_PIN_REG(MX51_PAD_USBH1_NXT, 0x684, 0x284, 1, 0x918, 0), /* MX51_PAD_USBH1_NXT__CSPI_MISO */
746 IMX_PIN_REG(MX51_PAD_USBH1_NXT, 0x684, 0x284, 2, 0x000, 0), /* MX51_PAD_USBH1_NXT__GPIO1_28 */
747 IMX_PIN_REG(MX51_PAD_USBH1_NXT, 0x684, 0x284, 5, 0x000, 0), /* MX51_PAD_USBH1_NXT__UART3_TXD */
748 IMX_PIN_REG(MX51_PAD_USBH1_NXT, 0x684, 0x284, 0, 0x000, 0), /* MX51_PAD_USBH1_NXT__USBH1_NXT */
749 IMX_PIN_REG(MX51_PAD_USBH1_DATA0, 0x688, 0x288, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA0__GPIO1_11 */
750 IMX_PIN_REG(MX51_PAD_USBH1_DATA0, 0x688, 0x288, 1, 0x000, 0), /* MX51_PAD_USBH1_DATA0__UART2_CTS */
751 IMX_PIN_REG(MX51_PAD_USBH1_DATA0, 0x688, 0x288, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA0__USBH1_DATA0 */
752 IMX_PIN_REG(MX51_PAD_USBH1_DATA1, 0x68c, 0x28c, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA1__GPIO1_12 */
753 IMX_PIN_REG(MX51_PAD_USBH1_DATA1, 0x68c, 0x28c, 1, 0x9ec, 4), /* MX51_PAD_USBH1_DATA1__UART2_RXD */
754 IMX_PIN_REG(MX51_PAD_USBH1_DATA1, 0x68c, 0x28c, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA1__USBH1_DATA1 */
755 IMX_PIN_REG(MX51_PAD_USBH1_DATA2, 0x690, 0x290, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA2__GPIO1_13 */
756 IMX_PIN_REG(MX51_PAD_USBH1_DATA2, 0x690, 0x290, 1, 0x000, 0), /* MX51_PAD_USBH1_DATA2__UART2_TXD */
757 IMX_PIN_REG(MX51_PAD_USBH1_DATA2, 0x690, 0x290, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA2__USBH1_DATA2 */
758 IMX_PIN_REG(MX51_PAD_USBH1_DATA3, 0x694, 0x294, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA3__GPIO1_14 */
759 IMX_PIN_REG(MX51_PAD_USBH1_DATA3, 0x694, 0x294, 1, 0x9e8, 5), /* MX51_PAD_USBH1_DATA3__UART2_RTS */
760 IMX_PIN_REG(MX51_PAD_USBH1_DATA3, 0x694, 0x294, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA3__USBH1_DATA3 */
761 IMX_PIN_REG(MX51_PAD_USBH1_DATA4, 0x698, 0x298, 1, 0x000, 0), /* MX51_PAD_USBH1_DATA4__CSPI_SS0 */
762 IMX_PIN_REG(MX51_PAD_USBH1_DATA4, 0x698, 0x298, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA4__GPIO1_15 */
763 IMX_PIN_REG(MX51_PAD_USBH1_DATA4, 0x698, 0x298, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA4__USBH1_DATA4 */
764 IMX_PIN_REG(MX51_PAD_USBH1_DATA5, 0x69c, 0x29c, 1, 0x920, 0), /* MX51_PAD_USBH1_DATA5__CSPI_SS1 */
765 IMX_PIN_REG(MX51_PAD_USBH1_DATA5, 0x69c, 0x29c, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA5__GPIO1_16 */
766 IMX_PIN_REG(MX51_PAD_USBH1_DATA5, 0x69c, 0x29c, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA5__USBH1_DATA5 */
767 IMX_PIN_REG(MX51_PAD_USBH1_DATA6, 0x6a0, 0x2a0, 1, 0x928, 1), /* MX51_PAD_USBH1_DATA6__CSPI_SS3 */
768 IMX_PIN_REG(MX51_PAD_USBH1_DATA6, 0x6a0, 0x2a0, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA6__GPIO1_17 */
769 IMX_PIN_REG(MX51_PAD_USBH1_DATA6, 0x6a0, 0x2a0, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA6__USBH1_DATA6 */
770 IMX_PIN_REG(MX51_PAD_USBH1_DATA7, 0x6a4, 0x2a4, 1, 0x000, 0), /* MX51_PAD_USBH1_DATA7__ECSPI1_SS3 */
771 IMX_PIN_REG(MX51_PAD_USBH1_DATA7, 0x6a4, 0x2a4, 5, 0x934, 1), /* MX51_PAD_USBH1_DATA7__ECSPI2_SS3 */
772 IMX_PIN_REG(MX51_PAD_USBH1_DATA7, 0x6a4, 0x2a4, 2, 0x000, 0), /* MX51_PAD_USBH1_DATA7__GPIO1_18 */
773 IMX_PIN_REG(MX51_PAD_USBH1_DATA7, 0x6a4, 0x2a4, 0, 0x000, 0), /* MX51_PAD_USBH1_DATA7__USBH1_DATA7 */
774 IMX_PIN_REG(MX51_PAD_DI1_PIN11, 0x6a8, 0x2a8, 0, 0x000, 0), /* MX51_PAD_DI1_PIN11__DI1_PIN11 */
775 IMX_PIN_REG(MX51_PAD_DI1_PIN11, 0x6a8, 0x2a8, 7, 0x000, 0), /* MX51_PAD_DI1_PIN11__ECSPI1_SS2 */
776 IMX_PIN_REG(MX51_PAD_DI1_PIN11, 0x6a8, 0x2a8, 4, 0x000, 0), /* MX51_PAD_DI1_PIN11__GPIO3_0 */
777 IMX_PIN_REG(MX51_PAD_DI1_PIN12, 0x6ac, 0x2ac, 0, 0x000, 0), /* MX51_PAD_DI1_PIN12__DI1_PIN12 */
778 IMX_PIN_REG(MX51_PAD_DI1_PIN12, 0x6ac, 0x2ac, 4, 0x978, 1), /* MX51_PAD_DI1_PIN12__GPIO3_1 */
779 IMX_PIN_REG(MX51_PAD_DI1_PIN13, 0x6b0, 0x2b0, 0, 0x000, 0), /* MX51_PAD_DI1_PIN13__DI1_PIN13 */
780 IMX_PIN_REG(MX51_PAD_DI1_PIN13, 0x6b0, 0x2b0, 4, 0x97c, 1), /* MX51_PAD_DI1_PIN13__GPIO3_2 */
781 IMX_PIN_REG(MX51_PAD_DI1_D0_CS, 0x6b4, 0x2b4, 0, 0x000, 0), /* MX51_PAD_DI1_D0_CS__DI1_D0_CS */
782 IMX_PIN_REG(MX51_PAD_DI1_D0_CS, 0x6b4, 0x2b4, 4, 0x980, 1), /* MX51_PAD_DI1_D0_CS__GPIO3_3 */
783 IMX_PIN_REG(MX51_PAD_DI1_D1_CS, 0x6b8, 0x2b8, 0, 0x000, 0), /* MX51_PAD_DI1_D1_CS__DI1_D1_CS */
784 IMX_PIN_REG(MX51_PAD_DI1_D1_CS, 0x6b8, 0x2b8, 2, 0x000, 0), /* MX51_PAD_DI1_D1_CS__DISP1_PIN14 */
785 IMX_PIN_REG(MX51_PAD_DI1_D1_CS, 0x6b8, 0x2b8, 3, 0x000, 0), /* MX51_PAD_DI1_D1_CS__DISP1_PIN5 */
786 IMX_PIN_REG(MX51_PAD_DI1_D1_CS, 0x6b8, 0x2b8, 4, 0x984, 1), /* MX51_PAD_DI1_D1_CS__GPIO3_4 */
787 IMX_PIN_REG(MX51_PAD_DISPB2_SER_DIN, 0x6bc, 0x2bc, 2, 0x9a4, 1), /* MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 */
788 IMX_PIN_REG(MX51_PAD_DISPB2_SER_DIN, 0x6bc, 0x2bc, 0, 0x9c4, 0), /* MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN */
789 IMX_PIN_REG(MX51_PAD_DISPB2_SER_DIN, 0x6bc, 0x2bc, 4, 0x988, 1), /* MX51_PAD_DISPB2_SER_DIN__GPIO3_5 */
790 IMX_PIN_REG(MX51_PAD_DISPB2_SER_DIO, 0x6c0, 0x2c0, 3, 0x000, 0), /* MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 */
791 IMX_PIN_REG(MX51_PAD_DISPB2_SER_DIO, 0x6c0, 0x2c0, 0, 0x9c4, 1), /* MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO */
792 IMX_PIN_REG(MX51_PAD_DISPB2_SER_DIO, 0x6c0, 0x2c0, 4, 0x98c, 1), /* MX51_PAD_DISPB2_SER_DIO__GPIO3_6 */
793 IMX_PIN_REG(MX51_PAD_DISPB2_SER_CLK, 0x6c4, 0x2c4, 2, 0x000, 0), /* MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 */
794 IMX_PIN_REG(MX51_PAD_DISPB2_SER_CLK, 0x6c4, 0x2c4, 3, 0x000, 0), /* MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 */
795 IMX_PIN_REG(MX51_PAD_DISPB2_SER_CLK, 0x6c4, 0x2c4, 0, 0x000, 0), /* MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK */
796 IMX_PIN_REG(MX51_PAD_DISPB2_SER_CLK, 0x6c4, 0x2c4, 4, 0x990, 1), /* MX51_PAD_DISPB2_SER_CLK__GPIO3_7 */
797 IMX_PIN_REG(MX51_PAD_DISPB2_SER_RS, 0x6c8, 0x2c8, 2, 0x000, 0), /* MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK */
798 IMX_PIN_REG(MX51_PAD_DISPB2_SER_RS, 0x6c8, 0x2c8, 2, 0x000, 0), /* MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 */
799 IMX_PIN_REG(MX51_PAD_DISPB2_SER_RS, 0x6c8, 0x2c8, 3, 0x000, 0), /* MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 */
800 IMX_PIN_REG(MX51_PAD_DISPB2_SER_RS, 0x6c8, 0x2c8, 0, 0x000, 0), /* MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS */
801 IMX_PIN_REG(MX51_PAD_DISPB2_SER_RS, 0x6c8, 0x2c8, 0, 0x000, 0), /* MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS */
802 IMX_PIN_REG(MX51_PAD_DISPB2_SER_RS, 0x6c8, 0x2c8, 4, 0x994, 1), /* MX51_PAD_DISPB2_SER_RS__GPIO3_8 */
803 IMX_PIN_REG(MX51_PAD_DISP1_DAT0, 0x6cc, 0x2cc, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT0__DISP1_DAT0 */
804 IMX_PIN_REG(MX51_PAD_DISP1_DAT1, 0x6d0, 0x2d0, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT1__DISP1_DAT1 */
805 IMX_PIN_REG(MX51_PAD_DISP1_DAT2, 0x6d4, 0x2d4, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT2__DISP1_DAT2 */
806 IMX_PIN_REG(MX51_PAD_DISP1_DAT3, 0x6d8, 0x2d8, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT3__DISP1_DAT3 */
807 IMX_PIN_REG(MX51_PAD_DISP1_DAT4, 0x6dc, 0x2dc, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT4__DISP1_DAT4 */
808 IMX_PIN_REG(MX51_PAD_DISP1_DAT5, 0x6e0, 0x2e0, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT5__DISP1_DAT5 */
809 IMX_PIN_REG(MX51_PAD_DISP1_DAT6, 0x6e4, 0x2e4, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT6__BOOT_USB_SRC */
810 IMX_PIN_REG(MX51_PAD_DISP1_DAT6, 0x6e4, 0x2e4, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT6__DISP1_DAT6 */
811 IMX_PIN_REG(MX51_PAD_DISP1_DAT7, 0x6e8, 0x2e8, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG */
812 IMX_PIN_REG(MX51_PAD_DISP1_DAT7, 0x6e8, 0x2e8, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT7__DISP1_DAT7 */
813 IMX_PIN_REG(MX51_PAD_DISP1_DAT8, 0x6ec, 0x2ec, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT8__BOOT_SRC0 */
814 IMX_PIN_REG(MX51_PAD_DISP1_DAT8, 0x6ec, 0x2ec, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT8__DISP1_DAT8 */
815 IMX_PIN_REG(MX51_PAD_DISP1_DAT9, 0x6f0, 0x2f0, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT9__BOOT_SRC1 */
816 IMX_PIN_REG(MX51_PAD_DISP1_DAT9, 0x6f0, 0x2f0, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT9__DISP1_DAT9 */
817 IMX_PIN_REG(MX51_PAD_DISP1_DAT10, 0x6f4, 0x2f4, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE */
818 IMX_PIN_REG(MX51_PAD_DISP1_DAT10, 0x6f4, 0x2f4, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT10__DISP1_DAT10 */
819 IMX_PIN_REG(MX51_PAD_DISP1_DAT11, 0x6f8, 0x2f8, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 */
820 IMX_PIN_REG(MX51_PAD_DISP1_DAT11, 0x6f8, 0x2f8, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT11__DISP1_DAT11 */
821 IMX_PIN_REG(MX51_PAD_DISP1_DAT12, 0x6fc, 0x2fc, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL */
822 IMX_PIN_REG(MX51_PAD_DISP1_DAT12, 0x6fc, 0x2fc, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT12__DISP1_DAT12 */
823 IMX_PIN_REG(MX51_PAD_DISP1_DAT13, 0x700, 0x300, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 */
824 IMX_PIN_REG(MX51_PAD_DISP1_DAT13, 0x700, 0x300, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT13__DISP1_DAT13 */
825 IMX_PIN_REG(MX51_PAD_DISP1_DAT14, 0x704, 0x304, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 */
826 IMX_PIN_REG(MX51_PAD_DISP1_DAT14, 0x704, 0x304, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT14__DISP1_DAT14 */
827 IMX_PIN_REG(MX51_PAD_DISP1_DAT15, 0x708, 0x308, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH */
828 IMX_PIN_REG(MX51_PAD_DISP1_DAT15, 0x708, 0x308, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT15__DISP1_DAT15 */
829 IMX_PIN_REG(MX51_PAD_DISP1_DAT16, 0x70c, 0x30c, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 */
830 IMX_PIN_REG(MX51_PAD_DISP1_DAT16, 0x70c, 0x30c, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT16__DISP1_DAT16 */
831 IMX_PIN_REG(MX51_PAD_DISP1_DAT17, 0x710, 0x310, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 */
832 IMX_PIN_REG(MX51_PAD_DISP1_DAT17, 0x710, 0x310, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT17__DISP1_DAT17 */
833 IMX_PIN_REG(MX51_PAD_DISP1_DAT18, 0x714, 0x314, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 */
834 IMX_PIN_REG(MX51_PAD_DISP1_DAT18, 0x714, 0x314, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT18__DISP1_DAT18 */
835 IMX_PIN_REG(MX51_PAD_DISP1_DAT18, 0x714, 0x314, 5, 0x000, 0), /* MX51_PAD_DISP1_DAT18__DISP2_PIN11 */
836 IMX_PIN_REG(MX51_PAD_DISP1_DAT18, 0x714, 0x314, 4, 0x000, 0), /* MX51_PAD_DISP1_DAT18__DISP2_PIN5 */
837 IMX_PIN_REG(MX51_PAD_DISP1_DAT19, 0x718, 0x318, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 */
838 IMX_PIN_REG(MX51_PAD_DISP1_DAT19, 0x718, 0x318, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT19__DISP1_DAT19 */
839 IMX_PIN_REG(MX51_PAD_DISP1_DAT19, 0x718, 0x318, 5, 0x000, 0), /* MX51_PAD_DISP1_DAT19__DISP2_PIN12 */
840 IMX_PIN_REG(MX51_PAD_DISP1_DAT19, 0x718, 0x318, 4, 0x000, 0), /* MX51_PAD_DISP1_DAT19__DISP2_PIN6 */
841 IMX_PIN_REG(MX51_PAD_DISP1_DAT20, 0x71c, 0x31c, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 */
842 IMX_PIN_REG(MX51_PAD_DISP1_DAT20, 0x71c, 0x31c, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT20__DISP1_DAT20 */
843 IMX_PIN_REG(MX51_PAD_DISP1_DAT20, 0x71c, 0x31c, 5, 0x000, 0), /* MX51_PAD_DISP1_DAT20__DISP2_PIN13 */
844 IMX_PIN_REG(MX51_PAD_DISP1_DAT20, 0x71c, 0x31c, 4, 0x000, 0), /* MX51_PAD_DISP1_DAT20__DISP2_PIN7 */
845 IMX_PIN_REG(MX51_PAD_DISP1_DAT21, 0x720, 0x320, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 */
846 IMX_PIN_REG(MX51_PAD_DISP1_DAT21, 0x720, 0x320, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT21__DISP1_DAT21 */
847 IMX_PIN_REG(MX51_PAD_DISP1_DAT21, 0x720, 0x320, 5, 0x000, 0), /* MX51_PAD_DISP1_DAT21__DISP2_PIN14 */
848 IMX_PIN_REG(MX51_PAD_DISP1_DAT21, 0x720, 0x320, 4, 0x000, 0), /* MX51_PAD_DISP1_DAT21__DISP2_PIN8 */
849 IMX_PIN_REG(MX51_PAD_DISP1_DAT22, 0x724, 0x324, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 */
850 IMX_PIN_REG(MX51_PAD_DISP1_DAT22, 0x724, 0x324, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT22__DISP1_DAT22 */
851 IMX_PIN_REG(MX51_PAD_DISP1_DAT22, 0x724, 0x324, 6, 0x000, 0), /* MX51_PAD_DISP1_DAT22__DISP2_D0_CS */
852 IMX_PIN_REG(MX51_PAD_DISP1_DAT22, 0x724, 0x324, 5, 0x000, 0), /* MX51_PAD_DISP1_DAT22__DISP2_DAT16 */
853 IMX_PIN_REG(MX51_PAD_DISP1_DAT23, 0x728, 0x328, 7, 0x000, 0), /* MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 */
854 IMX_PIN_REG(MX51_PAD_DISP1_DAT23, 0x728, 0x328, 0, 0x000, 0), /* MX51_PAD_DISP1_DAT23__DISP1_DAT23 */
855 IMX_PIN_REG(MX51_PAD_DISP1_DAT23, 0x728, 0x328, 6, 0x000, 0), /* MX51_PAD_DISP1_DAT23__DISP2_D1_CS */
856 IMX_PIN_REG(MX51_PAD_DISP1_DAT23, 0x728, 0x328, 5, 0x000, 0), /* MX51_PAD_DISP1_DAT23__DISP2_DAT17 */
857 IMX_PIN_REG(MX51_PAD_DISP1_DAT23, 0x728, 0x328, 4, 0x000, 0), /* MX51_PAD_DISP1_DAT23__DISP2_SER_CS */
858 IMX_PIN_REG(MX51_PAD_DI1_PIN3, 0x72c, 0x32c, 0, 0x000, 0), /* MX51_PAD_DI1_PIN3__DI1_PIN3 */
859 IMX_PIN_REG(MX51_PAD_DI1_PIN2, 0x734, 0x330, 0, 0x000, 0), /* MX51_PAD_DI1_PIN2__DI1_PIN2 */
860 IMX_PIN_REG(MX51_PAD_DI_GP2, 0x740, 0x338, 0, 0x000, 0), /* MX51_PAD_DI_GP2__DISP1_SER_CLK */
861 IMX_PIN_REG(MX51_PAD_DI_GP2, 0x740, 0x338, 2, 0x9a8, 1), /* MX51_PAD_DI_GP2__DISP2_WAIT */
862 IMX_PIN_REG(MX51_PAD_DI_GP3, 0x744, 0x33c, 3, 0x9a0, 1), /* MX51_PAD_DI_GP3__CSI1_DATA_EN */
863 IMX_PIN_REG(MX51_PAD_DI_GP3, 0x744, 0x33c, 0, 0x9c0, 0), /* MX51_PAD_DI_GP3__DISP1_SER_DIO */
864 IMX_PIN_REG(MX51_PAD_DI_GP3, 0x744, 0x33c, 2, 0x000, 0), /* MX51_PAD_DI_GP3__FEC_TX_ER */
865 IMX_PIN_REG(MX51_PAD_DI2_PIN4, 0x748, 0x340, 3, 0x99c, 1), /* MX51_PAD_DI2_PIN4__CSI2_DATA_EN */
866 IMX_PIN_REG(MX51_PAD_DI2_PIN4, 0x748, 0x340, 0, 0x000, 0), /* MX51_PAD_DI2_PIN4__DI2_PIN4 */
867 IMX_PIN_REG(MX51_PAD_DI2_PIN4, 0x748, 0x340, 2, 0x950, 1), /* MX51_PAD_DI2_PIN4__FEC_CRS */
868 IMX_PIN_REG(MX51_PAD_DI2_PIN2, 0x74c, 0x344, 0, 0x000, 0), /* MX51_PAD_DI2_PIN2__DI2_PIN2 */
869 IMX_PIN_REG(MX51_PAD_DI2_PIN2, 0x74c, 0x344, 2, 0x000, 0), /* MX51_PAD_DI2_PIN2__FEC_MDC */
870 IMX_PIN_REG(MX51_PAD_DI2_PIN3, 0x750, 0x348, 0, 0x000, 0), /* MX51_PAD_DI2_PIN3__DI2_PIN3 */
871 IMX_PIN_REG(MX51_PAD_DI2_PIN3, 0x750, 0x348, 2, 0x954, 1), /* MX51_PAD_DI2_PIN3__FEC_MDIO */
872 IMX_PIN_REG(MX51_PAD_DI2_DISP_CLK, 0x754, 0x34c, 0, 0x000, 0), /* MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK */
873 IMX_PIN_REG(MX51_PAD_DI2_DISP_CLK, 0x754, 0x34c, 2, 0x95c, 1), /* MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 */
874 IMX_PIN_REG(MX51_PAD_DI_GP4, 0x758, 0x350, 4, 0x000, 0), /* MX51_PAD_DI_GP4__DI2_PIN15 */
875 IMX_PIN_REG(MX51_PAD_DI_GP4, 0x758, 0x350, 0, 0x9c0, 1), /* MX51_PAD_DI_GP4__DISP1_SER_DIN */
876 IMX_PIN_REG(MX51_PAD_DI_GP4, 0x758, 0x350, 3, 0x000, 0), /* MX51_PAD_DI_GP4__DISP2_PIN1 */
877 IMX_PIN_REG(MX51_PAD_DI_GP4, 0x758, 0x350, 2, 0x960, 1), /* MX51_PAD_DI_GP4__FEC_RDATA2 */
878 IMX_PIN_REG(MX51_PAD_DISP2_DAT0, 0x75c, 0x354, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT0__DISP2_DAT0 */
879 IMX_PIN_REG(MX51_PAD_DISP2_DAT0, 0x75c, 0x354, 2, 0x964, 1), /* MX51_PAD_DISP2_DAT0__FEC_RDATA3 */
880 IMX_PIN_REG(MX51_PAD_DISP2_DAT0, 0x75c, 0x354, 4, 0x9c8, 1), /* MX51_PAD_DISP2_DAT0__KEY_COL6 */
881 IMX_PIN_REG(MX51_PAD_DISP2_DAT0, 0x75c, 0x354, 5, 0x9f4, 8), /* MX51_PAD_DISP2_DAT0__UART3_RXD */
882 IMX_PIN_REG(MX51_PAD_DISP2_DAT0, 0x75c, 0x354, 3, 0x9f8, 1), /* MX51_PAD_DISP2_DAT0__USBH3_CLK */
883 IMX_PIN_REG(MX51_PAD_DISP2_DAT1, 0x760, 0x358, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT1__DISP2_DAT1 */
884 IMX_PIN_REG(MX51_PAD_DISP2_DAT1, 0x760, 0x358, 2, 0x970, 1), /* MX51_PAD_DISP2_DAT1__FEC_RX_ER */
885 IMX_PIN_REG(MX51_PAD_DISP2_DAT1, 0x760, 0x358, 4, 0x9cc, 1), /* MX51_PAD_DISP2_DAT1__KEY_COL7 */
886 IMX_PIN_REG(MX51_PAD_DISP2_DAT1, 0x760, 0x358, 5, 0x000, 0), /* MX51_PAD_DISP2_DAT1__UART3_TXD */
887 IMX_PIN_REG(MX51_PAD_DISP2_DAT1, 0x760, 0x358, 3, 0xa1c, 1), /* MX51_PAD_DISP2_DAT1__USBH3_DIR */
888 IMX_PIN_REG(MX51_PAD_DISP2_DAT2, 0x764, 0x35c, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT2__DISP2_DAT2 */
889 IMX_PIN_REG(MX51_PAD_DISP2_DAT3, 0x768, 0x360, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT3__DISP2_DAT3 */
890 IMX_PIN_REG(MX51_PAD_DISP2_DAT4, 0x76c, 0x364, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT4__DISP2_DAT4 */
891 IMX_PIN_REG(MX51_PAD_DISP2_DAT5, 0x770, 0x368, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT5__DISP2_DAT5 */
892 IMX_PIN_REG(MX51_PAD_DISP2_DAT6, 0x774, 0x36c, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT6__DISP2_DAT6 */
893 IMX_PIN_REG(MX51_PAD_DISP2_DAT6, 0x774, 0x36c, 2, 0x000, 0), /* MX51_PAD_DISP2_DAT6__FEC_TDATA1 */
894 IMX_PIN_REG(MX51_PAD_DISP2_DAT6, 0x774, 0x36c, 5, 0x000, 0), /* MX51_PAD_DISP2_DAT6__GPIO1_19 */
895 IMX_PIN_REG(MX51_PAD_DISP2_DAT6, 0x774, 0x36c, 4, 0x9d0, 1), /* MX51_PAD_DISP2_DAT6__KEY_ROW4 */
896 IMX_PIN_REG(MX51_PAD_DISP2_DAT6, 0x774, 0x36c, 3, 0xa24, 1), /* MX51_PAD_DISP2_DAT6__USBH3_STP */
897 IMX_PIN_REG(MX51_PAD_DISP2_DAT7, 0x778, 0x370, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT7__DISP2_DAT7 */
898 IMX_PIN_REG(MX51_PAD_DISP2_DAT7, 0x778, 0x370, 2, 0x000, 0), /* MX51_PAD_DISP2_DAT7__FEC_TDATA2 */
899 IMX_PIN_REG(MX51_PAD_DISP2_DAT7, 0x778, 0x370, 5, 0x000, 0), /* MX51_PAD_DISP2_DAT7__GPIO1_29 */
900 IMX_PIN_REG(MX51_PAD_DISP2_DAT7, 0x778, 0x370, 4, 0x9d4, 1), /* MX51_PAD_DISP2_DAT7__KEY_ROW5 */
901 IMX_PIN_REG(MX51_PAD_DISP2_DAT7, 0x778, 0x370, 3, 0xa20, 1), /* MX51_PAD_DISP2_DAT7__USBH3_NXT */
902 IMX_PIN_REG(MX51_PAD_DISP2_DAT8, 0x77c, 0x374, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT8__DISP2_DAT8 */
903 IMX_PIN_REG(MX51_PAD_DISP2_DAT8, 0x77c, 0x374, 2, 0x000, 0), /* MX51_PAD_DISP2_DAT8__FEC_TDATA3 */
904 IMX_PIN_REG(MX51_PAD_DISP2_DAT8, 0x77c, 0x374, 5, 0x000, 0), /* MX51_PAD_DISP2_DAT8__GPIO1_30 */
905 IMX_PIN_REG(MX51_PAD_DISP2_DAT8, 0x77c, 0x374, 4, 0x9d8, 1), /* MX51_PAD_DISP2_DAT8__KEY_ROW6 */
906 IMX_PIN_REG(MX51_PAD_DISP2_DAT8, 0x77c, 0x374, 3, 0x9fc, 1), /* MX51_PAD_DISP2_DAT8__USBH3_DATA0 */
907 IMX_PIN_REG(MX51_PAD_DISP2_DAT9, 0x780, 0x378, 4, 0x8f4, 1), /* MX51_PAD_DISP2_DAT9__AUD6_RXC */
908 IMX_PIN_REG(MX51_PAD_DISP2_DAT9, 0x780, 0x378, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT9__DISP2_DAT9 */
909 IMX_PIN_REG(MX51_PAD_DISP2_DAT9, 0x780, 0x378, 2, 0x000, 0), /* MX51_PAD_DISP2_DAT9__FEC_TX_EN */
910 IMX_PIN_REG(MX51_PAD_DISP2_DAT9, 0x780, 0x378, 5, 0x000, 0), /* MX51_PAD_DISP2_DAT9__GPIO1_31 */
911 IMX_PIN_REG(MX51_PAD_DISP2_DAT9, 0x780, 0x378, 3, 0xa00, 1), /* MX51_PAD_DISP2_DAT9__USBH3_DATA1 */
912 IMX_PIN_REG(MX51_PAD_DISP2_DAT10, 0x784, 0x37c, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT10__DISP2_DAT10 */
913 IMX_PIN_REG(MX51_PAD_DISP2_DAT10, 0x784, 0x37c, 5, 0x000, 0), /* MX51_PAD_DISP2_DAT10__DISP2_SER_CS */
914 IMX_PIN_REG(MX51_PAD_DISP2_DAT10, 0x784, 0x37c, 2, 0x94c, 1), /* MX51_PAD_DISP2_DAT10__FEC_COL */
915 IMX_PIN_REG(MX51_PAD_DISP2_DAT10, 0x784, 0x37c, 4, 0x9dc, 1), /* MX51_PAD_DISP2_DAT10__KEY_ROW7 */
916 IMX_PIN_REG(MX51_PAD_DISP2_DAT10, 0x784, 0x37c, 3, 0xa04, 1), /* MX51_PAD_DISP2_DAT10__USBH3_DATA2 */
917 IMX_PIN_REG(MX51_PAD_DISP2_DAT11, 0x788, 0x380, 4, 0x8f0, 1), /* MX51_PAD_DISP2_DAT11__AUD6_TXD */
918 IMX_PIN_REG(MX51_PAD_DISP2_DAT11, 0x788, 0x380, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT11__DISP2_DAT11 */
919 IMX_PIN_REG(MX51_PAD_DISP2_DAT11, 0x788, 0x380, 2, 0x968, 1), /* MX51_PAD_DISP2_DAT11__FEC_RX_CLK */
920 IMX_PIN_REG(MX51_PAD_DISP2_DAT11, 0x788, 0x380, 7, 0x000, 0), /* MX51_PAD_DISP2_DAT11__GPIO1_10 */
921 IMX_PIN_REG(MX51_PAD_DISP2_DAT11, 0x788, 0x380, 3, 0xa08, 1), /* MX51_PAD_DISP2_DAT11__USBH3_DATA3 */
922 IMX_PIN_REG(MX51_PAD_DISP2_DAT12, 0x78c, 0x384, 4, 0x8ec, 1), /* MX51_PAD_DISP2_DAT12__AUD6_RXD */
923 IMX_PIN_REG(MX51_PAD_DISP2_DAT12, 0x78c, 0x384, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT12__DISP2_DAT12 */
924 IMX_PIN_REG(MX51_PAD_DISP2_DAT12, 0x78c, 0x384, 2, 0x96c, 1), /* MX51_PAD_DISP2_DAT12__FEC_RX_DV */
925 IMX_PIN_REG(MX51_PAD_DISP2_DAT12, 0x78c, 0x384, 3, 0xa0c, 1), /* MX51_PAD_DISP2_DAT12__USBH3_DATA4 */
926 IMX_PIN_REG(MX51_PAD_DISP2_DAT13, 0x790, 0x388, 4, 0x8fc, 1), /* MX51_PAD_DISP2_DAT13__AUD6_TXC */
927 IMX_PIN_REG(MX51_PAD_DISP2_DAT13, 0x790, 0x388, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT13__DISP2_DAT13 */
928 IMX_PIN_REG(MX51_PAD_DISP2_DAT13, 0x790, 0x388, 2, 0x974, 1), /* MX51_PAD_DISP2_DAT13__FEC_TX_CLK */
929 IMX_PIN_REG(MX51_PAD_DISP2_DAT13, 0x790, 0x388, 3, 0xa10, 1), /* MX51_PAD_DISP2_DAT13__USBH3_DATA5 */
930 IMX_PIN_REG(MX51_PAD_DISP2_DAT14, 0x794, 0x38c, 4, 0x900, 1), /* MX51_PAD_DISP2_DAT14__AUD6_TXFS */
931 IMX_PIN_REG(MX51_PAD_DISP2_DAT14, 0x794, 0x38c, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT14__DISP2_DAT14 */
932 IMX_PIN_REG(MX51_PAD_DISP2_DAT14, 0x794, 0x38c, 2, 0x958, 1), /* MX51_PAD_DISP2_DAT14__FEC_RDATA0 */
933 IMX_PIN_REG(MX51_PAD_DISP2_DAT14, 0x794, 0x38c, 3, 0xa14, 1), /* MX51_PAD_DISP2_DAT14__USBH3_DATA6 */
934 IMX_PIN_REG(MX51_PAD_DISP2_DAT15, 0x798, 0x390, 4, 0x8f8, 1), /* MX51_PAD_DISP2_DAT15__AUD6_RXFS */
935 IMX_PIN_REG(MX51_PAD_DISP2_DAT15, 0x798, 0x390, 5, 0x000, 0), /* MX51_PAD_DISP2_DAT15__DISP1_SER_CS */
936 IMX_PIN_REG(MX51_PAD_DISP2_DAT15, 0x798, 0x390, 0, 0x000, 0), /* MX51_PAD_DISP2_DAT15__DISP2_DAT15 */
937 IMX_PIN_REG(MX51_PAD_DISP2_DAT15, 0x798, 0x390, 2, 0x000, 0), /* MX51_PAD_DISP2_DAT15__FEC_TDATA0 */
938 IMX_PIN_REG(MX51_PAD_DISP2_DAT15, 0x798, 0x390, 3, 0xa18, 1), /* MX51_PAD_DISP2_DAT15__USBH3_DATA7 */
939 IMX_PIN_REG(MX51_PAD_SD1_CMD, 0x79c, 0x394, 1, 0x8e0, 1), /* MX51_PAD_SD1_CMD__AUD5_RXFS */
940 IMX_PIN_REG(MX51_PAD_SD1_CMD, 0x79c, 0x394, 2, 0x91c, 2), /* MX51_PAD_SD1_CMD__CSPI_MOSI */
941 IMX_PIN_REG(MX51_PAD_SD1_CMD, 0x79c, 0x394, 0, 0x000, 0), /* MX51_PAD_SD1_CMD__SD1_CMD */
942 IMX_PIN_REG(MX51_PAD_SD1_CLK, 0x7a0, 0x398, 1, 0x8dc, 1), /* MX51_PAD_SD1_CLK__AUD5_RXC */
943 IMX_PIN_REG(MX51_PAD_SD1_CLK, 0x7a0, 0x398, 2, 0x914, 2), /* MX51_PAD_SD1_CLK__CSPI_SCLK */
944 IMX_PIN_REG(MX51_PAD_SD1_CLK, 0x7a0, 0x398, 0, 0x000, 0), /* MX51_PAD_SD1_CLK__SD1_CLK */
945 IMX_PIN_REG(MX51_PAD_SD1_DATA0, 0x7a4, 0x39c, 1, 0x8d8, 2), /* MX51_PAD_SD1_DATA0__AUD5_TXD */
946 IMX_PIN_REG(MX51_PAD_SD1_DATA0, 0x7a4, 0x39c, 2, 0x918, 1), /* MX51_PAD_SD1_DATA0__CSPI_MISO */
947 IMX_PIN_REG(MX51_PAD_SD1_DATA0, 0x7a4, 0x39c, 0, 0x000, 0), /* MX51_PAD_SD1_DATA0__SD1_DATA0 */
948 IMX_PIN_REG(MX51_PAD_EIM_DA0, NO_PAD, 0x01c, 0, 0x000, 0), /* MX51_PAD_EIM_DA0__EIM_DA0 */
949 IMX_PIN_REG(MX51_PAD_EIM_DA1, NO_PAD, 0x020, 0, 0x000, 0), /* MX51_PAD_EIM_DA1__EIM_DA1 */
950 IMX_PIN_REG(MX51_PAD_EIM_DA2, NO_PAD, 0x024, 0, 0x000, 0), /* MX51_PAD_EIM_DA2__EIM_DA2 */
951 IMX_PIN_REG(MX51_PAD_EIM_DA3, NO_PAD, 0x028, 0, 0x000, 0), /* MX51_PAD_EIM_DA3__EIM_DA3 */
952 IMX_PIN_REG(MX51_PAD_SD1_DATA1, 0x7a8, 0x3a0, 1, 0x8d4, 2), /* MX51_PAD_SD1_DATA1__AUD5_RXD */
953 IMX_PIN_REG(MX51_PAD_SD1_DATA1, 0x7a8, 0x3a0, 0, 0x000, 0), /* MX51_PAD_SD1_DATA1__SD1_DATA1 */
954 IMX_PIN_REG(MX51_PAD_EIM_DA4, NO_PAD, 0x02c, 0, 0x000, 0), /* MX51_PAD_EIM_DA4__EIM_DA4 */
955 IMX_PIN_REG(MX51_PAD_EIM_DA5, NO_PAD, 0x030, 0, 0x000, 0), /* MX51_PAD_EIM_DA5__EIM_DA5 */
956 IMX_PIN_REG(MX51_PAD_EIM_DA6, NO_PAD, 0x034, 0, 0x000, 0), /* MX51_PAD_EIM_DA6__EIM_DA6 */
957 IMX_PIN_REG(MX51_PAD_EIM_DA7, NO_PAD, 0x038, 0, 0x000, 0), /* MX51_PAD_EIM_DA7__EIM_DA7 */
958 IMX_PIN_REG(MX51_PAD_SD1_DATA2, 0x7ac, 0x3a4, 1, 0x8e4, 2), /* MX51_PAD_SD1_DATA2__AUD5_TXC */
959 IMX_PIN_REG(MX51_PAD_SD1_DATA2, 0x7ac, 0x3a4, 0, 0x000, 0), /* MX51_PAD_SD1_DATA2__SD1_DATA2 */
960 IMX_PIN_REG(MX51_PAD_EIM_DA10, NO_PAD, 0x044, 0, 0x000, 0), /* MX51_PAD_EIM_DA10__EIM_DA10 */
961 IMX_PIN_REG(MX51_PAD_EIM_DA11, NO_PAD, 0x048, 0, 0x000, 0), /* MX51_PAD_EIM_DA11__EIM_DA11 */
962 IMX_PIN_REG(MX51_PAD_EIM_DA8, NO_PAD, 0x03c, 0, 0x000, 0), /* MX51_PAD_EIM_DA8__EIM_DA8 */
963 IMX_PIN_REG(MX51_PAD_EIM_DA9, NO_PAD, 0x040, 0, 0x000, 0), /* MX51_PAD_EIM_DA9__EIM_DA9 */
964 IMX_PIN_REG(MX51_PAD_SD1_DATA3, 0x7b0, 0x3a8, 1, 0x8e8, 2), /* MX51_PAD_SD1_DATA3__AUD5_TXFS */
965 IMX_PIN_REG(MX51_PAD_SD1_DATA3, 0x7b0, 0x3a8, 2, 0x920, 1), /* MX51_PAD_SD1_DATA3__CSPI_SS1 */
966 IMX_PIN_REG(MX51_PAD_SD1_DATA3, 0x7b0, 0x3a8, 0, 0x000, 0), /* MX51_PAD_SD1_DATA3__SD1_DATA3 */
967 IMX_PIN_REG(MX51_PAD_GPIO1_0, 0x7b4, 0x3ac, 2, 0x924, 0), /* MX51_PAD_GPIO1_0__CSPI_SS2 */
968 IMX_PIN_REG(MX51_PAD_GPIO1_0, 0x7b4, 0x3ac, 1, 0x000, 0), /* MX51_PAD_GPIO1_0__GPIO1_0 */
969 IMX_PIN_REG(MX51_PAD_GPIO1_0, 0x7b4, 0x3ac, 0, 0x000, 0), /* MX51_PAD_GPIO1_0__SD1_CD */
970 IMX_PIN_REG(MX51_PAD_GPIO1_1, 0x7b8, 0x3b0, 2, 0x918, 2), /* MX51_PAD_GPIO1_1__CSPI_MISO */
971 IMX_PIN_REG(MX51_PAD_GPIO1_1, 0x7b8, 0x3b0, 1, 0x000, 0), /* MX51_PAD_GPIO1_1__GPIO1_1 */
972 IMX_PIN_REG(MX51_PAD_GPIO1_1, 0x7b8, 0x3b0, 0, 0x000, 0), /* MX51_PAD_GPIO1_1__SD1_WP */
973 IMX_PIN_REG(MX51_PAD_EIM_DA12, NO_PAD, 0x04c, 0, 0x000, 0), /* MX51_PAD_EIM_DA12__EIM_DA12 */
974 IMX_PIN_REG(MX51_PAD_EIM_DA13, NO_PAD, 0x050, 0, 0x000, 0), /* MX51_PAD_EIM_DA13__EIM_DA13 */
975 IMX_PIN_REG(MX51_PAD_EIM_DA14, NO_PAD, 0x054, 0, 0x000, 0), /* MX51_PAD_EIM_DA14__EIM_DA14 */
976 IMX_PIN_REG(MX51_PAD_EIM_DA15, NO_PAD, 0x058, 0, 0x000, 0), /* MX51_PAD_EIM_DA15__EIM_DA15 */
977 IMX_PIN_REG(MX51_PAD_SD2_CMD, NO_PAD, 0x3b4, 2, 0x91c, 3), /* MX51_PAD_SD2_CMD__CSPI_MOSI */
978 IMX_PIN_REG(MX51_PAD_SD2_CMD, 0x7bc, 0x3b4, 1, 0x9b0, 2), /* MX51_PAD_SD2_CMD__I2C1_SCL */
979 IMX_PIN_REG(MX51_PAD_SD2_CMD, 0x7bc, 0x3b4, 0, 0x000, 0), /* MX51_PAD_SD2_CMD__SD2_CMD */
980 IMX_PIN_REG(MX51_PAD_SD2_CLK, 0x7c0, 0x3b8, 2, 0x914, 3), /* MX51_PAD_SD2_CLK__CSPI_SCLK */
981 IMX_PIN_REG(MX51_PAD_SD2_CLK, 0x7c0, 0x3b8, 1, 0x9b4, 2), /* MX51_PAD_SD2_CLK__I2C1_SDA */
982 IMX_PIN_REG(MX51_PAD_SD2_CLK, 0x7c0, 0x3b8, 0, 0x000, 0), /* MX51_PAD_SD2_CLK__SD2_CLK */
983 IMX_PIN_REG(MX51_PAD_SD2_DATA0, 0x7c4, 0x3bc, 2, 0x918, 3), /* MX51_PAD_SD2_DATA0__CSPI_MISO */
984 IMX_PIN_REG(MX51_PAD_SD2_DATA0, 0x7c4, 0x3bc, 1, 0x000, 0), /* MX51_PAD_SD2_DATA0__SD1_DAT4 */
985 IMX_PIN_REG(MX51_PAD_SD2_DATA0, 0x7c4, 0x3bc, 0, 0x000, 0), /* MX51_PAD_SD2_DATA0__SD2_DATA0 */
986 IMX_PIN_REG(MX51_PAD_SD2_DATA1, 0x7c8, 0x3c0, 1, 0x000, 0), /* MX51_PAD_SD2_DATA1__SD1_DAT5 */
987 IMX_PIN_REG(MX51_PAD_SD2_DATA1, 0x7c8, 0x3c0, 0, 0x000, 0), /* MX51_PAD_SD2_DATA1__SD2_DATA1 */
988 IMX_PIN_REG(MX51_PAD_SD2_DATA1, 0x7c8, 0x3c0, 2, 0x000, 0), /* MX51_PAD_SD2_DATA1__USBH3_H2_DP */
989 IMX_PIN_REG(MX51_PAD_SD2_DATA2, 0x7cc, 0x3c4, 1, 0x000, 0), /* MX51_PAD_SD2_DATA2__SD1_DAT6 */
990 IMX_PIN_REG(MX51_PAD_SD2_DATA2, 0x7cc, 0x3c4, 0, 0x000, 0), /* MX51_PAD_SD2_DATA2__SD2_DATA2 */
991 IMX_PIN_REG(MX51_PAD_SD2_DATA2, 0x7cc, 0x3c4, 2, 0x000, 0), /* MX51_PAD_SD2_DATA2__USBH3_H2_DM */
992 IMX_PIN_REG(MX51_PAD_SD2_DATA3, 0x7d0, 0x3c8, 2, 0x924, 1), /* MX51_PAD_SD2_DATA3__CSPI_SS2 */
993 IMX_PIN_REG(MX51_PAD_SD2_DATA3, 0x7d0, 0x3c8, 1, 0x000, 0), /* MX51_PAD_SD2_DATA3__SD1_DAT7 */
994 IMX_PIN_REG(MX51_PAD_SD2_DATA3, 0x7d0, 0x3c8, 0, 0x000, 0), /* MX51_PAD_SD2_DATA3__SD2_DATA3 */
995 IMX_PIN_REG(MX51_PAD_GPIO1_2, 0x7d4, 0x3cc, 5, 0x000, 0), /* MX51_PAD_GPIO1_2__CCM_OUT_2 */
996 IMX_PIN_REG(MX51_PAD_GPIO1_2, 0x7d4, 0x3cc, 0, 0x000, 0), /* MX51_PAD_GPIO1_2__GPIO1_2 */
997 IMX_PIN_REG(MX51_PAD_GPIO1_2, 0x7d4, 0x3cc, 2, 0x9b8, 3), /* MX51_PAD_GPIO1_2__I2C2_SCL */
998 IMX_PIN_REG(MX51_PAD_GPIO1_2, 0x7d4, 0x3cc, 7, 0x90c, 1), /* MX51_PAD_GPIO1_2__PLL1_BYP */
999 IMX_PIN_REG(MX51_PAD_GPIO1_2, 0x7d4, 0x3cc, 1, 0x000, 0), /* MX51_PAD_GPIO1_2__PWM1_PWMO */
1000 IMX_PIN_REG(MX51_PAD_GPIO1_3, 0x7d8, 0x3d0, 0, 0x000, 0), /* MX51_PAD_GPIO1_3__GPIO1_3 */
1001 IMX_PIN_REG(MX51_PAD_GPIO1_3, 0x7d8, 0x3d0, 2, 0x9bc, 3), /* MX51_PAD_GPIO1_3__I2C2_SDA */
1002 IMX_PIN_REG(MX51_PAD_GPIO1_3, 0x7d8, 0x3d0, 7, 0x910, 1), /* MX51_PAD_GPIO1_3__PLL2_BYP */
1003 IMX_PIN_REG(MX51_PAD_GPIO1_3, 0x7d8, 0x3d0, 1, 0x000, 0), /* MX51_PAD_GPIO1_3__PWM2_PWMO */
1004 IMX_PIN_REG(MX51_PAD_PMIC_INT_REQ, 0x7fc, 0x3d4, 0, 0x000, 0), /* MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ */
1005 IMX_PIN_REG(MX51_PAD_PMIC_INT_REQ, 0x7fc, 0x3d4, 1, 0x000, 0), /* MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B */
1006 IMX_PIN_REG(MX51_PAD_GPIO1_4, 0x804, 0x3d8, 4, 0x908, 1), /* MX51_PAD_GPIO1_4__DISP2_EXT_CLK */
1007 IMX_PIN_REG(MX51_PAD_GPIO1_4, 0x804, 0x3d8, 3, 0x938, 1), /* MX51_PAD_GPIO1_4__EIM_RDY */
1008 IMX_PIN_REG(MX51_PAD_GPIO1_4, 0x804, 0x3d8, 0, 0x000, 0), /* MX51_PAD_GPIO1_4__GPIO1_4 */
1009 IMX_PIN_REG(MX51_PAD_GPIO1_4, 0x804, 0x3d8, 2, 0x000, 0), /* MX51_PAD_GPIO1_4__WDOG1_WDOG_B */
1010 IMX_PIN_REG(MX51_PAD_GPIO1_5, 0x808, 0x3dc, 6, 0x000, 0), /* MX51_PAD_GPIO1_5__CSI2_MCLK */
1011 IMX_PIN_REG(MX51_PAD_GPIO1_5, 0x808, 0x3dc, 3, 0x000, 0), /* MX51_PAD_GPIO1_5__DISP2_PIN16 */
1012 IMX_PIN_REG(MX51_PAD_GPIO1_5, 0x808, 0x3dc, 0, 0x000, 0), /* MX51_PAD_GPIO1_5__GPIO1_5 */
1013 IMX_PIN_REG(MX51_PAD_GPIO1_5, 0x808, 0x3dc, 2, 0x000, 0), /* MX51_PAD_GPIO1_5__WDOG2_WDOG_B */
1014 IMX_PIN_REG(MX51_PAD_GPIO1_6, 0x80c, 0x3e0, 4, 0x000, 0), /* MX51_PAD_GPIO1_6__DISP2_PIN17 */
1015 IMX_PIN_REG(MX51_PAD_GPIO1_6, 0x80c, 0x3e0, 0, 0x000, 0), /* MX51_PAD_GPIO1_6__GPIO1_6 */
1016 IMX_PIN_REG(MX51_PAD_GPIO1_6, 0x80c, 0x3e0, 3, 0x000, 0), /* MX51_PAD_GPIO1_6__REF_EN_B */
1017 IMX_PIN_REG(MX51_PAD_GPIO1_7, 0x810, 0x3e4, 3, 0x000, 0), /* MX51_PAD_GPIO1_7__CCM_OUT_0 */
1018 IMX_PIN_REG(MX51_PAD_GPIO1_7, 0x810, 0x3e4, 0, 0x000, 0), /* MX51_PAD_GPIO1_7__GPIO1_7 */
1019 IMX_PIN_REG(MX51_PAD_GPIO1_7, 0x810, 0x3e4, 6, 0x000, 0), /* MX51_PAD_GPIO1_7__SD2_WP */
1020 IMX_PIN_REG(MX51_PAD_GPIO1_7, 0x810, 0x3e4, 2, 0x000, 0), /* MX51_PAD_GPIO1_7__SPDIF_OUT1 */
1021 IMX_PIN_REG(MX51_PAD_GPIO1_8, 0x814, 0x3e8, 2, 0x99c, 2), /* MX51_PAD_GPIO1_8__CSI2_DATA_EN */
1022 IMX_PIN_REG(MX51_PAD_GPIO1_8, 0x814, 0x3e8, 0, 0x000, 0), /* MX51_PAD_GPIO1_8__GPIO1_8 */
1023 IMX_PIN_REG(MX51_PAD_GPIO1_8, 0x814, 0x3e8, 6, 0x000, 0), /* MX51_PAD_GPIO1_8__SD2_CD */
1024 IMX_PIN_REG(MX51_PAD_GPIO1_8, 0x814, 0x3e8, 1, 0x000, 0), /* MX51_PAD_GPIO1_8__USBH3_PWR */
1025 IMX_PIN_REG(MX51_PAD_GPIO1_9, 0x818, 0x3ec, 3, 0x000, 0), /* MX51_PAD_GPIO1_9__CCM_OUT_1 */
1026 IMX_PIN_REG(MX51_PAD_GPIO1_9, 0x818, 0x3ec, 2, 0x000, 0), /* MX51_PAD_GPIO1_9__DISP2_D1_CS */
1027 IMX_PIN_REG(MX51_PAD_GPIO1_9, 0x818, 0x3ec, 7, 0x000, 0), /* MX51_PAD_GPIO1_9__DISP2_SER_CS */
1028 IMX_PIN_REG(MX51_PAD_GPIO1_9, 0x818, 0x3ec, 0, 0x000, 0), /* MX51_PAD_GPIO1_9__GPIO1_9 */
1029 IMX_PIN_REG(MX51_PAD_GPIO1_9, 0x818, 0x3ec, 6, 0x000, 0), /* MX51_PAD_GPIO1_9__SD2_LCTL */
1030 IMX_PIN_REG(MX51_PAD_GPIO1_9, 0x818, 0x3ec, 1, 0x000, 0), /* MX51_PAD_GPIO1_9__USBH3_OC */
1031};
1032
1033/* Pad names for the pinmux subsystem */
1034static const struct pinctrl_pin_desc imx51_pinctrl_pads[] = {
1035 IMX_PINCTRL_PIN(MX51_PAD_EIM_D16),
1036 IMX_PINCTRL_PIN(MX51_PAD_EIM_D17),
1037 IMX_PINCTRL_PIN(MX51_PAD_EIM_D18),
1038 IMX_PINCTRL_PIN(MX51_PAD_EIM_D19),
1039 IMX_PINCTRL_PIN(MX51_PAD_EIM_D20),
1040 IMX_PINCTRL_PIN(MX51_PAD_EIM_D21),
1041 IMX_PINCTRL_PIN(MX51_PAD_EIM_D22),
1042 IMX_PINCTRL_PIN(MX51_PAD_EIM_D23),
1043 IMX_PINCTRL_PIN(MX51_PAD_EIM_D24),
1044 IMX_PINCTRL_PIN(MX51_PAD_EIM_D25),
1045 IMX_PINCTRL_PIN(MX51_PAD_EIM_D26),
1046 IMX_PINCTRL_PIN(MX51_PAD_EIM_D27),
1047 IMX_PINCTRL_PIN(MX51_PAD_EIM_D28),
1048 IMX_PINCTRL_PIN(MX51_PAD_EIM_D29),
1049 IMX_PINCTRL_PIN(MX51_PAD_EIM_D30),
1050 IMX_PINCTRL_PIN(MX51_PAD_EIM_D31),
1051 IMX_PINCTRL_PIN(MX51_PAD_EIM_A16),
1052 IMX_PINCTRL_PIN(MX51_PAD_EIM_A17),
1053 IMX_PINCTRL_PIN(MX51_PAD_EIM_A18),
1054 IMX_PINCTRL_PIN(MX51_PAD_EIM_A19),
1055 IMX_PINCTRL_PIN(MX51_PAD_EIM_A20),
1056 IMX_PINCTRL_PIN(MX51_PAD_EIM_A21),
1057 IMX_PINCTRL_PIN(MX51_PAD_EIM_A22),
1058 IMX_PINCTRL_PIN(MX51_PAD_EIM_A23),
1059 IMX_PINCTRL_PIN(MX51_PAD_EIM_A24),
1060 IMX_PINCTRL_PIN(MX51_PAD_EIM_A25),
1061 IMX_PINCTRL_PIN(MX51_PAD_EIM_A26),
1062 IMX_PINCTRL_PIN(MX51_PAD_EIM_A27),
1063 IMX_PINCTRL_PIN(MX51_PAD_EIM_EB0),
1064 IMX_PINCTRL_PIN(MX51_PAD_EIM_EB1),
1065 IMX_PINCTRL_PIN(MX51_PAD_EIM_EB2),
1066 IMX_PINCTRL_PIN(MX51_PAD_EIM_EB3),
1067 IMX_PINCTRL_PIN(MX51_PAD_EIM_OE),
1068 IMX_PINCTRL_PIN(MX51_PAD_EIM_CS0),
1069 IMX_PINCTRL_PIN(MX51_PAD_EIM_CS1),
1070 IMX_PINCTRL_PIN(MX51_PAD_EIM_CS2),
1071 IMX_PINCTRL_PIN(MX51_PAD_EIM_CS3),
1072 IMX_PINCTRL_PIN(MX51_PAD_EIM_CS4),
1073 IMX_PINCTRL_PIN(MX51_PAD_EIM_CS5),
1074 IMX_PINCTRL_PIN(MX51_PAD_EIM_DTACK),
1075 IMX_PINCTRL_PIN(MX51_PAD_EIM_LBA),
1076 IMX_PINCTRL_PIN(MX51_PAD_EIM_CRE),
1077 IMX_PINCTRL_PIN(MX51_PAD_DRAM_CS1),
1078 IMX_PINCTRL_PIN(MX51_PAD_NANDF_WE_B),
1079 IMX_PINCTRL_PIN(MX51_PAD_NANDF_RE_B),
1080 IMX_PINCTRL_PIN(MX51_PAD_NANDF_ALE),
1081 IMX_PINCTRL_PIN(MX51_PAD_NANDF_CLE),
1082 IMX_PINCTRL_PIN(MX51_PAD_NANDF_WP_B),
1083 IMX_PINCTRL_PIN(MX51_PAD_NANDF_RB0),
1084 IMX_PINCTRL_PIN(MX51_PAD_NANDF_RB1),
1085 IMX_PINCTRL_PIN(MX51_PAD_NANDF_RB2),
1086 IMX_PINCTRL_PIN(MX51_PAD_NANDF_RB3),
1087 IMX_PINCTRL_PIN(MX51_PAD_GPIO_NAND),
1088 IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS0),
1089 IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS1),
1090 IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS2),
1091 IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS3),
1092 IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS4),
1093 IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS5),
1094 IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS6),
1095 IMX_PINCTRL_PIN(MX51_PAD_NANDF_CS7),
1096 IMX_PINCTRL_PIN(MX51_PAD_NANDF_RDY_INT),
1097 IMX_PINCTRL_PIN(MX51_PAD_NANDF_D15),
1098 IMX_PINCTRL_PIN(MX51_PAD_NANDF_D14),
1099 IMX_PINCTRL_PIN(MX51_PAD_NANDF_D13),
1100 IMX_PINCTRL_PIN(MX51_PAD_NANDF_D12),
1101 IMX_PINCTRL_PIN(MX51_PAD_NANDF_D11),
1102 IMX_PINCTRL_PIN(MX51_PAD_NANDF_D10),
1103 IMX_PINCTRL_PIN(MX51_PAD_NANDF_D9),
1104 IMX_PINCTRL_PIN(MX51_PAD_NANDF_D8),
1105 IMX_PINCTRL_PIN(MX51_PAD_NANDF_D7),
1106 IMX_PINCTRL_PIN(MX51_PAD_NANDF_D6),
1107 IMX_PINCTRL_PIN(MX51_PAD_NANDF_D5),
1108 IMX_PINCTRL_PIN(MX51_PAD_NANDF_D4),
1109 IMX_PINCTRL_PIN(MX51_PAD_NANDF_D3),
1110 IMX_PINCTRL_PIN(MX51_PAD_NANDF_D2),
1111 IMX_PINCTRL_PIN(MX51_PAD_NANDF_D1),
1112 IMX_PINCTRL_PIN(MX51_PAD_NANDF_D0),
1113 IMX_PINCTRL_PIN(MX51_PAD_CSI1_D8),
1114 IMX_PINCTRL_PIN(MX51_PAD_CSI1_D9),
1115 IMX_PINCTRL_PIN(MX51_PAD_CSI1_D10),
1116 IMX_PINCTRL_PIN(MX51_PAD_CSI1_D11),
1117 IMX_PINCTRL_PIN(MX51_PAD_CSI1_D12),
1118 IMX_PINCTRL_PIN(MX51_PAD_CSI1_D13),
1119 IMX_PINCTRL_PIN(MX51_PAD_CSI1_D14),
1120 IMX_PINCTRL_PIN(MX51_PAD_CSI1_D15),
1121 IMX_PINCTRL_PIN(MX51_PAD_CSI1_D16),
1122 IMX_PINCTRL_PIN(MX51_PAD_CSI1_D17),
1123 IMX_PINCTRL_PIN(MX51_PAD_CSI1_D18),
1124 IMX_PINCTRL_PIN(MX51_PAD_CSI1_D19),
1125 IMX_PINCTRL_PIN(MX51_PAD_CSI1_VSYNC),
1126 IMX_PINCTRL_PIN(MX51_PAD_CSI1_HSYNC),
1127 IMX_PINCTRL_PIN(MX51_PAD_CSI1_PIXCLK),
1128 IMX_PINCTRL_PIN(MX51_PAD_CSI1_MCLK),
1129 IMX_PINCTRL_PIN(MX51_PAD_CSI2_D12),
1130 IMX_PINCTRL_PIN(MX51_PAD_CSI2_D13),
1131 IMX_PINCTRL_PIN(MX51_PAD_CSI2_D14),
1132 IMX_PINCTRL_PIN(MX51_PAD_CSI2_D15),
1133 IMX_PINCTRL_PIN(MX51_PAD_CSI2_D16),
1134 IMX_PINCTRL_PIN(MX51_PAD_CSI2_D17),
1135 IMX_PINCTRL_PIN(MX51_PAD_CSI2_D18),
1136 IMX_PINCTRL_PIN(MX51_PAD_CSI2_D19),
1137 IMX_PINCTRL_PIN(MX51_PAD_CSI2_VSYNC),
1138 IMX_PINCTRL_PIN(MX51_PAD_CSI2_HSYNC),
1139 IMX_PINCTRL_PIN(MX51_PAD_CSI2_PIXCLK),
1140 IMX_PINCTRL_PIN(MX51_PAD_I2C1_CLK),
1141 IMX_PINCTRL_PIN(MX51_PAD_I2C1_DAT),
1142 IMX_PINCTRL_PIN(MX51_PAD_AUD3_BB_TXD),
1143 IMX_PINCTRL_PIN(MX51_PAD_AUD3_BB_RXD),
1144 IMX_PINCTRL_PIN(MX51_PAD_AUD3_BB_CK),
1145 IMX_PINCTRL_PIN(MX51_PAD_AUD3_BB_FS),
1146 IMX_PINCTRL_PIN(MX51_PAD_CSPI1_MOSI),
1147 IMX_PINCTRL_PIN(MX51_PAD_CSPI1_MISO),
1148 IMX_PINCTRL_PIN(MX51_PAD_CSPI1_SS0),
1149 IMX_PINCTRL_PIN(MX51_PAD_CSPI1_SS1),
1150 IMX_PINCTRL_PIN(MX51_PAD_CSPI1_RDY),
1151 IMX_PINCTRL_PIN(MX51_PAD_CSPI1_SCLK),
1152 IMX_PINCTRL_PIN(MX51_PAD_UART1_RXD),
1153 IMX_PINCTRL_PIN(MX51_PAD_UART1_TXD),
1154 IMX_PINCTRL_PIN(MX51_PAD_UART1_RTS),
1155 IMX_PINCTRL_PIN(MX51_PAD_UART1_CTS),
1156 IMX_PINCTRL_PIN(MX51_PAD_UART2_RXD),
1157 IMX_PINCTRL_PIN(MX51_PAD_UART2_TXD),
1158 IMX_PINCTRL_PIN(MX51_PAD_UART3_RXD),
1159 IMX_PINCTRL_PIN(MX51_PAD_UART3_TXD),
1160 IMX_PINCTRL_PIN(MX51_PAD_OWIRE_LINE),
1161 IMX_PINCTRL_PIN(MX51_PAD_KEY_ROW0),
1162 IMX_PINCTRL_PIN(MX51_PAD_KEY_ROW1),
1163 IMX_PINCTRL_PIN(MX51_PAD_KEY_ROW2),
1164 IMX_PINCTRL_PIN(MX51_PAD_KEY_ROW3),
1165 IMX_PINCTRL_PIN(MX51_PAD_KEY_COL0),
1166 IMX_PINCTRL_PIN(MX51_PAD_KEY_COL1),
1167 IMX_PINCTRL_PIN(MX51_PAD_KEY_COL2),
1168 IMX_PINCTRL_PIN(MX51_PAD_KEY_COL3),
1169 IMX_PINCTRL_PIN(MX51_PAD_KEY_COL4),
1170 IMX_PINCTRL_PIN(MX51_PAD_KEY_COL5),
1171 IMX_PINCTRL_PIN(MX51_PAD_USBH1_CLK),
1172 IMX_PINCTRL_PIN(MX51_PAD_USBH1_DIR),
1173 IMX_PINCTRL_PIN(MX51_PAD_USBH1_STP),
1174 IMX_PINCTRL_PIN(MX51_PAD_USBH1_NXT),
1175 IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA0),
1176 IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA1),
1177 IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA2),
1178 IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA3),
1179 IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA4),
1180 IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA5),
1181 IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA6),
1182 IMX_PINCTRL_PIN(MX51_PAD_USBH1_DATA7),
1183 IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN11),
1184 IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN12),
1185 IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN13),
1186 IMX_PINCTRL_PIN(MX51_PAD_DI1_D0_CS),
1187 IMX_PINCTRL_PIN(MX51_PAD_DI1_D1_CS),
1188 IMX_PINCTRL_PIN(MX51_PAD_DISPB2_SER_DIN),
1189 IMX_PINCTRL_PIN(MX51_PAD_DISPB2_SER_DIO),
1190 IMX_PINCTRL_PIN(MX51_PAD_DISPB2_SER_CLK),
1191 IMX_PINCTRL_PIN(MX51_PAD_DISPB2_SER_RS),
1192 IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT0),
1193 IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT1),
1194 IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT2),
1195 IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT3),
1196 IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT4),
1197 IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT5),
1198 IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT6),
1199 IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT7),
1200 IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT8),
1201 IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT9),
1202 IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT10),
1203 IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT11),
1204 IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT12),
1205 IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT13),
1206 IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT14),
1207 IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT15),
1208 IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT16),
1209 IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT17),
1210 IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT18),
1211 IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT19),
1212 IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT20),
1213 IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT21),
1214 IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT22),
1215 IMX_PINCTRL_PIN(MX51_PAD_DISP1_DAT23),
1216 IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN3),
1217 IMX_PINCTRL_PIN(MX51_PAD_DI1_PIN2),
1218 IMX_PINCTRL_PIN(MX51_PAD_DI_GP2),
1219 IMX_PINCTRL_PIN(MX51_PAD_DI_GP3),
1220 IMX_PINCTRL_PIN(MX51_PAD_DI2_PIN4),
1221 IMX_PINCTRL_PIN(MX51_PAD_DI2_PIN2),
1222 IMX_PINCTRL_PIN(MX51_PAD_DI2_PIN3),
1223 IMX_PINCTRL_PIN(MX51_PAD_DI2_DISP_CLK),
1224 IMX_PINCTRL_PIN(MX51_PAD_DI_GP4),
1225 IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT0),
1226 IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT1),
1227 IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT2),
1228 IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT3),
1229 IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT4),
1230 IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT5),
1231 IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT6),
1232 IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT7),
1233 IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT8),
1234 IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT9),
1235 IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT10),
1236 IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT11),
1237 IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT12),
1238 IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT13),
1239 IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT14),
1240 IMX_PINCTRL_PIN(MX51_PAD_DISP2_DAT15),
1241 IMX_PINCTRL_PIN(MX51_PAD_SD1_CMD),
1242 IMX_PINCTRL_PIN(MX51_PAD_SD1_CLK),
1243 IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA0),
1244 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA0),
1245 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA1),
1246 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA2),
1247 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA3),
1248 IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA1),
1249 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA4),
1250 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA5),
1251 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA6),
1252 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA7),
1253 IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA2),
1254 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA10),
1255 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA11),
1256 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA8),
1257 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA9),
1258 IMX_PINCTRL_PIN(MX51_PAD_SD1_DATA3),
1259 IMX_PINCTRL_PIN(MX51_PAD_GPIO1_0),
1260 IMX_PINCTRL_PIN(MX51_PAD_GPIO1_1),
1261 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA12),
1262 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA13),
1263 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA14),
1264 IMX_PINCTRL_PIN(MX51_PAD_EIM_DA15),
1265 IMX_PINCTRL_PIN(MX51_PAD_SD2_CMD),
1266 IMX_PINCTRL_PIN(MX51_PAD_SD2_CLK),
1267 IMX_PINCTRL_PIN(MX51_PAD_SD2_DATA0),
1268 IMX_PINCTRL_PIN(MX51_PAD_SD2_DATA1),
1269 IMX_PINCTRL_PIN(MX51_PAD_SD2_DATA2),
1270 IMX_PINCTRL_PIN(MX51_PAD_SD2_DATA3),
1271 IMX_PINCTRL_PIN(MX51_PAD_GPIO1_2),
1272 IMX_PINCTRL_PIN(MX51_PAD_GPIO1_3),
1273 IMX_PINCTRL_PIN(MX51_PAD_PMIC_INT_REQ),
1274 IMX_PINCTRL_PIN(MX51_PAD_GPIO1_4),
1275 IMX_PINCTRL_PIN(MX51_PAD_GPIO1_5),
1276 IMX_PINCTRL_PIN(MX51_PAD_GPIO1_6),
1277 IMX_PINCTRL_PIN(MX51_PAD_GPIO1_7),
1278 IMX_PINCTRL_PIN(MX51_PAD_GPIO1_8),
1279 IMX_PINCTRL_PIN(MX51_PAD_GPIO1_9),
1280};
1281
1282static struct imx_pinctrl_soc_info imx51_pinctrl_info = {
1283 .pins = imx51_pinctrl_pads,
1284 .npins = ARRAY_SIZE(imx51_pinctrl_pads),
1285 .pin_regs = imx51_pin_regs,
1286 .npin_regs = ARRAY_SIZE(imx51_pin_regs),
1287};
1288
1289static struct of_device_id imx51_pinctrl_of_match[] __devinitdata = {
1290 { .compatible = "fsl,imx51-iomuxc", },
1291 { /* sentinel */ }
1292};
1293
1294static int __devinit imx51_pinctrl_probe(struct platform_device *pdev)
1295{
1296 return imx_pinctrl_probe(pdev, &imx51_pinctrl_info);
1297}
1298
1299static struct platform_driver imx51_pinctrl_driver = {
1300 .driver = {
1301 .name = "imx51-pinctrl",
1302 .owner = THIS_MODULE,
1303 .of_match_table = of_match_ptr(imx51_pinctrl_of_match),
1304 },
1305 .probe = imx51_pinctrl_probe,
1306 .remove = __devexit_p(imx_pinctrl_remove),
1307};
1308
1309static int __init imx51_pinctrl_init(void)
1310{
1311 return platform_driver_register(&imx51_pinctrl_driver);
1312}
1313arch_initcall(imx51_pinctrl_init);
1314
1315static void __exit imx51_pinctrl_exit(void)
1316{
1317 platform_driver_unregister(&imx51_pinctrl_driver);
1318}
1319module_exit(imx51_pinctrl_exit);
1320MODULE_AUTHOR("Dong Aisheng <dong.aisheng@linaro.org>");
1321MODULE_DESCRIPTION("Freescale IMX51 pinctrl driver");
1322MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-imx53.c b/drivers/pinctrl/pinctrl-imx53.c
new file mode 100644
index 00000000000..1f49e16a9bc
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx53.c
@@ -0,0 +1,1649 @@
1/*
2 * imx53 pinctrl driver based on imx pinmux core
3 *
4 * Copyright (C) 2012 Freescale Semiconductor, Inc.
5 * Copyright (C) 2012 Linaro, Inc.
6 *
7 * Author: Dong Aisheng <dong.aisheng@linaro.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#include <linux/err.h>
16#include <linux/init.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/pinctrl/pinctrl.h>
22
23#include "pinctrl-imx.h"
24
25enum imx53_pads {
26 MX53_PAD_GPIO_19 = 1,
27 MX53_PAD_KEY_COL0 = 2,
28 MX53_PAD_KEY_ROW0 = 3,
29 MX53_PAD_KEY_COL1 = 4,
30 MX53_PAD_KEY_ROW1 = 5,
31 MX53_PAD_KEY_COL2 = 6,
32 MX53_PAD_KEY_ROW2 = 7,
33 MX53_PAD_KEY_COL3 = 8,
34 MX53_PAD_KEY_ROW3 = 9,
35 MX53_PAD_KEY_COL4 = 10,
36 MX53_PAD_KEY_ROW4 = 11,
37 MX53_PAD_DI0_DISP_CLK = 12,
38 MX53_PAD_DI0_PIN15 = 13,
39 MX53_PAD_DI0_PIN2 = 14,
40 MX53_PAD_DI0_PIN3 = 15,
41 MX53_PAD_DI0_PIN4 = 16,
42 MX53_PAD_DISP0_DAT0 = 17,
43 MX53_PAD_DISP0_DAT1 = 18,
44 MX53_PAD_DISP0_DAT2 = 19,
45 MX53_PAD_DISP0_DAT3 = 20,
46 MX53_PAD_DISP0_DAT4 = 21,
47 MX53_PAD_DISP0_DAT5 = 22,
48 MX53_PAD_DISP0_DAT6 = 23,
49 MX53_PAD_DISP0_DAT7 = 24,
50 MX53_PAD_DISP0_DAT8 = 25,
51 MX53_PAD_DISP0_DAT9 = 26,
52 MX53_PAD_DISP0_DAT10 = 27,
53 MX53_PAD_DISP0_DAT11 = 28,
54 MX53_PAD_DISP0_DAT12 = 29,
55 MX53_PAD_DISP0_DAT13 = 30,
56 MX53_PAD_DISP0_DAT14 = 31,
57 MX53_PAD_DISP0_DAT15 = 32,
58 MX53_PAD_DISP0_DAT16 = 33,
59 MX53_PAD_DISP0_DAT17 = 34,
60 MX53_PAD_DISP0_DAT18 = 35,
61 MX53_PAD_DISP0_DAT19 = 36,
62 MX53_PAD_DISP0_DAT20 = 37,
63 MX53_PAD_DISP0_DAT21 = 38,
64 MX53_PAD_DISP0_DAT22 = 39,
65 MX53_PAD_DISP0_DAT23 = 40,
66 MX53_PAD_CSI0_PIXCLK = 41,
67 MX53_PAD_CSI0_MCLK = 42,
68 MX53_PAD_CSI0_DATA_EN = 43,
69 MX53_PAD_CSI0_VSYNC = 44,
70 MX53_PAD_CSI0_DAT4 = 45,
71 MX53_PAD_CSI0_DAT5 = 46,
72 MX53_PAD_CSI0_DAT6 = 47,
73 MX53_PAD_CSI0_DAT7 = 48,
74 MX53_PAD_CSI0_DAT8 = 49,
75 MX53_PAD_CSI0_DAT9 = 50,
76 MX53_PAD_CSI0_DAT10 = 51,
77 MX53_PAD_CSI0_DAT11 = 52,
78 MX53_PAD_CSI0_DAT12 = 53,
79 MX53_PAD_CSI0_DAT13 = 54,
80 MX53_PAD_CSI0_DAT14 = 55,
81 MX53_PAD_CSI0_DAT15 = 56,
82 MX53_PAD_CSI0_DAT16 = 57,
83 MX53_PAD_CSI0_DAT17 = 58,
84 MX53_PAD_CSI0_DAT18 = 59,
85 MX53_PAD_CSI0_DAT19 = 60,
86 MX53_PAD_EIM_A25 = 61,
87 MX53_PAD_EIM_EB2 = 62,
88 MX53_PAD_EIM_D16 = 63,
89 MX53_PAD_EIM_D17 = 64,
90 MX53_PAD_EIM_D18 = 65,
91 MX53_PAD_EIM_D19 = 66,
92 MX53_PAD_EIM_D20 = 67,
93 MX53_PAD_EIM_D21 = 68,
94 MX53_PAD_EIM_D22 = 69,
95 MX53_PAD_EIM_D23 = 70,
96 MX53_PAD_EIM_EB3 = 71,
97 MX53_PAD_EIM_D24 = 72,
98 MX53_PAD_EIM_D25 = 73,
99 MX53_PAD_EIM_D26 = 74,
100 MX53_PAD_EIM_D27 = 75,
101 MX53_PAD_EIM_D28 = 76,
102 MX53_PAD_EIM_D29 = 77,
103 MX53_PAD_EIM_D30 = 78,
104 MX53_PAD_EIM_D31 = 79,
105 MX53_PAD_EIM_A24 = 80,
106 MX53_PAD_EIM_A23 = 81,
107 MX53_PAD_EIM_A22 = 82,
108 MX53_PAD_EIM_A21 = 83,
109 MX53_PAD_EIM_A20 = 84,
110 MX53_PAD_EIM_A19 = 85,
111 MX53_PAD_EIM_A18 = 86,
112 MX53_PAD_EIM_A17 = 87,
113 MX53_PAD_EIM_A16 = 88,
114 MX53_PAD_EIM_CS0 = 89,
115 MX53_PAD_EIM_CS1 = 90,
116 MX53_PAD_EIM_OE = 91,
117 MX53_PAD_EIM_RW = 92,
118 MX53_PAD_EIM_LBA = 93,
119 MX53_PAD_EIM_EB0 = 94,
120 MX53_PAD_EIM_EB1 = 95,
121 MX53_PAD_EIM_DA0 = 96,
122 MX53_PAD_EIM_DA1 = 97,
123 MX53_PAD_EIM_DA2 = 98,
124 MX53_PAD_EIM_DA3 = 99,
125 MX53_PAD_EIM_DA4 = 100,
126 MX53_PAD_EIM_DA5 = 101,
127 MX53_PAD_EIM_DA6 = 102,
128 MX53_PAD_EIM_DA7 = 103,
129 MX53_PAD_EIM_DA8 = 104,
130 MX53_PAD_EIM_DA9 = 105,
131 MX53_PAD_EIM_DA10 = 106,
132 MX53_PAD_EIM_DA11 = 107,
133 MX53_PAD_EIM_DA12 = 108,
134 MX53_PAD_EIM_DA13 = 109,
135 MX53_PAD_EIM_DA14 = 110,
136 MX53_PAD_EIM_DA15 = 111,
137 MX53_PAD_NANDF_WE_B = 112,
138 MX53_PAD_NANDF_RE_B = 113,
139 MX53_PAD_EIM_WAIT = 114,
140 MX53_PAD_LVDS1_TX3_P = 115,
141 MX53_PAD_LVDS1_TX2_P = 116,
142 MX53_PAD_LVDS1_CLK_P = 117,
143 MX53_PAD_LVDS1_TX1_P = 118,
144 MX53_PAD_LVDS1_TX0_P = 119,
145 MX53_PAD_LVDS0_TX3_P = 120,
146 MX53_PAD_LVDS0_CLK_P = 121,
147 MX53_PAD_LVDS0_TX2_P = 122,
148 MX53_PAD_LVDS0_TX1_P = 123,
149 MX53_PAD_LVDS0_TX0_P = 124,
150 MX53_PAD_GPIO_10 = 125,
151 MX53_PAD_GPIO_11 = 126,
152 MX53_PAD_GPIO_12 = 127,
153 MX53_PAD_GPIO_13 = 128,
154 MX53_PAD_GPIO_14 = 129,
155 MX53_PAD_NANDF_CLE = 130,
156 MX53_PAD_NANDF_ALE = 131,
157 MX53_PAD_NANDF_WP_B = 132,
158 MX53_PAD_NANDF_RB0 = 133,
159 MX53_PAD_NANDF_CS0 = 134,
160 MX53_PAD_NANDF_CS1 = 135,
161 MX53_PAD_NANDF_CS2 = 136,
162 MX53_PAD_NANDF_CS3 = 137,
163 MX53_PAD_FEC_MDIO = 138,
164 MX53_PAD_FEC_REF_CLK = 139,
165 MX53_PAD_FEC_RX_ER = 140,
166 MX53_PAD_FEC_CRS_DV = 141,
167 MX53_PAD_FEC_RXD1 = 142,
168 MX53_PAD_FEC_RXD0 = 143,
169 MX53_PAD_FEC_TX_EN = 144,
170 MX53_PAD_FEC_TXD1 = 145,
171 MX53_PAD_FEC_TXD0 = 146,
172 MX53_PAD_FEC_MDC = 147,
173 MX53_PAD_PATA_DIOW = 148,
174 MX53_PAD_PATA_DMACK = 149,
175 MX53_PAD_PATA_DMARQ = 150,
176 MX53_PAD_PATA_BUFFER_EN = 151,
177 MX53_PAD_PATA_INTRQ = 152,
178 MX53_PAD_PATA_DIOR = 153,
179 MX53_PAD_PATA_RESET_B = 154,
180 MX53_PAD_PATA_IORDY = 155,
181 MX53_PAD_PATA_DA_0 = 156,
182 MX53_PAD_PATA_DA_1 = 157,
183 MX53_PAD_PATA_DA_2 = 158,
184 MX53_PAD_PATA_CS_0 = 159,
185 MX53_PAD_PATA_CS_1 = 160,
186 MX53_PAD_PATA_DATA0 = 161,
187 MX53_PAD_PATA_DATA1 = 162,
188 MX53_PAD_PATA_DATA2 = 163,
189 MX53_PAD_PATA_DATA3 = 164,
190 MX53_PAD_PATA_DATA4 = 165,
191 MX53_PAD_PATA_DATA5 = 166,
192 MX53_PAD_PATA_DATA6 = 167,
193 MX53_PAD_PATA_DATA7 = 168,
194 MX53_PAD_PATA_DATA8 = 169,
195 MX53_PAD_PATA_DATA9 = 170,
196 MX53_PAD_PATA_DATA10 = 171,
197 MX53_PAD_PATA_DATA11 = 172,
198 MX53_PAD_PATA_DATA12 = 173,
199 MX53_PAD_PATA_DATA13 = 174,
200 MX53_PAD_PATA_DATA14 = 175,
201 MX53_PAD_PATA_DATA15 = 176,
202 MX53_PAD_SD1_DATA0 = 177,
203 MX53_PAD_SD1_DATA1 = 178,
204 MX53_PAD_SD1_CMD = 179,
205 MX53_PAD_SD1_DATA2 = 180,
206 MX53_PAD_SD1_CLK = 181,
207 MX53_PAD_SD1_DATA3 = 182,
208 MX53_PAD_SD2_CLK = 183,
209 MX53_PAD_SD2_CMD = 184,
210 MX53_PAD_SD2_DATA3 = 185,
211 MX53_PAD_SD2_DATA2 = 186,
212 MX53_PAD_SD2_DATA1 = 187,
213 MX53_PAD_SD2_DATA0 = 188,
214 MX53_PAD_GPIO_0 = 189,
215 MX53_PAD_GPIO_1 = 190,
216 MX53_PAD_GPIO_9 = 191,
217 MX53_PAD_GPIO_3 = 192,
218 MX53_PAD_GPIO_6 = 193,
219 MX53_PAD_GPIO_2 = 194,
220 MX53_PAD_GPIO_4 = 195,
221 MX53_PAD_GPIO_5 = 196,
222 MX53_PAD_GPIO_7 = 197,
223 MX53_PAD_GPIO_8 = 198,
224 MX53_PAD_GPIO_16 = 199,
225 MX53_PAD_GPIO_17 = 200,
226 MX53_PAD_GPIO_18 = 201,
227};
228
229/* imx53 register maps */
230static struct imx_pin_reg imx53_pin_regs[] = {
231 IMX_PIN_REG(MX53_PAD_GPIO_19, 0x348, 0x020, 0, 0x840, 0), /* MX53_PAD_GPIO_19__KPP_COL_5 */
232 IMX_PIN_REG(MX53_PAD_GPIO_19, 0x348, 0x020, 1, 0x000, 0), /* MX53_PAD_GPIO_19__GPIO4_5 */
233 IMX_PIN_REG(MX53_PAD_GPIO_19, 0x348, 0x020, 2, 0x000, 0), /* MX53_PAD_GPIO_19__CCM_CLKO */
234 IMX_PIN_REG(MX53_PAD_GPIO_19, 0x348, 0x020, 3, 0x000, 0), /* MX53_PAD_GPIO_19__SPDIF_OUT1 */
235 IMX_PIN_REG(MX53_PAD_GPIO_19, 0x348, 0x020, 4, 0x000, 0), /* MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 */
236 IMX_PIN_REG(MX53_PAD_GPIO_19, 0x348, 0x020, 5, 0x000, 0), /* MX53_PAD_GPIO_19__ECSPI1_RDY */
237 IMX_PIN_REG(MX53_PAD_GPIO_19, 0x348, 0x020, 6, 0x000, 0), /* MX53_PAD_GPIO_19__FEC_TDATA_3 */
238 IMX_PIN_REG(MX53_PAD_GPIO_19, 0x348, 0x020, 7, 0x000, 0), /* MX53_PAD_GPIO_19__SRC_INT_BOOT */
239 IMX_PIN_REG(MX53_PAD_KEY_COL0, 0x34C, 0x024, 0, 0x000, 0), /* MX53_PAD_KEY_COL0__KPP_COL_0 */
240 IMX_PIN_REG(MX53_PAD_KEY_COL0, 0x34C, 0x024, 1, 0x000, 0), /* MX53_PAD_KEY_COL0__GPIO4_6 */
241 IMX_PIN_REG(MX53_PAD_KEY_COL0, 0x34C, 0x024, 2, 0x758, 0), /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */
242 IMX_PIN_REG(MX53_PAD_KEY_COL0, 0x34C, 0x024, 4, 0x000, 0), /* MX53_PAD_KEY_COL0__UART4_TXD_MUX */
243 IMX_PIN_REG(MX53_PAD_KEY_COL0, 0x34C, 0x024, 5, 0x79C, 0), /* MX53_PAD_KEY_COL0__ECSPI1_SCLK */
244 IMX_PIN_REG(MX53_PAD_KEY_COL0, 0x34C, 0x024, 6, 0x000, 0), /* MX53_PAD_KEY_COL0__FEC_RDATA_3 */
245 IMX_PIN_REG(MX53_PAD_KEY_COL0, 0x34C, 0x024, 7, 0x000, 0), /* MX53_PAD_KEY_COL0__SRC_ANY_PU_RST */
246 IMX_PIN_REG(MX53_PAD_KEY_ROW0, 0x350, 0x028, 0, 0x000, 0), /* MX53_PAD_KEY_ROW0__KPP_ROW_0 */
247 IMX_PIN_REG(MX53_PAD_KEY_ROW0, 0x350, 0x028, 1, 0x000, 0), /* MX53_PAD_KEY_ROW0__GPIO4_7 */
248 IMX_PIN_REG(MX53_PAD_KEY_ROW0, 0x350, 0x028, 2, 0x74C, 0), /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */
249 IMX_PIN_REG(MX53_PAD_KEY_ROW0, 0x350, 0x028, 4, 0x890, 1), /* MX53_PAD_KEY_ROW0__UART4_RXD_MUX */
250 IMX_PIN_REG(MX53_PAD_KEY_ROW0, 0x350, 0x028, 5, 0x7A4, 0), /* MX53_PAD_KEY_ROW0__ECSPI1_MOSI */
251 IMX_PIN_REG(MX53_PAD_KEY_ROW0, 0x350, 0x028, 6, 0x000, 0), /* MX53_PAD_KEY_ROW0__FEC_TX_ER */
252 IMX_PIN_REG(MX53_PAD_KEY_COL1, 0x354, 0x02C, 0, 0x000, 0), /* MX53_PAD_KEY_COL1__KPP_COL_1 */
253 IMX_PIN_REG(MX53_PAD_KEY_COL1, 0x354, 0x02C, 1, 0x000, 0), /* MX53_PAD_KEY_COL1__GPIO4_8 */
254 IMX_PIN_REG(MX53_PAD_KEY_COL1, 0x354, 0x02C, 2, 0x75C, 0), /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */
255 IMX_PIN_REG(MX53_PAD_KEY_COL1, 0x354, 0x02C, 4, 0x000, 0), /* MX53_PAD_KEY_COL1__UART5_TXD_MUX */
256 IMX_PIN_REG(MX53_PAD_KEY_COL1, 0x354, 0x02C, 5, 0x7A0, 0), /* MX53_PAD_KEY_COL1__ECSPI1_MISO */
257 IMX_PIN_REG(MX53_PAD_KEY_COL1, 0x354, 0x02C, 6, 0x808, 0), /* MX53_PAD_KEY_COL1__FEC_RX_CLK */
258 IMX_PIN_REG(MX53_PAD_KEY_COL1, 0x354, 0x02C, 7, 0x000, 0), /* MX53_PAD_KEY_COL1__USBPHY1_TXREADY */
259 IMX_PIN_REG(MX53_PAD_KEY_ROW1, 0x358, 0x030, 0, 0x000, 0), /* MX53_PAD_KEY_ROW1__KPP_ROW_1 */
260 IMX_PIN_REG(MX53_PAD_KEY_ROW1, 0x358, 0x030, 1, 0x000, 0), /* MX53_PAD_KEY_ROW1__GPIO4_9 */
261 IMX_PIN_REG(MX53_PAD_KEY_ROW1, 0x358, 0x030, 2, 0x748, 0), /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */
262 IMX_PIN_REG(MX53_PAD_KEY_ROW1, 0x358, 0x030, 4, 0x898, 1), /* MX53_PAD_KEY_ROW1__UART5_RXD_MUX */
263 IMX_PIN_REG(MX53_PAD_KEY_ROW1, 0x358, 0x030, 5, 0x7A8, 0), /* MX53_PAD_KEY_ROW1__ECSPI1_SS0 */
264 IMX_PIN_REG(MX53_PAD_KEY_ROW1, 0x358, 0x030, 6, 0x800, 0), /* MX53_PAD_KEY_ROW1__FEC_COL */
265 IMX_PIN_REG(MX53_PAD_KEY_ROW1, 0x358, 0x030, 7, 0x000, 0), /* MX53_PAD_KEY_ROW1__USBPHY1_RXVALID */
266 IMX_PIN_REG(MX53_PAD_KEY_COL2, 0x35C, 0x034, 0, 0x000, 0), /* MX53_PAD_KEY_COL2__KPP_COL_2 */
267 IMX_PIN_REG(MX53_PAD_KEY_COL2, 0x35C, 0x034, 1, 0x000, 0), /* MX53_PAD_KEY_COL2__GPIO4_10 */
268 IMX_PIN_REG(MX53_PAD_KEY_COL2, 0x35C, 0x034, 2, 0x000, 0), /* MX53_PAD_KEY_COL2__CAN1_TXCAN */
269 IMX_PIN_REG(MX53_PAD_KEY_COL2, 0x35C, 0x034, 4, 0x804, 0), /* MX53_PAD_KEY_COL2__FEC_MDIO */
270 IMX_PIN_REG(MX53_PAD_KEY_COL2, 0x35C, 0x034, 5, 0x7AC, 0), /* MX53_PAD_KEY_COL2__ECSPI1_SS1 */
271 IMX_PIN_REG(MX53_PAD_KEY_COL2, 0x35C, 0x034, 6, 0x000, 0), /* MX53_PAD_KEY_COL2__FEC_RDATA_2 */
272 IMX_PIN_REG(MX53_PAD_KEY_COL2, 0x35C, 0x034, 7, 0x000, 0), /* MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE */
273 IMX_PIN_REG(MX53_PAD_KEY_ROW2, 0x360, 0x038, 0, 0x000, 0), /* MX53_PAD_KEY_ROW2__KPP_ROW_2 */
274 IMX_PIN_REG(MX53_PAD_KEY_ROW2, 0x360, 0x038, 1, 0x000, 0), /* MX53_PAD_KEY_ROW2__GPIO4_11 */
275 IMX_PIN_REG(MX53_PAD_KEY_ROW2, 0x360, 0x038, 2, 0x760, 0), /* MX53_PAD_KEY_ROW2__CAN1_RXCAN */
276 IMX_PIN_REG(MX53_PAD_KEY_ROW2, 0x360, 0x038, 4, 0x000, 0), /* MX53_PAD_KEY_ROW2__FEC_MDC */
277 IMX_PIN_REG(MX53_PAD_KEY_ROW2, 0x360, 0x038, 5, 0x7B0, 0), /* MX53_PAD_KEY_ROW2__ECSPI1_SS2 */
278 IMX_PIN_REG(MX53_PAD_KEY_ROW2, 0x360, 0x038, 6, 0x000, 0), /* MX53_PAD_KEY_ROW2__FEC_TDATA_2 */
279 IMX_PIN_REG(MX53_PAD_KEY_ROW2, 0x360, 0x038, 7, 0x000, 0), /* MX53_PAD_KEY_ROW2__USBPHY1_RXERROR */
280 IMX_PIN_REG(MX53_PAD_KEY_COL3, 0x364, 0x03C, 0, 0x000, 0), /* MX53_PAD_KEY_COL3__KPP_COL_3 */
281 IMX_PIN_REG(MX53_PAD_KEY_COL3, 0x364, 0x03C, 1, 0x000, 0), /* MX53_PAD_KEY_COL3__GPIO4_12 */
282 IMX_PIN_REG(MX53_PAD_KEY_COL3, 0x364, 0x03C, 2, 0x000, 0), /* MX53_PAD_KEY_COL3__USBOH3_H2_DP */
283 IMX_PIN_REG(MX53_PAD_KEY_COL3, 0x364, 0x03C, 3, 0x870, 0), /* MX53_PAD_KEY_COL3__SPDIF_IN1 */
284 IMX_PIN_REG(MX53_PAD_KEY_COL3, 0x364, 0x03C, 4, 0x81C, 0), /* MX53_PAD_KEY_COL3__I2C2_SCL */
285 IMX_PIN_REG(MX53_PAD_KEY_COL3, 0x364, 0x03C, 5, 0x7B4, 0), /* MX53_PAD_KEY_COL3__ECSPI1_SS3 */
286 IMX_PIN_REG(MX53_PAD_KEY_COL3, 0x364, 0x03C, 6, 0x000, 0), /* MX53_PAD_KEY_COL3__FEC_CRS */
287 IMX_PIN_REG(MX53_PAD_KEY_COL3, 0x364, 0x03C, 7, 0x000, 0), /* MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK */
288 IMX_PIN_REG(MX53_PAD_KEY_ROW3, 0x368, 0x040, 0, 0x000, 0), /* MX53_PAD_KEY_ROW3__KPP_ROW_3 */
289 IMX_PIN_REG(MX53_PAD_KEY_ROW3, 0x368, 0x040, 1, 0x000, 0), /* MX53_PAD_KEY_ROW3__GPIO4_13 */
290 IMX_PIN_REG(MX53_PAD_KEY_ROW3, 0x368, 0x040, 2, 0x000, 0), /* MX53_PAD_KEY_ROW3__USBOH3_H2_DM */
291 IMX_PIN_REG(MX53_PAD_KEY_ROW3, 0x368, 0x040, 3, 0x768, 0), /* MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK */
292 IMX_PIN_REG(MX53_PAD_KEY_ROW3, 0x368, 0x040, 4, 0x820, 0), /* MX53_PAD_KEY_ROW3__I2C2_SDA */
293 IMX_PIN_REG(MX53_PAD_KEY_ROW3, 0x368, 0x040, 5, 0x000, 0), /* MX53_PAD_KEY_ROW3__OSC32K_32K_OUT */
294 IMX_PIN_REG(MX53_PAD_KEY_ROW3, 0x368, 0x040, 6, 0x77C, 0), /* MX53_PAD_KEY_ROW3__CCM_PLL4_BYP */
295 IMX_PIN_REG(MX53_PAD_KEY_ROW3, 0x368, 0x040, 7, 0x000, 0), /* MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 */
296 IMX_PIN_REG(MX53_PAD_KEY_COL4, 0x36C, 0x044, 0, 0x000, 0), /* MX53_PAD_KEY_COL4__KPP_COL_4 */
297 IMX_PIN_REG(MX53_PAD_KEY_COL4, 0x36C, 0x044, 1, 0x000, 0), /* MX53_PAD_KEY_COL4__GPIO4_14 */
298 IMX_PIN_REG(MX53_PAD_KEY_COL4, 0x36C, 0x044, 2, 0x000, 0), /* MX53_PAD_KEY_COL4__CAN2_TXCAN */
299 IMX_PIN_REG(MX53_PAD_KEY_COL4, 0x36C, 0x044, 3, 0x000, 0), /* MX53_PAD_KEY_COL4__IPU_SISG_4 */
300 IMX_PIN_REG(MX53_PAD_KEY_COL4, 0x36C, 0x044, 4, 0x894, 0), /* MX53_PAD_KEY_COL4__UART5_RTS */
301 IMX_PIN_REG(MX53_PAD_KEY_COL4, 0x36C, 0x044, 5, 0x89C, 0), /* MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC */
302 IMX_PIN_REG(MX53_PAD_KEY_COL4, 0x36C, 0x044, 7, 0x000, 0), /* MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 */
303 IMX_PIN_REG(MX53_PAD_KEY_ROW4, 0x370, 0x048, 0, 0x000, 0), /* MX53_PAD_KEY_ROW4__KPP_ROW_4 */
304 IMX_PIN_REG(MX53_PAD_KEY_ROW4, 0x370, 0x048, 1, 0x000, 0), /* MX53_PAD_KEY_ROW4__GPIO4_15 */
305 IMX_PIN_REG(MX53_PAD_KEY_ROW4, 0x370, 0x048, 2, 0x764, 0), /* MX53_PAD_KEY_ROW4__CAN2_RXCAN */
306 IMX_PIN_REG(MX53_PAD_KEY_ROW4, 0x370, 0x048, 3, 0x000, 0), /* MX53_PAD_KEY_ROW4__IPU_SISG_5 */
307 IMX_PIN_REG(MX53_PAD_KEY_ROW4, 0x370, 0x048, 4, 0x000, 0), /* MX53_PAD_KEY_ROW4__UART5_CTS */
308 IMX_PIN_REG(MX53_PAD_KEY_ROW4, 0x370, 0x048, 5, 0x000, 0), /* MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR */
309 IMX_PIN_REG(MX53_PAD_KEY_ROW4, 0x370, 0x048, 7, 0x000, 0), /* MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID */
310 IMX_PIN_REG(MX53_PAD_DI0_DISP_CLK, 0x378, 0x04C, 0, 0x000, 0), /* MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK */
311 IMX_PIN_REG(MX53_PAD_DI0_DISP_CLK, 0x378, 0x04C, 1, 0x000, 0), /* MX53_PAD_DI0_DISP_CLK__GPIO4_16 */
312 IMX_PIN_REG(MX53_PAD_DI0_DISP_CLK, 0x378, 0x04C, 2, 0x000, 0), /* MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR */
313 IMX_PIN_REG(MX53_PAD_DI0_DISP_CLK, 0x378, 0x04C, 5, 0x000, 0), /* MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 */
314 IMX_PIN_REG(MX53_PAD_DI0_DISP_CLK, 0x378, 0x04C, 6, 0x000, 0), /* MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 */
315 IMX_PIN_REG(MX53_PAD_DI0_DISP_CLK, 0x378, 0x04C, 7, 0x000, 0), /* MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID */
316 IMX_PIN_REG(MX53_PAD_DI0_PIN15, 0x37C, 0x050, 0, 0x000, 0), /* MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 */
317 IMX_PIN_REG(MX53_PAD_DI0_PIN15, 0x37C, 0x050, 1, 0x000, 0), /* MX53_PAD_DI0_PIN15__GPIO4_17 */
318 IMX_PIN_REG(MX53_PAD_DI0_PIN15, 0x37C, 0x050, 2, 0x000, 0), /* MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC */
319 IMX_PIN_REG(MX53_PAD_DI0_PIN15, 0x37C, 0x050, 5, 0x000, 0), /* MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 */
320 IMX_PIN_REG(MX53_PAD_DI0_PIN15, 0x37C, 0x050, 6, 0x000, 0), /* MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 */
321 IMX_PIN_REG(MX53_PAD_DI0_PIN15, 0x37C, 0x050, 7, 0x000, 0), /* MX53_PAD_DI0_PIN15__USBPHY1_BVALID */
322 IMX_PIN_REG(MX53_PAD_DI0_PIN2, 0x380, 0x054, 0, 0x000, 0), /* MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 */
323 IMX_PIN_REG(MX53_PAD_DI0_PIN2, 0x380, 0x054, 1, 0x000, 0), /* MX53_PAD_DI0_PIN2__GPIO4_18 */
324 IMX_PIN_REG(MX53_PAD_DI0_PIN2, 0x380, 0x054, 2, 0x000, 0), /* MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD */
325 IMX_PIN_REG(MX53_PAD_DI0_PIN2, 0x380, 0x054, 5, 0x000, 0), /* MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 */
326 IMX_PIN_REG(MX53_PAD_DI0_PIN2, 0x380, 0x054, 6, 0x000, 0), /* MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 */
327 IMX_PIN_REG(MX53_PAD_DI0_PIN2, 0x380, 0x054, 7, 0x000, 0), /* MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION */
328 IMX_PIN_REG(MX53_PAD_DI0_PIN3, 0x384, 0x058, 0, 0x000, 0), /* MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 */
329 IMX_PIN_REG(MX53_PAD_DI0_PIN3, 0x384, 0x058, 1, 0x000, 0), /* MX53_PAD_DI0_PIN3__GPIO4_19 */
330 IMX_PIN_REG(MX53_PAD_DI0_PIN3, 0x384, 0x058, 2, 0x000, 0), /* MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS */
331 IMX_PIN_REG(MX53_PAD_DI0_PIN3, 0x384, 0x058, 5, 0x000, 0), /* MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 */
332 IMX_PIN_REG(MX53_PAD_DI0_PIN3, 0x384, 0x058, 6, 0x000, 0), /* MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 */
333 IMX_PIN_REG(MX53_PAD_DI0_PIN3, 0x384, 0x058, 7, 0x000, 0), /* MX53_PAD_DI0_PIN3__USBPHY1_IDDIG */
334 IMX_PIN_REG(MX53_PAD_DI0_PIN4, 0x388, 0x05C, 0, 0x000, 0), /* MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 */
335 IMX_PIN_REG(MX53_PAD_DI0_PIN4, 0x388, 0x05C, 1, 0x000, 0), /* MX53_PAD_DI0_PIN4__GPIO4_20 */
336 IMX_PIN_REG(MX53_PAD_DI0_PIN4, 0x388, 0x05C, 2, 0x000, 0), /* MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD */
337 IMX_PIN_REG(MX53_PAD_DI0_PIN4, 0x388, 0x05C, 3, 0x7FC, 0), /* MX53_PAD_DI0_PIN4__ESDHC1_WP */
338 IMX_PIN_REG(MX53_PAD_DI0_PIN4, 0x388, 0x05C, 5, 0x000, 0), /* MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD */
339 IMX_PIN_REG(MX53_PAD_DI0_PIN4, 0x388, 0x05C, 6, 0x000, 0), /* MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 */
340 IMX_PIN_REG(MX53_PAD_DI0_PIN4, 0x388, 0x05C, 7, 0x000, 0), /* MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT */
341 IMX_PIN_REG(MX53_PAD_DISP0_DAT0, 0x38C, 0x060, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 */
342 IMX_PIN_REG(MX53_PAD_DISP0_DAT0, 0x38C, 0x060, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT0__GPIO4_21 */
343 IMX_PIN_REG(MX53_PAD_DISP0_DAT0, 0x38C, 0x060, 2, 0x780, 0), /* MX53_PAD_DISP0_DAT0__CSPI_SCLK */
344 IMX_PIN_REG(MX53_PAD_DISP0_DAT0, 0x38C, 0x060, 3, 0x000, 0), /* MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 */
345 IMX_PIN_REG(MX53_PAD_DISP0_DAT0, 0x38C, 0x060, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN */
346 IMX_PIN_REG(MX53_PAD_DISP0_DAT0, 0x38C, 0x060, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 */
347 IMX_PIN_REG(MX53_PAD_DISP0_DAT0, 0x38C, 0x060, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY */
348 IMX_PIN_REG(MX53_PAD_DISP0_DAT1, 0x390, 0x064, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 */
349 IMX_PIN_REG(MX53_PAD_DISP0_DAT1, 0x390, 0x064, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT1__GPIO4_22 */
350 IMX_PIN_REG(MX53_PAD_DISP0_DAT1, 0x390, 0x064, 2, 0x788, 0), /* MX53_PAD_DISP0_DAT1__CSPI_MOSI */
351 IMX_PIN_REG(MX53_PAD_DISP0_DAT1, 0x390, 0x064, 3, 0x000, 0), /* MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 */
352 IMX_PIN_REG(MX53_PAD_DISP0_DAT1, 0x390, 0x064, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL */
353 IMX_PIN_REG(MX53_PAD_DISP0_DAT1, 0x390, 0x064, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 */
354 IMX_PIN_REG(MX53_PAD_DISP0_DAT1, 0x390, 0x064, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID */
355 IMX_PIN_REG(MX53_PAD_DISP0_DAT2, 0x394, 0x068, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 */
356 IMX_PIN_REG(MX53_PAD_DISP0_DAT2, 0x394, 0x068, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT2__GPIO4_23 */
357 IMX_PIN_REG(MX53_PAD_DISP0_DAT2, 0x394, 0x068, 2, 0x784, 0), /* MX53_PAD_DISP0_DAT2__CSPI_MISO */
358 IMX_PIN_REG(MX53_PAD_DISP0_DAT2, 0x394, 0x068, 3, 0x000, 0), /* MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 */
359 IMX_PIN_REG(MX53_PAD_DISP0_DAT2, 0x394, 0x068, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE */
360 IMX_PIN_REG(MX53_PAD_DISP0_DAT2, 0x394, 0x068, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 */
361 IMX_PIN_REG(MX53_PAD_DISP0_DAT2, 0x394, 0x068, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE */
362 IMX_PIN_REG(MX53_PAD_DISP0_DAT3, 0x398, 0x06C, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 */
363 IMX_PIN_REG(MX53_PAD_DISP0_DAT3, 0x398, 0x06C, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT3__GPIO4_24 */
364 IMX_PIN_REG(MX53_PAD_DISP0_DAT3, 0x398, 0x06C, 2, 0x78C, 0), /* MX53_PAD_DISP0_DAT3__CSPI_SS0 */
365 IMX_PIN_REG(MX53_PAD_DISP0_DAT3, 0x398, 0x06C, 3, 0x000, 0), /* MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 */
366 IMX_PIN_REG(MX53_PAD_DISP0_DAT3, 0x398, 0x06C, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR */
367 IMX_PIN_REG(MX53_PAD_DISP0_DAT3, 0x398, 0x06C, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 */
368 IMX_PIN_REG(MX53_PAD_DISP0_DAT3, 0x398, 0x06C, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR */
369 IMX_PIN_REG(MX53_PAD_DISP0_DAT4, 0x39C, 0x070, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 */
370 IMX_PIN_REG(MX53_PAD_DISP0_DAT4, 0x39C, 0x070, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT4__GPIO4_25 */
371 IMX_PIN_REG(MX53_PAD_DISP0_DAT4, 0x39C, 0x070, 2, 0x790, 0), /* MX53_PAD_DISP0_DAT4__CSPI_SS1 */
372 IMX_PIN_REG(MX53_PAD_DISP0_DAT4, 0x39C, 0x070, 3, 0x000, 0), /* MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 */
373 IMX_PIN_REG(MX53_PAD_DISP0_DAT4, 0x39C, 0x070, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB */
374 IMX_PIN_REG(MX53_PAD_DISP0_DAT4, 0x39C, 0x070, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 */
375 IMX_PIN_REG(MX53_PAD_DISP0_DAT4, 0x39C, 0x070, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK */
376 IMX_PIN_REG(MX53_PAD_DISP0_DAT5, 0x3A0, 0x074, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 */
377 IMX_PIN_REG(MX53_PAD_DISP0_DAT5, 0x3A0, 0x074, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT5__GPIO4_26 */
378 IMX_PIN_REG(MX53_PAD_DISP0_DAT5, 0x3A0, 0x074, 2, 0x794, 0), /* MX53_PAD_DISP0_DAT5__CSPI_SS2 */
379 IMX_PIN_REG(MX53_PAD_DISP0_DAT5, 0x3A0, 0x074, 3, 0x000, 0), /* MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 */
380 IMX_PIN_REG(MX53_PAD_DISP0_DAT5, 0x3A0, 0x074, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS */
381 IMX_PIN_REG(MX53_PAD_DISP0_DAT5, 0x3A0, 0x074, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 */
382 IMX_PIN_REG(MX53_PAD_DISP0_DAT5, 0x3A0, 0x074, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 */
383 IMX_PIN_REG(MX53_PAD_DISP0_DAT6, 0x3A4, 0x078, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 */
384 IMX_PIN_REG(MX53_PAD_DISP0_DAT6, 0x3A4, 0x078, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT6__GPIO4_27 */
385 IMX_PIN_REG(MX53_PAD_DISP0_DAT6, 0x3A4, 0x078, 2, 0x798, 0), /* MX53_PAD_DISP0_DAT6__CSPI_SS3 */
386 IMX_PIN_REG(MX53_PAD_DISP0_DAT6, 0x3A4, 0x078, 3, 0x000, 0), /* MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 */
387 IMX_PIN_REG(MX53_PAD_DISP0_DAT6, 0x3A4, 0x078, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE */
388 IMX_PIN_REG(MX53_PAD_DISP0_DAT6, 0x3A4, 0x078, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 */
389 IMX_PIN_REG(MX53_PAD_DISP0_DAT6, 0x3A4, 0x078, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 */
390 IMX_PIN_REG(MX53_PAD_DISP0_DAT7, 0x3A8, 0x07C, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 */
391 IMX_PIN_REG(MX53_PAD_DISP0_DAT7, 0x3A8, 0x07C, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT7__GPIO4_28 */
392 IMX_PIN_REG(MX53_PAD_DISP0_DAT7, 0x3A8, 0x07C, 2, 0x000, 0), /* MX53_PAD_DISP0_DAT7__CSPI_RDY */
393 IMX_PIN_REG(MX53_PAD_DISP0_DAT7, 0x3A8, 0x07C, 3, 0x000, 0), /* MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 */
394 IMX_PIN_REG(MX53_PAD_DISP0_DAT7, 0x3A8, 0x07C, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 */
395 IMX_PIN_REG(MX53_PAD_DISP0_DAT7, 0x3A8, 0x07C, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 */
396 IMX_PIN_REG(MX53_PAD_DISP0_DAT7, 0x3A8, 0x07C, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID */
397 IMX_PIN_REG(MX53_PAD_DISP0_DAT8, 0x3AC, 0x080, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 */
398 IMX_PIN_REG(MX53_PAD_DISP0_DAT8, 0x3AC, 0x080, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT8__GPIO4_29 */
399 IMX_PIN_REG(MX53_PAD_DISP0_DAT8, 0x3AC, 0x080, 2, 0x000, 0), /* MX53_PAD_DISP0_DAT8__PWM1_PWMO */
400 IMX_PIN_REG(MX53_PAD_DISP0_DAT8, 0x3AC, 0x080, 3, 0x000, 0), /* MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B */
401 IMX_PIN_REG(MX53_PAD_DISP0_DAT8, 0x3AC, 0x080, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 */
402 IMX_PIN_REG(MX53_PAD_DISP0_DAT8, 0x3AC, 0x080, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 */
403 IMX_PIN_REG(MX53_PAD_DISP0_DAT8, 0x3AC, 0x080, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT8__USBPHY2_AVALID */
404 IMX_PIN_REG(MX53_PAD_DISP0_DAT9, 0x3B0, 0x084, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 */
405 IMX_PIN_REG(MX53_PAD_DISP0_DAT9, 0x3B0, 0x084, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT9__GPIO4_30 */
406 IMX_PIN_REG(MX53_PAD_DISP0_DAT9, 0x3B0, 0x084, 2, 0x000, 0), /* MX53_PAD_DISP0_DAT9__PWM2_PWMO */
407 IMX_PIN_REG(MX53_PAD_DISP0_DAT9, 0x3B0, 0x084, 3, 0x000, 0), /* MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B */
408 IMX_PIN_REG(MX53_PAD_DISP0_DAT9, 0x3B0, 0x084, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 */
409 IMX_PIN_REG(MX53_PAD_DISP0_DAT9, 0x3B0, 0x084, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 */
410 IMX_PIN_REG(MX53_PAD_DISP0_DAT9, 0x3B0, 0x084, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 */
411 IMX_PIN_REG(MX53_PAD_DISP0_DAT10, 0x3B4, 0x088, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 */
412 IMX_PIN_REG(MX53_PAD_DISP0_DAT10, 0x3B4, 0x088, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT10__GPIO4_31 */
413 IMX_PIN_REG(MX53_PAD_DISP0_DAT10, 0x3B4, 0x088, 2, 0x000, 0), /* MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP */
414 IMX_PIN_REG(MX53_PAD_DISP0_DAT10, 0x3B4, 0x088, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 */
415 IMX_PIN_REG(MX53_PAD_DISP0_DAT10, 0x3B4, 0x088, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 */
416 IMX_PIN_REG(MX53_PAD_DISP0_DAT10, 0x3B4, 0x088, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 */
417 IMX_PIN_REG(MX53_PAD_DISP0_DAT11, 0x3B8, 0x08C, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 */
418 IMX_PIN_REG(MX53_PAD_DISP0_DAT11, 0x3B8, 0x08C, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT11__GPIO5_5 */
419 IMX_PIN_REG(MX53_PAD_DISP0_DAT11, 0x3B8, 0x08C, 2, 0x000, 0), /* MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT */
420 IMX_PIN_REG(MX53_PAD_DISP0_DAT11, 0x3B8, 0x08C, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 */
421 IMX_PIN_REG(MX53_PAD_DISP0_DAT11, 0x3B8, 0x08C, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 */
422 IMX_PIN_REG(MX53_PAD_DISP0_DAT11, 0x3B8, 0x08C, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 */
423 IMX_PIN_REG(MX53_PAD_DISP0_DAT12, 0x3BC, 0x090, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 */
424 IMX_PIN_REG(MX53_PAD_DISP0_DAT12, 0x3BC, 0x090, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT12__GPIO5_6 */
425 IMX_PIN_REG(MX53_PAD_DISP0_DAT12, 0x3BC, 0x090, 2, 0x000, 0), /* MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK */
426 IMX_PIN_REG(MX53_PAD_DISP0_DAT12, 0x3BC, 0x090, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 */
427 IMX_PIN_REG(MX53_PAD_DISP0_DAT12, 0x3BC, 0x090, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 */
428 IMX_PIN_REG(MX53_PAD_DISP0_DAT12, 0x3BC, 0x090, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 */
429 IMX_PIN_REG(MX53_PAD_DISP0_DAT13, 0x3C0, 0x094, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 */
430 IMX_PIN_REG(MX53_PAD_DISP0_DAT13, 0x3C0, 0x094, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT13__GPIO5_7 */
431 IMX_PIN_REG(MX53_PAD_DISP0_DAT13, 0x3C0, 0x094, 3, 0x754, 0), /* MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS */
432 IMX_PIN_REG(MX53_PAD_DISP0_DAT13, 0x3C0, 0x094, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 */
433 IMX_PIN_REG(MX53_PAD_DISP0_DAT13, 0x3C0, 0x094, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 */
434 IMX_PIN_REG(MX53_PAD_DISP0_DAT13, 0x3C0, 0x094, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 */
435 IMX_PIN_REG(MX53_PAD_DISP0_DAT14, 0x3C4, 0x098, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 */
436 IMX_PIN_REG(MX53_PAD_DISP0_DAT14, 0x3C4, 0x098, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT14__GPIO5_8 */
437 IMX_PIN_REG(MX53_PAD_DISP0_DAT14, 0x3C4, 0x098, 3, 0x750, 0), /* MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC */
438 IMX_PIN_REG(MX53_PAD_DISP0_DAT14, 0x3C4, 0x098, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 */
439 IMX_PIN_REG(MX53_PAD_DISP0_DAT14, 0x3C4, 0x098, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 */
440 IMX_PIN_REG(MX53_PAD_DISP0_DAT14, 0x3C4, 0x098, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 */
441 IMX_PIN_REG(MX53_PAD_DISP0_DAT15, 0x3C8, 0x09C, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 */
442 IMX_PIN_REG(MX53_PAD_DISP0_DAT15, 0x3C8, 0x09C, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT15__GPIO5_9 */
443 IMX_PIN_REG(MX53_PAD_DISP0_DAT15, 0x3C8, 0x09C, 2, 0x7AC, 1), /* MX53_PAD_DISP0_DAT15__ECSPI1_SS1 */
444 IMX_PIN_REG(MX53_PAD_DISP0_DAT15, 0x3C8, 0x09C, 3, 0x7C8, 0), /* MX53_PAD_DISP0_DAT15__ECSPI2_SS1 */
445 IMX_PIN_REG(MX53_PAD_DISP0_DAT15, 0x3C8, 0x09C, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 */
446 IMX_PIN_REG(MX53_PAD_DISP0_DAT15, 0x3C8, 0x09C, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 */
447 IMX_PIN_REG(MX53_PAD_DISP0_DAT15, 0x3C8, 0x09C, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 */
448 IMX_PIN_REG(MX53_PAD_DISP0_DAT16, 0x3CC, 0x0A0, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 */
449 IMX_PIN_REG(MX53_PAD_DISP0_DAT16, 0x3CC, 0x0A0, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT16__GPIO5_10 */
450 IMX_PIN_REG(MX53_PAD_DISP0_DAT16, 0x3CC, 0x0A0, 2, 0x7C0, 0), /* MX53_PAD_DISP0_DAT16__ECSPI2_MOSI */
451 IMX_PIN_REG(MX53_PAD_DISP0_DAT16, 0x3CC, 0x0A0, 3, 0x758, 1), /* MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC */
452 IMX_PIN_REG(MX53_PAD_DISP0_DAT16, 0x3CC, 0x0A0, 4, 0x868, 0), /* MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 */
453 IMX_PIN_REG(MX53_PAD_DISP0_DAT16, 0x3CC, 0x0A0, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 */
454 IMX_PIN_REG(MX53_PAD_DISP0_DAT16, 0x3CC, 0x0A0, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 */
455 IMX_PIN_REG(MX53_PAD_DISP0_DAT16, 0x3CC, 0x0A0, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 */
456 IMX_PIN_REG(MX53_PAD_DISP0_DAT17, 0x3D0, 0x0A4, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 */
457 IMX_PIN_REG(MX53_PAD_DISP0_DAT17, 0x3D0, 0x0A4, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT17__GPIO5_11 */
458 IMX_PIN_REG(MX53_PAD_DISP0_DAT17, 0x3D0, 0x0A4, 2, 0x7BC, 0), /* MX53_PAD_DISP0_DAT17__ECSPI2_MISO */
459 IMX_PIN_REG(MX53_PAD_DISP0_DAT17, 0x3D0, 0x0A4, 3, 0x74C, 1), /* MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD */
460 IMX_PIN_REG(MX53_PAD_DISP0_DAT17, 0x3D0, 0x0A4, 4, 0x86C, 0), /* MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 */
461 IMX_PIN_REG(MX53_PAD_DISP0_DAT17, 0x3D0, 0x0A4, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 */
462 IMX_PIN_REG(MX53_PAD_DISP0_DAT17, 0x3D0, 0x0A4, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 */
463 IMX_PIN_REG(MX53_PAD_DISP0_DAT18, 0x3D4, 0x0A8, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 */
464 IMX_PIN_REG(MX53_PAD_DISP0_DAT18, 0x3D4, 0x0A8, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT18__GPIO5_12 */
465 IMX_PIN_REG(MX53_PAD_DISP0_DAT18, 0x3D4, 0x0A8, 2, 0x7C4, 0), /* MX53_PAD_DISP0_DAT18__ECSPI2_SS0 */
466 IMX_PIN_REG(MX53_PAD_DISP0_DAT18, 0x3D4, 0x0A8, 3, 0x75C, 1), /* MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS */
467 IMX_PIN_REG(MX53_PAD_DISP0_DAT18, 0x3D4, 0x0A8, 4, 0x73C, 0), /* MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS */
468 IMX_PIN_REG(MX53_PAD_DISP0_DAT18, 0x3D4, 0x0A8, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 */
469 IMX_PIN_REG(MX53_PAD_DISP0_DAT18, 0x3D4, 0x0A8, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 */
470 IMX_PIN_REG(MX53_PAD_DISP0_DAT18, 0x3D4, 0x0A8, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 */
471 IMX_PIN_REG(MX53_PAD_DISP0_DAT19, 0x3D8, 0x0AC, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 */
472 IMX_PIN_REG(MX53_PAD_DISP0_DAT19, 0x3D8, 0x0AC, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT19__GPIO5_13 */
473 IMX_PIN_REG(MX53_PAD_DISP0_DAT19, 0x3D8, 0x0AC, 2, 0x7B8, 0), /* MX53_PAD_DISP0_DAT19__ECSPI2_SCLK */
474 IMX_PIN_REG(MX53_PAD_DISP0_DAT19, 0x3D8, 0x0AC, 3, 0x748, 1), /* MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD */
475 IMX_PIN_REG(MX53_PAD_DISP0_DAT19, 0x3D8, 0x0AC, 4, 0x738, 0), /* MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC */
476 IMX_PIN_REG(MX53_PAD_DISP0_DAT19, 0x3D8, 0x0AC, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 */
477 IMX_PIN_REG(MX53_PAD_DISP0_DAT19, 0x3D8, 0x0AC, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 */
478 IMX_PIN_REG(MX53_PAD_DISP0_DAT19, 0x3D8, 0x0AC, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 */
479 IMX_PIN_REG(MX53_PAD_DISP0_DAT20, 0x3DC, 0x0B0, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 */
480 IMX_PIN_REG(MX53_PAD_DISP0_DAT20, 0x3DC, 0x0B0, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT20__GPIO5_14 */
481 IMX_PIN_REG(MX53_PAD_DISP0_DAT20, 0x3DC, 0x0B0, 2, 0x79C, 1), /* MX53_PAD_DISP0_DAT20__ECSPI1_SCLK */
482 IMX_PIN_REG(MX53_PAD_DISP0_DAT20, 0x3DC, 0x0B0, 3, 0x740, 0), /* MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC */
483 IMX_PIN_REG(MX53_PAD_DISP0_DAT20, 0x3DC, 0x0B0, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 */
484 IMX_PIN_REG(MX53_PAD_DISP0_DAT20, 0x3DC, 0x0B0, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 */
485 IMX_PIN_REG(MX53_PAD_DISP0_DAT20, 0x3DC, 0x0B0, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT20__SATA_PHY_TDI */
486 IMX_PIN_REG(MX53_PAD_DISP0_DAT21, 0x3E0, 0x0B4, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 */
487 IMX_PIN_REG(MX53_PAD_DISP0_DAT21, 0x3E0, 0x0B4, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT21__GPIO5_15 */
488 IMX_PIN_REG(MX53_PAD_DISP0_DAT21, 0x3E0, 0x0B4, 2, 0x7A4, 1), /* MX53_PAD_DISP0_DAT21__ECSPI1_MOSI */
489 IMX_PIN_REG(MX53_PAD_DISP0_DAT21, 0x3E0, 0x0B4, 3, 0x734, 0), /* MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD */
490 IMX_PIN_REG(MX53_PAD_DISP0_DAT21, 0x3E0, 0x0B4, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 */
491 IMX_PIN_REG(MX53_PAD_DISP0_DAT21, 0x3E0, 0x0B4, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 */
492 IMX_PIN_REG(MX53_PAD_DISP0_DAT21, 0x3E0, 0x0B4, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT21__SATA_PHY_TDO */
493 IMX_PIN_REG(MX53_PAD_DISP0_DAT22, 0x3E4, 0x0B8, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 */
494 IMX_PIN_REG(MX53_PAD_DISP0_DAT22, 0x3E4, 0x0B8, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT22__GPIO5_16 */
495 IMX_PIN_REG(MX53_PAD_DISP0_DAT22, 0x3E4, 0x0B8, 2, 0x7A0, 1), /* MX53_PAD_DISP0_DAT22__ECSPI1_MISO */
496 IMX_PIN_REG(MX53_PAD_DISP0_DAT22, 0x3E4, 0x0B8, 3, 0x744, 0), /* MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS */
497 IMX_PIN_REG(MX53_PAD_DISP0_DAT22, 0x3E4, 0x0B8, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 */
498 IMX_PIN_REG(MX53_PAD_DISP0_DAT22, 0x3E4, 0x0B8, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 */
499 IMX_PIN_REG(MX53_PAD_DISP0_DAT22, 0x3E4, 0x0B8, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT22__SATA_PHY_TCK */
500 IMX_PIN_REG(MX53_PAD_DISP0_DAT23, 0x3E8, 0x0BC, 0, 0x000, 0), /* MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 */
501 IMX_PIN_REG(MX53_PAD_DISP0_DAT23, 0x3E8, 0x0BC, 1, 0x000, 0), /* MX53_PAD_DISP0_DAT23__GPIO5_17 */
502 IMX_PIN_REG(MX53_PAD_DISP0_DAT23, 0x3E8, 0x0BC, 2, 0x7A8, 1), /* MX53_PAD_DISP0_DAT23__ECSPI1_SS0 */
503 IMX_PIN_REG(MX53_PAD_DISP0_DAT23, 0x3E8, 0x0BC, 3, 0x730, 0), /* MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD */
504 IMX_PIN_REG(MX53_PAD_DISP0_DAT23, 0x3E8, 0x0BC, 5, 0x000, 0), /* MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 */
505 IMX_PIN_REG(MX53_PAD_DISP0_DAT23, 0x3E8, 0x0BC, 6, 0x000, 0), /* MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 */
506 IMX_PIN_REG(MX53_PAD_DISP0_DAT23, 0x3E8, 0x0BC, 7, 0x000, 0), /* MX53_PAD_DISP0_DAT23__SATA_PHY_TMS */
507 IMX_PIN_REG(MX53_PAD_CSI0_PIXCLK, 0x3EC, 0x0C0, 0, 0x000, 0), /* MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK */
508 IMX_PIN_REG(MX53_PAD_CSI0_PIXCLK, 0x3EC, 0x0C0, 1, 0x000, 0), /* MX53_PAD_CSI0_PIXCLK__GPIO5_18 */
509 IMX_PIN_REG(MX53_PAD_CSI0_PIXCLK, 0x3EC, 0x0C0, 5, 0x000, 0), /* MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 */
510 IMX_PIN_REG(MX53_PAD_CSI0_PIXCLK, 0x3EC, 0x0C0, 6, 0x000, 0), /* MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 */
511 IMX_PIN_REG(MX53_PAD_CSI0_MCLK, 0x3F0, 0x0C4, 0, 0x000, 0), /* MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC */
512 IMX_PIN_REG(MX53_PAD_CSI0_MCLK, 0x3F0, 0x0C4, 1, 0x000, 0), /* MX53_PAD_CSI0_MCLK__GPIO5_19 */
513 IMX_PIN_REG(MX53_PAD_CSI0_MCLK, 0x3F0, 0x0C4, 2, 0x000, 0), /* MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK */
514 IMX_PIN_REG(MX53_PAD_CSI0_MCLK, 0x3F0, 0x0C4, 5, 0x000, 0), /* MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 */
515 IMX_PIN_REG(MX53_PAD_CSI0_MCLK, 0x3F0, 0x0C4, 6, 0x000, 0), /* MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 */
516 IMX_PIN_REG(MX53_PAD_CSI0_MCLK, 0x3F0, 0x0C4, 7, 0x000, 0), /* MX53_PAD_CSI0_MCLK__TPIU_TRCTL */
517 IMX_PIN_REG(MX53_PAD_CSI0_DATA_EN, 0x3F4, 0x0C8, 0, 0x000, 0), /* MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN */
518 IMX_PIN_REG(MX53_PAD_CSI0_DATA_EN, 0x3F4, 0x0C8, 1, 0x000, 0), /* MX53_PAD_CSI0_DATA_EN__GPIO5_20 */
519 IMX_PIN_REG(MX53_PAD_CSI0_DATA_EN, 0x3F4, 0x0C8, 5, 0x000, 0), /* MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 */
520 IMX_PIN_REG(MX53_PAD_CSI0_DATA_EN, 0x3F4, 0x0C8, 6, 0x000, 0), /* MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 */
521 IMX_PIN_REG(MX53_PAD_CSI0_DATA_EN, 0x3F4, 0x0C8, 7, 0x000, 0), /* MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK */
522 IMX_PIN_REG(MX53_PAD_CSI0_VSYNC, 0x3F8, 0x0CC, 0, 0x000, 0), /* MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC */
523 IMX_PIN_REG(MX53_PAD_CSI0_VSYNC, 0x3F8, 0x0CC, 1, 0x000, 0), /* MX53_PAD_CSI0_VSYNC__GPIO5_21 */
524 IMX_PIN_REG(MX53_PAD_CSI0_VSYNC, 0x3F8, 0x0CC, 5, 0x000, 0), /* MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 */
525 IMX_PIN_REG(MX53_PAD_CSI0_VSYNC, 0x3F8, 0x0CC, 6, 0x000, 0), /* MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 */
526 IMX_PIN_REG(MX53_PAD_CSI0_VSYNC, 0x3F8, 0x0CC, 7, 0x000, 0), /* MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 */
527 IMX_PIN_REG(MX53_PAD_CSI0_DAT4, 0x3FC, 0x0D0, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 */
528 IMX_PIN_REG(MX53_PAD_CSI0_DAT4, 0x3FC, 0x0D0, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT4__GPIO5_22 */
529 IMX_PIN_REG(MX53_PAD_CSI0_DAT4, 0x3FC, 0x0D0, 2, 0x840, 1), /* MX53_PAD_CSI0_DAT4__KPP_COL_5 */
530 IMX_PIN_REG(MX53_PAD_CSI0_DAT4, 0x3FC, 0x0D0, 3, 0x79C, 2), /* MX53_PAD_CSI0_DAT4__ECSPI1_SCLK */
531 IMX_PIN_REG(MX53_PAD_CSI0_DAT4, 0x3FC, 0x0D0, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP */
532 IMX_PIN_REG(MX53_PAD_CSI0_DAT4, 0x3FC, 0x0D0, 5, 0x000, 0), /* MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC */
533 IMX_PIN_REG(MX53_PAD_CSI0_DAT4, 0x3FC, 0x0D0, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 */
534 IMX_PIN_REG(MX53_PAD_CSI0_DAT4, 0x3FC, 0x0D0, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 */
535 IMX_PIN_REG(MX53_PAD_CSI0_DAT5, 0x400, 0x0D4, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 */
536 IMX_PIN_REG(MX53_PAD_CSI0_DAT5, 0x400, 0x0D4, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT5__GPIO5_23 */
537 IMX_PIN_REG(MX53_PAD_CSI0_DAT5, 0x400, 0x0D4, 2, 0x84C, 0), /* MX53_PAD_CSI0_DAT5__KPP_ROW_5 */
538 IMX_PIN_REG(MX53_PAD_CSI0_DAT5, 0x400, 0x0D4, 3, 0x7A4, 2), /* MX53_PAD_CSI0_DAT5__ECSPI1_MOSI */
539 IMX_PIN_REG(MX53_PAD_CSI0_DAT5, 0x400, 0x0D4, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT */
540 IMX_PIN_REG(MX53_PAD_CSI0_DAT5, 0x400, 0x0D4, 5, 0x000, 0), /* MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD */
541 IMX_PIN_REG(MX53_PAD_CSI0_DAT5, 0x400, 0x0D4, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 */
542 IMX_PIN_REG(MX53_PAD_CSI0_DAT5, 0x400, 0x0D4, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 */
543 IMX_PIN_REG(MX53_PAD_CSI0_DAT6, 0x404, 0x0D8, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 */
544 IMX_PIN_REG(MX53_PAD_CSI0_DAT6, 0x404, 0x0D8, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT6__GPIO5_24 */
545 IMX_PIN_REG(MX53_PAD_CSI0_DAT6, 0x404, 0x0D8, 2, 0x844, 0), /* MX53_PAD_CSI0_DAT6__KPP_COL_6 */
546 IMX_PIN_REG(MX53_PAD_CSI0_DAT6, 0x404, 0x0D8, 3, 0x7A0, 2), /* MX53_PAD_CSI0_DAT6__ECSPI1_MISO */
547 IMX_PIN_REG(MX53_PAD_CSI0_DAT6, 0x404, 0x0D8, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK */
548 IMX_PIN_REG(MX53_PAD_CSI0_DAT6, 0x404, 0x0D8, 5, 0x000, 0), /* MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS */
549 IMX_PIN_REG(MX53_PAD_CSI0_DAT6, 0x404, 0x0D8, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 */
550 IMX_PIN_REG(MX53_PAD_CSI0_DAT6, 0x404, 0x0D8, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 */
551 IMX_PIN_REG(MX53_PAD_CSI0_DAT7, 0x408, 0x0DC, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 */
552 IMX_PIN_REG(MX53_PAD_CSI0_DAT7, 0x408, 0x0DC, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT7__GPIO5_25 */
553 IMX_PIN_REG(MX53_PAD_CSI0_DAT7, 0x408, 0x0DC, 2, 0x850, 0), /* MX53_PAD_CSI0_DAT7__KPP_ROW_6 */
554 IMX_PIN_REG(MX53_PAD_CSI0_DAT7, 0x408, 0x0DC, 3, 0x7A8, 2), /* MX53_PAD_CSI0_DAT7__ECSPI1_SS0 */
555 IMX_PIN_REG(MX53_PAD_CSI0_DAT7, 0x408, 0x0DC, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR */
556 IMX_PIN_REG(MX53_PAD_CSI0_DAT7, 0x408, 0x0DC, 5, 0x000, 0), /* MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD */
557 IMX_PIN_REG(MX53_PAD_CSI0_DAT7, 0x408, 0x0DC, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 */
558 IMX_PIN_REG(MX53_PAD_CSI0_DAT7, 0x408, 0x0DC, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 */
559 IMX_PIN_REG(MX53_PAD_CSI0_DAT8, 0x40C, 0x0E0, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 */
560 IMX_PIN_REG(MX53_PAD_CSI0_DAT8, 0x40C, 0x0E0, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT8__GPIO5_26 */
561 IMX_PIN_REG(MX53_PAD_CSI0_DAT8, 0x40C, 0x0E0, 2, 0x848, 0), /* MX53_PAD_CSI0_DAT8__KPP_COL_7 */
562 IMX_PIN_REG(MX53_PAD_CSI0_DAT8, 0x40C, 0x0E0, 3, 0x7B8, 1), /* MX53_PAD_CSI0_DAT8__ECSPI2_SCLK */
563 IMX_PIN_REG(MX53_PAD_CSI0_DAT8, 0x40C, 0x0E0, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC */
564 IMX_PIN_REG(MX53_PAD_CSI0_DAT8, 0x40C, 0x0E0, 5, 0x818, 0), /* MX53_PAD_CSI0_DAT8__I2C1_SDA */
565 IMX_PIN_REG(MX53_PAD_CSI0_DAT8, 0x40C, 0x0E0, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 */
566 IMX_PIN_REG(MX53_PAD_CSI0_DAT8, 0x40C, 0x0E0, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 */
567 IMX_PIN_REG(MX53_PAD_CSI0_DAT9, 0x410, 0x0E4, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 */
568 IMX_PIN_REG(MX53_PAD_CSI0_DAT9, 0x410, 0x0E4, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT9__GPIO5_27 */
569 IMX_PIN_REG(MX53_PAD_CSI0_DAT9, 0x410, 0x0E4, 2, 0x854, 0), /* MX53_PAD_CSI0_DAT9__KPP_ROW_7 */
570 IMX_PIN_REG(MX53_PAD_CSI0_DAT9, 0x410, 0x0E4, 3, 0x7C0, 1), /* MX53_PAD_CSI0_DAT9__ECSPI2_MOSI */
571 IMX_PIN_REG(MX53_PAD_CSI0_DAT9, 0x410, 0x0E4, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR */
572 IMX_PIN_REG(MX53_PAD_CSI0_DAT9, 0x410, 0x0E4, 5, 0x814, 0), /* MX53_PAD_CSI0_DAT9__I2C1_SCL */
573 IMX_PIN_REG(MX53_PAD_CSI0_DAT9, 0x410, 0x0E4, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 */
574 IMX_PIN_REG(MX53_PAD_CSI0_DAT9, 0x410, 0x0E4, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 */
575 IMX_PIN_REG(MX53_PAD_CSI0_DAT10, 0x414, 0x0E8, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 */
576 IMX_PIN_REG(MX53_PAD_CSI0_DAT10, 0x414, 0x0E8, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT10__GPIO5_28 */
577 IMX_PIN_REG(MX53_PAD_CSI0_DAT10, 0x414, 0x0E8, 2, 0x000, 0), /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */
578 IMX_PIN_REG(MX53_PAD_CSI0_DAT10, 0x414, 0x0E8, 3, 0x7BC, 1), /* MX53_PAD_CSI0_DAT10__ECSPI2_MISO */
579 IMX_PIN_REG(MX53_PAD_CSI0_DAT10, 0x414, 0x0E8, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC */
580 IMX_PIN_REG(MX53_PAD_CSI0_DAT10, 0x414, 0x0E8, 5, 0x000, 0), /* MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 */
581 IMX_PIN_REG(MX53_PAD_CSI0_DAT10, 0x414, 0x0E8, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 */
582 IMX_PIN_REG(MX53_PAD_CSI0_DAT10, 0x414, 0x0E8, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 */
583 IMX_PIN_REG(MX53_PAD_CSI0_DAT11, 0x418, 0x0EC, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 */
584 IMX_PIN_REG(MX53_PAD_CSI0_DAT11, 0x418, 0x0EC, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT11__GPIO5_29 */
585 IMX_PIN_REG(MX53_PAD_CSI0_DAT11, 0x418, 0x0EC, 2, 0x878, 1), /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */
586 IMX_PIN_REG(MX53_PAD_CSI0_DAT11, 0x418, 0x0EC, 3, 0x7C4, 1), /* MX53_PAD_CSI0_DAT11__ECSPI2_SS0 */
587 IMX_PIN_REG(MX53_PAD_CSI0_DAT11, 0x418, 0x0EC, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS */
588 IMX_PIN_REG(MX53_PAD_CSI0_DAT11, 0x418, 0x0EC, 5, 0x000, 0), /* MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 */
589 IMX_PIN_REG(MX53_PAD_CSI0_DAT11, 0x418, 0x0EC, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 */
590 IMX_PIN_REG(MX53_PAD_CSI0_DAT11, 0x418, 0x0EC, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 */
591 IMX_PIN_REG(MX53_PAD_CSI0_DAT12, 0x41C, 0x0F0, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 */
592 IMX_PIN_REG(MX53_PAD_CSI0_DAT12, 0x41C, 0x0F0, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT12__GPIO5_30 */
593 IMX_PIN_REG(MX53_PAD_CSI0_DAT12, 0x41C, 0x0F0, 2, 0x000, 0), /* MX53_PAD_CSI0_DAT12__UART4_TXD_MUX */
594 IMX_PIN_REG(MX53_PAD_CSI0_DAT12, 0x41C, 0x0F0, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 */
595 IMX_PIN_REG(MX53_PAD_CSI0_DAT12, 0x41C, 0x0F0, 5, 0x000, 0), /* MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 */
596 IMX_PIN_REG(MX53_PAD_CSI0_DAT12, 0x41C, 0x0F0, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 */
597 IMX_PIN_REG(MX53_PAD_CSI0_DAT12, 0x41C, 0x0F0, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 */
598 IMX_PIN_REG(MX53_PAD_CSI0_DAT13, 0x420, 0x0F4, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 */
599 IMX_PIN_REG(MX53_PAD_CSI0_DAT13, 0x420, 0x0F4, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT13__GPIO5_31 */
600 IMX_PIN_REG(MX53_PAD_CSI0_DAT13, 0x420, 0x0F4, 2, 0x890, 3), /* MX53_PAD_CSI0_DAT13__UART4_RXD_MUX */
601 IMX_PIN_REG(MX53_PAD_CSI0_DAT13, 0x420, 0x0F4, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 */
602 IMX_PIN_REG(MX53_PAD_CSI0_DAT13, 0x420, 0x0F4, 5, 0x000, 0), /* MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 */
603 IMX_PIN_REG(MX53_PAD_CSI0_DAT13, 0x420, 0x0F4, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 */
604 IMX_PIN_REG(MX53_PAD_CSI0_DAT13, 0x420, 0x0F4, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 */
605 IMX_PIN_REG(MX53_PAD_CSI0_DAT14, 0x424, 0x0F8, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 */
606 IMX_PIN_REG(MX53_PAD_CSI0_DAT14, 0x424, 0x0F8, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT14__GPIO6_0 */
607 IMX_PIN_REG(MX53_PAD_CSI0_DAT14, 0x424, 0x0F8, 2, 0x000, 0), /* MX53_PAD_CSI0_DAT14__UART5_TXD_MUX */
608 IMX_PIN_REG(MX53_PAD_CSI0_DAT14, 0x424, 0x0F8, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 */
609 IMX_PIN_REG(MX53_PAD_CSI0_DAT14, 0x424, 0x0F8, 5, 0x000, 0), /* MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 */
610 IMX_PIN_REG(MX53_PAD_CSI0_DAT14, 0x424, 0x0F8, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 */
611 IMX_PIN_REG(MX53_PAD_CSI0_DAT14, 0x424, 0x0F8, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 */
612 IMX_PIN_REG(MX53_PAD_CSI0_DAT15, 0x428, 0x0FC, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 */
613 IMX_PIN_REG(MX53_PAD_CSI0_DAT15, 0x428, 0x0FC, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT15__GPIO6_1 */
614 IMX_PIN_REG(MX53_PAD_CSI0_DAT15, 0x428, 0x0FC, 2, 0x898, 3), /* MX53_PAD_CSI0_DAT15__UART5_RXD_MUX */
615 IMX_PIN_REG(MX53_PAD_CSI0_DAT15, 0x428, 0x0FC, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 */
616 IMX_PIN_REG(MX53_PAD_CSI0_DAT15, 0x428, 0x0FC, 5, 0x000, 0), /* MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 */
617 IMX_PIN_REG(MX53_PAD_CSI0_DAT15, 0x428, 0x0FC, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 */
618 IMX_PIN_REG(MX53_PAD_CSI0_DAT15, 0x428, 0x0FC, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 */
619 IMX_PIN_REG(MX53_PAD_CSI0_DAT16, 0x42C, 0x100, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 */
620 IMX_PIN_REG(MX53_PAD_CSI0_DAT16, 0x42C, 0x100, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT16__GPIO6_2 */
621 IMX_PIN_REG(MX53_PAD_CSI0_DAT16, 0x42C, 0x100, 2, 0x88C, 0), /* MX53_PAD_CSI0_DAT16__UART4_RTS */
622 IMX_PIN_REG(MX53_PAD_CSI0_DAT16, 0x42C, 0x100, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 */
623 IMX_PIN_REG(MX53_PAD_CSI0_DAT16, 0x42C, 0x100, 5, 0x000, 0), /* MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 */
624 IMX_PIN_REG(MX53_PAD_CSI0_DAT16, 0x42C, 0x100, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 */
625 IMX_PIN_REG(MX53_PAD_CSI0_DAT16, 0x42C, 0x100, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 */
626 IMX_PIN_REG(MX53_PAD_CSI0_DAT17, 0x430, 0x104, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 */
627 IMX_PIN_REG(MX53_PAD_CSI0_DAT17, 0x430, 0x104, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT17__GPIO6_3 */
628 IMX_PIN_REG(MX53_PAD_CSI0_DAT17, 0x430, 0x104, 2, 0x000, 0), /* MX53_PAD_CSI0_DAT17__UART4_CTS */
629 IMX_PIN_REG(MX53_PAD_CSI0_DAT17, 0x430, 0x104, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 */
630 IMX_PIN_REG(MX53_PAD_CSI0_DAT17, 0x430, 0x104, 5, 0x000, 0), /* MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 */
631 IMX_PIN_REG(MX53_PAD_CSI0_DAT17, 0x430, 0x104, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 */
632 IMX_PIN_REG(MX53_PAD_CSI0_DAT17, 0x430, 0x104, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 */
633 IMX_PIN_REG(MX53_PAD_CSI0_DAT18, 0x434, 0x108, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 */
634 IMX_PIN_REG(MX53_PAD_CSI0_DAT18, 0x434, 0x108, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT18__GPIO6_4 */
635 IMX_PIN_REG(MX53_PAD_CSI0_DAT18, 0x434, 0x108, 2, 0x894, 2), /* MX53_PAD_CSI0_DAT18__UART5_RTS */
636 IMX_PIN_REG(MX53_PAD_CSI0_DAT18, 0x434, 0x108, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 */
637 IMX_PIN_REG(MX53_PAD_CSI0_DAT18, 0x434, 0x108, 5, 0x000, 0), /* MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 */
638 IMX_PIN_REG(MX53_PAD_CSI0_DAT18, 0x434, 0x108, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 */
639 IMX_PIN_REG(MX53_PAD_CSI0_DAT18, 0x434, 0x108, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 */
640 IMX_PIN_REG(MX53_PAD_CSI0_DAT19, 0x438, 0x10C, 0, 0x000, 0), /* MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 */
641 IMX_PIN_REG(MX53_PAD_CSI0_DAT19, 0x438, 0x10C, 1, 0x000, 0), /* MX53_PAD_CSI0_DAT19__GPIO6_5 */
642 IMX_PIN_REG(MX53_PAD_CSI0_DAT19, 0x438, 0x10C, 2, 0x000, 0), /* MX53_PAD_CSI0_DAT19__UART5_CTS */
643 IMX_PIN_REG(MX53_PAD_CSI0_DAT19, 0x438, 0x10C, 4, 0x000, 0), /* MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 */
644 IMX_PIN_REG(MX53_PAD_CSI0_DAT19, 0x438, 0x10C, 5, 0x000, 0), /* MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 */
645 IMX_PIN_REG(MX53_PAD_CSI0_DAT19, 0x438, 0x10C, 6, 0x000, 0), /* MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 */
646 IMX_PIN_REG(MX53_PAD_CSI0_DAT19, 0x438, 0x10C, 7, 0x000, 0), /* MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK */
647 IMX_PIN_REG(MX53_PAD_EIM_A25, 0x458, 0x110, 0, 0x000, 0), /* MX53_PAD_EIM_A25__EMI_WEIM_A_25 */
648 IMX_PIN_REG(MX53_PAD_EIM_A25, 0x458, 0x110, 1, 0x000, 0), /* MX53_PAD_EIM_A25__GPIO5_2 */
649 IMX_PIN_REG(MX53_PAD_EIM_A25, 0x458, 0x110, 2, 0x000, 0), /* MX53_PAD_EIM_A25__ECSPI2_RDY */
650 IMX_PIN_REG(MX53_PAD_EIM_A25, 0x458, 0x110, 3, 0x000, 0), /* MX53_PAD_EIM_A25__IPU_DI1_PIN12 */
651 IMX_PIN_REG(MX53_PAD_EIM_A25, 0x458, 0x110, 4, 0x790, 1), /* MX53_PAD_EIM_A25__CSPI_SS1 */
652 IMX_PIN_REG(MX53_PAD_EIM_A25, 0x458, 0x110, 6, 0x000, 0), /* MX53_PAD_EIM_A25__IPU_DI0_D1_CS */
653 IMX_PIN_REG(MX53_PAD_EIM_A25, 0x458, 0x110, 7, 0x000, 0), /* MX53_PAD_EIM_A25__USBPHY1_BISTOK */
654 IMX_PIN_REG(MX53_PAD_EIM_EB2, 0x45C, 0x114, 0, 0x000, 0), /* MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 */
655 IMX_PIN_REG(MX53_PAD_EIM_EB2, 0x45C, 0x114, 1, 0x000, 0), /* MX53_PAD_EIM_EB2__GPIO2_30 */
656 IMX_PIN_REG(MX53_PAD_EIM_EB2, 0x45C, 0x114, 2, 0x76C, 0), /* MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK */
657 IMX_PIN_REG(MX53_PAD_EIM_EB2, 0x45C, 0x114, 3, 0x000, 0), /* MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS */
658 IMX_PIN_REG(MX53_PAD_EIM_EB2, 0x45C, 0x114, 4, 0x7A8, 3), /* MX53_PAD_EIM_EB2__ECSPI1_SS0 */
659 IMX_PIN_REG(MX53_PAD_EIM_EB2, 0x45C, 0x114, 5, 0x81C, 1), /* MX53_PAD_EIM_EB2__I2C2_SCL */
660 IMX_PIN_REG(MX53_PAD_EIM_D16, 0x460, 0x118, 0, 0x000, 0), /* MX53_PAD_EIM_D16__EMI_WEIM_D_16 */
661 IMX_PIN_REG(MX53_PAD_EIM_D16, 0x460, 0x118, 1, 0x000, 0), /* MX53_PAD_EIM_D16__GPIO3_16 */
662 IMX_PIN_REG(MX53_PAD_EIM_D16, 0x460, 0x118, 2, 0x000, 0), /* MX53_PAD_EIM_D16__IPU_DI0_PIN5 */
663 IMX_PIN_REG(MX53_PAD_EIM_D16, 0x460, 0x118, 3, 0x000, 0), /* MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK */
664 IMX_PIN_REG(MX53_PAD_EIM_D16, 0x460, 0x118, 4, 0x79C, 3), /* MX53_PAD_EIM_D16__ECSPI1_SCLK */
665 IMX_PIN_REG(MX53_PAD_EIM_D16, 0x460, 0x118, 5, 0x820, 1), /* MX53_PAD_EIM_D16__I2C2_SDA */
666 IMX_PIN_REG(MX53_PAD_EIM_D17, 0x464, 0x11C, 0, 0x000, 0), /* MX53_PAD_EIM_D17__EMI_WEIM_D_17 */
667 IMX_PIN_REG(MX53_PAD_EIM_D17, 0x464, 0x11C, 1, 0x000, 0), /* MX53_PAD_EIM_D17__GPIO3_17 */
668 IMX_PIN_REG(MX53_PAD_EIM_D17, 0x464, 0x11C, 2, 0x000, 0), /* MX53_PAD_EIM_D17__IPU_DI0_PIN6 */
669 IMX_PIN_REG(MX53_PAD_EIM_D17, 0x464, 0x11C, 3, 0x830, 0), /* MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN */
670 IMX_PIN_REG(MX53_PAD_EIM_D17, 0x464, 0x11C, 4, 0x7A0, 3), /* MX53_PAD_EIM_D17__ECSPI1_MISO */
671 IMX_PIN_REG(MX53_PAD_EIM_D17, 0x464, 0x11C, 5, 0x824, 0), /* MX53_PAD_EIM_D17__I2C3_SCL */
672 IMX_PIN_REG(MX53_PAD_EIM_D18, 0x468, 0x120, 0, 0x000, 0), /* MX53_PAD_EIM_D18__EMI_WEIM_D_18 */
673 IMX_PIN_REG(MX53_PAD_EIM_D18, 0x468, 0x120, 1, 0x000, 0), /* MX53_PAD_EIM_D18__GPIO3_18 */
674 IMX_PIN_REG(MX53_PAD_EIM_D18, 0x468, 0x120, 2, 0x000, 0), /* MX53_PAD_EIM_D18__IPU_DI0_PIN7 */
675 IMX_PIN_REG(MX53_PAD_EIM_D18, 0x468, 0x120, 3, 0x830, 1), /* MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO */
676 IMX_PIN_REG(MX53_PAD_EIM_D18, 0x468, 0x120, 4, 0x7A4, 3), /* MX53_PAD_EIM_D18__ECSPI1_MOSI */
677 IMX_PIN_REG(MX53_PAD_EIM_D18, 0x468, 0x120, 5, 0x828, 0), /* MX53_PAD_EIM_D18__I2C3_SDA */
678 IMX_PIN_REG(MX53_PAD_EIM_D18, 0x468, 0x120, 6, 0x000, 0), /* MX53_PAD_EIM_D18__IPU_DI1_D0_CS */
679 IMX_PIN_REG(MX53_PAD_EIM_D19, 0x46C, 0x124, 0, 0x000, 0), /* MX53_PAD_EIM_D19__EMI_WEIM_D_19 */
680 IMX_PIN_REG(MX53_PAD_EIM_D19, 0x46C, 0x124, 1, 0x000, 0), /* MX53_PAD_EIM_D19__GPIO3_19 */
681 IMX_PIN_REG(MX53_PAD_EIM_D19, 0x46C, 0x124, 2, 0x000, 0), /* MX53_PAD_EIM_D19__IPU_DI0_PIN8 */
682 IMX_PIN_REG(MX53_PAD_EIM_D19, 0x46C, 0x124, 3, 0x000, 0), /* MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS */
683 IMX_PIN_REG(MX53_PAD_EIM_D19, 0x46C, 0x124, 4, 0x7AC, 2), /* MX53_PAD_EIM_D19__ECSPI1_SS1 */
684 IMX_PIN_REG(MX53_PAD_EIM_D19, 0x46C, 0x124, 5, 0x000, 0), /* MX53_PAD_EIM_D19__EPIT1_EPITO */
685 IMX_PIN_REG(MX53_PAD_EIM_D19, 0x46C, 0x124, 6, 0x000, 0), /* MX53_PAD_EIM_D19__UART1_CTS */
686 IMX_PIN_REG(MX53_PAD_EIM_D19, 0x46C, 0x124, 7, 0x8A4, 0), /* MX53_PAD_EIM_D19__USBOH3_USBH2_OC */
687 IMX_PIN_REG(MX53_PAD_EIM_D20, 0x470, 0x128, 0, 0x000, 0), /* MX53_PAD_EIM_D20__EMI_WEIM_D_20 */
688 IMX_PIN_REG(MX53_PAD_EIM_D20, 0x470, 0x128, 1, 0x000, 0), /* MX53_PAD_EIM_D20__GPIO3_20 */
689 IMX_PIN_REG(MX53_PAD_EIM_D20, 0x470, 0x128, 2, 0x000, 0), /* MX53_PAD_EIM_D20__IPU_DI0_PIN16 */
690 IMX_PIN_REG(MX53_PAD_EIM_D20, 0x470, 0x128, 3, 0x000, 0), /* MX53_PAD_EIM_D20__IPU_SER_DISP0_CS */
691 IMX_PIN_REG(MX53_PAD_EIM_D20, 0x470, 0x128, 4, 0x78C, 1), /* MX53_PAD_EIM_D20__CSPI_SS0 */
692 IMX_PIN_REG(MX53_PAD_EIM_D20, 0x470, 0x128, 5, 0x000, 0), /* MX53_PAD_EIM_D20__EPIT2_EPITO */
693 IMX_PIN_REG(MX53_PAD_EIM_D20, 0x470, 0x128, 6, 0x874, 1), /* MX53_PAD_EIM_D20__UART1_RTS */
694 IMX_PIN_REG(MX53_PAD_EIM_D20, 0x470, 0x128, 7, 0x000, 0), /* MX53_PAD_EIM_D20__USBOH3_USBH2_PWR */
695 IMX_PIN_REG(MX53_PAD_EIM_D21, 0x474, 0x12C, 0, 0x000, 0), /* MX53_PAD_EIM_D21__EMI_WEIM_D_21 */
696 IMX_PIN_REG(MX53_PAD_EIM_D21, 0x474, 0x12C, 1, 0x000, 0), /* MX53_PAD_EIM_D21__GPIO3_21 */
697 IMX_PIN_REG(MX53_PAD_EIM_D21, 0x474, 0x12C, 2, 0x000, 0), /* MX53_PAD_EIM_D21__IPU_DI0_PIN17 */
698 IMX_PIN_REG(MX53_PAD_EIM_D21, 0x474, 0x12C, 3, 0x000, 0), /* MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK */
699 IMX_PIN_REG(MX53_PAD_EIM_D21, 0x474, 0x12C, 4, 0x780, 1), /* MX53_PAD_EIM_D21__CSPI_SCLK */
700 IMX_PIN_REG(MX53_PAD_EIM_D21, 0x474, 0x12C, 5, 0x814, 1), /* MX53_PAD_EIM_D21__I2C1_SCL */
701 IMX_PIN_REG(MX53_PAD_EIM_D21, 0x474, 0x12C, 6, 0x89C, 1), /* MX53_PAD_EIM_D21__USBOH3_USBOTG_OC */
702 IMX_PIN_REG(MX53_PAD_EIM_D22, 0x478, 0x130, 0, 0x000, 0), /* MX53_PAD_EIM_D22__EMI_WEIM_D_22 */
703 IMX_PIN_REG(MX53_PAD_EIM_D22, 0x478, 0x130, 1, 0x000, 0), /* MX53_PAD_EIM_D22__GPIO3_22 */
704 IMX_PIN_REG(MX53_PAD_EIM_D22, 0x478, 0x130, 2, 0x000, 0), /* MX53_PAD_EIM_D22__IPU_DI0_PIN1 */
705 IMX_PIN_REG(MX53_PAD_EIM_D22, 0x478, 0x130, 3, 0x82C, 0), /* MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN */
706 IMX_PIN_REG(MX53_PAD_EIM_D22, 0x478, 0x130, 4, 0x784, 1), /* MX53_PAD_EIM_D22__CSPI_MISO */
707 IMX_PIN_REG(MX53_PAD_EIM_D22, 0x478, 0x130, 6, 0x000, 0), /* MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR */
708 IMX_PIN_REG(MX53_PAD_EIM_D23, 0x47C, 0x134, 0, 0x000, 0), /* MX53_PAD_EIM_D23__EMI_WEIM_D_23 */
709 IMX_PIN_REG(MX53_PAD_EIM_D23, 0x47C, 0x134, 1, 0x000, 0), /* MX53_PAD_EIM_D23__GPIO3_23 */
710 IMX_PIN_REG(MX53_PAD_EIM_D23, 0x47C, 0x134, 2, 0x000, 0), /* MX53_PAD_EIM_D23__UART3_CTS */
711 IMX_PIN_REG(MX53_PAD_EIM_D23, 0x47C, 0x134, 3, 0x000, 0), /* MX53_PAD_EIM_D23__UART1_DCD */
712 IMX_PIN_REG(MX53_PAD_EIM_D23, 0x47C, 0x134, 4, 0x000, 0), /* MX53_PAD_EIM_D23__IPU_DI0_D0_CS */
713 IMX_PIN_REG(MX53_PAD_EIM_D23, 0x47C, 0x134, 5, 0x000, 0), /* MX53_PAD_EIM_D23__IPU_DI1_PIN2 */
714 IMX_PIN_REG(MX53_PAD_EIM_D23, 0x47C, 0x134, 6, 0x834, 0), /* MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN */
715 IMX_PIN_REG(MX53_PAD_EIM_D23, 0x47C, 0x134, 7, 0x000, 0), /* MX53_PAD_EIM_D23__IPU_DI1_PIN14 */
716 IMX_PIN_REG(MX53_PAD_EIM_EB3, 0x480, 0x138, 0, 0x000, 0), /* MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 */
717 IMX_PIN_REG(MX53_PAD_EIM_EB3, 0x480, 0x138, 1, 0x000, 0), /* MX53_PAD_EIM_EB3__GPIO2_31 */
718 IMX_PIN_REG(MX53_PAD_EIM_EB3, 0x480, 0x138, 2, 0x884, 1), /* MX53_PAD_EIM_EB3__UART3_RTS */
719 IMX_PIN_REG(MX53_PAD_EIM_EB3, 0x480, 0x138, 3, 0x000, 0), /* MX53_PAD_EIM_EB3__UART1_RI */
720 IMX_PIN_REG(MX53_PAD_EIM_EB3, 0x480, 0x138, 5, 0x000, 0), /* MX53_PAD_EIM_EB3__IPU_DI1_PIN3 */
721 IMX_PIN_REG(MX53_PAD_EIM_EB3, 0x480, 0x138, 6, 0x838, 0), /* MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC */
722 IMX_PIN_REG(MX53_PAD_EIM_EB3, 0x480, 0x138, 7, 0x000, 0), /* MX53_PAD_EIM_EB3__IPU_DI1_PIN16 */
723 IMX_PIN_REG(MX53_PAD_EIM_D24, 0x484, 0x13C, 0, 0x000, 0), /* MX53_PAD_EIM_D24__EMI_WEIM_D_24 */
724 IMX_PIN_REG(MX53_PAD_EIM_D24, 0x484, 0x13C, 1, 0x000, 0), /* MX53_PAD_EIM_D24__GPIO3_24 */
725 IMX_PIN_REG(MX53_PAD_EIM_D24, 0x484, 0x13C, 2, 0x000, 0), /* MX53_PAD_EIM_D24__UART3_TXD_MUX */
726 IMX_PIN_REG(MX53_PAD_EIM_D24, 0x484, 0x13C, 3, 0x7B0, 1), /* MX53_PAD_EIM_D24__ECSPI1_SS2 */
727 IMX_PIN_REG(MX53_PAD_EIM_D24, 0x484, 0x13C, 4, 0x794, 1), /* MX53_PAD_EIM_D24__CSPI_SS2 */
728 IMX_PIN_REG(MX53_PAD_EIM_D24, 0x484, 0x13C, 5, 0x754, 1), /* MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS */
729 IMX_PIN_REG(MX53_PAD_EIM_D24, 0x484, 0x13C, 6, 0x000, 0), /* MX53_PAD_EIM_D24__ECSPI2_SS2 */
730 IMX_PIN_REG(MX53_PAD_EIM_D24, 0x484, 0x13C, 7, 0x000, 0), /* MX53_PAD_EIM_D24__UART1_DTR */
731 IMX_PIN_REG(MX53_PAD_EIM_D25, 0x488, 0x140, 0, 0x000, 0), /* MX53_PAD_EIM_D25__EMI_WEIM_D_25 */
732 IMX_PIN_REG(MX53_PAD_EIM_D25, 0x488, 0x140, 1, 0x000, 0), /* MX53_PAD_EIM_D25__GPIO3_25 */
733 IMX_PIN_REG(MX53_PAD_EIM_D25, 0x488, 0x140, 2, 0x888, 1), /* MX53_PAD_EIM_D25__UART3_RXD_MUX */
734 IMX_PIN_REG(MX53_PAD_EIM_D25, 0x488, 0x140, 3, 0x7B4, 1), /* MX53_PAD_EIM_D25__ECSPI1_SS3 */
735 IMX_PIN_REG(MX53_PAD_EIM_D25, 0x488, 0x140, 4, 0x798, 1), /* MX53_PAD_EIM_D25__CSPI_SS3 */
736 IMX_PIN_REG(MX53_PAD_EIM_D25, 0x488, 0x140, 5, 0x750, 1), /* MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC */
737 IMX_PIN_REG(MX53_PAD_EIM_D25, 0x488, 0x140, 6, 0x000, 0), /* MX53_PAD_EIM_D25__ECSPI2_SS3 */
738 IMX_PIN_REG(MX53_PAD_EIM_D25, 0x488, 0x140, 7, 0x000, 0), /* MX53_PAD_EIM_D25__UART1_DSR */
739 IMX_PIN_REG(MX53_PAD_EIM_D26, 0x48C, 0x144, 0, 0x000, 0), /* MX53_PAD_EIM_D26__EMI_WEIM_D_26 */
740 IMX_PIN_REG(MX53_PAD_EIM_D26, 0x48C, 0x144, 1, 0x000, 0), /* MX53_PAD_EIM_D26__GPIO3_26 */
741 IMX_PIN_REG(MX53_PAD_EIM_D26, 0x48C, 0x144, 2, 0x000, 0), /* MX53_PAD_EIM_D26__UART2_TXD_MUX */
742 IMX_PIN_REG(MX53_PAD_EIM_D26, 0x48C, 0x144, 3, 0x80C, 0), /* MX53_PAD_EIM_D26__FIRI_RXD */
743 IMX_PIN_REG(MX53_PAD_EIM_D26, 0x48C, 0x144, 4, 0x000, 0), /* MX53_PAD_EIM_D26__IPU_CSI0_D_1 */
744 IMX_PIN_REG(MX53_PAD_EIM_D26, 0x48C, 0x144, 5, 0x000, 0), /* MX53_PAD_EIM_D26__IPU_DI1_PIN11 */
745 IMX_PIN_REG(MX53_PAD_EIM_D26, 0x48C, 0x144, 6, 0x000, 0), /* MX53_PAD_EIM_D26__IPU_SISG_2 */
746 IMX_PIN_REG(MX53_PAD_EIM_D26, 0x48C, 0x144, 7, 0x000, 0), /* MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 */
747 IMX_PIN_REG(MX53_PAD_EIM_D27, 0x490, 0x148, 0, 0x000, 0), /* MX53_PAD_EIM_D27__EMI_WEIM_D_27 */
748 IMX_PIN_REG(MX53_PAD_EIM_D27, 0x490, 0x148, 1, 0x000, 0), /* MX53_PAD_EIM_D27__GPIO3_27 */
749 IMX_PIN_REG(MX53_PAD_EIM_D27, 0x490, 0x148, 2, 0x880, 1), /* MX53_PAD_EIM_D27__UART2_RXD_MUX */
750 IMX_PIN_REG(MX53_PAD_EIM_D27, 0x490, 0x148, 3, 0x000, 0), /* MX53_PAD_EIM_D27__FIRI_TXD */
751 IMX_PIN_REG(MX53_PAD_EIM_D27, 0x490, 0x148, 4, 0x000, 0), /* MX53_PAD_EIM_D27__IPU_CSI0_D_0 */
752 IMX_PIN_REG(MX53_PAD_EIM_D27, 0x490, 0x148, 5, 0x000, 0), /* MX53_PAD_EIM_D27__IPU_DI1_PIN13 */
753 IMX_PIN_REG(MX53_PAD_EIM_D27, 0x490, 0x148, 6, 0x000, 0), /* MX53_PAD_EIM_D27__IPU_SISG_3 */
754 IMX_PIN_REG(MX53_PAD_EIM_D27, 0x490, 0x148, 7, 0x000, 0), /* MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 */
755 IMX_PIN_REG(MX53_PAD_EIM_D28, 0x494, 0x14C, 0, 0x000, 0), /* MX53_PAD_EIM_D28__EMI_WEIM_D_28 */
756 IMX_PIN_REG(MX53_PAD_EIM_D28, 0x494, 0x14C, 1, 0x000, 0), /* MX53_PAD_EIM_D28__GPIO3_28 */
757 IMX_PIN_REG(MX53_PAD_EIM_D28, 0x494, 0x14C, 2, 0x000, 0), /* MX53_PAD_EIM_D28__UART2_CTS */
758 IMX_PIN_REG(MX53_PAD_EIM_D28, 0x494, 0x14C, 3, 0x82C, 1), /* MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO */
759 IMX_PIN_REG(MX53_PAD_EIM_D28, 0x494, 0x14C, 4, 0x788, 1), /* MX53_PAD_EIM_D28__CSPI_MOSI */
760 IMX_PIN_REG(MX53_PAD_EIM_D28, 0x494, 0x14C, 5, 0x818, 1), /* MX53_PAD_EIM_D28__I2C1_SDA */
761 IMX_PIN_REG(MX53_PAD_EIM_D28, 0x494, 0x14C, 6, 0x000, 0), /* MX53_PAD_EIM_D28__IPU_EXT_TRIG */
762 IMX_PIN_REG(MX53_PAD_EIM_D28, 0x494, 0x14C, 7, 0x000, 0), /* MX53_PAD_EIM_D28__IPU_DI0_PIN13 */
763 IMX_PIN_REG(MX53_PAD_EIM_D29, 0x498, 0x150, 0, 0x000, 0), /* MX53_PAD_EIM_D29__EMI_WEIM_D_29 */
764 IMX_PIN_REG(MX53_PAD_EIM_D29, 0x498, 0x150, 1, 0x000, 0), /* MX53_PAD_EIM_D29__GPIO3_29 */
765 IMX_PIN_REG(MX53_PAD_EIM_D29, 0x498, 0x150, 2, 0x87C, 1), /* MX53_PAD_EIM_D29__UART2_RTS */
766 IMX_PIN_REG(MX53_PAD_EIM_D29, 0x498, 0x150, 3, 0x000, 0), /* MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS */
767 IMX_PIN_REG(MX53_PAD_EIM_D29, 0x498, 0x150, 4, 0x78C, 2), /* MX53_PAD_EIM_D29__CSPI_SS0 */
768 IMX_PIN_REG(MX53_PAD_EIM_D29, 0x498, 0x150, 5, 0x000, 0), /* MX53_PAD_EIM_D29__IPU_DI1_PIN15 */
769 IMX_PIN_REG(MX53_PAD_EIM_D29, 0x498, 0x150, 6, 0x83C, 0), /* MX53_PAD_EIM_D29__IPU_CSI1_VSYNC */
770 IMX_PIN_REG(MX53_PAD_EIM_D29, 0x498, 0x150, 7, 0x000, 0), /* MX53_PAD_EIM_D29__IPU_DI0_PIN14 */
771 IMX_PIN_REG(MX53_PAD_EIM_D30, 0x49C, 0x154, 0, 0x000, 0), /* MX53_PAD_EIM_D30__EMI_WEIM_D_30 */
772 IMX_PIN_REG(MX53_PAD_EIM_D30, 0x49C, 0x154, 1, 0x000, 0), /* MX53_PAD_EIM_D30__GPIO3_30 */
773 IMX_PIN_REG(MX53_PAD_EIM_D30, 0x49C, 0x154, 2, 0x000, 0), /* MX53_PAD_EIM_D30__UART3_CTS */
774 IMX_PIN_REG(MX53_PAD_EIM_D30, 0x49C, 0x154, 3, 0x000, 0), /* MX53_PAD_EIM_D30__IPU_CSI0_D_3 */
775 IMX_PIN_REG(MX53_PAD_EIM_D30, 0x49C, 0x154, 4, 0x000, 0), /* MX53_PAD_EIM_D30__IPU_DI0_PIN11 */
776 IMX_PIN_REG(MX53_PAD_EIM_D30, 0x49C, 0x154, 5, 0x000, 0), /* MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 */
777 IMX_PIN_REG(MX53_PAD_EIM_D30, 0x49C, 0x154, 6, 0x8A0, 0), /* MX53_PAD_EIM_D30__USBOH3_USBH1_OC */
778 IMX_PIN_REG(MX53_PAD_EIM_D30, 0x49C, 0x154, 7, 0x8A4, 1), /* MX53_PAD_EIM_D30__USBOH3_USBH2_OC */
779 IMX_PIN_REG(MX53_PAD_EIM_D31, 0x4A0, 0x158, 0, 0x000, 0), /* MX53_PAD_EIM_D31__EMI_WEIM_D_31 */
780 IMX_PIN_REG(MX53_PAD_EIM_D31, 0x4A0, 0x158, 1, 0x000, 0), /* MX53_PAD_EIM_D31__GPIO3_31 */
781 IMX_PIN_REG(MX53_PAD_EIM_D31, 0x4A0, 0x158, 2, 0x884, 3), /* MX53_PAD_EIM_D31__UART3_RTS */
782 IMX_PIN_REG(MX53_PAD_EIM_D31, 0x4A0, 0x158, 3, 0x000, 0), /* MX53_PAD_EIM_D31__IPU_CSI0_D_2 */
783 IMX_PIN_REG(MX53_PAD_EIM_D31, 0x4A0, 0x158, 4, 0x000, 0), /* MX53_PAD_EIM_D31__IPU_DI0_PIN12 */
784 IMX_PIN_REG(MX53_PAD_EIM_D31, 0x4A0, 0x158, 5, 0x000, 0), /* MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 */
785 IMX_PIN_REG(MX53_PAD_EIM_D31, 0x4A0, 0x158, 6, 0x000, 0), /* MX53_PAD_EIM_D31__USBOH3_USBH1_PWR */
786 IMX_PIN_REG(MX53_PAD_EIM_D31, 0x4A0, 0x158, 7, 0x000, 0), /* MX53_PAD_EIM_D31__USBOH3_USBH2_PWR */
787 IMX_PIN_REG(MX53_PAD_EIM_A24, 0x4A8, 0x15C, 0, 0x000, 0), /* MX53_PAD_EIM_A24__EMI_WEIM_A_24 */
788 IMX_PIN_REG(MX53_PAD_EIM_A24, 0x4A8, 0x15C, 1, 0x000, 0), /* MX53_PAD_EIM_A24__GPIO5_4 */
789 IMX_PIN_REG(MX53_PAD_EIM_A24, 0x4A8, 0x15C, 2, 0x000, 0), /* MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 */
790 IMX_PIN_REG(MX53_PAD_EIM_A24, 0x4A8, 0x15C, 3, 0x000, 0), /* MX53_PAD_EIM_A24__IPU_CSI1_D_19 */
791 IMX_PIN_REG(MX53_PAD_EIM_A24, 0x4A8, 0x15C, 6, 0x000, 0), /* MX53_PAD_EIM_A24__IPU_SISG_2 */
792 IMX_PIN_REG(MX53_PAD_EIM_A24, 0x4A8, 0x15C, 7, 0x000, 0), /* MX53_PAD_EIM_A24__USBPHY2_BVALID */
793 IMX_PIN_REG(MX53_PAD_EIM_A23, 0x4AC, 0x160, 0, 0x000, 0), /* MX53_PAD_EIM_A23__EMI_WEIM_A_23 */
794 IMX_PIN_REG(MX53_PAD_EIM_A23, 0x4AC, 0x160, 1, 0x000, 0), /* MX53_PAD_EIM_A23__GPIO6_6 */
795 IMX_PIN_REG(MX53_PAD_EIM_A23, 0x4AC, 0x160, 2, 0x000, 0), /* MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 */
796 IMX_PIN_REG(MX53_PAD_EIM_A23, 0x4AC, 0x160, 3, 0x000, 0), /* MX53_PAD_EIM_A23__IPU_CSI1_D_18 */
797 IMX_PIN_REG(MX53_PAD_EIM_A23, 0x4AC, 0x160, 6, 0x000, 0), /* MX53_PAD_EIM_A23__IPU_SISG_3 */
798 IMX_PIN_REG(MX53_PAD_EIM_A23, 0x4AC, 0x160, 7, 0x000, 0), /* MX53_PAD_EIM_A23__USBPHY2_ENDSESSION */
799 IMX_PIN_REG(MX53_PAD_EIM_A22, 0x4B0, 0x164, 0, 0x000, 0), /* MX53_PAD_EIM_A22__EMI_WEIM_A_22 */
800 IMX_PIN_REG(MX53_PAD_EIM_A22, 0x4B0, 0x164, 1, 0x000, 0), /* MX53_PAD_EIM_A22__GPIO2_16 */
801 IMX_PIN_REG(MX53_PAD_EIM_A22, 0x4B0, 0x164, 2, 0x000, 0), /* MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 */
802 IMX_PIN_REG(MX53_PAD_EIM_A22, 0x4B0, 0x164, 3, 0x000, 0), /* MX53_PAD_EIM_A22__IPU_CSI1_D_17 */
803 IMX_PIN_REG(MX53_PAD_EIM_A22, 0x4B0, 0x164, 7, 0x000, 0), /* MX53_PAD_EIM_A22__SRC_BT_CFG1_7 */
804 IMX_PIN_REG(MX53_PAD_EIM_A21, 0x4B4, 0x168, 0, 0x000, 0), /* MX53_PAD_EIM_A21__EMI_WEIM_A_21 */
805 IMX_PIN_REG(MX53_PAD_EIM_A21, 0x4B4, 0x168, 1, 0x000, 0), /* MX53_PAD_EIM_A21__GPIO2_17 */
806 IMX_PIN_REG(MX53_PAD_EIM_A21, 0x4B4, 0x168, 2, 0x000, 0), /* MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 */
807 IMX_PIN_REG(MX53_PAD_EIM_A21, 0x4B4, 0x168, 3, 0x000, 0), /* MX53_PAD_EIM_A21__IPU_CSI1_D_16 */
808 IMX_PIN_REG(MX53_PAD_EIM_A21, 0x4B4, 0x168, 7, 0x000, 0), /* MX53_PAD_EIM_A21__SRC_BT_CFG1_6 */
809 IMX_PIN_REG(MX53_PAD_EIM_A20, 0x4B8, 0x16C, 0, 0x000, 0), /* MX53_PAD_EIM_A20__EMI_WEIM_A_20 */
810 IMX_PIN_REG(MX53_PAD_EIM_A20, 0x4B8, 0x16C, 1, 0x000, 0), /* MX53_PAD_EIM_A20__GPIO2_18 */
811 IMX_PIN_REG(MX53_PAD_EIM_A20, 0x4B8, 0x16C, 2, 0x000, 0), /* MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 */
812 IMX_PIN_REG(MX53_PAD_EIM_A20, 0x4B8, 0x16C, 3, 0x000, 0), /* MX53_PAD_EIM_A20__IPU_CSI1_D_15 */
813 IMX_PIN_REG(MX53_PAD_EIM_A20, 0x4B8, 0x16C, 7, 0x000, 0), /* MX53_PAD_EIM_A20__SRC_BT_CFG1_5 */
814 IMX_PIN_REG(MX53_PAD_EIM_A19, 0x4BC, 0x170, 0, 0x000, 0), /* MX53_PAD_EIM_A19__EMI_WEIM_A_19 */
815 IMX_PIN_REG(MX53_PAD_EIM_A19, 0x4BC, 0x170, 1, 0x000, 0), /* MX53_PAD_EIM_A19__GPIO2_19 */
816 IMX_PIN_REG(MX53_PAD_EIM_A19, 0x4BC, 0x170, 2, 0x000, 0), /* MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 */
817 IMX_PIN_REG(MX53_PAD_EIM_A19, 0x4BC, 0x170, 3, 0x000, 0), /* MX53_PAD_EIM_A19__IPU_CSI1_D_14 */
818 IMX_PIN_REG(MX53_PAD_EIM_A19, 0x4BC, 0x170, 7, 0x000, 0), /* MX53_PAD_EIM_A19__SRC_BT_CFG1_4 */
819 IMX_PIN_REG(MX53_PAD_EIM_A18, 0x4C0, 0x174, 0, 0x000, 0), /* MX53_PAD_EIM_A18__EMI_WEIM_A_18 */
820 IMX_PIN_REG(MX53_PAD_EIM_A18, 0x4C0, 0x174, 1, 0x000, 0), /* MX53_PAD_EIM_A18__GPIO2_20 */
821 IMX_PIN_REG(MX53_PAD_EIM_A18, 0x4C0, 0x174, 2, 0x000, 0), /* MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 */
822 IMX_PIN_REG(MX53_PAD_EIM_A18, 0x4C0, 0x174, 3, 0x000, 0), /* MX53_PAD_EIM_A18__IPU_CSI1_D_13 */
823 IMX_PIN_REG(MX53_PAD_EIM_A18, 0x4C0, 0x174, 7, 0x000, 0), /* MX53_PAD_EIM_A18__SRC_BT_CFG1_3 */
824 IMX_PIN_REG(MX53_PAD_EIM_A17, 0x4C4, 0x178, 0, 0x000, 0), /* MX53_PAD_EIM_A17__EMI_WEIM_A_17 */
825 IMX_PIN_REG(MX53_PAD_EIM_A17, 0x4C4, 0x178, 1, 0x000, 0), /* MX53_PAD_EIM_A17__GPIO2_21 */
826 IMX_PIN_REG(MX53_PAD_EIM_A17, 0x4C4, 0x178, 2, 0x000, 0), /* MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 */
827 IMX_PIN_REG(MX53_PAD_EIM_A17, 0x4C4, 0x178, 3, 0x000, 0), /* MX53_PAD_EIM_A17__IPU_CSI1_D_12 */
828 IMX_PIN_REG(MX53_PAD_EIM_A17, 0x4C4, 0x178, 7, 0x000, 0), /* MX53_PAD_EIM_A17__SRC_BT_CFG1_2 */
829 IMX_PIN_REG(MX53_PAD_EIM_A16, 0x4C8, 0x17C, 0, 0x000, 0), /* MX53_PAD_EIM_A16__EMI_WEIM_A_16 */
830 IMX_PIN_REG(MX53_PAD_EIM_A16, 0x4C8, 0x17C, 1, 0x000, 0), /* MX53_PAD_EIM_A16__GPIO2_22 */
831 IMX_PIN_REG(MX53_PAD_EIM_A16, 0x4C8, 0x17C, 2, 0x000, 0), /* MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK */
832 IMX_PIN_REG(MX53_PAD_EIM_A16, 0x4C8, 0x17C, 3, 0x000, 0), /* MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK */
833 IMX_PIN_REG(MX53_PAD_EIM_A16, 0x4C8, 0x17C, 7, 0x000, 0), /* MX53_PAD_EIM_A16__SRC_BT_CFG1_1 */
834 IMX_PIN_REG(MX53_PAD_EIM_CS0, 0x4CC, 0x180, 0, 0x000, 0), /* MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 */
835 IMX_PIN_REG(MX53_PAD_EIM_CS0, 0x4CC, 0x180, 1, 0x000, 0), /* MX53_PAD_EIM_CS0__GPIO2_23 */
836 IMX_PIN_REG(MX53_PAD_EIM_CS0, 0x4CC, 0x180, 2, 0x7B8, 2), /* MX53_PAD_EIM_CS0__ECSPI2_SCLK */
837 IMX_PIN_REG(MX53_PAD_EIM_CS0, 0x4CC, 0x180, 3, 0x000, 0), /* MX53_PAD_EIM_CS0__IPU_DI1_PIN5 */
838 IMX_PIN_REG(MX53_PAD_EIM_CS1, 0x4D0, 0x184, 0, 0x000, 0), /* MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 */
839 IMX_PIN_REG(MX53_PAD_EIM_CS1, 0x4D0, 0x184, 1, 0x000, 0), /* MX53_PAD_EIM_CS1__GPIO2_24 */
840 IMX_PIN_REG(MX53_PAD_EIM_CS1, 0x4D0, 0x184, 2, 0x7C0, 2), /* MX53_PAD_EIM_CS1__ECSPI2_MOSI */
841 IMX_PIN_REG(MX53_PAD_EIM_CS1, 0x4D0, 0x184, 3, 0x000, 0), /* MX53_PAD_EIM_CS1__IPU_DI1_PIN6 */
842 IMX_PIN_REG(MX53_PAD_EIM_OE, 0x4D4, 0x188, 0, 0x000, 0), /* MX53_PAD_EIM_OE__EMI_WEIM_OE */
843 IMX_PIN_REG(MX53_PAD_EIM_OE, 0x4D4, 0x188, 1, 0x000, 0), /* MX53_PAD_EIM_OE__GPIO2_25 */
844 IMX_PIN_REG(MX53_PAD_EIM_OE, 0x4D4, 0x188, 2, 0x7BC, 2), /* MX53_PAD_EIM_OE__ECSPI2_MISO */
845 IMX_PIN_REG(MX53_PAD_EIM_OE, 0x4D4, 0x188, 3, 0x000, 0), /* MX53_PAD_EIM_OE__IPU_DI1_PIN7 */
846 IMX_PIN_REG(MX53_PAD_EIM_OE, 0x4D4, 0x188, 7, 0x000, 0), /* MX53_PAD_EIM_OE__USBPHY2_IDDIG */
847 IMX_PIN_REG(MX53_PAD_EIM_RW, 0x4D8, 0x18C, 0, 0x000, 0), /* MX53_PAD_EIM_RW__EMI_WEIM_RW */
848 IMX_PIN_REG(MX53_PAD_EIM_RW, 0x4D8, 0x18C, 1, 0x000, 0), /* MX53_PAD_EIM_RW__GPIO2_26 */
849 IMX_PIN_REG(MX53_PAD_EIM_RW, 0x4D8, 0x18C, 2, 0x7C4, 2), /* MX53_PAD_EIM_RW__ECSPI2_SS0 */
850 IMX_PIN_REG(MX53_PAD_EIM_RW, 0x4D8, 0x18C, 3, 0x000, 0), /* MX53_PAD_EIM_RW__IPU_DI1_PIN8 */
851 IMX_PIN_REG(MX53_PAD_EIM_RW, 0x4D8, 0x18C, 7, 0x000, 0), /* MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT */
852 IMX_PIN_REG(MX53_PAD_EIM_LBA, 0x4DC, 0x190, 0, 0x000, 0), /* MX53_PAD_EIM_LBA__EMI_WEIM_LBA */
853 IMX_PIN_REG(MX53_PAD_EIM_LBA, 0x4DC, 0x190, 1, 0x000, 0), /* MX53_PAD_EIM_LBA__GPIO2_27 */
854 IMX_PIN_REG(MX53_PAD_EIM_LBA, 0x4DC, 0x190, 2, 0x7C8, 1), /* MX53_PAD_EIM_LBA__ECSPI2_SS1 */
855 IMX_PIN_REG(MX53_PAD_EIM_LBA, 0x4DC, 0x190, 3, 0x000, 0), /* MX53_PAD_EIM_LBA__IPU_DI1_PIN17 */
856 IMX_PIN_REG(MX53_PAD_EIM_LBA, 0x4DC, 0x190, 7, 0x000, 0), /* MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 */
857 IMX_PIN_REG(MX53_PAD_EIM_EB0, 0x4E4, 0x194, 0, 0x000, 0), /* MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 */
858 IMX_PIN_REG(MX53_PAD_EIM_EB0, 0x4E4, 0x194, 1, 0x000, 0), /* MX53_PAD_EIM_EB0__GPIO2_28 */
859 IMX_PIN_REG(MX53_PAD_EIM_EB0, 0x4E4, 0x194, 3, 0x000, 0), /* MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 */
860 IMX_PIN_REG(MX53_PAD_EIM_EB0, 0x4E4, 0x194, 4, 0x000, 0), /* MX53_PAD_EIM_EB0__IPU_CSI1_D_11 */
861 IMX_PIN_REG(MX53_PAD_EIM_EB0, 0x4E4, 0x194, 5, 0x810, 0), /* MX53_PAD_EIM_EB0__GPC_PMIC_RDY */
862 IMX_PIN_REG(MX53_PAD_EIM_EB0, 0x4E4, 0x194, 7, 0x000, 0), /* MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 */
863 IMX_PIN_REG(MX53_PAD_EIM_EB1, 0x4E8, 0x198, 0, 0x000, 0), /* MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 */
864 IMX_PIN_REG(MX53_PAD_EIM_EB1, 0x4E8, 0x198, 1, 0x000, 0), /* MX53_PAD_EIM_EB1__GPIO2_29 */
865 IMX_PIN_REG(MX53_PAD_EIM_EB1, 0x4E8, 0x198, 3, 0x000, 0), /* MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 */
866 IMX_PIN_REG(MX53_PAD_EIM_EB1, 0x4E8, 0x198, 4, 0x000, 0), /* MX53_PAD_EIM_EB1__IPU_CSI1_D_10 */
867 IMX_PIN_REG(MX53_PAD_EIM_EB1, 0x4E8, 0x198, 7, 0x000, 0), /* MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 */
868 IMX_PIN_REG(MX53_PAD_EIM_DA0, 0x4EC, 0x19C, 0, 0x000, 0), /* MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 */
869 IMX_PIN_REG(MX53_PAD_EIM_DA0, 0x4EC, 0x19C, 1, 0x000, 0), /* MX53_PAD_EIM_DA0__GPIO3_0 */
870 IMX_PIN_REG(MX53_PAD_EIM_DA0, 0x4EC, 0x19C, 3, 0x000, 0), /* MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 */
871 IMX_PIN_REG(MX53_PAD_EIM_DA0, 0x4EC, 0x19C, 4, 0x000, 0), /* MX53_PAD_EIM_DA0__IPU_CSI1_D_9 */
872 IMX_PIN_REG(MX53_PAD_EIM_DA0, 0x4EC, 0x19C, 7, 0x000, 0), /* MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 */
873 IMX_PIN_REG(MX53_PAD_EIM_DA1, 0x4F0, 0x1A0, 0, 0x000, 0), /* MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 */
874 IMX_PIN_REG(MX53_PAD_EIM_DA1, 0x4F0, 0x1A0, 1, 0x000, 0), /* MX53_PAD_EIM_DA1__GPIO3_1 */
875 IMX_PIN_REG(MX53_PAD_EIM_DA1, 0x4F0, 0x1A0, 3, 0x000, 0), /* MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 */
876 IMX_PIN_REG(MX53_PAD_EIM_DA1, 0x4F0, 0x1A0, 4, 0x000, 0), /* MX53_PAD_EIM_DA1__IPU_CSI1_D_8 */
877 IMX_PIN_REG(MX53_PAD_EIM_DA1, 0x4F0, 0x1A0, 7, 0x000, 0), /* MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 */
878 IMX_PIN_REG(MX53_PAD_EIM_DA2, 0x4F4, 0x1A4, 0, 0x000, 0), /* MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 */
879 IMX_PIN_REG(MX53_PAD_EIM_DA2, 0x4F4, 0x1A4, 1, 0x000, 0), /* MX53_PAD_EIM_DA2__GPIO3_2 */
880 IMX_PIN_REG(MX53_PAD_EIM_DA2, 0x4F4, 0x1A4, 3, 0x000, 0), /* MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 */
881 IMX_PIN_REG(MX53_PAD_EIM_DA2, 0x4F4, 0x1A4, 4, 0x000, 0), /* MX53_PAD_EIM_DA2__IPU_CSI1_D_7 */
882 IMX_PIN_REG(MX53_PAD_EIM_DA2, 0x4F4, 0x1A4, 7, 0x000, 0), /* MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 */
883 IMX_PIN_REG(MX53_PAD_EIM_DA3, 0x4F8, 0x1A8, 0, 0x000, 0), /* MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 */
884 IMX_PIN_REG(MX53_PAD_EIM_DA3, 0x4F8, 0x1A8, 1, 0x000, 0), /* MX53_PAD_EIM_DA3__GPIO3_3 */
885 IMX_PIN_REG(MX53_PAD_EIM_DA3, 0x4F8, 0x1A8, 3, 0x000, 0), /* MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 */
886 IMX_PIN_REG(MX53_PAD_EIM_DA3, 0x4F8, 0x1A8, 4, 0x000, 0), /* MX53_PAD_EIM_DA3__IPU_CSI1_D_6 */
887 IMX_PIN_REG(MX53_PAD_EIM_DA3, 0x4F8, 0x1A8, 7, 0x000, 0), /* MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 */
888 IMX_PIN_REG(MX53_PAD_EIM_DA4, 0x4FC, 0x1AC, 0, 0x000, 0), /* MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 */
889 IMX_PIN_REG(MX53_PAD_EIM_DA4, 0x4FC, 0x1AC, 1, 0x000, 0), /* MX53_PAD_EIM_DA4__GPIO3_4 */
890 IMX_PIN_REG(MX53_PAD_EIM_DA4, 0x4FC, 0x1AC, 3, 0x000, 0), /* MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 */
891 IMX_PIN_REG(MX53_PAD_EIM_DA4, 0x4FC, 0x1AC, 4, 0x000, 0), /* MX53_PAD_EIM_DA4__IPU_CSI1_D_5 */
892 IMX_PIN_REG(MX53_PAD_EIM_DA4, 0x4FC, 0x1AC, 7, 0x000, 0), /* MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 */
893 IMX_PIN_REG(MX53_PAD_EIM_DA5, 0x500, 0x1B0, 0, 0x000, 0), /* MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 */
894 IMX_PIN_REG(MX53_PAD_EIM_DA5, 0x500, 0x1B0, 1, 0x000, 0), /* MX53_PAD_EIM_DA5__GPIO3_5 */
895 IMX_PIN_REG(MX53_PAD_EIM_DA5, 0x500, 0x1B0, 3, 0x000, 0), /* MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 */
896 IMX_PIN_REG(MX53_PAD_EIM_DA5, 0x500, 0x1B0, 4, 0x000, 0), /* MX53_PAD_EIM_DA5__IPU_CSI1_D_4 */
897 IMX_PIN_REG(MX53_PAD_EIM_DA5, 0x500, 0x1B0, 7, 0x000, 0), /* MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 */
898 IMX_PIN_REG(MX53_PAD_EIM_DA6, 0x504, 0x1B4, 0, 0x000, 0), /* MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 */
899 IMX_PIN_REG(MX53_PAD_EIM_DA6, 0x504, 0x1B4, 1, 0x000, 0), /* MX53_PAD_EIM_DA6__GPIO3_6 */
900 IMX_PIN_REG(MX53_PAD_EIM_DA6, 0x504, 0x1B4, 3, 0x000, 0), /* MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 */
901 IMX_PIN_REG(MX53_PAD_EIM_DA6, 0x504, 0x1B4, 4, 0x000, 0), /* MX53_PAD_EIM_DA6__IPU_CSI1_D_3 */
902 IMX_PIN_REG(MX53_PAD_EIM_DA6, 0x504, 0x1B4, 7, 0x000, 0), /* MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 */
903 IMX_PIN_REG(MX53_PAD_EIM_DA7, 0x508, 0x1B8, 0, 0x000, 0), /* MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 */
904 IMX_PIN_REG(MX53_PAD_EIM_DA7, 0x508, 0x1B8, 1, 0x000, 0), /* MX53_PAD_EIM_DA7__GPIO3_7 */
905 IMX_PIN_REG(MX53_PAD_EIM_DA7, 0x508, 0x1B8, 3, 0x000, 0), /* MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 */
906 IMX_PIN_REG(MX53_PAD_EIM_DA7, 0x508, 0x1B8, 4, 0x000, 0), /* MX53_PAD_EIM_DA7__IPU_CSI1_D_2 */
907 IMX_PIN_REG(MX53_PAD_EIM_DA7, 0x508, 0x1B8, 7, 0x000, 0), /* MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 */
908 IMX_PIN_REG(MX53_PAD_EIM_DA8, 0x50C, 0x1BC, 0, 0x000, 0), /* MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 */
909 IMX_PIN_REG(MX53_PAD_EIM_DA8, 0x50C, 0x1BC, 1, 0x000, 0), /* MX53_PAD_EIM_DA8__GPIO3_8 */
910 IMX_PIN_REG(MX53_PAD_EIM_DA8, 0x50C, 0x1BC, 3, 0x000, 0), /* MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 */
911 IMX_PIN_REG(MX53_PAD_EIM_DA8, 0x50C, 0x1BC, 4, 0x000, 0), /* MX53_PAD_EIM_DA8__IPU_CSI1_D_1 */
912 IMX_PIN_REG(MX53_PAD_EIM_DA8, 0x50C, 0x1BC, 7, 0x000, 0), /* MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 */
913 IMX_PIN_REG(MX53_PAD_EIM_DA9, 0x510, 0x1C0, 0, 0x000, 0), /* MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 */
914 IMX_PIN_REG(MX53_PAD_EIM_DA9, 0x510, 0x1C0, 1, 0x000, 0), /* MX53_PAD_EIM_DA9__GPIO3_9 */
915 IMX_PIN_REG(MX53_PAD_EIM_DA9, 0x510, 0x1C0, 3, 0x000, 0), /* MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 */
916 IMX_PIN_REG(MX53_PAD_EIM_DA9, 0x510, 0x1C0, 4, 0x000, 0), /* MX53_PAD_EIM_DA9__IPU_CSI1_D_0 */
917 IMX_PIN_REG(MX53_PAD_EIM_DA9, 0x510, 0x1C0, 7, 0x000, 0), /* MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 */
918 IMX_PIN_REG(MX53_PAD_EIM_DA10, 0x514, 0x1C4, 0, 0x000, 0), /* MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 */
919 IMX_PIN_REG(MX53_PAD_EIM_DA10, 0x514, 0x1C4, 1, 0x000, 0), /* MX53_PAD_EIM_DA10__GPIO3_10 */
920 IMX_PIN_REG(MX53_PAD_EIM_DA10, 0x514, 0x1C4, 3, 0x000, 0), /* MX53_PAD_EIM_DA10__IPU_DI1_PIN15 */
921 IMX_PIN_REG(MX53_PAD_EIM_DA10, 0x514, 0x1C4, 4, 0x834, 1), /* MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN */
922 IMX_PIN_REG(MX53_PAD_EIM_DA10, 0x514, 0x1C4, 7, 0x000, 0), /* MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 */
923 IMX_PIN_REG(MX53_PAD_EIM_DA11, 0x518, 0x1C8, 0, 0x000, 0), /* MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 */
924 IMX_PIN_REG(MX53_PAD_EIM_DA11, 0x518, 0x1C8, 1, 0x000, 0), /* MX53_PAD_EIM_DA11__GPIO3_11 */
925 IMX_PIN_REG(MX53_PAD_EIM_DA11, 0x518, 0x1C8, 3, 0x000, 0), /* MX53_PAD_EIM_DA11__IPU_DI1_PIN2 */
926 IMX_PIN_REG(MX53_PAD_EIM_DA11, 0x518, 0x1C8, 4, 0x838, 1), /* MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC */
927 IMX_PIN_REG(MX53_PAD_EIM_DA12, 0x51C, 0x1CC, 0, 0x000, 0), /* MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 */
928 IMX_PIN_REG(MX53_PAD_EIM_DA12, 0x51C, 0x1CC, 1, 0x000, 0), /* MX53_PAD_EIM_DA12__GPIO3_12 */
929 IMX_PIN_REG(MX53_PAD_EIM_DA12, 0x51C, 0x1CC, 3, 0x000, 0), /* MX53_PAD_EIM_DA12__IPU_DI1_PIN3 */
930 IMX_PIN_REG(MX53_PAD_EIM_DA12, 0x51C, 0x1CC, 4, 0x83C, 1), /* MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC */
931 IMX_PIN_REG(MX53_PAD_EIM_DA13, 0x520, 0x1D0, 0, 0x000, 0), /* MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 */
932 IMX_PIN_REG(MX53_PAD_EIM_DA13, 0x520, 0x1D0, 1, 0x000, 0), /* MX53_PAD_EIM_DA13__GPIO3_13 */
933 IMX_PIN_REG(MX53_PAD_EIM_DA13, 0x520, 0x1D0, 3, 0x000, 0), /* MX53_PAD_EIM_DA13__IPU_DI1_D0_CS */
934 IMX_PIN_REG(MX53_PAD_EIM_DA13, 0x520, 0x1D0, 4, 0x76C, 1), /* MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK */
935 IMX_PIN_REG(MX53_PAD_EIM_DA14, 0x524, 0x1D4, 0, 0x000, 0), /* MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 */
936 IMX_PIN_REG(MX53_PAD_EIM_DA14, 0x524, 0x1D4, 1, 0x000, 0), /* MX53_PAD_EIM_DA14__GPIO3_14 */
937 IMX_PIN_REG(MX53_PAD_EIM_DA14, 0x524, 0x1D4, 3, 0x000, 0), /* MX53_PAD_EIM_DA14__IPU_DI1_D1_CS */
938 IMX_PIN_REG(MX53_PAD_EIM_DA14, 0x524, 0x1D4, 4, 0x000, 0), /* MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK */
939 IMX_PIN_REG(MX53_PAD_EIM_DA15, 0x528, 0x1D8, 0, 0x000, 0), /* MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 */
940 IMX_PIN_REG(MX53_PAD_EIM_DA15, 0x528, 0x1D8, 1, 0x000, 0), /* MX53_PAD_EIM_DA15__GPIO3_15 */
941 IMX_PIN_REG(MX53_PAD_EIM_DA15, 0x528, 0x1D8, 3, 0x000, 0), /* MX53_PAD_EIM_DA15__IPU_DI1_PIN1 */
942 IMX_PIN_REG(MX53_PAD_EIM_DA15, 0x528, 0x1D8, 4, 0x000, 0), /* MX53_PAD_EIM_DA15__IPU_DI1_PIN4 */
943 IMX_PIN_REG(MX53_PAD_NANDF_WE_B, 0x52C, 0x1DC, 0, 0x000, 0), /* MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B */
944 IMX_PIN_REG(MX53_PAD_NANDF_WE_B, 0x52C, 0x1DC, 1, 0x000, 0), /* MX53_PAD_NANDF_WE_B__GPIO6_12 */
945 IMX_PIN_REG(MX53_PAD_NANDF_RE_B, 0x530, 0x1E0, 0, 0x000, 0), /* MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B */
946 IMX_PIN_REG(MX53_PAD_NANDF_RE_B, 0x530, 0x1E0, 1, 0x000, 0), /* MX53_PAD_NANDF_RE_B__GPIO6_13 */
947 IMX_PIN_REG(MX53_PAD_EIM_WAIT, 0x534, 0x1E4, 0, 0x000, 0), /* MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT */
948 IMX_PIN_REG(MX53_PAD_EIM_WAIT, 0x534, 0x1E4, 1, 0x000, 0), /* MX53_PAD_EIM_WAIT__GPIO5_0 */
949 IMX_PIN_REG(MX53_PAD_EIM_WAIT, 0x534, 0x1E4, 2, 0x000, 0), /* MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B */
950 IMX_PIN_REG(MX53_PAD_LVDS1_TX3_P, NO_PAD, 0x1EC, 0, 0x000, 0), /* MX53_PAD_LVDS1_TX3_P__GPIO6_22 */
951 IMX_PIN_REG(MX53_PAD_LVDS1_TX3_P, NO_PAD, 0x1EC, 1, 0x000, 0), /* MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 */
952 IMX_PIN_REG(MX53_PAD_LVDS1_TX2_P, NO_PAD, 0x1F0, 0, 0x000, 0), /* MX53_PAD_LVDS1_TX2_P__GPIO6_24 */
953 IMX_PIN_REG(MX53_PAD_LVDS1_TX2_P, NO_PAD, 0x1F0, 1, 0x000, 0), /* MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 */
954 IMX_PIN_REG(MX53_PAD_LVDS1_CLK_P, NO_PAD, 0x1F4, 0, 0x000, 0), /* MX53_PAD_LVDS1_CLK_P__GPIO6_26 */
955 IMX_PIN_REG(MX53_PAD_LVDS1_CLK_P, NO_PAD, 0x1F4, 1, 0x000, 0), /* MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK */
956 IMX_PIN_REG(MX53_PAD_LVDS1_TX1_P, NO_PAD, 0x1F8, 0, 0x000, 0), /* MX53_PAD_LVDS1_TX1_P__GPIO6_28 */
957 IMX_PIN_REG(MX53_PAD_LVDS1_TX1_P, NO_PAD, 0x1F8, 1, 0x000, 0), /* MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 */
958 IMX_PIN_REG(MX53_PAD_LVDS1_TX0_P, NO_PAD, 0x1FC, 0, 0x000, 0), /* MX53_PAD_LVDS1_TX0_P__GPIO6_30 */
959 IMX_PIN_REG(MX53_PAD_LVDS1_TX0_P, NO_PAD, 0x1FC, 1, 0x000, 0), /* MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 */
960 IMX_PIN_REG(MX53_PAD_LVDS0_TX3_P, NO_PAD, 0x200, 0, 0x000, 0), /* MX53_PAD_LVDS0_TX3_P__GPIO7_22 */
961 IMX_PIN_REG(MX53_PAD_LVDS0_TX3_P, NO_PAD, 0x200, 1, 0x000, 0), /* MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 */
962 IMX_PIN_REG(MX53_PAD_LVDS0_CLK_P, NO_PAD, 0x204, 0, 0x000, 0), /* MX53_PAD_LVDS0_CLK_P__GPIO7_24 */
963 IMX_PIN_REG(MX53_PAD_LVDS0_CLK_P, NO_PAD, 0x204, 1, 0x000, 0), /* MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK */
964 IMX_PIN_REG(MX53_PAD_LVDS0_TX2_P, NO_PAD, 0x208, 0, 0x000, 0), /* MX53_PAD_LVDS0_TX2_P__GPIO7_26 */
965 IMX_PIN_REG(MX53_PAD_LVDS0_TX2_P, NO_PAD, 0x208, 1, 0x000, 0), /* MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 */
966 IMX_PIN_REG(MX53_PAD_LVDS0_TX1_P, NO_PAD, 0x20C, 0, 0x000, 0), /* MX53_PAD_LVDS0_TX1_P__GPIO7_28 */
967 IMX_PIN_REG(MX53_PAD_LVDS0_TX1_P, NO_PAD, 0x20C, 1, 0x000, 0), /* MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 */
968 IMX_PIN_REG(MX53_PAD_LVDS0_TX0_P, NO_PAD, 0x210, 0, 0x000, 0), /* MX53_PAD_LVDS0_TX0_P__GPIO7_30 */
969 IMX_PIN_REG(MX53_PAD_LVDS0_TX0_P, NO_PAD, 0x210, 1, 0x000, 0), /* MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 */
970 IMX_PIN_REG(MX53_PAD_GPIO_10, 0x540, 0x214, 0, 0x000, 0), /* MX53_PAD_GPIO_10__GPIO4_0 */
971 IMX_PIN_REG(MX53_PAD_GPIO_10, 0x540, 0x214, 1, 0x000, 0), /* MX53_PAD_GPIO_10__OSC32k_32K_OUT */
972 IMX_PIN_REG(MX53_PAD_GPIO_11, 0x544, 0x218, 0, 0x000, 0), /* MX53_PAD_GPIO_11__GPIO4_1 */
973 IMX_PIN_REG(MX53_PAD_GPIO_12, 0x548, 0x21C, 0, 0x000, 0), /* MX53_PAD_GPIO_12__GPIO4_2 */
974 IMX_PIN_REG(MX53_PAD_GPIO_13, 0x54C, 0x220, 0, 0x000, 0), /* MX53_PAD_GPIO_13__GPIO4_3 */
975 IMX_PIN_REG(MX53_PAD_GPIO_14, 0x550, 0x224, 0, 0x000, 0), /* MX53_PAD_GPIO_14__GPIO4_4 */
976 IMX_PIN_REG(MX53_PAD_NANDF_CLE, 0x5A0, 0x228, 0, 0x000, 0), /* MX53_PAD_NANDF_CLE__EMI_NANDF_CLE */
977 IMX_PIN_REG(MX53_PAD_NANDF_CLE, 0x5A0, 0x228, 1, 0x000, 0), /* MX53_PAD_NANDF_CLE__GPIO6_7 */
978 IMX_PIN_REG(MX53_PAD_NANDF_CLE, 0x5A0, 0x228, 7, 0x000, 0), /* MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 */
979 IMX_PIN_REG(MX53_PAD_NANDF_ALE, 0x5A4, 0x22C, 0, 0x000, 0), /* MX53_PAD_NANDF_ALE__EMI_NANDF_ALE */
980 IMX_PIN_REG(MX53_PAD_NANDF_ALE, 0x5A4, 0x22C, 1, 0x000, 0), /* MX53_PAD_NANDF_ALE__GPIO6_8 */
981 IMX_PIN_REG(MX53_PAD_NANDF_ALE, 0x5A4, 0x22C, 7, 0x000, 0), /* MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 */
982 IMX_PIN_REG(MX53_PAD_NANDF_WP_B, 0x5A8, 0x230, 0, 0x000, 0), /* MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B */
983 IMX_PIN_REG(MX53_PAD_NANDF_WP_B, 0x5A8, 0x230, 1, 0x000, 0), /* MX53_PAD_NANDF_WP_B__GPIO6_9 */
984 IMX_PIN_REG(MX53_PAD_NANDF_WP_B, 0x5A8, 0x230, 7, 0x000, 0), /* MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 */
985 IMX_PIN_REG(MX53_PAD_NANDF_RB0, 0x5AC, 0x234, 0, 0x000, 0), /* MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 */
986 IMX_PIN_REG(MX53_PAD_NANDF_RB0, 0x5AC, 0x234, 1, 0x000, 0), /* MX53_PAD_NANDF_RB0__GPIO6_10 */
987 IMX_PIN_REG(MX53_PAD_NANDF_RB0, 0x5AC, 0x234, 7, 0x000, 0), /* MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 */
988 IMX_PIN_REG(MX53_PAD_NANDF_CS0, 0x5B0, 0x238, 0, 0x000, 0), /* MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 */
989 IMX_PIN_REG(MX53_PAD_NANDF_CS0, 0x5B0, 0x238, 1, 0x000, 0), /* MX53_PAD_NANDF_CS0__GPIO6_11 */
990 IMX_PIN_REG(MX53_PAD_NANDF_CS0, 0x5B0, 0x238, 7, 0x000, 0), /* MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 */
991 IMX_PIN_REG(MX53_PAD_NANDF_CS1, 0x5B4, 0x23C, 0, 0x000, 0), /* MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 */
992 IMX_PIN_REG(MX53_PAD_NANDF_CS1, 0x5B4, 0x23C, 1, 0x000, 0), /* MX53_PAD_NANDF_CS1__GPIO6_14 */
993 IMX_PIN_REG(MX53_PAD_NANDF_CS1, 0x5B4, 0x23C, 6, 0x858, 0), /* MX53_PAD_NANDF_CS1__MLB_MLBCLK */
994 IMX_PIN_REG(MX53_PAD_NANDF_CS1, 0x5B4, 0x23C, 7, 0x000, 0), /* MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 */
995 IMX_PIN_REG(MX53_PAD_NANDF_CS2, 0x5B8, 0x240, 0, 0x000, 0), /* MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 */
996 IMX_PIN_REG(MX53_PAD_NANDF_CS2, 0x5B8, 0x240, 1, 0x000, 0), /* MX53_PAD_NANDF_CS2__GPIO6_15 */
997 IMX_PIN_REG(MX53_PAD_NANDF_CS2, 0x5B8, 0x240, 2, 0x000, 0), /* MX53_PAD_NANDF_CS2__IPU_SISG_0 */
998 IMX_PIN_REG(MX53_PAD_NANDF_CS2, 0x5B8, 0x240, 3, 0x7E4, 0), /* MX53_PAD_NANDF_CS2__ESAI1_TX0 */
999 IMX_PIN_REG(MX53_PAD_NANDF_CS2, 0x5B8, 0x240, 4, 0x000, 0), /* MX53_PAD_NANDF_CS2__EMI_WEIM_CRE */
1000 IMX_PIN_REG(MX53_PAD_NANDF_CS2, 0x5B8, 0x240, 5, 0x000, 0), /* MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK */
1001 IMX_PIN_REG(MX53_PAD_NANDF_CS2, 0x5B8, 0x240, 6, 0x860, 0), /* MX53_PAD_NANDF_CS2__MLB_MLBSIG */
1002 IMX_PIN_REG(MX53_PAD_NANDF_CS2, 0x5B8, 0x240, 7, 0x000, 0), /* MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 */
1003 IMX_PIN_REG(MX53_PAD_NANDF_CS3, 0x5BC, 0x244, 0, 0x000, 0), /* MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 */
1004 IMX_PIN_REG(MX53_PAD_NANDF_CS3, 0x5BC, 0x244, 1, 0x000, 0), /* MX53_PAD_NANDF_CS3__GPIO6_16 */
1005 IMX_PIN_REG(MX53_PAD_NANDF_CS3, 0x5BC, 0x244, 2, 0x000, 0), /* MX53_PAD_NANDF_CS3__IPU_SISG_1 */
1006 IMX_PIN_REG(MX53_PAD_NANDF_CS3, 0x5BC, 0x244, 3, 0x7E8, 0), /* MX53_PAD_NANDF_CS3__ESAI1_TX1 */
1007 IMX_PIN_REG(MX53_PAD_NANDF_CS3, 0x5BC, 0x244, 4, 0x000, 0), /* MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 */
1008 IMX_PIN_REG(MX53_PAD_NANDF_CS3, 0x5BC, 0x244, 6, 0x85C, 0), /* MX53_PAD_NANDF_CS3__MLB_MLBDAT */
1009 IMX_PIN_REG(MX53_PAD_NANDF_CS3, 0x5BC, 0x244, 7, 0x000, 0), /* MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 */
1010 IMX_PIN_REG(MX53_PAD_FEC_MDIO, 0x5C4, 0x248, 0, 0x804, 1), /* MX53_PAD_FEC_MDIO__FEC_MDIO */
1011 IMX_PIN_REG(MX53_PAD_FEC_MDIO, 0x5C4, 0x248, 1, 0x000, 0), /* MX53_PAD_FEC_MDIO__GPIO1_22 */
1012 IMX_PIN_REG(MX53_PAD_FEC_MDIO, 0x5C4, 0x248, 2, 0x7DC, 0), /* MX53_PAD_FEC_MDIO__ESAI1_SCKR */
1013 IMX_PIN_REG(MX53_PAD_FEC_MDIO, 0x5C4, 0x248, 3, 0x800, 1), /* MX53_PAD_FEC_MDIO__FEC_COL */
1014 IMX_PIN_REG(MX53_PAD_FEC_MDIO, 0x5C4, 0x248, 4, 0x000, 0), /* MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 */
1015 IMX_PIN_REG(MX53_PAD_FEC_MDIO, 0x5C4, 0x248, 5, 0x000, 0), /* MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 */
1016 IMX_PIN_REG(MX53_PAD_FEC_MDIO, 0x5C4, 0x248, 6, 0x000, 0), /* MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 */
1017 IMX_PIN_REG(MX53_PAD_FEC_REF_CLK, 0x5C8, 0x24C, 0, 0x000, 0), /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */
1018 IMX_PIN_REG(MX53_PAD_FEC_REF_CLK, 0x5C8, 0x24C, 1, 0x000, 0), /* MX53_PAD_FEC_REF_CLK__GPIO1_23 */
1019 IMX_PIN_REG(MX53_PAD_FEC_REF_CLK, 0x5C8, 0x24C, 2, 0x7CC, 0), /* MX53_PAD_FEC_REF_CLK__ESAI1_FSR */
1020 IMX_PIN_REG(MX53_PAD_FEC_REF_CLK, 0x5C8, 0x24C, 5, 0x000, 0), /* MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 */
1021 IMX_PIN_REG(MX53_PAD_FEC_REF_CLK, 0x5C8, 0x24C, 6, 0x000, 0), /* MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 */
1022 IMX_PIN_REG(MX53_PAD_FEC_RX_ER, 0x5CC, 0x250, 0, 0x000, 0), /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */
1023 IMX_PIN_REG(MX53_PAD_FEC_RX_ER, 0x5CC, 0x250, 1, 0x000, 0), /* MX53_PAD_FEC_RX_ER__GPIO1_24 */
1024 IMX_PIN_REG(MX53_PAD_FEC_RX_ER, 0x5CC, 0x250, 2, 0x7D4, 0), /* MX53_PAD_FEC_RX_ER__ESAI1_HCKR */
1025 IMX_PIN_REG(MX53_PAD_FEC_RX_ER, 0x5CC, 0x250, 3, 0x808, 1), /* MX53_PAD_FEC_RX_ER__FEC_RX_CLK */
1026 IMX_PIN_REG(MX53_PAD_FEC_RX_ER, 0x5CC, 0x250, 4, 0x000, 0), /* MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 */
1027 IMX_PIN_REG(MX53_PAD_FEC_CRS_DV, 0x5D0, 0x254, 0, 0x000, 0), /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */
1028 IMX_PIN_REG(MX53_PAD_FEC_CRS_DV, 0x5D0, 0x254, 1, 0x000, 0), /* MX53_PAD_FEC_CRS_DV__GPIO1_25 */
1029 IMX_PIN_REG(MX53_PAD_FEC_CRS_DV, 0x5D0, 0x254, 2, 0x7E0, 0), /* MX53_PAD_FEC_CRS_DV__ESAI1_SCKT */
1030 IMX_PIN_REG(MX53_PAD_FEC_RXD1, 0x5D4, 0x258, 0, 0x000, 0), /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */
1031 IMX_PIN_REG(MX53_PAD_FEC_RXD1, 0x5D4, 0x258, 1, 0x000, 0), /* MX53_PAD_FEC_RXD1__GPIO1_26 */
1032 IMX_PIN_REG(MX53_PAD_FEC_RXD1, 0x5D4, 0x258, 2, 0x7D0, 0), /* MX53_PAD_FEC_RXD1__ESAI1_FST */
1033 IMX_PIN_REG(MX53_PAD_FEC_RXD1, 0x5D4, 0x258, 3, 0x860, 1), /* MX53_PAD_FEC_RXD1__MLB_MLBSIG */
1034 IMX_PIN_REG(MX53_PAD_FEC_RXD1, 0x5D4, 0x258, 4, 0x000, 0), /* MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 */
1035 IMX_PIN_REG(MX53_PAD_FEC_RXD0, 0x5D8, 0x25C, 0, 0x000, 0), /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */
1036 IMX_PIN_REG(MX53_PAD_FEC_RXD0, 0x5D8, 0x25C, 1, 0x000, 0), /* MX53_PAD_FEC_RXD0__GPIO1_27 */
1037 IMX_PIN_REG(MX53_PAD_FEC_RXD0, 0x5D8, 0x25C, 2, 0x7D8, 0), /* MX53_PAD_FEC_RXD0__ESAI1_HCKT */
1038 IMX_PIN_REG(MX53_PAD_FEC_RXD0, 0x5D8, 0x25C, 3, 0x000, 0), /* MX53_PAD_FEC_RXD0__OSC32k_32K_OUT */
1039 IMX_PIN_REG(MX53_PAD_FEC_TX_EN, 0x5DC, 0x260, 0, 0x000, 0), /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */
1040 IMX_PIN_REG(MX53_PAD_FEC_TX_EN, 0x5DC, 0x260, 1, 0x000, 0), /* MX53_PAD_FEC_TX_EN__GPIO1_28 */
1041 IMX_PIN_REG(MX53_PAD_FEC_TX_EN, 0x5DC, 0x260, 2, 0x7F0, 0), /* MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 */
1042 IMX_PIN_REG(MX53_PAD_FEC_TXD1, 0x5E0, 0x264, 0, 0x000, 0), /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */
1043 IMX_PIN_REG(MX53_PAD_FEC_TXD1, 0x5E0, 0x264, 1, 0x000, 0), /* MX53_PAD_FEC_TXD1__GPIO1_29 */
1044 IMX_PIN_REG(MX53_PAD_FEC_TXD1, 0x5E0, 0x264, 2, 0x7EC, 0), /* MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 */
1045 IMX_PIN_REG(MX53_PAD_FEC_TXD1, 0x5E0, 0x264, 3, 0x858, 1), /* MX53_PAD_FEC_TXD1__MLB_MLBCLK */
1046 IMX_PIN_REG(MX53_PAD_FEC_TXD1, 0x5E0, 0x264, 4, 0x000, 0), /* MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK */
1047 IMX_PIN_REG(MX53_PAD_FEC_TXD0, 0x5E4, 0x268, 0, 0x000, 0), /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */
1048 IMX_PIN_REG(MX53_PAD_FEC_TXD0, 0x5E4, 0x268, 1, 0x000, 0), /* MX53_PAD_FEC_TXD0__GPIO1_30 */
1049 IMX_PIN_REG(MX53_PAD_FEC_TXD0, 0x5E4, 0x268, 2, 0x7F4, 0), /* MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 */
1050 IMX_PIN_REG(MX53_PAD_FEC_TXD0, 0x5E4, 0x268, 7, 0x000, 0), /* MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 */
1051 IMX_PIN_REG(MX53_PAD_FEC_MDC, 0x5E8, 0x26C, 0, 0x000, 0), /* MX53_PAD_FEC_MDC__FEC_MDC */
1052 IMX_PIN_REG(MX53_PAD_FEC_MDC, 0x5E8, 0x26C, 1, 0x000, 0), /* MX53_PAD_FEC_MDC__GPIO1_31 */
1053 IMX_PIN_REG(MX53_PAD_FEC_MDC, 0x5E8, 0x26C, 2, 0x7F8, 0), /* MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 */
1054 IMX_PIN_REG(MX53_PAD_FEC_MDC, 0x5E8, 0x26C, 3, 0x85C, 1), /* MX53_PAD_FEC_MDC__MLB_MLBDAT */
1055 IMX_PIN_REG(MX53_PAD_FEC_MDC, 0x5E8, 0x26C, 4, 0x000, 0), /* MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG */
1056 IMX_PIN_REG(MX53_PAD_FEC_MDC, 0x5E8, 0x26C, 7, 0x000, 0), /* MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 */
1057 IMX_PIN_REG(MX53_PAD_PATA_DIOW, 0x5F0, 0x270, 0, 0x000, 0), /* MX53_PAD_PATA_DIOW__PATA_DIOW */
1058 IMX_PIN_REG(MX53_PAD_PATA_DIOW, 0x5F0, 0x270, 1, 0x000, 0), /* MX53_PAD_PATA_DIOW__GPIO6_17 */
1059 IMX_PIN_REG(MX53_PAD_PATA_DIOW, 0x5F0, 0x270, 3, 0x000, 0), /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */
1060 IMX_PIN_REG(MX53_PAD_PATA_DIOW, 0x5F0, 0x270, 7, 0x000, 0), /* MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 */
1061 IMX_PIN_REG(MX53_PAD_PATA_DMACK, 0x5F4, 0x274, 0, 0x000, 0), /* MX53_PAD_PATA_DMACK__PATA_DMACK */
1062 IMX_PIN_REG(MX53_PAD_PATA_DMACK, 0x5F4, 0x274, 1, 0x000, 0), /* MX53_PAD_PATA_DMACK__GPIO6_18 */
1063 IMX_PIN_REG(MX53_PAD_PATA_DMACK, 0x5F4, 0x274, 3, 0x878, 3), /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */
1064 IMX_PIN_REG(MX53_PAD_PATA_DMACK, 0x5F4, 0x274, 7, 0x000, 0), /* MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 */
1065 IMX_PIN_REG(MX53_PAD_PATA_DMARQ, 0x5F8, 0x278, 0, 0x000, 0), /* MX53_PAD_PATA_DMARQ__PATA_DMARQ */
1066 IMX_PIN_REG(MX53_PAD_PATA_DMARQ, 0x5F8, 0x278, 1, 0x000, 0), /* MX53_PAD_PATA_DMARQ__GPIO7_0 */
1067 IMX_PIN_REG(MX53_PAD_PATA_DMARQ, 0x5F8, 0x278, 3, 0x000, 0), /* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */
1068 IMX_PIN_REG(MX53_PAD_PATA_DMARQ, 0x5F8, 0x278, 5, 0x000, 0), /* MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 */
1069 IMX_PIN_REG(MX53_PAD_PATA_DMARQ, 0x5F8, 0x278, 7, 0x000, 0), /* MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 */
1070 IMX_PIN_REG(MX53_PAD_PATA_BUFFER_EN, 0x5FC, 0x27C, 0, 0x000, 0), /* MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN */
1071 IMX_PIN_REG(MX53_PAD_PATA_BUFFER_EN, 0x5FC, 0x27C, 1, 0x000, 0), /* MX53_PAD_PATA_BUFFER_EN__GPIO7_1 */
1072 IMX_PIN_REG(MX53_PAD_PATA_BUFFER_EN, 0x5FC, 0x27C, 3, 0x880, 3), /* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */
1073 IMX_PIN_REG(MX53_PAD_PATA_BUFFER_EN, 0x5FC, 0x27C, 5, 0x000, 0), /* MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 */
1074 IMX_PIN_REG(MX53_PAD_PATA_BUFFER_EN, 0x5FC, 0x27C, 7, 0x000, 0), /* MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 */
1075 IMX_PIN_REG(MX53_PAD_PATA_INTRQ, 0x600, 0x280, 0, 0x000, 0), /* MX53_PAD_PATA_INTRQ__PATA_INTRQ */
1076 IMX_PIN_REG(MX53_PAD_PATA_INTRQ, 0x600, 0x280, 1, 0x000, 0), /* MX53_PAD_PATA_INTRQ__GPIO7_2 */
1077 IMX_PIN_REG(MX53_PAD_PATA_INTRQ, 0x600, 0x280, 3, 0x000, 0), /* MX53_PAD_PATA_INTRQ__UART2_CTS */
1078 IMX_PIN_REG(MX53_PAD_PATA_INTRQ, 0x600, 0x280, 4, 0x000, 0), /* MX53_PAD_PATA_INTRQ__CAN1_TXCAN */
1079 IMX_PIN_REG(MX53_PAD_PATA_INTRQ, 0x600, 0x280, 5, 0x000, 0), /* MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 */
1080 IMX_PIN_REG(MX53_PAD_PATA_INTRQ, 0x600, 0x280, 7, 0x000, 0), /* MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 */
1081 IMX_PIN_REG(MX53_PAD_PATA_DIOR, 0x604, 0x284, 0, 0x000, 0), /* MX53_PAD_PATA_DIOR__PATA_DIOR */
1082 IMX_PIN_REG(MX53_PAD_PATA_DIOR, 0x604, 0x284, 1, 0x000, 0), /* MX53_PAD_PATA_DIOR__GPIO7_3 */
1083 IMX_PIN_REG(MX53_PAD_PATA_DIOR, 0x604, 0x284, 3, 0x87C, 3), /* MX53_PAD_PATA_DIOR__UART2_RTS */
1084 IMX_PIN_REG(MX53_PAD_PATA_DIOR, 0x604, 0x284, 4, 0x760, 1), /* MX53_PAD_PATA_DIOR__CAN1_RXCAN */
1085 IMX_PIN_REG(MX53_PAD_PATA_DIOR, 0x604, 0x284, 7, 0x000, 0), /* MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 */
1086 IMX_PIN_REG(MX53_PAD_PATA_RESET_B, 0x608, 0x288, 0, 0x000, 0), /* MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B */
1087 IMX_PIN_REG(MX53_PAD_PATA_RESET_B, 0x608, 0x288, 1, 0x000, 0), /* MX53_PAD_PATA_RESET_B__GPIO7_4 */
1088 IMX_PIN_REG(MX53_PAD_PATA_RESET_B, 0x608, 0x288, 2, 0x000, 0), /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */
1089 IMX_PIN_REG(MX53_PAD_PATA_RESET_B, 0x608, 0x288, 3, 0x000, 0), /* MX53_PAD_PATA_RESET_B__UART1_CTS */
1090 IMX_PIN_REG(MX53_PAD_PATA_RESET_B, 0x608, 0x288, 4, 0x000, 0), /* MX53_PAD_PATA_RESET_B__CAN2_TXCAN */
1091 IMX_PIN_REG(MX53_PAD_PATA_RESET_B, 0x608, 0x288, 7, 0x000, 0), /* MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 */
1092 IMX_PIN_REG(MX53_PAD_PATA_IORDY, 0x60C, 0x28C, 0, 0x000, 0), /* MX53_PAD_PATA_IORDY__PATA_IORDY */
1093 IMX_PIN_REG(MX53_PAD_PATA_IORDY, 0x60C, 0x28C, 1, 0x000, 0), /* MX53_PAD_PATA_IORDY__GPIO7_5 */
1094 IMX_PIN_REG(MX53_PAD_PATA_IORDY, 0x60C, 0x28C, 2, 0x000, 0), /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */
1095 IMX_PIN_REG(MX53_PAD_PATA_IORDY, 0x60C, 0x28C, 3, 0x874, 3), /* MX53_PAD_PATA_IORDY__UART1_RTS */
1096 IMX_PIN_REG(MX53_PAD_PATA_IORDY, 0x60C, 0x28C, 4, 0x764, 1), /* MX53_PAD_PATA_IORDY__CAN2_RXCAN */
1097 IMX_PIN_REG(MX53_PAD_PATA_IORDY, 0x60C, 0x28C, 7, 0x000, 0), /* MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 */
1098 IMX_PIN_REG(MX53_PAD_PATA_DA_0, 0x610, 0x290, 0, 0x000, 0), /* MX53_PAD_PATA_DA_0__PATA_DA_0 */
1099 IMX_PIN_REG(MX53_PAD_PATA_DA_0, 0x610, 0x290, 1, 0x000, 0), /* MX53_PAD_PATA_DA_0__GPIO7_6 */
1100 IMX_PIN_REG(MX53_PAD_PATA_DA_0, 0x610, 0x290, 2, 0x000, 0), /* MX53_PAD_PATA_DA_0__ESDHC3_RST */
1101 IMX_PIN_REG(MX53_PAD_PATA_DA_0, 0x610, 0x290, 4, 0x864, 0), /* MX53_PAD_PATA_DA_0__OWIRE_LINE */
1102 IMX_PIN_REG(MX53_PAD_PATA_DA_0, 0x610, 0x290, 7, 0x000, 0), /* MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 */
1103 IMX_PIN_REG(MX53_PAD_PATA_DA_1, 0x614, 0x294, 0, 0x000, 0), /* MX53_PAD_PATA_DA_1__PATA_DA_1 */
1104 IMX_PIN_REG(MX53_PAD_PATA_DA_1, 0x614, 0x294, 1, 0x000, 0), /* MX53_PAD_PATA_DA_1__GPIO7_7 */
1105 IMX_PIN_REG(MX53_PAD_PATA_DA_1, 0x614, 0x294, 2, 0x000, 0), /* MX53_PAD_PATA_DA_1__ESDHC4_CMD */
1106 IMX_PIN_REG(MX53_PAD_PATA_DA_1, 0x614, 0x294, 4, 0x000, 0), /* MX53_PAD_PATA_DA_1__UART3_CTS */
1107 IMX_PIN_REG(MX53_PAD_PATA_DA_1, 0x614, 0x294, 7, 0x000, 0), /* MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 */
1108 IMX_PIN_REG(MX53_PAD_PATA_DA_2, 0x618, 0x298, 0, 0x000, 0), /* MX53_PAD_PATA_DA_2__PATA_DA_2 */
1109 IMX_PIN_REG(MX53_PAD_PATA_DA_2, 0x618, 0x298, 1, 0x000, 0), /* MX53_PAD_PATA_DA_2__GPIO7_8 */
1110 IMX_PIN_REG(MX53_PAD_PATA_DA_2, 0x618, 0x298, 2, 0x000, 0), /* MX53_PAD_PATA_DA_2__ESDHC4_CLK */
1111 IMX_PIN_REG(MX53_PAD_PATA_DA_2, 0x618, 0x298, 4, 0x884, 5), /* MX53_PAD_PATA_DA_2__UART3_RTS */
1112 IMX_PIN_REG(MX53_PAD_PATA_DA_2, 0x618, 0x298, 7, 0x000, 0), /* MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 */
1113 IMX_PIN_REG(MX53_PAD_PATA_CS_0, 0x61C, 0x29C, 0, 0x000, 0), /* MX53_PAD_PATA_CS_0__PATA_CS_0 */
1114 IMX_PIN_REG(MX53_PAD_PATA_CS_0, 0x61C, 0x29C, 1, 0x000, 0), /* MX53_PAD_PATA_CS_0__GPIO7_9 */
1115 IMX_PIN_REG(MX53_PAD_PATA_CS_0, 0x61C, 0x29C, 4, 0x000, 0), /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */
1116 IMX_PIN_REG(MX53_PAD_PATA_CS_0, 0x61C, 0x29C, 7, 0x000, 0), /* MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 */
1117 IMX_PIN_REG(MX53_PAD_PATA_CS_1, 0x620, 0x2A0, 0, 0x000, 0), /* MX53_PAD_PATA_CS_1__PATA_CS_1 */
1118 IMX_PIN_REG(MX53_PAD_PATA_CS_1, 0x620, 0x2A0, 1, 0x000, 0), /* MX53_PAD_PATA_CS_1__GPIO7_10 */
1119 IMX_PIN_REG(MX53_PAD_PATA_CS_1, 0x620, 0x2A0, 4, 0x888, 3), /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */
1120 IMX_PIN_REG(MX53_PAD_PATA_CS_1, 0x620, 0x2A0, 7, 0x000, 0), /* MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 */
1121 IMX_PIN_REG(MX53_PAD_PATA_DATA0, 0x628, 0x2A4, 0, 0x000, 0), /* MX53_PAD_PATA_DATA0__PATA_DATA_0 */
1122 IMX_PIN_REG(MX53_PAD_PATA_DATA0, 0x628, 0x2A4, 1, 0x000, 0), /* MX53_PAD_PATA_DATA0__GPIO2_0 */
1123 IMX_PIN_REG(MX53_PAD_PATA_DATA0, 0x628, 0x2A4, 3, 0x000, 0), /* MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 */
1124 IMX_PIN_REG(MX53_PAD_PATA_DATA0, 0x628, 0x2A4, 4, 0x000, 0), /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */
1125 IMX_PIN_REG(MX53_PAD_PATA_DATA0, 0x628, 0x2A4, 5, 0x000, 0), /* MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 */
1126 IMX_PIN_REG(MX53_PAD_PATA_DATA0, 0x628, 0x2A4, 6, 0x000, 0), /* MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 */
1127 IMX_PIN_REG(MX53_PAD_PATA_DATA0, 0x628, 0x2A4, 7, 0x000, 0), /* MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 */
1128 IMX_PIN_REG(MX53_PAD_PATA_DATA1, 0x62C, 0x2A8, 0, 0x000, 0), /* MX53_PAD_PATA_DATA1__PATA_DATA_1 */
1129 IMX_PIN_REG(MX53_PAD_PATA_DATA1, 0x62C, 0x2A8, 1, 0x000, 0), /* MX53_PAD_PATA_DATA1__GPIO2_1 */
1130 IMX_PIN_REG(MX53_PAD_PATA_DATA1, 0x62C, 0x2A8, 3, 0x000, 0), /* MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 */
1131 IMX_PIN_REG(MX53_PAD_PATA_DATA1, 0x62C, 0x2A8, 4, 0x000, 0), /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */
1132 IMX_PIN_REG(MX53_PAD_PATA_DATA1, 0x62C, 0x2A8, 5, 0x000, 0), /* MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 */
1133 IMX_PIN_REG(MX53_PAD_PATA_DATA1, 0x62C, 0x2A8, 6, 0x000, 0), /* MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 */
1134 IMX_PIN_REG(MX53_PAD_PATA_DATA2, 0x630, 0x2AC, 0, 0x000, 0), /* MX53_PAD_PATA_DATA2__PATA_DATA_2 */
1135 IMX_PIN_REG(MX53_PAD_PATA_DATA2, 0x630, 0x2AC, 1, 0x000, 0), /* MX53_PAD_PATA_DATA2__GPIO2_2 */
1136 IMX_PIN_REG(MX53_PAD_PATA_DATA2, 0x630, 0x2AC, 3, 0x000, 0), /* MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 */
1137 IMX_PIN_REG(MX53_PAD_PATA_DATA2, 0x630, 0x2AC, 4, 0x000, 0), /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */
1138 IMX_PIN_REG(MX53_PAD_PATA_DATA2, 0x630, 0x2AC, 5, 0x000, 0), /* MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 */
1139 IMX_PIN_REG(MX53_PAD_PATA_DATA2, 0x630, 0x2AC, 6, 0x000, 0), /* MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 */
1140 IMX_PIN_REG(MX53_PAD_PATA_DATA3, 0x634, 0x2B0, 0, 0x000, 0), /* MX53_PAD_PATA_DATA3__PATA_DATA_3 */
1141 IMX_PIN_REG(MX53_PAD_PATA_DATA3, 0x634, 0x2B0, 1, 0x000, 0), /* MX53_PAD_PATA_DATA3__GPIO2_3 */
1142 IMX_PIN_REG(MX53_PAD_PATA_DATA3, 0x634, 0x2B0, 3, 0x000, 0), /* MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 */
1143 IMX_PIN_REG(MX53_PAD_PATA_DATA3, 0x634, 0x2B0, 4, 0x000, 0), /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */
1144 IMX_PIN_REG(MX53_PAD_PATA_DATA3, 0x634, 0x2B0, 5, 0x000, 0), /* MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 */
1145 IMX_PIN_REG(MX53_PAD_PATA_DATA3, 0x634, 0x2B0, 6, 0x000, 0), /* MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 */
1146 IMX_PIN_REG(MX53_PAD_PATA_DATA4, 0x638, 0x2B4, 0, 0x000, 0), /* MX53_PAD_PATA_DATA4__PATA_DATA_4 */
1147 IMX_PIN_REG(MX53_PAD_PATA_DATA4, 0x638, 0x2B4, 1, 0x000, 0), /* MX53_PAD_PATA_DATA4__GPIO2_4 */
1148 IMX_PIN_REG(MX53_PAD_PATA_DATA4, 0x638, 0x2B4, 3, 0x000, 0), /* MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 */
1149 IMX_PIN_REG(MX53_PAD_PATA_DATA4, 0x638, 0x2B4, 4, 0x000, 0), /* MX53_PAD_PATA_DATA4__ESDHC4_DAT4 */
1150 IMX_PIN_REG(MX53_PAD_PATA_DATA4, 0x638, 0x2B4, 5, 0x000, 0), /* MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 */
1151 IMX_PIN_REG(MX53_PAD_PATA_DATA4, 0x638, 0x2B4, 6, 0x000, 0), /* MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 */
1152 IMX_PIN_REG(MX53_PAD_PATA_DATA5, 0x63C, 0x2B8, 0, 0x000, 0), /* MX53_PAD_PATA_DATA5__PATA_DATA_5 */
1153 IMX_PIN_REG(MX53_PAD_PATA_DATA5, 0x63C, 0x2B8, 1, 0x000, 0), /* MX53_PAD_PATA_DATA5__GPIO2_5 */
1154 IMX_PIN_REG(MX53_PAD_PATA_DATA5, 0x63C, 0x2B8, 3, 0x000, 0), /* MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 */
1155 IMX_PIN_REG(MX53_PAD_PATA_DATA5, 0x63C, 0x2B8, 4, 0x000, 0), /* MX53_PAD_PATA_DATA5__ESDHC4_DAT5 */
1156 IMX_PIN_REG(MX53_PAD_PATA_DATA5, 0x63C, 0x2B8, 5, 0x000, 0), /* MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 */
1157 IMX_PIN_REG(MX53_PAD_PATA_DATA5, 0x63C, 0x2B8, 6, 0x000, 0), /* MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 */
1158 IMX_PIN_REG(MX53_PAD_PATA_DATA6, 0x640, 0x2BC, 0, 0x000, 0), /* MX53_PAD_PATA_DATA6__PATA_DATA_6 */
1159 IMX_PIN_REG(MX53_PAD_PATA_DATA6, 0x640, 0x2BC, 1, 0x000, 0), /* MX53_PAD_PATA_DATA6__GPIO2_6 */
1160 IMX_PIN_REG(MX53_PAD_PATA_DATA6, 0x640, 0x2BC, 3, 0x000, 0), /* MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 */
1161 IMX_PIN_REG(MX53_PAD_PATA_DATA6, 0x640, 0x2BC, 4, 0x000, 0), /* MX53_PAD_PATA_DATA6__ESDHC4_DAT6 */
1162 IMX_PIN_REG(MX53_PAD_PATA_DATA6, 0x640, 0x2BC, 5, 0x000, 0), /* MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 */
1163 IMX_PIN_REG(MX53_PAD_PATA_DATA6, 0x640, 0x2BC, 6, 0x000, 0), /* MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 */
1164 IMX_PIN_REG(MX53_PAD_PATA_DATA7, 0x644, 0x2C0, 0, 0x000, 0), /* MX53_PAD_PATA_DATA7__PATA_DATA_7 */
1165 IMX_PIN_REG(MX53_PAD_PATA_DATA7, 0x644, 0x2C0, 1, 0x000, 0), /* MX53_PAD_PATA_DATA7__GPIO2_7 */
1166 IMX_PIN_REG(MX53_PAD_PATA_DATA7, 0x644, 0x2C0, 3, 0x000, 0), /* MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 */
1167 IMX_PIN_REG(MX53_PAD_PATA_DATA7, 0x644, 0x2C0, 4, 0x000, 0), /* MX53_PAD_PATA_DATA7__ESDHC4_DAT7 */
1168 IMX_PIN_REG(MX53_PAD_PATA_DATA7, 0x644, 0x2C0, 5, 0x000, 0), /* MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 */
1169 IMX_PIN_REG(MX53_PAD_PATA_DATA7, 0x644, 0x2C0, 6, 0x000, 0), /* MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 */
1170 IMX_PIN_REG(MX53_PAD_PATA_DATA8, 0x648, 0x2C4, 0, 0x000, 0), /* MX53_PAD_PATA_DATA8__PATA_DATA_8 */
1171 IMX_PIN_REG(MX53_PAD_PATA_DATA8, 0x648, 0x2C4, 1, 0x000, 0), /* MX53_PAD_PATA_DATA8__GPIO2_8 */
1172 IMX_PIN_REG(MX53_PAD_PATA_DATA8, 0x648, 0x2C4, 2, 0x000, 0), /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */
1173 IMX_PIN_REG(MX53_PAD_PATA_DATA8, 0x648, 0x2C4, 3, 0x000, 0), /* MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 */
1174 IMX_PIN_REG(MX53_PAD_PATA_DATA8, 0x648, 0x2C4, 4, 0x000, 0), /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */
1175 IMX_PIN_REG(MX53_PAD_PATA_DATA8, 0x648, 0x2C4, 5, 0x000, 0), /* MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 */
1176 IMX_PIN_REG(MX53_PAD_PATA_DATA8, 0x648, 0x2C4, 6, 0x000, 0), /* MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 */
1177 IMX_PIN_REG(MX53_PAD_PATA_DATA9, 0x64C, 0x2C8, 0, 0x000, 0), /* MX53_PAD_PATA_DATA9__PATA_DATA_9 */
1178 IMX_PIN_REG(MX53_PAD_PATA_DATA9, 0x64C, 0x2C8, 1, 0x000, 0), /* MX53_PAD_PATA_DATA9__GPIO2_9 */
1179 IMX_PIN_REG(MX53_PAD_PATA_DATA9, 0x64C, 0x2C8, 2, 0x000, 0), /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */
1180 IMX_PIN_REG(MX53_PAD_PATA_DATA9, 0x64C, 0x2C8, 3, 0x000, 0), /* MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 */
1181 IMX_PIN_REG(MX53_PAD_PATA_DATA9, 0x64C, 0x2C8, 4, 0x000, 0), /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */
1182 IMX_PIN_REG(MX53_PAD_PATA_DATA9, 0x64C, 0x2C8, 5, 0x000, 0), /* MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 */
1183 IMX_PIN_REG(MX53_PAD_PATA_DATA9, 0x64C, 0x2C8, 6, 0x000, 0), /* MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 */
1184 IMX_PIN_REG(MX53_PAD_PATA_DATA10, 0x650, 0x2CC, 0, 0x000, 0), /* MX53_PAD_PATA_DATA10__PATA_DATA_10 */
1185 IMX_PIN_REG(MX53_PAD_PATA_DATA10, 0x650, 0x2CC, 1, 0x000, 0), /* MX53_PAD_PATA_DATA10__GPIO2_10 */
1186 IMX_PIN_REG(MX53_PAD_PATA_DATA10, 0x650, 0x2CC, 2, 0x000, 0), /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */
1187 IMX_PIN_REG(MX53_PAD_PATA_DATA10, 0x650, 0x2CC, 3, 0x000, 0), /* MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 */
1188 IMX_PIN_REG(MX53_PAD_PATA_DATA10, 0x650, 0x2CC, 4, 0x000, 0), /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */
1189 IMX_PIN_REG(MX53_PAD_PATA_DATA10, 0x650, 0x2CC, 5, 0x000, 0), /* MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 */
1190 IMX_PIN_REG(MX53_PAD_PATA_DATA10, 0x650, 0x2CC, 6, 0x000, 0), /* MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 */
1191 IMX_PIN_REG(MX53_PAD_PATA_DATA11, 0x654, 0x2D0, 0, 0x000, 0), /* MX53_PAD_PATA_DATA11__PATA_DATA_11 */
1192 IMX_PIN_REG(MX53_PAD_PATA_DATA11, 0x654, 0x2D0, 1, 0x000, 0), /* MX53_PAD_PATA_DATA11__GPIO2_11 */
1193 IMX_PIN_REG(MX53_PAD_PATA_DATA11, 0x654, 0x2D0, 2, 0x000, 0), /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */
1194 IMX_PIN_REG(MX53_PAD_PATA_DATA11, 0x654, 0x2D0, 3, 0x000, 0), /* MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 */
1195 IMX_PIN_REG(MX53_PAD_PATA_DATA11, 0x654, 0x2D0, 4, 0x000, 0), /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */
1196 IMX_PIN_REG(MX53_PAD_PATA_DATA11, 0x654, 0x2D0, 5, 0x000, 0), /* MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 */
1197 IMX_PIN_REG(MX53_PAD_PATA_DATA11, 0x654, 0x2D0, 6, 0x000, 0), /* MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 */
1198 IMX_PIN_REG(MX53_PAD_PATA_DATA12, 0x658, 0x2D4, 0, 0x000, 0), /* MX53_PAD_PATA_DATA12__PATA_DATA_12 */
1199 IMX_PIN_REG(MX53_PAD_PATA_DATA12, 0x658, 0x2D4, 1, 0x000, 0), /* MX53_PAD_PATA_DATA12__GPIO2_12 */
1200 IMX_PIN_REG(MX53_PAD_PATA_DATA12, 0x658, 0x2D4, 2, 0x000, 0), /* MX53_PAD_PATA_DATA12__ESDHC2_DAT4 */
1201 IMX_PIN_REG(MX53_PAD_PATA_DATA12, 0x658, 0x2D4, 3, 0x000, 0), /* MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 */
1202 IMX_PIN_REG(MX53_PAD_PATA_DATA12, 0x658, 0x2D4, 4, 0x000, 0), /* MX53_PAD_PATA_DATA12__ESDHC4_DAT0 */
1203 IMX_PIN_REG(MX53_PAD_PATA_DATA12, 0x658, 0x2D4, 5, 0x000, 0), /* MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 */
1204 IMX_PIN_REG(MX53_PAD_PATA_DATA12, 0x658, 0x2D4, 6, 0x000, 0), /* MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 */
1205 IMX_PIN_REG(MX53_PAD_PATA_DATA13, 0x65C, 0x2D8, 0, 0x000, 0), /* MX53_PAD_PATA_DATA13__PATA_DATA_13 */
1206 IMX_PIN_REG(MX53_PAD_PATA_DATA13, 0x65C, 0x2D8, 1, 0x000, 0), /* MX53_PAD_PATA_DATA13__GPIO2_13 */
1207 IMX_PIN_REG(MX53_PAD_PATA_DATA13, 0x65C, 0x2D8, 2, 0x000, 0), /* MX53_PAD_PATA_DATA13__ESDHC2_DAT5 */
1208 IMX_PIN_REG(MX53_PAD_PATA_DATA13, 0x65C, 0x2D8, 3, 0x000, 0), /* MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 */
1209 IMX_PIN_REG(MX53_PAD_PATA_DATA13, 0x65C, 0x2D8, 4, 0x000, 0), /* MX53_PAD_PATA_DATA13__ESDHC4_DAT1 */
1210 IMX_PIN_REG(MX53_PAD_PATA_DATA13, 0x65C, 0x2D8, 5, 0x000, 0), /* MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 */
1211 IMX_PIN_REG(MX53_PAD_PATA_DATA13, 0x65C, 0x2D8, 6, 0x000, 0), /* MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 */
1212 IMX_PIN_REG(MX53_PAD_PATA_DATA14, 0x660, 0x2DC, 0, 0x000, 0), /* MX53_PAD_PATA_DATA14__PATA_DATA_14 */
1213 IMX_PIN_REG(MX53_PAD_PATA_DATA14, 0x660, 0x2DC, 1, 0x000, 0), /* MX53_PAD_PATA_DATA14__GPIO2_14 */
1214 IMX_PIN_REG(MX53_PAD_PATA_DATA14, 0x660, 0x2DC, 2, 0x000, 0), /* MX53_PAD_PATA_DATA14__ESDHC2_DAT6 */
1215 IMX_PIN_REG(MX53_PAD_PATA_DATA14, 0x660, 0x2DC, 3, 0x000, 0), /* MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 */
1216 IMX_PIN_REG(MX53_PAD_PATA_DATA14, 0x660, 0x2DC, 4, 0x000, 0), /* MX53_PAD_PATA_DATA14__ESDHC4_DAT2 */
1217 IMX_PIN_REG(MX53_PAD_PATA_DATA14, 0x660, 0x2DC, 5, 0x000, 0), /* MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 */
1218 IMX_PIN_REG(MX53_PAD_PATA_DATA14, 0x660, 0x2DC, 6, 0x000, 0), /* MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 */
1219 IMX_PIN_REG(MX53_PAD_PATA_DATA15, 0x664, 0x2E0, 0, 0x000, 0), /* MX53_PAD_PATA_DATA15__PATA_DATA_15 */
1220 IMX_PIN_REG(MX53_PAD_PATA_DATA15, 0x664, 0x2E0, 1, 0x000, 0), /* MX53_PAD_PATA_DATA15__GPIO2_15 */
1221 IMX_PIN_REG(MX53_PAD_PATA_DATA15, 0x664, 0x2E0, 2, 0x000, 0), /* MX53_PAD_PATA_DATA15__ESDHC2_DAT7 */
1222 IMX_PIN_REG(MX53_PAD_PATA_DATA15, 0x664, 0x2E0, 3, 0x000, 0), /* MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 */
1223 IMX_PIN_REG(MX53_PAD_PATA_DATA15, 0x664, 0x2E0, 4, 0x000, 0), /* MX53_PAD_PATA_DATA15__ESDHC4_DAT3 */
1224 IMX_PIN_REG(MX53_PAD_PATA_DATA15, 0x664, 0x2E0, 5, 0x000, 0), /* MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 */
1225 IMX_PIN_REG(MX53_PAD_PATA_DATA15, 0x664, 0x2E0, 6, 0x000, 0), /* MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 */
1226 IMX_PIN_REG(MX53_PAD_SD1_DATA0, 0x66C, 0x2E4, 0, 0x000, 0), /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
1227 IMX_PIN_REG(MX53_PAD_SD1_DATA0, 0x66C, 0x2E4, 1, 0x000, 0), /* MX53_PAD_SD1_DATA0__GPIO1_16 */
1228 IMX_PIN_REG(MX53_PAD_SD1_DATA0, 0x66C, 0x2E4, 3, 0x000, 0), /* MX53_PAD_SD1_DATA0__GPT_CAPIN1 */
1229 IMX_PIN_REG(MX53_PAD_SD1_DATA0, 0x66C, 0x2E4, 5, 0x784, 2), /* MX53_PAD_SD1_DATA0__CSPI_MISO */
1230 IMX_PIN_REG(MX53_PAD_SD1_DATA0, 0x66C, 0x2E4, 7, 0x778, 0), /* MX53_PAD_SD1_DATA0__CCM_PLL3_BYP */
1231 IMX_PIN_REG(MX53_PAD_SD1_DATA1, 0x670, 0x2E8, 0, 0x000, 0), /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
1232 IMX_PIN_REG(MX53_PAD_SD1_DATA1, 0x670, 0x2E8, 1, 0x000, 0), /* MX53_PAD_SD1_DATA1__GPIO1_17 */
1233 IMX_PIN_REG(MX53_PAD_SD1_DATA1, 0x670, 0x2E8, 3, 0x000, 0), /* MX53_PAD_SD1_DATA1__GPT_CAPIN2 */
1234 IMX_PIN_REG(MX53_PAD_SD1_DATA1, 0x670, 0x2E8, 5, 0x78C, 3), /* MX53_PAD_SD1_DATA1__CSPI_SS0 */
1235 IMX_PIN_REG(MX53_PAD_SD1_DATA1, 0x670, 0x2E8, 7, 0x77C, 1), /* MX53_PAD_SD1_DATA1__CCM_PLL4_BYP */
1236 IMX_PIN_REG(MX53_PAD_SD1_CMD, 0x674, 0x2EC, 0, 0x000, 0), /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
1237 IMX_PIN_REG(MX53_PAD_SD1_CMD, 0x674, 0x2EC, 1, 0x000, 0), /* MX53_PAD_SD1_CMD__GPIO1_18 */
1238 IMX_PIN_REG(MX53_PAD_SD1_CMD, 0x674, 0x2EC, 3, 0x000, 0), /* MX53_PAD_SD1_CMD__GPT_CMPOUT1 */
1239 IMX_PIN_REG(MX53_PAD_SD1_CMD, 0x674, 0x2EC, 5, 0x788, 2), /* MX53_PAD_SD1_CMD__CSPI_MOSI */
1240 IMX_PIN_REG(MX53_PAD_SD1_CMD, 0x674, 0x2EC, 7, 0x770, 0), /* MX53_PAD_SD1_CMD__CCM_PLL1_BYP */
1241 IMX_PIN_REG(MX53_PAD_SD1_DATA2, 0x678, 0x2F0, 0, 0x000, 0), /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
1242 IMX_PIN_REG(MX53_PAD_SD1_DATA2, 0x678, 0x2F0, 1, 0x000, 0), /* MX53_PAD_SD1_DATA2__GPIO1_19 */
1243 IMX_PIN_REG(MX53_PAD_SD1_DATA2, 0x678, 0x2F0, 2, 0x000, 0), /* MX53_PAD_SD1_DATA2__GPT_CMPOUT2 */
1244 IMX_PIN_REG(MX53_PAD_SD1_DATA2, 0x678, 0x2F0, 3, 0x000, 0), /* MX53_PAD_SD1_DATA2__PWM2_PWMO */
1245 IMX_PIN_REG(MX53_PAD_SD1_DATA2, 0x678, 0x2F0, 4, 0x000, 0), /* MX53_PAD_SD1_DATA2__WDOG1_WDOG_B */
1246 IMX_PIN_REG(MX53_PAD_SD1_DATA2, 0x678, 0x2F0, 5, 0x790, 2), /* MX53_PAD_SD1_DATA2__CSPI_SS1 */
1247 IMX_PIN_REG(MX53_PAD_SD1_DATA2, 0x678, 0x2F0, 6, 0x000, 0), /* MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB */
1248 IMX_PIN_REG(MX53_PAD_SD1_DATA2, 0x678, 0x2F0, 7, 0x774, 0), /* MX53_PAD_SD1_DATA2__CCM_PLL2_BYP */
1249 IMX_PIN_REG(MX53_PAD_SD1_CLK, 0x67C, 0x2F4, 0, 0x000, 0), /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
1250 IMX_PIN_REG(MX53_PAD_SD1_CLK, 0x67C, 0x2F4, 1, 0x000, 0), /* MX53_PAD_SD1_CLK__GPIO1_20 */
1251 IMX_PIN_REG(MX53_PAD_SD1_CLK, 0x67C, 0x2F4, 2, 0x000, 0), /* MX53_PAD_SD1_CLK__OSC32k_32K_OUT */
1252 IMX_PIN_REG(MX53_PAD_SD1_CLK, 0x67C, 0x2F4, 3, 0x000, 0), /* MX53_PAD_SD1_CLK__GPT_CLKIN */
1253 IMX_PIN_REG(MX53_PAD_SD1_CLK, 0x67C, 0x2F4, 5, 0x780, 2), /* MX53_PAD_SD1_CLK__CSPI_SCLK */
1254 IMX_PIN_REG(MX53_PAD_SD1_CLK, 0x67C, 0x2F4, 7, 0x000, 0), /* MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 */
1255 IMX_PIN_REG(MX53_PAD_SD1_DATA3, 0x680, 0x2F8, 0, 0x000, 0), /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
1256 IMX_PIN_REG(MX53_PAD_SD1_DATA3, 0x680, 0x2F8, 1, 0x000, 0), /* MX53_PAD_SD1_DATA3__GPIO1_21 */
1257 IMX_PIN_REG(MX53_PAD_SD1_DATA3, 0x680, 0x2F8, 2, 0x000, 0), /* MX53_PAD_SD1_DATA3__GPT_CMPOUT3 */
1258 IMX_PIN_REG(MX53_PAD_SD1_DATA3, 0x680, 0x2F8, 3, 0x000, 0), /* MX53_PAD_SD1_DATA3__PWM1_PWMO */
1259 IMX_PIN_REG(MX53_PAD_SD1_DATA3, 0x680, 0x2F8, 4, 0x000, 0), /* MX53_PAD_SD1_DATA3__WDOG2_WDOG_B */
1260 IMX_PIN_REG(MX53_PAD_SD1_DATA3, 0x680, 0x2F8, 5, 0x794, 2), /* MX53_PAD_SD1_DATA3__CSPI_SS2 */
1261 IMX_PIN_REG(MX53_PAD_SD1_DATA3, 0x680, 0x2F8, 6, 0x000, 0), /* MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB */
1262 IMX_PIN_REG(MX53_PAD_SD1_DATA3, 0x680, 0x2F8, 7, 0x000, 0), /* MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 */
1263 IMX_PIN_REG(MX53_PAD_SD2_CLK, 0x688, 0x2FC, 0, 0x000, 0), /* MX53_PAD_SD2_CLK__ESDHC2_CLK */
1264 IMX_PIN_REG(MX53_PAD_SD2_CLK, 0x688, 0x2FC, 1, 0x000, 0), /* MX53_PAD_SD2_CLK__GPIO1_10 */
1265 IMX_PIN_REG(MX53_PAD_SD2_CLK, 0x688, 0x2FC, 2, 0x840, 2), /* MX53_PAD_SD2_CLK__KPP_COL_5 */
1266 IMX_PIN_REG(MX53_PAD_SD2_CLK, 0x688, 0x2FC, 3, 0x73C, 1), /* MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS */
1267 IMX_PIN_REG(MX53_PAD_SD2_CLK, 0x688, 0x2FC, 5, 0x780, 3), /* MX53_PAD_SD2_CLK__CSPI_SCLK */
1268 IMX_PIN_REG(MX53_PAD_SD2_CLK, 0x688, 0x2FC, 7, 0x000, 0), /* MX53_PAD_SD2_CLK__SCC_RANDOM_V */
1269 IMX_PIN_REG(MX53_PAD_SD2_CMD, 0x68C, 0x300, 0, 0x000, 0), /* MX53_PAD_SD2_CMD__ESDHC2_CMD */
1270 IMX_PIN_REG(MX53_PAD_SD2_CMD, 0x68C, 0x300, 1, 0x000, 0), /* MX53_PAD_SD2_CMD__GPIO1_11 */
1271 IMX_PIN_REG(MX53_PAD_SD2_CMD, 0x68C, 0x300, 2, 0x84C, 1), /* MX53_PAD_SD2_CMD__KPP_ROW_5 */
1272 IMX_PIN_REG(MX53_PAD_SD2_CMD, 0x68C, 0x300, 3, 0x738, 1), /* MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC */
1273 IMX_PIN_REG(MX53_PAD_SD2_CMD, 0x68C, 0x300, 5, 0x788, 3), /* MX53_PAD_SD2_CMD__CSPI_MOSI */
1274 IMX_PIN_REG(MX53_PAD_SD2_CMD, 0x68C, 0x300, 7, 0x000, 0), /* MX53_PAD_SD2_CMD__SCC_RANDOM */
1275 IMX_PIN_REG(MX53_PAD_SD2_DATA3, 0x690, 0x304, 0, 0x000, 0), /* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */
1276 IMX_PIN_REG(MX53_PAD_SD2_DATA3, 0x690, 0x304, 1, 0x000, 0), /* MX53_PAD_SD2_DATA3__GPIO1_12 */
1277 IMX_PIN_REG(MX53_PAD_SD2_DATA3, 0x690, 0x304, 2, 0x844, 1), /* MX53_PAD_SD2_DATA3__KPP_COL_6 */
1278 IMX_PIN_REG(MX53_PAD_SD2_DATA3, 0x690, 0x304, 3, 0x740, 1), /* MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC */
1279 IMX_PIN_REG(MX53_PAD_SD2_DATA3, 0x690, 0x304, 5, 0x794, 3), /* MX53_PAD_SD2_DATA3__CSPI_SS2 */
1280 IMX_PIN_REG(MX53_PAD_SD2_DATA3, 0x690, 0x304, 7, 0x000, 0), /* MX53_PAD_SD2_DATA3__SJC_DONE */
1281 IMX_PIN_REG(MX53_PAD_SD2_DATA2, 0x694, 0x308, 0, 0x000, 0), /* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */
1282 IMX_PIN_REG(MX53_PAD_SD2_DATA2, 0x694, 0x308, 1, 0x000, 0), /* MX53_PAD_SD2_DATA2__GPIO1_13 */
1283 IMX_PIN_REG(MX53_PAD_SD2_DATA2, 0x694, 0x308, 2, 0x850, 1), /* MX53_PAD_SD2_DATA2__KPP_ROW_6 */
1284 IMX_PIN_REG(MX53_PAD_SD2_DATA2, 0x694, 0x308, 3, 0x734, 1), /* MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD */
1285 IMX_PIN_REG(MX53_PAD_SD2_DATA2, 0x694, 0x308, 5, 0x790, 3), /* MX53_PAD_SD2_DATA2__CSPI_SS1 */
1286 IMX_PIN_REG(MX53_PAD_SD2_DATA2, 0x694, 0x308, 7, 0x000, 0), /* MX53_PAD_SD2_DATA2__SJC_FAIL */
1287 IMX_PIN_REG(MX53_PAD_SD2_DATA1, 0x698, 0x30C, 0, 0x000, 0), /* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */
1288 IMX_PIN_REG(MX53_PAD_SD2_DATA1, 0x698, 0x30C, 1, 0x000, 0), /* MX53_PAD_SD2_DATA1__GPIO1_14 */
1289 IMX_PIN_REG(MX53_PAD_SD2_DATA1, 0x698, 0x30C, 2, 0x848, 1), /* MX53_PAD_SD2_DATA1__KPP_COL_7 */
1290 IMX_PIN_REG(MX53_PAD_SD2_DATA1, 0x698, 0x30C, 3, 0x744, 0), /* MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS */
1291 IMX_PIN_REG(MX53_PAD_SD2_DATA1, 0x698, 0x30C, 5, 0x78C, 4), /* MX53_PAD_SD2_DATA1__CSPI_SS0 */
1292 IMX_PIN_REG(MX53_PAD_SD2_DATA1, 0x698, 0x30C, 7, 0x000, 0), /* MX53_PAD_SD2_DATA1__RTIC_SEC_VIO */
1293 IMX_PIN_REG(MX53_PAD_SD2_DATA0, 0x69C, 0x310, 0, 0x000, 0), /* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */
1294 IMX_PIN_REG(MX53_PAD_SD2_DATA0, 0x69C, 0x310, 1, 0x000, 0), /* MX53_PAD_SD2_DATA0__GPIO1_15 */
1295 IMX_PIN_REG(MX53_PAD_SD2_DATA0, 0x69C, 0x310, 2, 0x854, 1), /* MX53_PAD_SD2_DATA0__KPP_ROW_7 */
1296 IMX_PIN_REG(MX53_PAD_SD2_DATA0, 0x69C, 0x310, 3, 0x730, 1), /* MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD */
1297 IMX_PIN_REG(MX53_PAD_SD2_DATA0, 0x69C, 0x310, 5, 0x784, 3), /* MX53_PAD_SD2_DATA0__CSPI_MISO */
1298 IMX_PIN_REG(MX53_PAD_SD2_DATA0, 0x69C, 0x310, 7, 0x000, 0), /* MX53_PAD_SD2_DATA0__RTIC_DONE_INT */
1299 IMX_PIN_REG(MX53_PAD_GPIO_0, 0x6A4, 0x314, 0, 0x000, 0), /* MX53_PAD_GPIO_0__CCM_CLKO */
1300 IMX_PIN_REG(MX53_PAD_GPIO_0, 0x6A4, 0x314, 1, 0x000, 0), /* MX53_PAD_GPIO_0__GPIO1_0 */
1301 IMX_PIN_REG(MX53_PAD_GPIO_0, 0x6A4, 0x314, 2, 0x840, 3), /* MX53_PAD_GPIO_0__KPP_COL_5 */
1302 IMX_PIN_REG(MX53_PAD_GPIO_0, 0x6A4, 0x314, 3, 0x000, 0), /* MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK */
1303 IMX_PIN_REG(MX53_PAD_GPIO_0, 0x6A4, 0x314, 4, 0x000, 0), /* MX53_PAD_GPIO_0__EPIT1_EPITO */
1304 IMX_PIN_REG(MX53_PAD_GPIO_0, 0x6A4, 0x314, 5, 0x000, 0), /* MX53_PAD_GPIO_0__SRTC_ALARM_DEB */
1305 IMX_PIN_REG(MX53_PAD_GPIO_0, 0x6A4, 0x314, 6, 0x000, 0), /* MX53_PAD_GPIO_0__USBOH3_USBH1_PWR */
1306 IMX_PIN_REG(MX53_PAD_GPIO_0, 0x6A4, 0x314, 7, 0x000, 0), /* MX53_PAD_GPIO_0__CSU_TD */
1307 IMX_PIN_REG(MX53_PAD_GPIO_1, 0x6A8, 0x318, 0, 0x7DC, 1), /* MX53_PAD_GPIO_1__ESAI1_SCKR */
1308 IMX_PIN_REG(MX53_PAD_GPIO_1, 0x6A8, 0x318, 1, 0x000, 0), /* MX53_PAD_GPIO_1__GPIO1_1 */
1309 IMX_PIN_REG(MX53_PAD_GPIO_1, 0x6A8, 0x318, 2, 0x84C, 2), /* MX53_PAD_GPIO_1__KPP_ROW_5 */
1310 IMX_PIN_REG(MX53_PAD_GPIO_1, 0x6A8, 0x318, 3, 0x000, 0), /* MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK */
1311 IMX_PIN_REG(MX53_PAD_GPIO_1, 0x6A8, 0x318, 4, 0x000, 0), /* MX53_PAD_GPIO_1__PWM2_PWMO */
1312 IMX_PIN_REG(MX53_PAD_GPIO_1, 0x6A8, 0x318, 5, 0x000, 0), /* MX53_PAD_GPIO_1__WDOG2_WDOG_B */
1313 IMX_PIN_REG(MX53_PAD_GPIO_1, 0x6A8, 0x318, 6, 0x000, 0), /* MX53_PAD_GPIO_1__ESDHC1_CD */
1314 IMX_PIN_REG(MX53_PAD_GPIO_1, 0x6A8, 0x318, 7, 0x000, 0), /* MX53_PAD_GPIO_1__SRC_TESTER_ACK */
1315 IMX_PIN_REG(MX53_PAD_GPIO_9, 0x6AC, 0x31C, 0, 0x7CC, 1), /* MX53_PAD_GPIO_9__ESAI1_FSR */
1316 IMX_PIN_REG(MX53_PAD_GPIO_9, 0x6AC, 0x31C, 1, 0x000, 0), /* MX53_PAD_GPIO_9__GPIO1_9 */
1317 IMX_PIN_REG(MX53_PAD_GPIO_9, 0x6AC, 0x31C, 2, 0x844, 2), /* MX53_PAD_GPIO_9__KPP_COL_6 */
1318 IMX_PIN_REG(MX53_PAD_GPIO_9, 0x6AC, 0x31C, 3, 0x000, 0), /* MX53_PAD_GPIO_9__CCM_REF_EN_B */
1319 IMX_PIN_REG(MX53_PAD_GPIO_9, 0x6AC, 0x31C, 4, 0x000, 0), /* MX53_PAD_GPIO_9__PWM1_PWMO */
1320 IMX_PIN_REG(MX53_PAD_GPIO_9, 0x6AC, 0x31C, 5, 0x000, 0), /* MX53_PAD_GPIO_9__WDOG1_WDOG_B */
1321 IMX_PIN_REG(MX53_PAD_GPIO_9, 0x6AC, 0x31C, 6, 0x7FC, 1), /* MX53_PAD_GPIO_9__ESDHC1_WP */
1322 IMX_PIN_REG(MX53_PAD_GPIO_9, 0x6AC, 0x31C, 7, 0x000, 0), /* MX53_PAD_GPIO_9__SCC_FAIL_STATE */
1323 IMX_PIN_REG(MX53_PAD_GPIO_3, 0x6B0, 0x320, 0, 0x7D4, 1), /* MX53_PAD_GPIO_3__ESAI1_HCKR */
1324 IMX_PIN_REG(MX53_PAD_GPIO_3, 0x6B0, 0x320, 1, 0x000, 0), /* MX53_PAD_GPIO_3__GPIO1_3 */
1325 IMX_PIN_REG(MX53_PAD_GPIO_3, 0x6B0, 0x320, 2, 0x824, 1), /* MX53_PAD_GPIO_3__I2C3_SCL */
1326 IMX_PIN_REG(MX53_PAD_GPIO_3, 0x6B0, 0x320, 3, 0x000, 0), /* MX53_PAD_GPIO_3__DPLLIP1_TOG_EN */
1327 IMX_PIN_REG(MX53_PAD_GPIO_3, 0x6B0, 0x320, 4, 0x000, 0), /* MX53_PAD_GPIO_3__CCM_CLKO2 */
1328 IMX_PIN_REG(MX53_PAD_GPIO_3, 0x6B0, 0x320, 5, 0x000, 0), /* MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 */
1329 IMX_PIN_REG(MX53_PAD_GPIO_3, 0x6B0, 0x320, 6, 0x8A0, 1), /* MX53_PAD_GPIO_3__USBOH3_USBH1_OC */
1330 IMX_PIN_REG(MX53_PAD_GPIO_3, 0x6B0, 0x320, 7, 0x858, 2), /* MX53_PAD_GPIO_3__MLB_MLBCLK */
1331 IMX_PIN_REG(MX53_PAD_GPIO_6, 0x6B4, 0x324, 0, 0x7E0, 1), /* MX53_PAD_GPIO_6__ESAI1_SCKT */
1332 IMX_PIN_REG(MX53_PAD_GPIO_6, 0x6B4, 0x324, 1, 0x000, 0), /* MX53_PAD_GPIO_6__GPIO1_6 */
1333 IMX_PIN_REG(MX53_PAD_GPIO_6, 0x6B4, 0x324, 2, 0x828, 1), /* MX53_PAD_GPIO_6__I2C3_SDA */
1334 IMX_PIN_REG(MX53_PAD_GPIO_6, 0x6B4, 0x324, 3, 0x000, 0), /* MX53_PAD_GPIO_6__CCM_CCM_OUT_0 */
1335 IMX_PIN_REG(MX53_PAD_GPIO_6, 0x6B4, 0x324, 4, 0x000, 0), /* MX53_PAD_GPIO_6__CSU_CSU_INT_DEB */
1336 IMX_PIN_REG(MX53_PAD_GPIO_6, 0x6B4, 0x324, 5, 0x000, 0), /* MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 */
1337 IMX_PIN_REG(MX53_PAD_GPIO_6, 0x6B4, 0x324, 6, 0x000, 0), /* MX53_PAD_GPIO_6__ESDHC2_LCTL */
1338 IMX_PIN_REG(MX53_PAD_GPIO_6, 0x6B4, 0x324, 7, 0x860, 2), /* MX53_PAD_GPIO_6__MLB_MLBSIG */
1339 IMX_PIN_REG(MX53_PAD_GPIO_2, 0x6B8, 0x328, 0, 0x7D0, 1), /* MX53_PAD_GPIO_2__ESAI1_FST */
1340 IMX_PIN_REG(MX53_PAD_GPIO_2, 0x6B8, 0x328, 1, 0x000, 0), /* MX53_PAD_GPIO_2__GPIO1_2 */
1341 IMX_PIN_REG(MX53_PAD_GPIO_2, 0x6B8, 0x328, 2, 0x850, 2), /* MX53_PAD_GPIO_2__KPP_ROW_6 */
1342 IMX_PIN_REG(MX53_PAD_GPIO_2, 0x6B8, 0x328, 3, 0x000, 0), /* MX53_PAD_GPIO_2__CCM_CCM_OUT_1 */
1343 IMX_PIN_REG(MX53_PAD_GPIO_2, 0x6B8, 0x328, 4, 0x000, 0), /* MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 */
1344 IMX_PIN_REG(MX53_PAD_GPIO_2, 0x6B8, 0x328, 5, 0x000, 0), /* MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 */
1345 IMX_PIN_REG(MX53_PAD_GPIO_2, 0x6B8, 0x328, 6, 0x000, 0), /* MX53_PAD_GPIO_2__ESDHC2_WP */
1346 IMX_PIN_REG(MX53_PAD_GPIO_2, 0x6B8, 0x328, 7, 0x85C, 2), /* MX53_PAD_GPIO_2__MLB_MLBDAT */
1347 IMX_PIN_REG(MX53_PAD_GPIO_4, 0x6BC, 0x32C, 0, 0x7D8, 1), /* MX53_PAD_GPIO_4__ESAI1_HCKT */
1348 IMX_PIN_REG(MX53_PAD_GPIO_4, 0x6BC, 0x32C, 1, 0x000, 0), /* MX53_PAD_GPIO_4__GPIO1_4 */
1349 IMX_PIN_REG(MX53_PAD_GPIO_4, 0x6BC, 0x32C, 2, 0x848, 2), /* MX53_PAD_GPIO_4__KPP_COL_7 */
1350 IMX_PIN_REG(MX53_PAD_GPIO_4, 0x6BC, 0x32C, 3, 0x000, 0), /* MX53_PAD_GPIO_4__CCM_CCM_OUT_2 */
1351 IMX_PIN_REG(MX53_PAD_GPIO_4, 0x6BC, 0x32C, 4, 0x000, 0), /* MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 */
1352 IMX_PIN_REG(MX53_PAD_GPIO_4, 0x6BC, 0x32C, 5, 0x000, 0), /* MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 */
1353 IMX_PIN_REG(MX53_PAD_GPIO_4, 0x6BC, 0x32C, 6, 0x000, 0), /* MX53_PAD_GPIO_4__ESDHC2_CD */
1354 IMX_PIN_REG(MX53_PAD_GPIO_4, 0x6BC, 0x32C, 7, 0x000, 0), /* MX53_PAD_GPIO_4__SCC_SEC_STATE */
1355 IMX_PIN_REG(MX53_PAD_GPIO_5, 0x6C0, 0x330, 0, 0x7EC, 1), /* MX53_PAD_GPIO_5__ESAI1_TX2_RX3 */
1356 IMX_PIN_REG(MX53_PAD_GPIO_5, 0x6C0, 0x330, 1, 0x000, 0), /* MX53_PAD_GPIO_5__GPIO1_5 */
1357 IMX_PIN_REG(MX53_PAD_GPIO_5, 0x6C0, 0x330, 2, 0x854, 2), /* MX53_PAD_GPIO_5__KPP_ROW_7 */
1358 IMX_PIN_REG(MX53_PAD_GPIO_5, 0x6C0, 0x330, 3, 0x000, 0), /* MX53_PAD_GPIO_5__CCM_CLKO */
1359 IMX_PIN_REG(MX53_PAD_GPIO_5, 0x6C0, 0x330, 4, 0x000, 0), /* MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 */
1360 IMX_PIN_REG(MX53_PAD_GPIO_5, 0x6C0, 0x330, 5, 0x000, 0), /* MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 */
1361 IMX_PIN_REG(MX53_PAD_GPIO_5, 0x6C0, 0x330, 6, 0x824, 2), /* MX53_PAD_GPIO_5__I2C3_SCL */
1362 IMX_PIN_REG(MX53_PAD_GPIO_5, 0x6C0, 0x330, 7, 0x770, 1), /* MX53_PAD_GPIO_5__CCM_PLL1_BYP */
1363 IMX_PIN_REG(MX53_PAD_GPIO_7, 0x6C4, 0x334, 0, 0x7F4, 1), /* MX53_PAD_GPIO_7__ESAI1_TX4_RX1 */
1364 IMX_PIN_REG(MX53_PAD_GPIO_7, 0x6C4, 0x334, 1, 0x000, 0), /* MX53_PAD_GPIO_7__GPIO1_7 */
1365 IMX_PIN_REG(MX53_PAD_GPIO_7, 0x6C4, 0x334, 2, 0x000, 0), /* MX53_PAD_GPIO_7__EPIT1_EPITO */
1366 IMX_PIN_REG(MX53_PAD_GPIO_7, 0x6C4, 0x334, 3, 0x000, 0), /* MX53_PAD_GPIO_7__CAN1_TXCAN */
1367 IMX_PIN_REG(MX53_PAD_GPIO_7, 0x6C4, 0x334, 4, 0x000, 0), /* MX53_PAD_GPIO_7__UART2_TXD_MUX */
1368 IMX_PIN_REG(MX53_PAD_GPIO_7, 0x6C4, 0x334, 5, 0x80C, 1), /* MX53_PAD_GPIO_7__FIRI_RXD */
1369 IMX_PIN_REG(MX53_PAD_GPIO_7, 0x6C4, 0x334, 6, 0x000, 0), /* MX53_PAD_GPIO_7__SPDIF_PLOCK */
1370 IMX_PIN_REG(MX53_PAD_GPIO_7, 0x6C4, 0x334, 7, 0x774, 1), /* MX53_PAD_GPIO_7__CCM_PLL2_BYP */
1371 IMX_PIN_REG(MX53_PAD_GPIO_8, 0x6C8, 0x338, 0, 0x7F8, 1), /* MX53_PAD_GPIO_8__ESAI1_TX5_RX0 */
1372 IMX_PIN_REG(MX53_PAD_GPIO_8, 0x6C8, 0x338, 1, 0x000, 0), /* MX53_PAD_GPIO_8__GPIO1_8 */
1373 IMX_PIN_REG(MX53_PAD_GPIO_8, 0x6C8, 0x338, 2, 0x000, 0), /* MX53_PAD_GPIO_8__EPIT2_EPITO */
1374 IMX_PIN_REG(MX53_PAD_GPIO_8, 0x6C8, 0x338, 3, 0x760, 3), /* MX53_PAD_GPIO_8__CAN1_RXCAN */
1375 IMX_PIN_REG(MX53_PAD_GPIO_8, 0x6C8, 0x338, 4, 0x880, 5), /* MX53_PAD_GPIO_8__UART2_RXD_MUX */
1376 IMX_PIN_REG(MX53_PAD_GPIO_8, 0x6C8, 0x338, 5, 0x000, 0), /* MX53_PAD_GPIO_8__FIRI_TXD */
1377 IMX_PIN_REG(MX53_PAD_GPIO_8, 0x6C8, 0x338, 6, 0x000, 0), /* MX53_PAD_GPIO_8__SPDIF_SRCLK */
1378 IMX_PIN_REG(MX53_PAD_GPIO_8, 0x6C8, 0x338, 7, 0x778, 1), /* MX53_PAD_GPIO_8__CCM_PLL3_BYP */
1379 IMX_PIN_REG(MX53_PAD_GPIO_16, 0x6CC, 0x33C, 0, 0x7F0, 1), /* MX53_PAD_GPIO_16__ESAI1_TX3_RX2 */
1380 IMX_PIN_REG(MX53_PAD_GPIO_16, 0x6CC, 0x33C, 1, 0x000, 0), /* MX53_PAD_GPIO_16__GPIO7_11 */
1381 IMX_PIN_REG(MX53_PAD_GPIO_16, 0x6CC, 0x33C, 2, 0x000, 0), /* MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT */
1382 IMX_PIN_REG(MX53_PAD_GPIO_16, 0x6CC, 0x33C, 4, 0x000, 0), /* MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 */
1383 IMX_PIN_REG(MX53_PAD_GPIO_16, 0x6CC, 0x33C, 5, 0x870, 1), /* MX53_PAD_GPIO_16__SPDIF_IN1 */
1384 IMX_PIN_REG(MX53_PAD_GPIO_16, 0x6CC, 0x33C, 6, 0x828, 2), /* MX53_PAD_GPIO_16__I2C3_SDA */
1385 IMX_PIN_REG(MX53_PAD_GPIO_16, 0x6CC, 0x33C, 7, 0x000, 0), /* MX53_PAD_GPIO_16__SJC_DE_B */
1386 IMX_PIN_REG(MX53_PAD_GPIO_17, 0x6D0, 0x340, 0, 0x7E4, 1), /* MX53_PAD_GPIO_17__ESAI1_TX0 */
1387 IMX_PIN_REG(MX53_PAD_GPIO_17, 0x6D0, 0x340, 1, 0x000, 0), /* MX53_PAD_GPIO_17__GPIO7_12 */
1388 IMX_PIN_REG(MX53_PAD_GPIO_17, 0x6D0, 0x340, 2, 0x868, 1), /* MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 */
1389 IMX_PIN_REG(MX53_PAD_GPIO_17, 0x6D0, 0x340, 3, 0x810, 1), /* MX53_PAD_GPIO_17__GPC_PMIC_RDY */
1390 IMX_PIN_REG(MX53_PAD_GPIO_17, 0x6D0, 0x340, 4, 0x000, 0), /* MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG */
1391 IMX_PIN_REG(MX53_PAD_GPIO_17, 0x6D0, 0x340, 5, 0x000, 0), /* MX53_PAD_GPIO_17__SPDIF_OUT1 */
1392 IMX_PIN_REG(MX53_PAD_GPIO_17, 0x6D0, 0x340, 6, 0x000, 0), /* MX53_PAD_GPIO_17__IPU_SNOOP2 */
1393 IMX_PIN_REG(MX53_PAD_GPIO_17, 0x6D0, 0x340, 7, 0x000, 0), /* MX53_PAD_GPIO_17__SJC_JTAG_ACT */
1394 IMX_PIN_REG(MX53_PAD_GPIO_18, 0x6D4, 0x344, 0, 0x7E8, 1), /* MX53_PAD_GPIO_18__ESAI1_TX1 */
1395 IMX_PIN_REG(MX53_PAD_GPIO_18, 0x6D4, 0x344, 1, 0x000, 0), /* MX53_PAD_GPIO_18__GPIO7_13 */
1396 IMX_PIN_REG(MX53_PAD_GPIO_18, 0x6D4, 0x344, 2, 0x86C, 1), /* MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 */
1397 IMX_PIN_REG(MX53_PAD_GPIO_18, 0x6D4, 0x344, 3, 0x864, 1), /* MX53_PAD_GPIO_18__OWIRE_LINE */
1398 IMX_PIN_REG(MX53_PAD_GPIO_18, 0x6D4, 0x344, 4, 0x000, 0), /* MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG */
1399 IMX_PIN_REG(MX53_PAD_GPIO_18, 0x6D4, 0x344, 5, 0x768, 1), /* MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK */
1400 IMX_PIN_REG(MX53_PAD_GPIO_18, 0x6D4, 0x344, 6, 0x000, 0), /* MX53_PAD_GPIO_18__ESDHC1_LCTL */
1401 IMX_PIN_REG(MX53_PAD_GPIO_18, 0x6D4, 0x344, 7, 0x000, 0), /* MX53_PAD_GPIO_18__SRC_SYSTEM_RST */
1402};
1403
1404/* Pad names for the pinmux subsystem */
1405static const struct pinctrl_pin_desc imx53_pinctrl_pads[] = {
1406 IMX_PINCTRL_PIN(MX53_PAD_GPIO_19),
1407 IMX_PINCTRL_PIN(MX53_PAD_KEY_COL0),
1408 IMX_PINCTRL_PIN(MX53_PAD_KEY_ROW0),
1409 IMX_PINCTRL_PIN(MX53_PAD_KEY_COL1),
1410 IMX_PINCTRL_PIN(MX53_PAD_KEY_ROW1),
1411 IMX_PINCTRL_PIN(MX53_PAD_KEY_COL2),
1412 IMX_PINCTRL_PIN(MX53_PAD_KEY_ROW2),
1413 IMX_PINCTRL_PIN(MX53_PAD_KEY_COL3),
1414 IMX_PINCTRL_PIN(MX53_PAD_KEY_ROW3),
1415 IMX_PINCTRL_PIN(MX53_PAD_KEY_COL4),
1416 IMX_PINCTRL_PIN(MX53_PAD_KEY_ROW4),
1417 IMX_PINCTRL_PIN(MX53_PAD_DI0_DISP_CLK),
1418 IMX_PINCTRL_PIN(MX53_PAD_DI0_PIN15),
1419 IMX_PINCTRL_PIN(MX53_PAD_DI0_PIN2),
1420 IMX_PINCTRL_PIN(MX53_PAD_DI0_PIN3),
1421 IMX_PINCTRL_PIN(MX53_PAD_DI0_PIN4),
1422 IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT0),
1423 IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT1),
1424 IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT2),
1425 IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT3),
1426 IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT4),
1427 IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT5),
1428 IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT6),
1429 IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT7),
1430 IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT8),
1431 IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT9),
1432 IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT10),
1433 IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT11),
1434 IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT12),
1435 IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT13),
1436 IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT14),
1437 IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT15),
1438 IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT16),
1439 IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT17),
1440 IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT18),
1441 IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT19),
1442 IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT20),
1443 IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT21),
1444 IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT22),
1445 IMX_PINCTRL_PIN(MX53_PAD_DISP0_DAT23),
1446 IMX_PINCTRL_PIN(MX53_PAD_CSI0_PIXCLK),
1447 IMX_PINCTRL_PIN(MX53_PAD_CSI0_MCLK),
1448 IMX_PINCTRL_PIN(MX53_PAD_CSI0_DATA_EN),
1449 IMX_PINCTRL_PIN(MX53_PAD_CSI0_VSYNC),
1450 IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT4),
1451 IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT5),
1452 IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT6),
1453 IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT7),
1454 IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT8),
1455 IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT9),
1456 IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT10),
1457 IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT11),
1458 IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT12),
1459 IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT13),
1460 IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT14),
1461 IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT15),
1462 IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT16),
1463 IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT17),
1464 IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT18),
1465 IMX_PINCTRL_PIN(MX53_PAD_CSI0_DAT19),
1466 IMX_PINCTRL_PIN(MX53_PAD_EIM_A25),
1467 IMX_PINCTRL_PIN(MX53_PAD_EIM_EB2),
1468 IMX_PINCTRL_PIN(MX53_PAD_EIM_D16),
1469 IMX_PINCTRL_PIN(MX53_PAD_EIM_D17),
1470 IMX_PINCTRL_PIN(MX53_PAD_EIM_D18),
1471 IMX_PINCTRL_PIN(MX53_PAD_EIM_D19),
1472 IMX_PINCTRL_PIN(MX53_PAD_EIM_D20),
1473 IMX_PINCTRL_PIN(MX53_PAD_EIM_D21),
1474 IMX_PINCTRL_PIN(MX53_PAD_EIM_D22),
1475 IMX_PINCTRL_PIN(MX53_PAD_EIM_D23),
1476 IMX_PINCTRL_PIN(MX53_PAD_EIM_EB3),
1477 IMX_PINCTRL_PIN(MX53_PAD_EIM_D24),
1478 IMX_PINCTRL_PIN(MX53_PAD_EIM_D25),
1479 IMX_PINCTRL_PIN(MX53_PAD_EIM_D26),
1480 IMX_PINCTRL_PIN(MX53_PAD_EIM_D27),
1481 IMX_PINCTRL_PIN(MX53_PAD_EIM_D28),
1482 IMX_PINCTRL_PIN(MX53_PAD_EIM_D29),
1483 IMX_PINCTRL_PIN(MX53_PAD_EIM_D30),
1484 IMX_PINCTRL_PIN(MX53_PAD_EIM_D31),
1485 IMX_PINCTRL_PIN(MX53_PAD_EIM_A24),
1486 IMX_PINCTRL_PIN(MX53_PAD_EIM_A23),
1487 IMX_PINCTRL_PIN(MX53_PAD_EIM_A22),
1488 IMX_PINCTRL_PIN(MX53_PAD_EIM_A21),
1489 IMX_PINCTRL_PIN(MX53_PAD_EIM_A20),
1490 IMX_PINCTRL_PIN(MX53_PAD_EIM_A19),
1491 IMX_PINCTRL_PIN(MX53_PAD_EIM_A18),
1492 IMX_PINCTRL_PIN(MX53_PAD_EIM_A17),
1493 IMX_PINCTRL_PIN(MX53_PAD_EIM_A16),
1494 IMX_PINCTRL_PIN(MX53_PAD_EIM_CS0),
1495 IMX_PINCTRL_PIN(MX53_PAD_EIM_CS1),
1496 IMX_PINCTRL_PIN(MX53_PAD_EIM_OE),
1497 IMX_PINCTRL_PIN(MX53_PAD_EIM_RW),
1498 IMX_PINCTRL_PIN(MX53_PAD_EIM_LBA),
1499 IMX_PINCTRL_PIN(MX53_PAD_EIM_EB0),
1500 IMX_PINCTRL_PIN(MX53_PAD_EIM_EB1),
1501 IMX_PINCTRL_PIN(MX53_PAD_EIM_DA0),
1502 IMX_PINCTRL_PIN(MX53_PAD_EIM_DA1),
1503 IMX_PINCTRL_PIN(MX53_PAD_EIM_DA2),
1504 IMX_PINCTRL_PIN(MX53_PAD_EIM_DA3),
1505 IMX_PINCTRL_PIN(MX53_PAD_EIM_DA4),
1506 IMX_PINCTRL_PIN(MX53_PAD_EIM_DA5),
1507 IMX_PINCTRL_PIN(MX53_PAD_EIM_DA6),
1508 IMX_PINCTRL_PIN(MX53_PAD_EIM_DA7),
1509 IMX_PINCTRL_PIN(MX53_PAD_EIM_DA8),
1510 IMX_PINCTRL_PIN(MX53_PAD_EIM_DA9),
1511 IMX_PINCTRL_PIN(MX53_PAD_EIM_DA10),
1512 IMX_PINCTRL_PIN(MX53_PAD_EIM_DA11),
1513 IMX_PINCTRL_PIN(MX53_PAD_EIM_DA12),
1514 IMX_PINCTRL_PIN(MX53_PAD_EIM_DA13),
1515 IMX_PINCTRL_PIN(MX53_PAD_EIM_DA14),
1516 IMX_PINCTRL_PIN(MX53_PAD_EIM_DA15),
1517 IMX_PINCTRL_PIN(MX53_PAD_NANDF_WE_B),
1518 IMX_PINCTRL_PIN(MX53_PAD_NANDF_RE_B),
1519 IMX_PINCTRL_PIN(MX53_PAD_EIM_WAIT),
1520 IMX_PINCTRL_PIN(MX53_PAD_LVDS1_TX3_P),
1521 IMX_PINCTRL_PIN(MX53_PAD_LVDS1_TX2_P),
1522 IMX_PINCTRL_PIN(MX53_PAD_LVDS1_CLK_P),
1523 IMX_PINCTRL_PIN(MX53_PAD_LVDS1_TX1_P),
1524 IMX_PINCTRL_PIN(MX53_PAD_LVDS1_TX0_P),
1525 IMX_PINCTRL_PIN(MX53_PAD_LVDS0_TX3_P),
1526 IMX_PINCTRL_PIN(MX53_PAD_LVDS0_CLK_P),
1527 IMX_PINCTRL_PIN(MX53_PAD_LVDS0_TX2_P),
1528 IMX_PINCTRL_PIN(MX53_PAD_LVDS0_TX1_P),
1529 IMX_PINCTRL_PIN(MX53_PAD_LVDS0_TX0_P),
1530 IMX_PINCTRL_PIN(MX53_PAD_GPIO_10),
1531 IMX_PINCTRL_PIN(MX53_PAD_GPIO_11),
1532 IMX_PINCTRL_PIN(MX53_PAD_GPIO_12),
1533 IMX_PINCTRL_PIN(MX53_PAD_GPIO_13),
1534 IMX_PINCTRL_PIN(MX53_PAD_GPIO_14),
1535 IMX_PINCTRL_PIN(MX53_PAD_NANDF_CLE),
1536 IMX_PINCTRL_PIN(MX53_PAD_NANDF_ALE),
1537 IMX_PINCTRL_PIN(MX53_PAD_NANDF_WP_B),
1538 IMX_PINCTRL_PIN(MX53_PAD_NANDF_RB0),
1539 IMX_PINCTRL_PIN(MX53_PAD_NANDF_CS0),
1540 IMX_PINCTRL_PIN(MX53_PAD_NANDF_CS1),
1541 IMX_PINCTRL_PIN(MX53_PAD_NANDF_CS2),
1542 IMX_PINCTRL_PIN(MX53_PAD_NANDF_CS3),
1543 IMX_PINCTRL_PIN(MX53_PAD_FEC_MDIO),
1544 IMX_PINCTRL_PIN(MX53_PAD_FEC_REF_CLK),
1545 IMX_PINCTRL_PIN(MX53_PAD_FEC_RX_ER),
1546 IMX_PINCTRL_PIN(MX53_PAD_FEC_CRS_DV),
1547 IMX_PINCTRL_PIN(MX53_PAD_FEC_RXD1),
1548 IMX_PINCTRL_PIN(MX53_PAD_FEC_RXD0),
1549 IMX_PINCTRL_PIN(MX53_PAD_FEC_TX_EN),
1550 IMX_PINCTRL_PIN(MX53_PAD_FEC_TXD1),
1551 IMX_PINCTRL_PIN(MX53_PAD_FEC_TXD0),
1552 IMX_PINCTRL_PIN(MX53_PAD_FEC_MDC),
1553 IMX_PINCTRL_PIN(MX53_PAD_PATA_DIOW),
1554 IMX_PINCTRL_PIN(MX53_PAD_PATA_DMACK),
1555 IMX_PINCTRL_PIN(MX53_PAD_PATA_DMARQ),
1556 IMX_PINCTRL_PIN(MX53_PAD_PATA_BUFFER_EN),
1557 IMX_PINCTRL_PIN(MX53_PAD_PATA_INTRQ),
1558 IMX_PINCTRL_PIN(MX53_PAD_PATA_DIOR),
1559 IMX_PINCTRL_PIN(MX53_PAD_PATA_RESET_B),
1560 IMX_PINCTRL_PIN(MX53_PAD_PATA_IORDY),
1561 IMX_PINCTRL_PIN(MX53_PAD_PATA_DA_0),
1562 IMX_PINCTRL_PIN(MX53_PAD_PATA_DA_1),
1563 IMX_PINCTRL_PIN(MX53_PAD_PATA_DA_2),
1564 IMX_PINCTRL_PIN(MX53_PAD_PATA_CS_0),
1565 IMX_PINCTRL_PIN(MX53_PAD_PATA_CS_1),
1566 IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA0),
1567 IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA1),
1568 IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA2),
1569 IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA3),
1570 IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA4),
1571 IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA5),
1572 IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA6),
1573 IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA7),
1574 IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA8),
1575 IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA9),
1576 IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA10),
1577 IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA11),
1578 IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA12),
1579 IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA13),
1580 IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA14),
1581 IMX_PINCTRL_PIN(MX53_PAD_PATA_DATA15),
1582 IMX_PINCTRL_PIN(MX53_PAD_SD1_DATA0),
1583 IMX_PINCTRL_PIN(MX53_PAD_SD1_DATA1),
1584 IMX_PINCTRL_PIN(MX53_PAD_SD1_CMD),
1585 IMX_PINCTRL_PIN(MX53_PAD_SD1_DATA2),
1586 IMX_PINCTRL_PIN(MX53_PAD_SD1_CLK),
1587 IMX_PINCTRL_PIN(MX53_PAD_SD1_DATA3),
1588 IMX_PINCTRL_PIN(MX53_PAD_SD2_CLK),
1589 IMX_PINCTRL_PIN(MX53_PAD_SD2_CMD),
1590 IMX_PINCTRL_PIN(MX53_PAD_SD2_DATA3),
1591 IMX_PINCTRL_PIN(MX53_PAD_SD2_DATA2),
1592 IMX_PINCTRL_PIN(MX53_PAD_SD2_DATA1),
1593 IMX_PINCTRL_PIN(MX53_PAD_SD2_DATA0),
1594 IMX_PINCTRL_PIN(MX53_PAD_GPIO_0),
1595 IMX_PINCTRL_PIN(MX53_PAD_GPIO_1),
1596 IMX_PINCTRL_PIN(MX53_PAD_GPIO_9),
1597 IMX_PINCTRL_PIN(MX53_PAD_GPIO_3),
1598 IMX_PINCTRL_PIN(MX53_PAD_GPIO_6),
1599 IMX_PINCTRL_PIN(MX53_PAD_GPIO_2),
1600 IMX_PINCTRL_PIN(MX53_PAD_GPIO_4),
1601 IMX_PINCTRL_PIN(MX53_PAD_GPIO_5),
1602 IMX_PINCTRL_PIN(MX53_PAD_GPIO_7),
1603 IMX_PINCTRL_PIN(MX53_PAD_GPIO_8),
1604 IMX_PINCTRL_PIN(MX53_PAD_GPIO_16),
1605 IMX_PINCTRL_PIN(MX53_PAD_GPIO_17),
1606 IMX_PINCTRL_PIN(MX53_PAD_GPIO_18),
1607};
1608
1609static struct imx_pinctrl_soc_info imx53_pinctrl_info = {
1610 .pins = imx53_pinctrl_pads,
1611 .npins = ARRAY_SIZE(imx53_pinctrl_pads),
1612 .pin_regs = imx53_pin_regs,
1613 .npin_regs = ARRAY_SIZE(imx53_pin_regs),
1614};
1615
1616static struct of_device_id imx53_pinctrl_of_match[] __devinitdata = {
1617 { .compatible = "fsl,imx53-iomuxc", },
1618 { /* sentinel */ }
1619};
1620
1621static int __devinit imx53_pinctrl_probe(struct platform_device *pdev)
1622{
1623 return imx_pinctrl_probe(pdev, &imx53_pinctrl_info);
1624}
1625
1626static struct platform_driver imx53_pinctrl_driver = {
1627 .driver = {
1628 .name = "imx53-pinctrl",
1629 .owner = THIS_MODULE,
1630 .of_match_table = of_match_ptr(imx53_pinctrl_of_match),
1631 },
1632 .probe = imx53_pinctrl_probe,
1633 .remove = __devexit_p(imx_pinctrl_remove),
1634};
1635
1636static int __init imx53_pinctrl_init(void)
1637{
1638 return platform_driver_register(&imx53_pinctrl_driver);
1639}
1640arch_initcall(imx53_pinctrl_init);
1641
1642static void __exit imx53_pinctrl_exit(void)
1643{
1644 platform_driver_unregister(&imx53_pinctrl_driver);
1645}
1646module_exit(imx53_pinctrl_exit);
1647MODULE_AUTHOR("Dong Aisheng <dong.aisheng@linaro.org>");
1648MODULE_DESCRIPTION("Freescale IMX53 pinctrl driver");
1649MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-imx6q.c b/drivers/pinctrl/pinctrl-imx6q.c
new file mode 100644
index 00000000000..7737d4d71a3
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx6q.c
@@ -0,0 +1,2331 @@
1/*
2 * imx6q pinctrl driver based on imx pinmux core
3 *
4 * Copyright (C) 2012 Freescale Semiconductor, Inc.
5 * Copyright (C) 2012 Linaro, Inc.
6 *
7 * Author: Dong Aisheng <dong.aisheng@linaro.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#include <linux/err.h>
16#include <linux/init.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/pinctrl/pinctrl.h>
22
23#include "pinctrl-imx.h"
24
25enum imx6q_pads {
26 MX6Q_PAD_SD2_DAT1 = 0,
27 MX6Q_PAD_SD2_DAT2 = 1,
28 MX6Q_PAD_SD2_DAT0 = 2,
29 MX6Q_PAD_RGMII_TXC = 3,
30 MX6Q_PAD_RGMII_TD0 = 4,
31 MX6Q_PAD_RGMII_TD1 = 5,
32 MX6Q_PAD_RGMII_TD2 = 6,
33 MX6Q_PAD_RGMII_TD3 = 7,
34 MX6Q_PAD_RGMII_RX_CTL = 8,
35 MX6Q_PAD_RGMII_RD0 = 9,
36 MX6Q_PAD_RGMII_TX_CTL = 10,
37 MX6Q_PAD_RGMII_RD1 = 11,
38 MX6Q_PAD_RGMII_RD2 = 12,
39 MX6Q_PAD_RGMII_RD3 = 13,
40 MX6Q_PAD_RGMII_RXC = 14,
41 MX6Q_PAD_EIM_A25 = 15,
42 MX6Q_PAD_EIM_EB2 = 16,
43 MX6Q_PAD_EIM_D16 = 17,
44 MX6Q_PAD_EIM_D17 = 18,
45 MX6Q_PAD_EIM_D18 = 19,
46 MX6Q_PAD_EIM_D19 = 20,
47 MX6Q_PAD_EIM_D20 = 21,
48 MX6Q_PAD_EIM_D21 = 22,
49 MX6Q_PAD_EIM_D22 = 23,
50 MX6Q_PAD_EIM_D23 = 24,
51 MX6Q_PAD_EIM_EB3 = 25,
52 MX6Q_PAD_EIM_D24 = 26,
53 MX6Q_PAD_EIM_D25 = 27,
54 MX6Q_PAD_EIM_D26 = 28,
55 MX6Q_PAD_EIM_D27 = 29,
56 MX6Q_PAD_EIM_D28 = 30,
57 MX6Q_PAD_EIM_D29 = 31,
58 MX6Q_PAD_EIM_D30 = 32,
59 MX6Q_PAD_EIM_D31 = 33,
60 MX6Q_PAD_EIM_A24 = 34,
61 MX6Q_PAD_EIM_A23 = 35,
62 MX6Q_PAD_EIM_A22 = 36,
63 MX6Q_PAD_EIM_A21 = 37,
64 MX6Q_PAD_EIM_A20 = 38,
65 MX6Q_PAD_EIM_A19 = 39,
66 MX6Q_PAD_EIM_A18 = 40,
67 MX6Q_PAD_EIM_A17 = 41,
68 MX6Q_PAD_EIM_A16 = 42,
69 MX6Q_PAD_EIM_CS0 = 43,
70 MX6Q_PAD_EIM_CS1 = 44,
71 MX6Q_PAD_EIM_OE = 45,
72 MX6Q_PAD_EIM_RW = 46,
73 MX6Q_PAD_EIM_LBA = 47,
74 MX6Q_PAD_EIM_EB0 = 48,
75 MX6Q_PAD_EIM_EB1 = 49,
76 MX6Q_PAD_EIM_DA0 = 50,
77 MX6Q_PAD_EIM_DA1 = 51,
78 MX6Q_PAD_EIM_DA2 = 52,
79 MX6Q_PAD_EIM_DA3 = 53,
80 MX6Q_PAD_EIM_DA4 = 54,
81 MX6Q_PAD_EIM_DA5 = 55,
82 MX6Q_PAD_EIM_DA6 = 56,
83 MX6Q_PAD_EIM_DA7 = 57,
84 MX6Q_PAD_EIM_DA8 = 58,
85 MX6Q_PAD_EIM_DA9 = 59,
86 MX6Q_PAD_EIM_DA10 = 60,
87 MX6Q_PAD_EIM_DA11 = 61,
88 MX6Q_PAD_EIM_DA12 = 62,
89 MX6Q_PAD_EIM_DA13 = 63,
90 MX6Q_PAD_EIM_DA14 = 64,
91 MX6Q_PAD_EIM_DA15 = 65,
92 MX6Q_PAD_EIM_WAIT = 66,
93 MX6Q_PAD_EIM_BCLK = 67,
94 MX6Q_PAD_DI0_DISP_CLK = 68,
95 MX6Q_PAD_DI0_PIN15 = 69,
96 MX6Q_PAD_DI0_PIN2 = 70,
97 MX6Q_PAD_DI0_PIN3 = 71,
98 MX6Q_PAD_DI0_PIN4 = 72,
99 MX6Q_PAD_DISP0_DAT0 = 73,
100 MX6Q_PAD_DISP0_DAT1 = 74,
101 MX6Q_PAD_DISP0_DAT2 = 75,
102 MX6Q_PAD_DISP0_DAT3 = 76,
103 MX6Q_PAD_DISP0_DAT4 = 77,
104 MX6Q_PAD_DISP0_DAT5 = 78,
105 MX6Q_PAD_DISP0_DAT6 = 79,
106 MX6Q_PAD_DISP0_DAT7 = 80,
107 MX6Q_PAD_DISP0_DAT8 = 81,
108 MX6Q_PAD_DISP0_DAT9 = 82,
109 MX6Q_PAD_DISP0_DAT10 = 83,
110 MX6Q_PAD_DISP0_DAT11 = 84,
111 MX6Q_PAD_DISP0_DAT12 = 85,
112 MX6Q_PAD_DISP0_DAT13 = 86,
113 MX6Q_PAD_DISP0_DAT14 = 87,
114 MX6Q_PAD_DISP0_DAT15 = 88,
115 MX6Q_PAD_DISP0_DAT16 = 89,
116 MX6Q_PAD_DISP0_DAT17 = 90,
117 MX6Q_PAD_DISP0_DAT18 = 91,
118 MX6Q_PAD_DISP0_DAT19 = 92,
119 MX6Q_PAD_DISP0_DAT20 = 93,
120 MX6Q_PAD_DISP0_DAT21 = 94,
121 MX6Q_PAD_DISP0_DAT22 = 95,
122 MX6Q_PAD_DISP0_DAT23 = 96,
123 MX6Q_PAD_ENET_MDIO = 97,
124 MX6Q_PAD_ENET_REF_CLK = 98,
125 MX6Q_PAD_ENET_RX_ER = 99,
126 MX6Q_PAD_ENET_CRS_DV = 100,
127 MX6Q_PAD_ENET_RXD1 = 101,
128 MX6Q_PAD_ENET_RXD0 = 102,
129 MX6Q_PAD_ENET_TX_EN = 103,
130 MX6Q_PAD_ENET_TXD1 = 104,
131 MX6Q_PAD_ENET_TXD0 = 105,
132 MX6Q_PAD_ENET_MDC = 106,
133 MX6Q_PAD_DRAM_D40 = 107,
134 MX6Q_PAD_DRAM_D41 = 108,
135 MX6Q_PAD_DRAM_D42 = 109,
136 MX6Q_PAD_DRAM_D43 = 110,
137 MX6Q_PAD_DRAM_D44 = 111,
138 MX6Q_PAD_DRAM_D45 = 112,
139 MX6Q_PAD_DRAM_D46 = 113,
140 MX6Q_PAD_DRAM_D47 = 114,
141 MX6Q_PAD_DRAM_SDQS5 = 115,
142 MX6Q_PAD_DRAM_DQM5 = 116,
143 MX6Q_PAD_DRAM_D32 = 117,
144 MX6Q_PAD_DRAM_D33 = 118,
145 MX6Q_PAD_DRAM_D34 = 119,
146 MX6Q_PAD_DRAM_D35 = 120,
147 MX6Q_PAD_DRAM_D36 = 121,
148 MX6Q_PAD_DRAM_D37 = 122,
149 MX6Q_PAD_DRAM_D38 = 123,
150 MX6Q_PAD_DRAM_D39 = 124,
151 MX6Q_PAD_DRAM_DQM4 = 125,
152 MX6Q_PAD_DRAM_SDQS4 = 126,
153 MX6Q_PAD_DRAM_D24 = 127,
154 MX6Q_PAD_DRAM_D25 = 128,
155 MX6Q_PAD_DRAM_D26 = 129,
156 MX6Q_PAD_DRAM_D27 = 130,
157 MX6Q_PAD_DRAM_D28 = 131,
158 MX6Q_PAD_DRAM_D29 = 132,
159 MX6Q_PAD_DRAM_SDQS3 = 133,
160 MX6Q_PAD_DRAM_D30 = 134,
161 MX6Q_PAD_DRAM_D31 = 135,
162 MX6Q_PAD_DRAM_DQM3 = 136,
163 MX6Q_PAD_DRAM_D16 = 137,
164 MX6Q_PAD_DRAM_D17 = 138,
165 MX6Q_PAD_DRAM_D18 = 139,
166 MX6Q_PAD_DRAM_D19 = 140,
167 MX6Q_PAD_DRAM_D20 = 141,
168 MX6Q_PAD_DRAM_D21 = 142,
169 MX6Q_PAD_DRAM_D22 = 143,
170 MX6Q_PAD_DRAM_SDQS2 = 144,
171 MX6Q_PAD_DRAM_D23 = 145,
172 MX6Q_PAD_DRAM_DQM2 = 146,
173 MX6Q_PAD_DRAM_A0 = 147,
174 MX6Q_PAD_DRAM_A1 = 148,
175 MX6Q_PAD_DRAM_A2 = 149,
176 MX6Q_PAD_DRAM_A3 = 150,
177 MX6Q_PAD_DRAM_A4 = 151,
178 MX6Q_PAD_DRAM_A5 = 152,
179 MX6Q_PAD_DRAM_A6 = 153,
180 MX6Q_PAD_DRAM_A7 = 154,
181 MX6Q_PAD_DRAM_A8 = 155,
182 MX6Q_PAD_DRAM_A9 = 156,
183 MX6Q_PAD_DRAM_A10 = 157,
184 MX6Q_PAD_DRAM_A11 = 158,
185 MX6Q_PAD_DRAM_A12 = 159,
186 MX6Q_PAD_DRAM_A13 = 160,
187 MX6Q_PAD_DRAM_A14 = 161,
188 MX6Q_PAD_DRAM_A15 = 162,
189 MX6Q_PAD_DRAM_CAS = 163,
190 MX6Q_PAD_DRAM_CS0 = 164,
191 MX6Q_PAD_DRAM_CS1 = 165,
192 MX6Q_PAD_DRAM_RAS = 166,
193 MX6Q_PAD_DRAM_RESET = 167,
194 MX6Q_PAD_DRAM_SDBA0 = 168,
195 MX6Q_PAD_DRAM_SDBA1 = 169,
196 MX6Q_PAD_DRAM_SDCLK_0 = 170,
197 MX6Q_PAD_DRAM_SDBA2 = 171,
198 MX6Q_PAD_DRAM_SDCKE0 = 172,
199 MX6Q_PAD_DRAM_SDCLK_1 = 173,
200 MX6Q_PAD_DRAM_SDCKE1 = 174,
201 MX6Q_PAD_DRAM_SDODT0 = 175,
202 MX6Q_PAD_DRAM_SDODT1 = 176,
203 MX6Q_PAD_DRAM_SDWE = 177,
204 MX6Q_PAD_DRAM_D0 = 178,
205 MX6Q_PAD_DRAM_D1 = 179,
206 MX6Q_PAD_DRAM_D2 = 180,
207 MX6Q_PAD_DRAM_D3 = 181,
208 MX6Q_PAD_DRAM_D4 = 182,
209 MX6Q_PAD_DRAM_D5 = 183,
210 MX6Q_PAD_DRAM_SDQS0 = 184,
211 MX6Q_PAD_DRAM_D6 = 185,
212 MX6Q_PAD_DRAM_D7 = 186,
213 MX6Q_PAD_DRAM_DQM0 = 187,
214 MX6Q_PAD_DRAM_D8 = 188,
215 MX6Q_PAD_DRAM_D9 = 189,
216 MX6Q_PAD_DRAM_D10 = 190,
217 MX6Q_PAD_DRAM_D11 = 191,
218 MX6Q_PAD_DRAM_D12 = 192,
219 MX6Q_PAD_DRAM_D13 = 193,
220 MX6Q_PAD_DRAM_D14 = 194,
221 MX6Q_PAD_DRAM_SDQS1 = 195,
222 MX6Q_PAD_DRAM_D15 = 196,
223 MX6Q_PAD_DRAM_DQM1 = 197,
224 MX6Q_PAD_DRAM_D48 = 198,
225 MX6Q_PAD_DRAM_D49 = 199,
226 MX6Q_PAD_DRAM_D50 = 200,
227 MX6Q_PAD_DRAM_D51 = 201,
228 MX6Q_PAD_DRAM_D52 = 202,
229 MX6Q_PAD_DRAM_D53 = 203,
230 MX6Q_PAD_DRAM_D54 = 204,
231 MX6Q_PAD_DRAM_D55 = 205,
232 MX6Q_PAD_DRAM_SDQS6 = 206,
233 MX6Q_PAD_DRAM_DQM6 = 207,
234 MX6Q_PAD_DRAM_D56 = 208,
235 MX6Q_PAD_DRAM_SDQS7 = 209,
236 MX6Q_PAD_DRAM_D57 = 210,
237 MX6Q_PAD_DRAM_D58 = 211,
238 MX6Q_PAD_DRAM_D59 = 212,
239 MX6Q_PAD_DRAM_D60 = 213,
240 MX6Q_PAD_DRAM_DQM7 = 214,
241 MX6Q_PAD_DRAM_D61 = 215,
242 MX6Q_PAD_DRAM_D62 = 216,
243 MX6Q_PAD_DRAM_D63 = 217,
244 MX6Q_PAD_KEY_COL0 = 218,
245 MX6Q_PAD_KEY_ROW0 = 219,
246 MX6Q_PAD_KEY_COL1 = 220,
247 MX6Q_PAD_KEY_ROW1 = 221,
248 MX6Q_PAD_KEY_COL2 = 222,
249 MX6Q_PAD_KEY_ROW2 = 223,
250 MX6Q_PAD_KEY_COL3 = 224,
251 MX6Q_PAD_KEY_ROW3 = 225,
252 MX6Q_PAD_KEY_COL4 = 226,
253 MX6Q_PAD_KEY_ROW4 = 227,
254 MX6Q_PAD_GPIO_0 = 228,
255 MX6Q_PAD_GPIO_1 = 229,
256 MX6Q_PAD_GPIO_9 = 230,
257 MX6Q_PAD_GPIO_3 = 231,
258 MX6Q_PAD_GPIO_6 = 232,
259 MX6Q_PAD_GPIO_2 = 233,
260 MX6Q_PAD_GPIO_4 = 234,
261 MX6Q_PAD_GPIO_5 = 235,
262 MX6Q_PAD_GPIO_7 = 236,
263 MX6Q_PAD_GPIO_8 = 237,
264 MX6Q_PAD_GPIO_16 = 238,
265 MX6Q_PAD_GPIO_17 = 239,
266 MX6Q_PAD_GPIO_18 = 240,
267 MX6Q_PAD_GPIO_19 = 241,
268 MX6Q_PAD_CSI0_PIXCLK = 242,
269 MX6Q_PAD_CSI0_MCLK = 243,
270 MX6Q_PAD_CSI0_DATA_EN = 244,
271 MX6Q_PAD_CSI0_VSYNC = 245,
272 MX6Q_PAD_CSI0_DAT4 = 246,
273 MX6Q_PAD_CSI0_DAT5 = 247,
274 MX6Q_PAD_CSI0_DAT6 = 248,
275 MX6Q_PAD_CSI0_DAT7 = 249,
276 MX6Q_PAD_CSI0_DAT8 = 250,
277 MX6Q_PAD_CSI0_DAT9 = 251,
278 MX6Q_PAD_CSI0_DAT10 = 252,
279 MX6Q_PAD_CSI0_DAT11 = 253,
280 MX6Q_PAD_CSI0_DAT12 = 254,
281 MX6Q_PAD_CSI0_DAT13 = 255,
282 MX6Q_PAD_CSI0_DAT14 = 256,
283 MX6Q_PAD_CSI0_DAT15 = 257,
284 MX6Q_PAD_CSI0_DAT16 = 258,
285 MX6Q_PAD_CSI0_DAT17 = 259,
286 MX6Q_PAD_CSI0_DAT18 = 260,
287 MX6Q_PAD_CSI0_DAT19 = 261,
288 MX6Q_PAD_JTAG_TMS = 262,
289 MX6Q_PAD_JTAG_MOD = 263,
290 MX6Q_PAD_JTAG_TRSTB = 264,
291 MX6Q_PAD_JTAG_TDI = 265,
292 MX6Q_PAD_JTAG_TCK = 266,
293 MX6Q_PAD_JTAG_TDO = 267,
294 MX6Q_PAD_LVDS1_TX3_P = 268,
295 MX6Q_PAD_LVDS1_TX2_P = 269,
296 MX6Q_PAD_LVDS1_CLK_P = 270,
297 MX6Q_PAD_LVDS1_TX1_P = 271,
298 MX6Q_PAD_LVDS1_TX0_P = 272,
299 MX6Q_PAD_LVDS0_TX3_P = 273,
300 MX6Q_PAD_LVDS0_CLK_P = 274,
301 MX6Q_PAD_LVDS0_TX2_P = 275,
302 MX6Q_PAD_LVDS0_TX1_P = 276,
303 MX6Q_PAD_LVDS0_TX0_P = 277,
304 MX6Q_PAD_TAMPER = 278,
305 MX6Q_PAD_PMIC_ON_REQ = 279,
306 MX6Q_PAD_PMIC_STBY_REQ = 280,
307 MX6Q_PAD_POR_B = 281,
308 MX6Q_PAD_BOOT_MODE1 = 282,
309 MX6Q_PAD_RESET_IN_B = 283,
310 MX6Q_PAD_BOOT_MODE0 = 284,
311 MX6Q_PAD_TEST_MODE = 285,
312 MX6Q_PAD_SD3_DAT7 = 286,
313 MX6Q_PAD_SD3_DAT6 = 287,
314 MX6Q_PAD_SD3_DAT5 = 288,
315 MX6Q_PAD_SD3_DAT4 = 289,
316 MX6Q_PAD_SD3_CMD = 290,
317 MX6Q_PAD_SD3_CLK = 291,
318 MX6Q_PAD_SD3_DAT0 = 292,
319 MX6Q_PAD_SD3_DAT1 = 293,
320 MX6Q_PAD_SD3_DAT2 = 294,
321 MX6Q_PAD_SD3_DAT3 = 295,
322 MX6Q_PAD_SD3_RST = 296,
323 MX6Q_PAD_NANDF_CLE = 297,
324 MX6Q_PAD_NANDF_ALE = 298,
325 MX6Q_PAD_NANDF_WP_B = 299,
326 MX6Q_PAD_NANDF_RB0 = 300,
327 MX6Q_PAD_NANDF_CS0 = 301,
328 MX6Q_PAD_NANDF_CS1 = 302,
329 MX6Q_PAD_NANDF_CS2 = 303,
330 MX6Q_PAD_NANDF_CS3 = 304,
331 MX6Q_PAD_SD4_CMD = 305,
332 MX6Q_PAD_SD4_CLK = 306,
333 MX6Q_PAD_NANDF_D0 = 307,
334 MX6Q_PAD_NANDF_D1 = 308,
335 MX6Q_PAD_NANDF_D2 = 309,
336 MX6Q_PAD_NANDF_D3 = 310,
337 MX6Q_PAD_NANDF_D4 = 311,
338 MX6Q_PAD_NANDF_D5 = 312,
339 MX6Q_PAD_NANDF_D6 = 313,
340 MX6Q_PAD_NANDF_D7 = 314,
341 MX6Q_PAD_SD4_DAT0 = 315,
342 MX6Q_PAD_SD4_DAT1 = 316,
343 MX6Q_PAD_SD4_DAT2 = 317,
344 MX6Q_PAD_SD4_DAT3 = 318,
345 MX6Q_PAD_SD4_DAT4 = 319,
346 MX6Q_PAD_SD4_DAT5 = 320,
347 MX6Q_PAD_SD4_DAT6 = 321,
348 MX6Q_PAD_SD4_DAT7 = 322,
349 MX6Q_PAD_SD1_DAT1 = 323,
350 MX6Q_PAD_SD1_DAT0 = 324,
351 MX6Q_PAD_SD1_DAT3 = 325,
352 MX6Q_PAD_SD1_CMD = 326,
353 MX6Q_PAD_SD1_DAT2 = 327,
354 MX6Q_PAD_SD1_CLK = 328,
355 MX6Q_PAD_SD2_CLK = 329,
356 MX6Q_PAD_SD2_CMD = 330,
357 MX6Q_PAD_SD2_DAT3 = 331,
358};
359
360/* imx6q register maps */
361static struct imx_pin_reg imx6q_pin_regs[] = {
362 IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */
363 IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 1, 0x0834, 0), /* MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 */
364 IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 2, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 */
365 IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 3, 0x07C8, 0), /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
366 IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 4, 0x08F0, 0), /* MX6Q_PAD_SD2_DAT1__KPP_COL_7 */
367 IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__GPIO_1_14 */
368 IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__CCM_WAIT */
369 IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__ANATOP_TESTO_0 */
370 IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */
371 IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 1, 0x0838, 0), /* MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 */
372 IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 2, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 */
373 IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 3, 0x07B8, 0), /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
374 IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 4, 0x08F8, 0), /* MX6Q_PAD_SD2_DAT2__KPP_ROW_6 */
375 IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__GPIO_1_13 */
376 IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__CCM_STOP */
377 IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__ANATOP_TESTO_1 */
378 IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */
379 IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 1, 0x082C, 0), /* MX6Q_PAD_SD2_DAT0__ECSPI5_MISO */
380 IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 3, 0x07B4, 0), /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
381 IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 4, 0x08FC, 0), /* MX6Q_PAD_SD2_DAT0__KPP_ROW_7 */
382 IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__GPIO_1_15 */
383 IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT */
384 IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__TESTO_2 */
385 IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA */
386 IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
387 IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 2, 0x0918, 0), /* MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK */
388 IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__GPIO_6_19 */
389 IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_IN_0 */
390 IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__ANATOP_24M_OUT */
391 IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__MIPI_HSI_CRL_TX_RDY */
392 IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
393 IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__GPIO_6_20 */
394 IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_IN_1 */
395 IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__MIPI_HSI_CRL_RX_FLG */
396 IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
397 IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__GPIO_6_21 */
398 IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_IN_2 */
399 IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP */
400 IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__MIPI_HSI_CRL_RX_DTA */
401 IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
402 IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__GPIO_6_22 */
403 IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_IN_3 */
404 IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP */
405 IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__MIPI_HSI_CRL_RX_WAK */
406 IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
407 IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__GPIO_6_23 */
408 IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_IN_4 */
409 IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA */
410 IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 1, 0x0858, 0), /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
411 IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 */
412 IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RX_CTL__MIPI_DPHY_IN_5 */
413 IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD0__MIPI_HSI_CRL_RX_RDY */
414 IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 1, 0x0848, 0), /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
415 IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD0__GPIO_6_25 */
416 IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_IN_6 */
417 IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE */
418 IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
419 IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 */
420 IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__CORE_DPHY_IN_7 */
421 IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 7, 0x083C, 0), /* MX6Q_PAD_RGMII_TX_CTL__ANATOP_REF_OUT */
422 IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FL */
423 IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 1, 0x084C, 0), /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
424 IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__GPIO_6_27 */
425 IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__CORE_DPHY_TEST_IN_8 */
426 IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__SJC_FAIL */
427 IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD2__MIPI_HSI_CRL_TX_DTA */
428 IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 1, 0x0850, 0), /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
429 IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD2__GPIO_6_28 */
430 IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_IN_9 */
431 IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD3__MIPI_HSI_CRL_TX_WAK */
432 IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 1, 0x0854, 0), /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
433 IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD3__GPIO_6_29 */
434 IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_IN10 */
435 IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE */
436 IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 1, 0x0844, 0), /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
437 IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RXC__GPIO_6_30 */
438 IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_IN11 */
439 IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 */
440 IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A25__ECSPI4_SS1 */
441 IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 2, 0x0000, 0), /* MX6Q_PAD_EIM_A25__ECSPI2_RDY */
442 IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 */
443 IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS */
444 IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A25__GPIO_5_2 */
445 IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 6, 0x088C, 0), /* MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE */
446 IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A25__PL301_PER1_HBURST_0 */
447 IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 */
448 IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 1, 0x0800, 0), /* MX6Q_PAD_EIM_EB2__ECSPI1_SS0 */
449 IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 2, 0x07EC, 0), /* MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK */
450 IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 3, 0x08D4, 0), /* MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 */
451 IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 4, 0x0890, 0), /* MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL */
452 IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB2__GPIO_2_30 */
453 IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 6, 0x08A0, 0), /* MX6Q_PAD_EIM_EB2__I2C2_SCL */
454 IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 */
455 IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 */
456 IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 1, 0x07F4, 0), /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
457 IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 */
458 IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 3, 0x08D0, 0), /* MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 */
459 IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 4, 0x0894, 0), /* MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA */
460 IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D16__GPIO_3_16 */
461 IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 6, 0x08A4, 0), /* MX6Q_PAD_EIM_D16__I2C2_SDA */
462 IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 */
463 IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 1, 0x07F8, 0), /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
464 IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 */
465 IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 3, 0x08E0, 0), /* MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK */
466 IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT */
467 IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D17__GPIO_3_17 */
468 IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 6, 0x08A8, 0), /* MX6Q_PAD_EIM_D17__I2C3_SCL */
469 IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D17__PL301_PER1_HBURST_1 */
470 IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 */
471 IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 1, 0x07FC, 0), /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
472 IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 */
473 IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 3, 0x08CC, 0), /* MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 */
474 IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS */
475 IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D18__GPIO_3_18 */
476 IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 6, 0x08AC, 0), /* MX6Q_PAD_EIM_D18__I2C3_SDA */
477 IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D18__PL301_PER1_HBURST_2 */
478 IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 */
479 IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 1, 0x0804, 0), /* MX6Q_PAD_EIM_D19__ECSPI1_SS1 */
480 IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 */
481 IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 3, 0x08C8, 0), /* MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 */
482 IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 4, 0x091C, 0), /* MX6Q_PAD_EIM_D19__UART1_CTS */
483 IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
484 IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D19__EPIT1_EPITO */
485 IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D19__PL301_PER1_HRESP */
486 IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 */
487 IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 1, 0x0824, 0), /* MX6Q_PAD_EIM_D20__ECSPI4_SS0 */
488 IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 */
489 IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 3, 0x08C4, 0), /* MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 */
490 IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 4, 0x091C, 1), /* MX6Q_PAD_EIM_D20__UART1_RTS */
491 IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D20__GPIO_3_20 */
492 IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D20__EPIT2_EPITO */
493 IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 */
494 IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D21__ECSPI4_SCLK */
495 IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 */
496 IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 3, 0x08B4, 0), /* MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 */
497 IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 4, 0x0944, 0), /* MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC */
498 IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D21__GPIO_3_21 */
499 IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 6, 0x0898, 0), /* MX6Q_PAD_EIM_D21__I2C1_SCL */
500 IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 7, 0x0914, 0), /* MX6Q_PAD_EIM_D21__SPDIF_IN1 */
501 IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 */
502 IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D22__ECSPI4_MISO */
503 IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 */
504 IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 3, 0x08B0, 0), /* MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 */
505 IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR */
506 IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
507 IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D22__SPDIF_OUT1 */
508 IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D22__PL301_PER1_HWRITE */
509 IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 */
510 IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS */
511 IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 2, 0x092C, 0), /* MX6Q_PAD_EIM_D23__UART3_CTS */
512 IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 3, 0x0000, 0), /* MX6Q_PAD_EIM_D23__UART1_DCD */
513 IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 4, 0x08D8, 0), /* MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN */
514 IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D23__GPIO_3_23 */
515 IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 */
516 IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 */
517 IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 */
518 IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__ECSPI4_RDY */
519 IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 2, 0x092C, 1), /* MX6Q_PAD_EIM_EB3__UART3_RTS */
520 IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__UART1_RI */
521 IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 4, 0x08DC, 0), /* MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC */
522 IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__GPIO_2_31 */
523 IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 */
524 IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 */
525 IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 */
526 IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D24__ECSPI4_SS2 */
527 IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D24__UART3_TXD */
528 IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 3, 0x0808, 0), /* MX6Q_PAD_EIM_D24__ECSPI1_SS2 */
529 IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D24__ECSPI2_SS2 */
530 IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D24__GPIO_3_24 */
531 IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 6, 0x07D8, 0), /* MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS */
532 IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D24__UART1_DTR */
533 IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 */
534 IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D25__ECSPI4_SS3 */
535 IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 2, 0x0930, 1), /* MX6Q_PAD_EIM_D25__UART3_RXD */
536 IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 3, 0x080C, 0), /* MX6Q_PAD_EIM_D25__ECSPI1_SS3 */
537 IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D25__ECSPI2_SS3 */
538 IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D25__GPIO_3_25 */
539 IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 6, 0x07D4, 0), /* MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC */
540 IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D25__UART1_DSR */
541 IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 */
542 IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 */
543 IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 */
544 IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 3, 0x08C0, 0), /* MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 */
545 IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D26__UART2_TXD */
546 IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D26__GPIO_3_26 */
547 IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_SISG_2 */
548 IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 */
549 IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 */
550 IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 */
551 IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 */
552 IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 3, 0x08BC, 0), /* MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 */
553 IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 4, 0x0928, 1), /* MX6Q_PAD_EIM_D27__UART2_RXD */
554 IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D27__GPIO_3_27 */
555 IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_SISG_3 */
556 IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 */
557 IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 */
558 IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 1, 0x089C, 0), /* MX6Q_PAD_EIM_D28__I2C1_SDA */
559 IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D28__ECSPI4_MOSI */
560 IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 3, 0x08B8, 0), /* MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 */
561 IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 4, 0x0924, 0), /* MX6Q_PAD_EIM_D28__UART2_CTS */
562 IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D28__GPIO_3_28 */
563 IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG */
564 IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 */
565 IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 */
566 IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 */
567 IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 2, 0x0824, 1), /* MX6Q_PAD_EIM_D29__ECSPI4_SS0 */
568 IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 4, 0x0924, 1), /* MX6Q_PAD_EIM_D29__UART2_RTS */
569 IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D29__GPIO_3_29 */
570 IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 6, 0x08E4, 0), /* MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC */
571 IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 */
572 IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 */
573 IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 */
574 IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 */
575 IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 3, 0x0000, 0), /* MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 */
576 IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 4, 0x092C, 2), /* MX6Q_PAD_EIM_D30__UART3_CTS */
577 IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D30__GPIO_3_30 */
578 IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 6, 0x0948, 0), /* MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC */
579 IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D30__PL301_PER1_HPROT_0 */
580 IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 */
581 IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 */
582 IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 */
583 IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 */
584 IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 4, 0x092C, 3), /* MX6Q_PAD_EIM_D31__UART3_RTS */
585 IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D31__GPIO_3_31 */
586 IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR */
587 IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D31__PL301_PER1_HPROT_1 */
588 IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 */
589 IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 */
590 IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 2, 0x08D4, 1), /* MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 */
591 IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A24__IPU2_SISG_2 */
592 IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A24__IPU1_SISG_2 */
593 IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A24__GPIO_5_4 */
594 IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A24__PL301_PER1_HPROT_2 */
595 IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 */
596 IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 */
597 IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 */
598 IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 2, 0x08D0, 1), /* MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 */
599 IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A23__IPU2_SISG_3 */
600 IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A23__IPU1_SISG_3 */
601 IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A23__GPIO_6_6 */
602 IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A23__PL301_PER1_HPROT_3 */
603 IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 */
604 IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 */
605 IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 */
606 IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 2, 0x08CC, 1), /* MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 */
607 IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A22__GPIO_2_16 */
608 IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 */
609 IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 */
610 IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 */
611 IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 */
612 IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 2, 0x08C8, 1), /* MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 */
613 IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A21__RESERVED_RESERVED */
614 IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_OUT_18 */
615 IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A21__GPIO_2_17 */
616 IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 */
617 IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 */
618 IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 */
619 IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 */
620 IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 2, 0x08C4, 1), /* MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 */
621 IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A20__RESERVED_RESERVED */
622 IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_OUT_19 */
623 IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A20__GPIO_2_18 */
624 IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 */
625 IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 */
626 IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 */
627 IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 */
628 IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 2, 0x08C0, 1), /* MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 */
629 IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A19__RESERVED_RESERVED */
630 IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_OUT_20 */
631 IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A19__GPIO_2_19 */
632 IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 */
633 IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 */
634 IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 */
635 IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 */
636 IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 2, 0x08BC, 1), /* MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 */
637 IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A18__RESERVED_RESERVED */
638 IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_OUT_21 */
639 IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A18__GPIO_2_20 */
640 IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 */
641 IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 */
642 IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 */
643 IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 */
644 IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 2, 0x08B8, 1), /* MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 */
645 IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A17__RESERVED_RESERVED */
646 IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_OUT_22 */
647 IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A17__GPIO_2_21 */
648 IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 */
649 IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 */
650 IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 */
651 IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK */
652 IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 2, 0x08E0, 1), /* MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK */
653 IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_OUT_23 */
654 IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A16__GPIO_2_22 */
655 IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 */
656 IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 */
657 IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 */
658 IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 */
659 IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 2, 0x0810, 0), /* MX6Q_PAD_EIM_CS0__ECSPI2_SCLK */
660 IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_OUT_24 */
661 IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__GPIO_2_23 */
662 IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 */
663 IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 */
664 IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 */
665 IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 2, 0x0818, 0), /* MX6Q_PAD_EIM_CS1__ECSPI2_MOSI */
666 IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 4, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_OUT_25 */
667 IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__GPIO_2_24 */
668 IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 */
669 IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 0, 0x0000, 0), /* MX6Q_PAD_EIM_OE__WEIM_WEIM_OE */
670 IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 1, 0x0000, 0), /* MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 */
671 IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 2, 0x0814, 0), /* MX6Q_PAD_EIM_OE__ECSPI2_MISO */
672 IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 4, 0x0000, 0), /* MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_OUT_26 */
673 IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 5, 0x0000, 0), /* MX6Q_PAD_EIM_OE__GPIO_2_25 */
674 IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 6, 0x0000, 0), /* MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 */
675 IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 0, 0x0000, 0), /* MX6Q_PAD_EIM_RW__WEIM_WEIM_RW */
676 IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 1, 0x0000, 0), /* MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 */
677 IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 2, 0x081C, 0), /* MX6Q_PAD_EIM_RW__ECSPI2_SS0 */
678 IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 4, 0x0000, 0), /* MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_OUT_27 */
679 IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 5, 0x0000, 0), /* MX6Q_PAD_EIM_RW__GPIO_2_26 */
680 IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 6, 0x0000, 0), /* MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 */
681 IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 7, 0x0000, 0), /* MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 */
682 IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 0, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA */
683 IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 1, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 */
684 IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 2, 0x0820, 0), /* MX6Q_PAD_EIM_LBA__ECSPI2_SS1 */
685 IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 5, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__GPIO_2_27 */
686 IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 6, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 */
687 IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 7, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 */
688 IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 */
689 IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 */
690 IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 2, 0x08B4, 1), /* MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 */
691 IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_OUT_0 */
692 IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 4, 0x07F0, 0), /* MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY */
693 IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__GPIO_2_28 */
694 IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 */
695 IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 */
696 IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 */
697 IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 1, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 */
698 IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 2, 0x08B0, 1), /* MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 */
699 IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 3, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY__OUT_1 */
700 IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__GPIO_2_29 */
701 IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 6, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 */
702 IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 */
703 IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 */
704 IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 */
705 IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 */
706 IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY__OUT_2 */
707 IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__GPIO_3_0 */
708 IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 */
709 IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 */
710 IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 */
711 IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 */
712 IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 */
713 IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_OUT_3 */
714 IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__USBPHY1_TX_LS_MODE */
715 IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__GPIO_3_1 */
716 IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 */
717 IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 */
718 IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 */
719 IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 */
720 IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 */
721 IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_OUT_4 */
722 IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__USBPHY1_TX_HS_MODE */
723 IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__GPIO_3_2 */
724 IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 */
725 IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 */
726 IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 */
727 IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 */
728 IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 */
729 IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_OUT_5 */
730 IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__USBPHY1_TX_HIZ */
731 IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__GPIO_3_3 */
732 IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 */
733 IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 */
734 IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 */
735 IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 */
736 IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 */
737 IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_OUT_6 */
738 IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TX_EN */
739 IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__GPIO_3_4 */
740 IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 */
741 IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 */
742 IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 */
743 IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 */
744 IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 */
745 IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_OUT_7 */
746 IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TX_DP */
747 IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__GPIO_3_5 */
748 IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 */
749 IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 */
750 IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 */
751 IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 */
752 IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 */
753 IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_OUT_8 */
754 IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TX_DN */
755 IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__GPIO_3_6 */
756 IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 */
757 IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 */
758 IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 */
759 IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 */
760 IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 */
761 IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_OUT_9 */
762 IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__GPIO_3_7 */
763 IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 */
764 IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 */
765 IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 */
766 IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 */
767 IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 */
768 IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_OUT_10 */
769 IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__GPIO_3_8 */
770 IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 */
771 IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 */
772 IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 */
773 IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 */
774 IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 */
775 IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_OUT_11 */
776 IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__GPIO_3_9 */
777 IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 */
778 IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 */
779 IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 */
780 IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 */
781 IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 2, 0x08D8, 1), /* MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN */
782 IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_OUT12 */
783 IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__GPIO_3_10 */
784 IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 */
785 IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 */
786 IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 */
787 IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 */
788 IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 2, 0x08DC, 1), /* MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC */
789 IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_OUT13 */
790 IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__SDMA_DBG_EVT_CHN_6 */
791 IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__GPIO_3_11 */
792 IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 */
793 IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 */
794 IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 */
795 IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 */
796 IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 2, 0x08E4, 1), /* MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC */
797 IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_OUT14 */
798 IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_3 */
799 IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__GPIO_3_12 */
800 IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 */
801 IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 */
802 IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 */
803 IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS */
804 IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 2, 0x07EC, 1), /* MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK */
805 IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_OUT15 */
806 IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_4 */
807 IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__GPIO_3_13 */
808 IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 */
809 IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 */
810 IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 */
811 IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS */
812 IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK */
813 IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_OUT16 */
814 IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_5 */
815 IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__GPIO_3_14 */
816 IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 */
817 IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 */
818 IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 */
819 IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 */
820 IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 */
821 IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_OUT17 */
822 IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__GPIO_3_15 */
823 IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 */
824 IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 */
825 IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 0, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT */
826 IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 1, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B */
827 IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 5, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__GPIO_5_0 */
828 IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 6, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 */
829 IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 7, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 */
830 IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 0, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK */
831 IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 1, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 */
832 IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 5, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__GPIO_6_31 */
833 IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 6, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 */
834 IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 0, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DSP_CLK */
835 IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 1, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DSP_CLK */
836 IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 3, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 */
837 IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 4, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 */
838 IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 5, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 */
839 IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 6, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__MMDC_DEBUG_0 */
840 IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 */
841 IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 */
842 IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC */
843 IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 3, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29 */
844 IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1 */
845 IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__GPIO_4_17 */
846 IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 */
847 IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 */
848 IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 */
849 IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD */
850 IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 3, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30 */
851 IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__SDMA_DBG_CORE_STA_2 */
852 IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__GPIO_4_18 */
853 IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__MMDC_DEBUG_2 */
854 IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 7, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__PL301_PER1_HADDR_9 */
855 IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 */
856 IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 */
857 IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS */
858 IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 3, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31 */
859 IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__SDMA_DBG_CORE_STA_3 */
860 IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__GPIO_4_19 */
861 IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 */
862 IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 7, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__PL301_PER1_HADDR_10 */
863 IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 */
864 IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 */
865 IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD */
866 IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 3, 0x094C, 0), /* MX6Q_PAD_DI0_PIN4__USDHC1_WP */
867 IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD */
868 IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__GPIO_4_20 */
869 IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 */
870 IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 7, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__PL301_PER1_HADDR_11 */
871 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 */
872 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 */
873 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK */
874 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0 */
875 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__SDMA_DBG_CORE_RUN */
876 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__GPIO_4_21 */
877 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 */
878 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 */
879 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 */
880 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI */
881 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1 */
882 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__SDMA_DBG_EVT_CHNSL */
883 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__GPIO_4_22 */
884 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__MMDC_DEBUG_6 */
885 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__PL301_PER1_HADR_12 */
886 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 */
887 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 */
888 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO */
889 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2 */
890 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE */
891 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__GPIO_4_23 */
892 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__MMDC_DEBUG_7 */
893 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__PL301_PER1_HADR_13 */
894 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 */
895 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 */
896 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 */
897 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3 */
898 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__SDMA_DBG_BUS_ERROR */
899 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__GPIO_4_24 */
900 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8 */
901 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__PL301_PER1_HADR_14 */
902 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 */
903 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 */
904 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 */
905 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DBG_4 */
906 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB */
907 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__GPIO_4_25 */
908 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 */
909 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__PL301_PER1_HADR_15 */
910 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 */
911 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 */
912 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 */
913 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS */
914 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__SDMA_DBG_MCH_DMBUS */
915 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__GPIO_4_26 */
916 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__MMDC_DEBUG_10 */
917 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__PL301_PER1_HADR_16 */
918 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 */
919 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 */
920 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 */
921 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC */
922 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__SDMA_DBG_RTBUF_WRT */
923 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__GPIO_4_27 */
924 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__MMDC_DEBUG_11 */
925 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__PL301_PER1_HADR_17 */
926 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 */
927 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 */
928 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY */
929 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5 */
930 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__SDMA_DBG_EVT_CHN_0 */
931 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__GPIO_4_28 */
932 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__MMDC_DEBUG_12 */
933 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__PL301_PER1_HADR_18 */
934 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 */
935 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 */
936 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__PWM1_PWMO */
937 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B */
938 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__SDMA_DBG_EVT_CHN_1 */
939 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__GPIO_4_29 */
940 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__MMDC_DEBUG_13 */
941 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__PL301_PER1_HADR_19 */
942 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 */
943 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 */
944 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__PWM2_PWMO */
945 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B */
946 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__SDMA_DBG_EVT_CHN_2 */
947 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__GPIO_4_30 */
948 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__MMDC_DEBUG_14 */
949 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__PL301_PER1_HADR_20 */
950 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 */
951 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 */
952 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__USDHC1_DBG_6 */
953 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__SDMA_DBG_EVT_CHN3 */
954 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__GPIO_4_31 */
955 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__MMDC_DEBUG_15 */
956 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__PL301_PER1_HADR21 */
957 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 */
958 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 */
959 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7 */
960 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__SDMA_DBG_EVT_CHN4 */
961 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__GPIO_5_5 */
962 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__MMDC_DEBUG_16 */
963 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__PL301_PER1_HADR22 */
964 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 */
965 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 */
966 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED */
967 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__SDMA_DBG_EVT_CHN5 */
968 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__GPIO_5_6 */
969 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__MMDC_DEBUG_17 */
970 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__PL301_PER1_HADR23 */
971 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 */
972 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 */
973 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 3, 0x07D8, 1), /* MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS */
974 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__SDMA_DBG_EVT_CHN0 */
975 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__GPIO_5_7 */
976 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__MMDC_DEBUG_18 */
977 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__PL301_PER1_HADR24 */
978 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 */
979 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 */
980 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 3, 0x07D4, 1), /* MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC */
981 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__SDMA_DBG_EVT_CHN1 */
982 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__GPIO_5_8 */
983 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__MMDC_DEBUG_19 */
984 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 */
985 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 */
986 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 2, 0x0804, 1), /* MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 */
987 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 3, 0x0820, 1), /* MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 */
988 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__SDMA_DBG_EVT_CHN2 */
989 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__GPIO_5_9 */
990 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__MMDC_DEBUG_20 */
991 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__PL301_PER1_HADR25 */
992 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 */
993 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 */
994 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 2, 0x0818, 1), /* MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI */
995 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 3, 0x07DC, 0), /* MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC */
996 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 4, 0x090C, 0), /* MX6Q_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 */
997 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__GPIO_5_10 */
998 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__MMDC_DEBUG_21 */
999 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__PL301_PER1_HADR26 */
1000 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 */
1001 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 */
1002 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 2, 0x0814, 1), /* MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO */
1003 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 3, 0x07D0, 0), /* MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD */
1004 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 4, 0x0910, 0), /* MX6Q_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 */
1005 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__GPIO_5_11 */
1006 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__MMDC_DEBUG_22 */
1007 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__PL301_PER1_HADR27 */
1008 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 */
1009 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 */
1010 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 2, 0x081C, 1), /* MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 */
1011 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 3, 0x07E0, 0), /* MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS */
1012 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 4, 0x07C0, 0), /* MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS */
1013 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__GPIO_5_12 */
1014 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__MMDC_DEBUG_23 */
1015 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 */
1016 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 */
1017 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 */
1018 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 2, 0x0810, 1), /* MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK */
1019 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 3, 0x07CC, 0), /* MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD */
1020 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 4, 0x07BC, 0), /* MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC */
1021 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__GPIO_5_13 */
1022 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__MMDC_DEBUG_24 */
1023 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 */
1024 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 */
1025 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 */
1026 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 2, 0x07F4, 1), /* MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK */
1027 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 3, 0x07C4, 0), /* MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC */
1028 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__SDMA_DBG_EVT_CHN7 */
1029 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__GPIO_5_14 */
1030 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__MMDC_DEBUG_25 */
1031 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__PL301_PER1_HADR28 */
1032 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 */
1033 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 */
1034 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 2, 0x07FC, 1), /* MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI */
1035 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 3, 0x07B8, 1), /* MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD */
1036 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__SDMA_DBG_BUS_DEV0 */
1037 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__GPIO_5_15 */
1038 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__MMDC_DEBUG_26 */
1039 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__PL301_PER1_HADR29 */
1040 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 */
1041 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 */
1042 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 2, 0x07F8, 1), /* MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO */
1043 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 3, 0x07C8, 1), /* MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS */
1044 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__SDMA_DBG_BUS_DEV1 */
1045 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__GPIO_5_16 */
1046 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__MMDC_DEBUG_27 */
1047 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__PL301_PER1_HADR30 */
1048 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 */
1049 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 */
1050 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 2, 0x0800, 1), /* MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 */
1051 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 3, 0x07B4, 1), /* MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD */
1052 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__SDMA_DBG_BUS_DEV2 */
1053 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__GPIO_5_17 */
1054 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__MMDC_DEBUG_28 */
1055 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__PL301_PER1_HADR31 */
1056 IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 0, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED */
1057 IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 1, 0x0840, 0), /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */
1058 IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 2, 0x086C, 0), /* MX6Q_PAD_ENET_MDIO__ESAI1_SCKR */
1059 IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 3, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEV3 */
1060 IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 4, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__ENET_1588_EVT1_OUT */
1061 IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 5, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__GPIO_1_22 */
1062 IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 6, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK */
1063 IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 0, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__RESERVED_RSRVED */
1064 IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 1, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
1065 IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 2, 0x085C, 0), /* MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR */
1066 IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 3, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__SDMA_DBGBUS_DEV4 */
1067 IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 5, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 */
1068 IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 6, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK */
1069 IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 7, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__USBPHY1_RX_SQH */
1070 IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 1, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__ENET_RX_ER */
1071 IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 2, 0x0864, 0), /* MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR */
1072 IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 3, 0x0914, 1), /* MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 */
1073 IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 4, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__ENET_1588_EVT2_OUT */
1074 IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 5, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__GPIO_1_24 */
1075 IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 6, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__PHY_TDI */
1076 IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 7, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__USBPHY1_RX_HS_RXD */
1077 IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 0, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__RESERVED_RSRVED */
1078 IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 1, 0x0858, 1), /* MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN */
1079 IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 2, 0x0870, 0), /* MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT */
1080 IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 3, 0x0918, 1), /* MX6Q_PAD_ENET_CRS_DV__SPDIF_EXTCLK */
1081 IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 5, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 */
1082 IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 6, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__PHY_TDO */
1083 IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 7, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__USBPHY1_RX_FS_RXD */
1084 IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 0, 0x0908, 0), /* MX6Q_PAD_ENET_RXD1__MLB_MLBSIG */
1085 IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 1, 0x084C, 1), /* MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 */
1086 IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 2, 0x0860, 0), /* MX6Q_PAD_ENET_RXD1__ESAI1_FST */
1087 IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 4, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__ENET_1588_EVT3_OUT */
1088 IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 5, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__GPIO_1_26 */
1089 IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 6, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__PHY_TCK */
1090 IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 7, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__USBPHY1_RX_DISCON */
1091 IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 0, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT */
1092 IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 1, 0x0848, 1), /* MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 */
1093 IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 2, 0x0868, 0), /* MX6Q_PAD_ENET_RXD0__ESAI1_HCKT */
1094 IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 3, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 */
1095 IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 5, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__GPIO_1_27 */
1096 IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 6, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__PHY_TMS */
1097 IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 7, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__USBPHY1_PLL_CK20DIV */
1098 IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 0, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__RESERVED_RSRVED */
1099 IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 1, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__ENET_TX_EN */
1100 IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 2, 0x0880, 0), /* MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 */
1101 IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 5, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__GPIO_1_28 */
1102 IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 6, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI */
1103 IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 7, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__USBPHY2_RX_SQH */
1104 IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 0, 0x0900, 0), /* MX6Q_PAD_ENET_TXD1__MLB_MLBCLK */
1105 IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 1, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 */
1106 IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 2, 0x087C, 0), /* MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 */
1107 IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 4, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN */
1108 IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 5, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__GPIO_1_29 */
1109 IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 6, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO */
1110 IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 7, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__USBPHY2_RX_HS_RXD */
1111 IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 0, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__RESERVED_RSRVED */
1112 IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 1, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 */
1113 IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 2, 0x0884, 0), /* MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 */
1114 IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 5, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__GPIO_1_30 */
1115 IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 6, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK */
1116 IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 7, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__USBPHY2_RX_FS_RXD */
1117 IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 0, 0x0904, 0), /* MX6Q_PAD_ENET_MDC__MLB_MLBDAT */
1118 IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 1, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__ENET_MDC */
1119 IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 2, 0x0888, 0), /* MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 */
1120 IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 4, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN */
1121 IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 5, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__GPIO_1_31 */
1122 IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 6, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__SATA_PHY_TMS */
1123 IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 7, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__USBPHY2_RX_DISCON */
1124 IMX_PIN_REG(MX6Q_PAD_DRAM_D40, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 */
1125 IMX_PIN_REG(MX6Q_PAD_DRAM_D41, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 */
1126 IMX_PIN_REG(MX6Q_PAD_DRAM_D42, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 */
1127 IMX_PIN_REG(MX6Q_PAD_DRAM_D43, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 */
1128 IMX_PIN_REG(MX6Q_PAD_DRAM_D44, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 */
1129 IMX_PIN_REG(MX6Q_PAD_DRAM_D45, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 */
1130 IMX_PIN_REG(MX6Q_PAD_DRAM_D46, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 */
1131 IMX_PIN_REG(MX6Q_PAD_DRAM_D47, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 */
1132 IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS5, 0x050C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 */
1133 IMX_PIN_REG(MX6Q_PAD_DRAM_DQM5, 0x0510, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 */
1134 IMX_PIN_REG(MX6Q_PAD_DRAM_D32, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 */
1135 IMX_PIN_REG(MX6Q_PAD_DRAM_D33, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 */
1136 IMX_PIN_REG(MX6Q_PAD_DRAM_D34, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 */
1137 IMX_PIN_REG(MX6Q_PAD_DRAM_D35, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 */
1138 IMX_PIN_REG(MX6Q_PAD_DRAM_D36, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 */
1139 IMX_PIN_REG(MX6Q_PAD_DRAM_D37, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 */
1140 IMX_PIN_REG(MX6Q_PAD_DRAM_D38, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 */
1141 IMX_PIN_REG(MX6Q_PAD_DRAM_D39, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 */
1142 IMX_PIN_REG(MX6Q_PAD_DRAM_DQM4, 0x0514, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 */
1143 IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS4, 0x0518, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 */
1144 IMX_PIN_REG(MX6Q_PAD_DRAM_D24, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 */
1145 IMX_PIN_REG(MX6Q_PAD_DRAM_D25, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 */
1146 IMX_PIN_REG(MX6Q_PAD_DRAM_D26, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 */
1147 IMX_PIN_REG(MX6Q_PAD_DRAM_D27, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 */
1148 IMX_PIN_REG(MX6Q_PAD_DRAM_D28, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 */
1149 IMX_PIN_REG(MX6Q_PAD_DRAM_D29, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 */
1150 IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS3, 0x051C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 */
1151 IMX_PIN_REG(MX6Q_PAD_DRAM_D30, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 */
1152 IMX_PIN_REG(MX6Q_PAD_DRAM_D31, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 */
1153 IMX_PIN_REG(MX6Q_PAD_DRAM_DQM3, 0x0520, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 */
1154 IMX_PIN_REG(MX6Q_PAD_DRAM_D16, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 */
1155 IMX_PIN_REG(MX6Q_PAD_DRAM_D17, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 */
1156 IMX_PIN_REG(MX6Q_PAD_DRAM_D18, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 */
1157 IMX_PIN_REG(MX6Q_PAD_DRAM_D19, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 */
1158 IMX_PIN_REG(MX6Q_PAD_DRAM_D20, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 */
1159 IMX_PIN_REG(MX6Q_PAD_DRAM_D21, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 */
1160 IMX_PIN_REG(MX6Q_PAD_DRAM_D22, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 */
1161 IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS2, 0x0524, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 */
1162 IMX_PIN_REG(MX6Q_PAD_DRAM_D23, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 */
1163 IMX_PIN_REG(MX6Q_PAD_DRAM_DQM2, 0x0528, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 */
1164 IMX_PIN_REG(MX6Q_PAD_DRAM_A0, 0x052C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 */
1165 IMX_PIN_REG(MX6Q_PAD_DRAM_A1, 0x0530, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 */
1166 IMX_PIN_REG(MX6Q_PAD_DRAM_A2, 0x0534, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 */
1167 IMX_PIN_REG(MX6Q_PAD_DRAM_A3, 0x0538, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 */
1168 IMX_PIN_REG(MX6Q_PAD_DRAM_A4, 0x053C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 */
1169 IMX_PIN_REG(MX6Q_PAD_DRAM_A5, 0x0540, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 */
1170 IMX_PIN_REG(MX6Q_PAD_DRAM_A6, 0x0544, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 */
1171 IMX_PIN_REG(MX6Q_PAD_DRAM_A7, 0x0548, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 */
1172 IMX_PIN_REG(MX6Q_PAD_DRAM_A8, 0x054C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 */
1173 IMX_PIN_REG(MX6Q_PAD_DRAM_A9, 0x0550, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 */
1174 IMX_PIN_REG(MX6Q_PAD_DRAM_A10, 0x0554, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 */
1175 IMX_PIN_REG(MX6Q_PAD_DRAM_A11, 0x0558, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 */
1176 IMX_PIN_REG(MX6Q_PAD_DRAM_A12, 0x055C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 */
1177 IMX_PIN_REG(MX6Q_PAD_DRAM_A13, 0x0560, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 */
1178 IMX_PIN_REG(MX6Q_PAD_DRAM_A14, 0x0564, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 */
1179 IMX_PIN_REG(MX6Q_PAD_DRAM_A15, 0x0568, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 */
1180 IMX_PIN_REG(MX6Q_PAD_DRAM_CAS, 0x056C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS */
1181 IMX_PIN_REG(MX6Q_PAD_DRAM_CS0, 0x0570, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 */
1182 IMX_PIN_REG(MX6Q_PAD_DRAM_CS1, 0x0574, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 */
1183 IMX_PIN_REG(MX6Q_PAD_DRAM_RAS, 0x0578, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS */
1184 IMX_PIN_REG(MX6Q_PAD_DRAM_RESET, 0x057C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET */
1185 IMX_PIN_REG(MX6Q_PAD_DRAM_SDBA0, 0x0580, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 */
1186 IMX_PIN_REG(MX6Q_PAD_DRAM_SDBA1, 0x0584, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 */
1187 IMX_PIN_REG(MX6Q_PAD_DRAM_SDCLK_0, 0x0588, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 */
1188 IMX_PIN_REG(MX6Q_PAD_DRAM_SDBA2, 0x058C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 */
1189 IMX_PIN_REG(MX6Q_PAD_DRAM_SDCKE0, 0x0590, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 */
1190 IMX_PIN_REG(MX6Q_PAD_DRAM_SDCLK_1, 0x0594, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 */
1191 IMX_PIN_REG(MX6Q_PAD_DRAM_SDCKE1, 0x0598, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 */
1192 IMX_PIN_REG(MX6Q_PAD_DRAM_SDODT0, 0x059C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 */
1193 IMX_PIN_REG(MX6Q_PAD_DRAM_SDODT1, 0x05A0, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 */
1194 IMX_PIN_REG(MX6Q_PAD_DRAM_SDWE, 0x05A4, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE */
1195 IMX_PIN_REG(MX6Q_PAD_DRAM_D0, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 */
1196 IMX_PIN_REG(MX6Q_PAD_DRAM_D1, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 */
1197 IMX_PIN_REG(MX6Q_PAD_DRAM_D2, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 */
1198 IMX_PIN_REG(MX6Q_PAD_DRAM_D3, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 */
1199 IMX_PIN_REG(MX6Q_PAD_DRAM_D4, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 */
1200 IMX_PIN_REG(MX6Q_PAD_DRAM_D5, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 */
1201 IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS0, 0x05A8, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 */
1202 IMX_PIN_REG(MX6Q_PAD_DRAM_D6, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 */
1203 IMX_PIN_REG(MX6Q_PAD_DRAM_D7, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 */
1204 IMX_PIN_REG(MX6Q_PAD_DRAM_DQM0, 0x05AC, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 */
1205 IMX_PIN_REG(MX6Q_PAD_DRAM_D8, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 */
1206 IMX_PIN_REG(MX6Q_PAD_DRAM_D9, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 */
1207 IMX_PIN_REG(MX6Q_PAD_DRAM_D10, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 */
1208 IMX_PIN_REG(MX6Q_PAD_DRAM_D11, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 */
1209 IMX_PIN_REG(MX6Q_PAD_DRAM_D12, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 */
1210 IMX_PIN_REG(MX6Q_PAD_DRAM_D13, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 */
1211 IMX_PIN_REG(MX6Q_PAD_DRAM_D14, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 */
1212 IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS1, 0x05B0, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 */
1213 IMX_PIN_REG(MX6Q_PAD_DRAM_D15, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 */
1214 IMX_PIN_REG(MX6Q_PAD_DRAM_DQM1, 0x05B4, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 */
1215 IMX_PIN_REG(MX6Q_PAD_DRAM_D48, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 */
1216 IMX_PIN_REG(MX6Q_PAD_DRAM_D49, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 */
1217 IMX_PIN_REG(MX6Q_PAD_DRAM_D50, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 */
1218 IMX_PIN_REG(MX6Q_PAD_DRAM_D51, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 */
1219 IMX_PIN_REG(MX6Q_PAD_DRAM_D52, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 */
1220 IMX_PIN_REG(MX6Q_PAD_DRAM_D53, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 */
1221 IMX_PIN_REG(MX6Q_PAD_DRAM_D54, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 */
1222 IMX_PIN_REG(MX6Q_PAD_DRAM_D55, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 */
1223 IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS6, 0x05B8, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 */
1224 IMX_PIN_REG(MX6Q_PAD_DRAM_DQM6, 0x05BC, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 */
1225 IMX_PIN_REG(MX6Q_PAD_DRAM_D56, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 */
1226 IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS7, 0x05C0, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 */
1227 IMX_PIN_REG(MX6Q_PAD_DRAM_D57, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 */
1228 IMX_PIN_REG(MX6Q_PAD_DRAM_D58, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 */
1229 IMX_PIN_REG(MX6Q_PAD_DRAM_D59, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 */
1230 IMX_PIN_REG(MX6Q_PAD_DRAM_D60, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 */
1231 IMX_PIN_REG(MX6Q_PAD_DRAM_DQM7, 0x05C4, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 */
1232 IMX_PIN_REG(MX6Q_PAD_DRAM_D61, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 */
1233 IMX_PIN_REG(MX6Q_PAD_DRAM_D62, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 */
1234 IMX_PIN_REG(MX6Q_PAD_DRAM_D63, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 */
1235 IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 0, 0x07F4, 2), /* MX6Q_PAD_KEY_COL0__ECSPI1_SCLK */
1236 IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 1, 0x0854, 1), /* MX6Q_PAD_KEY_COL0__ENET_RDATA_3 */
1237 IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 2, 0x07DC, 1), /* MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC */
1238 IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__KPP_COL_0 */
1239 IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 4, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__UART4_TXD */
1240 IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__GPIO_4_6 */
1241 IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT */
1242 IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST */
1243 IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 0, 0x07FC, 2), /* MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI */
1244 IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 */
1245 IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 2, 0x07D0, 1), /* MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */
1246 IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__KPP_ROW_0 */
1247 IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 4, 0x0938, 1), /* MX6Q_PAD_KEY_ROW0__UART4_RXD */
1248 IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__GPIO_4_7 */
1249 IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT */
1250 IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__PL301_PER1_HADR_0 */
1251 IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 0, 0x07F8, 2), /* MX6Q_PAD_KEY_COL1__ECSPI1_MISO */
1252 IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 1, 0x0840, 1), /* MX6Q_PAD_KEY_COL1__ENET_MDIO */
1253 IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 2, 0x07E0, 1), /* MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */
1254 IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__KPP_COL_1 */
1255 IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 4, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__UART5_TXD */
1256 IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__GPIO_4_8 */
1257 IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__USDHC1_VSELECT */
1258 IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__PL301MX_PER1_HADR_1 */
1259 IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 0, 0x0800, 2), /* MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 */
1260 IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__ENET_COL */
1261 IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 2, 0x07CC, 1), /* MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */
1262 IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__KPP_ROW_1 */
1263 IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 4, 0x0940, 1), /* MX6Q_PAD_KEY_ROW1__UART5_RXD */
1264 IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__GPIO_4_9 */
1265 IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT */
1266 IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__PL301_PER1_HADDR_2 */
1267 IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 0, 0x0804, 2), /* MX6Q_PAD_KEY_COL2__ECSPI1_SS1 */
1268 IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 1, 0x0850, 1), /* MX6Q_PAD_KEY_COL2__ENET_RDATA_2 */
1269 IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 2, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__CAN1_TXCAN */
1270 IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__KPP_COL_2 */
1271 IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 4, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__ENET_MDC */
1272 IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__GPIO_4_10 */
1273 IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__USBOH3_H1_PWRCTL_WKP */
1274 IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__PL301_PER1_HADDR_3 */
1275 IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 0, 0x0808, 1), /* MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 */
1276 IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 */
1277 IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 2, 0x07E4, 0), /* MX6Q_PAD_KEY_ROW2__CAN1_RXCAN */
1278 IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__KPP_ROW_2 */
1279 IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 4, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT */
1280 IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__GPIO_4_11 */
1281 IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 6, 0x088C, 1), /* MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE */
1282 IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__PL301_PER1_HADR_4 */
1283 IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 0, 0x080C, 1), /* MX6Q_PAD_KEY_COL3__ECSPI1_SS3 */
1284 IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 1, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__ENET_CRS */
1285 IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 2, 0x0890, 1), /* MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL */
1286 IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__KPP_COL_3 */
1287 IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 4, 0x08A0, 1), /* MX6Q_PAD_KEY_COL3__I2C2_SCL */
1288 IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__GPIO_4_12 */
1289 IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 6, 0x0914, 2), /* MX6Q_PAD_KEY_COL3__SPDIF_IN1 */
1290 IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__PL301_PER1_HADR_5 */
1291 IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 0, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT */
1292 IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 1, 0x07B0, 0), /* MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK */
1293 IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 2, 0x0894, 1), /* MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA */
1294 IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__KPP_ROW_3 */
1295 IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 4, 0x08A4, 1), /* MX6Q_PAD_KEY_ROW3__I2C2_SDA */
1296 IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__GPIO_4_13 */
1297 IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT */
1298 IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__PL301_PER1_HADR_6 */
1299 IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 0, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__CAN2_TXCAN */
1300 IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 1, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__IPU1_SISG_4 */
1301 IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 2, 0x0944, 1), /* MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC */
1302 IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__KPP_COL_4 */
1303 IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 4, 0x093C, 0), /* MX6Q_PAD_KEY_COL4__UART5_RTS */
1304 IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__GPIO_4_14 */
1305 IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__MMDC_DEBUG_49 */
1306 IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__PL301_PER1_HADDR_7 */
1307 IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 0, 0x07E8, 0), /* MX6Q_PAD_KEY_ROW4__CAN2_RXCAN */
1308 IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 */
1309 IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 2, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR */
1310 IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__KPP_ROW_4 */
1311 IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 4, 0x093C, 1), /* MX6Q_PAD_KEY_ROW4__UART5_CTS */
1312 IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__GPIO_4_15 */
1313 IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__MMDC_DEBUG_50 */
1314 IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__PL301_PER1_HADR_8 */
1315 IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 0, 0x0000, 0), /* MX6Q_PAD_GPIO_0__CCM_CLKO */
1316 IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 2, 0x08E8, 0), /* MX6Q_PAD_GPIO_0__KPP_COL_5 */
1317 IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 3, 0x07B0, 1), /* MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK */
1318 IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_0__EPIT1_EPITO */
1319 IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_0__GPIO_1_0 */
1320 IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR */
1321 IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_0__SNVS_HP_WRAP_SNVS_VIO5 */
1322 IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 0, 0x086C, 1), /* MX6Q_PAD_GPIO_1__ESAI1_SCKR */
1323 IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_1__WDOG2_WDOG_B */
1324 IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 2, 0x08F4, 0), /* MX6Q_PAD_GPIO_1__KPP_ROW_5 */
1325 IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_1__PWM2_PWMO */
1326 IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_1__GPIO_1_1 */
1327 IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_1__USDHC1_CD */
1328 IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_1__SRC_TESTER_ACK */
1329 IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 0, 0x085C, 1), /* MX6Q_PAD_GPIO_9__ESAI1_FSR */
1330 IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_9__WDOG1_WDOG_B */
1331 IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 2, 0x08EC, 0), /* MX6Q_PAD_GPIO_9__KPP_COL_6 */
1332 IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_9__CCM_REF_EN_B */
1333 IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_9__PWM1_PWMO */
1334 IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_9__GPIO_1_9 */
1335 IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 6, 0x094C, 1), /* MX6Q_PAD_GPIO_9__USDHC1_WP */
1336 IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_9__SRC_EARLY_RST */
1337 IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 0, 0x0864, 1), /* MX6Q_PAD_GPIO_3__ESAI1_HCKR */
1338 IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_3__OBSERVE_MUX_INT_OUT0 */
1339 IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 2, 0x08A8, 1), /* MX6Q_PAD_GPIO_3__I2C3_SCL */
1340 IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_3__ANATOP_24M_OUT */
1341 IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_3__CCM_CLKO2 */
1342 IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_3__GPIO_1_3 */
1343 IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 6, 0x0948, 1), /* MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC */
1344 IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 7, 0x0900, 1), /* MX6Q_PAD_GPIO_3__MLB_MLBCLK */
1345 IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 0, 0x0870, 1), /* MX6Q_PAD_GPIO_6__ESAI1_SCKT */
1346 IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_6__OBSERVE_MUX_INT_OUT1 */
1347 IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 2, 0x08AC, 1), /* MX6Q_PAD_GPIO_6__I2C3_SDA */
1348 IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 */
1349 IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB */
1350 IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_6__GPIO_1_6 */
1351 IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_6__USDHC2_LCTL */
1352 IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 7, 0x0908, 1), /* MX6Q_PAD_GPIO_6__MLB_MLBSIG */
1353 IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 0, 0x0860, 1), /* MX6Q_PAD_GPIO_2__ESAI1_FST */
1354 IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_2__OBSERVE_MUX_INT_OUT2 */
1355 IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 2, 0x08F8, 1), /* MX6Q_PAD_GPIO_2__KPP_ROW_6 */
1356 IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 */
1357 IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 */
1358 IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_2__GPIO_1_2 */
1359 IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_2__USDHC2_WP */
1360 IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 7, 0x0904, 1), /* MX6Q_PAD_GPIO_2__MLB_MLBDAT */
1361 IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 0, 0x0868, 1), /* MX6Q_PAD_GPIO_4__ESAI1_HCKT */
1362 IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_4__OBSERVE_MUX_INT_OUT3 */
1363 IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 2, 0x08F0, 1), /* MX6Q_PAD_GPIO_4__KPP_COL_7 */
1364 IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 */
1365 IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 */
1366 IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_4__GPIO_1_4 */
1367 IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_4__USDHC2_CD */
1368 IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_4__OCOTP_CRL_WRAR_FUSE_LA */
1369 IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 0, 0x087C, 1), /* MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 */
1370 IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_5__OBSERVE_MUX_INT_OUT4 */
1371 IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 2, 0x08FC, 1), /* MX6Q_PAD_GPIO_5__KPP_ROW_7 */
1372 IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_5__CCM_CLKO */
1373 IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 */
1374 IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_5__GPIO_1_5 */
1375 IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 6, 0x08A8, 2), /* MX6Q_PAD_GPIO_5__I2C3_SCL */
1376 IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_5__CHEETAH_EVENTI */
1377 IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 0, 0x0884, 1), /* MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 */
1378 IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_7__ECSPI5_RDY */
1379 IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_7__EPIT1_EPITO */
1380 IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_7__CAN1_TXCAN */
1381 IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_7__UART2_TXD */
1382 IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_7__GPIO_1_7 */
1383 IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_7__SPDIF_PLOCK */
1384 IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HST_MODE */
1385 IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 0, 0x0888, 1), /* MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 */
1386 IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT */
1387 IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_8__EPIT2_EPITO */
1388 IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 3, 0x07E4, 1), /* MX6Q_PAD_GPIO_8__CAN1_RXCAN */
1389 IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 4, 0x0928, 3), /* MX6Q_PAD_GPIO_8__UART2_RXD */
1390 IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_8__GPIO_1_8 */
1391 IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_8__SPDIF_SRCLK */
1392 IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_8__USBOH3_OTG_PWRCTL_WAK */
1393 IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 0, 0x0880, 1), /* MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 */
1394 IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN */
1395 IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 2, 0x083C, 1), /* MX6Q_PAD_GPIO_16__ENET_ETHERNET_REF_OUT */
1396 IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_16__USDHC1_LCTL */
1397 IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 4, 0x0914, 3), /* MX6Q_PAD_GPIO_16__SPDIF_IN1 */
1398 IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_16__GPIO_7_11 */
1399 IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 6, 0x08AC, 2), /* MX6Q_PAD_GPIO_16__I2C3_SDA */
1400 IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_16__SJC_DE_B */
1401 IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 0, 0x0874, 0), /* MX6Q_PAD_GPIO_17__ESAI1_TX0 */
1402 IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN */
1403 IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 2, 0x07F0, 1), /* MX6Q_PAD_GPIO_17__CCM_PMIC_RDY */
1404 IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 3, 0x090C, 1), /* MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 */
1405 IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_17__SPDIF_OUT1 */
1406 IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_17__GPIO_7_12 */
1407 IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_17__SJC_JTAG_ACT */
1408 IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 0, 0x0878, 0), /* MX6Q_PAD_GPIO_18__ESAI1_TX1 */
1409 IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 1, 0x0844, 1), /* MX6Q_PAD_GPIO_18__ENET_RX_CLK */
1410 IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_18__USDHC3_VSELECT */
1411 IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 3, 0x0910, 1), /* MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 */
1412 IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 4, 0x07B0, 2), /* MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK */
1413 IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_18__GPIO_7_13 */
1414 IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_18__SNVS_HP_WRA_SNVS_VIO5 */
1415 IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST */
1416 IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 0, 0x08E8, 1), /* MX6Q_PAD_GPIO_19__KPP_COL_5 */
1417 IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT */
1418 IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_19__SPDIF_OUT1 */
1419 IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_19__CCM_CLKO */
1420 IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_19__ECSPI1_RDY */
1421 IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_19__GPIO_4_5 */
1422 IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_19__ENET_TX_ER */
1423 IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_19__SRC_INT_BOOT */
1424 IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK */
1425 IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_MUX_12 */
1426 IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 */
1427 IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 */
1428 IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK___MMDC_DEBUG_29 */
1429 IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO */
1430 IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC */
1431 IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_MUX_13 */
1432 IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__CCM_CLKO */
1433 IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 */
1434 IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__GPIO_5_19 */
1435 IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 */
1436 IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL */
1437 IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DA_EN */
1438 IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 */
1439 IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_MUX_14 */
1440 IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 */
1441 IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 */
1442 IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__MMDC_DEBUG_31 */
1443 IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK */
1444 IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC */
1445 IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 */
1446 IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_MUX_15 */
1447 IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 */
1448 IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 */
1449 IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__MMDC_DEBUG_32 */
1450 IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 */
1451 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 */
1452 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 */
1453 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 2, 0x07F4, 3), /* MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK */
1454 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 3, 0x08E8, 2), /* MX6Q_PAD_CSI0_DAT4__KPP_COL_5 */
1455 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC */
1456 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__GPIO_5_22 */
1457 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__MMDC_DEBUG_43 */
1458 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 */
1459 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 */
1460 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 */
1461 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 2, 0x07FC, 3), /* MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI */
1462 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 3, 0x08F4, 1), /* MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 */
1463 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD */
1464 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__GPIO_5_23 */
1465 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 */
1466 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 */
1467 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 */
1468 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 */
1469 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 2, 0x07F8, 3), /* MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO */
1470 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 3, 0x08EC, 1), /* MX6Q_PAD_CSI0_DAT6__KPP_COL_6 */
1471 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS */
1472 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__GPIO_5_24 */
1473 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 */
1474 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 */
1475 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 */
1476 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 */
1477 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 2, 0x0800, 3), /* MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 */
1478 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 3, 0x08F8, 2), /* MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 */
1479 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD */
1480 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__GPIO_5_25 */
1481 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 */
1482 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 */
1483 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 */
1484 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 */
1485 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 2, 0x0810, 2), /* MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK */
1486 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 3, 0x08F0, 2), /* MX6Q_PAD_CSI0_DAT8__KPP_COL_7 */
1487 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 4, 0x089C, 1), /* MX6Q_PAD_CSI0_DAT8__I2C1_SDA */
1488 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__GPIO_5_26 */
1489 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 */
1490 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 */
1491 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 */
1492 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 */
1493 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 2, 0x0818, 2), /* MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI */
1494 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 3, 0x08FC, 2), /* MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 */
1495 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 4, 0x0898, 1), /* MX6Q_PAD_CSI0_DAT9__I2C1_SCL */
1496 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__GPIO_5_27 */
1497 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 */
1498 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 */
1499 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 */
1500 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC */
1501 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 2, 0x0814, 2), /* MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO */
1502 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */
1503 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 */
1504 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__GPIO_5_28 */
1505 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 */
1506 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 */
1507 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 */
1508 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS */
1509 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 2, 0x081C, 2), /* MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 */
1510 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 3, 0x0920, 1), /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */
1511 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 */
1512 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__GPIO_5_29 */
1513 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 */
1514 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 */
1515 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 */
1516 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 */
1517 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_MUX_16 */
1518 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__UART4_TXD */
1519 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 */
1520 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__GPIO_5_30 */
1521 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 */
1522 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 */
1523 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 */
1524 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 */
1525 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_MUX_17 */
1526 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 3, 0x0938, 3), /* MX6Q_PAD_CSI0_DAT13__UART4_RXD */
1527 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 */
1528 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__GPIO_5_31 */
1529 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 */
1530 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 */
1531 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 */
1532 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 */
1533 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_MUX_18 */
1534 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__UART5_TXD */
1535 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 */
1536 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__GPIO_6_0 */
1537 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 */
1538 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 */
1539 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 */
1540 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 */
1541 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_MUX_19 */
1542 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 3, 0x0940, 3), /* MX6Q_PAD_CSI0_DAT15__UART5_RXD */
1543 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 */
1544 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__GPIO_6_1 */
1545 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 */
1546 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 */
1547 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 */
1548 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 */
1549 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_MUX_20 */
1550 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 3, 0x0934, 0), /* MX6Q_PAD_CSI0_DAT16__UART4_RTS */
1551 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 */
1552 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__GPIO_6_2 */
1553 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 */
1554 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 */
1555 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 */
1556 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 */
1557 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_MUX_21 */
1558 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 3, 0x0934, 1), /* MX6Q_PAD_CSI0_DAT17__UART4_CTS */
1559 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 */
1560 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__GPIO_6_3 */
1561 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 */
1562 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 */
1563 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 */
1564 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 */
1565 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_MUX_22 */
1566 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 3, 0x093C, 2), /* MX6Q_PAD_CSI0_DAT18__UART5_RTS */
1567 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 */
1568 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__GPIO_6_4 */
1569 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 */
1570 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 */
1571 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 */
1572 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 */
1573 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_MUX_23 */
1574 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 3, 0x093C, 3), /* MX6Q_PAD_CSI0_DAT19__UART5_CTS */
1575 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 */
1576 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__GPIO_6_5 */
1577 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 */
1578 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__ANATOP_TESTO_9 */
1579 IMX_PIN_REG(MX6Q_PAD_JTAG_TMS, 0x0678, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TMS__SJC_TMS */
1580 IMX_PIN_REG(MX6Q_PAD_JTAG_MOD, 0x067C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_MOD__SJC_MOD */
1581 IMX_PIN_REG(MX6Q_PAD_JTAG_TRSTB, 0x0680, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB */
1582 IMX_PIN_REG(MX6Q_PAD_JTAG_TDI, 0x0684, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TDI__SJC_TDI */
1583 IMX_PIN_REG(MX6Q_PAD_JTAG_TCK, 0x0688, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TCK__SJC_TCK */
1584 IMX_PIN_REG(MX6Q_PAD_JTAG_TDO, 0x068C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TDO__SJC_TDO */
1585 IMX_PIN_REG(MX6Q_PAD_LVDS1_TX3_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 */
1586 IMX_PIN_REG(MX6Q_PAD_LVDS1_TX2_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 */
1587 IMX_PIN_REG(MX6Q_PAD_LVDS1_CLK_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK */
1588 IMX_PIN_REG(MX6Q_PAD_LVDS1_TX1_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 */
1589 IMX_PIN_REG(MX6Q_PAD_LVDS1_TX0_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 */
1590 IMX_PIN_REG(MX6Q_PAD_LVDS0_TX3_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 */
1591 IMX_PIN_REG(MX6Q_PAD_LVDS0_CLK_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK */
1592 IMX_PIN_REG(MX6Q_PAD_LVDS0_TX2_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 */
1593 IMX_PIN_REG(MX6Q_PAD_LVDS0_TX1_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 */
1594 IMX_PIN_REG(MX6Q_PAD_LVDS0_TX0_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 */
1595 IMX_PIN_REG(MX6Q_PAD_TAMPER, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_TAMPER__SNVS_LP_WRAP_SNVS_TD1 */
1596 IMX_PIN_REG(MX6Q_PAD_PMIC_ON_REQ, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_PMIC_ON_REQ__SNVS_LPWRAP_WKALM */
1597 IMX_PIN_REG(MX6Q_PAD_PMIC_STBY_REQ, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_STBYRQ */
1598 IMX_PIN_REG(MX6Q_PAD_POR_B, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_POR_B__SRC_POR_B */
1599 IMX_PIN_REG(MX6Q_PAD_BOOT_MODE1, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 */
1600 IMX_PIN_REG(MX6Q_PAD_RESET_IN_B, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_RESET_IN_B__SRC_RESET_B */
1601 IMX_PIN_REG(MX6Q_PAD_BOOT_MODE0, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 */
1602 IMX_PIN_REG(MX6Q_PAD_TEST_MODE, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_TEST_MODE__TCU_TEST_MODE */
1603 IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
1604 IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 1, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__UART1_TXD */
1605 IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__PCIE_CTRL_MUX_24 */
1606 IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 */
1607 IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 */
1608 IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__GPIO_6_17 */
1609 IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_IN_12 */
1610 IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USBPHY2_CLK20DIV */
1611 IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
1612 IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 1, 0x0920, 3), /* MX6Q_PAD_SD3_DAT6__UART1_RXD */
1613 IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__PCIE_CTRL_MUX_25 */
1614 IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 */
1615 IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 */
1616 IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__GPIO_6_18 */
1617 IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_IN_13 */
1618 IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__ANATOP_TESTO_10 */
1619 IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
1620 IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 1, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__UART2_TXD */
1621 IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__PCIE_CTRL_MUX_26 */
1622 IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 */
1623 IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 */
1624 IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */
1625 IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_IN_14 */
1626 IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__ANATOP_TESTO_11 */
1627 IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
1628 IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 1, 0x0928, 5), /* MX6Q_PAD_SD3_DAT4__UART2_RXD */
1629 IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__PCIE_CTRL_MUX_27 */
1630 IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 */
1631 IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 */
1632 IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */
1633 IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_IN_15 */
1634 IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__ANATOP_TESTO_12 */
1635 IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 0, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
1636 IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 1, 0x0924, 2), /* MX6Q_PAD_SD3_CMD__UART2_CTS */
1637 IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 2, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__CAN1_TXCAN */
1638 IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 3, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 */
1639 IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 4, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 */
1640 IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 5, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__GPIO_7_2 */
1641 IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 6, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_IN_16 */
1642 IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 7, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__ANATOP_TESTO_13 */
1643 IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 0, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
1644 IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 1, 0x0924, 3), /* MX6Q_PAD_SD3_CLK__UART2_RTS */
1645 IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 2, 0x07E4, 2), /* MX6Q_PAD_SD3_CLK__CAN1_RXCAN */
1646 IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 3, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 */
1647 IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 4, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 */
1648 IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 5, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__GPIO_7_3 */
1649 IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 6, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_IN_17 */
1650 IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 7, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__ANATOP_TESTO_14 */
1651 IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
1652 IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 1, 0x091C, 2), /* MX6Q_PAD_SD3_DAT0__UART1_CTS */
1653 IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__CAN2_TXCAN */
1654 IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 */
1655 IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 */
1656 IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__GPIO_7_4 */
1657 IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_IN_18 */
1658 IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__ANATOP_TESTO_15 */
1659 IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
1660 IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 1, 0x091C, 3), /* MX6Q_PAD_SD3_DAT1__UART1_RTS */
1661 IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 2, 0x07E8, 1), /* MX6Q_PAD_SD3_DAT1__CAN2_RXCAN */
1662 IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 */
1663 IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 */
1664 IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__GPIO_7_5 */
1665 IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_IN_19 */
1666 IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__ANATOP_TESTI_0 */
1667 IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
1668 IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__PCIE_CTRL_MUX_28 */
1669 IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 */
1670 IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 */
1671 IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__GPIO_7_6 */
1672 IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_IN_20 */
1673 IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__ANATOP_TESTI_1 */
1674 IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
1675 IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 1, 0x092C, 4), /* MX6Q_PAD_SD3_DAT3__UART3_CTS */
1676 IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__PCIE_CTRL_MUX_29 */
1677 IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 */
1678 IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 */
1679 IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__GPIO_7_7 */
1680 IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_IN_21 */
1681 IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__ANATOP_TESTI_2 */
1682 IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 0, 0x0000, 0), /* MX6Q_PAD_SD3_RST__USDHC3_RST */
1683 IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 1, 0x092C, 5), /* MX6Q_PAD_SD3_RST__UART3_RTS */
1684 IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 2, 0x0000, 0), /* MX6Q_PAD_SD3_RST__PCIE_CTRL_MUX_30 */
1685 IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 3, 0x0000, 0), /* MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 */
1686 IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 4, 0x0000, 0), /* MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 */
1687 IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 5, 0x0000, 0), /* MX6Q_PAD_SD3_RST__GPIO_7_8 */
1688 IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 6, 0x0000, 0), /* MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_IN_22 */
1689 IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 7, 0x0000, 0), /* MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 */
1690 IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
1691 IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 */
1692 IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__PCIE_CTRL_MUX_31 */
1693 IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OT11 */
1694 IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OT11 */
1695 IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__GPIO_6_7 */
1696 IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_IN23 */
1697 IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 */
1698 IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
1699 IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__USDHC4_RST */
1700 IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__PCIE_CTRL_MUX_0 */
1701 IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OT12 */
1702 IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OT12 */
1703 IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__GPIO_6_8 */
1704 IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__MIPI_CR_DPHY_IN_24 */
1705 IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 */
1706 IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
1707 IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 */
1708 IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__PCIE_CTRL__MUX_1 */
1709 IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFDOT13 */
1710 IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFDOT13 */
1711 IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__GPIO_6_9 */
1712 IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__MIPI_CR_DPHY_OUT32 */
1713 IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__PL301_PER1_HSIZE_0 */
1714 IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
1715 IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 */
1716 IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__PCIE_CTRL_MUX_2 */
1717 IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OT14 */
1718 IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OT14 */
1719 IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__GPIO_6_10 */
1720 IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__MIPI_CR_DPHY_OUT_33 */
1721 IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__PL301_PER1_HSIZE_1 */
1722 IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
1723 IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OT15 */
1724 IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OT15 */
1725 IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */
1726 IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__PL301_PER1_HSIZE_2 */
1727 IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
1728 IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT */
1729 IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT */
1730 IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__PCIE_CTRL_MUX_3 */
1731 IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */
1732 IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__PL301_PER1_HRDYOUT */
1733 IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
1734 IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 */
1735 IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 2, 0x0874, 1), /* MX6Q_PAD_NANDF_CS2__ESAI1_TX0 */
1736 IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE */
1737 IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__CCM_CLKO2 */
1738 IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__GPIO_6_15 */
1739 IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 */
1740 IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
1741 IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 */
1742 IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 2, 0x0878, 1), /* MX6Q_PAD_NANDF_CS3__ESAI1_TX1 */
1743 IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 */
1744 IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__PCIE_CTRL_MUX_4 */
1745 IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__GPIO_6_16 */
1746 IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 */
1747 IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__TPSMP_CLK */
1748 IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 0, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
1749 IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 1, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
1750 IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 2, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__UART3_TXD */
1751 IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 4, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__PCIE_CTRL_MUX_5 */
1752 IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 5, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__GPIO_7_9 */
1753 IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 7, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR */
1754 IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 0, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
1755 IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 1, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
1756 IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 2, 0x0930, 3), /* MX6Q_PAD_SD4_CLK__UART3_RXD */
1757 IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 4, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__PCIE_CTRL_MUX_6 */
1758 IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 5, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__GPIO_7_10 */
1759 IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
1760 IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__USDHC1_DAT4 */
1761 IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__GPU3D_GPU_DBG_OUT_0 */
1762 IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT16 */
1763 IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT16 */
1764 IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */
1765 IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 */
1766 IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 */
1767 IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
1768 IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__USDHC1_DAT5 */
1769 IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT1 */
1770 IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT17 */
1771 IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT17 */
1772 IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */
1773 IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 */
1774 IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 */
1775 IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
1776 IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__USDHC1_DAT6 */
1777 IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__GPU3D_GPU_DBG_OUT_2 */
1778 IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT18 */
1779 IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT18 */
1780 IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */
1781 IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 */
1782 IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 */
1783 IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
1784 IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__USDHC1_DAT7 */
1785 IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__GPU3D_GPU_DBG_OUT_3 */
1786 IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT19 */
1787 IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT19 */
1788 IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */
1789 IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 */
1790 IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 */
1791 IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
1792 IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */
1793 IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__GPU3D_GPU_DBG_OUT_4 */
1794 IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT20 */
1795 IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT20 */
1796 IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__GPIO_2_4 */
1797 IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 */
1798 IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 */
1799 IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
1800 IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */
1801 IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__GPU3D_GPU_DBG_OUT_5 */
1802 IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT21 */
1803 IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT21 */
1804 IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__GPIO_2_5 */
1805 IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 */
1806 IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 */
1807 IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
1808 IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */
1809 IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__GPU3D_GPU_DBG_OUT_6 */
1810 IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT22 */
1811 IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT22 */
1812 IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */
1813 IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 */
1814 IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 */
1815 IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
1816 IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */
1817 IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__GPU3D_GPU_DBG_OUT_7 */
1818 IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT23 */
1819 IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT23 */
1820 IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */
1821 IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 */
1822 IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 */
1823 IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__RAWNAND_D8 */
1824 IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
1825 IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
1826 IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT24 */
1827 IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT24 */
1828 IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__GPIO_2_8 */
1829 IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 */
1830 IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 */
1831 IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__RAWNAND_D9 */
1832 IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
1833 IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__PWM3_PWMO */
1834 IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT25 */
1835 IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT25 */
1836 IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__GPIO_2_9 */
1837 IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 */
1838 IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 */
1839 IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__RAWNAND_D10 */
1840 IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
1841 IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__PWM4_PWMO */
1842 IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT26 */
1843 IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT26 */
1844 IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__GPIO_2_10 */
1845 IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 */
1846 IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 */
1847 IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__RAWNAND_D11 */
1848 IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
1849 IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT27 */
1850 IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT27 */
1851 IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__GPIO_2_11 */
1852 IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 */
1853 IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 */
1854 IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__RAWNAND_D12 */
1855 IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
1856 IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 2, 0x0928, 6), /* MX6Q_PAD_SD4_DAT4__UART2_RXD */
1857 IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT28 */
1858 IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT28 */
1859 IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__GPIO_2_12 */
1860 IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 */
1861 IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 */
1862 IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__RAWNAND_D13 */
1863 IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
1864 IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 2, 0x0924, 4), /* MX6Q_PAD_SD4_DAT5__UART2_RTS */
1865 IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT29 */
1866 IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT29 */
1867 IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__GPIO_2_13 */
1868 IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 */
1869 IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 */
1870 IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__RAWNAND_D14 */
1871 IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
1872 IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 2, 0x0924, 5), /* MX6Q_PAD_SD4_DAT6__UART2_CTS */
1873 IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT30 */
1874 IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT30 */
1875 IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__GPIO_2_14 */
1876 IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 */
1877 IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 */
1878 IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__RAWNAND_D15 */
1879 IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
1880 IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__UART2_TXD */
1881 IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT31 */
1882 IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT31 */
1883 IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__GPIO_2_15 */
1884 IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 */
1885 IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 */
1886 IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 */
1887 IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 1, 0x0834, 1), /* MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 */
1888 IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__PWM3_PWMO */
1889 IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 */
1890 IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__PCIE_CTRL_MUX_7 */
1891 IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__GPIO_1_17 */
1892 IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 */
1893 IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__ANATOP_TESTO_8 */
1894 IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 */
1895 IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 1, 0x082C, 1), /* MX6Q_PAD_SD1_DAT0__ECSPI5_MISO */
1896 IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__CAAM_WRAP_RNG_OSCOBS */
1897 IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 */
1898 IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__PCIE_CTRL_MUX_8 */
1899 IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__GPIO_1_16 */
1900 IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 */
1901 IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__ANATOP_TESTO_7 */
1902 IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 */
1903 IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 1, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 */
1904 IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 */
1905 IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__PWM1_PWMO */
1906 IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B */
1907 IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__GPIO_1_21 */
1908 IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB */
1909 IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__ANATOP_TESTO_6 */
1910 IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 0, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__USDHC1_CMD */
1911 IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 1, 0x0830, 0), /* MX6Q_PAD_SD1_CMD__ECSPI5_MOSI */
1912 IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 2, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__PWM4_PWMO */
1913 IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 3, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 */
1914 IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 5, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__GPIO_1_18 */
1915 IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 7, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__ANATOP_TESTO_5 */
1916 IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 */
1917 IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 1, 0x0838, 1), /* MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 */
1918 IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 */
1919 IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__PWM2_PWMO */
1920 IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B */
1921 IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__GPIO_1_19 */
1922 IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB */
1923 IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__ANATOP_TESTO_4 */
1924 IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 0, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__USDHC1_CLK */
1925 IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 1, 0x0828, 0), /* MX6Q_PAD_SD1_CLK__ECSPI5_SCLK */
1926 IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 2, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT */
1927 IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 3, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__GPT_CLKIN */
1928 IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 5, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__GPIO_1_20 */
1929 IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 6, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__PHY_DTB_0 */
1930 IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 7, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 */
1931 IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 0, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */
1932 IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 1, 0x0828, 1), /* MX6Q_PAD_SD2_CLK__ECSPI5_SCLK */
1933 IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 2, 0x08E8, 3), /* MX6Q_PAD_SD2_CLK__KPP_COL_5 */
1934 IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 3, 0x07C0, 1), /* MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS */
1935 IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 4, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__PCIE_CTRL_MUX_9 */
1936 IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 5, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__GPIO_1_10 */
1937 IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 6, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__PHY_DTB_1 */
1938 IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 7, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 */
1939 IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 0, 0x0000, 0), /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */
1940 IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 1, 0x0830, 1), /* MX6Q_PAD_SD2_CMD__ECSPI5_MOSI */
1941 IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 2, 0x08F4, 2), /* MX6Q_PAD_SD2_CMD__KPP_ROW_5 */
1942 IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 3, 0x07BC, 1), /* MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC */
1943 IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 4, 0x0000, 0), /* MX6Q_PAD_SD2_CMD__PCIE_CTRL_MUX_10 */
1944 IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 5, 0x0000, 0), /* MX6Q_PAD_SD2_CMD__GPIO_1_11 */
1945 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */
1946 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 1, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 */
1947 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 2, 0x08EC, 2), /* MX6Q_PAD_SD2_DAT3__KPP_COL_6 */
1948 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 3, 0x07C4, 1), /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
1949 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 4, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__PCIE_CTRL_MUX_11 */
1950 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__GPIO_1_12 */
1951 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__SJC_DONE */
1952 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__ANATOP_TESTO_3 */
1953};
1954
1955/* Pad names for the pinmux subsystem */
1956static const struct pinctrl_pin_desc imx6q_pinctrl_pads[] = {
1957 IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT1),
1958 IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT2),
1959 IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT0),
1960 IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TXC),
1961 IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD0),
1962 IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD1),
1963 IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD2),
1964 IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD3),
1965 IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RX_CTL),
1966 IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD0),
1967 IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TX_CTL),
1968 IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD1),
1969 IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD2),
1970 IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD3),
1971 IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RXC),
1972 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A25),
1973 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB2),
1974 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D16),
1975 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D17),
1976 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D18),
1977 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D19),
1978 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D20),
1979 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D21),
1980 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D22),
1981 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D23),
1982 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB3),
1983 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D24),
1984 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D25),
1985 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D26),
1986 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D27),
1987 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D28),
1988 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D29),
1989 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D30),
1990 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D31),
1991 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A24),
1992 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A23),
1993 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A22),
1994 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A21),
1995 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A20),
1996 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A19),
1997 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A18),
1998 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A17),
1999 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A16),
2000 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_CS0),
2001 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_CS1),
2002 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_OE),
2003 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_RW),
2004 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_LBA),
2005 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB0),
2006 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB1),
2007 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA0),
2008 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA1),
2009 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA2),
2010 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA3),
2011 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA4),
2012 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA5),
2013 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA6),
2014 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA7),
2015 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA8),
2016 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA9),
2017 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA10),
2018 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA11),
2019 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA12),
2020 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA13),
2021 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA14),
2022 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA15),
2023 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_WAIT),
2024 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_BCLK),
2025 IMX_PINCTRL_PIN(MX6Q_PAD_DI0_DISP_CLK),
2026 IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN15),
2027 IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN2),
2028 IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN3),
2029 IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN4),
2030 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT0),
2031 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT1),
2032 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT2),
2033 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT3),
2034 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT4),
2035 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT5),
2036 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT6),
2037 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT7),
2038 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT8),
2039 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT9),
2040 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT10),
2041 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT11),
2042 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT12),
2043 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT13),
2044 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT14),
2045 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT15),
2046 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT16),
2047 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT17),
2048 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT18),
2049 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT19),
2050 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT20),
2051 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT21),
2052 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT22),
2053 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT23),
2054 IMX_PINCTRL_PIN(MX6Q_PAD_ENET_MDIO),
2055 IMX_PINCTRL_PIN(MX6Q_PAD_ENET_REF_CLK),
2056 IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RX_ER),
2057 IMX_PINCTRL_PIN(MX6Q_PAD_ENET_CRS_DV),
2058 IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RXD1),
2059 IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RXD0),
2060 IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TX_EN),
2061 IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TXD1),
2062 IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TXD0),
2063 IMX_PINCTRL_PIN(MX6Q_PAD_ENET_MDC),
2064 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D40),
2065 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D41),
2066 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D42),
2067 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D43),
2068 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D44),
2069 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D45),
2070 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D46),
2071 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D47),
2072 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS5),
2073 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM5),
2074 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D32),
2075 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D33),
2076 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D34),
2077 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D35),
2078 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D36),
2079 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D37),
2080 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D38),
2081 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D39),
2082 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM4),
2083 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS4),
2084 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D24),
2085 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D25),
2086 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D26),
2087 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D27),
2088 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D28),
2089 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D29),
2090 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS3),
2091 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D30),
2092 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D31),
2093 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM3),
2094 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D16),
2095 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D17),
2096 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D18),
2097 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D19),
2098 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D20),
2099 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D21),
2100 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D22),
2101 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS2),
2102 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D23),
2103 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM2),
2104 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A0),
2105 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A1),
2106 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A2),
2107 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A3),
2108 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A4),
2109 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A5),
2110 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A6),
2111 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A7),
2112 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A8),
2113 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A9),
2114 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A10),
2115 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A11),
2116 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A12),
2117 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A13),
2118 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A14),
2119 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A15),
2120 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_CAS),
2121 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_CS0),
2122 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_CS1),
2123 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_RAS),
2124 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_RESET),
2125 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDBA0),
2126 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDBA1),
2127 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCLK_0),
2128 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDBA2),
2129 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCKE0),
2130 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCLK_1),
2131 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCKE1),
2132 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDODT0),
2133 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDODT1),
2134 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDWE),
2135 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D0),
2136 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D1),
2137 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D2),
2138 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D3),
2139 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D4),
2140 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D5),
2141 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS0),
2142 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D6),
2143 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D7),
2144 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM0),
2145 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D8),
2146 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D9),
2147 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D10),
2148 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D11),
2149 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D12),
2150 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D13),
2151 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D14),
2152 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS1),
2153 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D15),
2154 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM1),
2155 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D48),
2156 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D49),
2157 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D50),
2158 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D51),
2159 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D52),
2160 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D53),
2161 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D54),
2162 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D55),
2163 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS6),
2164 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM6),
2165 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D56),
2166 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS7),
2167 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D57),
2168 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D58),
2169 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D59),
2170 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D60),
2171 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM7),
2172 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D61),
2173 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D62),
2174 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D63),
2175 IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL0),
2176 IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW0),
2177 IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL1),
2178 IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW1),
2179 IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL2),
2180 IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW2),
2181 IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL3),
2182 IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW3),
2183 IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL4),
2184 IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW4),
2185 IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_0),
2186 IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_1),
2187 IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_9),
2188 IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_3),
2189 IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_6),
2190 IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_2),
2191 IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_4),
2192 IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_5),
2193 IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_7),
2194 IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_8),
2195 IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_16),
2196 IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_17),
2197 IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_18),
2198 IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_19),
2199 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_PIXCLK),
2200 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_MCLK),
2201 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DATA_EN),
2202 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_VSYNC),
2203 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT4),
2204 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT5),
2205 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT6),
2206 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT7),
2207 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT8),
2208 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT9),
2209 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT10),
2210 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT11),
2211 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT12),
2212 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT13),
2213 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT14),
2214 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT15),
2215 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT16),
2216 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT17),
2217 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT18),
2218 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT19),
2219 IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TMS),
2220 IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_MOD),
2221 IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TRSTB),
2222 IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TDI),
2223 IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TCK),
2224 IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TDO),
2225 IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX3_P),
2226 IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX2_P),
2227 IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_CLK_P),
2228 IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX1_P),
2229 IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX0_P),
2230 IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX3_P),
2231 IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_CLK_P),
2232 IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX2_P),
2233 IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX1_P),
2234 IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX0_P),
2235 IMX_PINCTRL_PIN(MX6Q_PAD_TAMPER),
2236 IMX_PINCTRL_PIN(MX6Q_PAD_PMIC_ON_REQ),
2237 IMX_PINCTRL_PIN(MX6Q_PAD_PMIC_STBY_REQ),
2238 IMX_PINCTRL_PIN(MX6Q_PAD_POR_B),
2239 IMX_PINCTRL_PIN(MX6Q_PAD_BOOT_MODE1),
2240 IMX_PINCTRL_PIN(MX6Q_PAD_RESET_IN_B),
2241 IMX_PINCTRL_PIN(MX6Q_PAD_BOOT_MODE0),
2242 IMX_PINCTRL_PIN(MX6Q_PAD_TEST_MODE),
2243 IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT7),
2244 IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT6),
2245 IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT5),
2246 IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT4),
2247 IMX_PINCTRL_PIN(MX6Q_PAD_SD3_CMD),
2248 IMX_PINCTRL_PIN(MX6Q_PAD_SD3_CLK),
2249 IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT0),
2250 IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT1),
2251 IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT2),
2252 IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT3),
2253 IMX_PINCTRL_PIN(MX6Q_PAD_SD3_RST),
2254 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CLE),
2255 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_ALE),
2256 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_WP_B),
2257 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_RB0),
2258 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS0),
2259 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS1),
2260 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS2),
2261 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS3),
2262 IMX_PINCTRL_PIN(MX6Q_PAD_SD4_CMD),
2263 IMX_PINCTRL_PIN(MX6Q_PAD_SD4_CLK),
2264 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D0),
2265 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D1),
2266 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D2),
2267 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D3),
2268 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D4),
2269 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D5),
2270 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D6),
2271 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D7),
2272 IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT0),
2273 IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT1),
2274 IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT2),
2275 IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT3),
2276 IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT4),
2277 IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT5),
2278 IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT6),
2279 IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT7),
2280 IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT1),
2281 IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT0),
2282 IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT3),
2283 IMX_PINCTRL_PIN(MX6Q_PAD_SD1_CMD),
2284 IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT2),
2285 IMX_PINCTRL_PIN(MX6Q_PAD_SD1_CLK),
2286 IMX_PINCTRL_PIN(MX6Q_PAD_SD2_CLK),
2287 IMX_PINCTRL_PIN(MX6Q_PAD_SD2_CMD),
2288 IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT3),
2289};
2290
2291static struct imx_pinctrl_soc_info imx6q_pinctrl_info = {
2292 .pins = imx6q_pinctrl_pads,
2293 .npins = ARRAY_SIZE(imx6q_pinctrl_pads),
2294 .pin_regs = imx6q_pin_regs,
2295 .npin_regs = ARRAY_SIZE(imx6q_pin_regs),
2296};
2297
2298static struct of_device_id imx6q_pinctrl_of_match[] __devinitdata = {
2299 { .compatible = "fsl,imx6q-iomuxc", },
2300 { /* sentinel */ }
2301};
2302
2303static int __devinit imx6q_pinctrl_probe(struct platform_device *pdev)
2304{
2305 return imx_pinctrl_probe(pdev, &imx6q_pinctrl_info);
2306}
2307
2308static struct platform_driver imx6q_pinctrl_driver = {
2309 .driver = {
2310 .name = "imx6q-pinctrl",
2311 .owner = THIS_MODULE,
2312 .of_match_table = of_match_ptr(imx6q_pinctrl_of_match),
2313 },
2314 .probe = imx6q_pinctrl_probe,
2315 .remove = __devexit_p(imx_pinctrl_remove),
2316};
2317
2318static int __init imx6q_pinctrl_init(void)
2319{
2320 return platform_driver_register(&imx6q_pinctrl_driver);
2321}
2322arch_initcall(imx6q_pinctrl_init);
2323
2324static void __exit imx6q_pinctrl_exit(void)
2325{
2326 platform_driver_unregister(&imx6q_pinctrl_driver);
2327}
2328module_exit(imx6q_pinctrl_exit);
2329MODULE_AUTHOR("Dong Aisheng <dong.aisheng@linaro.org>");
2330MODULE_DESCRIPTION("Freescale IMX6Q pinctrl driver");
2331MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-mxs.c b/drivers/pinctrl/pinctrl-mxs.c
new file mode 100644
index 00000000000..556e45a213e
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-mxs.c
@@ -0,0 +1,528 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <linux/err.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18#include <linux/pinctrl/machine.h>
19#include <linux/pinctrl/pinconf.h>
20#include <linux/pinctrl/pinctrl.h>
21#include <linux/pinctrl/pinmux.h>
22#include <linux/platform_device.h>
23#include <linux/slab.h>
24#include "core.h"
25#include "pinctrl-mxs.h"
26
27#define SUFFIX_LEN 4
28
29struct mxs_pinctrl_data {
30 struct device *dev;
31 struct pinctrl_dev *pctl;
32 void __iomem *base;
33 struct mxs_pinctrl_soc_data *soc;
34};
35
36static int mxs_get_groups_count(struct pinctrl_dev *pctldev)
37{
38 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
39
40 return d->soc->ngroups;
41}
42
43static const char *mxs_get_group_name(struct pinctrl_dev *pctldev,
44 unsigned group)
45{
46 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
47
48 return d->soc->groups[group].name;
49}
50
51static int mxs_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
52 const unsigned **pins, unsigned *num_pins)
53{
54 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
55
56 *pins = d->soc->groups[group].pins;
57 *num_pins = d->soc->groups[group].npins;
58
59 return 0;
60}
61
62static void mxs_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
63 unsigned offset)
64{
65 seq_printf(s, " %s", dev_name(pctldev->dev));
66}
67
68static int mxs_dt_node_to_map(struct pinctrl_dev *pctldev,
69 struct device_node *np,
70 struct pinctrl_map **map, unsigned *num_maps)
71{
72 struct pinctrl_map *new_map;
73 char *group = NULL;
74 unsigned new_num = 1;
75 unsigned long config = 0;
76 unsigned long *pconfig;
77 int length = strlen(np->name) + SUFFIX_LEN;
78 bool purecfg = false;
79 u32 val, reg;
80 int ret, i = 0;
81
82 /* Check for pin config node which has no 'reg' property */
83 if (of_property_read_u32(np, "reg", &reg))
84 purecfg = true;
85
86 ret = of_property_read_u32(np, "fsl,drive-strength", &val);
87 if (!ret)
88 config = val | MA_PRESENT;
89 ret = of_property_read_u32(np, "fsl,voltage", &val);
90 if (!ret)
91 config |= val << VOL_SHIFT | VOL_PRESENT;
92 ret = of_property_read_u32(np, "fsl,pull-up", &val);
93 if (!ret)
94 config |= val << PULL_SHIFT | PULL_PRESENT;
95
96 /* Check for group node which has both mux and config settings */
97 if (!purecfg && config)
98 new_num = 2;
99
100 new_map = kzalloc(sizeof(*new_map) * new_num, GFP_KERNEL);
101 if (!new_map)
102 return -ENOMEM;
103
104 if (!purecfg) {
105 new_map[i].type = PIN_MAP_TYPE_MUX_GROUP;
106 new_map[i].data.mux.function = np->name;
107
108 /* Compose group name */
109 group = kzalloc(length, GFP_KERNEL);
110 if (!group)
111 return -ENOMEM;
112 snprintf(group, length, "%s.%d", np->name, reg);
113 new_map[i].data.mux.group = group;
114 i++;
115 }
116
117 if (config) {
118 pconfig = kmemdup(&config, sizeof(config), GFP_KERNEL);
119 if (!pconfig) {
120 ret = -ENOMEM;
121 goto free;
122 }
123
124 new_map[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
125 new_map[i].data.configs.group_or_pin = purecfg ? np->name :
126 group;
127 new_map[i].data.configs.configs = pconfig;
128 new_map[i].data.configs.num_configs = 1;
129 }
130
131 *map = new_map;
132 *num_maps = new_num;
133
134 return 0;
135
136free:
137 kfree(new_map);
138 return ret;
139}
140
141static void mxs_dt_free_map(struct pinctrl_dev *pctldev,
142 struct pinctrl_map *map, unsigned num_maps)
143{
144 int i;
145
146 for (i = 0; i < num_maps; i++) {
147 if (map[i].type == PIN_MAP_TYPE_MUX_GROUP)
148 kfree(map[i].data.mux.group);
149 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
150 kfree(map[i].data.configs.configs);
151 }
152
153 kfree(map);
154}
155
156static struct pinctrl_ops mxs_pinctrl_ops = {
157 .get_groups_count = mxs_get_groups_count,
158 .get_group_name = mxs_get_group_name,
159 .get_group_pins = mxs_get_group_pins,
160 .pin_dbg_show = mxs_pin_dbg_show,
161 .dt_node_to_map = mxs_dt_node_to_map,
162 .dt_free_map = mxs_dt_free_map,
163};
164
165static int mxs_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
166{
167 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
168
169 return d->soc->nfunctions;
170}
171
172static const char *mxs_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
173 unsigned function)
174{
175 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
176
177 return d->soc->functions[function].name;
178}
179
180static int mxs_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
181 unsigned group,
182 const char * const **groups,
183 unsigned * const num_groups)
184{
185 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
186
187 *groups = d->soc->functions[group].groups;
188 *num_groups = d->soc->functions[group].ngroups;
189
190 return 0;
191}
192
193static int mxs_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned selector,
194 unsigned group)
195{
196 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
197 struct mxs_group *g = &d->soc->groups[group];
198 void __iomem *reg;
199 u8 bank, shift;
200 u16 pin;
201 int i;
202
203 for (i = 0; i < g->npins; i++) {
204 bank = PINID_TO_BANK(g->pins[i]);
205 pin = PINID_TO_PIN(g->pins[i]);
206 reg = d->base + d->soc->regs->muxsel;
207 reg += bank * 0x20 + pin / 16 * 0x10;
208 shift = pin % 16 * 2;
209
210 writel(0x3 << shift, reg + CLR);
211 writel(g->muxsel[i] << shift, reg + SET);
212 }
213
214 return 0;
215}
216
217static struct pinmux_ops mxs_pinmux_ops = {
218 .get_functions_count = mxs_pinctrl_get_funcs_count,
219 .get_function_name = mxs_pinctrl_get_func_name,
220 .get_function_groups = mxs_pinctrl_get_func_groups,
221 .enable = mxs_pinctrl_enable,
222};
223
224static int mxs_pinconf_get(struct pinctrl_dev *pctldev,
225 unsigned pin, unsigned long *config)
226{
227 return -ENOTSUPP;
228}
229
230static int mxs_pinconf_set(struct pinctrl_dev *pctldev,
231 unsigned pin, unsigned long config)
232{
233 return -ENOTSUPP;
234}
235
236static int mxs_pinconf_group_get(struct pinctrl_dev *pctldev,
237 unsigned group, unsigned long *config)
238{
239 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
240
241 *config = d->soc->groups[group].config;
242
243 return 0;
244}
245
246static int mxs_pinconf_group_set(struct pinctrl_dev *pctldev,
247 unsigned group, unsigned long config)
248{
249 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
250 struct mxs_group *g = &d->soc->groups[group];
251 void __iomem *reg;
252 u8 ma, vol, pull, bank, shift;
253 u16 pin;
254 int i;
255
256 ma = CONFIG_TO_MA(config);
257 vol = CONFIG_TO_VOL(config);
258 pull = CONFIG_TO_PULL(config);
259
260 for (i = 0; i < g->npins; i++) {
261 bank = PINID_TO_BANK(g->pins[i]);
262 pin = PINID_TO_PIN(g->pins[i]);
263
264 /* drive */
265 reg = d->base + d->soc->regs->drive;
266 reg += bank * 0x40 + pin / 8 * 0x10;
267
268 /* mA */
269 if (config & MA_PRESENT) {
270 shift = pin % 8 * 4;
271 writel(0x3 << shift, reg + CLR);
272 writel(ma << shift, reg + SET);
273 }
274
275 /* vol */
276 if (config & VOL_PRESENT) {
277 shift = pin % 8 * 4 + 2;
278 if (vol)
279 writel(1 << shift, reg + SET);
280 else
281 writel(1 << shift, reg + CLR);
282 }
283
284 /* pull */
285 if (config & PULL_PRESENT) {
286 reg = d->base + d->soc->regs->pull;
287 reg += bank * 0x10;
288 shift = pin;
289 if (pull)
290 writel(1 << shift, reg + SET);
291 else
292 writel(1 << shift, reg + CLR);
293 }
294 }
295
296 /* cache the config value for mxs_pinconf_group_get() */
297 g->config = config;
298
299 return 0;
300}
301
302static void mxs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
303 struct seq_file *s, unsigned pin)
304{
305 /* Not support */
306}
307
308static void mxs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
309 struct seq_file *s, unsigned group)
310{
311 unsigned long config;
312
313 if (!mxs_pinconf_group_get(pctldev, group, &config))
314 seq_printf(s, "0x%lx", config);
315}
316
317struct pinconf_ops mxs_pinconf_ops = {
318 .pin_config_get = mxs_pinconf_get,
319 .pin_config_set = mxs_pinconf_set,
320 .pin_config_group_get = mxs_pinconf_group_get,
321 .pin_config_group_set = mxs_pinconf_group_set,
322 .pin_config_dbg_show = mxs_pinconf_dbg_show,
323 .pin_config_group_dbg_show = mxs_pinconf_group_dbg_show,
324};
325
326static struct pinctrl_desc mxs_pinctrl_desc = {
327 .pctlops = &mxs_pinctrl_ops,
328 .pmxops = &mxs_pinmux_ops,
329 .confops = &mxs_pinconf_ops,
330 .owner = THIS_MODULE,
331};
332
333static int __devinit mxs_pinctrl_parse_group(struct platform_device *pdev,
334 struct device_node *np, int idx,
335 const char **out_name)
336{
337 struct mxs_pinctrl_data *d = platform_get_drvdata(pdev);
338 struct mxs_group *g = &d->soc->groups[idx];
339 struct property *prop;
340 const char *propname = "fsl,pinmux-ids";
341 char *group;
342 int length = strlen(np->name) + SUFFIX_LEN;
343 int i;
344 u32 val;
345
346 group = devm_kzalloc(&pdev->dev, length, GFP_KERNEL);
347 if (!group)
348 return -ENOMEM;
349 if (of_property_read_u32(np, "reg", &val))
350 snprintf(group, length, "%s", np->name);
351 else
352 snprintf(group, length, "%s.%d", np->name, val);
353 g->name = group;
354
355 prop = of_find_property(np, propname, &length);
356 if (!prop)
357 return -EINVAL;
358 g->npins = length / sizeof(u32);
359
360 g->pins = devm_kzalloc(&pdev->dev, g->npins * sizeof(*g->pins),
361 GFP_KERNEL);
362 if (!g->pins)
363 return -ENOMEM;
364
365 g->muxsel = devm_kzalloc(&pdev->dev, g->npins * sizeof(*g->muxsel),
366 GFP_KERNEL);
367 if (!g->muxsel)
368 return -ENOMEM;
369
370 of_property_read_u32_array(np, propname, g->pins, g->npins);
371 for (i = 0; i < g->npins; i++) {
372 g->muxsel[i] = MUXID_TO_MUXSEL(g->pins[i]);
373 g->pins[i] = MUXID_TO_PINID(g->pins[i]);
374 }
375
376 if (out_name)
377 *out_name = g->name;
378
379 return 0;
380}
381
382static int __devinit mxs_pinctrl_probe_dt(struct platform_device *pdev,
383 struct mxs_pinctrl_data *d)
384{
385 struct mxs_pinctrl_soc_data *soc = d->soc;
386 struct device_node *np = pdev->dev.of_node;
387 struct device_node *child;
388 struct mxs_function *f;
389 const char *gpio_compat = "fsl,mxs-gpio";
390 const char *fn, *fnull = "";
391 int i = 0, idxf = 0, idxg = 0;
392 int ret;
393 u32 val;
394
395 child = of_get_next_child(np, NULL);
396 if (!child) {
397 dev_err(&pdev->dev, "no group is defined\n");
398 return -ENOENT;
399 }
400
401 /* Count total functions and groups */
402 fn = fnull;
403 for_each_child_of_node(np, child) {
404 if (of_device_is_compatible(child, gpio_compat))
405 continue;
406 soc->ngroups++;
407 /* Skip pure pinconf node */
408 if (of_property_read_u32(child, "reg", &val))
409 continue;
410 if (strcmp(fn, child->name)) {
411 fn = child->name;
412 soc->nfunctions++;
413 }
414 }
415
416 soc->functions = devm_kzalloc(&pdev->dev, soc->nfunctions *
417 sizeof(*soc->functions), GFP_KERNEL);
418 if (!soc->functions)
419 return -ENOMEM;
420
421 soc->groups = devm_kzalloc(&pdev->dev, soc->ngroups *
422 sizeof(*soc->groups), GFP_KERNEL);
423 if (!soc->groups)
424 return -ENOMEM;
425
426 /* Count groups for each function */
427 fn = fnull;
428 f = &soc->functions[idxf];
429 for_each_child_of_node(np, child) {
430 if (of_device_is_compatible(child, gpio_compat))
431 continue;
432 if (of_property_read_u32(child, "reg", &val))
433 continue;
434 if (strcmp(fn, child->name)) {
435 f = &soc->functions[idxf++];
436 f->name = fn = child->name;
437 }
438 f->ngroups++;
439 };
440
441 /* Get groups for each function */
442 idxf = 0;
443 fn = fnull;
444 for_each_child_of_node(np, child) {
445 if (of_device_is_compatible(child, gpio_compat))
446 continue;
447 if (of_property_read_u32(child, "reg", &val)) {
448 ret = mxs_pinctrl_parse_group(pdev, child,
449 idxg++, NULL);
450 if (ret)
451 return ret;
452 continue;
453 }
454
455 if (strcmp(fn, child->name)) {
456 f = &soc->functions[idxf++];
457 f->groups = devm_kzalloc(&pdev->dev, f->ngroups *
458 sizeof(*f->groups),
459 GFP_KERNEL);
460 if (!f->groups)
461 return -ENOMEM;
462 fn = child->name;
463 i = 0;
464 }
465 ret = mxs_pinctrl_parse_group(pdev, child, idxg++,
466 &f->groups[i++]);
467 if (ret)
468 return ret;
469 }
470
471 return 0;
472}
473
474int __devinit mxs_pinctrl_probe(struct platform_device *pdev,
475 struct mxs_pinctrl_soc_data *soc)
476{
477 struct device_node *np = pdev->dev.of_node;
478 struct mxs_pinctrl_data *d;
479 int ret;
480
481 d = devm_kzalloc(&pdev->dev, sizeof(*d), GFP_KERNEL);
482 if (!d)
483 return -ENOMEM;
484
485 d->dev = &pdev->dev;
486 d->soc = soc;
487
488 d->base = of_iomap(np, 0);
489 if (!d->base)
490 return -EADDRNOTAVAIL;
491
492 mxs_pinctrl_desc.pins = d->soc->pins;
493 mxs_pinctrl_desc.npins = d->soc->npins;
494 mxs_pinctrl_desc.name = dev_name(&pdev->dev);
495
496 platform_set_drvdata(pdev, d);
497
498 ret = mxs_pinctrl_probe_dt(pdev, d);
499 if (ret) {
500 dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
501 goto err;
502 }
503
504 d->pctl = pinctrl_register(&mxs_pinctrl_desc, &pdev->dev, d);
505 if (!d->pctl) {
506 dev_err(&pdev->dev, "Couldn't register MXS pinctrl driver\n");
507 ret = -EINVAL;
508 goto err;
509 }
510
511 return 0;
512
513err:
514 iounmap(d->base);
515 return ret;
516}
517EXPORT_SYMBOL_GPL(mxs_pinctrl_probe);
518
519int __devexit mxs_pinctrl_remove(struct platform_device *pdev)
520{
521 struct mxs_pinctrl_data *d = platform_get_drvdata(pdev);
522
523 pinctrl_unregister(d->pctl);
524 iounmap(d->base);
525
526 return 0;
527}
528EXPORT_SYMBOL_GPL(mxs_pinctrl_remove);
diff --git a/drivers/pinctrl/pinctrl-mxs.h b/drivers/pinctrl/pinctrl-mxs.h
new file mode 100644
index 00000000000..fdd88d0bae2
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-mxs.h
@@ -0,0 +1,91 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#ifndef __PINCTRL_MXS_H
13#define __PINCTRL_MXS_H
14
15#include <linux/platform_device.h>
16#include <linux/pinctrl/pinctrl.h>
17
18#define SET 0x4
19#define CLR 0x8
20#define TOG 0xc
21
22#define MXS_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
23#define PINID(bank, pin) ((bank) * 32 + (pin))
24
25/*
26 * pinmux-id bit field definitions
27 *
28 * bank: 15..12 (4)
29 * pin: 11..4 (8)
30 * muxsel: 3..0 (4)
31 */
32#define MUXID_TO_PINID(m) PINID((m) >> 12 & 0xf, (m) >> 4 & 0xff)
33#define MUXID_TO_MUXSEL(m) ((m) & 0xf)
34
35#define PINID_TO_BANK(p) ((p) >> 5)
36#define PINID_TO_PIN(p) ((p) % 32)
37
38/*
39 * pin config bit field definitions
40 *
41 * pull-up: 6..5 (2)
42 * voltage: 4..3 (2)
43 * mA: 2..0 (3)
44 *
45 * MSB of each field is presence bit for the config.
46 */
47#define PULL_PRESENT (1 << 6)
48#define PULL_SHIFT 5
49#define VOL_PRESENT (1 << 4)
50#define VOL_SHIFT 3
51#define MA_PRESENT (1 << 2)
52#define MA_SHIFT 0
53#define CONFIG_TO_PULL(c) ((c) >> PULL_SHIFT & 0x1)
54#define CONFIG_TO_VOL(c) ((c) >> VOL_SHIFT & 0x1)
55#define CONFIG_TO_MA(c) ((c) >> MA_SHIFT & 0x3)
56
57struct mxs_function {
58 const char *name;
59 const char **groups;
60 unsigned ngroups;
61};
62
63struct mxs_group {
64 const char *name;
65 unsigned int *pins;
66 unsigned npins;
67 u8 *muxsel;
68 u8 config;
69};
70
71struct mxs_regs {
72 u16 muxsel;
73 u16 drive;
74 u16 pull;
75};
76
77struct mxs_pinctrl_soc_data {
78 const struct mxs_regs *regs;
79 const struct pinctrl_pin_desc *pins;
80 unsigned npins;
81 struct mxs_function *functions;
82 unsigned nfunctions;
83 struct mxs_group *groups;
84 unsigned ngroups;
85};
86
87int mxs_pinctrl_probe(struct platform_device *pdev,
88 struct mxs_pinctrl_soc_data *soc);
89int mxs_pinctrl_remove(struct platform_device *pdev);
90
91#endif /* __PINCTRL_MXS_H */
diff --git a/drivers/pinctrl/pinctrl-pxa3xx.c b/drivers/pinctrl/pinctrl-pxa3xx.c
index 079dce0e93e..f14cd6ba4c0 100644
--- a/drivers/pinctrl/pinctrl-pxa3xx.c
+++ b/drivers/pinctrl/pinctrl-pxa3xx.c
@@ -25,20 +25,18 @@ static struct pinctrl_gpio_range pxa3xx_pinctrl_gpio_range = {
25 .pin_base = 0, 25 .pin_base = 0,
26}; 26};
27 27
28static int pxa3xx_list_groups(struct pinctrl_dev *pctrldev, unsigned selector) 28static int pxa3xx_get_groups_count(struct pinctrl_dev *pctrldev)
29{ 29{
30 struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); 30 struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
31 if (selector >= info->num_grps) 31
32 return -EINVAL; 32 return info->num_grps;
33 return 0;
34} 33}
35 34
36static const char *pxa3xx_get_group_name(struct pinctrl_dev *pctrldev, 35static const char *pxa3xx_get_group_name(struct pinctrl_dev *pctrldev,
37 unsigned selector) 36 unsigned selector)
38{ 37{
39 struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); 38 struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
40 if (selector >= info->num_grps) 39
41 return NULL;
42 return info->grps[selector].name; 40 return info->grps[selector].name;
43} 41}
44 42
@@ -48,25 +46,23 @@ static int pxa3xx_get_group_pins(struct pinctrl_dev *pctrldev,
48 unsigned *num_pins) 46 unsigned *num_pins)
49{ 47{
50 struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); 48 struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
51 if (selector >= info->num_grps) 49
52 return -EINVAL;
53 *pins = info->grps[selector].pins; 50 *pins = info->grps[selector].pins;
54 *num_pins = info->grps[selector].npins; 51 *num_pins = info->grps[selector].npins;
55 return 0; 52 return 0;
56} 53}
57 54
58static struct pinctrl_ops pxa3xx_pctrl_ops = { 55static struct pinctrl_ops pxa3xx_pctrl_ops = {
59 .list_groups = pxa3xx_list_groups, 56 .get_groups_count = pxa3xx_get_groups_count,
60 .get_group_name = pxa3xx_get_group_name, 57 .get_group_name = pxa3xx_get_group_name,
61 .get_group_pins = pxa3xx_get_group_pins, 58 .get_group_pins = pxa3xx_get_group_pins,
62}; 59};
63 60
64static int pxa3xx_pmx_list_func(struct pinctrl_dev *pctrldev, unsigned func) 61static int pxa3xx_pmx_get_funcs_count(struct pinctrl_dev *pctrldev)
65{ 62{
66 struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); 63 struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
67 if (func >= info->num_funcs) 64
68 return -EINVAL; 65 return info->num_funcs;
69 return 0;
70} 66}
71 67
72static const char *pxa3xx_pmx_get_func_name(struct pinctrl_dev *pctrldev, 68static const char *pxa3xx_pmx_get_func_name(struct pinctrl_dev *pctrldev,
@@ -142,11 +138,6 @@ static int pxa3xx_pmx_enable(struct pinctrl_dev *pctrldev, unsigned func,
142 return 0; 138 return 0;
143} 139}
144 140
145static void pxa3xx_pmx_disable(struct pinctrl_dev *pctrldev, unsigned func,
146 unsigned group)
147{
148}
149
150static int pxa3xx_pmx_request_gpio(struct pinctrl_dev *pctrldev, 141static int pxa3xx_pmx_request_gpio(struct pinctrl_dev *pctrldev,
151 struct pinctrl_gpio_range *range, 142 struct pinctrl_gpio_range *range,
152 unsigned pin) 143 unsigned pin)
@@ -170,11 +161,10 @@ static int pxa3xx_pmx_request_gpio(struct pinctrl_dev *pctrldev,
170} 161}
171 162
172static struct pinmux_ops pxa3xx_pmx_ops = { 163static struct pinmux_ops pxa3xx_pmx_ops = {
173 .list_functions = pxa3xx_pmx_list_func, 164 .get_functions_count = pxa3xx_pmx_get_funcs_count,
174 .get_function_name = pxa3xx_pmx_get_func_name, 165 .get_function_name = pxa3xx_pmx_get_func_name,
175 .get_function_groups = pxa3xx_pmx_get_groups, 166 .get_function_groups = pxa3xx_pmx_get_groups,
176 .enable = pxa3xx_pmx_enable, 167 .enable = pxa3xx_pmx_enable,
177 .disable = pxa3xx_pmx_disable,
178 .gpio_request_enable = pxa3xx_pmx_request_gpio, 168 .gpio_request_enable = pxa3xx_pmx_request_gpio,
179}; 169};
180 170
diff --git a/drivers/pinctrl/pinctrl-sirf.c b/drivers/pinctrl/pinctrl-sirf.c
index 6b3534cc051..ba15b1a29e5 100644
--- a/drivers/pinctrl/pinctrl-sirf.c
+++ b/drivers/pinctrl/pinctrl-sirf.c
@@ -853,18 +853,14 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
853 SIRFSOC_PIN_GROUP("gpsgrp", gps_pins), 853 SIRFSOC_PIN_GROUP("gpsgrp", gps_pins),
854}; 854};
855 855
856static int sirfsoc_list_groups(struct pinctrl_dev *pctldev, unsigned selector) 856static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev)
857{ 857{
858 if (selector >= ARRAY_SIZE(sirfsoc_pin_groups)) 858 return ARRAY_SIZE(sirfsoc_pin_groups);
859 return -EINVAL;
860 return 0;
861} 859}
862 860
863static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev, 861static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev,
864 unsigned selector) 862 unsigned selector)
865{ 863{
866 if (selector >= ARRAY_SIZE(sirfsoc_pin_groups))
867 return NULL;
868 return sirfsoc_pin_groups[selector].name; 864 return sirfsoc_pin_groups[selector].name;
869} 865}
870 866
@@ -872,8 +868,6 @@ static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector
872 const unsigned **pins, 868 const unsigned **pins,
873 unsigned *num_pins) 869 unsigned *num_pins)
874{ 870{
875 if (selector >= ARRAY_SIZE(sirfsoc_pin_groups))
876 return -EINVAL;
877 *pins = sirfsoc_pin_groups[selector].pins; 871 *pins = sirfsoc_pin_groups[selector].pins;
878 *num_pins = sirfsoc_pin_groups[selector].num_pins; 872 *num_pins = sirfsoc_pin_groups[selector].num_pins;
879 return 0; 873 return 0;
@@ -886,7 +880,7 @@ static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s
886} 880}
887 881
888static struct pinctrl_ops sirfsoc_pctrl_ops = { 882static struct pinctrl_ops sirfsoc_pctrl_ops = {
889 .list_groups = sirfsoc_list_groups, 883 .get_groups_count = sirfsoc_get_groups_count,
890 .get_group_name = sirfsoc_get_group_name, 884 .get_group_name = sirfsoc_get_group_name,
891 .get_group_pins = sirfsoc_get_group_pins, 885 .get_group_pins = sirfsoc_get_group_pins,
892 .pin_dbg_show = sirfsoc_pin_dbg_show, 886 .pin_dbg_show = sirfsoc_pin_dbg_show,
@@ -1033,11 +1027,9 @@ static void sirfsoc_pinmux_disable(struct pinctrl_dev *pmxdev, unsigned selector
1033 sirfsoc_pinmux_endisable(spmx, selector, false); 1027 sirfsoc_pinmux_endisable(spmx, selector, false);
1034} 1028}
1035 1029
1036static int sirfsoc_pinmux_list_funcs(struct pinctrl_dev *pmxdev, unsigned selector) 1030static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev)
1037{ 1031{
1038 if (selector >= ARRAY_SIZE(sirfsoc_pmx_functions)) 1032 return ARRAY_SIZE(sirfsoc_pmx_functions);
1039 return -EINVAL;
1040 return 0;
1041} 1033}
1042 1034
1043static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev, 1035static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev,
@@ -1074,9 +1066,9 @@ static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
1074} 1066}
1075 1067
1076static struct pinmux_ops sirfsoc_pinmux_ops = { 1068static struct pinmux_ops sirfsoc_pinmux_ops = {
1077 .list_functions = sirfsoc_pinmux_list_funcs,
1078 .enable = sirfsoc_pinmux_enable, 1069 .enable = sirfsoc_pinmux_enable,
1079 .disable = sirfsoc_pinmux_disable, 1070 .disable = sirfsoc_pinmux_disable,
1071 .get_functions_count = sirfsoc_pinmux_get_funcs_count,
1080 .get_function_name = sirfsoc_pinmux_get_func_name, 1072 .get_function_name = sirfsoc_pinmux_get_func_name,
1081 .get_function_groups = sirfsoc_pinmux_get_groups, 1073 .get_function_groups = sirfsoc_pinmux_get_groups,
1082 .gpio_request_enable = sirfsoc_pinmux_request_gpio, 1074 .gpio_request_enable = sirfsoc_pinmux_request_gpio,
diff --git a/drivers/pinctrl/pinctrl-tegra.c b/drivers/pinctrl/pinctrl-tegra.c
index 9b329688120..2c98fba01ca 100644
--- a/drivers/pinctrl/pinctrl-tegra.c
+++ b/drivers/pinctrl/pinctrl-tegra.c
@@ -23,9 +23,11 @@
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/module.h> 24#include <linux/module.h>
25#include <linux/of_device.h> 25#include <linux/of_device.h>
26#include <linux/pinctrl/machine.h>
26#include <linux/pinctrl/pinctrl.h> 27#include <linux/pinctrl/pinctrl.h>
27#include <linux/pinctrl/pinmux.h> 28#include <linux/pinctrl/pinmux.h>
28#include <linux/pinctrl/pinconf.h> 29#include <linux/pinctrl/pinconf.h>
30#include <linux/slab.h>
29 31
30#include <mach/pinconf-tegra.h> 32#include <mach/pinconf-tegra.h>
31 33
@@ -53,15 +55,11 @@ static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)
53 writel(val, pmx->regs[bank] + reg); 55 writel(val, pmx->regs[bank] + reg);
54} 56}
55 57
56static int tegra_pinctrl_list_groups(struct pinctrl_dev *pctldev, 58static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
57 unsigned group)
58{ 59{
59 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 60 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
60 61
61 if (group >= pmx->soc->ngroups) 62 return pmx->soc->ngroups;
62 return -EINVAL;
63
64 return 0;
65} 63}
66 64
67static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev, 65static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
@@ -69,9 +67,6 @@ static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
69{ 67{
70 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 68 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
71 69
72 if (group >= pmx->soc->ngroups)
73 return NULL;
74
75 return pmx->soc->groups[group].name; 70 return pmx->soc->groups[group].name;
76} 71}
77 72
@@ -82,9 +77,6 @@ static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
82{ 77{
83 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 78 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
84 79
85 if (group >= pmx->soc->ngroups)
86 return -EINVAL;
87
88 *pins = pmx->soc->groups[group].pins; 80 *pins = pmx->soc->groups[group].pins;
89 *num_pins = pmx->soc->groups[group].npins; 81 *num_pins = pmx->soc->groups[group].npins;
90 82
@@ -98,22 +90,221 @@ static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
98 seq_printf(s, " " DRIVER_NAME); 90 seq_printf(s, " " DRIVER_NAME);
99} 91}
100 92
93static int reserve_map(struct pinctrl_map **map, unsigned *reserved_maps,
94 unsigned *num_maps, unsigned reserve)
95{
96 unsigned old_num = *reserved_maps;
97 unsigned new_num = *num_maps + reserve;
98 struct pinctrl_map *new_map;
99
100 if (old_num >= new_num)
101 return 0;
102
103 new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
104 if (!new_map)
105 return -ENOMEM;
106
107 memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
108
109 *map = new_map;
110 *reserved_maps = new_num;
111
112 return 0;
113}
114
115static int add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
116 unsigned *num_maps, const char *group,
117 const char *function)
118{
119 if (*num_maps == *reserved_maps)
120 return -ENOSPC;
121
122 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
123 (*map)[*num_maps].data.mux.group = group;
124 (*map)[*num_maps].data.mux.function = function;
125 (*num_maps)++;
126
127 return 0;
128}
129
130static int add_map_configs(struct pinctrl_map **map, unsigned *reserved_maps,
131 unsigned *num_maps, const char *group,
132 unsigned long *configs, unsigned num_configs)
133{
134 unsigned long *dup_configs;
135
136 if (*num_maps == *reserved_maps)
137 return -ENOSPC;
138
139 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
140 GFP_KERNEL);
141 if (!dup_configs)
142 return -ENOMEM;
143
144 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
145 (*map)[*num_maps].data.configs.group_or_pin = group;
146 (*map)[*num_maps].data.configs.configs = dup_configs;
147 (*map)[*num_maps].data.configs.num_configs = num_configs;
148 (*num_maps)++;
149
150 return 0;
151}
152
153static int add_config(unsigned long **configs, unsigned *num_configs,
154 unsigned long config)
155{
156 unsigned old_num = *num_configs;
157 unsigned new_num = old_num + 1;
158 unsigned long *new_configs;
159
160 new_configs = krealloc(*configs, sizeof(*new_configs) * new_num,
161 GFP_KERNEL);
162 if (!new_configs)
163 return -ENOMEM;
164
165 new_configs[old_num] = config;
166
167 *configs = new_configs;
168 *num_configs = new_num;
169
170 return 0;
171}
172
173void tegra_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
174 struct pinctrl_map *map, unsigned num_maps)
175{
176 int i;
177
178 for (i = 0; i < num_maps; i++)
179 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
180 kfree(map[i].data.configs.configs);
181
182 kfree(map);
183}
184
185static const struct cfg_param {
186 const char *property;
187 enum tegra_pinconf_param param;
188} cfg_params[] = {
189 {"nvidia,pull", TEGRA_PINCONF_PARAM_PULL},
190 {"nvidia,tristate", TEGRA_PINCONF_PARAM_TRISTATE},
191 {"nvidia,enable-input", TEGRA_PINCONF_PARAM_ENABLE_INPUT},
192 {"nvidia,open-drain", TEGRA_PINCONF_PARAM_OPEN_DRAIN},
193 {"nvidia,lock", TEGRA_PINCONF_PARAM_LOCK},
194 {"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET},
195 {"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
196 {"nvidia,schmitt", TEGRA_PINCONF_PARAM_SCHMITT},
197 {"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
198 {"nvidia,pull-down-strength", TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
199 {"nvidia,pull-up-strength", TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
200 {"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
201 {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
202};
203
204int tegra_pinctrl_dt_subnode_to_map(struct device_node *np,
205 struct pinctrl_map **map,
206 unsigned *reserved_maps,
207 unsigned *num_maps)
208{
209 int ret, i;
210 const char *function;
211 u32 val;
212 unsigned long config;
213 unsigned long *configs = NULL;
214 unsigned num_configs = 0;
215 unsigned reserve;
216 struct property *prop;
217 const char *group;
218
219 ret = of_property_read_string(np, "nvidia,function", &function);
220 if (ret < 0)
221 function = NULL;
222
223 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
224 ret = of_property_read_u32(np, cfg_params[i].property, &val);
225 if (!ret) {
226 config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
227 ret = add_config(&configs, &num_configs, config);
228 if (ret < 0)
229 goto exit;
230 }
231 }
232
233 reserve = 0;
234 if (function != NULL)
235 reserve++;
236 if (num_configs)
237 reserve++;
238 ret = of_property_count_strings(np, "nvidia,pins");
239 if (ret < 0)
240 goto exit;
241 reserve *= ret;
242
243 ret = reserve_map(map, reserved_maps, num_maps, reserve);
244 if (ret < 0)
245 goto exit;
246
247 of_property_for_each_string(np, "nvidia,pins", prop, group) {
248 if (function) {
249 ret = add_map_mux(map, reserved_maps, num_maps,
250 group, function);
251 if (ret < 0)
252 goto exit;
253 }
254
255 if (num_configs) {
256 ret = add_map_configs(map, reserved_maps, num_maps,
257 group, configs, num_configs);
258 if (ret < 0)
259 goto exit;
260 }
261 }
262
263 ret = 0;
264
265exit:
266 kfree(configs);
267 return ret;
268}
269
270int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
271 struct device_node *np_config,
272 struct pinctrl_map **map, unsigned *num_maps)
273{
274 unsigned reserved_maps;
275 struct device_node *np;
276 int ret;
277
278 reserved_maps = 0;
279 *map = NULL;
280 *num_maps = 0;
281
282 for_each_child_of_node(np_config, np) {
283 ret = tegra_pinctrl_dt_subnode_to_map(np, map, &reserved_maps,
284 num_maps);
285 if (ret < 0) {
286 tegra_pinctrl_dt_free_map(pctldev, *map, *num_maps);
287 return ret;
288 }
289 }
290
291 return 0;
292}
293
101static struct pinctrl_ops tegra_pinctrl_ops = { 294static struct pinctrl_ops tegra_pinctrl_ops = {
102 .list_groups = tegra_pinctrl_list_groups, 295 .get_groups_count = tegra_pinctrl_get_groups_count,
103 .get_group_name = tegra_pinctrl_get_group_name, 296 .get_group_name = tegra_pinctrl_get_group_name,
104 .get_group_pins = tegra_pinctrl_get_group_pins, 297 .get_group_pins = tegra_pinctrl_get_group_pins,
105 .pin_dbg_show = tegra_pinctrl_pin_dbg_show, 298 .pin_dbg_show = tegra_pinctrl_pin_dbg_show,
299 .dt_node_to_map = tegra_pinctrl_dt_node_to_map,
300 .dt_free_map = tegra_pinctrl_dt_free_map,
106}; 301};
107 302
108static int tegra_pinctrl_list_funcs(struct pinctrl_dev *pctldev, 303static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
109 unsigned function)
110{ 304{
111 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 305 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
112 306
113 if (function >= pmx->soc->nfunctions) 307 return pmx->soc->nfunctions;
114 return -EINVAL;
115
116 return 0;
117} 308}
118 309
119static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev, 310static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
@@ -121,9 +312,6 @@ static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
121{ 312{
122 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 313 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
123 314
124 if (function >= pmx->soc->nfunctions)
125 return NULL;
126
127 return pmx->soc->functions[function].name; 315 return pmx->soc->functions[function].name;
128} 316}
129 317
@@ -134,9 +322,6 @@ static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
134{ 322{
135 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 323 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
136 324
137 if (function >= pmx->soc->nfunctions)
138 return -EINVAL;
139
140 *groups = pmx->soc->functions[function].groups; 325 *groups = pmx->soc->functions[function].groups;
141 *num_groups = pmx->soc->functions[function].ngroups; 326 *num_groups = pmx->soc->functions[function].ngroups;
142 327
@@ -151,8 +336,6 @@ static int tegra_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
151 int i; 336 int i;
152 u32 val; 337 u32 val;
153 338
154 if (group >= pmx->soc->ngroups)
155 return -EINVAL;
156 g = &pmx->soc->groups[group]; 339 g = &pmx->soc->groups[group];
157 340
158 if (g->mux_reg < 0) 341 if (g->mux_reg < 0)
@@ -180,8 +363,6 @@ static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev,
180 const struct tegra_pingroup *g; 363 const struct tegra_pingroup *g;
181 u32 val; 364 u32 val;
182 365
183 if (group >= pmx->soc->ngroups)
184 return;
185 g = &pmx->soc->groups[group]; 366 g = &pmx->soc->groups[group];
186 367
187 if (g->mux_reg < 0) 368 if (g->mux_reg < 0)
@@ -194,7 +375,7 @@ static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev,
194} 375}
195 376
196static struct pinmux_ops tegra_pinmux_ops = { 377static struct pinmux_ops tegra_pinmux_ops = {
197 .list_functions = tegra_pinctrl_list_funcs, 378 .get_functions_count = tegra_pinctrl_get_funcs_count,
198 .get_function_name = tegra_pinctrl_get_func_name, 379 .get_function_name = tegra_pinctrl_get_func_name,
199 .get_function_groups = tegra_pinctrl_get_func_groups, 380 .get_function_groups = tegra_pinctrl_get_func_groups,
200 .enable = tegra_pinctrl_enable, 381 .enable = tegra_pinctrl_enable,
@@ -324,8 +505,6 @@ static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
324 s16 reg; 505 s16 reg;
325 u32 val, mask; 506 u32 val, mask;
326 507
327 if (group >= pmx->soc->ngroups)
328 return -EINVAL;
329 g = &pmx->soc->groups[group]; 508 g = &pmx->soc->groups[group];
330 509
331 ret = tegra_pinconf_reg(pmx, g, param, &bank, &reg, &bit, &width); 510 ret = tegra_pinconf_reg(pmx, g, param, &bank, &reg, &bit, &width);
@@ -353,8 +532,6 @@ static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
353 s16 reg; 532 s16 reg;
354 u32 val, mask; 533 u32 val, mask;
355 534
356 if (group >= pmx->soc->ngroups)
357 return -EINVAL;
358 g = &pmx->soc->groups[group]; 535 g = &pmx->soc->groups[group];
359 536
360 ret = tegra_pinconf_reg(pmx, g, param, &bank, &reg, &bit, &width); 537 ret = tegra_pinconf_reg(pmx, g, param, &bank, &reg, &bit, &width);
diff --git a/drivers/pinctrl/pinctrl-u300.c b/drivers/pinctrl/pinctrl-u300.c
index 26eb8ccd72d..05d029911be 100644
--- a/drivers/pinctrl/pinctrl-u300.c
+++ b/drivers/pinctrl/pinctrl-u300.c
@@ -836,18 +836,14 @@ static const struct u300_pin_group u300_pin_groups[] = {
836 }, 836 },
837}; 837};
838 838
839static int u300_list_groups(struct pinctrl_dev *pctldev, unsigned selector) 839static int u300_get_groups_count(struct pinctrl_dev *pctldev)
840{ 840{
841 if (selector >= ARRAY_SIZE(u300_pin_groups)) 841 return ARRAY_SIZE(u300_pin_groups);
842 return -EINVAL;
843 return 0;
844} 842}
845 843
846static const char *u300_get_group_name(struct pinctrl_dev *pctldev, 844static const char *u300_get_group_name(struct pinctrl_dev *pctldev,
847 unsigned selector) 845 unsigned selector)
848{ 846{
849 if (selector >= ARRAY_SIZE(u300_pin_groups))
850 return NULL;
851 return u300_pin_groups[selector].name; 847 return u300_pin_groups[selector].name;
852} 848}
853 849
@@ -855,8 +851,6 @@ static int u300_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
855 const unsigned **pins, 851 const unsigned **pins,
856 unsigned *num_pins) 852 unsigned *num_pins)
857{ 853{
858 if (selector >= ARRAY_SIZE(u300_pin_groups))
859 return -EINVAL;
860 *pins = u300_pin_groups[selector].pins; 854 *pins = u300_pin_groups[selector].pins;
861 *num_pins = u300_pin_groups[selector].num_pins; 855 *num_pins = u300_pin_groups[selector].num_pins;
862 return 0; 856 return 0;
@@ -869,7 +863,7 @@ static void u300_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
869} 863}
870 864
871static struct pinctrl_ops u300_pctrl_ops = { 865static struct pinctrl_ops u300_pctrl_ops = {
872 .list_groups = u300_list_groups, 866 .get_groups_count = u300_get_groups_count,
873 .get_group_name = u300_get_group_name, 867 .get_group_name = u300_get_group_name,
874 .get_group_pins = u300_get_group_pins, 868 .get_group_pins = u300_get_group_pins,
875 .pin_dbg_show = u300_pin_dbg_show, 869 .pin_dbg_show = u300_pin_dbg_show,
@@ -991,11 +985,9 @@ static void u300_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector,
991 u300_pmx_endisable(upmx, selector, false); 985 u300_pmx_endisable(upmx, selector, false);
992} 986}
993 987
994static int u300_pmx_list_funcs(struct pinctrl_dev *pctldev, unsigned selector) 988static int u300_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
995{ 989{
996 if (selector >= ARRAY_SIZE(u300_pmx_functions)) 990 return ARRAY_SIZE(u300_pmx_functions);
997 return -EINVAL;
998 return 0;
999} 991}
1000 992
1001static const char *u300_pmx_get_func_name(struct pinctrl_dev *pctldev, 993static const char *u300_pmx_get_func_name(struct pinctrl_dev *pctldev,
@@ -1014,7 +1006,7 @@ static int u300_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
1014} 1006}
1015 1007
1016static struct pinmux_ops u300_pmx_ops = { 1008static struct pinmux_ops u300_pmx_ops = {
1017 .list_functions = u300_pmx_list_funcs, 1009 .get_functions_count = u300_pmx_get_funcs_count,
1018 .get_function_name = u300_pmx_get_func_name, 1010 .get_function_name = u300_pmx_get_func_name,
1019 .get_function_groups = u300_pmx_get_groups, 1011 .get_function_groups = u300_pmx_get_groups,
1020 .enable = u300_pmx_enable, 1012 .enable = u300_pmx_enable,
diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c
index 4e62783a573..3d5ac73bd5a 100644
--- a/drivers/pinctrl/pinmux.c
+++ b/drivers/pinctrl/pinmux.c
@@ -33,22 +33,25 @@
33int pinmux_check_ops(struct pinctrl_dev *pctldev) 33int pinmux_check_ops(struct pinctrl_dev *pctldev)
34{ 34{
35 const struct pinmux_ops *ops = pctldev->desc->pmxops; 35 const struct pinmux_ops *ops = pctldev->desc->pmxops;
36 unsigned nfuncs;
36 unsigned selector = 0; 37 unsigned selector = 0;
37 38
38 /* Check that we implement required operations */ 39 /* Check that we implement required operations */
39 if (!ops->list_functions || 40 if (!ops ||
41 !ops->get_functions_count ||
40 !ops->get_function_name || 42 !ops->get_function_name ||
41 !ops->get_function_groups || 43 !ops->get_function_groups ||
42 !ops->enable || 44 !ops->enable) {
43 !ops->disable) 45 dev_err(pctldev->dev, "pinmux ops lacks necessary functions\n");
44 return -EINVAL; 46 return -EINVAL;
45 47 }
46 /* Check that all functions registered have names */ 48 /* Check that all functions registered have names */
47 while (ops->list_functions(pctldev, selector) >= 0) { 49 nfuncs = ops->get_functions_count(pctldev);
50 while (selector < nfuncs) {
48 const char *fname = ops->get_function_name(pctldev, 51 const char *fname = ops->get_function_name(pctldev,
49 selector); 52 selector);
50 if (!fname) { 53 if (!fname) {
51 pr_err("pinmux ops has no name for function%u\n", 54 dev_err(pctldev->dev, "pinmux ops has no name for function%u\n",
52 selector); 55 selector);
53 return -EINVAL; 56 return -EINVAL;
54 } 57 }
@@ -85,20 +88,23 @@ static int pin_request(struct pinctrl_dev *pctldev,
85 const struct pinmux_ops *ops = pctldev->desc->pmxops; 88 const struct pinmux_ops *ops = pctldev->desc->pmxops;
86 int status = -EINVAL; 89 int status = -EINVAL;
87 90
88 dev_dbg(pctldev->dev, "request pin %d for %s\n", pin, owner);
89
90 desc = pin_desc_get(pctldev, pin); 91 desc = pin_desc_get(pctldev, pin);
91 if (desc == NULL) { 92 if (desc == NULL) {
92 dev_err(pctldev->dev, 93 dev_err(pctldev->dev,
93 "pin is not registered so it cannot be requested\n"); 94 "pin %d is not registered so it cannot be requested\n",
95 pin);
94 goto out; 96 goto out;
95 } 97 }
96 98
99 dev_dbg(pctldev->dev, "request pin %d (%s) for %s\n",
100 pin, desc->name, owner);
101
97 if (gpio_range) { 102 if (gpio_range) {
98 /* There's no need to support multiple GPIO requests */ 103 /* There's no need to support multiple GPIO requests */
99 if (desc->gpio_owner) { 104 if (desc->gpio_owner) {
100 dev_err(pctldev->dev, 105 dev_err(pctldev->dev,
101 "pin already requested\n"); 106 "pin %s already requested by %s; cannot claim for %s\n",
107 desc->name, desc->gpio_owner, owner);
102 goto out; 108 goto out;
103 } 109 }
104 110
@@ -106,7 +112,8 @@ static int pin_request(struct pinctrl_dev *pctldev,
106 } else { 112 } else {
107 if (desc->mux_usecount && strcmp(desc->mux_owner, owner)) { 113 if (desc->mux_usecount && strcmp(desc->mux_owner, owner)) {
108 dev_err(pctldev->dev, 114 dev_err(pctldev->dev,
109 "pin already requested\n"); 115 "pin %s already requested by %s; cannot claim for %s\n",
116 desc->name, desc->mux_owner, owner);
110 goto out; 117 goto out;
111 } 118 }
112 119
@@ -139,8 +146,7 @@ static int pin_request(struct pinctrl_dev *pctldev,
139 status = 0; 146 status = 0;
140 147
141 if (status) { 148 if (status) {
142 dev_err(pctldev->dev, "->request on device %s failed for pin %d\n", 149 dev_err(pctldev->dev, "request() failed for pin %d\n", pin);
143 pctldev->desc->name, pin);
144 module_put(pctldev->owner); 150 module_put(pctldev->owner);
145 } 151 }
146 152
@@ -157,7 +163,7 @@ out_free_pin:
157out: 163out:
158 if (status) 164 if (status)
159 dev_err(pctldev->dev, "pin-%d (%s) status %d\n", 165 dev_err(pctldev->dev, "pin-%d (%s) status %d\n",
160 pin, owner, status); 166 pin, owner, status);
161 167
162 return status; 168 return status;
163} 169}
@@ -287,10 +293,11 @@ static int pinmux_func_name_to_selector(struct pinctrl_dev *pctldev,
287 const char *function) 293 const char *function)
288{ 294{
289 const struct pinmux_ops *ops = pctldev->desc->pmxops; 295 const struct pinmux_ops *ops = pctldev->desc->pmxops;
296 unsigned nfuncs = ops->get_functions_count(pctldev);
290 unsigned selector = 0; 297 unsigned selector = 0;
291 298
292 /* See if this pctldev has this function */ 299 /* See if this pctldev has this function */
293 while (ops->list_functions(pctldev, selector) >= 0) { 300 while (selector < nfuncs) {
294 const char *fname = ops->get_function_name(pctldev, 301 const char *fname = ops->get_function_name(pctldev,
295 selector); 302 selector);
296 303
@@ -319,18 +326,32 @@ int pinmux_map_to_setting(struct pinctrl_map const *map,
319 const unsigned *pins; 326 const unsigned *pins;
320 unsigned num_pins; 327 unsigned num_pins;
321 328
322 setting->data.mux.func = 329 if (!pmxops) {
323 pinmux_func_name_to_selector(pctldev, map->data.mux.function); 330 dev_err(pctldev->dev, "does not support mux function\n");
324 if (setting->data.mux.func < 0) 331 return -EINVAL;
325 return setting->data.mux.func; 332 }
333
334 ret = pinmux_func_name_to_selector(pctldev, map->data.mux.function);
335 if (ret < 0) {
336 dev_err(pctldev->dev, "invalid function %s in map table\n",
337 map->data.mux.function);
338 return ret;
339 }
340 setting->data.mux.func = ret;
326 341
327 ret = pmxops->get_function_groups(pctldev, setting->data.mux.func, 342 ret = pmxops->get_function_groups(pctldev, setting->data.mux.func,
328 &groups, &num_groups); 343 &groups, &num_groups);
329 if (ret < 0) 344 if (ret < 0) {
345 dev_err(pctldev->dev, "can't query groups for function %s\n",
346 map->data.mux.function);
330 return ret; 347 return ret;
331 if (!num_groups) 348 }
349 if (!num_groups) {
350 dev_err(pctldev->dev,
351 "function %s can't be selected on any group\n",
352 map->data.mux.function);
332 return -EINVAL; 353 return -EINVAL;
333 354 }
334 if (map->data.mux.group) { 355 if (map->data.mux.group) {
335 bool found = false; 356 bool found = false;
336 group = map->data.mux.group; 357 group = map->data.mux.group;
@@ -340,15 +361,23 @@ int pinmux_map_to_setting(struct pinctrl_map const *map,
340 break; 361 break;
341 } 362 }
342 } 363 }
343 if (!found) 364 if (!found) {
365 dev_err(pctldev->dev,
366 "invalid group \"%s\" for function \"%s\"\n",
367 group, map->data.mux.function);
344 return -EINVAL; 368 return -EINVAL;
369 }
345 } else { 370 } else {
346 group = groups[0]; 371 group = groups[0];
347 } 372 }
348 373
349 setting->data.mux.group = pinctrl_get_group_selector(pctldev, group); 374 ret = pinctrl_get_group_selector(pctldev, group);
350 if (setting->data.mux.group < 0) 375 if (ret < 0) {
351 return setting->data.mux.group; 376 dev_err(pctldev->dev, "invalid group %s in map table\n",
377 map->data.mux.group);
378 return ret;
379 }
380 setting->data.mux.group = ret;
352 381
353 ret = pctlops->get_group_pins(pctldev, setting->data.mux.group, &pins, 382 ret = pctlops->get_group_pins(pctldev, setting->data.mux.group, &pins,
354 &num_pins); 383 &num_pins);
@@ -364,7 +393,7 @@ int pinmux_map_to_setting(struct pinctrl_map const *map,
364 ret = pin_request(pctldev, pins[i], map->dev_name, NULL); 393 ret = pin_request(pctldev, pins[i], map->dev_name, NULL);
365 if (ret) { 394 if (ret) {
366 dev_err(pctldev->dev, 395 dev_err(pctldev->dev,
367 "could not get request pin %d on device %s\n", 396 "could not request pin %d on device %s\n",
368 pins[i], pinctrl_dev_get_name(pctldev)); 397 pins[i], pinctrl_dev_get_name(pctldev));
369 /* On error release all taken pins */ 398 /* On error release all taken pins */
370 i--; /* this pin just failed */ 399 i--; /* this pin just failed */
@@ -467,7 +496,8 @@ void pinmux_disable_setting(struct pinctrl_setting const *setting)
467 desc->mux_setting = NULL; 496 desc->mux_setting = NULL;
468 } 497 }
469 498
470 ops->disable(pctldev, setting->data.mux.func, setting->data.mux.group); 499 if (ops->disable)
500 ops->disable(pctldev, setting->data.mux.func, setting->data.mux.group);
471} 501}
472 502
473#ifdef CONFIG_DEBUG_FS 503#ifdef CONFIG_DEBUG_FS
@@ -477,11 +507,15 @@ static int pinmux_functions_show(struct seq_file *s, void *what)
477{ 507{
478 struct pinctrl_dev *pctldev = s->private; 508 struct pinctrl_dev *pctldev = s->private;
479 const struct pinmux_ops *pmxops = pctldev->desc->pmxops; 509 const struct pinmux_ops *pmxops = pctldev->desc->pmxops;
510 unsigned nfuncs;
480 unsigned func_selector = 0; 511 unsigned func_selector = 0;
481 512
482 mutex_lock(&pinctrl_mutex); 513 if (!pmxops)
514 return 0;
483 515
484 while (pmxops->list_functions(pctldev, func_selector) >= 0) { 516 mutex_lock(&pinctrl_mutex);
517 nfuncs = pmxops->get_functions_count(pctldev);
518 while (func_selector < nfuncs) {
485 const char *func = pmxops->get_function_name(pctldev, 519 const char *func = pmxops->get_function_name(pctldev,
486 func_selector); 520 func_selector);
487 const char * const *groups; 521 const char * const *groups;
@@ -515,6 +549,9 @@ static int pinmux_pins_show(struct seq_file *s, void *what)
515 const struct pinmux_ops *pmxops = pctldev->desc->pmxops; 549 const struct pinmux_ops *pmxops = pctldev->desc->pmxops;
516 unsigned i, pin; 550 unsigned i, pin;
517 551
552 if (!pmxops)
553 return 0;
554
518 seq_puts(s, "Pinmux settings per pin\n"); 555 seq_puts(s, "Pinmux settings per pin\n");
519 seq_puts(s, "Format: pin (name): mux_owner gpio_owner hog?\n"); 556 seq_puts(s, "Format: pin (name): mux_owner gpio_owner hog?\n");
520 557
diff --git a/drivers/pinctrl/pinmux.h b/drivers/pinctrl/pinmux.h
index 6fc47003e95..d1a98b1c9fc 100644
--- a/drivers/pinctrl/pinmux.h
+++ b/drivers/pinctrl/pinmux.h
@@ -31,12 +31,6 @@ void pinmux_free_setting(struct pinctrl_setting const *setting);
31int pinmux_enable_setting(struct pinctrl_setting const *setting); 31int pinmux_enable_setting(struct pinctrl_setting const *setting);
32void pinmux_disable_setting(struct pinctrl_setting const *setting); 32void pinmux_disable_setting(struct pinctrl_setting const *setting);
33 33
34void pinmux_show_map(struct seq_file *s, struct pinctrl_map const *map);
35void pinmux_show_setting(struct seq_file *s,
36 struct pinctrl_setting const *setting);
37void pinmux_init_device_debugfs(struct dentry *devroot,
38 struct pinctrl_dev *pctldev);
39
40#else 34#else
41 35
42static inline int pinmux_check_ops(struct pinctrl_dev *pctldev) 36static inline int pinmux_check_ops(struct pinctrl_dev *pctldev)
@@ -89,6 +83,18 @@ static inline void pinmux_disable_setting(
89{ 83{
90} 84}
91 85
86#endif
87
88#if defined(CONFIG_PINMUX) && defined(CONFIG_DEBUG_FS)
89
90void pinmux_show_map(struct seq_file *s, struct pinctrl_map const *map);
91void pinmux_show_setting(struct seq_file *s,
92 struct pinctrl_setting const *setting);
93void pinmux_init_device_debugfs(struct dentry *devroot,
94 struct pinctrl_dev *pctldev);
95
96#else
97
92static inline void pinmux_show_map(struct seq_file *s, 98static inline void pinmux_show_map(struct seq_file *s,
93 struct pinctrl_map const *map) 99 struct pinctrl_map const *map)
94{ 100{
diff --git a/include/linux/of.h b/include/linux/of.h
index fa7fb1d9745..2ec1083af7f 100644
--- a/include/linux/of.h
+++ b/include/linux/of.h
@@ -193,6 +193,17 @@ extern struct device_node *of_get_next_child(const struct device_node *node,
193 for (child = of_get_next_child(parent, NULL); child != NULL; \ 193 for (child = of_get_next_child(parent, NULL); child != NULL; \
194 child = of_get_next_child(parent, child)) 194 child = of_get_next_child(parent, child))
195 195
196static inline int of_get_child_count(const struct device_node *np)
197{
198 struct device_node *child;
199 int num = 0;
200
201 for_each_child_of_node(np, child)
202 num++;
203
204 return num;
205}
206
196extern struct device_node *of_find_node_with_property( 207extern struct device_node *of_find_node_with_property(
197 struct device_node *from, const char *prop_name); 208 struct device_node *from, const char *prop_name);
198#define for_each_node_with_property(dn, prop_name) \ 209#define for_each_node_with_property(dn, prop_name) \
@@ -259,6 +270,37 @@ extern void of_detach_node(struct device_node *);
259#endif 270#endif
260 271
261#define of_match_ptr(_ptr) (_ptr) 272#define of_match_ptr(_ptr) (_ptr)
273
274/*
275 * struct property *prop;
276 * const __be32 *p;
277 * u32 u;
278 *
279 * of_property_for_each_u32(np, "propname", prop, p, u)
280 * printk("U32 value: %x\n", u);
281 */
282const __be32 *of_prop_next_u32(struct property *prop, const __be32 *cur,
283 u32 *pu);
284#define of_property_for_each_u32(np, propname, prop, p, u) \
285 for (prop = of_find_property(np, propname, NULL), \
286 p = of_prop_next_u32(prop, NULL, &u); \
287 p; \
288 p = of_prop_next_u32(prop, p, &u))
289
290/*
291 * struct property *prop;
292 * const char *s;
293 *
294 * of_property_for_each_string(np, "propname", prop, s)
295 * printk("String value: %s\n", s);
296 */
297const char *of_prop_next_string(struct property *prop, const char *cur);
298#define of_property_for_each_string(np, propname, prop, s) \
299 for (prop = of_find_property(np, propname, NULL), \
300 s = of_prop_next_string(prop, NULL); \
301 s; \
302 s = of_prop_next_string(prop, s))
303
262#else /* CONFIG_OF */ 304#else /* CONFIG_OF */
263 305
264static inline bool of_have_populated_dt(void) 306static inline bool of_have_populated_dt(void)
@@ -269,6 +311,11 @@ static inline bool of_have_populated_dt(void)
269#define for_each_child_of_node(parent, child) \ 311#define for_each_child_of_node(parent, child) \
270 while (0) 312 while (0)
271 313
314static inline int of_get_child_count(const struct device_node *np)
315{
316 return 0;
317}
318
272static inline int of_device_is_compatible(const struct device_node *device, 319static inline int of_device_is_compatible(const struct device_node *device,
273 const char *name) 320 const char *name)
274{ 321{
@@ -349,6 +396,10 @@ static inline int of_machine_is_compatible(const char *compat)
349 396
350#define of_match_ptr(_ptr) NULL 397#define of_match_ptr(_ptr) NULL
351#define of_match_node(_matches, _node) NULL 398#define of_match_node(_matches, _node) NULL
399#define of_property_for_each_u32(np, propname, prop, p, u) \
400 while (0)
401#define of_property_for_each_string(np, propname, prop, s) \
402 while (0)
352#endif /* CONFIG_OF */ 403#endif /* CONFIG_OF */
353 404
354/** 405/**
diff --git a/include/linux/pinctrl/consumer.h b/include/linux/pinctrl/consumer.h
index 191e7268848..6dd96fb4548 100644
--- a/include/linux/pinctrl/consumer.h
+++ b/include/linux/pinctrl/consumer.h
@@ -36,6 +36,9 @@ extern struct pinctrl_state * __must_check pinctrl_lookup_state(
36 const char *name); 36 const char *name);
37extern int pinctrl_select_state(struct pinctrl *p, struct pinctrl_state *s); 37extern int pinctrl_select_state(struct pinctrl *p, struct pinctrl_state *s);
38 38
39extern struct pinctrl * __must_check devm_pinctrl_get(struct device *dev);
40extern void devm_pinctrl_put(struct pinctrl *p);
41
39#else /* !CONFIG_PINCTRL */ 42#else /* !CONFIG_PINCTRL */
40 43
41static inline int pinctrl_request_gpio(unsigned gpio) 44static inline int pinctrl_request_gpio(unsigned gpio)
@@ -79,6 +82,15 @@ static inline int pinctrl_select_state(struct pinctrl *p,
79 return 0; 82 return 0;
80} 83}
81 84
85static inline struct pinctrl * __must_check devm_pinctrl_get(struct device *dev)
86{
87 return NULL;
88}
89
90static inline void devm_pinctrl_put(struct pinctrl *p)
91{
92}
93
82#endif /* CONFIG_PINCTRL */ 94#endif /* CONFIG_PINCTRL */
83 95
84static inline struct pinctrl * __must_check pinctrl_get_select( 96static inline struct pinctrl * __must_check pinctrl_get_select(
@@ -113,6 +125,38 @@ static inline struct pinctrl * __must_check pinctrl_get_select_default(
113 return pinctrl_get_select(dev, PINCTRL_STATE_DEFAULT); 125 return pinctrl_get_select(dev, PINCTRL_STATE_DEFAULT);
114} 126}
115 127
128static inline struct pinctrl * __must_check devm_pinctrl_get_select(
129 struct device *dev, const char *name)
130{
131 struct pinctrl *p;
132 struct pinctrl_state *s;
133 int ret;
134
135 p = devm_pinctrl_get(dev);
136 if (IS_ERR(p))
137 return p;
138
139 s = pinctrl_lookup_state(p, name);
140 if (IS_ERR(s)) {
141 devm_pinctrl_put(p);
142 return ERR_PTR(PTR_ERR(s));
143 }
144
145 ret = pinctrl_select_state(p, s);
146 if (ret < 0) {
147 devm_pinctrl_put(p);
148 return ERR_PTR(ret);
149 }
150
151 return p;
152}
153
154static inline struct pinctrl * __must_check devm_pinctrl_get_select_default(
155 struct device *dev)
156{
157 return devm_pinctrl_get_select(dev, PINCTRL_STATE_DEFAULT);
158}
159
116#ifdef CONFIG_PINCONF 160#ifdef CONFIG_PINCONF
117 161
118extern int pin_config_get(const char *dev_name, const char *name, 162extern int pin_config_get(const char *dev_name, const char *name,
diff --git a/include/linux/pinctrl/machine.h b/include/linux/pinctrl/machine.h
index e4d1de74250..7d22ab00343 100644
--- a/include/linux/pinctrl/machine.h
+++ b/include/linux/pinctrl/machine.h
@@ -154,7 +154,7 @@ struct pinctrl_map {
154 154
155extern int pinctrl_register_mappings(struct pinctrl_map const *map, 155extern int pinctrl_register_mappings(struct pinctrl_map const *map,
156 unsigned num_maps); 156 unsigned num_maps);
157 157extern void pinctrl_provide_dummies(void);
158#else 158#else
159 159
160static inline int pinctrl_register_mappings(struct pinctrl_map const *map, 160static inline int pinctrl_register_mappings(struct pinctrl_map const *map,
@@ -163,5 +163,8 @@ static inline int pinctrl_register_mappings(struct pinctrl_map const *map,
163 return 0; 163 return 0;
164} 164}
165 165
166#endif /* !CONFIG_PINMUX */ 166static inline void pinctrl_provide_dummies(void)
167{
168}
169#endif /* !CONFIG_PINCTRL */
167#endif 170#endif
diff --git a/include/linux/pinctrl/pinconf.h b/include/linux/pinctrl/pinconf.h
index ec431f03362..e7a720104a4 100644
--- a/include/linux/pinctrl/pinconf.h
+++ b/include/linux/pinctrl/pinconf.h
@@ -25,7 +25,6 @@ struct seq_file;
25 * @pin_config_get: get the config of a certain pin, if the requested config 25 * @pin_config_get: get the config of a certain pin, if the requested config
26 * is not available on this controller this should return -ENOTSUPP 26 * is not available on this controller this should return -ENOTSUPP
27 * and if it is available but disabled it should return -EINVAL 27 * and if it is available but disabled it should return -EINVAL
28 * @pin_config_get: get the config of a certain pin
29 * @pin_config_set: configure an individual pin 28 * @pin_config_set: configure an individual pin
30 * @pin_config_group_get: get configurations for an entire pin group 29 * @pin_config_group_get: get configurations for an entire pin group
31 * @pin_config_group_set: configure all pins in a group 30 * @pin_config_group_set: configure all pins in a group
@@ -33,6 +32,8 @@ struct seq_file;
33 * per-device info for a certain pin in debugfs 32 * per-device info for a certain pin in debugfs
34 * @pin_config_group_dbg_show: optional debugfs display hook that will provide 33 * @pin_config_group_dbg_show: optional debugfs display hook that will provide
35 * per-device info for a certain group in debugfs 34 * per-device info for a certain group in debugfs
35 * @pin_config_config_dbg_show: optional debugfs display hook that will decode
36 * and display a driver's pin configuration parameter
36 */ 37 */
37struct pinconf_ops { 38struct pinconf_ops {
38#ifdef CONFIG_GENERIC_PINCONF 39#ifdef CONFIG_GENERIC_PINCONF
@@ -56,6 +57,9 @@ struct pinconf_ops {
56 void (*pin_config_group_dbg_show) (struct pinctrl_dev *pctldev, 57 void (*pin_config_group_dbg_show) (struct pinctrl_dev *pctldev,
57 struct seq_file *s, 58 struct seq_file *s,
58 unsigned selector); 59 unsigned selector);
60 void (*pin_config_config_dbg_show) (struct pinctrl_dev *pctldev,
61 struct seq_file *s,
62 unsigned long config);
59}; 63};
60 64
61#endif 65#endif
diff --git a/include/linux/pinctrl/pinctrl.h b/include/linux/pinctrl/pinctrl.h
index 4e9f0788c22..3b894a668d3 100644
--- a/include/linux/pinctrl/pinctrl.h
+++ b/include/linux/pinctrl/pinctrl.h
@@ -21,9 +21,11 @@
21 21
22struct device; 22struct device;
23struct pinctrl_dev; 23struct pinctrl_dev;
24struct pinctrl_map;
24struct pinmux_ops; 25struct pinmux_ops;
25struct pinconf_ops; 26struct pinconf_ops;
26struct gpio_chip; 27struct gpio_chip;
28struct device_node;
27 29
28/** 30/**
29 * struct pinctrl_pin_desc - boards/machines provide information on their 31 * struct pinctrl_pin_desc - boards/machines provide information on their
@@ -64,17 +66,24 @@ struct pinctrl_gpio_range {
64/** 66/**
65 * struct pinctrl_ops - global pin control operations, to be implemented by 67 * struct pinctrl_ops - global pin control operations, to be implemented by
66 * pin controller drivers. 68 * pin controller drivers.
67 * @list_groups: list the number of selectable named groups available 69 * @get_groups_count: Returns the count of total number of groups registered.
68 * in this pinmux driver, the core will begin on 0 and call this
69 * repeatedly as long as it returns >= 0 to enumerate the groups
70 * @get_group_name: return the group name of the pin group 70 * @get_group_name: return the group name of the pin group
71 * @get_group_pins: return an array of pins corresponding to a certain 71 * @get_group_pins: return an array of pins corresponding to a certain
72 * group selector @pins, and the size of the array in @num_pins 72 * group selector @pins, and the size of the array in @num_pins
73 * @pin_dbg_show: optional debugfs display hook that will provide per-device 73 * @pin_dbg_show: optional debugfs display hook that will provide per-device
74 * info for a certain pin in debugfs 74 * info for a certain pin in debugfs
75 * @dt_node_to_map: parse a device tree "pin configuration node", and create
76 * mapping table entries for it. These are returned through the @map and
77 * @num_maps output parameters. This function is optional, and may be
78 * omitted for pinctrl drivers that do not support device tree.
79 * @dt_free_map: free mapping table entries created via @dt_node_to_map. The
80 * top-level @map pointer must be freed, along with any dynamically
81 * allocated members of the mapping table entries themselves. This
82 * function is optional, and may be omitted for pinctrl drivers that do
83 * not support device tree.
75 */ 84 */
76struct pinctrl_ops { 85struct pinctrl_ops {
77 int (*list_groups) (struct pinctrl_dev *pctldev, unsigned selector); 86 int (*get_groups_count) (struct pinctrl_dev *pctldev);
78 const char *(*get_group_name) (struct pinctrl_dev *pctldev, 87 const char *(*get_group_name) (struct pinctrl_dev *pctldev,
79 unsigned selector); 88 unsigned selector);
80 int (*get_group_pins) (struct pinctrl_dev *pctldev, 89 int (*get_group_pins) (struct pinctrl_dev *pctldev,
@@ -83,6 +92,11 @@ struct pinctrl_ops {
83 unsigned *num_pins); 92 unsigned *num_pins);
84 void (*pin_dbg_show) (struct pinctrl_dev *pctldev, struct seq_file *s, 93 void (*pin_dbg_show) (struct pinctrl_dev *pctldev, struct seq_file *s,
85 unsigned offset); 94 unsigned offset);
95 int (*dt_node_to_map) (struct pinctrl_dev *pctldev,
96 struct device_node *np_config,
97 struct pinctrl_map **map, unsigned *num_maps);
98 void (*dt_free_map) (struct pinctrl_dev *pctldev,
99 struct pinctrl_map *map, unsigned num_maps);
86}; 100};
87 101
88/** 102/**
diff --git a/include/linux/pinctrl/pinmux.h b/include/linux/pinctrl/pinmux.h
index 47e9237edd4..1818dcbdd9a 100644
--- a/include/linux/pinctrl/pinmux.h
+++ b/include/linux/pinctrl/pinmux.h
@@ -23,15 +23,14 @@ struct pinctrl_dev;
23/** 23/**
24 * struct pinmux_ops - pinmux operations, to be implemented by pin controller 24 * struct pinmux_ops - pinmux operations, to be implemented by pin controller
25 * drivers that support pinmuxing 25 * drivers that support pinmuxing
26 * @request: called by the core to see if a certain pin can be made available 26 * @request: called by the core to see if a certain pin can be made
27 * available for muxing. This is called by the core to acquire the pins 27 * available for muxing. This is called by the core to acquire the pins
28 * before selecting any actual mux setting across a function. The driver 28 * before selecting any actual mux setting across a function. The driver
29 * is allowed to answer "no" by returning a negative error code 29 * is allowed to answer "no" by returning a negative error code
30 * @free: the reverse function of the request() callback, frees a pin after 30 * @free: the reverse function of the request() callback, frees a pin after
31 * being requested 31 * being requested
32 * @list_functions: list the number of selectable named functions available 32 * @get_functions_count: returns number of selectable named functions available
33 * in this pinmux driver, the core will begin on 0 and call this 33 * in this pinmux driver
34 * repeatedly as long as it returns >= 0 to enumerate mux settings
35 * @get_function_name: return the function name of the muxing selector, 34 * @get_function_name: return the function name of the muxing selector,
36 * called by the core to figure out which mux setting it shall map a 35 * called by the core to figure out which mux setting it shall map a
37 * certain device to 36 * certain device to
@@ -62,7 +61,7 @@ struct pinctrl_dev;
62struct pinmux_ops { 61struct pinmux_ops {
63 int (*request) (struct pinctrl_dev *pctldev, unsigned offset); 62 int (*request) (struct pinctrl_dev *pctldev, unsigned offset);
64 int (*free) (struct pinctrl_dev *pctldev, unsigned offset); 63 int (*free) (struct pinctrl_dev *pctldev, unsigned offset);
65 int (*list_functions) (struct pinctrl_dev *pctldev, unsigned selector); 64 int (*get_functions_count) (struct pinctrl_dev *pctldev);
66 const char *(*get_function_name) (struct pinctrl_dev *pctldev, 65 const char *(*get_function_name) (struct pinctrl_dev *pctldev,
67 unsigned selector); 66 unsigned selector);
68 int (*get_function_groups) (struct pinctrl_dev *pctldev, 67 int (*get_function_groups) (struct pinctrl_dev *pctldev,
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-13 02:51:37 -0400