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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2009-02-17 21:23:30 -0500
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2009-02-17 21:23:30 -0500
commit3b7faeb49e7c35db857b595c389436994ab1275e (patch)
tree973208eb935876ebed9f2baf262ed08351764752
parent82a0a1cc8f94bc59e5919715bc03fc8353fa770d (diff)
parent96a8bac5895a41b0fb05a6aa7c3fa1ea631a91fe (diff)
Merge commit 'kumar/next' into next
Diffstat
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds.dts10
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds_36b.dts787
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts8
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts4
-rw-r--r--arch/powerpc/include/asm/mmu-book3e.h (renamed from arch/powerpc/include/asm/mmu-fsl-booke.h)66
-rw-r--r--arch/powerpc/include/asm/mmu.h6
-rw-r--r--arch/powerpc/kernel/entry_32.S6
-rw-r--r--arch/powerpc/kernel/head_fsl_booke.S14
-rw-r--r--arch/powerpc/mm/fsl_booke_mmu.c6
-rw-r--r--arch/powerpc/platforms/Kconfig.cputype4
10 files changed, 860 insertions, 51 deletions
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts
index 359c3b72742..6c9354b2d7b 100644
--- a/arch/powerpc/boot/dts/mpc8572ds.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC8572 DS Device Tree Source 2 * MPC8572 DS Device Tree Source
3 * 3 *
4 * Copyright 2007, 2008 Freescale Semiconductor Inc. 4 * Copyright 2007-2009 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -643,7 +643,7 @@
643 643
644 0x1000000 0x0 0x0 644 0x1000000 0x0 0x0
645 0x1000000 0x0 0x0 645 0x1000000 0x0 0x0
646 0x0 0x100000>; 646 0x0 0x10000>;
647 uli1575@0 { 647 uli1575@0 {
648 reg = <0x0 0x0 0x0 0x0 0x0>; 648 reg = <0x0 0x0 0x0 0x0 0x0>;
649 #size-cells = <2>; 649 #size-cells = <2>;
@@ -654,7 +654,7 @@
654 654
655 0x1000000 0x0 0x0 655 0x1000000 0x0 0x0
656 0x1000000 0x0 0x0 656 0x1000000 0x0 0x0
657 0x0 0x100000>; 657 0x0 0x10000>;
658 isa@1e { 658 isa@1e {
659 device_type = "isa"; 659 device_type = "isa";
660 #interrupt-cells = <2>; 660 #interrupt-cells = <2>;
@@ -744,7 +744,7 @@
744 744
745 0x1000000 0x0 0x0 745 0x1000000 0x0 0x0
746 0x1000000 0x0 0x0 746 0x1000000 0x0 0x0
747 0x0 0x100000>; 747 0x0 0x10000>;
748 }; 748 };
749 }; 749 };
750 750
@@ -781,7 +781,7 @@
781 781
782 0x1000000 0x0 0x0 782 0x1000000 0x0 0x0
783 0x1000000 0x0 0x0 783 0x1000000 0x0 0x0
784 0x0 0x100000>; 784 0x0 0x10000>;
785 }; 785 };
786 }; 786 };
787}; 787};
diff --git a/arch/powerpc/boot/dts/mpc8572ds_36b.dts b/arch/powerpc/boot/dts/mpc8572ds_36b.dts
new file mode 100644
index 00000000000..fc7dbf49f4c
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8572ds_36b.dts
@@ -0,0 +1,787 @@
1/*
2 * MPC8572 DS Device Tree Source
3 *
4 * Copyright 2007-2009 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13/ {
14 model = "fsl,MPC8572DS";
15 compatible = "fsl,MPC8572DS";
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 aliases {
20 ethernet0 = &enet0;
21 ethernet1 = &enet1;
22 ethernet2 = &enet2;
23 ethernet3 = &enet3;
24 serial0 = &serial0;
25 serial1 = &serial1;
26 pci0 = &pci0;
27 pci1 = &pci1;
28 pci2 = &pci2;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 PowerPC,8572@0 {
36 device_type = "cpu";
37 reg = <0x0>;
38 d-cache-line-size = <32>; // 32 bytes
39 i-cache-line-size = <32>; // 32 bytes
40 d-cache-size = <0x8000>; // L1, 32K
41 i-cache-size = <0x8000>; // L1, 32K
42 timebase-frequency = <0>;
43 bus-frequency = <0>;
44 clock-frequency = <0>;
45 next-level-cache = <&L2>;
46 };
47
48 PowerPC,8572@1 {
49 device_type = "cpu";
50 reg = <0x1>;
51 d-cache-line-size = <32>; // 32 bytes
52 i-cache-line-size = <32>; // 32 bytes
53 d-cache-size = <0x8000>; // L1, 32K
54 i-cache-size = <0x8000>; // L1, 32K
55 timebase-frequency = <0>;
56 bus-frequency = <0>;
57 clock-frequency = <0>;
58 next-level-cache = <&L2>;
59 };
60 };
61
62 memory {
63 device_type = "memory";
64 };
65
66 localbus@fffe05000 {
67 #address-cells = <2>;
68 #size-cells = <1>;
69 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
70 reg = <0xf 0xffe05000 0 0x1000>;
71 interrupts = <19 2>;
72 interrupt-parent = <&mpic>;
73
74 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
75 0x1 0x0 0xf 0xe0000000 0x08000000
76 0x2 0x0 0xf 0xffa00000 0x00040000
77 0x3 0x0 0xf 0xffdf0000 0x00008000
78 0x4 0x0 0xf 0xffa40000 0x00040000
79 0x5 0x0 0xf 0xffa80000 0x00040000
80 0x6 0x0 0xf 0xffac0000 0x00040000>;
81
82 nor@0,0 {
83 #address-cells = <1>;
84 #size-cells = <1>;
85 compatible = "cfi-flash";
86 reg = <0x0 0x0 0x8000000>;
87 bank-width = <2>;
88 device-width = <1>;
89
90 ramdisk@0 {
91 reg = <0x0 0x03000000>;
92 read-only;
93 };
94
95 diagnostic@3000000 {
96 reg = <0x03000000 0x00e00000>;
97 read-only;
98 };
99
100 dink@3e00000 {
101 reg = <0x03e00000 0x00200000>;
102 read-only;
103 };
104
105 kernel@4000000 {
106 reg = <0x04000000 0x00400000>;
107 read-only;
108 };
109
110 jffs2@4400000 {
111 reg = <0x04400000 0x03b00000>;
112 };
113
114 dtb@7f00000 {
115 reg = <0x07f00000 0x00080000>;
116 read-only;
117 };
118
119 u-boot@7f80000 {
120 reg = <0x07f80000 0x00080000>;
121 read-only;
122 };
123 };
124
125 nand@2,0 {
126 #address-cells = <1>;
127 #size-cells = <1>;
128 compatible = "fsl,mpc8572-fcm-nand",
129 "fsl,elbc-fcm-nand";
130 reg = <0x2 0x0 0x40000>;
131
132 u-boot@0 {
133 reg = <0x0 0x02000000>;
134 read-only;
135 };
136
137 jffs2@2000000 {
138 reg = <0x02000000 0x10000000>;
139 };
140
141 ramdisk@12000000 {
142 reg = <0x12000000 0x08000000>;
143 read-only;
144 };
145
146 kernel@1a000000 {
147 reg = <0x1a000000 0x04000000>;
148 };
149
150 dtb@1e000000 {
151 reg = <0x1e000000 0x01000000>;
152 read-only;
153 };
154
155 empty@1f000000 {
156 reg = <0x1f000000 0x21000000>;
157 };
158 };
159
160 nand@4,0 {
161 compatible = "fsl,mpc8572-fcm-nand",
162 "fsl,elbc-fcm-nand";
163 reg = <0x4 0x0 0x40000>;
164 };
165
166 nand@5,0 {
167 compatible = "fsl,mpc8572-fcm-nand",
168 "fsl,elbc-fcm-nand";
169 reg = <0x5 0x0 0x40000>;
170 };
171
172 nand@6,0 {
173 compatible = "fsl,mpc8572-fcm-nand",
174 "fsl,elbc-fcm-nand";
175 reg = <0x6 0x0 0x40000>;
176 };
177 };
178
179 soc8572@fffe00000 {
180 #address-cells = <1>;
181 #size-cells = <1>;
182 device_type = "soc";
183 compatible = "simple-bus";
184 ranges = <0x0 0xf 0xffe00000 0x100000>;
185 reg = <0xf 0xffe00000 0 0x1000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed
186 bus-frequency = <0>; // Filled out by uboot.
187
188 memory-controller@2000 {
189 compatible = "fsl,mpc8572-memory-controller";
190 reg = <0x2000 0x1000>;
191 interrupt-parent = <&mpic>;
192 interrupts = <18 2>;
193 };
194
195 memory-controller@6000 {
196 compatible = "fsl,mpc8572-memory-controller";
197 reg = <0x6000 0x1000>;
198 interrupt-parent = <&mpic>;
199 interrupts = <18 2>;
200 };
201
202 L2: l2-cache-controller@20000 {
203 compatible = "fsl,mpc8572-l2-cache-controller";
204 reg = <0x20000 0x1000>;
205 cache-line-size = <32>; // 32 bytes
206 cache-size = <0x100000>; // L2, 1M
207 interrupt-parent = <&mpic>;
208 interrupts = <16 2>;
209 };
210
211 i2c@3000 {
212 #address-cells = <1>;
213 #size-cells = <0>;
214 cell-index = <0>;
215 compatible = "fsl-i2c";
216 reg = <0x3000 0x100>;
217 interrupts = <43 2>;
218 interrupt-parent = <&mpic>;
219 dfsrr;
220 };
221
222 i2c@3100 {
223 #address-cells = <1>;
224 #size-cells = <0>;
225 cell-index = <1>;
226 compatible = "fsl-i2c";
227 reg = <0x3100 0x100>;
228 interrupts = <43 2>;
229 interrupt-parent = <&mpic>;
230 dfsrr;
231 };
232
233 dma@c300 {
234 #address-cells = <1>;
235 #size-cells = <1>;
236 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
237 reg = <0xc300 0x4>;
238 ranges = <0x0 0xc100 0x200>;
239 cell-index = <1>;
240 dma-channel@0 {
241 compatible = "fsl,mpc8572-dma-channel",
242 "fsl,eloplus-dma-channel";
243 reg = <0x0 0x80>;
244 cell-index = <0>;
245 interrupt-parent = <&mpic>;
246 interrupts = <76 2>;
247 };
248 dma-channel@80 {
249 compatible = "fsl,mpc8572-dma-channel",
250 "fsl,eloplus-dma-channel";
251 reg = <0x80 0x80>;
252 cell-index = <1>;
253 interrupt-parent = <&mpic>;
254 interrupts = <77 2>;
255 };
256 dma-channel@100 {
257 compatible = "fsl,mpc8572-dma-channel",
258 "fsl,eloplus-dma-channel";
259 reg = <0x100 0x80>;
260 cell-index = <2>;
261 interrupt-parent = <&mpic>;
262 interrupts = <78 2>;
263 };
264 dma-channel@180 {
265 compatible = "fsl,mpc8572-dma-channel",
266 "fsl,eloplus-dma-channel";
267 reg = <0x180 0x80>;
268 cell-index = <3>;
269 interrupt-parent = <&mpic>;
270 interrupts = <79 2>;
271 };
272 };
273
274 dma@21300 {
275 #address-cells = <1>;
276 #size-cells = <1>;
277 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
278 reg = <0x21300 0x4>;
279 ranges = <0x0 0x21100 0x200>;
280 cell-index = <0>;
281 dma-channel@0 {
282 compatible = "fsl,mpc8572-dma-channel",
283 "fsl,eloplus-dma-channel";
284 reg = <0x0 0x80>;
285 cell-index = <0>;
286 interrupt-parent = <&mpic>;
287 interrupts = <20 2>;
288 };
289 dma-channel@80 {
290 compatible = "fsl,mpc8572-dma-channel",
291 "fsl,eloplus-dma-channel";
292 reg = <0x80 0x80>;
293 cell-index = <1>;
294 interrupt-parent = <&mpic>;
295 interrupts = <21 2>;
296 };
297 dma-channel@100 {
298 compatible = "fsl,mpc8572-dma-channel",
299 "fsl,eloplus-dma-channel";
300 reg = <0x100 0x80>;
301 cell-index = <2>;
302 interrupt-parent = <&mpic>;
303 interrupts = <22 2>;
304 };
305 dma-channel@180 {
306 compatible = "fsl,mpc8572-dma-channel",
307 "fsl,eloplus-dma-channel";
308 reg = <0x180 0x80>;
309 cell-index = <3>;
310 interrupt-parent = <&mpic>;
311 interrupts = <23 2>;
312 };
313 };
314
315 mdio@24520 {
316 #address-cells = <1>;
317 #size-cells = <0>;
318 compatible = "fsl,gianfar-mdio";
319 reg = <0x24520 0x20>;
320
321 phy0: ethernet-phy@0 {
322 interrupt-parent = <&mpic>;
323 interrupts = <10 1>;
324 reg = <0x0>;
325 };
326 phy1: ethernet-phy@1 {
327 interrupt-parent = <&mpic>;
328 interrupts = <10 1>;
329 reg = <0x1>;
330 };
331 phy2: ethernet-phy@2 {
332 interrupt-parent = <&mpic>;
333 interrupts = <10 1>;
334 reg = <0x2>;
335 };
336 phy3: ethernet-phy@3 {
337 interrupt-parent = <&mpic>;
338 interrupts = <10 1>;
339 reg = <0x3>;
340 };
341
342 tbi0: tbi-phy@11 {
343 reg = <0x11>;
344 device_type = "tbi-phy";
345 };
346 };
347
348 mdio@25520 {
349 #address-cells = <1>;
350 #size-cells = <0>;
351 compatible = "fsl,gianfar-tbi";
352 reg = <0x25520 0x20>;
353
354 tbi1: tbi-phy@11 {
355 reg = <0x11>;
356 device_type = "tbi-phy";
357 };
358 };
359
360 mdio@26520 {
361 #address-cells = <1>;
362 #size-cells = <0>;
363 compatible = "fsl,gianfar-tbi";
364 reg = <0x26520 0x20>;
365
366 tbi2: tbi-phy@11 {
367 reg = <0x11>;
368 device_type = "tbi-phy";
369 };
370 };
371
372 mdio@27520 {
373 #address-cells = <1>;
374 #size-cells = <0>;
375 compatible = "fsl,gianfar-tbi";
376 reg = <0x27520 0x20>;
377
378 tbi3: tbi-phy@11 {
379 reg = <0x11>;
380 device_type = "tbi-phy";
381 };
382 };
383
384 enet0: ethernet@24000 {
385 cell-index = <0>;
386 device_type = "network";
387 model = "eTSEC";
388 compatible = "gianfar";
389 reg = <0x24000 0x1000>;
390 local-mac-address = [ 00 00 00 00 00 00 ];
391 interrupts = <29 2 30 2 34 2>;
392 interrupt-parent = <&mpic>;
393 tbi-handle = <&tbi0>;
394 phy-handle = <&phy0>;
395 phy-connection-type = "rgmii-id";
396 };
397
398 enet1: ethernet@25000 {
399 cell-index = <1>;
400 device_type = "network";
401 model = "eTSEC";
402 compatible = "gianfar";
403 reg = <0x25000 0x1000>;
404 local-mac-address = [ 00 00 00 00 00 00 ];
405 interrupts = <35 2 36 2 40 2>;
406 interrupt-parent = <&mpic>;
407 tbi-handle = <&tbi1>;
408 phy-handle = <&phy1>;
409 phy-connection-type = "rgmii-id";
410 };
411
412 enet2: ethernet@26000 {
413 cell-index = <2>;
414 device_type = "network";
415 model = "eTSEC";
416 compatible = "gianfar";
417 reg = <0x26000 0x1000>;
418 local-mac-address = [ 00 00 00 00 00 00 ];
419 interrupts = <31 2 32 2 33 2>;
420 interrupt-parent = <&mpic>;
421 tbi-handle = <&tbi2>;
422 phy-handle = <&phy2>;
423 phy-connection-type = "rgmii-id";
424 };
425
426 enet3: ethernet@27000 {
427 cell-index = <3>;
428 device_type = "network";
429 model = "eTSEC";
430 compatible = "gianfar";
431 reg = <0x27000 0x1000>;
432 local-mac-address = [ 00 00 00 00 00 00 ];
433 interrupts = <37 2 38 2 39 2>;
434 interrupt-parent = <&mpic>;
435 tbi-handle = <&tbi3>;
436 phy-handle = <&phy3>;
437 phy-connection-type = "rgmii-id";
438 };
439
440 serial0: serial@4500 {
441 cell-index = <0>;
442 device_type = "serial";
443 compatible = "ns16550";
444 reg = <0x4500 0x100>;
445 clock-frequency = <0>;
446 interrupts = <42 2>;
447 interrupt-parent = <&mpic>;
448 };
449
450 serial1: serial@4600 {
451 cell-index = <1>;
452 device_type = "serial";
453 compatible = "ns16550";
454 reg = <0x4600 0x100>;
455 clock-frequency = <0>;
456 interrupts = <42 2>;
457 interrupt-parent = <&mpic>;
458 };
459
460 global-utilities@e0000 { //global utilities block
461 compatible = "fsl,mpc8572-guts";
462 reg = <0xe0000 0x1000>;
463 fsl,has-rstcr;
464 };
465
466 msi@41600 {
467 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
468 reg = <0x41600 0x80>;
469 msi-available-ranges = <0 0x100>;
470 interrupts = <
471 0xe0 0
472 0xe1 0
473 0xe2 0
474 0xe3 0
475 0xe4 0
476 0xe5 0
477 0xe6 0
478 0xe7 0>;
479 interrupt-parent = <&mpic>;
480 };
481
482 crypto@30000 {
483 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
484 "fsl,sec2.1", "fsl,sec2.0";
485 reg = <0x30000 0x10000>;
486 interrupts = <45 2 58 2>;
487 interrupt-parent = <&mpic>;
488 fsl,num-channels = <4>;
489 fsl,channel-fifo-len = <24>;
490 fsl,exec-units-mask = <0x9fe>;
491 fsl,descriptor-types-mask = <0x3ab0ebf>;
492 };
493
494 mpic: pic@40000 {
495 interrupt-controller;
496 #address-cells = <0>;
497 #interrupt-cells = <2>;
498 reg = <0x40000 0x40000>;
499 compatible = "chrp,open-pic";
500 device_type = "open-pic";
501 };
502 };
503
504 pci0: pcie@fffe08000 {
505 cell-index = <0>;
506 compatible = "fsl,mpc8548-pcie";
507 device_type = "pci";
508 #interrupt-cells = <1>;
509 #size-cells = <2>;
510 #address-cells = <3>;
511 reg = <0xf 0xffe08000 0 0x1000>;
512 bus-range = <0 255>;
513 ranges = <0x2000000 0x0 0xc0000000 0xc 0x00000000 0x0 0x20000000
514 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000>;
515 clock-frequency = <33333333>;
516 interrupt-parent = <&mpic>;
517 interrupts = <24 2>;
518 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
519 interrupt-map = <
520 /* IDSEL 0x11 func 0 - PCI slot 1 */
521 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
522 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
523 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
524 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
525
526 /* IDSEL 0x11 func 1 - PCI slot 1 */
527 0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
528 0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
529 0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
530 0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
531
532 /* IDSEL 0x11 func 2 - PCI slot 1 */
533 0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
534 0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
535 0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
536 0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
537
538 /* IDSEL 0x11 func 3 - PCI slot 1 */
539 0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
540 0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
541 0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
542 0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
543
544 /* IDSEL 0x11 func 4 - PCI slot 1 */
545 0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
546 0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
547 0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
548 0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
549
550 /* IDSEL 0x11 func 5 - PCI slot 1 */
551 0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
552 0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
553 0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
554 0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
555
556 /* IDSEL 0x11 func 6 - PCI slot 1 */
557 0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
558 0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
559 0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
560 0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
561
562 /* IDSEL 0x11 func 7 - PCI slot 1 */
563 0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
564 0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
565 0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
566 0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
567
568 /* IDSEL 0x12 func 0 - PCI slot 2 */
569 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
570 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
571 0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
572 0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
573
574 /* IDSEL 0x12 func 1 - PCI slot 2 */
575 0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
576 0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
577 0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
578 0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
579
580 /* IDSEL 0x12 func 2 - PCI slot 2 */
581 0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
582 0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
583 0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
584 0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
585
586 /* IDSEL 0x12 func 3 - PCI slot 2 */
587 0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
588 0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
589 0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
590 0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
591
592 /* IDSEL 0x12 func 4 - PCI slot 2 */
593 0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
594 0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
595 0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
596 0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
597
598 /* IDSEL 0x12 func 5 - PCI slot 2 */
599 0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
600 0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
601 0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
602 0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
603
604 /* IDSEL 0x12 func 6 - PCI slot 2 */
605 0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
606 0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
607 0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
608 0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
609
610 /* IDSEL 0x12 func 7 - PCI slot 2 */
611 0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
612 0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
613 0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
614 0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
615
616 // IDSEL 0x1c USB
617 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
618 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
619 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
620 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
621
622 // IDSEL 0x1d Audio
623 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
624
625 // IDSEL 0x1e Legacy
626 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
627 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
628
629 // IDSEL 0x1f IDE/SATA
630 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
631 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
632
633 >;
634
635 pcie@0 {
636 reg = <0x0 0x0 0x0 0x0 0x0>;
637 #size-cells = <2>;
638 #address-cells = <3>;
639 device_type = "pci";
640 ranges = <0x2000000 0x0 0xc0000000
641 0x2000000 0x0 0xc0000000
642 0x0 0x20000000
643
644 0x1000000 0x0 0x0
645 0x1000000 0x0 0x0
646 0x0 0x10000>;
647 uli1575@0 {
648 reg = <0x0 0x0 0x0 0x0 0x0>;
649 #size-cells = <2>;
650 #address-cells = <3>;
651 ranges = <0x2000000 0x0 0xc0000000
652 0x2000000 0x0 0xc0000000
653 0x0 0x20000000
654
655 0x1000000 0x0 0x0
656 0x1000000 0x0 0x0
657 0x0 0x10000>;
658 isa@1e {
659 device_type = "isa";
660 #interrupt-cells = <2>;
661 #size-cells = <1>;
662 #address-cells = <2>;
663 reg = <0xf000 0x0 0x0 0x0 0x0>;
664 ranges = <0x1 0x0 0x1000000 0x0 0x0
665 0x1000>;
666 interrupt-parent = <&i8259>;
667
668 i8259: interrupt-controller@20 {
669 reg = <0x1 0x20 0x2
670 0x1 0xa0 0x2
671 0x1 0x4d0 0x2>;
672 interrupt-controller;
673 device_type = "interrupt-controller";
674 #address-cells = <0>;
675 #interrupt-cells = <2>;
676 compatible = "chrp,iic";
677 interrupts = <9 2>;
678 interrupt-parent = <&mpic>;
679 };
680
681 i8042@60 {
682 #size-cells = <0>;
683 #address-cells = <1>;
684 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
685 interrupts = <1 3 12 3>;
686 interrupt-parent =
687 <&i8259>;
688
689 keyboard@0 {
690 reg = <0x0>;
691 compatible = "pnpPNP,303";
692 };
693
694 mouse@1 {
695 reg = <0x1>;
696 compatible = "pnpPNP,f03";
697 };
698 };
699
700 rtc@70 {
701 compatible = "pnpPNP,b00";
702 reg = <0x1 0x70 0x2>;
703 };
704
705 gpio@400 {
706 reg = <0x1 0x400 0x80>;
707 };
708 };
709 };
710 };
711
712 };
713
714 pci1: pcie@fffe09000 {
715 cell-index = <1>;
716 compatible = "fsl,mpc8548-pcie";
717 device_type = "pci";
718 #interrupt-cells = <1>;
719 #size-cells = <2>;
720 #address-cells = <3>;
721 reg = <0xf 0xffe09000 0 0x1000>;
722 bus-range = <0 255>;
723 ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
724 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000>;
725 clock-frequency = <33333333>;
726 interrupt-parent = <&mpic>;
727 interrupts = <25 2>;
728 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
729 interrupt-map = <
730 /* IDSEL 0x0 */
731 0000 0x0 0x0 0x1 &mpic 0x4 0x1
732 0000 0x0 0x0 0x2 &mpic 0x5 0x1
733 0000 0x0 0x0 0x3 &mpic 0x6 0x1
734 0000 0x0 0x0 0x4 &mpic 0x7 0x1
735 >;
736 pcie@0 {
737 reg = <0x0 0x0 0x0 0x0 0x0>;
738 #size-cells = <2>;
739 #address-cells = <3>;
740 device_type = "pci";
741 ranges = <0x2000000 0x0 0xc0000000
742 0x2000000 0x0 0xc0000000
743 0x0 0x20000000
744
745 0x1000000 0x0 0x0
746 0x1000000 0x0 0x0
747 0x0 0x10000>;
748 };
749 };
750
751 pci2: pcie@fffe0a000 {
752 cell-index = <2>;
753 compatible = "fsl,mpc8548-pcie";
754 device_type = "pci";
755 #interrupt-cells = <1>;
756 #size-cells = <2>;
757 #address-cells = <3>;
758 reg = <0xf 0xffe0a000 0 0x1000>;
759 bus-range = <0 255>;
760 ranges = <0x2000000 0x0 0xc0000000 0xc 0x40000000 0x0 0x20000000
761 0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x00010000>;
762 clock-frequency = <33333333>;
763 interrupt-parent = <&mpic>;
764 interrupts = <26 2>;
765 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
766 interrupt-map = <
767 /* IDSEL 0x0 */
768 0000 0x0 0x0 0x1 &mpic 0x0 0x1
769 0000 0x0 0x0 0x2 &mpic 0x1 0x1
770 0000 0x0 0x0 0x3 &mpic 0x2 0x1
771 0000 0x0 0x0 0x4 &mpic 0x3 0x1
772 >;
773 pcie@0 {
774 reg = <0x0 0x0 0x0 0x0 0x0>;
775 #size-cells = <2>;
776 #address-cells = <3>;
777 device_type = "pci";
778 ranges = <0x2000000 0x0 0xc0000000
779 0x2000000 0x0 0xc0000000
780 0x0 0x20000000
781
782 0x1000000 0x0 0x0
783 0x1000000 0x0 0x0
784 0x0 0x10000>;
785 };
786 };
787};
diff --git a/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts b/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
index fd462efa9e6..15d9e35eb58 100644
--- a/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
@@ -6,7 +6,7 @@
6 * This dts file allows core0 to have memory, l2, i2c, dma1, global-util, eth0, 6 * This dts file allows core0 to have memory, l2, i2c, dma1, global-util, eth0,
7 * eth1, crypto, pci0, pci1. 7 * eth1, crypto, pci0, pci1.
8 * 8 *
9 * Copyright 2007, 2008 Freescale Semiconductor Inc. 9 * Copyright 2007-2009 Freescale Semiconductor Inc.
10 * 10 *
11 * This program is free software; you can redistribute it and/or modify it 11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the 12 * under the terms of the GNU General Public License as published by the
@@ -376,7 +376,7 @@
376 376
377 0x1000000 0x0 0x0 377 0x1000000 0x0 0x0
378 0x1000000 0x0 0x0 378 0x1000000 0x0 0x0
379 0x0 0x100000>; 379 0x0 0x10000>;
380 uli1575@0 { 380 uli1575@0 {
381 reg = <0x0 0x0 0x0 0x0 0x0>; 381 reg = <0x0 0x0 0x0 0x0 0x0>;
382 #size-cells = <2>; 382 #size-cells = <2>;
@@ -387,7 +387,7 @@
387 387
388 0x1000000 0x0 0x0 388 0x1000000 0x0 0x0
389 0x1000000 0x0 0x0 389 0x1000000 0x0 0x0
390 0x0 0x100000>; 390 0x0 0x10000>;
391 isa@1e { 391 isa@1e {
392 device_type = "isa"; 392 device_type = "isa";
393 #interrupt-cells = <2>; 393 #interrupt-cells = <2>;
@@ -477,7 +477,7 @@
477 477
478 0x1000000 0x0 0x0 478 0x1000000 0x0 0x0
479 0x1000000 0x0 0x0 479 0x1000000 0x0 0x0
480 0x0 0x100000>; 480 0x0 0x10000>;
481 }; 481 };
482 }; 482 };
483}; 483};
diff --git a/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts b/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts
index e35230f2ac9..eace811d27e 100644
--- a/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts
@@ -7,7 +7,7 @@
7 * 7 *
8 * Please note to add "-b 1" for core1's dts compiling. 8 * Please note to add "-b 1" for core1's dts compiling.
9 * 9 *
10 * Copyright 2007, 2008 Freescale Semiconductor Inc. 10 * Copyright 2007-2009 Freescale Semiconductor Inc.
11 * 11 *
12 * This program is free software; you can redistribute it and/or modify it 12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the 13 * under the terms of the GNU General Public License as published by the
@@ -228,7 +228,7 @@
228 228
229 0x1000000 0x0 0x0 229 0x1000000 0x0 0x0
230 0x1000000 0x0 0x0 230 0x1000000 0x0 0x0
231 0x0 0x100000>; 231 0x0 0x10000>;
232 }; 232 };
233 }; 233 };
234}; 234};
diff --git a/arch/powerpc/include/asm/mmu-fsl-booke.h b/arch/powerpc/include/asm/mmu-book3e.h
index 3f941c0f7e8..c5363c3a720 100644
--- a/arch/powerpc/include/asm/mmu-fsl-booke.h
+++ b/arch/powerpc/include/asm/mmu-book3e.h
@@ -1,26 +1,42 @@
1#ifndef _ASM_POWERPC_MMU_FSL_BOOKE_H_ 1#ifndef _ASM_POWERPC_MMU_BOOK3E_H_
2#define _ASM_POWERPC_MMU_FSL_BOOKE_H_ 2#define _ASM_POWERPC_MMU_BOOK3E_H_
3/* 3/*
4 * Freescale Book-E MMU support 4 * Freescale Book-E/Book-3e (ISA 2.06+) MMU support
5 */ 5 */
6 6
7/* Book-E defined page sizes */ 7/* Book-3e defined page sizes */
8#define BOOKE_PAGESZ_1K 0 8#define BOOK3E_PAGESZ_1K 0
9#define BOOKE_PAGESZ_4K 1 9#define BOOK3E_PAGESZ_2K 1
10#define BOOKE_PAGESZ_16K 2 10#define BOOK3E_PAGESZ_4K 2
11#define BOOKE_PAGESZ_64K 3 11#define BOOK3E_PAGESZ_8K 3
12#define BOOKE_PAGESZ_256K 4 12#define BOOK3E_PAGESZ_16K 4
13#define BOOKE_PAGESZ_1M 5 13#define BOOK3E_PAGESZ_32K 5
14#define BOOKE_PAGESZ_4M 6 14#define BOOK3E_PAGESZ_64K 6
15#define BOOKE_PAGESZ_16M 7 15#define BOOK3E_PAGESZ_128K 7
16#define BOOKE_PAGESZ_64M 8 16#define BOOK3E_PAGESZ_256K 8
17#define BOOKE_PAGESZ_256M 9 17#define BOOK3E_PAGESZ_512K 9
18#define BOOKE_PAGESZ_1GB 10 18#define BOOK3E_PAGESZ_1M 10
19#define BOOKE_PAGESZ_4GB 11 19#define BOOK3E_PAGESZ_2M 11
20#define BOOKE_PAGESZ_16GB 12 20#define BOOK3E_PAGESZ_4M 12
21#define BOOKE_PAGESZ_64GB 13 21#define BOOK3E_PAGESZ_8M 13
22#define BOOKE_PAGESZ_256GB 14 22#define BOOK3E_PAGESZ_16M 14
23#define BOOKE_PAGESZ_1TB 15 23#define BOOK3E_PAGESZ_32M 15
24#define BOOK3E_PAGESZ_64M 16
25#define BOOK3E_PAGESZ_128M 17
26#define BOOK3E_PAGESZ_256M 18
27#define BOOK3E_PAGESZ_512M 19
28#define BOOK3E_PAGESZ_1GB 20
29#define BOOK3E_PAGESZ_2GB 21
30#define BOOK3E_PAGESZ_4GB 22
31#define BOOK3E_PAGESZ_8GB 23
32#define BOOK3E_PAGESZ_16GB 24
33#define BOOK3E_PAGESZ_32GB 25
34#define BOOK3E_PAGESZ_64GB 26
35#define BOOK3E_PAGESZ_128GB 27
36#define BOOK3E_PAGESZ_256GB 28
37#define BOOK3E_PAGESZ_512GB 29
38#define BOOK3E_PAGESZ_1TB 30
39#define BOOK3E_PAGESZ_2TB 31
24 40
25#define MAS0_TLBSEL(x) ((x << 28) & 0x30000000) 41#define MAS0_TLBSEL(x) ((x << 28) & 0x30000000)
26#define MAS0_ESEL(x) ((x << 16) & 0x0FFF0000) 42#define MAS0_ESEL(x) ((x << 16) & 0x0FFF0000)
@@ -29,8 +45,9 @@
29#define MAS1_VALID 0x80000000 45#define MAS1_VALID 0x80000000
30#define MAS1_IPROT 0x40000000 46#define MAS1_IPROT 0x40000000
31#define MAS1_TID(x) ((x << 16) & 0x3FFF0000) 47#define MAS1_TID(x) ((x << 16) & 0x3FFF0000)
48#define MAS1_IND 0x00002000
32#define MAS1_TS 0x00001000 49#define MAS1_TS 0x00001000
33#define MAS1_TSIZE(x) ((x << 8) & 0x00000F00) 50#define MAS1_TSIZE(x) ((x << 7) & 0x00000F80)
34 51
35#define MAS2_EPN 0xFFFFF000 52#define MAS2_EPN 0xFFFFF000
36#define MAS2_X0 0x00000040 53#define MAS2_X0 0x00000040
@@ -40,7 +57,7 @@
40#define MAS2_M 0x00000004 57#define MAS2_M 0x00000004
41#define MAS2_G 0x00000002 58#define MAS2_G 0x00000002
42#define MAS2_E 0x00000001 59#define MAS2_E 0x00000001
43#define MAS2_EPN_MASK(size) (~0 << (2*(size) + 10)) 60#define MAS2_EPN_MASK(size) (~0 << (size + 10))
44#define MAS2_VAL(addr, size, flags) ((addr) & MAS2_EPN_MASK(size) | (flags)) 61#define MAS2_VAL(addr, size, flags) ((addr) & MAS2_EPN_MASK(size) | (flags))
45 62
46#define MAS3_RPN 0xFFFFF000 63#define MAS3_RPN 0xFFFFF000
@@ -56,7 +73,7 @@
56#define MAS3_SR 0x00000001 73#define MAS3_SR 0x00000001
57 74
58#define MAS4_TLBSELD(x) MAS0_TLBSEL(x) 75#define MAS4_TLBSELD(x) MAS0_TLBSEL(x)
59#define MAS4_TIDDSEL 0x000F0000 76#define MAS4_INDD 0x00008000
60#define MAS4_TSIZED(x) MAS1_TSIZE(x) 77#define MAS4_TSIZED(x) MAS1_TSIZE(x)
61#define MAS4_X0D 0x00000040 78#define MAS4_X0D 0x00000040
62#define MAS4_X1D 0x00000020 79#define MAS4_X1D 0x00000020
@@ -68,6 +85,7 @@
68 85
69#define MAS6_SPID0 0x3FFF0000 86#define MAS6_SPID0 0x3FFF0000
70#define MAS6_SPID1 0x00007FFE 87#define MAS6_SPID1 0x00007FFE
88#define MAS6_ISIZE(x) MAS1_TSIZE(x)
71#define MAS6_SAS 0x00000001 89#define MAS6_SAS 0x00000001
72#define MAS6_SPID MAS6_SPID0 90#define MAS6_SPID MAS6_SPID0
73 91
@@ -82,4 +100,4 @@ typedef struct {
82} mm_context_t; 100} mm_context_t;
83#endif /* !__ASSEMBLY__ */ 101#endif /* !__ASSEMBLY__ */
84 102
85#endif /* _ASM_POWERPC_MMU_FSL_BOOKE_H_ */ 103#endif /* _ASM_POWERPC_MMU_BOOK3E_H_ */
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index 6e763991131..5c78079cfa3 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -71,9 +71,9 @@ extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup;
71#elif defined(CONFIG_44x) 71#elif defined(CONFIG_44x)
72/* 44x-style software loaded TLB */ 72/* 44x-style software loaded TLB */
73# include <asm/mmu-44x.h> 73# include <asm/mmu-44x.h>
74#elif defined(CONFIG_FSL_BOOKE) 74#elif defined(CONFIG_PPC_BOOK3E_MMU)
75/* Freescale Book-E software loaded TLB */ 75/* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */
76# include <asm/mmu-fsl-booke.h> 76# include <asm/mmu-book3e.h>
77#elif defined (CONFIG_PPC_8xx) 77#elif defined (CONFIG_PPC_8xx)
78/* Motorola/Freescale 8xx software loaded TLB */ 78/* Motorola/Freescale 8xx software loaded TLB */
79# include <asm/mmu-8xx.h> 79# include <asm/mmu-8xx.h>
diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
index 6f7eb7e00c7..301c646d1a7 100644
--- a/arch/powerpc/kernel/entry_32.S
+++ b/arch/powerpc/kernel/entry_32.S
@@ -63,7 +63,7 @@ debug_transfer_to_handler:
63 63
64 .globl crit_transfer_to_handler 64 .globl crit_transfer_to_handler
65crit_transfer_to_handler: 65crit_transfer_to_handler:
66#ifdef CONFIG_FSL_BOOKE 66#ifdef CONFIG_PPC_BOOK3E_MMU
67 mfspr r0,SPRN_MAS0 67 mfspr r0,SPRN_MAS0
68 stw r0,MAS0(r11) 68 stw r0,MAS0(r11)
69 mfspr r0,SPRN_MAS1 69 mfspr r0,SPRN_MAS1
@@ -78,7 +78,7 @@ crit_transfer_to_handler:
78 mfspr r0,SPRN_MAS7 78 mfspr r0,SPRN_MAS7
79 stw r0,MAS7(r11) 79 stw r0,MAS7(r11)
80#endif /* CONFIG_PHYS_64BIT */ 80#endif /* CONFIG_PHYS_64BIT */
81#endif /* CONFIG_FSL_BOOKE */ 81#endif /* CONFIG_PPC_BOOK3E_MMU */
82#ifdef CONFIG_44x 82#ifdef CONFIG_44x
83 mfspr r0,SPRN_MMUCR 83 mfspr r0,SPRN_MMUCR
84 stw r0,MMUCR(r11) 84 stw r0,MMUCR(r11)
@@ -914,7 +914,7 @@ exc_exit_restart_end:
914 mtspr SPRN_##exc_lvl_srr0,r9; \ 914 mtspr SPRN_##exc_lvl_srr0,r9; \
915 mtspr SPRN_##exc_lvl_srr1,r10; 915 mtspr SPRN_##exc_lvl_srr1,r10;
916 916
917#if defined(CONFIG_FSL_BOOKE) 917#if defined(CONFIG_PPC_BOOK3E_MMU)
918#ifdef CONFIG_PHYS_64BIT 918#ifdef CONFIG_PHYS_64BIT
919#define RESTORE_MAS7 \ 919#define RESTORE_MAS7 \
920 lwz r11,MAS7(r1); \ 920 lwz r11,MAS7(r1); \
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index 64ecb1603a7..4ea6e1a7e4b 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -173,7 +173,7 @@ skpinv: addi r6,r6,1 /* Increment */
173 173
174 /* grab and fixup the RPN */ 174 /* grab and fixup the RPN */
175 mfspr r6,SPRN_MAS1 /* extract MAS1[SIZE] */ 175 mfspr r6,SPRN_MAS1 /* extract MAS1[SIZE] */
176 rlwinm r6,r6,25,27,30 176 rlwinm r6,r6,25,27,31
177 li r8,-1 177 li r8,-1
178 addi r6,r6,10 178 addi r6,r6,10
179 slw r6,r8,r6 /* convert to mask */ 179 slw r6,r8,r6 /* convert to mask */
@@ -199,7 +199,7 @@ skpinv: addi r6,r6,1 /* Increment */
199 xori r6,r4,1 /* Setup TMP mapping in the other Address space */ 199 xori r6,r4,1 /* Setup TMP mapping in the other Address space */
200 slwi r6,r6,12 200 slwi r6,r6,12
201 oris r6,r6,(MAS1_VALID|MAS1_IPROT)@h 201 oris r6,r6,(MAS1_VALID|MAS1_IPROT)@h
202 ori r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_4K))@l 202 ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_4K))@l
203 mtspr SPRN_MAS1,r6 203 mtspr SPRN_MAS1,r6
204 mfspr r6,SPRN_MAS2 204 mfspr r6,SPRN_MAS2
205 li r7,0 /* temp EPN = 0 */ 205 li r7,0 /* temp EPN = 0 */
@@ -257,10 +257,10 @@ skpinv: addi r6,r6,1 /* Increment */
257 lis r6,0x1000 /* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */ 257 lis r6,0x1000 /* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */
258 mtspr SPRN_MAS0,r6 258 mtspr SPRN_MAS0,r6
259 lis r6,(MAS1_VALID|MAS1_IPROT)@h 259 lis r6,(MAS1_VALID|MAS1_IPROT)@h
260 ori r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l 260 ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_64M))@l
261 mtspr SPRN_MAS1,r6 261 mtspr SPRN_MAS1,r6
262 lis r6,MAS2_VAL(PAGE_OFFSET, BOOKE_PAGESZ_64M, M_IF_SMP)@h 262 lis r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@h
263 ori r6,r6,MAS2_VAL(PAGE_OFFSET, BOOKE_PAGESZ_64M, M_IF_SMP)@l 263 ori r6,r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@l
264 mtspr SPRN_MAS2,r6 264 mtspr SPRN_MAS2,r6
265 mtspr SPRN_MAS3,r8 265 mtspr SPRN_MAS3,r8
266 tlbwe 266 tlbwe
@@ -315,7 +315,7 @@ skpinv: addi r6,r6,1 /* Increment */
315 mtspr SPRN_IVPR,r4 315 mtspr SPRN_IVPR,r4
316 316
317 /* Setup the defaults for TLB entries */ 317 /* Setup the defaults for TLB entries */
318 li r2,(MAS4_TSIZED(BOOKE_PAGESZ_4K))@l 318 li r2,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
319#ifdef CONFIG_E200 319#ifdef CONFIG_E200
320 oris r2,r2,MAS4_TLBSELD(1)@h 320 oris r2,r2,MAS4_TLBSELD(1)@h
321#endif 321#endif
@@ -1116,7 +1116,7 @@ __secondary_start:
1116 mtspr SPRN_SPRG3,r4 1116 mtspr SPRN_SPRG3,r4
1117 1117
1118 /* Setup the defaults for TLB entries */ 1118 /* Setup the defaults for TLB entries */
1119 li r4,(MAS4_TSIZED(BOOKE_PAGESZ_4K))@l 1119 li r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
1120 mtspr SPRN_MAS4,r4 1120 mtspr SPRN_MAS4,r4
1121 1121
1122 /* Jump to start_secondary */ 1122 /* Jump to start_secondary */
diff --git a/arch/powerpc/mm/fsl_booke_mmu.c b/arch/powerpc/mm/fsl_booke_mmu.c
index 3d8cf01582f..985b6c361ab 100644
--- a/arch/powerpc/mm/fsl_booke_mmu.c
+++ b/arch/powerpc/mm/fsl_booke_mmu.c
@@ -111,7 +111,7 @@ void settlbcam(int index, unsigned long virt, phys_addr_t phys,
111 unsigned int tsize, lz; 111 unsigned int tsize, lz;
112 112
113 asm ("cntlzw %0,%1" : "=r" (lz) : "r" (size)); 113 asm ("cntlzw %0,%1" : "=r" (lz) : "r" (size));
114 tsize = (21 - lz) / 2; 114 tsize = 21 - lz;
115 115
116#ifdef CONFIG_SMP 116#ifdef CONFIG_SMP
117 if ((flags & _PAGE_NO_CACHE) == 0) 117 if ((flags & _PAGE_NO_CACHE) == 0)
@@ -218,7 +218,7 @@ adjust_total_lowmem(void)
218 p += sprintf(p, "0/"); 218 p += sprintf(p, "0/");
219 p[-1] = '\0'; 219 p[-1] = '\0';
220 220
221 pr_info("Memory CAM mapping: %s Mb, residual: %ldMb\n", buf, 221 pr_info("Memory CAM mapping: %s Mb, residual: %dMb\n", buf,
222 (total_lowmem - __max_low_memory) >> 20); 222 (unsigned int)((total_lowmem - __max_low_memory) >> 20));
223 __initial_memory_limit_addr = memstart_addr + __max_low_memory; 223 __initial_memory_limit_addr = memstart_addr + __max_low_memory;
224} 224}
diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
index e868b5c5072..9428c0e11b2 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
+++ b/arch/powerpc/platforms/Kconfig.cputype
@@ -210,6 +210,10 @@ config PPC_MMU_NOHASH
210 def_bool y 210 def_bool y
211 depends on !PPC_STD_MMU 211 depends on !PPC_STD_MMU
212 212
213config PPC_BOOK3E_MMU
214 def_bool y
215 depends on FSL_BOOKE
216
213config PPC_MM_SLICES 217config PPC_MM_SLICES
214 bool 218 bool
215 default y if HUGETLB_PAGE || (PPC_STD_MMU_64 && PPC_64K_PAGES) 219 default y if HUGETLB_PAGE || (PPC_STD_MMU_64 && PPC_64K_PAGES)
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-22 17:36:07 -0400