aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorSascha Hauer <s.hauer@pengutronix.de>2010-01-14 04:58:10 -0500
committerSascha Hauer <s.hauer@pengutronix.de>2010-01-14 04:58:10 -0500
commit37439a0f123e9eecf7b3920c9f9bd25e35ea8e3e (patch)
treecd6d6433f1c80475f36b94b7432923b4d4b7b660
parentbecc670a1bda8f240a93e45d9794f9f79713ffdb (diff)
parenta8dfb6462a033984b99fee4122fe0799a31f5bb4 (diff)
Merge branch 'imx' of git://git.pengutronix.de/git/ukl/linux-2.6 into mxc-master
Diffstat
-rw-r--r--arch/arm/configs/mx1ads_defconfig742
-rw-r--r--arch/arm/configs/mx27_defconfig2
-rw-r--r--arch/arm/mach-mx1/Makefile4
-rw-r--r--arch/arm/mach-mx1/mach-mx1ads.c (renamed from arch/arm/mach-mx1/mx1ads.c)2
-rw-r--r--arch/arm/mach-mx1/mach-scb9328.c (renamed from arch/arm/mach-mx1/scb9328.c)2
-rw-r--r--arch/arm/mach-mx2/Kconfig8
-rw-r--r--arch/arm/mach-mx2/Makefile20
-rw-r--r--arch/arm/mach-mx2/clock_imx21.c236
-rw-r--r--arch/arm/mach-mx2/clock_imx27.c33
-rw-r--r--arch/arm/mach-mx2/cpu_imx27.c3
-rw-r--r--arch/arm/mach-mx2/crm_regs.h258
-rw-r--r--arch/arm/mach-mx2/mach-cpuimx27.c (renamed from arch/arm/mach-mx2/eukrea_cpuimx27.c)12
-rw-r--r--arch/arm/mach-mx2/mach-imx27lite.c (renamed from arch/arm/mach-mx2/mx27lite.c)4
-rw-r--r--arch/arm/mach-mx2/mach-mx21ads.c (renamed from arch/arm/mach-mx2/mx21ads.c)10
-rw-r--r--arch/arm/mach-mx2/mach-mx27_3ds.c (renamed from arch/arm/mach-mx2/mx27pdk.c)4
-rw-r--r--arch/arm/mach-mx2/mach-mx27ads.c (renamed from arch/arm/mach-mx2/mx27ads.c)6
-rw-r--r--arch/arm/mach-mx2/mach-mxt_td60.c (renamed from arch/arm/mach-mx2/mxt_td60.c)28
-rw-r--r--arch/arm/mach-mx2/mach-pca100.c (renamed from arch/arm/mach-mx2/pca100.c)4
-rw-r--r--arch/arm/mach-mx2/mach-pcm038.c (renamed from arch/arm/mach-mx2/pcm038.c)12
-rw-r--r--arch/arm/mach-mx2/pcm970-baseboard.c4
-rw-r--r--arch/arm/mach-mx25/clock.c2
-rw-r--r--arch/arm/mach-mx25/devices.c19
-rw-r--r--arch/arm/mach-mx25/devices.h1
-rw-r--r--arch/arm/mach-mx25/mx25pdk.c46
-rw-r--r--arch/arm/mach-mx3/Kconfig3
-rw-r--r--arch/arm/mach-mx3/Makefile30
-rw-r--r--arch/arm/mach-mx3/clock-imx31.c (renamed from arch/arm/mach-mx3/clock.c)5
-rw-r--r--arch/arm/mach-mx3/clock-imx35.c5
-rw-r--r--arch/arm/mach-mx3/cpu.c2
-rw-r--r--arch/arm/mach-mx3/crm_regs.h2
-rw-r--r--arch/arm/mach-mx3/iomux-imx31.c (renamed from arch/arm/mach-mx3/iomux.c)2
-rw-r--r--arch/arm/mach-mx3/mach-armadillo5x0.c (renamed from arch/arm/mach-mx3/armadillo5x0.c)12
-rw-r--r--arch/arm/mach-mx3/mach-kzm_arm11_01.c (renamed from arch/arm/mach-mx3/kzmarm11.c)31
-rw-r--r--arch/arm/mach-mx3/mach-mx31_3ds.c (renamed from arch/arm/mach-mx3/mx31pdk.c)15
-rw-r--r--arch/arm/mach-mx3/mach-mx31ads.c (renamed from arch/arm/mach-mx3/mx31ads.c)19
-rw-r--r--arch/arm/mach-mx3/mach-mx31lilly.c (renamed from arch/arm/mach-mx3/mx31lilly.c)8
-rw-r--r--arch/arm/mach-mx3/mach-mx31lite.c (renamed from arch/arm/mach-mx3/mx31lite.c)23
-rw-r--r--arch/arm/mach-mx3/mach-mx31moboard.c (renamed from arch/arm/mach-mx3/mx31moboard.c)11
-rw-r--r--arch/arm/mach-mx3/mach-mx35pdk.c (renamed from arch/arm/mach-mx3/mx35pdk.c)4
-rw-r--r--arch/arm/mach-mx3/mach-pcm037.c (renamed from arch/arm/mach-mx3/pcm037.c)48
-rw-r--r--arch/arm/mach-mx3/mach-pcm037_eet.c (renamed from arch/arm/mach-mx3/pcm037_eet.c)0
-rw-r--r--arch/arm/mach-mx3/mach-pcm043.c (renamed from arch/arm/mach-mx3/pcm043.c)4
-rw-r--r--arch/arm/mach-mx3/mach-qong.c (renamed from arch/arm/mach-mx3/qong.c)18
-rw-r--r--arch/arm/mach-mx3/mm.c5
-rw-r--r--arch/arm/mach-mx3/mx31moboard-devboard.c2
-rw-r--r--arch/arm/mach-mx3/mx31moboard-marxbot.c2
-rw-r--r--arch/arm/plat-mxc/Makefile4
-rw-r--r--arch/arm/plat-mxc/ehci.c4
-rw-r--r--arch/arm/plat-mxc/include/mach/board-kzmarm11.h18
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx31ads.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/hardware.h5
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx25.h58
-rw-r--r--arch/arm/plat-mxc/include/mach/mx1.h6
-rw-r--r--arch/arm/plat-mxc/include/mach/mx21.h13
-rw-r--r--arch/arm/plat-mxc/include/mach/mx25.h25
-rw-r--r--arch/arm/plat-mxc/include/mach/mx27.h32
-rw-r--r--arch/arm/plat-mxc/include/mach/mx2x.h8
-rw-r--r--arch/arm/plat-mxc/include/mach/mx31.h33
-rw-r--r--arch/arm/plat-mxc/include/mach/mx35.h13
-rw-r--r--arch/arm/plat-mxc/include/mach/mx3x.h8
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc.h7
-rw-r--r--arch/arm/plat-mxc/include/mach/uncompress.h3
62 files changed, 669 insertions, 1283 deletions
diff --git a/arch/arm/configs/mx1ads_defconfig b/arch/arm/configs/mx1ads_defconfig
deleted file mode 100644
index 3cabbb6d927..00000000000
--- a/arch/arm/configs/mx1ads_defconfig
+++ /dev/null
@@ -1,742 +0,0 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.12-rc1-bk2
4# Sun Mar 27 02:15:46 2005
5#
6CONFIG_ARM=y
7CONFIG_MMU=y
8CONFIG_UID16=y
9CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_CALIBRATE_DELAY=y
11CONFIG_GENERIC_IOMAP=y
12
13#
14# Code maturity level options
15#
16CONFIG_EXPERIMENTAL=y
17CONFIG_CLEAN_COMPILE=y
18CONFIG_BROKEN_ON_SMP=y
19CONFIG_LOCK_KERNEL=y
20
21#
22# General setup
23#
24CONFIG_LOCALVERSION=""
25CONFIG_SWAP=y
26CONFIG_SYSVIPC=y
27# CONFIG_POSIX_MQUEUE is not set
28# CONFIG_BSD_PROCESS_ACCT is not set
29# CONFIG_SYSCTL is not set
30# CONFIG_AUDIT is not set
31# CONFIG_HOTPLUG is not set
32CONFIG_KOBJECT_UEVENT=y
33# CONFIG_IKCONFIG is not set
34CONFIG_EMBEDDED=y
35# CONFIG_KALLSYMS is not set
36CONFIG_BASE_FULL=y
37CONFIG_FUTEX=y
38CONFIG_EPOLL=y
39CONFIG_CC_OPTIMIZE_FOR_SIZE=y
40CONFIG_SHMEM=y
41CONFIG_CC_ALIGN_FUNCTIONS=0
42CONFIG_CC_ALIGN_LABELS=0
43CONFIG_CC_ALIGN_LOOPS=0
44CONFIG_CC_ALIGN_JUMPS=0
45# CONFIG_TINY_SHMEM is not set
46CONFIG_BASE_SMALL=0
47
48#
49# Loadable module support
50#
51CONFIG_MODULES=y
52CONFIG_MODULE_UNLOAD=y
53# CONFIG_MODULE_FORCE_UNLOAD is not set
54CONFIG_OBSOLETE_MODPARM=y
55# CONFIG_MODVERSIONS is not set
56# CONFIG_MODULE_SRCVERSION_ALL is not set
57CONFIG_KMOD=y
58
59#
60# System Type
61#
62# CONFIG_ARCH_CLPS7500 is not set
63# CONFIG_ARCH_CLPS711X is not set
64# CONFIG_ARCH_CO285 is not set
65# CONFIG_ARCH_EBSA110 is not set
66# CONFIG_ARCH_FOOTBRIDGE is not set
67# CONFIG_ARCH_INTEGRATOR is not set
68# CONFIG_ARCH_IOP3XX is not set
69# CONFIG_ARCH_IXP4XX is not set
70# CONFIG_ARCH_IXP2000 is not set
71# CONFIG_ARCH_L7200 is not set
72# CONFIG_ARCH_PXA is not set
73# CONFIG_ARCH_RPC is not set
74# CONFIG_ARCH_SA1100 is not set
75# CONFIG_ARCH_S3C2410 is not set
76# CONFIG_ARCH_SHARK is not set
77# CONFIG_ARCH_LH7A40X is not set
78# CONFIG_ARCH_OMAP is not set
79# CONFIG_ARCH_VERSATILE is not set
80CONFIG_ARCH_IMX=y
81# CONFIG_ARCH_H720X is not set
82
83#
84# IMX Implementations
85#
86CONFIG_ARCH_MX1ADS=y
87
88#
89# Processor Type
90#
91CONFIG_CPU_ARM920T=y
92CONFIG_CPU_32v4=y
93CONFIG_CPU_ABRT_EV4T=y
94CONFIG_CPU_CACHE_V4WT=y
95CONFIG_CPU_CACHE_VIVT=y
96CONFIG_CPU_COPY_V4WB=y
97CONFIG_CPU_TLB_V4WBI=y
98
99#
100# Processor Features
101#
102# CONFIG_ARM_THUMB is not set
103# CONFIG_CPU_ICACHE_DISABLE is not set
104# CONFIG_CPU_DCACHE_DISABLE is not set
105# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
106
107#
108# Bus support
109#
110CONFIG_ISA=y
111
112#
113# PCCARD (PCMCIA/CardBus) support
114#
115# CONFIG_PCCARD is not set
116
117#
118# Kernel Features
119#
120CONFIG_PREEMPT=y
121# CONFIG_LEDS is not set
122CONFIG_ALIGNMENT_TRAP=y
123
124#
125# Boot options
126#
127CONFIG_ZBOOT_ROM_TEXT=0x0
128CONFIG_ZBOOT_ROM_BSS=0x0
129CONFIG_CMDLINE="console=ttySMX0,57600n8 ip=bootp root=/dev/nfs"
130# CONFIG_XIP_KERNEL is not set
131
132#
133# Floating point emulation
134#
135
136#
137# At least one emulation must be selected
138#
139CONFIG_FPE_NWFPE=y
140CONFIG_FPE_NWFPE_XP=y
141CONFIG_FPE_FASTFPE=y
142
143#
144# Userspace binary formats
145#
146CONFIG_BINFMT_ELF=y
147# CONFIG_BINFMT_AOUT is not set
148# CONFIG_BINFMT_MISC is not set
149# CONFIG_ARTHUR is not set
150
151#
152# Power management options
153#
154# CONFIG_PM is not set
155
156#
157# Device Drivers
158#
159
160#
161# Generic Driver Options
162#
163CONFIG_STANDALONE=y
164CONFIG_PREVENT_FIRMWARE_BUILD=y
165# CONFIG_FW_LOADER is not set
166# CONFIG_DEBUG_DRIVER is not set
167
168#
169# Memory Technology Devices (MTD)
170#
171CONFIG_MTD=y
172# CONFIG_MTD_DEBUG is not set
173# CONFIG_MTD_CONCAT is not set
174CONFIG_MTD_PARTITIONS=y
175# CONFIG_MTD_REDBOOT_PARTS is not set
176# CONFIG_MTD_CMDLINE_PARTS is not set
177# CONFIG_MTD_AFS_PARTS is not set
178
179#
180# User Modules And Translation Layers
181#
182CONFIG_MTD_CHAR=y
183CONFIG_MTD_BLOCK=y
184# CONFIG_FTL is not set
185# CONFIG_NFTL is not set
186# CONFIG_INFTL is not set
187
188#
189# RAM/ROM/Flash chip drivers
190#
191# CONFIG_MTD_CFI is not set
192# CONFIG_MTD_JEDECPROBE is not set
193CONFIG_MTD_MAP_BANK_WIDTH_1=y
194CONFIG_MTD_MAP_BANK_WIDTH_2=y
195CONFIG_MTD_MAP_BANK_WIDTH_4=y
196# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
197# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
198# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
199CONFIG_MTD_CFI_I1=y
200CONFIG_MTD_CFI_I2=y
201# CONFIG_MTD_CFI_I4 is not set
202# CONFIG_MTD_CFI_I8 is not set
203# CONFIG_MTD_RAM is not set
204CONFIG_MTD_ROM=y
205# CONFIG_MTD_ABSENT is not set
206
207#
208# Mapping drivers for chip access
209#
210# CONFIG_MTD_COMPLEX_MAPPINGS is not set
211
212#
213# Self-contained MTD device drivers
214#
215# CONFIG_MTD_SLRAM is not set
216# CONFIG_MTD_PHRAM is not set
217# CONFIG_MTD_MTDRAM is not set
218# CONFIG_MTD_BLKMTD is not set
219# CONFIG_MTD_BLOCK2MTD is not set
220
221#
222# Disk-On-Chip Device Drivers
223#
224# CONFIG_MTD_DOC2000 is not set
225# CONFIG_MTD_DOC2001 is not set
226# CONFIG_MTD_DOC2001PLUS is not set
227
228#
229# NAND Flash Device Drivers
230#
231# CONFIG_MTD_NAND is not set
232
233#
234# Parallel port support
235#
236# CONFIG_PARPORT is not set
237
238#
239# Plug and Play support
240#
241# CONFIG_PNP is not set
242
243#
244# Block devices
245#
246# CONFIG_BLK_DEV_FD is not set
247# CONFIG_BLK_DEV_XD is not set
248# CONFIG_BLK_DEV_COW_COMMON is not set
249CONFIG_BLK_DEV_LOOP=y
250# CONFIG_BLK_DEV_CRYPTOLOOP is not set
251# CONFIG_BLK_DEV_NBD is not set
252# CONFIG_BLK_DEV_RAM is not set
253CONFIG_BLK_DEV_RAM_COUNT=16
254CONFIG_INITRAMFS_SOURCE=""
255# CONFIG_CDROM_PKTCDVD is not set
256
257#
258# IO Schedulers
259#
260CONFIG_IOSCHED_NOOP=y
261# CONFIG_IOSCHED_AS is not set
262CONFIG_IOSCHED_DEADLINE=y
263CONFIG_IOSCHED_CFQ=y
264# CONFIG_ATA_OVER_ETH is not set
265
266#
267# SCSI device support
268#
269# CONFIG_SCSI is not set
270
271#
272# Multi-device support (RAID and LVM)
273#
274# CONFIG_MD is not set
275
276#
277# Fusion MPT device support
278#
279
280#
281# IEEE 1394 (FireWire) support
282#
283
284#
285# I2O device support
286#
287
288#
289# Networking support
290#
291CONFIG_NET=y
292
293#
294# Networking options
295#
296CONFIG_PACKET=m
297CONFIG_PACKET_MMAP=y
298# CONFIG_NETLINK_DEV is not set
299CONFIG_UNIX=y
300# CONFIG_NET_KEY is not set
301CONFIG_INET=y
302# CONFIG_IP_MULTICAST is not set
303# CONFIG_IP_ADVANCED_ROUTER is not set
304CONFIG_IP_PNP=y
305CONFIG_IP_PNP_DHCP=y
306CONFIG_IP_PNP_BOOTP=y
307# CONFIG_IP_PNP_RARP is not set
308# CONFIG_NET_IPIP is not set
309# CONFIG_NET_IPGRE is not set
310# CONFIG_ARPD is not set
311# CONFIG_SYN_COOKIES is not set
312# CONFIG_INET_AH is not set
313# CONFIG_INET_ESP is not set
314# CONFIG_INET_IPCOMP is not set
315# CONFIG_INET_TUNNEL is not set
316CONFIG_IP_TCPDIAG=y
317# CONFIG_IP_TCPDIAG_IPV6 is not set
318# CONFIG_IPV6 is not set
319# CONFIG_NETFILTER is not set
320
321#
322# SCTP Configuration (EXPERIMENTAL)
323#
324# CONFIG_IP_SCTP is not set
325# CONFIG_ATM is not set
326# CONFIG_BRIDGE is not set
327# CONFIG_VLAN_8021Q is not set
328# CONFIG_DECNET is not set
329# CONFIG_LLC2 is not set
330# CONFIG_IPX is not set
331# CONFIG_ATALK is not set
332# CONFIG_X25 is not set
333# CONFIG_LAPB is not set
334# CONFIG_NET_DIVERT is not set
335# CONFIG_ECONET is not set
336# CONFIG_WAN_ROUTER is not set
337
338#
339# QoS and/or fair queueing
340#
341# CONFIG_NET_SCHED is not set
342# CONFIG_NET_CLS_ROUTE is not set
343
344#
345# Network testing
346#
347# CONFIG_NET_PKTGEN is not set
348# CONFIG_NETPOLL is not set
349# CONFIG_NET_POLL_CONTROLLER is not set
350# CONFIG_HAMRADIO is not set
351# CONFIG_IRDA is not set
352# CONFIG_BT is not set
353CONFIG_NETDEVICES=y
354# CONFIG_DUMMY is not set
355# CONFIG_BONDING is not set
356# CONFIG_EQUALIZER is not set
357# CONFIG_TUN is not set
358
359#
360# ARCnet devices
361#
362# CONFIG_ARCNET is not set
363
364#
365# Ethernet (10 or 100Mbit)
366#
367CONFIG_NET_ETHERNET=y
368CONFIG_MII=y
369# CONFIG_NET_VENDOR_3COM is not set
370# CONFIG_LANCE is not set
371# CONFIG_NET_VENDOR_SMC is not set
372# CONFIG_SMC91X is not set
373# CONFIG_NET_VENDOR_RACAL is not set
374# CONFIG_AT1700 is not set
375# CONFIG_DEPCA is not set
376# CONFIG_HP100 is not set
377# CONFIG_NET_ISA is not set
378# CONFIG_NET_PCI is not set
379# CONFIG_NET_POCKET is not set
380
381#
382# Ethernet (1000 Mbit)
383#
384
385#
386# Ethernet (10000 Mbit)
387#
388
389#
390# Token Ring devices
391#
392# CONFIG_TR is not set
393
394#
395# Wireless LAN (non-hamradio)
396#
397# CONFIG_NET_RADIO is not set
398
399#
400# Wan interfaces
401#
402# CONFIG_WAN is not set
403CONFIG_PPP=y
404# CONFIG_PPP_MULTILINK is not set
405CONFIG_PPP_FILTER=y
406CONFIG_PPP_ASYNC=y
407# CONFIG_PPP_SYNC_TTY is not set
408CONFIG_PPP_DEFLATE=y
409CONFIG_PPP_BSDCOMP=y
410# CONFIG_PPPOE is not set
411# CONFIG_SLIP is not set
412# CONFIG_SHAPER is not set
413# CONFIG_NETCONSOLE is not set
414
415#
416# ISDN subsystem
417#
418# CONFIG_ISDN is not set
419
420#
421# Input device support
422#
423# CONFIG_INPUT is not set
424
425#
426# Hardware I/O ports
427#
428# CONFIG_SERIO is not set
429# CONFIG_GAMEPORT is not set
430CONFIG_SOUND_GAMEPORT=y
431
432#
433# Character devices
434#
435# CONFIG_VT is not set
436# CONFIG_SERIAL_NONSTANDARD is not set
437
438#
439# Serial drivers
440#
441# CONFIG_SERIAL_8250 is not set
442
443#
444# Non-8250 serial port support
445#
446CONFIG_SERIAL_IMX=y
447CONFIG_SERIAL_IMX_CONSOLE=y
448CONFIG_SERIAL_CORE=y
449CONFIG_SERIAL_CORE_CONSOLE=y
450CONFIG_UNIX98_PTYS=y
451# CONFIG_LEGACY_PTYS is not set
452
453#
454# IPMI
455#
456# CONFIG_IPMI_HANDLER is not set
457
458#
459# Watchdog Cards
460#
461# CONFIG_WATCHDOG is not set
462# CONFIG_NVRAM is not set
463CONFIG_RTC=m
464# CONFIG_DTLK is not set
465# CONFIG_R3964 is not set
466
467#
468# Ftape, the floppy tape device driver
469#
470# CONFIG_DRM is not set
471# CONFIG_RAW_DRIVER is not set
472
473#
474# TPM devices
475#
476# CONFIG_TCG_TPM is not set
477
478#
479# I2C support
480#
481# CONFIG_I2C is not set
482
483#
484# Misc devices
485#
486
487#
488# Multimedia devices
489#
490# CONFIG_VIDEO_DEV is not set
491
492#
493# Digital Video Broadcasting Devices
494#
495# CONFIG_DVB is not set
496
497#
498# Graphics support
499#
500# CONFIG_FB is not set
501
502#
503# Sound
504#
505# CONFIG_SOUND is not set
506
507#
508# USB support
509#
510CONFIG_USB_ARCH_HAS_HCD=y
511# CONFIG_USB_ARCH_HAS_OHCI is not set
512# CONFIG_USB is not set
513
514#
515# USB Gadget Support
516#
517# CONFIG_USB_GADGET is not set
518
519#
520# MMC/SD Card support
521#
522# CONFIG_MMC is not set
523
524#
525# File systems
526#
527# CONFIG_EXT2_FS is not set
528# CONFIG_EXT3_FS is not set
529# CONFIG_JBD is not set
530# CONFIG_REISERFS_FS is not set
531# CONFIG_JFS_FS is not set
532
533#
534# XFS support
535#
536# CONFIG_XFS_FS is not set
537# CONFIG_MINIX_FS is not set
538# CONFIG_ROMFS_FS is not set
539# CONFIG_QUOTA is not set
540CONFIG_DNOTIFY=y
541# CONFIG_AUTOFS_FS is not set
542# CONFIG_AUTOFS4_FS is not set
543
544#
545# CD-ROM/DVD Filesystems
546#
547# CONFIG_ISO9660_FS is not set
548# CONFIG_UDF_FS is not set
549
550#
551# DOS/FAT/NT Filesystems
552#
553CONFIG_FAT_FS=y
554CONFIG_MSDOS_FS=y
555CONFIG_VFAT_FS=y
556CONFIG_FAT_DEFAULT_CODEPAGE=437
557CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
558# CONFIG_NTFS_FS is not set
559
560#
561# Pseudo filesystems
562#
563CONFIG_PROC_FS=y
564CONFIG_SYSFS=y
565CONFIG_DEVFS_FS=y
566CONFIG_DEVFS_MOUNT=y
567# CONFIG_DEVFS_DEBUG is not set
568# CONFIG_DEVPTS_FS_XATTR is not set
569CONFIG_TMPFS=y
570# CONFIG_TMPFS_XATTR is not set
571# CONFIG_HUGETLB_PAGE is not set
572CONFIG_RAMFS=y
573
574#
575# Miscellaneous filesystems
576#
577# CONFIG_ADFS_FS is not set
578# CONFIG_AFFS_FS is not set
579# CONFIG_HFS_FS is not set
580# CONFIG_HFSPLUS_FS is not set
581# CONFIG_BEFS_FS is not set
582# CONFIG_BFS_FS is not set
583# CONFIG_EFS_FS is not set
584# CONFIG_JFFS_FS is not set
585CONFIG_JFFS2_FS=y
586CONFIG_JFFS2_FS_DEBUG=0
587# CONFIG_JFFS2_FS_NAND is not set
588# CONFIG_JFFS2_FS_NOR_ECC is not set
589# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
590CONFIG_JFFS2_ZLIB=y
591CONFIG_JFFS2_RTIME=y
592# CONFIG_JFFS2_RUBIN is not set
593CONFIG_CRAMFS=y
594# CONFIG_VXFS_FS is not set
595# CONFIG_HPFS_FS is not set
596# CONFIG_QNX4FS_FS is not set
597# CONFIG_SYSV_FS is not set
598# CONFIG_UFS_FS is not set
599
600#
601# Network File Systems
602#
603CONFIG_NFS_FS=y
604CONFIG_NFS_V3=y
605# CONFIG_NFS_V4 is not set
606# CONFIG_NFS_DIRECTIO is not set
607# CONFIG_NFSD is not set
608CONFIG_ROOT_NFS=y
609CONFIG_LOCKD=y
610CONFIG_LOCKD_V4=y
611CONFIG_SUNRPC=y
612# CONFIG_RPCSEC_GSS_KRB5 is not set
613# CONFIG_RPCSEC_GSS_SPKM3 is not set
614# CONFIG_SMB_FS is not set
615# CONFIG_CIFS is not set
616# CONFIG_NCP_FS is not set
617# CONFIG_CODA_FS is not set
618# CONFIG_AFS_FS is not set
619
620#
621# Partition Types
622#
623# CONFIG_PARTITION_ADVANCED is not set
624CONFIG_MSDOS_PARTITION=y
625
626#
627# Native Language Support
628#
629CONFIG_NLS=y
630CONFIG_NLS_DEFAULT="iso8859-1"
631# CONFIG_NLS_CODEPAGE_437 is not set
632# CONFIG_NLS_CODEPAGE_737 is not set
633# CONFIG_NLS_CODEPAGE_775 is not set
634# CONFIG_NLS_CODEPAGE_850 is not set
635# CONFIG_NLS_CODEPAGE_852 is not set
636# CONFIG_NLS_CODEPAGE_855 is not set
637# CONFIG_NLS_CODEPAGE_857 is not set
638# CONFIG_NLS_CODEPAGE_860 is not set
639# CONFIG_NLS_CODEPAGE_861 is not set
640# CONFIG_NLS_CODEPAGE_862 is not set
641# CONFIG_NLS_CODEPAGE_863 is not set
642# CONFIG_NLS_CODEPAGE_864 is not set
643# CONFIG_NLS_CODEPAGE_865 is not set
644# CONFIG_NLS_CODEPAGE_866 is not set
645# CONFIG_NLS_CODEPAGE_869 is not set
646# CONFIG_NLS_CODEPAGE_936 is not set
647# CONFIG_NLS_CODEPAGE_950 is not set
648# CONFIG_NLS_CODEPAGE_932 is not set
649# CONFIG_NLS_CODEPAGE_949 is not set
650# CONFIG_NLS_CODEPAGE_874 is not set
651# CONFIG_NLS_ISO8859_8 is not set
652# CONFIG_NLS_CODEPAGE_1250 is not set
653# CONFIG_NLS_CODEPAGE_1251 is not set
654# CONFIG_NLS_ASCII is not set
655# CONFIG_NLS_ISO8859_1 is not set
656# CONFIG_NLS_ISO8859_2 is not set
657# CONFIG_NLS_ISO8859_3 is not set
658# CONFIG_NLS_ISO8859_4 is not set
659# CONFIG_NLS_ISO8859_5 is not set
660# CONFIG_NLS_ISO8859_6 is not set
661# CONFIG_NLS_ISO8859_7 is not set
662# CONFIG_NLS_ISO8859_9 is not set
663# CONFIG_NLS_ISO8859_13 is not set
664# CONFIG_NLS_ISO8859_14 is not set
665# CONFIG_NLS_ISO8859_15 is not set
666# CONFIG_NLS_KOI8_R is not set
667# CONFIG_NLS_KOI8_U is not set
668# CONFIG_NLS_UTF8 is not set
669
670#
671# Profiling support
672#
673# CONFIG_PROFILING is not set
674
675#
676# Kernel hacking
677#
678# CONFIG_PRINTK_TIME is not set
679CONFIG_DEBUG_KERNEL=y
680CONFIG_MAGIC_SYSRQ=y
681CONFIG_LOG_BUF_SHIFT=14
682# CONFIG_SCHEDSTATS is not set
683# CONFIG_DEBUG_SLAB is not set
684CONFIG_DEBUG_PREEMPT=y
685# CONFIG_DEBUG_SPINLOCK is not set
686# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
687# CONFIG_DEBUG_KOBJECT is not set
688CONFIG_DEBUG_BUGVERBOSE=y
689CONFIG_DEBUG_INFO=y
690# CONFIG_DEBUG_FS is not set
691CONFIG_FRAME_POINTER=y
692CONFIG_DEBUG_USER=y
693CONFIG_DEBUG_ERRORS=y
694# CONFIG_DEBUG_LL is not set
695
696#
697# Security options
698#
699# CONFIG_KEYS is not set
700# CONFIG_SECURITY is not set
701
702#
703# Cryptographic options
704#
705CONFIG_CRYPTO=y
706# CONFIG_CRYPTO_HMAC is not set
707# CONFIG_CRYPTO_NULL is not set
708# CONFIG_CRYPTO_MD4 is not set
709# CONFIG_CRYPTO_MD5 is not set
710# CONFIG_CRYPTO_SHA1 is not set
711# CONFIG_CRYPTO_SHA256 is not set
712# CONFIG_CRYPTO_SHA512 is not set
713# CONFIG_CRYPTO_WP512 is not set
714# CONFIG_CRYPTO_TGR192 is not set
715# CONFIG_CRYPTO_DES is not set
716# CONFIG_CRYPTO_BLOWFISH is not set
717# CONFIG_CRYPTO_TWOFISH is not set
718# CONFIG_CRYPTO_SERPENT is not set
719# CONFIG_CRYPTO_AES is not set
720# CONFIG_CRYPTO_CAST5 is not set
721# CONFIG_CRYPTO_CAST6 is not set
722# CONFIG_CRYPTO_TEA is not set
723# CONFIG_CRYPTO_ARC4 is not set
724# CONFIG_CRYPTO_KHAZAD is not set
725# CONFIG_CRYPTO_ANUBIS is not set
726# CONFIG_CRYPTO_DEFLATE is not set
727# CONFIG_CRYPTO_MICHAEL_MIC is not set
728# CONFIG_CRYPTO_CRC32C is not set
729# CONFIG_CRYPTO_TEST is not set
730
731#
732# Hardware crypto devices
733#
734
735#
736# Library routines
737#
738CONFIG_CRC_CCITT=y
739CONFIG_CRC32=y
740# CONFIG_LIBCRC32C is not set
741CONFIG_ZLIB_INFLATE=y
742CONFIG_ZLIB_DEFLATE=y
diff --git a/arch/arm/configs/mx27_defconfig b/arch/arm/configs/mx27_defconfig
index edfdd6faf80..b4c1366e9e0 100644
--- a/arch/arm/configs/mx27_defconfig
+++ b/arch/arm/configs/mx27_defconfig
@@ -200,7 +200,7 @@ CONFIG_MACH_MX27ADS=y
200CONFIG_MACH_PCM038=y 200CONFIG_MACH_PCM038=y
201CONFIG_MACH_PCM970_BASEBOARD=y 201CONFIG_MACH_PCM970_BASEBOARD=y
202CONFIG_MACH_MX27_3DS=y 202CONFIG_MACH_MX27_3DS=y
203CONFIG_MACH_MX27LITE=y 203CONFIG_MACH_IMX27LITE=y
204CONFIG_MXC_IRQ_PRIOR=y 204CONFIG_MXC_IRQ_PRIOR=y
205CONFIG_MXC_PWM=y 205CONFIG_MXC_PWM=y
206 206
diff --git a/arch/arm/mach-mx1/Makefile b/arch/arm/mach-mx1/Makefile
index 7f86fe073ec..297d17210e1 100644
--- a/arch/arm/mach-mx1/Makefile
+++ b/arch/arm/mach-mx1/Makefile
@@ -10,5 +10,5 @@ obj-y += generic.o clock.o devices.o
10obj-$(CONFIG_MX1_VIDEO) += ksym_mx1.o mx1_camera_fiq.o 10obj-$(CONFIG_MX1_VIDEO) += ksym_mx1.o mx1_camera_fiq.o
11 11
12# Specific board support 12# Specific board support
13obj-$(CONFIG_ARCH_MX1ADS) += mx1ads.o 13obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o
14obj-$(CONFIG_MACH_SCB9328) += scb9328.o \ No newline at end of file 14obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o
diff --git a/arch/arm/mach-mx1/mx1ads.c b/arch/arm/mach-mx1/mach-mx1ads.c
index 30f04e56faf..a39433afb51 100644
--- a/arch/arm/mach-mx1/mx1ads.c
+++ b/arch/arm/mach-mx1/mach-mx1ads.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * arch/arm/mach-imx/mx1ads.c 2 * arch/arm/mach-imx/mach-mx1ads.c
3 * 3 *
4 * Initially based on: 4 * Initially based on:
5 * linux-2.6.7-imx/arch/arm/mach-imx/scb9328.c 5 * linux-2.6.7-imx/arch/arm/mach-imx/scb9328.c
diff --git a/arch/arm/mach-mx1/scb9328.c b/arch/arm/mach-mx1/mach-scb9328.c
index 325d98df605..b9530d76e99 100644
--- a/arch/arm/mach-mx1/scb9328.c
+++ b/arch/arm/mach-mx1/mach-scb9328.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/arm/mach-mx1/scb9328.c 2 * linux/arch/arm/mach-mx1/mach-scb9328.c
3 * 3 *
4 * Copyright (c) 2004 Sascha Hauer <saschahauer@web.de> 4 * Copyright (c) 2004 Sascha Hauer <saschahauer@web.de>
5 * Copyright (c) 2006-2008 Juergen Beisert <jbeisert@netscape.net> 5 * Copyright (c) 2006-2008 Juergen Beisert <jbeisert@netscape.net>
diff --git a/arch/arm/mach-mx2/Kconfig b/arch/arm/mach-mx2/Kconfig
index b96c6a38936..7bc797c1c3a 100644
--- a/arch/arm/mach-mx2/Kconfig
+++ b/arch/arm/mach-mx2/Kconfig
@@ -55,7 +55,7 @@ config MACH_PCM970_BASEBOARD
55 55
56endchoice 56endchoice
57 57
58config MACH_EUKREA_CPUIMX27 58config MACH_CPUIMX27
59 bool "Eukrea CPUIMX27 module" 59 bool "Eukrea CPUIMX27 module"
60 depends on MACH_MX27 60 depends on MACH_MX27
61 help 61 help
@@ -64,14 +64,14 @@ config MACH_EUKREA_CPUIMX27
64 64
65config MACH_EUKREA_CPUIMX27_USESDHC2 65config MACH_EUKREA_CPUIMX27_USESDHC2
66 bool "CPUIMX27 integrates SDHC2 module" 66 bool "CPUIMX27 integrates SDHC2 module"
67 depends on MACH_EUKREA_CPUIMX27 67 depends on MACH_CPUIMX27
68 help 68 help
69 This adds support for the internal SDHC2 used on CPUIMX27 used 69 This adds support for the internal SDHC2 used on CPUIMX27 used
70 for wifi or eMMC. 70 for wifi or eMMC.
71 71
72choice 72choice
73 prompt "Baseboard" 73 prompt "Baseboard"
74 depends on MACH_EUKREA_CPUIMX27 74 depends on MACH_CPUIMX27
75 default MACH_EUKREA_MBIMX27_BASEBOARD 75 default MACH_EUKREA_MBIMX27_BASEBOARD
76 76
77config MACH_EUKREA_MBIMX27_BASEBOARD 77config MACH_EUKREA_MBIMX27_BASEBOARD
@@ -90,7 +90,7 @@ config MACH_MX27_3DS
90 Include support for MX27PDK platform. This includes specific 90 Include support for MX27PDK platform. This includes specific
91 configurations for the board and its peripherals. 91 configurations for the board and its peripherals.
92 92
93config MACH_MX27LITE 93config MACH_IMX27LITE
94 bool "LogicPD MX27 LITEKIT platform" 94 bool "LogicPD MX27 LITEKIT platform"
95 depends on MACH_MX27 95 depends on MACH_MX27
96 help 96 help
diff --git a/arch/arm/mach-mx2/Makefile b/arch/arm/mach-mx2/Makefile
index 52aca0aaf9b..a9c94e39e32 100644
--- a/arch/arm/mach-mx2/Makefile
+++ b/arch/arm/mach-mx2/Makefile
@@ -5,20 +5,22 @@
5# Object file lists. 5# Object file lists.
6 6
7obj-y := generic.o devices.o serial.o 7obj-y := generic.o devices.o serial.o
8CFLAGS_generic.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
9CFLAGS_devices.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
10CFLAGS_serial.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
8 11
9obj-$(CONFIG_MACH_MX21) += clock_imx21.o 12obj-$(CONFIG_MACH_MX21) += clock_imx21.o
10 13
11obj-$(CONFIG_MACH_MX27) += cpu_imx27.o 14obj-$(CONFIG_MACH_MX27) += cpu_imx27.o
12obj-$(CONFIG_MACH_MX27) += clock_imx27.o 15obj-$(CONFIG_MACH_MX27) += clock_imx27.o
13 16
14obj-$(CONFIG_MACH_MX21ADS) += mx21ads.o 17obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
15obj-$(CONFIG_MACH_MX27ADS) += mx27ads.o 18obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
16obj-$(CONFIG_MACH_PCM038) += pcm038.o 19obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o
17obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o 20obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
18obj-$(CONFIG_MACH_MX27_3DS) += mx27pdk.o 21obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o
19obj-$(CONFIG_MACH_MX27LITE) += mx27lite.o 22obj-$(CONFIG_MACH_IMX27LITE) += mach-imx27lite.o
20obj-$(CONFIG_MACH_EUKREA_CPUIMX27) += eukrea_cpuimx27.o 23obj-$(CONFIG_MACH_CPUIMX27) += mach-cpuimx27.o
21obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o 24obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o
22obj-$(CONFIG_MACH_PCA100) += pca100.o 25obj-$(CONFIG_MACH_PCA100) += mach-pca100.o
23obj-$(CONFIG_MACH_MXT_TD60) += mxt_td60.o 26obj-$(CONFIG_MACH_MXT_TD60) += mach-mxt_td60.o
24
diff --git a/arch/arm/mach-mx2/clock_imx21.c b/arch/arm/mach-mx2/clock_imx21.c
index 91901b5d56c..8974faf9cef 100644
--- a/arch/arm/mach-mx2/clock_imx21.c
+++ b/arch/arm/mach-mx2/clock_imx21.c
@@ -23,11 +23,242 @@
23#include <linux/module.h> 23#include <linux/module.h>
24 24
25#include <mach/clock.h> 25#include <mach/clock.h>
26#include <mach/hardware.h>
26#include <mach/common.h> 27#include <mach/common.h>
27#include <asm/clkdev.h> 28#include <asm/clkdev.h>
28#include <asm/div64.h> 29#include <asm/div64.h>
29 30
30#include "crm_regs.h" 31#define IO_ADDR_CCM(off) (MX21_IO_ADDRESS(MX21_CCM_BASE_ADDR + (off)))
32
33/* Register offsets */
34#define CCM_CSCR IO_ADDR_CCM(0x0)
35#define CCM_MPCTL0 IO_ADDR_CCM(0x4)
36#define CCM_MPCTL1 IO_ADDR_CCM(0x8)
37#define CCM_SPCTL0 IO_ADDR_CCM(0xc)
38#define CCM_SPCTL1 IO_ADDR_CCM(0x10)
39#define CCM_OSC26MCTL IO_ADDR_CCM(0x14)
40#define CCM_PCDR0 IO_ADDR_CCM(0x18)
41#define CCM_PCDR1 IO_ADDR_CCM(0x1c)
42#define CCM_PCCR0 IO_ADDR_CCM(0x20)
43#define CCM_PCCR1 IO_ADDR_CCM(0x24)
44#define CCM_CCSR IO_ADDR_CCM(0x28)
45#define CCM_PMCTL IO_ADDR_CCM(0x2c)
46#define CCM_PMCOUNT IO_ADDR_CCM(0x30)
47#define CCM_WKGDCTL IO_ADDR_CCM(0x34)
48
49#define CCM_CSCR_PRESC_OFFSET 29
50#define CCM_CSCR_PRESC_MASK (0x7 << CCM_CSCR_PRESC_OFFSET)
51
52#define CCM_CSCR_USB_OFFSET 26
53#define CCM_CSCR_USB_MASK (0x7 << CCM_CSCR_USB_OFFSET)
54#define CCM_CSCR_SD_OFFSET 24
55#define CCM_CSCR_SD_MASK (0x3 << CCM_CSCR_SD_OFFSET)
56#define CCM_CSCR_SPLLRES (1 << 22)
57#define CCM_CSCR_MPLLRES (1 << 21)
58#define CCM_CSCR_SSI2_OFFSET 20
59#define CCM_CSCR_SSI2 (1 << CCM_CSCR_SSI2_OFFSET)
60#define CCM_CSCR_SSI1_OFFSET 19
61#define CCM_CSCR_SSI1 (1 << CCM_CSCR_SSI1_OFFSET)
62#define CCM_CSCR_FIR_OFFSET 18
63#define CCM_CSCR_FIR (1 << CCM_CSCR_FIR_OFFSET)
64#define CCM_CSCR_SP (1 << 17)
65#define CCM_CSCR_MCU (1 << 16)
66#define CCM_CSCR_BCLK_OFFSET 10
67#define CCM_CSCR_BCLK_MASK (0xf << CCM_CSCR_BCLK_OFFSET)
68#define CCM_CSCR_IPDIV_OFFSET 9
69#define CCM_CSCR_IPDIV (1 << CCM_CSCR_IPDIV_OFFSET)
70
71#define CCM_CSCR_OSC26MDIV (1 << 4)
72#define CCM_CSCR_OSC26M (1 << 3)
73#define CCM_CSCR_FPM (1 << 2)
74#define CCM_CSCR_SPEN (1 << 1)
75#define CCM_CSCR_MPEN 1
76
77#define CCM_MPCTL0_CPLM (1 << 31)
78#define CCM_MPCTL0_PD_OFFSET 26
79#define CCM_MPCTL0_PD_MASK (0xf << 26)
80#define CCM_MPCTL0_MFD_OFFSET 16
81#define CCM_MPCTL0_MFD_MASK (0x3ff << 16)
82#define CCM_MPCTL0_MFI_OFFSET 10
83#define CCM_MPCTL0_MFI_MASK (0xf << 10)
84#define CCM_MPCTL0_MFN_OFFSET 0
85#define CCM_MPCTL0_MFN_MASK 0x3ff
86
87#define CCM_MPCTL1_LF (1 << 15)
88#define CCM_MPCTL1_BRMO (1 << 6)
89
90#define CCM_SPCTL0_CPLM (1 << 31)
91#define CCM_SPCTL0_PD_OFFSET 26
92#define CCM_SPCTL0_PD_MASK (0xf << 26)
93#define CCM_SPCTL0_MFD_OFFSET 16
94#define CCM_SPCTL0_MFD_MASK (0x3ff << 16)
95#define CCM_SPCTL0_MFI_OFFSET 10
96#define CCM_SPCTL0_MFI_MASK (0xf << 10)
97#define CCM_SPCTL0_MFN_OFFSET 0
98#define CCM_SPCTL0_MFN_MASK 0x3ff
99
100#define CCM_SPCTL1_LF (1 << 15)
101#define CCM_SPCTL1_BRMO (1 << 6)
102
103#define CCM_OSC26MCTL_PEAK_OFFSET 16
104#define CCM_OSC26MCTL_PEAK_MASK (0x3 << 16)
105#define CCM_OSC26MCTL_AGC_OFFSET 8
106#define CCM_OSC26MCTL_AGC_MASK (0x3f << 8)
107#define CCM_OSC26MCTL_ANATEST_OFFSET 0
108#define CCM_OSC26MCTL_ANATEST_MASK 0x3f
109
110#define CCM_PCDR0_SSI2BAUDDIV_OFFSET 26
111#define CCM_PCDR0_SSI2BAUDDIV_MASK (0x3f << 26)
112#define CCM_PCDR0_SSI1BAUDDIV_OFFSET 16
113#define CCM_PCDR0_SSI1BAUDDIV_MASK (0x3f << 16)
114#define CCM_PCDR0_NFCDIV_OFFSET 12
115#define CCM_PCDR0_NFCDIV_MASK (0xf << 12)
116#define CCM_PCDR0_48MDIV_OFFSET 5
117#define CCM_PCDR0_48MDIV_MASK (0x7 << CCM_PCDR0_48MDIV_OFFSET)
118#define CCM_PCDR0_FIRIDIV_OFFSET 0
119#define CCM_PCDR0_FIRIDIV_MASK 0x1f
120#define CCM_PCDR1_PERDIV4_OFFSET 24
121#define CCM_PCDR1_PERDIV4_MASK (0x3f << 24)
122#define CCM_PCDR1_PERDIV3_OFFSET 16
123#define CCM_PCDR1_PERDIV3_MASK (0x3f << 16)
124#define CCM_PCDR1_PERDIV2_OFFSET 8
125#define CCM_PCDR1_PERDIV2_MASK (0x3f << 8)
126#define CCM_PCDR1_PERDIV1_OFFSET 0
127#define CCM_PCDR1_PERDIV1_MASK 0x3f
128
129#define CCM_PCCR_HCLK_CSI_OFFSET 31
130#define CCM_PCCR_HCLK_CSI_REG CCM_PCCR0
131#define CCM_PCCR_HCLK_DMA_OFFSET 30
132#define CCM_PCCR_HCLK_DMA_REG CCM_PCCR0
133#define CCM_PCCR_HCLK_BROM_OFFSET 28
134#define CCM_PCCR_HCLK_BROM_REG CCM_PCCR0
135#define CCM_PCCR_HCLK_EMMA_OFFSET 27
136#define CCM_PCCR_HCLK_EMMA_REG CCM_PCCR0
137#define CCM_PCCR_HCLK_LCDC_OFFSET 26
138#define CCM_PCCR_HCLK_LCDC_REG CCM_PCCR0
139#define CCM_PCCR_HCLK_SLCDC_OFFSET 25
140#define CCM_PCCR_HCLK_SLCDC_REG CCM_PCCR0
141#define CCM_PCCR_HCLK_USBOTG_OFFSET 24
142#define CCM_PCCR_HCLK_USBOTG_REG CCM_PCCR0
143#define CCM_PCCR_HCLK_BMI_OFFSET 23
144#define CCM_PCCR_BMI_MASK (1 << CCM_PCCR_BMI_MASK)
145#define CCM_PCCR_HCLK_BMI_REG CCM_PCCR0
146#define CCM_PCCR_PERCLK4_OFFSET 22
147#define CCM_PCCR_PERCLK4_REG CCM_PCCR0
148#define CCM_PCCR_SLCDC_OFFSET 21
149#define CCM_PCCR_SLCDC_REG CCM_PCCR0
150#define CCM_PCCR_FIRI_BAUD_OFFSET 20
151#define CCM_PCCR_FIRI_BAUD_MASK (1 << CCM_PCCR_FIRI_BAUD_MASK)
152#define CCM_PCCR_FIRI_BAUD_REG CCM_PCCR0
153#define CCM_PCCR_NFC_OFFSET 19
154#define CCM_PCCR_NFC_REG CCM_PCCR0
155#define CCM_PCCR_LCDC_OFFSET 18
156#define CCM_PCCR_LCDC_REG CCM_PCCR0
157#define CCM_PCCR_SSI1_BAUD_OFFSET 17
158#define CCM_PCCR_SSI1_BAUD_REG CCM_PCCR0
159#define CCM_PCCR_SSI2_BAUD_OFFSET 16
160#define CCM_PCCR_SSI2_BAUD_REG CCM_PCCR0
161#define CCM_PCCR_EMMA_OFFSET 15
162#define CCM_PCCR_EMMA_REG CCM_PCCR0
163#define CCM_PCCR_USBOTG_OFFSET 14
164#define CCM_PCCR_USBOTG_REG CCM_PCCR0
165#define CCM_PCCR_DMA_OFFSET 13
166#define CCM_PCCR_DMA_REG CCM_PCCR0
167#define CCM_PCCR_I2C1_OFFSET 12
168#define CCM_PCCR_I2C1_REG CCM_PCCR0
169#define CCM_PCCR_GPIO_OFFSET 11
170#define CCM_PCCR_GPIO_REG CCM_PCCR0
171#define CCM_PCCR_SDHC2_OFFSET 10
172#define CCM_PCCR_SDHC2_REG CCM_PCCR0
173#define CCM_PCCR_SDHC1_OFFSET 9
174#define CCM_PCCR_SDHC1_REG CCM_PCCR0
175#define CCM_PCCR_FIRI_OFFSET 8
176#define CCM_PCCR_FIRI_MASK (1 << CCM_PCCR_BAUD_MASK)
177#define CCM_PCCR_FIRI_REG CCM_PCCR0
178#define CCM_PCCR_SSI2_IPG_OFFSET 7
179#define CCM_PCCR_SSI2_REG CCM_PCCR0
180#define CCM_PCCR_SSI1_IPG_OFFSET 6
181#define CCM_PCCR_SSI1_REG CCM_PCCR0
182#define CCM_PCCR_CSPI2_OFFSET 5
183#define CCM_PCCR_CSPI2_REG CCM_PCCR0
184#define CCM_PCCR_CSPI1_OFFSET 4
185#define CCM_PCCR_CSPI1_REG CCM_PCCR0
186#define CCM_PCCR_UART4_OFFSET 3
187#define CCM_PCCR_UART4_REG CCM_PCCR0
188#define CCM_PCCR_UART3_OFFSET 2
189#define CCM_PCCR_UART3_REG CCM_PCCR0
190#define CCM_PCCR_UART2_OFFSET 1
191#define CCM_PCCR_UART2_REG CCM_PCCR0
192#define CCM_PCCR_UART1_OFFSET 0
193#define CCM_PCCR_UART1_REG CCM_PCCR0
194
195#define CCM_PCCR_OWIRE_OFFSET 31
196#define CCM_PCCR_OWIRE_REG CCM_PCCR1
197#define CCM_PCCR_KPP_OFFSET 30
198#define CCM_PCCR_KPP_REG CCM_PCCR1
199#define CCM_PCCR_RTC_OFFSET 29
200#define CCM_PCCR_RTC_REG CCM_PCCR1
201#define CCM_PCCR_PWM_OFFSET 28
202#define CCM_PCCR_PWM_REG CCM_PCCR1
203#define CCM_PCCR_GPT3_OFFSET 27
204#define CCM_PCCR_GPT3_REG CCM_PCCR1
205#define CCM_PCCR_GPT2_OFFSET 26
206#define CCM_PCCR_GPT2_REG CCM_PCCR1
207#define CCM_PCCR_GPT1_OFFSET 25
208#define CCM_PCCR_GPT1_REG CCM_PCCR1
209#define CCM_PCCR_WDT_OFFSET 24
210#define CCM_PCCR_WDT_REG CCM_PCCR1
211#define CCM_PCCR_CSPI3_OFFSET 23
212#define CCM_PCCR_CSPI3_REG CCM_PCCR1
213
214#define CCM_PCCR_CSPI1_MASK (1 << CCM_PCCR_CSPI1_OFFSET)
215#define CCM_PCCR_CSPI2_MASK (1 << CCM_PCCR_CSPI2_OFFSET)
216#define CCM_PCCR_CSPI3_MASK (1 << CCM_PCCR_CSPI3_OFFSET)
217#define CCM_PCCR_DMA_MASK (1 << CCM_PCCR_DMA_OFFSET)
218#define CCM_PCCR_EMMA_MASK (1 << CCM_PCCR_EMMA_OFFSET)
219#define CCM_PCCR_GPIO_MASK (1 << CCM_PCCR_GPIO_OFFSET)
220#define CCM_PCCR_GPT1_MASK (1 << CCM_PCCR_GPT1_OFFSET)
221#define CCM_PCCR_GPT2_MASK (1 << CCM_PCCR_GPT2_OFFSET)
222#define CCM_PCCR_GPT3_MASK (1 << CCM_PCCR_GPT3_OFFSET)
223#define CCM_PCCR_HCLK_BROM_MASK (1 << CCM_PCCR_HCLK_BROM_OFFSET)
224#define CCM_PCCR_HCLK_CSI_MASK (1 << CCM_PCCR_HCLK_CSI_OFFSET)
225#define CCM_PCCR_HCLK_DMA_MASK (1 << CCM_PCCR_HCLK_DMA_OFFSET)
226#define CCM_PCCR_HCLK_EMMA_MASK (1 << CCM_PCCR_HCLK_EMMA_OFFSET)
227#define CCM_PCCR_HCLK_LCDC_MASK (1 << CCM_PCCR_HCLK_LCDC_OFFSET)
228#define CCM_PCCR_HCLK_SLCDC_MASK (1 << CCM_PCCR_HCLK_SLCDC_OFFSET)
229#define CCM_PCCR_HCLK_USBOTG_MASK (1 << CCM_PCCR_HCLK_USBOTG_OFFSET)
230#define CCM_PCCR_I2C1_MASK (1 << CCM_PCCR_I2C1_OFFSET)
231#define CCM_PCCR_KPP_MASK (1 << CCM_PCCR_KPP_OFFSET)
232#define CCM_PCCR_LCDC_MASK (1 << CCM_PCCR_LCDC_OFFSET)
233#define CCM_PCCR_NFC_MASK (1 << CCM_PCCR_NFC_OFFSET)
234#define CCM_PCCR_OWIRE_MASK (1 << CCM_PCCR_OWIRE_OFFSET)
235#define CCM_PCCR_PERCLK4_MASK (1 << CCM_PCCR_PERCLK4_OFFSET)
236#define CCM_PCCR_PWM_MASK (1 << CCM_PCCR_PWM_OFFSET)
237#define CCM_PCCR_RTC_MASK (1 << CCM_PCCR_RTC_OFFSET)
238#define CCM_PCCR_SDHC1_MASK (1 << CCM_PCCR_SDHC1_OFFSET)
239#define CCM_PCCR_SDHC2_MASK (1 << CCM_PCCR_SDHC2_OFFSET)
240#define CCM_PCCR_SLCDC_MASK (1 << CCM_PCCR_SLCDC_OFFSET)
241#define CCM_PCCR_SSI1_BAUD_MASK (1 << CCM_PCCR_SSI1_BAUD_OFFSET)
242#define CCM_PCCR_SSI1_IPG_MASK (1 << CCM_PCCR_SSI1_IPG_OFFSET)
243#define CCM_PCCR_SSI2_BAUD_MASK (1 << CCM_PCCR_SSI2_BAUD_OFFSET)
244#define CCM_PCCR_SSI2_IPG_MASK (1 << CCM_PCCR_SSI2_IPG_OFFSET)
245#define CCM_PCCR_UART1_MASK (1 << CCM_PCCR_UART1_OFFSET)
246#define CCM_PCCR_UART2_MASK (1 << CCM_PCCR_UART2_OFFSET)
247#define CCM_PCCR_UART3_MASK (1 << CCM_PCCR_UART3_OFFSET)
248#define CCM_PCCR_UART4_MASK (1 << CCM_PCCR_UART4_OFFSET)
249#define CCM_PCCR_USBOTG_MASK (1 << CCM_PCCR_USBOTG_OFFSET)
250#define CCM_PCCR_WDT_MASK (1 << CCM_PCCR_WDT_OFFSET)
251
252#define CCM_CCSR_32KSR (1 << 15)
253
254#define CCM_CCSR_CLKMODE1 (1 << 9)
255#define CCM_CCSR_CLKMODE0 (1 << 8)
256
257#define CCM_CCSR_CLKOSEL_OFFSET 0
258#define CCM_CCSR_CLKOSEL_MASK 0x1f
259
260#define SYS_FMCR 0x14 /* Functional Muxing Control Reg */
261#define SYS_CHIP_ID 0x00 /* The offset of CHIP ID register */
31 262
32static int _clk_enable(struct clk *clk) 263static int _clk_enable(struct clk *clk)
33{ 264{
@@ -1004,6 +1235,7 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href)
1004 clk_enable(&uart_clk[0]); 1235 clk_enable(&uart_clk[0]);
1005#endif 1236#endif
1006 1237
1007 mxc_timer_init(&gpt_clk[0], IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT1); 1238 mxc_timer_init(&gpt_clk[0], MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR),
1239 MX21_INT_GPT1);
1008 return 0; 1240 return 0;
1009} 1241}
diff --git a/arch/arm/mach-mx2/clock_imx27.c b/arch/arm/mach-mx2/clock_imx27.c
index b010bf9ceaa..68bf93e6e90 100644
--- a/arch/arm/mach-mx2/clock_imx27.c
+++ b/arch/arm/mach-mx2/clock_imx27.c
@@ -29,21 +29,23 @@
29#include <mach/common.h> 29#include <mach/common.h>
30#include <mach/hardware.h> 30#include <mach/hardware.h>
31 31
32#define IO_ADDR_CCM(off) (MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR + (off)))
33
32/* Register offsets */ 34/* Register offsets */
33#define CCM_CSCR (IO_ADDRESS(CCM_BASE_ADDR) + 0x0) 35#define CCM_CSCR IO_ADDR_CCM(0x0)
34#define CCM_MPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x4) 36#define CCM_MPCTL0 IO_ADDR_CCM(0x4)
35#define CCM_MPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x8) 37#define CCM_MPCTL1 IO_ADDR_CCM(0x8)
36#define CCM_SPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0xC) 38#define CCM_SPCTL0 IO_ADDR_CCM(0xc)
37#define CCM_SPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x10) 39#define CCM_SPCTL1 IO_ADDR_CCM(0x10)
38#define CCM_OSC26MCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x14) 40#define CCM_OSC26MCTL IO_ADDR_CCM(0x14)
39#define CCM_PCDR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x18) 41#define CCM_PCDR0 IO_ADDR_CCM(0x18)
40#define CCM_PCDR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x1c) 42#define CCM_PCDR1 IO_ADDR_CCM(0x1c)
41#define CCM_PCCR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x20) 43#define CCM_PCCR0 IO_ADDR_CCM(0x20)
42#define CCM_PCCR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x24) 44#define CCM_PCCR1 IO_ADDR_CCM(0x24)
43#define CCM_CCSR (IO_ADDRESS(CCM_BASE_ADDR) + 0x28) 45#define CCM_CCSR IO_ADDR_CCM(0x28)
44#define CCM_PMCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x2c) 46#define CCM_PMCTL IO_ADDR_CCM(0x2c)
45#define CCM_PMCOUNT (IO_ADDRESS(CCM_BASE_ADDR) + 0x30) 47#define CCM_PMCOUNT IO_ADDR_CCM(0x30)
46#define CCM_WKGDCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x34) 48#define CCM_WKGDCTL IO_ADDR_CCM(0x34)
47 49
48#define CCM_CSCR_UPDATE_DIS (1 << 31) 50#define CCM_CSCR_UPDATE_DIS (1 << 31)
49#define CCM_CSCR_SSI2 (1 << 23) 51#define CCM_CSCR_SSI2 (1 << 23)
@@ -755,7 +757,8 @@ int __init mx27_clocks_init(unsigned long fref)
755 clk_enable(&uart1_clk); 757 clk_enable(&uart1_clk);
756#endif 758#endif
757 759
758 mxc_timer_init(&gpt1_clk, IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT1); 760 mxc_timer_init(&gpt1_clk, MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR),
761 MX27_INT_GPT1);
759 762
760 return 0; 763 return 0;
761} 764}
diff --git a/arch/arm/mach-mx2/cpu_imx27.c b/arch/arm/mach-mx2/cpu_imx27.c
index d9e3bf9644c..d8d3b2d84dc 100644
--- a/arch/arm/mach-mx2/cpu_imx27.c
+++ b/arch/arm/mach-mx2/cpu_imx27.c
@@ -39,7 +39,8 @@ static void query_silicon_parameter(void)
39 * the silicon revision very early we read it here to 39 * the silicon revision very early we read it here to
40 * avoid any further hooks 40 * avoid any further hooks
41 */ 41 */
42 val = __raw_readl(IO_ADDRESS(SYSCTRL_BASE_ADDR) + SYS_CHIP_ID); 42 val = __raw_readl(MX27_IO_ADDRESS(MX27_SYSCTRL_BASE_ADDR
43 + SYS_CHIP_ID));
43 44
44 cpu_silicon_rev = (int)(val >> 28); 45 cpu_silicon_rev = (int)(val >> 28);
45 cpu_partnumber = (int)((val >> 12) & 0xFFFF); 46 cpu_partnumber = (int)((val >> 12) & 0xFFFF);
diff --git a/arch/arm/mach-mx2/crm_regs.h b/arch/arm/mach-mx2/crm_regs.h
deleted file mode 100644
index 749de76b3f9..00000000000
--- a/arch/arm/mach-mx2/crm_regs.h
+++ /dev/null
@@ -1,258 +0,0 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#ifndef __ARCH_ARM_MACH_MX2_CRM_REGS_H__
21#define __ARCH_ARM_MACH_MX2_CRM_REGS_H__
22
23#include <mach/hardware.h>
24
25/* Register offsets */
26#define CCM_CSCR (IO_ADDRESS(CCM_BASE_ADDR) + 0x0)
27#define CCM_MPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x4)
28#define CCM_MPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x8)
29#define CCM_SPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0xC)
30#define CCM_SPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x10)
31#define CCM_OSC26MCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x14)
32#define CCM_PCDR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x18)
33#define CCM_PCDR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x1c)
34#define CCM_PCCR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x20)
35#define CCM_PCCR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x24)
36#define CCM_CCSR (IO_ADDRESS(CCM_BASE_ADDR) + 0x28)
37#define CCM_PMCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x2c)
38#define CCM_PMCOUNT (IO_ADDRESS(CCM_BASE_ADDR) + 0x30)
39#define CCM_WKGDCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x34)
40
41#define CCM_CSCR_PRESC_OFFSET 29
42#define CCM_CSCR_PRESC_MASK (0x7 << CCM_CSCR_PRESC_OFFSET)
43
44#define CCM_CSCR_USB_OFFSET 26
45#define CCM_CSCR_USB_MASK (0x7 << CCM_CSCR_USB_OFFSET)
46#define CCM_CSCR_SD_OFFSET 24
47#define CCM_CSCR_SD_MASK (0x3 << CCM_CSCR_SD_OFFSET)
48#define CCM_CSCR_SPLLRES (1 << 22)
49#define CCM_CSCR_MPLLRES (1 << 21)
50#define CCM_CSCR_SSI2_OFFSET 20
51#define CCM_CSCR_SSI2 (1 << CCM_CSCR_SSI2_OFFSET)
52#define CCM_CSCR_SSI1_OFFSET 19
53#define CCM_CSCR_SSI1 (1 << CCM_CSCR_SSI1_OFFSET)
54#define CCM_CSCR_FIR_OFFSET 18
55#define CCM_CSCR_FIR (1 << CCM_CSCR_FIR_OFFSET)
56#define CCM_CSCR_SP (1 << 17)
57#define CCM_CSCR_MCU (1 << 16)
58#define CCM_CSCR_BCLK_OFFSET 10
59#define CCM_CSCR_BCLK_MASK (0xf << CCM_CSCR_BCLK_OFFSET)
60#define CCM_CSCR_IPDIV_OFFSET 9
61#define CCM_CSCR_IPDIV (1 << CCM_CSCR_IPDIV_OFFSET)
62
63#define CCM_CSCR_OSC26MDIV (1 << 4)
64#define CCM_CSCR_OSC26M (1 << 3)
65#define CCM_CSCR_FPM (1 << 2)
66#define CCM_CSCR_SPEN (1 << 1)
67#define CCM_CSCR_MPEN 1
68
69
70
71#define CCM_MPCTL0_CPLM (1 << 31)
72#define CCM_MPCTL0_PD_OFFSET 26
73#define CCM_MPCTL0_PD_MASK (0xf << 26)
74#define CCM_MPCTL0_MFD_OFFSET 16
75#define CCM_MPCTL0_MFD_MASK (0x3ff << 16)
76#define CCM_MPCTL0_MFI_OFFSET 10
77#define CCM_MPCTL0_MFI_MASK (0xf << 10)
78#define CCM_MPCTL0_MFN_OFFSET 0
79#define CCM_MPCTL0_MFN_MASK 0x3ff
80
81#define CCM_MPCTL1_LF (1 << 15)
82#define CCM_MPCTL1_BRMO (1 << 6)
83
84#define CCM_SPCTL0_CPLM (1 << 31)
85#define CCM_SPCTL0_PD_OFFSET 26
86#define CCM_SPCTL0_PD_MASK (0xf << 26)
87#define CCM_SPCTL0_MFD_OFFSET 16
88#define CCM_SPCTL0_MFD_MASK (0x3ff << 16)
89#define CCM_SPCTL0_MFI_OFFSET 10
90#define CCM_SPCTL0_MFI_MASK (0xf << 10)
91#define CCM_SPCTL0_MFN_OFFSET 0
92#define CCM_SPCTL0_MFN_MASK 0x3ff
93
94#define CCM_SPCTL1_LF (1 << 15)
95#define CCM_SPCTL1_BRMO (1 << 6)
96
97#define CCM_OSC26MCTL_PEAK_OFFSET 16
98#define CCM_OSC26MCTL_PEAK_MASK (0x3 << 16)
99#define CCM_OSC26MCTL_AGC_OFFSET 8
100#define CCM_OSC26MCTL_AGC_MASK (0x3f << 8)
101#define CCM_OSC26MCTL_ANATEST_OFFSET 0
102#define CCM_OSC26MCTL_ANATEST_MASK 0x3f
103
104#define CCM_PCDR0_SSI2BAUDDIV_OFFSET 26
105#define CCM_PCDR0_SSI2BAUDDIV_MASK (0x3f << 26)
106#define CCM_PCDR0_SSI1BAUDDIV_OFFSET 16
107#define CCM_PCDR0_SSI1BAUDDIV_MASK (0x3f << 16)
108#define CCM_PCDR0_NFCDIV_OFFSET 12
109#define CCM_PCDR0_NFCDIV_MASK (0xf << 12)
110#define CCM_PCDR0_48MDIV_OFFSET 5
111#define CCM_PCDR0_48MDIV_MASK (0x7 << CCM_PCDR0_48MDIV_OFFSET)
112#define CCM_PCDR0_FIRIDIV_OFFSET 0
113#define CCM_PCDR0_FIRIDIV_MASK 0x1f
114#define CCM_PCDR1_PERDIV4_OFFSET 24
115#define CCM_PCDR1_PERDIV4_MASK (0x3f << 24)
116#define CCM_PCDR1_PERDIV3_OFFSET 16
117#define CCM_PCDR1_PERDIV3_MASK (0x3f << 16)
118#define CCM_PCDR1_PERDIV2_OFFSET 8
119#define CCM_PCDR1_PERDIV2_MASK (0x3f << 8)
120#define CCM_PCDR1_PERDIV1_OFFSET 0
121#define CCM_PCDR1_PERDIV1_MASK 0x3f
122
123#define CCM_PCCR_HCLK_CSI_OFFSET 31
124#define CCM_PCCR_HCLK_CSI_REG CCM_PCCR0
125#define CCM_PCCR_HCLK_DMA_OFFSET 30
126#define CCM_PCCR_HCLK_DMA_REG CCM_PCCR0
127#define CCM_PCCR_HCLK_BROM_OFFSET 28
128#define CCM_PCCR_HCLK_BROM_REG CCM_PCCR0
129#define CCM_PCCR_HCLK_EMMA_OFFSET 27
130#define CCM_PCCR_HCLK_EMMA_REG CCM_PCCR0
131#define CCM_PCCR_HCLK_LCDC_OFFSET 26
132#define CCM_PCCR_HCLK_LCDC_REG CCM_PCCR0
133#define CCM_PCCR_HCLK_SLCDC_OFFSET 25
134#define CCM_PCCR_HCLK_SLCDC_REG CCM_PCCR0
135#define CCM_PCCR_HCLK_USBOTG_OFFSET 24
136#define CCM_PCCR_HCLK_USBOTG_REG CCM_PCCR0
137#define CCM_PCCR_HCLK_BMI_OFFSET 23
138#define CCM_PCCR_BMI_MASK (1 << CCM_PCCR_BMI_MASK)
139#define CCM_PCCR_HCLK_BMI_REG CCM_PCCR0
140#define CCM_PCCR_PERCLK4_OFFSET 22
141#define CCM_PCCR_PERCLK4_REG CCM_PCCR0
142#define CCM_PCCR_SLCDC_OFFSET 21
143#define CCM_PCCR_SLCDC_REG CCM_PCCR0
144#define CCM_PCCR_FIRI_BAUD_OFFSET 20
145#define CCM_PCCR_FIRI_BAUD_MASK (1 << CCM_PCCR_FIRI_BAUD_MASK)
146#define CCM_PCCR_FIRI_BAUD_REG CCM_PCCR0
147#define CCM_PCCR_NFC_OFFSET 19
148#define CCM_PCCR_NFC_REG CCM_PCCR0
149#define CCM_PCCR_LCDC_OFFSET 18
150#define CCM_PCCR_LCDC_REG CCM_PCCR0
151#define CCM_PCCR_SSI1_BAUD_OFFSET 17
152#define CCM_PCCR_SSI1_BAUD_REG CCM_PCCR0
153#define CCM_PCCR_SSI2_BAUD_OFFSET 16
154#define CCM_PCCR_SSI2_BAUD_REG CCM_PCCR0
155#define CCM_PCCR_EMMA_OFFSET 15
156#define CCM_PCCR_EMMA_REG CCM_PCCR0
157#define CCM_PCCR_USBOTG_OFFSET 14
158#define CCM_PCCR_USBOTG_REG CCM_PCCR0
159#define CCM_PCCR_DMA_OFFSET 13
160#define CCM_PCCR_DMA_REG CCM_PCCR0
161#define CCM_PCCR_I2C1_OFFSET 12
162#define CCM_PCCR_I2C1_REG CCM_PCCR0
163#define CCM_PCCR_GPIO_OFFSET 11
164#define CCM_PCCR_GPIO_REG CCM_PCCR0
165#define CCM_PCCR_SDHC2_OFFSET 10
166#define CCM_PCCR_SDHC2_REG CCM_PCCR0
167#define CCM_PCCR_SDHC1_OFFSET 9
168#define CCM_PCCR_SDHC1_REG CCM_PCCR0
169#define CCM_PCCR_FIRI_OFFSET 8
170#define CCM_PCCR_FIRI_MASK (1 << CCM_PCCR_BAUD_MASK)
171#define CCM_PCCR_FIRI_REG CCM_PCCR0
172#define CCM_PCCR_SSI2_IPG_OFFSET 7
173#define CCM_PCCR_SSI2_REG CCM_PCCR0
174#define CCM_PCCR_SSI1_IPG_OFFSET 6
175#define CCM_PCCR_SSI1_REG CCM_PCCR0
176#define CCM_PCCR_CSPI2_OFFSET 5
177#define CCM_PCCR_CSPI2_REG CCM_PCCR0
178#define CCM_PCCR_CSPI1_OFFSET 4
179#define CCM_PCCR_CSPI1_REG CCM_PCCR0
180#define CCM_PCCR_UART4_OFFSET 3
181#define CCM_PCCR_UART4_REG CCM_PCCR0
182#define CCM_PCCR_UART3_OFFSET 2
183#define CCM_PCCR_UART3_REG CCM_PCCR0
184#define CCM_PCCR_UART2_OFFSET 1
185#define CCM_PCCR_UART2_REG CCM_PCCR0
186#define CCM_PCCR_UART1_OFFSET 0
187#define CCM_PCCR_UART1_REG CCM_PCCR0
188
189#define CCM_PCCR_OWIRE_OFFSET 31
190#define CCM_PCCR_OWIRE_REG CCM_PCCR1
191#define CCM_PCCR_KPP_OFFSET 30
192#define CCM_PCCR_KPP_REG CCM_PCCR1
193#define CCM_PCCR_RTC_OFFSET 29
194#define CCM_PCCR_RTC_REG CCM_PCCR1
195#define CCM_PCCR_PWM_OFFSET 28
196#define CCM_PCCR_PWM_REG CCM_PCCR1
197#define CCM_PCCR_GPT3_OFFSET 27
198#define CCM_PCCR_GPT3_REG CCM_PCCR1
199#define CCM_PCCR_GPT2_OFFSET 26
200#define CCM_PCCR_GPT2_REG CCM_PCCR1
201#define CCM_PCCR_GPT1_OFFSET 25
202#define CCM_PCCR_GPT1_REG CCM_PCCR1
203#define CCM_PCCR_WDT_OFFSET 24
204#define CCM_PCCR_WDT_REG CCM_PCCR1
205#define CCM_PCCR_CSPI3_OFFSET 23
206#define CCM_PCCR_CSPI3_REG CCM_PCCR1
207
208#define CCM_PCCR_CSPI1_MASK (1 << CCM_PCCR_CSPI1_OFFSET)
209#define CCM_PCCR_CSPI2_MASK (1 << CCM_PCCR_CSPI2_OFFSET)
210#define CCM_PCCR_CSPI3_MASK (1 << CCM_PCCR_CSPI3_OFFSET)
211#define CCM_PCCR_DMA_MASK (1 << CCM_PCCR_DMA_OFFSET)
212#define CCM_PCCR_EMMA_MASK (1 << CCM_PCCR_EMMA_OFFSET)
213#define CCM_PCCR_GPIO_MASK (1 << CCM_PCCR_GPIO_OFFSET)
214#define CCM_PCCR_GPT1_MASK (1 << CCM_PCCR_GPT1_OFFSET)
215#define CCM_PCCR_GPT2_MASK (1 << CCM_PCCR_GPT2_OFFSET)
216#define CCM_PCCR_GPT3_MASK (1 << CCM_PCCR_GPT3_OFFSET)
217#define CCM_PCCR_HCLK_BROM_MASK (1 << CCM_PCCR_HCLK_BROM_OFFSET)
218#define CCM_PCCR_HCLK_CSI_MASK (1 << CCM_PCCR_HCLK_CSI_OFFSET)
219#define CCM_PCCR_HCLK_DMA_MASK (1 << CCM_PCCR_HCLK_DMA_OFFSET)
220#define CCM_PCCR_HCLK_EMMA_MASK (1 << CCM_PCCR_HCLK_EMMA_OFFSET)
221#define CCM_PCCR_HCLK_LCDC_MASK (1 << CCM_PCCR_HCLK_LCDC_OFFSET)
222#define CCM_PCCR_HCLK_SLCDC_MASK (1 << CCM_PCCR_HCLK_SLCDC_OFFSET)
223#define CCM_PCCR_HCLK_USBOTG_MASK (1 << CCM_PCCR_HCLK_USBOTG_OFFSET)
224#define CCM_PCCR_I2C1_MASK (1 << CCM_PCCR_I2C1_OFFSET)
225#define CCM_PCCR_KPP_MASK (1 << CCM_PCCR_KPP_OFFSET)
226#define CCM_PCCR_LCDC_MASK (1 << CCM_PCCR_LCDC_OFFSET)
227#define CCM_PCCR_NFC_MASK (1 << CCM_PCCR_NFC_OFFSET)
228#define CCM_PCCR_OWIRE_MASK (1 << CCM_PCCR_OWIRE_OFFSET)
229#define CCM_PCCR_PERCLK4_MASK (1 << CCM_PCCR_PERCLK4_OFFSET)
230#define CCM_PCCR_PWM_MASK (1 << CCM_PCCR_PWM_OFFSET)
231#define CCM_PCCR_RTC_MASK (1 << CCM_PCCR_RTC_OFFSET)
232#define CCM_PCCR_SDHC1_MASK (1 << CCM_PCCR_SDHC1_OFFSET)
233#define CCM_PCCR_SDHC2_MASK (1 << CCM_PCCR_SDHC2_OFFSET)
234#define CCM_PCCR_SLCDC_MASK (1 << CCM_PCCR_SLCDC_OFFSET)
235#define CCM_PCCR_SSI1_BAUD_MASK (1 << CCM_PCCR_SSI1_BAUD_OFFSET)
236#define CCM_PCCR_SSI1_IPG_MASK (1 << CCM_PCCR_SSI1_IPG_OFFSET)
237#define CCM_PCCR_SSI2_BAUD_MASK (1 << CCM_PCCR_SSI2_BAUD_OFFSET)
238#define CCM_PCCR_SSI2_IPG_MASK (1 << CCM_PCCR_SSI2_IPG_OFFSET)
239#define CCM_PCCR_UART1_MASK (1 << CCM_PCCR_UART1_OFFSET)
240#define CCM_PCCR_UART2_MASK (1 << CCM_PCCR_UART2_OFFSET)
241#define CCM_PCCR_UART3_MASK (1 << CCM_PCCR_UART3_OFFSET)
242#define CCM_PCCR_UART4_MASK (1 << CCM_PCCR_UART4_OFFSET)
243#define CCM_PCCR_USBOTG_MASK (1 << CCM_PCCR_USBOTG_OFFSET)
244#define CCM_PCCR_WDT_MASK (1 << CCM_PCCR_WDT_OFFSET)
245
246
247#define CCM_CCSR_32KSR (1 << 15)
248
249#define CCM_CCSR_CLKMODE1 (1 << 9)
250#define CCM_CCSR_CLKMODE0 (1 << 8)
251
252#define CCM_CCSR_CLKOSEL_OFFSET 0
253#define CCM_CCSR_CLKOSEL_MASK 0x1f
254
255#define SYS_FMCR 0x14 /* Functional Muxing Control Reg */
256#define SYS_CHIP_ID 0x00 /* The offset of CHIP ID register */
257
258#endif /* __ARCH_ARM_MACH_MX2_CRM_REGS_H__ */
diff --git a/arch/arm/mach-mx2/eukrea_cpuimx27.c b/arch/arm/mach-mx2/mach-cpuimx27.c
index 7b187606682..8e4f3d08e32 100644
--- a/arch/arm/mach-mx2/eukrea_cpuimx27.c
+++ b/arch/arm/mach-mx2/mach-cpuimx27.c
@@ -142,28 +142,28 @@ static struct i2c_board_info eukrea_cpuimx27_i2c_devices[] = {
142#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) 142#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
143static struct plat_serial8250_port serial_platform_data[] = { 143static struct plat_serial8250_port serial_platform_data[] = {
144 { 144 {
145 .mapbase = (unsigned long)(CS3_BASE_ADDR + 0x200000), 145 .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x200000),
146 .irq = IRQ_GPIOB(23), 146 .irq = IRQ_GPIOB(23),
147 .uartclk = 14745600, 147 .uartclk = 14745600,
148 .regshift = 1, 148 .regshift = 1,
149 .iotype = UPIO_MEM, 149 .iotype = UPIO_MEM,
150 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, 150 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
151 }, { 151 }, {
152 .mapbase = (unsigned long)(CS3_BASE_ADDR + 0x400000), 152 .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x400000),
153 .irq = IRQ_GPIOB(22), 153 .irq = IRQ_GPIOB(22),
154 .uartclk = 14745600, 154 .uartclk = 14745600,
155 .regshift = 1, 155 .regshift = 1,
156 .iotype = UPIO_MEM, 156 .iotype = UPIO_MEM,
157 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, 157 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
158 }, { 158 }, {
159 .mapbase = (unsigned long)(CS3_BASE_ADDR + 0x800000), 159 .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x800000),
160 .irq = IRQ_GPIOB(27), 160 .irq = IRQ_GPIOB(27),
161 .uartclk = 14745600, 161 .uartclk = 14745600,
162 .regshift = 1, 162 .regshift = 1,
163 .iotype = UPIO_MEM, 163 .iotype = UPIO_MEM,
164 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, 164 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
165 }, { 165 }, {
166 .mapbase = (unsigned long)(CS3_BASE_ADDR + 0x1000000), 166 .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x1000000),
167 .irq = IRQ_GPIOB(30), 167 .irq = IRQ_GPIOB(30),
168 .uartclk = 14745600, 168 .uartclk = 14745600,
169 .regshift = 1, 169 .regshift = 1,
@@ -224,8 +224,8 @@ static struct sys_timer eukrea_cpuimx27_timer = {
224}; 224};
225 225
226MACHINE_START(CPUIMX27, "EUKREA CPUIMX27") 226MACHINE_START(CPUIMX27, "EUKREA CPUIMX27")
227 .phys_io = AIPI_BASE_ADDR, 227 .phys_io = MX27_AIPI_BASE_ADDR,
228 .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, 228 .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
229 .boot_params = PHYS_OFFSET + 0x100, 229 .boot_params = PHYS_OFFSET + 0x100,
230 .map_io = mx27_map_io, 230 .map_io = mx27_map_io,
231 .init_irq = mx27_init_irq, 231 .init_irq = mx27_init_irq,
diff --git a/arch/arm/mach-mx2/mx27lite.c b/arch/arm/mach-mx2/mach-imx27lite.c
index 82ea227ea0c..ca6ab1265f3 100644
--- a/arch/arm/mach-mx2/mx27lite.c
+++ b/arch/arm/mach-mx2/mach-imx27lite.c
@@ -85,8 +85,8 @@ static struct sys_timer mx27lite_timer = {
85}; 85};
86 86
87MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE") 87MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE")
88 .phys_io = AIPI_BASE_ADDR, 88 .phys_io = MX27_AIPI_BASE_ADDR,
89 .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, 89 .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
90 .boot_params = PHYS_OFFSET + 0x100, 90 .boot_params = PHYS_OFFSET + 0x100,
91 .map_io = mx27_map_io, 91 .map_io = mx27_map_io,
92 .init_irq = mx27_init_irq, 92 .init_irq = mx27_init_irq,
diff --git a/arch/arm/mach-mx2/mx21ads.c b/arch/arm/mach-mx2/mach-mx21ads.c
index cf5f77cbc2f..eb4a6e85559 100644
--- a/arch/arm/mach-mx2/mx21ads.c
+++ b/arch/arm/mach-mx2/mach-mx21ads.c
@@ -118,8 +118,8 @@ static struct physmap_flash_data mx21ads_flash_data = {
118}; 118};
119 119
120static struct resource mx21ads_flash_resource = { 120static struct resource mx21ads_flash_resource = {
121 .start = CS0_BASE_ADDR, 121 .start = MX21_CS0_BASE_ADDR,
122 .end = CS0_BASE_ADDR + 0x02000000 - 1, 122 .end = MX21_CS0_BASE_ADDR + 0x02000000 - 1,
123 .flags = IORESOURCE_MEM, 123 .flags = IORESOURCE_MEM,
124}; 124};
125 125
@@ -242,7 +242,7 @@ static struct map_desc mx21ads_io_desc[] __initdata = {
242 */ 242 */
243 { 243 {
244 .virtual = MX21ADS_MMIO_BASE_ADDR, 244 .virtual = MX21ADS_MMIO_BASE_ADDR,
245 .pfn = __phys_to_pfn(CS1_BASE_ADDR), 245 .pfn = __phys_to_pfn(MX21_CS1_BASE_ADDR),
246 .length = MX21ADS_MMIO_SIZE, 246 .length = MX21ADS_MMIO_SIZE,
247 .type = MT_DEVICE, 247 .type = MT_DEVICE,
248 }, 248 },
@@ -284,8 +284,8 @@ static struct sys_timer mx21ads_timer = {
284 284
285MACHINE_START(MX21ADS, "Freescale i.MX21ADS") 285MACHINE_START(MX21ADS, "Freescale i.MX21ADS")
286 /* maintainer: Freescale Semiconductor, Inc. */ 286 /* maintainer: Freescale Semiconductor, Inc. */
287 .phys_io = AIPI_BASE_ADDR, 287 .phys_io = MX21_AIPI_BASE_ADDR,
288 .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, 288 .io_pg_offst = ((MX21_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
289 .boot_params = PHYS_OFFSET + 0x100, 289 .boot_params = PHYS_OFFSET + 0x100,
290 .map_io = mx21ads_map_io, 290 .map_io = mx21ads_map_io,
291 .init_irq = mx21_init_irq, 291 .init_irq = mx21_init_irq,
diff --git a/arch/arm/mach-mx2/mx27pdk.c b/arch/arm/mach-mx2/mach-mx27_3ds.c
index 6761d1b79e4..595fea46b6f 100644
--- a/arch/arm/mach-mx2/mx27pdk.c
+++ b/arch/arm/mach-mx2/mach-mx27_3ds.c
@@ -85,8 +85,8 @@ static struct sys_timer mx27pdk_timer = {
85 85
86MACHINE_START(MX27_3DS, "Freescale MX27PDK") 86MACHINE_START(MX27_3DS, "Freescale MX27PDK")
87 /* maintainer: Freescale Semiconductor, Inc. */ 87 /* maintainer: Freescale Semiconductor, Inc. */
88 .phys_io = AIPI_BASE_ADDR, 88 .phys_io = MX27_AIPI_BASE_ADDR,
89 .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, 89 .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
90 .boot_params = PHYS_OFFSET + 0x100, 90 .boot_params = PHYS_OFFSET + 0x100,
91 .map_io = mx27_map_io, 91 .map_io = mx27_map_io,
92 .init_irq = mx27_init_irq, 92 .init_irq = mx27_init_irq,
diff --git a/arch/arm/mach-mx2/mx27ads.c b/arch/arm/mach-mx2/mach-mx27ads.c
index 83e412b713e..385fc1c9ad3 100644
--- a/arch/arm/mach-mx2/mx27ads.c
+++ b/arch/arm/mach-mx2/mach-mx27ads.c
@@ -320,7 +320,7 @@ static struct sys_timer mx27ads_timer = {
320static struct map_desc mx27ads_io_desc[] __initdata = { 320static struct map_desc mx27ads_io_desc[] __initdata = {
321 { 321 {
322 .virtual = PBC_BASE_ADDRESS, 322 .virtual = PBC_BASE_ADDRESS,
323 .pfn = __phys_to_pfn(CS4_BASE_ADDR), 323 .pfn = __phys_to_pfn(MX27_CS4_BASE_ADDR),
324 .length = SZ_1M, 324 .length = SZ_1M,
325 .type = MT_DEVICE, 325 .type = MT_DEVICE,
326 }, 326 },
@@ -334,8 +334,8 @@ static void __init mx27ads_map_io(void)
334 334
335MACHINE_START(MX27ADS, "Freescale i.MX27ADS") 335MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
336 /* maintainer: Freescale Semiconductor, Inc. */ 336 /* maintainer: Freescale Semiconductor, Inc. */
337 .phys_io = AIPI_BASE_ADDR, 337 .phys_io = MX27_AIPI_BASE_ADDR,
338 .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, 338 .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
339 .boot_params = PHYS_OFFSET + 0x100, 339 .boot_params = PHYS_OFFSET + 0x100,
340 .map_io = mx27ads_map_io, 340 .map_io = mx27ads_map_io,
341 .init_irq = mx27_init_irq, 341 .init_irq = mx27_init_irq,
diff --git a/arch/arm/mach-mx2/mxt_td60.c b/arch/arm/mach-mx2/mach-mxt_td60.c
index 03dbbdc9895..9ed4e492fc7 100644
--- a/arch/arm/mach-mx2/mxt_td60.c
+++ b/arch/arm/mach-mx2/mach-mxt_td60.c
@@ -58,21 +58,6 @@ static unsigned int mxt_td60_pins[] __initdata = {
58 PE9_PF_UART3_RXD, 58 PE9_PF_UART3_RXD,
59 PE10_PF_UART3_CTS, 59 PE10_PF_UART3_CTS,
60 PE11_PF_UART3_RTS, 60 PE11_PF_UART3_RTS,
61 /* UART3 */
62 PB26_AF_UART4_RTS,
63 PB28_AF_UART4_TXD,
64 PB29_AF_UART4_CTS,
65 PB31_AF_UART4_RXD,
66 /* UART4 */
67 PB18_AF_UART5_TXD,
68 PB19_AF_UART5_RXD,
69 PB20_AF_UART5_CTS,
70 PB21_AF_UART5_RTS,
71 /* UART5 */
72 PB10_AF_UART6_TXD,
73 PB12_AF_UART6_CTS,
74 PB11_AF_UART6_RXD,
75 PB13_AF_UART6_RTS,
76 /* FEC */ 61 /* FEC */
77 PD0_AIN_FEC_TXD0, 62 PD0_AIN_FEC_TXD0,
78 PD1_AIN_FEC_TXD1, 63 PD1_AIN_FEC_TXD1,
@@ -261,12 +246,6 @@ static struct imxuart_platform_data uart_pdata[] = {
261 .flags = IMXUART_HAVE_RTSCTS, 246 .flags = IMXUART_HAVE_RTSCTS,
262 }, { 247 }, {
263 .flags = IMXUART_HAVE_RTSCTS, 248 .flags = IMXUART_HAVE_RTSCTS,
264 }, {
265 .flags = IMXUART_HAVE_RTSCTS,
266 }, {
267 .flags = IMXUART_HAVE_RTSCTS,
268 }, {
269 .flags = IMXUART_HAVE_RTSCTS,
270 }, 249 },
271}; 250};
272 251
@@ -278,9 +257,6 @@ static void __init mxt_td60_board_init(void)
278 mxc_register_device(&mxc_uart_device0, &uart_pdata[0]); 257 mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
279 mxc_register_device(&mxc_uart_device1, &uart_pdata[1]); 258 mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
280 mxc_register_device(&mxc_uart_device2, &uart_pdata[2]); 259 mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
281 mxc_register_device(&mxc_uart_device3, &uart_pdata[3]);
282 mxc_register_device(&mxc_uart_device4, &uart_pdata[4]);
283 mxc_register_device(&mxc_uart_device5, &uart_pdata[5]);
284 mxc_register_device(&mxc_nand_device, &mxt_td60_nand_board_info); 260 mxc_register_device(&mxc_nand_device, &mxt_td60_nand_board_info);
285 261
286 i2c_register_board_info(0, mxt_td60_i2c_devices, 262 i2c_register_board_info(0, mxt_td60_i2c_devices,
@@ -308,8 +284,8 @@ static struct sys_timer mxt_td60_timer = {
308 284
309MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60") 285MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60")
310 /* maintainer: Maxtrack Industrial */ 286 /* maintainer: Maxtrack Industrial */
311 .phys_io = AIPI_BASE_ADDR, 287 .phys_io = MX27_AIPI_BASE_ADDR,
312 .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, 288 .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
313 .boot_params = PHYS_OFFSET + 0x100, 289 .boot_params = PHYS_OFFSET + 0x100,
314 .map_io = mx27_map_io, 290 .map_io = mx27_map_io,
315 .init_irq = mx27_init_irq, 291 .init_irq = mx27_init_irq,
diff --git a/arch/arm/mach-mx2/pca100.c b/arch/arm/mach-mx2/mach-pca100.c
index aea3d340d2e..55dbf5a64e0 100644
--- a/arch/arm/mach-mx2/pca100.c
+++ b/arch/arm/mach-mx2/mach-pca100.c
@@ -233,8 +233,8 @@ static struct sys_timer pca100_timer = {
233}; 233};
234 234
235MACHINE_START(PCA100, "phyCARD-i.MX27") 235MACHINE_START(PCA100, "phyCARD-i.MX27")
236 .phys_io = AIPI_BASE_ADDR, 236 .phys_io = MX27_AIPI_BASE_ADDR,
237 .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, 237 .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
238 .boot_params = PHYS_OFFSET + 0x100, 238 .boot_params = PHYS_OFFSET + 0x100,
239 .map_io = mx27_map_io, 239 .map_io = mx27_map_io,
240 .init_irq = mx27_init_irq, 240 .init_irq = mx27_init_irq,
diff --git a/arch/arm/mach-mx2/pcm038.c b/arch/arm/mach-mx2/mach-pcm038.c
index 906d59b0a7a..9636bb82f1e 100644
--- a/arch/arm/mach-mx2/pcm038.c
+++ b/arch/arm/mach-mx2/mach-pcm038.c
@@ -108,8 +108,8 @@ static struct platdata_mtd_ram pcm038_sram_data = {
108}; 108};
109 109
110static struct resource pcm038_sram_resource = { 110static struct resource pcm038_sram_resource = {
111 .start = CS1_BASE_ADDR, 111 .start = MX27_CS1_BASE_ADDR,
112 .end = CS1_BASE_ADDR + 512 * 1024 - 1, 112 .end = MX27_CS1_BASE_ADDR + 512 * 1024 - 1,
113 .flags = IORESOURCE_MEM, 113 .flags = IORESOURCE_MEM,
114}; 114};
115 115
@@ -173,9 +173,7 @@ static struct platform_device *platform_devices[] __initdata = {
173 * setup other stuffs to access the sram. */ 173 * setup other stuffs to access the sram. */
174static void __init pcm038_init_sram(void) 174static void __init pcm038_init_sram(void)
175{ 175{
176 __raw_writel(0x0000d843, CSCR_U(1)); 176 mx27_setup_weimcs(1, 0x0000d843, 0x22252521, 0x22220a00);
177 __raw_writel(0x22252521, CSCR_L(1));
178 __raw_writel(0x22220a00, CSCR_A(1));
179} 177}
180 178
181static struct imxi2c_platform_data pcm038_i2c_1_data = { 179static struct imxi2c_platform_data pcm038_i2c_1_data = {
@@ -328,8 +326,8 @@ static struct sys_timer pcm038_timer = {
328}; 326};
329 327
330MACHINE_START(PCM038, "phyCORE-i.MX27") 328MACHINE_START(PCM038, "phyCORE-i.MX27")
331 .phys_io = AIPI_BASE_ADDR, 329 .phys_io = MX27_AIPI_BASE_ADDR,
332 .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, 330 .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
333 .boot_params = PHYS_OFFSET + 0x100, 331 .boot_params = PHYS_OFFSET + 0x100,
334 .map_io = mx27_map_io, 332 .map_io = mx27_map_io,
335 .init_irq = mx27_init_irq, 333 .init_irq = mx27_init_irq,
diff --git a/arch/arm/mach-mx2/pcm970-baseboard.c b/arch/arm/mach-mx2/pcm970-baseboard.c
index 3cb7f457e5d..60d54465ada 100644
--- a/arch/arm/mach-mx2/pcm970-baseboard.c
+++ b/arch/arm/mach-mx2/pcm970-baseboard.c
@@ -190,8 +190,8 @@ static struct imx_fb_platform_data pcm038_fb_data = {
190 190
191static struct resource pcm970_sja1000_resources[] = { 191static struct resource pcm970_sja1000_resources[] = {
192 { 192 {
193 .start = CS4_BASE_ADDR, 193 .start = MX27_CS4_BASE_ADDR,
194 .end = CS4_BASE_ADDR + 0x100 - 1, 194 .end = MX27_CS4_BASE_ADDR + 0x100 - 1,
195 .flags = IORESOURCE_MEM, 195 .flags = IORESOURCE_MEM,
196 }, { 196 }, {
197 .start = IRQ_GPIOE(19), 197 .start = IRQ_GPIOE(19),
diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c
index ef26951a527..6e838b85771 100644
--- a/arch/arm/mach-mx25/clock.c
+++ b/arch/arm/mach-mx25/clock.c
@@ -173,6 +173,7 @@ DEFINE_CLOCK(pwm4_clk, 0, CCM_CGCR2, 2, get_rate_ipg, NULL);
173DEFINE_CLOCK(kpp_clk, 0, CCM_CGCR1, 28, get_rate_ipg, NULL); 173DEFINE_CLOCK(kpp_clk, 0, CCM_CGCR1, 28, get_rate_ipg, NULL);
174DEFINE_CLOCK(tsc_clk, 0, CCM_CGCR2, 13, get_rate_ipg, NULL); 174DEFINE_CLOCK(tsc_clk, 0, CCM_CGCR2, 13, get_rate_ipg, NULL);
175DEFINE_CLOCK(i2c_clk, 0, CCM_CGCR0, 6, get_rate_i2c, NULL); 175DEFINE_CLOCK(i2c_clk, 0, CCM_CGCR0, 6, get_rate_i2c, NULL);
176DEFINE_CLOCK(fec_clk, 0, CCM_CGCR0, 23, get_rate_ipg, NULL);
176 177
177#define _REGISTER_CLOCK(d, n, c) \ 178#define _REGISTER_CLOCK(d, n, c) \
178 { \ 179 { \
@@ -204,6 +205,7 @@ static struct clk_lookup lookups[] = {
204 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk) 205 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
205 _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk) 206 _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk)
206 _REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk) 207 _REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk)
208 _REGISTER_CLOCK("fec.0", NULL, fec_clk)
207}; 209};
208 210
209int __init mx25_clocks_init(unsigned long fref) 211int __init mx25_clocks_init(unsigned long fref)
diff --git a/arch/arm/mach-mx25/devices.c b/arch/arm/mach-mx25/devices.c
index 63511de3a55..9fdeea1c083 100644
--- a/arch/arm/mach-mx25/devices.c
+++ b/arch/arm/mach-mx25/devices.c
@@ -419,3 +419,22 @@ int __init mxc_register_gpios(void)
419 return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); 419 return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
420} 420}
421 421
422static struct resource mx25_fec_resources[] = {
423 {
424 .start = MX25_FEC_BASE_ADDR,
425 .end = MX25_FEC_BASE_ADDR + 0xfff,
426 .flags = IORESOURCE_MEM,
427 },
428 {
429 .start = MX25_INT_FEC,
430 .end = MX25_INT_FEC,
431 .flags = IORESOURCE_IRQ,
432 },
433};
434
435struct platform_device mx25_fec_device = {
436 .name = "fec",
437 .id = 0,
438 .num_resources = ARRAY_SIZE(mx25_fec_resources),
439 .resource = mx25_fec_resources,
440};
diff --git a/arch/arm/mach-mx25/devices.h b/arch/arm/mach-mx25/devices.h
index fe6bf88ad1d..fe5420fcd11 100644
--- a/arch/arm/mach-mx25/devices.h
+++ b/arch/arm/mach-mx25/devices.h
@@ -17,3 +17,4 @@ extern struct platform_device mxc_keypad_device;
17extern struct platform_device mxc_i2c_device0; 17extern struct platform_device mxc_i2c_device0;
18extern struct platform_device mxc_i2c_device1; 18extern struct platform_device mxc_i2c_device1;
19extern struct platform_device mxc_i2c_device2; 19extern struct platform_device mxc_i2c_device2;
20extern struct platform_device mx25_fec_device;
diff --git a/arch/arm/mach-mx25/mx25pdk.c b/arch/arm/mach-mx25/mx25pdk.c
index d23ae571c03..921bc99ea23 100644
--- a/arch/arm/mach-mx25/mx25pdk.c
+++ b/arch/arm/mach-mx25/mx25pdk.c
@@ -18,10 +18,11 @@
18 18
19#include <linux/types.h> 19#include <linux/types.h>
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/delay.h>
21#include <linux/clk.h> 22#include <linux/clk.h>
22#include <linux/irq.h> 23#include <linux/irq.h>
23#include <linux/gpio.h> 24#include <linux/gpio.h>
24#include <linux/smsc911x.h> 25#include <linux/fec.h>
25#include <linux/platform_device.h> 26#include <linux/platform_device.h>
26 27
27#include <mach/hardware.h> 28#include <mach/hardware.h>
@@ -35,16 +36,57 @@
35#include <mach/mx25.h> 36#include <mach/mx25.h>
36#include <mach/mxc_nand.h> 37#include <mach/mxc_nand.h>
37#include "devices.h" 38#include "devices.h"
38#include <mach/iomux-v3.h> 39#include <mach/iomux.h>
39 40
40static struct imxuart_platform_data uart_pdata = { 41static struct imxuart_platform_data uart_pdata = {
41 .flags = IMXUART_HAVE_RTSCTS, 42 .flags = IMXUART_HAVE_RTSCTS,
42}; 43};
43 44
45static struct pad_desc mx25pdk_pads[] = {
46 MX25_PAD_FEC_MDC__FEC_MDC,
47 MX25_PAD_FEC_MDIO__FEC_MDIO,
48 MX25_PAD_FEC_TDATA0__FEC_TDATA0,
49 MX25_PAD_FEC_TDATA1__FEC_TDATA1,
50 MX25_PAD_FEC_TX_EN__FEC_TX_EN,
51 MX25_PAD_FEC_RDATA0__FEC_RDATA0,
52 MX25_PAD_FEC_RDATA1__FEC_RDATA1,
53 MX25_PAD_FEC_RX_DV__FEC_RX_DV,
54 MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
55 MX25_PAD_A17__GPIO_2_3, /* FEC_EN, GPIO 35 */
56 MX25_PAD_D12__GPIO_4_8, /* FEC_RESET_B, GPIO 104 */
57};
58
59static struct fec_platform_data mx25_fec_pdata = {
60 .phy = PHY_INTERFACE_MODE_RMII,
61};
62
63#define FEC_ENABLE_GPIO 35
64#define FEC_RESET_B_GPIO 104
65
66static void __init mx25pdk_fec_reset(void)
67{
68 gpio_request(FEC_ENABLE_GPIO, "FEC PHY enable");
69 gpio_request(FEC_RESET_B_GPIO, "FEC PHY reset");
70
71 gpio_direction_output(FEC_ENABLE_GPIO, 0); /* drop PHY power */
72 gpio_direction_output(FEC_RESET_B_GPIO, 0); /* assert reset */
73 udelay(2);
74
75 /* turn on PHY power and lift reset */
76 gpio_set_value(FEC_ENABLE_GPIO, 1);
77 gpio_set_value(FEC_RESET_B_GPIO, 1);
78}
79
44static void __init mx25pdk_init(void) 80static void __init mx25pdk_init(void)
45{ 81{
82 mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads,
83 ARRAY_SIZE(mx25pdk_pads));
84
46 mxc_register_device(&mxc_uart_device0, &uart_pdata); 85 mxc_register_device(&mxc_uart_device0, &uart_pdata);
47 mxc_register_device(&mxc_usbh2, NULL); 86 mxc_register_device(&mxc_usbh2, NULL);
87
88 mx25pdk_fec_reset();
89 mxc_register_device(&mx25_fec_device, &mx25_fec_pdata);
48} 90}
49 91
50static void __init mx25pdk_timer_init(void) 92static void __init mx25pdk_timer_init(void)
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index ea8ed109a7c..28294416b0a 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -49,6 +49,7 @@ config MACH_PCM037_EET
49config MACH_MX31LITE 49config MACH_MX31LITE
50 bool "Support MX31 LITEKIT (LogicPD)" 50 bool "Support MX31 LITEKIT (LogicPD)"
51 select ARCH_MX31 51 select ARCH_MX31
52 select MXC_ULPI if USB_ULPI
52 help 53 help
53 Include support for MX31 LITEKIT platform. This includes specific 54 Include support for MX31 LITEKIT platform. This includes specific
54 configurations for the board and its peripherals. 55 configurations for the board and its peripherals.
@@ -63,7 +64,7 @@ config MACH_MX31_3DS
63config MACH_MX31MOBOARD 64config MACH_MX31MOBOARD
64 bool "Support mx31moboard platforms (EPFL Mobots group)" 65 bool "Support mx31moboard platforms (EPFL Mobots group)"
65 select ARCH_MX31 66 select ARCH_MX31
66 select MXC_ULPI 67 select MXC_ULPI if USB_ULPI
67 help 68 help
68 Include support for mx31moboard platform. This includes specific 69 Include support for mx31moboard platform. This includes specific
69 configurations for the board and its peripherals. 70 configurations for the board and its peripherals.
diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile
index 93c7b296be6..62b60931d87 100644
--- a/arch/arm/mach-mx3/Makefile
+++ b/arch/arm/mach-mx3/Makefile
@@ -5,18 +5,22 @@
5# Object file lists. 5# Object file lists.
6 6
7obj-y := mm.o devices.o cpu.o 7obj-y := mm.o devices.o cpu.o
8obj-$(CONFIG_ARCH_MX31) += clock.o iomux.o 8CFLAGS_mm.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
9CFLAGS_devices.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
10CFLAGS_cpu.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
11obj-$(CONFIG_ARCH_MX31) += clock-imx31.o iomux-imx31.o
9obj-$(CONFIG_ARCH_MX35) += clock-imx35.o 12obj-$(CONFIG_ARCH_MX35) += clock-imx35.o
10obj-$(CONFIG_MACH_MX31ADS) += mx31ads.o 13obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o
11obj-$(CONFIG_MACH_MX31LILLY) += mx31lilly.o mx31lilly-db.o 14obj-$(CONFIG_MACH_MX31LILLY) += mach-mx31lilly.o mx31lilly-db.o
12obj-$(CONFIG_MACH_MX31LITE) += mx31lite.o mx31lite-db.o 15obj-$(CONFIG_MACH_MX31LITE) += mach-mx31lite.o mx31lite-db.o
13obj-$(CONFIG_MACH_PCM037) += pcm037.o 16obj-$(CONFIG_MACH_PCM037) += mach-pcm037.o
14obj-$(CONFIG_MACH_PCM037_EET) += pcm037_eet.o 17obj-$(CONFIG_MACH_PCM037_EET) += mach-pcm037_eet.o
15obj-$(CONFIG_MACH_MX31_3DS) += mx31pdk.o 18obj-$(CONFIG_MACH_MX31_3DS) += mach-mx31_3ds.o
16obj-$(CONFIG_MACH_MX31MOBOARD) += mx31moboard.o mx31moboard-devboard.o \ 19CFLAGS_mach-mx31_3ds.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
20obj-$(CONFIG_MACH_MX31MOBOARD) += mach-mx31moboard.o mx31moboard-devboard.o \
17 mx31moboard-marxbot.o 21 mx31moboard-marxbot.o
18obj-$(CONFIG_MACH_QONG) += qong.o 22obj-$(CONFIG_MACH_QONG) += mach-qong.o
19obj-$(CONFIG_MACH_PCM043) += pcm043.o 23obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o
20obj-$(CONFIG_MACH_ARMADILLO5X0) += armadillo5x0.o 24obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o
21obj-$(CONFIG_MACH_MX35_3DS) += mx35pdk.o 25obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35pdk.o
22obj-$(CONFIG_MACH_KZM_ARM11_01) += kzmarm11.o 26obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o
diff --git a/arch/arm/mach-mx3/clock.c b/arch/arm/mach-mx3/clock-imx31.c
index 27a318af0d2..d22a66f502a 100644
--- a/arch/arm/mach-mx3/clock.c
+++ b/arch/arm/mach-mx3/clock-imx31.c
@@ -618,14 +618,15 @@ int __init mx31_clocks_init(unsigned long fref)
618 618
619 mx31_read_cpu_rev(); 619 mx31_read_cpu_rev();
620 620
621 if (mx31_revision() >= CHIP_REV_2_0) { 621 if (mx31_revision() >= MX31_CHIP_REV_2_0) {
622 reg = __raw_readl(MXC_CCM_PMCR1); 622 reg = __raw_readl(MXC_CCM_PMCR1);
623 /* No PLL restart on DVFS switch; enable auto EMI handshake */ 623 /* No PLL restart on DVFS switch; enable auto EMI handshake */
624 reg |= MXC_CCM_PMCR1_PLLRDIS | MXC_CCM_PMCR1_EMIRQ_EN; 624 reg |= MXC_CCM_PMCR1_PLLRDIS | MXC_CCM_PMCR1_EMIRQ_EN;
625 __raw_writel(reg, MXC_CCM_PMCR1); 625 __raw_writel(reg, MXC_CCM_PMCR1);
626 } 626 }
627 627
628 mxc_timer_init(&ipg_clk, IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT); 628 mxc_timer_init(&ipg_clk, MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR),
629 MX31_INT_GPT);
629 630
630 return 0; 631 return 0;
631} 632}
diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c
index 7584b4c6c55..07d630ebc28 100644
--- a/arch/arm/mach-mx3/clock-imx35.c
+++ b/arch/arm/mach-mx3/clock-imx35.c
@@ -28,7 +28,7 @@
28#include <mach/hardware.h> 28#include <mach/hardware.h>
29#include <mach/common.h> 29#include <mach/common.h>
30 30
31#define CCM_BASE IO_ADDRESS(CCM_BASE_ADDR) 31#define CCM_BASE MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR)
32 32
33#define CCM_CCMR 0x00 33#define CCM_CCMR 0x00
34#define CCM_PDR0 0x04 34#define CCM_PDR0 0x04
@@ -504,7 +504,8 @@ int __init mx35_clocks_init()
504 __raw_writel((3 << 26) | ll, CCM_BASE + CCM_CGR2); 504 __raw_writel((3 << 26) | ll, CCM_BASE + CCM_CGR2);
505 __raw_writel(0, CCM_BASE + CCM_CGR3); 505 __raw_writel(0, CCM_BASE + CCM_CGR3);
506 506
507 mxc_timer_init(&gpt_clk, IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT); 507 mxc_timer_init(&gpt_clk,
508 MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR), MX35_INT_GPT);
508 509
509 return 0; 510 return 0;
510} 511}
diff --git a/arch/arm/mach-mx3/cpu.c b/arch/arm/mach-mx3/cpu.c
index db828809c67..861afe0fe3a 100644
--- a/arch/arm/mach-mx3/cpu.c
+++ b/arch/arm/mach-mx3/cpu.c
@@ -41,7 +41,7 @@ void __init mx31_read_cpu_rev(void)
41 u32 i, srev; 41 u32 i, srev;
42 42
43 /* read SREV register from IIM module */ 43 /* read SREV register from IIM module */
44 srev = __raw_readl(IO_ADDRESS(IIM_BASE_ADDR) + MXC_IIMSREV); 44 srev = __raw_readl(IO_ADDRESS(IIM_BASE_ADDR + MXC_IIMSREV));
45 45
46 for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++) 46 for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
47 if (srev == mx31_cpu_type[i].srev) { 47 if (srev == mx31_cpu_type[i].srev) {
diff --git a/arch/arm/mach-mx3/crm_regs.h b/arch/arm/mach-mx3/crm_regs.h
index adfa3627ad8..37a8a07beda 100644
--- a/arch/arm/mach-mx3/crm_regs.h
+++ b/arch/arm/mach-mx3/crm_regs.h
@@ -24,7 +24,7 @@
24#define CKIH_CLK_FREQ_27MHZ 27000000 24#define CKIH_CLK_FREQ_27MHZ 27000000
25#define CKIL_CLK_FREQ 32768 25#define CKIL_CLK_FREQ 32768
26 26
27#define MXC_CCM_BASE IO_ADDRESS(CCM_BASE_ADDR) 27#define MXC_CCM_BASE MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR)
28 28
29/* Register addresses */ 29/* Register addresses */
30#define MXC_CCM_CCMR (MXC_CCM_BASE + 0x00) 30#define MXC_CCM_CCMR (MXC_CCM_BASE + 0x00)
diff --git a/arch/arm/mach-mx3/iomux.c b/arch/arm/mach-mx3/iomux-imx31.c
index c66ccbcdc11..a1d7fa5123d 100644
--- a/arch/arm/mach-mx3/iomux.c
+++ b/arch/arm/mach-mx3/iomux-imx31.c
@@ -29,7 +29,7 @@
29/* 29/*
30 * IOMUX register (base) addresses 30 * IOMUX register (base) addresses
31 */ 31 */
32#define IOMUX_BASE IO_ADDRESS(IOMUXC_BASE_ADDR) 32#define IOMUX_BASE MX31_IO_ADDRESS(MX31_IOMUXC_BASE_ADDR)
33#define IOMUXINT_OBS1 (IOMUX_BASE + 0x000) 33#define IOMUXINT_OBS1 (IOMUX_BASE + 0x000)
34#define IOMUXINT_OBS2 (IOMUX_BASE + 0x004) 34#define IOMUXINT_OBS2 (IOMUX_BASE + 0x004)
35#define IOMUXGPR (IOMUX_BASE + 0x008) 35#define IOMUXGPR (IOMUX_BASE + 0x008)
diff --git a/arch/arm/mach-mx3/armadillo5x0.c b/arch/arm/mach-mx3/mach-armadillo5x0.c
index 54aab401dbd..1fed146324f 100644
--- a/arch/arm/mach-mx3/armadillo5x0.c
+++ b/arch/arm/mach-mx3/mach-armadillo5x0.c
@@ -182,8 +182,8 @@ static struct physmap_flash_data armadillo5x0_nor_flash_pdata = {
182 182
183static struct resource armadillo5x0_nor_flash_resource = { 183static struct resource armadillo5x0_nor_flash_resource = {
184 .flags = IORESOURCE_MEM, 184 .flags = IORESOURCE_MEM,
185 .start = CS0_BASE_ADDR, 185 .start = MX31_CS0_BASE_ADDR,
186 .end = CS0_BASE_ADDR + SZ_64M - 1, 186 .end = MX31_CS0_BASE_ADDR + SZ_64M - 1,
187}; 187};
188 188
189static struct platform_device armadillo5x0_nor_flash = { 189static struct platform_device armadillo5x0_nor_flash = {
@@ -311,8 +311,8 @@ static struct imxmmc_platform_data sdhc_pdata = {
311 */ 311 */
312static struct resource armadillo5x0_smc911x_resources[] = { 312static struct resource armadillo5x0_smc911x_resources[] = {
313 { 313 {
314 .start = CS3_BASE_ADDR, 314 .start = MX31_CS3_BASE_ADDR,
315 .end = CS3_BASE_ADDR + SZ_32M - 1, 315 .end = MX31_CS3_BASE_ADDR + SZ_32M - 1,
316 .flags = IORESOURCE_MEM, 316 .flags = IORESOURCE_MEM,
317 }, { 317 }, {
318 .start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0), 318 .start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0),
@@ -406,8 +406,8 @@ static struct sys_timer armadillo5x0_timer = {
406 406
407MACHINE_START(ARMADILLO5X0, "Armadillo-500") 407MACHINE_START(ARMADILLO5X0, "Armadillo-500")
408 /* Maintainer: Alberto Panizzo */ 408 /* Maintainer: Alberto Panizzo */
409 .phys_io = AIPS1_BASE_ADDR, 409 .phys_io = MX31_AIPS1_BASE_ADDR,
410 .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, 410 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
411 .boot_params = PHYS_OFFSET + 0x00000100, 411 .boot_params = PHYS_OFFSET + 0x00000100,
412 .map_io = mx31_map_io, 412 .map_io = mx31_map_io,
413 .init_irq = mx31_init_irq, 413 .init_irq = mx31_init_irq,
diff --git a/arch/arm/mach-mx3/kzmarm11.c b/arch/arm/mach-mx3/mach-kzm_arm11_01.c
index 6fa99ce3008..2484dddca54 100644
--- a/arch/arm/mach-mx3/kzmarm11.c
+++ b/arch/arm/mach-mx3/mach-kzm_arm11_01.c
@@ -46,13 +46,18 @@
46 46
47#include "devices.h" 47#include "devices.h"
48 48
49#define KZM_ARM11_IO_ADDRESS(x) ( \
50 IMX_IO_ADDRESS(x, MX31_CS4) ?: \
51 IMX_IO_ADDRESS(x, MX31_CS5) ?: \
52 MX31_IO_ADDRESS(x))
53
49#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) 54#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
50/* 55/*
51 * KZM-ARM11-01 has an external UART on FPGA 56 * KZM-ARM11-01 has an external UART on FPGA
52 */ 57 */
53static struct plat_serial8250_port serial_platform_data[] = { 58static struct plat_serial8250_port serial_platform_data[] = {
54 { 59 {
55 .membase = IO_ADDRESS(KZM_ARM11_16550), 60 .membase = KZM_ARM11_IO_ADDRESS(KZM_ARM11_16550),
56 .mapbase = KZM_ARM11_16550, 61 .mapbase = KZM_ARM11_16550,
57 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), 62 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1),
58 .irqflags = IRQ_TYPE_EDGE_RISING, 63 .irqflags = IRQ_TYPE_EDGE_RISING,
@@ -102,9 +107,9 @@ static int __init kzm_init_ext_uart(void)
102 /* 107 /*
103 * Unmask UART interrupt 108 * Unmask UART interrupt
104 */ 109 */
105 tmp = __raw_readb(IO_ADDRESS(KZM_ARM11_CTL1)); 110 tmp = __raw_readb(KZM_ARM11_IO_ADDRESS(KZM_ARM11_CTL1));
106 tmp |= 0x2; 111 tmp |= 0x2;
107 __raw_writeb(tmp, IO_ADDRESS(KZM_ARM11_CTL1)); 112 __raw_writeb(tmp, KZM_ARM11_IO_ADDRESS(KZM_ARM11_CTL1));
108 113
109 return platform_device_register(&serial_device); 114 return platform_device_register(&serial_device);
110} 115}
@@ -128,8 +133,8 @@ static struct smsc911x_platform_config kzm_smsc9118_config = {
128 133
129static struct resource kzm_smsc9118_resources[] = { 134static struct resource kzm_smsc9118_resources[] = {
130 { 135 {
131 .start = CS5_BASE_ADDR, 136 .start = MX31_CS5_BASE_ADDR,
132 .end = CS5_BASE_ADDR + SZ_128K - 1, 137 .end = MX31_CS5_BASE_ADDR + SZ_128K - 1,
133 .flags = IORESOURCE_MEM, 138 .flags = IORESOURCE_MEM,
134 }, 139 },
135 { 140 {
@@ -222,15 +227,15 @@ static void __init kzm_board_init(void)
222 */ 227 */
223static struct map_desc kzm_io_desc[] __initdata = { 228static struct map_desc kzm_io_desc[] __initdata = {
224 { 229 {
225 .virtual = CS4_BASE_ADDR_VIRT, 230 .virtual = MX31_CS4_BASE_ADDR_VIRT,
226 .pfn = __phys_to_pfn(CS4_BASE_ADDR), 231 .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
227 .length = CS4_SIZE, 232 .length = MX31_CS4_SIZE,
228 .type = MT_DEVICE 233 .type = MT_DEVICE
229 }, 234 },
230 { 235 {
231 .virtual = CS5_BASE_ADDR_VIRT, 236 .virtual = MX31_CS5_BASE_ADDR_VIRT,
232 .pfn = __phys_to_pfn(CS5_BASE_ADDR), 237 .pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
233 .length = CS5_SIZE, 238 .length = MX31_CS5_SIZE,
234 .type = MT_DEVICE 239 .type = MT_DEVICE
235 }, 240 },
236}; 241};
@@ -258,8 +263,8 @@ static struct sys_timer kzm_timer = {
258 * initialize __mach_desc_KZM_ARM11_01 data structure. 263 * initialize __mach_desc_KZM_ARM11_01 data structure.
259 */ 264 */
260MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01") 265MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01")
261 .phys_io = AIPS1_BASE_ADDR, 266 .phys_io = MX31_AIPS1_BASE_ADDR,
262 .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, 267 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
263 .boot_params = PHYS_OFFSET + 0x100, 268 .boot_params = PHYS_OFFSET + 0x100,
264 .map_io = kzm_map_io, 269 .map_io = kzm_map_io,
265 .init_irq = mx31_init_irq, 270 .init_irq = mx31_init_irq,
diff --git a/arch/arm/mach-mx3/mx31pdk.c b/arch/arm/mach-mx3/mach-mx31_3ds.c
index 0f7a2f06bc2..88af58514a7 100644
--- a/arch/arm/mach-mx3/mx31pdk.c
+++ b/arch/arm/mach-mx3/mach-mx31_3ds.c
@@ -211,14 +211,9 @@ static int __init mx31pdk_init_expio(void)
211 */ 211 */
212static struct map_desc mx31pdk_io_desc[] __initdata = { 212static struct map_desc mx31pdk_io_desc[] __initdata = {
213 { 213 {
214 .virtual = SPBA0_BASE_ADDR_VIRT, 214 .virtual = MX31_CS5_BASE_ADDR_VIRT,
215 .pfn = __phys_to_pfn(SPBA0_BASE_ADDR), 215 .pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
216 .length = SPBA0_SIZE, 216 .length = MX31_CS5_SIZE,
217 .type = MT_DEVICE_NONSHARED,
218 }, {
219 .virtual = CS5_BASE_ADDR_VIRT,
220 .pfn = __phys_to_pfn(CS5_BASE_ADDR),
221 .length = CS5_SIZE,
222 .type = MT_DEVICE, 217 .type = MT_DEVICE,
223 }, 218 },
224}; 219};
@@ -261,8 +256,8 @@ static struct sys_timer mx31pdk_timer = {
261 */ 256 */
262MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)") 257MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
263 /* Maintainer: Freescale Semiconductor, Inc. */ 258 /* Maintainer: Freescale Semiconductor, Inc. */
264 .phys_io = AIPS1_BASE_ADDR, 259 .phys_io = MX31_AIPS1_BASE_ADDR,
265 .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, 260 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
266 .boot_params = PHYS_OFFSET + 0x100, 261 .boot_params = PHYS_OFFSET + 0x100,
267 .map_io = mx31pdk_map_io, 262 .map_io = mx31pdk_map_io,
268 .init_irq = mx31_init_irq, 263 .init_irq = mx31_init_irq,
diff --git a/arch/arm/mach-mx3/mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c
index 718fbe6615e..286f2179ecb 100644
--- a/arch/arm/mach-mx3/mx31ads.c
+++ b/arch/arm/mach-mx3/mach-mx31ads.c
@@ -60,7 +60,7 @@
60static struct plat_serial8250_port serial_platform_data[] = { 60static struct plat_serial8250_port serial_platform_data[] = {
61 { 61 {
62 .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA), 62 .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
63 .mapbase = (unsigned long)(CS4_BASE_ADDR + PBC_SC16C652_UARTA), 63 .mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTA),
64 .irq = EXPIO_INT_XUART_INTA, 64 .irq = EXPIO_INT_XUART_INTA,
65 .uartclk = 14745600, 65 .uartclk = 14745600,
66 .regshift = 0, 66 .regshift = 0,
@@ -68,7 +68,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
68 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ, 68 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
69 }, { 69 }, {
70 .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB), 70 .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
71 .mapbase = (unsigned long)(CS4_BASE_ADDR + PBC_SC16C652_UARTB), 71 .mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTB),
72 .irq = EXPIO_INT_XUART_INTB, 72 .irq = EXPIO_INT_XUART_INTB,
73 .uartclk = 14745600, 73 .uartclk = 14745600,
74 .regshift = 0, 74 .regshift = 0,
@@ -486,14 +486,9 @@ static void mxc_init_i2c(void)
486 */ 486 */
487static struct map_desc mx31ads_io_desc[] __initdata = { 487static struct map_desc mx31ads_io_desc[] __initdata = {
488 { 488 {
489 .virtual = SPBA0_BASE_ADDR_VIRT, 489 .virtual = MX31_CS4_BASE_ADDR_VIRT,
490 .pfn = __phys_to_pfn(SPBA0_BASE_ADDR), 490 .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
491 .length = SPBA0_SIZE, 491 .length = MX31_CS4_SIZE / 2,
492 .type = MT_DEVICE_NONSHARED
493 }, {
494 .virtual = CS4_BASE_ADDR_VIRT,
495 .pfn = __phys_to_pfn(CS4_BASE_ADDR),
496 .length = CS4_SIZE / 2,
497 .type = MT_DEVICE 492 .type = MT_DEVICE
498 }, 493 },
499}; 494};
@@ -538,8 +533,8 @@ static struct sys_timer mx31ads_timer = {
538 */ 533 */
539MACHINE_START(MX31ADS, "Freescale MX31ADS") 534MACHINE_START(MX31ADS, "Freescale MX31ADS")
540 /* Maintainer: Freescale Semiconductor, Inc. */ 535 /* Maintainer: Freescale Semiconductor, Inc. */
541 .phys_io = AIPS1_BASE_ADDR, 536 .phys_io = MX31_AIPS1_BASE_ADDR,
542 .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, 537 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
543 .boot_params = PHYS_OFFSET + 0x100, 538 .boot_params = PHYS_OFFSET + 0x100,
544 .map_io = mx31ads_map_io, 539 .map_io = mx31ads_map_io,
545 .init_irq = mx31ads_init_irq, 540 .init_irq = mx31ads_init_irq,
diff --git a/arch/arm/mach-mx3/mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c
index 9ce029f554b..9225cb72dd0 100644
--- a/arch/arm/mach-mx3/mx31lilly.c
+++ b/arch/arm/mach-mx3/mach-mx31lilly.c
@@ -57,8 +57,8 @@
57 57
58static struct resource smsc91x_resources[] = { 58static struct resource smsc91x_resources[] = {
59 { 59 {
60 .start = CS4_BASE_ADDR, 60 .start = MX31_CS4_BASE_ADDR,
61 .end = CS4_BASE_ADDR + 0xffff, 61 .end = MX31_CS4_BASE_ADDR + 0xffff,
62 .flags = IORESOURCE_MEM, 62 .flags = IORESOURCE_MEM,
63 }, 63 },
64 { 64 {
@@ -195,8 +195,8 @@ static struct sys_timer mx31lilly_timer = {
195}; 195};
196 196
197MACHINE_START(LILLY1131, "INCO startec LILLY-1131") 197MACHINE_START(LILLY1131, "INCO startec LILLY-1131")
198 .phys_io = AIPS1_BASE_ADDR, 198 .phys_io = MX31_AIPS1_BASE_ADDR,
199 .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, 199 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
200 .boot_params = PHYS_OFFSET + 0x100, 200 .boot_params = PHYS_OFFSET + 0x100,
201 .map_io = mx31_map_io, 201 .map_io = mx31_map_io,
202 .init_irq = mx31_init_irq, 202 .init_irq = mx31_init_irq,
diff --git a/arch/arm/mach-mx3/mx31lite.c b/arch/arm/mach-mx3/mach-mx31lite.c
index def6b673659..8589e3d1dad 100644
--- a/arch/arm/mach-mx3/mx31lite.c
+++ b/arch/arm/mach-mx3/mach-mx31lite.c
@@ -82,8 +82,8 @@ static struct smsc911x_platform_config smsc911x_config = {
82 82
83static struct resource smsc911x_resources[] = { 83static struct resource smsc911x_resources[] = {
84 { 84 {
85 .start = CS4_BASE_ADDR, 85 .start = MX31_CS4_BASE_ADDR,
86 .end = CS4_BASE_ADDR + 0x100, 86 .end = MX31_CS4_BASE_ADDR + 0x100,
87 .flags = IORESOURCE_MEM, 87 .flags = IORESOURCE_MEM,
88 }, { 88 }, {
89 .start = IOMUX_TO_IRQ(MX31_PIN_SFS6), 89 .start = IOMUX_TO_IRQ(MX31_PIN_SFS6),
@@ -135,6 +135,7 @@ static struct spi_board_info mc13783_spi_dev __initdata = {
135 * USB 135 * USB
136 */ 136 */
137 137
138#if defined(CONFIG_USB_ULPI)
138#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ 139#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
139 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) 140 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
140 141
@@ -180,6 +181,7 @@ static struct mxc_usbh_platform_data usbh2_pdata = {
180 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, 181 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
181 .flags = MXC_EHCI_POWER_PINS_ENABLED, 182 .flags = MXC_EHCI_POWER_PINS_ENABLED,
182}; 183};
184#endif
183 185
184/* 186/*
185 * NOR flash 187 * NOR flash
@@ -212,14 +214,9 @@ static struct platform_device physmap_flash_device = {
212 */ 214 */
213static struct map_desc mx31lite_io_desc[] __initdata = { 215static struct map_desc mx31lite_io_desc[] __initdata = {
214 { 216 {
215 .virtual = SPBA0_BASE_ADDR_VIRT, 217 .virtual = MX31_CS4_BASE_ADDR_VIRT,
216 .pfn = __phys_to_pfn(SPBA0_BASE_ADDR), 218 .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
217 .length = SPBA0_SIZE, 219 .length = MX31_CS4_SIZE,
218 .type = MT_DEVICE_NONSHARED
219 }, {
220 .virtual = CS4_BASE_ADDR_VIRT,
221 .pfn = __phys_to_pfn(CS4_BASE_ADDR),
222 .length = CS4_SIZE,
223 .type = MT_DEVICE 220 .type = MT_DEVICE
224 } 221 }
225}; 222};
@@ -261,11 +258,13 @@ static void __init mxc_board_init(void)
261 mxc_register_device(&mxc_spi_device1, &spi1_pdata); 258 mxc_register_device(&mxc_spi_device1, &spi1_pdata);
262 spi_register_board_info(&mc13783_spi_dev, 1); 259 spi_register_board_info(&mc13783_spi_dev, 1);
263 260
261#if defined(CONFIG_USB_ULPI)
264 /* USB */ 262 /* USB */
265 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 263 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
266 USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); 264 USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
267 265
268 mxc_register_device(&mxc_usbh2, &usbh2_pdata); 266 mxc_register_device(&mxc_usbh2, &usbh2_pdata);
267#endif
269 268
270 /* SMSC9117 IRQ pin */ 269 /* SMSC9117 IRQ pin */
271 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq"); 270 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq");
@@ -288,8 +287,8 @@ struct sys_timer mx31lite_timer = {
288 287
289MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM") 288MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM")
290 /* Maintainer: Freescale Semiconductor, Inc. */ 289 /* Maintainer: Freescale Semiconductor, Inc. */
291 .phys_io = AIPS1_BASE_ADDR, 290 .phys_io = MX31_AIPS1_BASE_ADDR,
292 .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, 291 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
293 .boot_params = PHYS_OFFSET + 0x100, 292 .boot_params = PHYS_OFFSET + 0x100,
294 .map_io = mx31lite_map_io, 293 .map_io = mx31lite_map_io,
295 .init_irq = mx31_init_irq, 294 .init_irq = mx31_init_irq,
diff --git a/arch/arm/mach-mx3/mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c
index b7052914593..63f991f8817 100644
--- a/arch/arm/mach-mx3/mx31moboard.c
+++ b/arch/arm/mach-mx3/mach-mx31moboard.c
@@ -346,6 +346,8 @@ static struct fsl_usb2_platform_data usb_pdata = {
346 .phy_mode = FSL_USB2_PHY_ULPI, 346 .phy_mode = FSL_USB2_PHY_ULPI,
347}; 347};
348 348
349#if defined(CONFIG_USB_ULPI)
350
349#define USBH2_EN_B IOMUX_TO_GPIO(MX31_PIN_SCK6) 351#define USBH2_EN_B IOMUX_TO_GPIO(MX31_PIN_SCK6)
350 352
351static int moboard_usbh2_hw_init(struct platform_device *pdev) 353static int moboard_usbh2_hw_init(struct platform_device *pdev)
@@ -392,8 +394,11 @@ static int __init moboard_usbh2_init(void)
392 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 394 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
393 USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); 395 USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
394 396
395 return mxc_register_device(&mx31_usbh2, &usbh2_pdata); 397 return mxc_register_device(&mxc_usbh2, &usbh2_pdata);
396} 398}
399#else
400static inline int moboard_usbh2_init(void) { return 0; }
401#endif
397 402
398 403
399static struct gpio_led mx31moboard_leds[] = { 404static struct gpio_led mx31moboard_leds[] = {
@@ -564,8 +569,8 @@ struct sys_timer mx31moboard_timer = {
564 569
565MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard") 570MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
566 /* Maintainer: Valentin Longchamp, EPFL Mobots group */ 571 /* Maintainer: Valentin Longchamp, EPFL Mobots group */
567 .phys_io = AIPS1_BASE_ADDR, 572 .phys_io = MX31_AIPS1_BASE_ADDR,
568 .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, 573 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
569 .boot_params = PHYS_OFFSET + 0x100, 574 .boot_params = PHYS_OFFSET + 0x100,
570 .map_io = mx31_map_io, 575 .map_io = mx31_map_io,
571 .init_irq = mx31_init_irq, 576 .init_irq = mx31_init_irq,
diff --git a/arch/arm/mach-mx3/mx35pdk.c b/arch/arm/mach-mx3/mach-mx35pdk.c
index 0bbc65ea23c..2d11bf053c7 100644
--- a/arch/arm/mach-mx3/mx35pdk.c
+++ b/arch/arm/mach-mx3/mach-mx35pdk.c
@@ -106,8 +106,8 @@ struct sys_timer mx35pdk_timer = {
106 106
107MACHINE_START(MX35_3DS, "Freescale MX35PDK") 107MACHINE_START(MX35_3DS, "Freescale MX35PDK")
108 /* Maintainer: Freescale Semiconductor, Inc */ 108 /* Maintainer: Freescale Semiconductor, Inc */
109 .phys_io = AIPS1_BASE_ADDR, 109 .phys_io = MX35_AIPS1_BASE_ADDR,
110 .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, 110 .io_pg_offst = ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
111 .boot_params = PHYS_OFFSET + 0x100, 111 .boot_params = PHYS_OFFSET + 0x100,
112 .map_io = mx35_map_io, 112 .map_io = mx35_map_io,
113 .init_irq = mx35_init_irq, 113 .init_irq = mx35_init_irq,
diff --git a/arch/arm/mach-mx3/pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c
index 6cbaabedf38..d9bd7d2b0ad 100644
--- a/arch/arm/mach-mx3/pcm037.c
+++ b/arch/arm/mach-mx3/mach-pcm037.c
@@ -248,8 +248,8 @@ static struct imxuart_platform_data uart_pdata = {
248 248
249static struct resource smsc911x_resources[] = { 249static struct resource smsc911x_resources[] = {
250 { 250 {
251 .start = CS1_BASE_ADDR + 0x300, 251 .start = MX31_CS1_BASE_ADDR + 0x300,
252 .end = CS1_BASE_ADDR + 0x300 + SZ_64K - 1, 252 .end = MX31_CS1_BASE_ADDR + 0x300 + SZ_64K - 1,
253 .flags = IORESOURCE_MEM, 253 .flags = IORESOURCE_MEM,
254 }, { 254 }, {
255 .start = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1), 255 .start = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
@@ -281,8 +281,8 @@ static struct platdata_mtd_ram pcm038_sram_data = {
281}; 281};
282 282
283static struct resource pcm038_sram_resource = { 283static struct resource pcm038_sram_resource = {
284 .start = CS4_BASE_ADDR, 284 .start = MX31_CS4_BASE_ADDR,
285 .end = CS4_BASE_ADDR + 512 * 1024 - 1, 285 .end = MX31_CS4_BASE_ADDR + 512 * 1024 - 1,
286 .flags = IORESOURCE_MEM, 286 .flags = IORESOURCE_MEM,
287}; 287};
288 288
@@ -322,16 +322,25 @@ static int pcm037_camera_power(struct device *dev, int on)
322 return 0; 322 return 0;
323} 323}
324 324
325static struct i2c_board_info pcm037_i2c_2_devices[] = { 325static struct i2c_board_info pcm037_i2c_camera[] = {
326 { 326 {
327 I2C_BOARD_INFO("mt9t031", 0x5d), 327 I2C_BOARD_INFO("mt9t031", 0x5d),
328 }, {
329 I2C_BOARD_INFO("mt9v022", 0x48),
328 }, 330 },
329}; 331};
330 332
331static struct soc_camera_link iclink = { 333static struct soc_camera_link iclink_mt9v022 = {
334 .bus_id = 0, /* Must match with the camera ID */
335 .board_info = &pcm037_i2c_camera[1],
336 .i2c_adapter_id = 2,
337 .module_name = "mt9v022",
338};
339
340static struct soc_camera_link iclink_mt9t031 = {
332 .bus_id = 0, /* Must match with the camera ID */ 341 .bus_id = 0, /* Must match with the camera ID */
333 .power = pcm037_camera_power, 342 .power = pcm037_camera_power,
334 .board_info = &pcm037_i2c_2_devices[0], 343 .board_info = &pcm037_i2c_camera[0],
335 .i2c_adapter_id = 2, 344 .i2c_adapter_id = 2,
336 .module_name = "mt9t031", 345 .module_name = "mt9t031",
337}; 346};
@@ -345,11 +354,19 @@ static struct i2c_board_info pcm037_i2c_devices[] = {
345 } 354 }
346}; 355};
347 356
348static struct platform_device pcm037_camera = { 357static struct platform_device pcm037_mt9t031 = {
349 .name = "soc-camera-pdrv", 358 .name = "soc-camera-pdrv",
350 .id = 0, 359 .id = 0,
351 .dev = { 360 .dev = {
352 .platform_data = &iclink, 361 .platform_data = &iclink_mt9t031,
362 },
363};
364
365static struct platform_device pcm037_mt9v022 = {
366 .name = "soc-camera-pdrv",
367 .id = 1,
368 .dev = {
369 .platform_data = &iclink_mt9v022,
353 }, 370 },
354}; 371};
355 372
@@ -449,7 +466,8 @@ static int __init pcm037_camera_alloc_dma(const size_t buf_size)
449static struct platform_device *devices[] __initdata = { 466static struct platform_device *devices[] __initdata = {
450 &pcm037_flash, 467 &pcm037_flash,
451 &pcm037_sram_device, 468 &pcm037_sram_device,
452 &pcm037_camera, 469 &pcm037_mt9t031,
470 &pcm037_mt9v022,
453}; 471};
454 472
455static struct ipu_platform_data mx3_ipu_data = { 473static struct ipu_platform_data mx3_ipu_data = {
@@ -518,8 +536,8 @@ static struct mx3fb_platform_data mx3fb_pdata = {
518 536
519static struct resource pcm970_sja1000_resources[] = { 537static struct resource pcm970_sja1000_resources[] = {
520 { 538 {
521 .start = CS5_BASE_ADDR, 539 .start = MX31_CS5_BASE_ADDR,
522 .end = CS5_BASE_ADDR + 0x100 - 1, 540 .end = MX31_CS5_BASE_ADDR + 0x100 - 1,
523 .flags = IORESOURCE_MEM, 541 .flags = IORESOURCE_MEM,
524 }, { 542 }, {
525 .start = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)), 543 .start = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
@@ -599,7 +617,7 @@ static void __init mxc_board_init(void)
599 if (!ret) 617 if (!ret)
600 gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), 1); 618 gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), 1);
601 else 619 else
602 iclink.power = NULL; 620 iclink_mt9t031.power = NULL;
603 621
604 if (!pcm037_camera_alloc_dma(4 * 1024 * 1024)) 622 if (!pcm037_camera_alloc_dma(4 * 1024 * 1024))
605 mxc_register_device(&mx3_camera, &camera_pdata); 623 mxc_register_device(&mx3_camera, &camera_pdata);
@@ -618,8 +636,8 @@ struct sys_timer pcm037_timer = {
618 636
619MACHINE_START(PCM037, "Phytec Phycore pcm037") 637MACHINE_START(PCM037, "Phytec Phycore pcm037")
620 /* Maintainer: Pengutronix */ 638 /* Maintainer: Pengutronix */
621 .phys_io = AIPS1_BASE_ADDR, 639 .phys_io = MX31_AIPS1_BASE_ADDR,
622 .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, 640 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
623 .boot_params = PHYS_OFFSET + 0x100, 641 .boot_params = PHYS_OFFSET + 0x100,
624 .map_io = mx31_map_io, 642 .map_io = mx31_map_io,
625 .init_irq = mx31_init_irq, 643 .init_irq = mx31_init_irq,
diff --git a/arch/arm/mach-mx3/pcm037_eet.c b/arch/arm/mach-mx3/mach-pcm037_eet.c
index 8d386000fc4..8d386000fc4 100644
--- a/arch/arm/mach-mx3/pcm037_eet.c
+++ b/arch/arm/mach-mx3/mach-pcm037_eet.c
diff --git a/arch/arm/mach-mx3/pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c
index e3aa829be58..1212194fb9c 100644
--- a/arch/arm/mach-mx3/pcm043.c
+++ b/arch/arm/mach-mx3/mach-pcm043.c
@@ -248,8 +248,8 @@ struct sys_timer pcm043_timer = {
248 248
249MACHINE_START(PCM043, "Phytec Phycore pcm043") 249MACHINE_START(PCM043, "Phytec Phycore pcm043")
250 /* Maintainer: Pengutronix */ 250 /* Maintainer: Pengutronix */
251 .phys_io = AIPS1_BASE_ADDR, 251 .phys_io = MX35_AIPS1_BASE_ADDR,
252 .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, 252 .io_pg_offst = ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
253 .boot_params = PHYS_OFFSET + 0x100, 253 .boot_params = PHYS_OFFSET + 0x100,
254 .map_io = mx35_map_io, 254 .map_io = mx35_map_io,
255 .init_irq = mx35_init_irq, 255 .init_irq = mx35_init_irq,
diff --git a/arch/arm/mach-mx3/qong.c b/arch/arm/mach-mx3/mach-qong.c
index 044511f1b9a..fdb819ae0e6 100644
--- a/arch/arm/mach-mx3/qong.c
+++ b/arch/arm/mach-mx3/mach-qong.c
@@ -43,7 +43,7 @@
43#define QONG_FPGA_VERSION(major, minor, rev) \ 43#define QONG_FPGA_VERSION(major, minor, rev) \
44 (((major & 0xF) << 12) | ((minor & 0xF) << 8) | (rev & 0xFF)) 44 (((major & 0xF) << 12) | ((minor & 0xF) << 8) | (rev & 0xFF))
45 45
46#define QONG_FPGA_BASEADDR CS1_BASE_ADDR 46#define QONG_FPGA_BASEADDR MX31_CS1_BASE_ADDR
47#define QONG_FPGA_PERIPH_SIZE (1 << 24) 47#define QONG_FPGA_PERIPH_SIZE (1 << 24)
48 48
49#define QONG_FPGA_CTRL_BASEADDR QONG_FPGA_BASEADDR 49#define QONG_FPGA_CTRL_BASEADDR QONG_FPGA_BASEADDR
@@ -115,8 +115,8 @@ static struct physmap_flash_data qong_flash_data = {
115}; 115};
116 116
117static struct resource qong_flash_resource = { 117static struct resource qong_flash_resource = {
118 .start = CS0_BASE_ADDR, 118 .start = MX31_CS0_BASE_ADDR,
119 .end = CS0_BASE_ADDR + QONG_NOR_SIZE - 1, 119 .end = MX31_CS0_BASE_ADDR + QONG_NOR_SIZE - 1,
120 .flags = IORESOURCE_MEM, 120 .flags = IORESOURCE_MEM,
121}; 121};
122 122
@@ -180,8 +180,8 @@ static struct platform_nand_data qong_nand_data = {
180}; 180};
181 181
182static struct resource qong_nand_resource = { 182static struct resource qong_nand_resource = {
183 .start = CS3_BASE_ADDR, 183 .start = MX31_CS3_BASE_ADDR,
184 .end = CS3_BASE_ADDR + SZ_32M - 1, 184 .end = MX31_CS3_BASE_ADDR + SZ_32M - 1,
185 .flags = IORESOURCE_MEM, 185 .flags = IORESOURCE_MEM,
186}; 186};
187 187
@@ -198,9 +198,7 @@ static struct platform_device qong_nand_device = {
198static void __init qong_init_nand_mtd(void) 198static void __init qong_init_nand_mtd(void)
199{ 199{
200 /* init CS */ 200 /* init CS */
201 __raw_writel(0x00004f00, CSCR_U(3)); 201 mx31_setup_weimcs(3, 0x00004f00, 0x20013b31, 0x00020800);
202 __raw_writel(0x20013b31, CSCR_L(3));
203 __raw_writel(0x00020800, CSCR_A(3));
204 mxc_iomux_set_gpr(MUX_SDCTL_CSD1_SEL, true); 202 mxc_iomux_set_gpr(MUX_SDCTL_CSD1_SEL, true);
205 203
206 /* enable pin */ 204 /* enable pin */
@@ -275,8 +273,8 @@ static struct sys_timer qong_timer = {
275 273
276MACHINE_START(QONG, "Dave/DENX QongEVB-LITE") 274MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
277 /* Maintainer: DENX Software Engineering GmbH */ 275 /* Maintainer: DENX Software Engineering GmbH */
278 .phys_io = AIPS1_BASE_ADDR, 276 .phys_io = MX31_AIPS1_BASE_ADDR,
279 .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, 277 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
280 .boot_params = PHYS_OFFSET + 0x100, 278 .boot_params = PHYS_OFFSET + 0x100,
281 .map_io = mx31_map_io, 279 .map_io = mx31_map_io,
282 .init_irq = mx31_init_irq, 280 .init_irq = mx31_init_irq,
diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c
index bedf5b8d976..6858a4f9806 100644
--- a/arch/arm/mach-mx3/mm.c
+++ b/arch/arm/mach-mx3/mm.c
@@ -65,6 +65,11 @@ static struct map_desc mxc_io_desc[] __initdata = {
65 .pfn = __phys_to_pfn(AIPS2_BASE_ADDR), 65 .pfn = __phys_to_pfn(AIPS2_BASE_ADDR),
66 .length = AIPS2_SIZE, 66 .length = AIPS2_SIZE,
67 .type = MT_DEVICE_NONSHARED 67 .type = MT_DEVICE_NONSHARED
68 }, {
69 .virtual = SPBA0_BASE_ADDR_VIRT,
70 .pfn = __phys_to_pfn(SPBA0_BASE_ADDR),
71 .length = SPBA0_SIZE,
72 .type = MT_DEVICE_NONSHARED
68 }, 73 },
69}; 74};
70 75
diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c
index 8fc624f141c..438428eaf76 100644
--- a/arch/arm/mach-mx3/mx31moboard-devboard.c
+++ b/arch/arm/mach-mx3/mx31moboard-devboard.c
@@ -179,7 +179,7 @@ static int __init devboard_usbh1_init(void)
179 179
180 usbh1_pdata.otg = otg; 180 usbh1_pdata.otg = otg;
181 181
182 return mxc_register_device(&mx31_usbh1, &usbh1_pdata); 182 return mxc_register_device(&mxc_usbh1, &usbh1_pdata);
183} 183}
184 184
185/* 185/*
diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c
index 85184a35e67..1f44b9ccbb0 100644
--- a/arch/arm/mach-mx3/mx31moboard-marxbot.c
+++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c
@@ -294,7 +294,7 @@ static int __init marxbot_usbh1_init(void)
294 294
295 usbh1_pdata.otg = otg; 295 usbh1_pdata.otg = otg;
296 296
297 return mxc_register_device(&mx31_usbh1, &usbh1_pdata); 297 return mxc_register_device(&mxc_usbh1, &usbh1_pdata);
298} 298}
299 299
300/* 300/*
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 996cbac6932..7322bca8f5f 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -7,9 +7,13 @@ obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o
7 7
8obj-$(CONFIG_ARCH_MX1) += iomux-mx1-mx2.o dma-mx1-mx2.o 8obj-$(CONFIG_ARCH_MX1) += iomux-mx1-mx2.o dma-mx1-mx2.o
9obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o 9obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o
10CFLAGS_iomux-mx1-mx2.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
11CFLAGS_dma-mx1-mx2.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
10obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o 12obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
11obj-$(CONFIG_MXC_PWM) += pwm.o 13obj-$(CONFIG_MXC_PWM) += pwm.o
12obj-$(CONFIG_USB_EHCI_MXC) += ehci.o 14obj-$(CONFIG_USB_EHCI_MXC) += ehci.o
13obj-$(CONFIG_MXC_ULPI) += ulpi.o 15obj-$(CONFIG_MXC_ULPI) += ulpi.o
14obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o 16obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o
17CFLAGS_audmux-v1.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
15obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o 18obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o
19CFLAGS_audmux-v2.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c
index 41599be882e..8df03f36295 100644
--- a/arch/arm/plat-mxc/ehci.c
+++ b/arch/arm/plat-mxc/ehci.c
@@ -43,7 +43,7 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
43 unsigned int v; 43 unsigned int v;
44 44
45 if (cpu_is_mx31()) { 45 if (cpu_is_mx31()) {
46 v = readl(IO_ADDRESS(MX31_OTG_BASE_ADDR + 46 v = readl(MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR +
47 USBCTRL_OTGBASE_OFFSET)); 47 USBCTRL_OTGBASE_OFFSET));
48 48
49 switch (port) { 49 switch (port) {
@@ -79,7 +79,7 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
79 break; 79 break;
80 } 80 }
81 81
82 writel(v, IO_ADDRESS(MX31_OTG_BASE_ADDR + 82 writel(v, MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR +
83 USBCTRL_OTGBASE_OFFSET)); 83 USBCTRL_OTGBASE_OFFSET));
84 return 0; 84 return 0;
85 } 85 }
diff --git a/arch/arm/plat-mxc/include/mach/board-kzmarm11.h b/arch/arm/plat-mxc/include/mach/board-kzmarm11.h
index 05ff2f31ef1..93cc66f104c 100644
--- a/arch/arm/plat-mxc/include/mach/board-kzmarm11.h
+++ b/arch/arm/plat-mxc/include/mach/board-kzmarm11.h
@@ -21,19 +21,19 @@
21/* 21/*
22 * KZM-ARM11-01 Board Control Registers on FPGA 22 * KZM-ARM11-01 Board Control Registers on FPGA
23 */ 23 */
24#define KZM_ARM11_CTL1 (CS4_BASE_ADDR + 0x1000) 24#define KZM_ARM11_CTL1 (MX31_CS4_BASE_ADDR + 0x1000)
25#define KZM_ARM11_CTL2 (CS4_BASE_ADDR + 0x1001) 25#define KZM_ARM11_CTL2 (MX31_CS4_BASE_ADDR + 0x1001)
26#define KZM_ARM11_RSW1 (CS4_BASE_ADDR + 0x1002) 26#define KZM_ARM11_RSW1 (MX31_CS4_BASE_ADDR + 0x1002)
27#define KZM_ARM11_BACK_LIGHT (CS4_BASE_ADDR + 0x1004) 27#define KZM_ARM11_BACK_LIGHT (MX31_CS4_BASE_ADDR + 0x1004)
28#define KZM_ARM11_FPGA_REV (CS4_BASE_ADDR + 0x1008) 28#define KZM_ARM11_FPGA_REV (MX31_CS4_BASE_ADDR + 0x1008)
29#define KZM_ARM11_7SEG_LED (CS4_BASE_ADDR + 0x1010) 29#define KZM_ARM11_7SEG_LED (MX31_CS4_BASE_ADDR + 0x1010)
30#define KZM_ARM11_LEDS (CS4_BASE_ADDR + 0x1020) 30#define KZM_ARM11_LEDS (MX31_CS4_BASE_ADDR + 0x1020)
31#define KZM_ARM11_DIPSW2 (CS4_BASE_ADDR + 0x1003) 31#define KZM_ARM11_DIPSW2 (MX31_CS4_BASE_ADDR + 0x1003)
32 32
33/* 33/*
34 * External UART for touch panel on FPGA 34 * External UART for touch panel on FPGA
35 */ 35 */
36#define KZM_ARM11_16550 (CS4_BASE_ADDR + 0x1050) 36#define KZM_ARM11_16550 (MX31_CS4_BASE_ADDR + 0x1050)
37 37
38#endif /* __ARM_ARCH_BOARD_KZM_ARM11_H */ 38#endif /* __ARM_ARCH_BOARD_KZM_ARM11_H */
39 39
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31ads.h b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
index 2cbfa35e82f..095a199591c 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31ads.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
@@ -14,7 +14,7 @@
14#include <mach/hardware.h> 14#include <mach/hardware.h>
15 15
16/* Base address of PBC controller */ 16/* Base address of PBC controller */
17#define PBC_BASE_ADDRESS IO_ADDRESS(CS4_BASE_ADDR) 17#define PBC_BASE_ADDRESS MX31_CS4_BASE_ADDR_VIRT
18/* Offsets for the PBC Controller register */ 18/* Offsets for the PBC Controller register */
19 19
20/* PBC Board status register offset */ 20/* PBC Board status register offset */
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index 78db75475f6..db14c56930a 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -22,6 +22,11 @@
22 22
23#include <asm/sizes.h> 23#include <asm/sizes.h>
24 24
25#define IMX_IO_ADDRESS(addr, module) \
26 ((void __force __iomem *) \
27 (((unsigned long)((addr) - (module ## _BASE_ADDR)) < module ## _SIZE) ?\
28 (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0))
29
25#ifdef CONFIG_ARCH_MX3 30#ifdef CONFIG_ARCH_MX3
26#include <mach/mx3x.h> 31#include <mach/mx3x.h>
27#include <mach/mx31.h> 32#include <mach/mx31.h>
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx25.h b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
index 810c47f56e7..9af494f0ab3 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx25.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
@@ -58,19 +58,19 @@
58 58
59#define MX25_PAD_A18__A18 IOMUX_PAD(0x23c, 0x020, 0x10, 0, 0, NO_PAD_CTRL) 59#define MX25_PAD_A18__A18 IOMUX_PAD(0x23c, 0x020, 0x10, 0, 0, NO_PAD_CTRL)
60#define MX25_PAD_A18__GPIO_2_4 IOMUX_PAD(0x23c, 0x020, 0x15, 0, 0, NO_PAD_CTRL) 60#define MX25_PAD_A18__GPIO_2_4 IOMUX_PAD(0x23c, 0x020, 0x15, 0, 0, NO_PAD_CTRL)
61#define MX25_PAD_A18__FEC_COL IOMUX_PAD(0x23c, 0x020, 0x17, 0x504, 0, NO_PAD_CTL) 61#define MX25_PAD_A18__FEC_COL IOMUX_PAD(0x23c, 0x020, 0x17, 0x504, 0, NO_PAD_CTRL)
62 62
63#define MX25_PAD_A19__A19 IOMUX_PAD(0x240, 0x024, 0x10, 0, 0, NO_PAD_CTRL) 63#define MX25_PAD_A19__A19 IOMUX_PAD(0x240, 0x024, 0x10, 0, 0, NO_PAD_CTRL)
64#define MX25_PAD_A19__FEC_RX_ER IOMUX_PAD(0x240, 0x024, 0x17, 0x518, 0, NO_PAD_CTL) 64#define MX25_PAD_A19__FEC_RX_ER IOMUX_PAD(0x240, 0x024, 0x17, 0x518, 0, NO_PAD_CTRL)
65#define MX25_PAD_A19__GPIO_2_5 IOMUX_PAD(0x240, 0x024, 0x15, 0, 0, NO_PAD_CTRL) 65#define MX25_PAD_A19__GPIO_2_5 IOMUX_PAD(0x240, 0x024, 0x15, 0, 0, NO_PAD_CTRL)
66 66
67#define MX25_PAD_A20__A20 IOMUX_PAD(0x244, 0x028, 0x10, 0, 0, NO_PAD_CTRL) 67#define MX25_PAD_A20__A20 IOMUX_PAD(0x244, 0x028, 0x10, 0, 0, NO_PAD_CTRL)
68#define MX25_PAD_A20__GPIO_2_6 IOMUX_PAD(0x244, 0x028, 0x15, 0, 0, NO_PAD_CTRL) 68#define MX25_PAD_A20__GPIO_2_6 IOMUX_PAD(0x244, 0x028, 0x15, 0, 0, NO_PAD_CTRL)
69#define MX25_PAD_A20__FEC_RDATA2 IOMUX_PAD(0x244, 0x028, 0x17, 0x50c, 0, NO_PAD_CTL) 69#define MX25_PAD_A20__FEC_RDATA2 IOMUX_PAD(0x244, 0x028, 0x17, 0x50c, 0, NO_PAD_CTRL)
70 70
71#define MX25_PAD_A21__A21 IOMUX_PAD(0x248, 0x02c, 0x10, 0, 0, NO_PAD_CTRL) 71#define MX25_PAD_A21__A21 IOMUX_PAD(0x248, 0x02c, 0x10, 0, 0, NO_PAD_CTRL)
72#define MX25_PAD_A21__GPIO_2_7 IOMUX_PAD(0x248, 0x02c, 0x15, 0, 0, NO_PAD_CTRL) 72#define MX25_PAD_A21__GPIO_2_7 IOMUX_PAD(0x248, 0x02c, 0x15, 0, 0, NO_PAD_CTRL)
73#define MX25_PAD_A21__FEC_RDATA3 IOMUX_PAD(0x248, 0x02c, 0x17, 0x510, 0, NO_PAD_CTL) 73#define MX25_PAD_A21__FEC_RDATA3 IOMUX_PAD(0x248, 0x02c, 0x17, 0x510, 0, NO_PAD_CTRL)
74 74
75#define MX25_PAD_A22__A22 IOMUX_PAD(0x000, 0x030, 0x10, 0, 0, NO_PAD_CTRL) 75#define MX25_PAD_A22__A22 IOMUX_PAD(0x000, 0x030, 0x10, 0, 0, NO_PAD_CTRL)
76#define MX25_PAD_A22__GPIO_2_8 IOMUX_PAD(0x000, 0x030, 0x15, 0, 0, NO_PAD_CTRL) 76#define MX25_PAD_A22__GPIO_2_8 IOMUX_PAD(0x000, 0x030, 0x15, 0, 0, NO_PAD_CTRL)
@@ -80,11 +80,11 @@
80 80
81#define MX25_PAD_A24__A24 IOMUX_PAD(0x250, 0x038, 0x10, 0, 0, NO_PAD_CTRL) 81#define MX25_PAD_A24__A24 IOMUX_PAD(0x250, 0x038, 0x10, 0, 0, NO_PAD_CTRL)
82#define MX25_PAD_A24__GPIO_2_10 IOMUX_PAD(0x250, 0x038, 0x15, 0, 0, NO_PAD_CTRL) 82#define MX25_PAD_A24__GPIO_2_10 IOMUX_PAD(0x250, 0x038, 0x15, 0, 0, NO_PAD_CTRL)
83#define MX25_PAD_A24__FEC_RX_CLK IOMUX_PAD(0x250, 0x038, 0x17, 0x514, 0, NO_PAD_CTL) 83#define MX25_PAD_A24__FEC_RX_CLK IOMUX_PAD(0x250, 0x038, 0x17, 0x514, 0, NO_PAD_CTRL)
84 84
85#define MX25_PAD_A25__A25 IOMUX_PAD(0x254, 0x03c, 0x10, 0, 0, NO_PAD_CTRL) 85#define MX25_PAD_A25__A25 IOMUX_PAD(0x254, 0x03c, 0x10, 0, 0, NO_PAD_CTRL)
86#define MX25_PAD_A25__GPIO_2_11 IOMUX_PAD(0x254, 0x03c, 0x15, 0, 0, NO_PAD_CTRL) 86#define MX25_PAD_A25__GPIO_2_11 IOMUX_PAD(0x254, 0x03c, 0x15, 0, 0, NO_PAD_CTRL)
87#define MX25_PAD_A25__FEC_CRS IOMUX_PAD(0x254, 0x03c, 0x17, 0x508, 0, NO_PAD_CTL) 87#define MX25_PAD_A25__FEC_CRS IOMUX_PAD(0x254, 0x03c, 0x17, 0x508, 0, NO_PAD_CTRL)
88 88
89#define MX25_PAD_EB0__EB0 IOMUX_PAD(0x258, 0x040, 0x10, 0, 0, NO_PAD_CTRL) 89#define MX25_PAD_EB0__EB0 IOMUX_PAD(0x258, 0x040, 0x10, 0, 0, NO_PAD_CTRL)
90#define MX25_PAD_EB0__AUD4_TXD IOMUX_PAD(0x258, 0x040, 0x14, 0x464, 0, NO_PAD_CTRL) 90#define MX25_PAD_EB0__AUD4_TXD IOMUX_PAD(0x258, 0x040, 0x14, 0x464, 0, NO_PAD_CTRL)
@@ -112,7 +112,7 @@
112#define MX25_PAD_CS5__UART5_RTS IOMUX_PAD(0x268, 0x058, 0x13, 0x574, 0, NO_PAD_CTRL) 112#define MX25_PAD_CS5__UART5_RTS IOMUX_PAD(0x268, 0x058, 0x13, 0x574, 0, NO_PAD_CTRL)
113#define MX25_PAD_CS5__GPIO_3_21 IOMUX_PAD(0x268, 0x058, 0x15, 0, 0, NO_PAD_CTRL) 113#define MX25_PAD_CS5__GPIO_3_21 IOMUX_PAD(0x268, 0x058, 0x15, 0, 0, NO_PAD_CTRL)
114 114
115#define MX25_PAD_NF_CE0__NF_CE0 IOMUX_PAD(0x26c, 0x05c, 0x10, 0, 0, NO_PAD_CTL) 115#define MX25_PAD_NF_CE0__NF_CE0 IOMUX_PAD(0x26c, 0x05c, 0x10, 0, 0, NO_PAD_CTRL)
116#define MX25_PAD_NF_CE0__GPIO_3_22 IOMUX_PAD(0x26c, 0x05c, 0x15, 0, 0, NO_PAD_CTRL) 116#define MX25_PAD_NF_CE0__GPIO_3_22 IOMUX_PAD(0x26c, 0x05c, 0x15, 0, 0, NO_PAD_CTRL)
117 117
118#define MX25_PAD_ECB__ECB IOMUX_PAD(0x270, 0x060, 0x10, 0, 0, NO_PAD_CTRL) 118#define MX25_PAD_ECB__ECB IOMUX_PAD(0x270, 0x060, 0x10, 0, 0, NO_PAD_CTRL)
@@ -229,28 +229,28 @@
229#define MX25_PAD_LD7__GPIO_1_21 IOMUX_PAD(0x2dc, 0x0e4, 0x15, 0, 0, NO_PAD_CTRL) 229#define MX25_PAD_LD7__GPIO_1_21 IOMUX_PAD(0x2dc, 0x0e4, 0x15, 0, 0, NO_PAD_CTRL)
230 230
231#define MX25_PAD_LD8__LD8 IOMUX_PAD(0x2e0, 0x0e8, 0x10, 0, 0, NO_PAD_CTRL) 231#define MX25_PAD_LD8__LD8 IOMUX_PAD(0x2e0, 0x0e8, 0x10, 0, 0, NO_PAD_CTRL)
232#define MX25_PAD_LD8__FEC_TX_ERR IOMUX_PAD(0x2e0, 0x0e8, 0x15, 0, 0, NO_PAD_CTL) 232#define MX25_PAD_LD8__FEC_TX_ERR IOMUX_PAD(0x2e0, 0x0e8, 0x15, 0, 0, NO_PAD_CTRL)
233 233
234#define MX25_PAD_LD9__LD9 IOMUX_PAD(0x2e4, 0x0ec, 0x10, 0, 0, NO_PAD_CTRL) 234#define MX25_PAD_LD9__LD9 IOMUX_PAD(0x2e4, 0x0ec, 0x10, 0, 0, NO_PAD_CTRL)
235#define MX25_PAD_LD9__FEC_COL IOMUX_PAD(0x2e4, 0x0ec, 0x15, 0x504, 1, NO_PAD_CTL) 235#define MX25_PAD_LD9__FEC_COL IOMUX_PAD(0x2e4, 0x0ec, 0x15, 0x504, 1, NO_PAD_CTRL)
236 236
237#define MX25_PAD_LD10__LD10 IOMUX_PAD(0x2e8, 0x0f0, 0x10, 0, 0, NO_PAD_CTRL) 237#define MX25_PAD_LD10__LD10 IOMUX_PAD(0x2e8, 0x0f0, 0x10, 0, 0, NO_PAD_CTRL)
238#define MX25_PAD_LD10__FEC_RX_ER IOMUX_PAD(0x2e8, 0x0f0, 0x15, 0x518, 1, NO_PAD_CTL) 238#define MX25_PAD_LD10__FEC_RX_ER IOMUX_PAD(0x2e8, 0x0f0, 0x15, 0x518, 1, NO_PAD_CTRL)
239 239
240#define MX25_PAD_LD11__LD11 IOMUX_PAD(0x2ec, 0x0f4, 0x10, 0, 0, NO_PAD_CTRL) 240#define MX25_PAD_LD11__LD11 IOMUX_PAD(0x2ec, 0x0f4, 0x10, 0, 0, NO_PAD_CTRL)
241#define MX25_PAD_LD11__FEC_RDATA2 IOMUX_PAD(0x2ec, 0x0f4, 0x15, 0x50c, 1, NO_PAD_CTL) 241#define MX25_PAD_LD11__FEC_RDATA2 IOMUX_PAD(0x2ec, 0x0f4, 0x15, 0x50c, 1, NO_PAD_CTRL)
242 242
243#define MX25_PAD_LD12__LD12 IOMUX_PAD(0x2f0, 0x0f8, 0x10, 0, 0, NO_PAD_CTRL) 243#define MX25_PAD_LD12__LD12 IOMUX_PAD(0x2f0, 0x0f8, 0x10, 0, 0, NO_PAD_CTRL)
244#define MX25_PAD_LD12__FEC_RDATA3 IOMUX_PAD(0x2f0, 0x0f8, 0x15, 0x510, 1, NO_PAD_CTL) 244#define MX25_PAD_LD12__FEC_RDATA3 IOMUX_PAD(0x2f0, 0x0f8, 0x15, 0x510, 1, NO_PAD_CTRL)
245 245
246#define MX25_PAD_LD13__LD13 IOMUX_PAD(0x2f4, 0x0fc, 0x10, 0, 0, NO_PAD_CTRL) 246#define MX25_PAD_LD13__LD13 IOMUX_PAD(0x2f4, 0x0fc, 0x10, 0, 0, NO_PAD_CTRL)
247#define MX25_PAD_LD13__FEC_TDATA2 IOMUX_PAD(0x2f4, 0x0fc, 0x15, 0, 0, NO_PAD_CTL) 247#define MX25_PAD_LD13__FEC_TDATA2 IOMUX_PAD(0x2f4, 0x0fc, 0x15, 0, 0, NO_PAD_CTRL)
248 248
249#define MX25_PAD_LD14__LD14 IOMUX_PAD(0x2f8, 0x100, 0x10, 0, 0, NO_PAD_CTRL) 249#define MX25_PAD_LD14__LD14 IOMUX_PAD(0x2f8, 0x100, 0x10, 0, 0, NO_PAD_CTRL)
250#define MX25_PAD_LD14__FEC_TDATA3 IOMUX_PAD(0x2f8, 0x100, 0x15, 0, 0, NO_PAD_CTL) 250#define MX25_PAD_LD14__FEC_TDATA3 IOMUX_PAD(0x2f8, 0x100, 0x15, 0, 0, NO_PAD_CTRL)
251 251
252#define MX25_PAD_LD15__LD15 IOMUX_PAD(0x2fc, 0x104, 0x10, 0, 0, NO_PAD_CTRL) 252#define MX25_PAD_LD15__LD15 IOMUX_PAD(0x2fc, 0x104, 0x10, 0, 0, NO_PAD_CTRL)
253#define MX25_PAD_LD15__FEC_RX_CLK IOMUX_PAD(0x2fc, 0x104, 0x15, 0x514, 1, NO_PAD_CTL) 253#define MX25_PAD_LD15__FEC_RX_CLK IOMUX_PAD(0x2fc, 0x104, 0x15, 0x514, 1, NO_PAD_CTRL)
254 254
255#define MX25_PAD_HSYNC__HSYNC IOMUX_PAD(0x300, 0x108, 0x10, 0, 0, NO_PAD_CTRL) 255#define MX25_PAD_HSYNC__HSYNC IOMUX_PAD(0x300, 0x108, 0x10, 0, 0, NO_PAD_CTRL)
256#define MX25_PAD_HSYNC__GPIO_1_22 IOMUX_PAD(0x300, 0x108, 0x15, 0, 0, NO_PAD_CTRL) 256#define MX25_PAD_HSYNC__GPIO_1_22 IOMUX_PAD(0x300, 0x108, 0x15, 0, 0, NO_PAD_CTRL)
@@ -265,7 +265,7 @@
265#define MX25_PAD_OE_ACD__GPIO_1_25 IOMUX_PAD(0x30c, 0x114, 0x15, 0, 0, NO_PAD_CTRL) 265#define MX25_PAD_OE_ACD__GPIO_1_25 IOMUX_PAD(0x30c, 0x114, 0x15, 0, 0, NO_PAD_CTRL)
266 266
267#define MX25_PAD_CONTRAST__CONTRAST IOMUX_PAD(0x310, 0x118, 0x10, 0, 0, NO_PAD_CTRL) 267#define MX25_PAD_CONTRAST__CONTRAST IOMUX_PAD(0x310, 0x118, 0x10, 0, 0, NO_PAD_CTRL)
268#define MX25_PAD_CONTRAST__FEC_CRS IOMUX_PAD(0x310, 0x118, 0x15, 0x508, 1, NO_PAD_CTL) 268#define MX25_PAD_CONTRAST__FEC_CRS IOMUX_PAD(0x310, 0x118, 0x15, 0x508, 1, NO_PAD_CTRL)
269 269
270#define MX25_PAD_PWM__PWM IOMUX_PAD(0x314, 0x11c, 0x10, 0, 0, NO_PAD_CTRL) 270#define MX25_PAD_PWM__PWM IOMUX_PAD(0x314, 0x11c, 0x10, 0, 0, NO_PAD_CTRL)
271#define MX25_PAD_PWM__GPIO_1_26 IOMUX_PAD(0x314, 0x11c, 0x15, 0, 0, NO_PAD_CTRL) 271#define MX25_PAD_PWM__GPIO_1_26 IOMUX_PAD(0x314, 0x11c, 0x15, 0, 0, NO_PAD_CTRL)
@@ -354,19 +354,19 @@
354#define MX25_PAD_UART2_TXD__GPIO_4_27 IOMUX_PAD(0x37c, 0x184, 0x15, 0, 0, NO_PAD_CTRL) 354#define MX25_PAD_UART2_TXD__GPIO_4_27 IOMUX_PAD(0x37c, 0x184, 0x15, 0, 0, NO_PAD_CTRL)
355 355
356#define MX25_PAD_UART2_RTS__UART2_RTS IOMUX_PAD(0x380, 0x188, 0x10, 0, 0, NO_PAD_CTRL) 356#define MX25_PAD_UART2_RTS__UART2_RTS IOMUX_PAD(0x380, 0x188, 0x10, 0, 0, NO_PAD_CTRL)
357#define MX25_PAD_UART2_RTS__FEC_COL IOMUX_PAD(0x380, 0x188, 0x12, 0x504, 2, NO_PAD_CTL) 357#define MX25_PAD_UART2_RTS__FEC_COL IOMUX_PAD(0x380, 0x188, 0x12, 0x504, 2, NO_PAD_CTRL)
358#define MX25_PAD_UART2_RTS__GPIO_4_28 IOMUX_PAD(0x380, 0x188, 0x15, 0, 0, NO_PAD_CTRL) 358#define MX25_PAD_UART2_RTS__GPIO_4_28 IOMUX_PAD(0x380, 0x188, 0x15, 0, 0, NO_PAD_CTRL)
359 359
360#define MX25_PAD_UART2_CTS__FEC_RX_ER IOMUX_PAD(0x384, 0x18c, 0x12, 0x518, 2, NO_PAD_CTL) 360#define MX25_PAD_UART2_CTS__FEC_RX_ER IOMUX_PAD(0x384, 0x18c, 0x12, 0x518, 2, NO_PAD_CTRL)
361#define MX25_PAD_UART2_CTS__UART2_CTS IOMUX_PAD(0x384, 0x18c, 0x10, 0, 0, NO_PAD_CTRL) 361#define MX25_PAD_UART2_CTS__UART2_CTS IOMUX_PAD(0x384, 0x18c, 0x10, 0, 0, NO_PAD_CTRL)
362#define MX25_PAD_UART2_CTS__GPIO_4_29 IOMUX_PAD(0x384, 0x18c, 0x15, 0, 0, NO_PAD_CTRL) 362#define MX25_PAD_UART2_CTS__GPIO_4_29 IOMUX_PAD(0x384, 0x18c, 0x15, 0, 0, NO_PAD_CTRL)
363 363
364#define MX25_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x388, 0x190, 0x10, 0, 0, PAD_CTL_PUS_47K_UP) 364#define MX25_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x388, 0x190, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
365#define MX25_PAD_SD1_CMD__FEC_RDATA2 IOMUX_PAD(0x388, 0x190, 0x12, 0x50c, 2, NO_PAD_CTL) 365#define MX25_PAD_SD1_CMD__FEC_RDATA2 IOMUX_PAD(0x388, 0x190, 0x12, 0x50c, 2, NO_PAD_CTRL)
366#define MX25_PAD_SD1_CMD__GPIO_2_23 IOMUX_PAD(0x388, 0x190, 0x15, 0, 0, NO_PAD_CTRL) 366#define MX25_PAD_SD1_CMD__GPIO_2_23 IOMUX_PAD(0x388, 0x190, 0x15, 0, 0, NO_PAD_CTRL)
367 367
368#define MX25_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x38c, 0x194, 0x10, 0, 0, PAD_CTL_PUS_47K_UP) 368#define MX25_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x38c, 0x194, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
369#define MX25_PAD_SD1_CLK__FEC_RDATA3 IOMUX_PAD(0x38c, 0x194, 0x12, 0x510, 2, NO_PAD_CTL) 369#define MX25_PAD_SD1_CLK__FEC_RDATA3 IOMUX_PAD(0x38c, 0x194, 0x12, 0x510, 2, NO_PAD_CTRL)
370#define MX25_PAD_SD1_CLK__GPIO_2_24 IOMUX_PAD(0x38c, 0x194, 0x15, 0, 0, NO_PAD_CTRL) 370#define MX25_PAD_SD1_CLK__GPIO_2_24 IOMUX_PAD(0x38c, 0x194, 0x15, 0, 0, NO_PAD_CTRL)
371 371
372#define MX25_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x390, 0x198, 0x10, 0, 0, PAD_CTL_PUS_47K_UP) 372#define MX25_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x390, 0x198, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
@@ -377,11 +377,11 @@
377#define MX25_PAD_SD1_DATA1__GPIO_2_26 IOMUX_PAD(0x394, 0x19c, 0x15, 0, 0, NO_PAD_CTRL) 377#define MX25_PAD_SD1_DATA1__GPIO_2_26 IOMUX_PAD(0x394, 0x19c, 0x15, 0, 0, NO_PAD_CTRL)
378 378
379#define MX25_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x398, 0x1a0, 0x10, 0, 0, PAD_CTL_PUS_47K_UP) 379#define MX25_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x398, 0x1a0, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
380#define MX25_PAD_SD1_DATA2__FEC_RX_CLK IOMUX_PAD(0x398, 0x1a0, 0x15, 0x514, 2, NO_PAD_CTL) 380#define MX25_PAD_SD1_DATA2__FEC_RX_CLK IOMUX_PAD(0x398, 0x1a0, 0x15, 0x514, 2, NO_PAD_CTRL)
381#define MX25_PAD_SD1_DATA2__GPIO_2_27 IOMUX_PAD(0x398, 0x1a0, 0x15, 0, 0, NO_PAD_CTRL) 381#define MX25_PAD_SD1_DATA2__GPIO_2_27 IOMUX_PAD(0x398, 0x1a0, 0x15, 0, 0, NO_PAD_CTRL)
382 382
383#define MX25_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x39c, 0x1a4, 0x10, 0, 0, PAD_CTL_PUS_47K_UP) 383#define MX25_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x39c, 0x1a4, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
384#define MX25_PAD_SD1_DATA3__FEC_CRS IOMUX_PAD(0x39c, 0x1a4, 0x10, 0x508, 2, NO_PAD_CTL) 384#define MX25_PAD_SD1_DATA3__FEC_CRS IOMUX_PAD(0x39c, 0x1a4, 0x10, 0x508, 2, NO_PAD_CTRL)
385#define MX25_PAD_SD1_DATA3__GPIO_2_28 IOMUX_PAD(0x39c, 0x1a4, 0x15, 0, 0, NO_PAD_CTRL) 385#define MX25_PAD_SD1_DATA3__GPIO_2_28 IOMUX_PAD(0x39c, 0x1a4, 0x15, 0, 0, NO_PAD_CTRL)
386 386
387#define MX25_PAD_KPP_ROW0__KPP_ROW0 IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, PAD_CTL_PKE) 387#define MX25_PAD_KPP_ROW0__KPP_ROW0 IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, PAD_CTL_PKE)
@@ -410,7 +410,7 @@
410#define MX25_PAD_KPP_COL3__KPP_COL3 IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE) 410#define MX25_PAD_KPP_COL3__KPP_COL3 IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE)
411#define MX25_PAD_KPP_COL3__GPIO_3_4 IOMUX_PAD(0x3bc, 0x1c4, 0x15, 0, 0, NO_PAD_CTRL) 411#define MX25_PAD_KPP_COL3__GPIO_3_4 IOMUX_PAD(0x3bc, 0x1c4, 0x15, 0, 0, NO_PAD_CTRL)
412 412
413#define MX25_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x3c0, 0x1c8, 0x10, 0, 0, NO_PAD_CTL) 413#define MX25_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x3c0, 0x1c8, 0x10, 0, 0, NO_PAD_CTRL)
414#define MX25_PAD_FEC_MDC__AUD4_TXD IOMUX_PAD(0x3c0, 0x1c8, 0x12, 0x464, 1, NO_PAD_CTRL) 414#define MX25_PAD_FEC_MDC__AUD4_TXD IOMUX_PAD(0x3c0, 0x1c8, 0x12, 0x464, 1, NO_PAD_CTRL)
415#define MX25_PAD_FEC_MDC__GPIO_3_5 IOMUX_PAD(0x3c0, 0x1c8, 0x15, 0, 0, NO_PAD_CTRL) 415#define MX25_PAD_FEC_MDC__GPIO_3_5 IOMUX_PAD(0x3c0, 0x1c8, 0x15, 0, 0, NO_PAD_CTRL)
416 416
@@ -418,23 +418,23 @@
418#define MX25_PAD_FEC_MDIO__AUD4_RXD IOMUX_PAD(0x3c4, 0x1cc, 0x12, 0x460, 1, NO_PAD_CTRL) 418#define MX25_PAD_FEC_MDIO__AUD4_RXD IOMUX_PAD(0x3c4, 0x1cc, 0x12, 0x460, 1, NO_PAD_CTRL)
419#define MX25_PAD_FEC_MDIO__GPIO_3_6 IOMUX_PAD(0x3c4, 0x1cc, 0x15, 0, 0, NO_PAD_CTRL) 419#define MX25_PAD_FEC_MDIO__GPIO_3_6 IOMUX_PAD(0x3c4, 0x1cc, 0x15, 0, 0, NO_PAD_CTRL)
420 420
421#define MX25_PAD_FEC_TDATA0__FEC_TDATA0 IOMUX_PAD(0x3c8, 0x1d0, 0x10, 0, 0, NO_PAD_CTL) 421#define MX25_PAD_FEC_TDATA0__FEC_TDATA0 IOMUX_PAD(0x3c8, 0x1d0, 0x10, 0, 0, NO_PAD_CTRL)
422#define MX25_PAD_FEC_TDATA0__GPIO_3_7 IOMUX_PAD(0x3c8, 0x1d0, 0x15, 0, 0, NO_PAD_CTRL) 422#define MX25_PAD_FEC_TDATA0__GPIO_3_7 IOMUX_PAD(0x3c8, 0x1d0, 0x15, 0, 0, NO_PAD_CTRL)
423 423
424#define MX25_PAD_FEC_TDATA1__FEC_TDATA1 IOMUX_PAD(0x3cc, 0x1d4, 0x10, 0, 0, NO_PAD_CTL) 424#define MX25_PAD_FEC_TDATA1__FEC_TDATA1 IOMUX_PAD(0x3cc, 0x1d4, 0x10, 0, 0, NO_PAD_CTRL)
425#define MX25_PAD_FEC_TDATA1__AUD4_TXFS IOMUX_PAD(0x3cc, 0x1d4, 0x12, 0x474, 1, NO_PAD_CTRL) 425#define MX25_PAD_FEC_TDATA1__AUD4_TXFS IOMUX_PAD(0x3cc, 0x1d4, 0x12, 0x474, 1, NO_PAD_CTRL)
426#define MX25_PAD_FEC_TDATA1__GPIO_3_8 IOMUX_PAD(0x3cc, 0x1d4, 0x15, 0, 0, NO_PAD_CTRL) 426#define MX25_PAD_FEC_TDATA1__GPIO_3_8 IOMUX_PAD(0x3cc, 0x1d4, 0x15, 0, 0, NO_PAD_CTRL)
427 427
428#define MX25_PAD_FEC_TX_EN__FEC_TX_EN IOMUX_PAD(0x3d0, 0x1d8, 0x10, 0, 0, NO_PAD_CTL) 428#define MX25_PAD_FEC_TX_EN__FEC_TX_EN IOMUX_PAD(0x3d0, 0x1d8, 0x10, 0, 0, NO_PAD_CTRL)
429#define MX25_PAD_FEC_TX_EN__GPIO_3_9 IOMUX_PAD(0x3d0, 0x1d8, 0x15, 0, 0, NO_PAD_CTRL) 429#define MX25_PAD_FEC_TX_EN__GPIO_3_9 IOMUX_PAD(0x3d0, 0x1d8, 0x15, 0, 0, NO_PAD_CTRL)
430 430
431#define MX25_PAD_FEC_RDATA0__FEC_RDATA0 IOMUX_PAD(0x3d4, 0x1dc, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTL) 431#define MX25_PAD_FEC_RDATA0__FEC_RDATA0 IOMUX_PAD(0x3d4, 0x1dc, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTRL)
432#define MX25_PAD_FEC_RDATA0__GPIO_3_10 IOMUX_PAD(0x3d4, 0x1dc, 0x15, 0, 0, NO_PAD_CTRL) 432#define MX25_PAD_FEC_RDATA0__GPIO_3_10 IOMUX_PAD(0x3d4, 0x1dc, 0x15, 0, 0, NO_PAD_CTRL)
433 433
434#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 IOMUX_PAD(0x3d8, 0x1e0, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTL) 434#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 IOMUX_PAD(0x3d8, 0x1e0, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTRL)
435#define MX25_PAD_FEC_RDATA1__GPIO_3_11 IOMUX_PAD(0x3d8, 0x1e0, 0x15, 0, 0, NO_PAD_CTRL) 435#define MX25_PAD_FEC_RDATA1__GPIO_3_11 IOMUX_PAD(0x3d8, 0x1e0, 0x15, 0, 0, NO_PAD_CTRL)
436 436
437#define MX25_PAD_FEC_RX_DV__FEC_RX_DV IOMUX_PAD(0x3dc, 0x1e4, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTL) 437#define MX25_PAD_FEC_RX_DV__FEC_RX_DV IOMUX_PAD(0x3dc, 0x1e4, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTRL)
438#define MX25_PAD_FEC_RX_DV__CAN2_RX IOMUX_PAD(0x3dc, 0x1e4, 0x14, 0x484, 0, PAD_CTL_PUS_22K_UP) 438#define MX25_PAD_FEC_RX_DV__CAN2_RX IOMUX_PAD(0x3dc, 0x1e4, 0x14, 0x484, 0, PAD_CTL_PUS_22K_UP)
439#define MX25_PAD_FEC_RX_DV__GPIO_3_12 IOMUX_PAD(0x3dc, 0x1e4, 0x15, 0, 0, NO_PAD_CTRL) 439#define MX25_PAD_FEC_RX_DV__GPIO_3_12 IOMUX_PAD(0x3dc, 0x1e4, 0x15, 0, 0, NO_PAD_CTRL)
440 440
diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h
index 1b2890a5c45..b652a9c2586 100644
--- a/arch/arm/plat-mxc/include/mach/mx1.h
+++ b/arch/arm/plat-mxc/include/mach/mx1.h
@@ -9,8 +9,8 @@
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10 */ 10 */
11 11
12#ifndef __ASM_ARCH_MXC_MX1_H__ 12#ifndef __MACH_MX1_H__
13#define __ASM_ARCH_MXC_MX1_H__ 13#define __MACH_MX1_H__
14 14
15#include <mach/vmalloc.h> 15#include <mach/vmalloc.h>
16 16
@@ -161,4 +161,4 @@
161#define DMA_REQ_UART1_T 30 161#define DMA_REQ_UART1_T 30
162#define DMA_REQ_UART1_R 31 162#define DMA_REQ_UART1_R 31
163 163
164#endif /* __ASM_ARCH_MXC_MX1_H__ */ 164#endif /* ifndef __MACH_MX1_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h
index bb297d8765a..ed98b9c9f38 100644
--- a/arch/arm/plat-mxc/include/mach/mx21.h
+++ b/arch/arm/plat-mxc/include/mach/mx21.h
@@ -22,8 +22,8 @@
22 * MA 02110-1301, USA. 22 * MA 02110-1301, USA.
23 */ 23 */
24 24
25#ifndef __ASM_ARCH_MXC_MX21_H__ 25#ifndef __MACH_MX21_H__
26#define __ASM_ARCH_MXC_MX21_H__ 26#define __MACH_MX21_H__
27 27
28#define MX21_AIPI_BASE_ADDR 0x10000000 28#define MX21_AIPI_BASE_ADDR 0x10000000
29#define MX21_AIPI_BASE_ADDR_VIRT 0xf4000000 29#define MX21_AIPI_BASE_ADDR_VIRT 0xf4000000
@@ -92,6 +92,11 @@
92 92
93#define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */ 93#define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */
94 94
95#define MX21_IO_ADDRESS(x) ( \
96 IMX_IO_ADDRESS(x, MX21_AIPI) ?: \
97 IMX_IO_ADDRESS(x, MX21_SAHB1) ?: \
98 IMX_IO_ADDRESS(x, MX21_X_MEMC))
99
95/* fixed interrupt numbers */ 100/* fixed interrupt numbers */
96#define MX21_INT_CSPI3 6 101#define MX21_INT_CSPI3 6
97#define MX21_INT_GPIO 8 102#define MX21_INT_GPIO 8
@@ -179,6 +184,7 @@
179#define MX21_DMA_REQ_CSI_STAT 30 184#define MX21_DMA_REQ_CSI_STAT 30
180#define MX21_DMA_REQ_CSI_RX 31 185#define MX21_DMA_REQ_CSI_RX 31
181 186
187#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
182/* these should go away */ 188/* these should go away */
183#define SDRAM_BASE_ADDR MX21_SDRAM_BASE_ADDR 189#define SDRAM_BASE_ADDR MX21_SDRAM_BASE_ADDR
184#define CSD1_BASE_ADDR MX21_CSD1_BASE_ADDR 190#define CSD1_BASE_ADDR MX21_CSD1_BASE_ADDR
@@ -211,5 +217,6 @@
211#define DMA_REQ_FIRI_RX MX21_DMA_REQ_FIRI_RX 217#define DMA_REQ_FIRI_RX MX21_DMA_REQ_FIRI_RX
212#define DMA_REQ_BMI_TX MX21_DMA_REQ_BMI_TX 218#define DMA_REQ_BMI_TX MX21_DMA_REQ_BMI_TX
213#define DMA_REQ_BMI_RX MX21_DMA_REQ_BMI_RX 219#define DMA_REQ_BMI_RX MX21_DMA_REQ_BMI_RX
220#endif
214 221
215#endif /* __ASM_ARCH_MXC_MX21_H__ */ 222#endif /* ifndef __MACH_MX21_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
index 91e73814480..18eb44c15ea 100644
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -22,23 +22,16 @@
22#define MX25_GPIO3_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xa4000) 22#define MX25_GPIO3_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xa4000)
23#define MX25_GPIO4_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0x9c000) 23#define MX25_GPIO4_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0x9c000)
24 24
25#define MX25_AIPS1_IO_ADDRESS(x) \ 25#define MX25_IO_ADDRESS(x) ( \
26 (((x) - MX25_AIPS1_BASE_ADDR) + MX25_AIPS1_BASE_ADDR_VIRT) 26 IMX_IO_ADDRESS(x, MX25_AIPS1) ?: \
27#define MX25_AIPS2_IO_ADDRESS(x) \ 27 IMX_IO_ADDRESS(x, MX25_AIPS2) ?: \
28 (((x) - MX25_AIPS2_BASE_ADDR) + MX25_AIPS2_BASE_ADDR_VIRT) 28 IMX_IO_ADDRESS(x, MX25_AVIC))
29#define MX25_AVIC_IO_ADDRESS(x) \
30 (((x) - MX25_AVIC_BASE_ADDR) + MX25_AVIC_BASE_ADDR_VIRT)
31
32#define __in_range(addr, name) ((addr) >= name##_BASE_ADDR && (addr) < name##_BASE_ADDR + name##_SIZE)
33
34#define MX25_IO_ADDRESS(x) \
35 (void __force __iomem *) \
36 (__in_range(x, MX25_AIPS1) ? MX25_AIPS1_IO_ADDRESS(x) : \
37 __in_range(x, MX25_AIPS2) ? MX25_AIPS2_IO_ADDRESS(x) : \
38 __in_range(x, MX25_AVIC) ? MX25_AVIC_IO_ADDRESS(x) : \
39 0xDEADBEEF)
40 29
41#define UART1_BASE_ADDR 0x43f90000 30#define UART1_BASE_ADDR 0x43f90000
42#define UART2_BASE_ADDR 0x43f94000 31#define UART2_BASE_ADDR 0x43f94000
43 32
44#endif /* __MACH_MX25_H__ */ 33#define MX25_FEC_BASE_ADDR 0x50038000
34
35#define MX25_INT_FEC 57
36
37#endif /* ifndef __MACH_MX25_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index e2ae19f5171..bae9cd75bee 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -21,8 +21,12 @@
21 * MA 02110-1301, USA. 21 * MA 02110-1301, USA.
22 */ 22 */
23 23
24#ifndef __ASM_ARCH_MXC_MX27_H__ 24#ifndef __MACH_MX27_H__
25#define __ASM_ARCH_MXC_MX27_H__ 25#define __MACH_MX27_H__
26
27#ifndef __ASSEMBLER__
28#include <linux/io.h>
29#endif
26 30
27#define MX27_AIPI_BASE_ADDR 0x10000000 31#define MX27_AIPI_BASE_ADDR 0x10000000
28#define MX27_AIPI_BASE_ADDR_VIRT 0xf4000000 32#define MX27_AIPI_BASE_ADDR_VIRT 0xf4000000
@@ -109,11 +113,31 @@
109#define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000) 113#define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000)
110#define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000) 114#define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000)
111 115
116#define MX27_WEIM_CSCRx_BASE_ADDR(cs) (MX27_WEIM_BASE_ADDR + (cs) * 0x10)
117#define MX27_WEIM_CSCRxU(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs))
118#define MX27_WEIM_CSCRxL(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
119#define MX27_WEIM_CSCRxA(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
120
112#define MX27_PCMCIA_MEM_BASE_ADDR 0xdc000000 121#define MX27_PCMCIA_MEM_BASE_ADDR 0xdc000000
113 122
114/* IRAM */ 123/* IRAM */
115#define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */ 124#define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */
116 125
126#define MX27_IO_ADDRESS(x) ( \
127 IMX_IO_ADDRESS(x, MX27_AIPI) ?: \
128 IMX_IO_ADDRESS(x, MX27_SAHB1) ?: \
129 IMX_IO_ADDRESS(x, MX27_X_MEMC))
130
131#ifndef __ASSEMBLER__
132static inline void mx27_setup_weimcs(size_t cs,
133 unsigned upper, unsigned lower, unsigned addional)
134{
135 __raw_writel(upper, MX27_IO_ADDRESS(MX27_WEIM_CSCRxU(cs)));
136 __raw_writel(lower, MX27_IO_ADDRESS(MX27_WEIM_CSCRxL(cs)));
137 __raw_writel(addional, MX27_IO_ADDRESS(MX27_WEIM_CSCRxA(cs)));
138}
139#endif
140
117/* fixed interrupt numbers */ 141/* fixed interrupt numbers */
118#define MX27_INT_I2C2 1 142#define MX27_INT_I2C2 1
119#define MX27_INT_GPT6 2 143#define MX27_INT_GPT6 2
@@ -225,6 +249,7 @@
225extern int mx27_revision(void); 249extern int mx27_revision(void);
226#endif 250#endif
227 251
252#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
228/* these should go away */ 253/* these should go away */
229#define MSHC_BASE_ADDR MX27_MSHC_BASE_ADDR 254#define MSHC_BASE_ADDR MX27_MSHC_BASE_ADDR
230#define GPT5_BASE_ADDR MX27_GPT5_BASE_ADDR 255#define GPT5_BASE_ADDR MX27_GPT5_BASE_ADDR
@@ -292,5 +317,6 @@ extern int mx27_revision(void);
292#define DMA_REQ_UART6_RX MX27_DMA_REQ_UART6_RX 317#define DMA_REQ_UART6_RX MX27_DMA_REQ_UART6_RX
293#define DMA_REQ_SDHC3 MX27_DMA_REQ_SDHC3 318#define DMA_REQ_SDHC3 MX27_DMA_REQ_SDHC3
294#define DMA_REQ_NFC MX27_DMA_REQ_NFC 319#define DMA_REQ_NFC MX27_DMA_REQ_NFC
320#endif
295 321
296#endif /* __ASM_ARCH_MXC_MX27_H__ */ 322#endif /* ifndef __MACH_MX27_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h
index f2eaf140ed0..afb895a0b5b 100644
--- a/arch/arm/plat-mxc/include/mach/mx2x.h
+++ b/arch/arm/plat-mxc/include/mach/mx2x.h
@@ -20,8 +20,8 @@
20 * MA 02110-1301, USA. 20 * MA 02110-1301, USA.
21 */ 21 */
22 22
23#ifndef __ASM_ARCH_MXC_MX2x_H__ 23#ifndef __MACH_MX2x_H__
24#define __ASM_ARCH_MXC_MX2x_H__ 24#define __MACH_MX2x_H__
25 25
26/* The following addresses are common between i.MX21 and i.MX27 */ 26/* The following addresses are common between i.MX21 and i.MX27 */
27 27
@@ -176,6 +176,7 @@
176#define MX2x_DMA_REQ_CSI_STAT 30 176#define MX2x_DMA_REQ_CSI_STAT 30
177#define MX2x_DMA_REQ_CSI_RX 31 177#define MX2x_DMA_REQ_CSI_RX 31
178 178
179#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
179/* these should go away */ 180/* these should go away */
180#define AIPI_BASE_ADDR MX2x_AIPI_BASE_ADDR 181#define AIPI_BASE_ADDR MX2x_AIPI_BASE_ADDR
181#define AIPI_BASE_ADDR_VIRT MX2x_AIPI_BASE_ADDR_VIRT 182#define AIPI_BASE_ADDR_VIRT MX2x_AIPI_BASE_ADDR_VIRT
@@ -287,5 +288,6 @@
287#define DMA_REQ_UART1_TX MX2x_DMA_REQ_UART1_TX 288#define DMA_REQ_UART1_TX MX2x_DMA_REQ_UART1_TX
288#define DMA_REQ_CSI_STAT MX2x_DMA_REQ_CSI_STAT 289#define DMA_REQ_CSI_STAT MX2x_DMA_REQ_CSI_STAT
289#define DMA_REQ_CSI_RX MX2x_DMA_REQ_CSI_RX 290#define DMA_REQ_CSI_RX MX2x_DMA_REQ_CSI_RX
291#endif
290 292
291#endif /* __ASM_ARCH_MXC_MX2x_H__ */ 293#endif /* ifndef __MACH_MX2x_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index b8b47d139eb..fb90e119c2b 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -1,3 +1,10 @@
1#ifndef __MACH_MX31_H__
2#define __MACH_MX31_H__
3
4#ifndef __ASSEMBLER__
5#include <linux/io.h>
6#endif
7
1/* 8/*
2 * IRAM 9 * IRAM
3 */ 10 */
@@ -107,8 +114,30 @@
107#define MX31_EMI_CTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x4000) 114#define MX31_EMI_CTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x4000)
108#define MX31_PCMCIA_CTL_BASE_ADDR MX31_EMI_CTL_BASE_ADDR 115#define MX31_PCMCIA_CTL_BASE_ADDR MX31_EMI_CTL_BASE_ADDR
109 116
117#define MX31_WEIM_CSCRx_BASE_ADDR(cs) (MX31_WEIM_BASE_ADDR + (cs) * 0x10)
118#define MX31_WEIM_CSCRxU(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs))
119#define MX31_WEIM_CSCRxL(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
120#define MX31_WEIM_CSCRxA(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
121
110#define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000 122#define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000
111 123
124#define MX31_IO_ADDRESS(x) ( \
125 IMX_IO_ADDRESS(x, MX31_AIPS1) ?: \
126 IMX_IO_ADDRESS(x, MX31_AIPS2) ?: \
127 IMX_IO_ADDRESS(x, MX31_AVIC) ?: \
128 IMX_IO_ADDRESS(x, MX31_X_MEMC) ?: \
129 IMX_IO_ADDRESS(x, MX31_SPBA0))
130
131#ifndef __ASSEMBLER__
132static inline void mx31_setup_weimcs(size_t cs,
133 unsigned upper, unsigned lower, unsigned addional)
134{
135 __raw_writel(upper, MX31_IO_ADDRESS(MX31_WEIM_CSCRxU(cs)));
136 __raw_writel(lower, MX31_IO_ADDRESS(MX31_WEIM_CSCRxL(cs)));
137 __raw_writel(addional, MX31_IO_ADDRESS(MX31_WEIM_CSCRxA(cs)));
138}
139#endif
140
112#define MX31_INT_I2C3 3 141#define MX31_INT_I2C3 3
113#define MX31_INT_I2C2 4 142#define MX31_INT_I2C2 4
114#define MX31_INT_MPEG4_ENCODER 5 143#define MX31_INT_MPEG4_ENCODER 5
@@ -186,6 +215,7 @@
186#define MX31_SYSTEM_REV_MIN MX31_CHIP_REV_1_0 215#define MX31_SYSTEM_REV_MIN MX31_CHIP_REV_1_0
187#define MX31_SYSTEM_REV_NUM 3 216#define MX31_SYSTEM_REV_NUM 3
188 217
218#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
189/* these should go away */ 219/* these should go away */
190#define ATA_BASE_ADDR MX31_ATA_BASE_ADDR 220#define ATA_BASE_ADDR MX31_ATA_BASE_ADDR
191#define UART4_BASE_ADDR MX31_UART4_BASE_ADDR 221#define UART4_BASE_ADDR MX31_UART4_BASE_ADDR
@@ -216,3 +246,6 @@
216#define MXC_INT_UART5 MX31_INT_UART5 246#define MXC_INT_UART5 MX31_INT_UART5
217#define MXC_INT_CCM MX31_INT_CCM 247#define MXC_INT_CCM MX31_INT_CCM
218#define MXC_INT_PCMCIA MX31_INT_PCMCIA 248#define MXC_INT_PCMCIA MX31_INT_PCMCIA
249#endif
250
251#endif /* ifndef __MACH_MX31_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
index af871bce35b..526a55842ae 100644
--- a/arch/arm/plat-mxc/include/mach/mx35.h
+++ b/arch/arm/plat-mxc/include/mach/mx35.h
@@ -1,3 +1,5 @@
1#ifndef __MACH_MX35_H__
2#define __MACH_MX35_H__
1/* 3/*
2 * IRAM 4 * IRAM
3 */ 5 */
@@ -104,6 +106,13 @@
104#define MX35_NFC_BASE_ADDR 0xbb000000 106#define MX35_NFC_BASE_ADDR 0xbb000000
105#define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000 107#define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000
106 108
109#define MX35_IO_ADDRESS(x) ( \
110 IMX_IO_ADDRESS(x, MX35_AIPS1) ?: \
111 IMX_IO_ADDRESS(x, MX35_AIPS2) ?: \
112 IMX_IO_ADDRESS(x, MX35_AVIC) ?: \
113 IMX_IO_ADDRESS(x, MX35_X_MEMC) ?: \
114 IMX_IO_ADDRESS(x, MX35_SPBA0))
115
107/* 116/*
108 * Interrupt numbers 117 * Interrupt numbers
109 */ 118 */
@@ -180,6 +189,7 @@
180#define MX35_SYSTEM_REV_MIN MX35_CHIP_REV_1_0 189#define MX35_SYSTEM_REV_MIN MX35_CHIP_REV_1_0
181#define MX35_SYSTEM_REV_NUM 3 190#define MX35_SYSTEM_REV_NUM 3
182 191
192#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
183/* these should go away */ 193/* these should go away */
184#define MXC_FEC_BASE_ADDR MX35_FEC_BASE_ADDR 194#define MXC_FEC_BASE_ADDR MX35_FEC_BASE_ADDR
185#define MXC_INT_OWIRE MX35_INT_OWIRE 195#define MXC_INT_OWIRE MX35_INT_OWIRE
@@ -195,3 +205,6 @@
195#define MXC_INT_MLB MX35_INT_MLB 205#define MXC_INT_MLB MX35_INT_MLB
196#define MXC_INT_SPDIF MX35_INT_SPDIF 206#define MXC_INT_SPDIF MX35_INT_SPDIF
197#define MXC_INT_FEC MX35_INT_FEC 207#define MXC_INT_FEC MX35_INT_FEC
208#endif
209
210#endif /* ifndef __MACH_MX35_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h
index be69272407a..7a356de385f 100644
--- a/arch/arm/plat-mxc/include/mach/mx3x.h
+++ b/arch/arm/plat-mxc/include/mach/mx3x.h
@@ -8,8 +8,8 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10 10
11#ifndef __ASM_ARCH_MXC_MX31_H__ 11#ifndef __MACH_MX3x_H__
12#define __ASM_ARCH_MXC_MX31_H__ 12#define __MACH_MX3x_H__
13 13
14/* 14/*
15 * MX31 memory map: 15 * MX31 memory map:
@@ -269,6 +269,7 @@ static inline int mx31_revision(void)
269} 269}
270#endif 270#endif
271 271
272#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
272/* these should go away */ 273/* these should go away */
273#define L2CC_BASE_ADDR MX3x_L2CC_BASE_ADDR 274#define L2CC_BASE_ADDR MX3x_L2CC_BASE_ADDR
274#define L2CC_SIZE MX3x_L2CC_SIZE 275#define L2CC_SIZE MX3x_L2CC_SIZE
@@ -401,5 +402,6 @@ static inline int mx31_revision(void)
401#define CHIP_REV_3_2 MX3x_CHIP_REV_3_2 402#define CHIP_REV_3_2 MX3x_CHIP_REV_3_2
402#define SYSTEM_REV_MIN MX3x_SYSTEM_REV_MIN 403#define SYSTEM_REV_MIN MX3x_SYSTEM_REV_MIN
403#define SYSTEM_REV_NUM MX3x_SYSTEM_REV_NUM 404#define SYSTEM_REV_NUM MX3x_SYSTEM_REV_NUM
405#endif
404 406
405#endif /* __ASM_ARCH_MXC_MX31_H__ */ 407#endif /* ifndef __MACH_MX3x_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index 51990536b84..800ae2a33b1 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -121,9 +121,10 @@ extern unsigned int __mxc_cpu_type;
121#endif 121#endif
122 122
123#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2) 123#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2)
124#define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10) 124/* These are deprecated, use mx[23][157]_setup_weimcs instead. */
125#define CSCR_L(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x4) 125#define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10))
126#define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x8) 126#define CSCR_L(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10 + 0x4))
127#define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10 + 0x8))
127#endif 128#endif
128 129
129#define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35() || cpu_is_mxc91231()) 130#define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35() || cpu_is_mxc91231())
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
index 4d5d395ad63..d189f00f236 100644
--- a/arch/arm/plat-mxc/include/mach/uncompress.h
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -1,8 +1,6 @@
1/* 1/*
2 * arch/arm/plat-mxc/include/mach/uncompress.h 2 * arch/arm/plat-mxc/include/mach/uncompress.h
3 * 3 *
4 *
5 *
6 * Copyright (C) 1999 ARM Limited 4 * Copyright (C) 1999 ARM Limited
7 * Copyright (C) Shane Nay (shane@minirl.com) 5 * Copyright (C) Shane Nay (shane@minirl.com)
8 * 6 *
@@ -25,7 +23,6 @@
25 23
26#define __MXC_BOOT_UNCOMPRESS 24#define __MXC_BOOT_UNCOMPRESS
27 25
28#include <mach/hardware.h>
29#include <asm/mach-types.h> 26#include <asm/mach-types.h>
30 27
31static unsigned long uart_base; 28static unsigned long uart_base;
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-19 13:17:58 -0500