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authorChris Wilson <chris@chris-wilson.co.uk>2010-06-07 09:03:05 -0400
committerEric Anholt <eric@anholt.net>2010-08-01 22:03:44 -0400
commit2dafb1e082c541d4bc0f275a6ffa9c39da690f01 (patch)
treeaba221033813b7e531ed8602c69579984b6c45b6
parent96b099fd6d64389e619dbf7ca9059bf16e441f6b (diff)
drm/i915: Propagate error from i915_gem_object_flush_gpu_write_domain()
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h2
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c43
-rw-r--r--drivers/gpu/drm/i915/intel_display.c4
3 files changed, 35 insertions, 14 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f5636d8da96..f8f315deda8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -982,7 +982,7 @@ void i915_gem_free_all_phys_object(struct drm_device *dev);
982int i915_gem_object_get_pages(struct drm_gem_object *obj, gfp_t gfpmask); 982int i915_gem_object_get_pages(struct drm_gem_object *obj, gfp_t gfpmask);
983void i915_gem_object_put_pages(struct drm_gem_object *obj); 983void i915_gem_object_put_pages(struct drm_gem_object *obj);
984void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv); 984void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
985void i915_gem_object_flush_write_domain(struct drm_gem_object *obj); 985int i915_gem_object_flush_write_domain(struct drm_gem_object *obj);
986 986
987void i915_gem_shrinker_init(void); 987void i915_gem_shrinker_init(void);
988void i915_gem_shrinker_exit(void); 988void i915_gem_shrinker_exit(void);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 0bf4bcd53e9..b1069dc0961 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -35,7 +35,7 @@
35#include <linux/swap.h> 35#include <linux/swap.h>
36#include <linux/pci.h> 36#include <linux/pci.h>
37 37
38static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj); 38static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
39static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj); 39static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
40static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj); 40static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
41static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, 41static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
@@ -2583,7 +2583,10 @@ i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2583 if (!IS_I965G(dev)) { 2583 if (!IS_I965G(dev)) {
2584 int ret; 2584 int ret;
2585 2585
2586 i915_gem_object_flush_gpu_write_domain(obj); 2586 ret = i915_gem_object_flush_gpu_write_domain(obj);
2587 if (ret != 0)
2588 return ret;
2589
2587 ret = i915_gem_object_wait_rendering(obj); 2590 ret = i915_gem_object_wait_rendering(obj);
2588 if (ret != 0) 2591 if (ret != 0)
2589 return ret; 2592 return ret;
@@ -2731,7 +2734,7 @@ i915_gem_clflush_object(struct drm_gem_object *obj)
2731} 2734}
2732 2735
2733/** Flushes any GPU write domain for the object if it's dirty. */ 2736/** Flushes any GPU write domain for the object if it's dirty. */
2734static void 2737static int
2735i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj) 2738i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2736{ 2739{
2737 struct drm_device *dev = obj->dev; 2740 struct drm_device *dev = obj->dev;
@@ -2739,17 +2742,18 @@ i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2739 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); 2742 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2740 2743
2741 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) 2744 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2742 return; 2745 return 0;
2743 2746
2744 /* Queue the GPU write cache flushing we need. */ 2747 /* Queue the GPU write cache flushing we need. */
2745 old_write_domain = obj->write_domain; 2748 old_write_domain = obj->write_domain;
2746 i915_gem_flush(dev, 0, obj->write_domain); 2749 i915_gem_flush(dev, 0, obj->write_domain);
2747 (void) i915_add_request(dev, NULL, obj->write_domain, obj_priv->ring); 2750 if (i915_add_request(dev, NULL, obj->write_domain, obj_priv->ring) == 0)
2748 BUG_ON(obj->write_domain); 2751 return -ENOMEM;
2749 2752
2750 trace_i915_gem_object_change_domain(obj, 2753 trace_i915_gem_object_change_domain(obj,
2751 obj->read_domains, 2754 obj->read_domains,
2752 old_write_domain); 2755 old_write_domain);
2756 return 0;
2753} 2757}
2754 2758
2755/** Flushes the GTT write domain for the object if it's dirty. */ 2759/** Flushes the GTT write domain for the object if it's dirty. */
@@ -2793,9 +2797,11 @@ i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2793 old_write_domain); 2797 old_write_domain);
2794} 2798}
2795 2799
2796void 2800int
2797i915_gem_object_flush_write_domain(struct drm_gem_object *obj) 2801i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
2798{ 2802{
2803 int ret = 0;
2804
2799 switch (obj->write_domain) { 2805 switch (obj->write_domain) {
2800 case I915_GEM_DOMAIN_GTT: 2806 case I915_GEM_DOMAIN_GTT:
2801 i915_gem_object_flush_gtt_write_domain(obj); 2807 i915_gem_object_flush_gtt_write_domain(obj);
@@ -2804,9 +2810,11 @@ i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
2804 i915_gem_object_flush_cpu_write_domain(obj); 2810 i915_gem_object_flush_cpu_write_domain(obj);
2805 break; 2811 break;
2806 default: 2812 default:
2807 i915_gem_object_flush_gpu_write_domain(obj); 2813 ret = i915_gem_object_flush_gpu_write_domain(obj);
2808 break; 2814 break;
2809 } 2815 }
2816
2817 return ret;
2810} 2818}
2811 2819
2812/** 2820/**
@@ -2826,7 +2834,10 @@ i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2826 if (obj_priv->gtt_space == NULL) 2834 if (obj_priv->gtt_space == NULL)
2827 return -EINVAL; 2835 return -EINVAL;
2828 2836
2829 i915_gem_object_flush_gpu_write_domain(obj); 2837 ret = i915_gem_object_flush_gpu_write_domain(obj);
2838 if (ret != 0)
2839 return ret;
2840
2830 /* Wait on any GPU rendering and flushing to occur. */ 2841 /* Wait on any GPU rendering and flushing to occur. */
2831 ret = i915_gem_object_wait_rendering(obj); 2842 ret = i915_gem_object_wait_rendering(obj);
2832 if (ret != 0) 2843 if (ret != 0)
@@ -2876,7 +2887,9 @@ i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
2876 if (obj_priv->gtt_space == NULL) 2887 if (obj_priv->gtt_space == NULL)
2877 return -EINVAL; 2888 return -EINVAL;
2878 2889
2879 i915_gem_object_flush_gpu_write_domain(obj); 2890 ret = i915_gem_object_flush_gpu_write_domain(obj);
2891 if (ret)
2892 return ret;
2880 2893
2881 /* Wait on any GPU rendering and flushing to occur. */ 2894 /* Wait on any GPU rendering and flushing to occur. */
2882 if (obj_priv->active) { 2895 if (obj_priv->active) {
@@ -2924,7 +2937,10 @@ i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2924 uint32_t old_write_domain, old_read_domains; 2937 uint32_t old_write_domain, old_read_domains;
2925 int ret; 2938 int ret;
2926 2939
2927 i915_gem_object_flush_gpu_write_domain(obj); 2940 ret = i915_gem_object_flush_gpu_write_domain(obj);
2941 if (ret)
2942 return ret;
2943
2928 /* Wait on any GPU rendering and flushing to occur. */ 2944 /* Wait on any GPU rendering and flushing to occur. */
2929 ret = i915_gem_object_wait_rendering(obj); 2945 ret = i915_gem_object_wait_rendering(obj);
2930 if (ret != 0) 2946 if (ret != 0)
@@ -3214,7 +3230,10 @@ i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3214 if (offset == 0 && size == obj->size) 3230 if (offset == 0 && size == obj->size)
3215 return i915_gem_object_set_to_cpu_domain(obj, 0); 3231 return i915_gem_object_set_to_cpu_domain(obj, 0);
3216 3232
3217 i915_gem_object_flush_gpu_write_domain(obj); 3233 ret = i915_gem_object_flush_gpu_write_domain(obj);
3234 if (ret)
3235 return ret;
3236
3218 /* Wait on any GPU rendering and flushing to occur. */ 3237 /* Wait on any GPU rendering and flushing to occur. */
3219 ret = i915_gem_object_wait_rendering(obj); 3238 ret = i915_gem_object_wait_rendering(obj);
3220 if (ret != 0) 3239 if (ret != 0)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index bf486b14283..81179fb5150 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4905,7 +4905,9 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
4905 drm_gem_object_reference(obj); 4905 drm_gem_object_reference(obj);
4906 4906
4907 crtc->fb = fb; 4907 crtc->fb = fb;
4908 i915_gem_object_flush_write_domain(obj); 4908 ret = i915_gem_object_flush_write_domain(obj);
4909 if (ret)
4910 goto cleanup_objs;
4909 4911
4910 ret = drm_vblank_get(dev, intel_crtc->pipe); 4912 ret = drm_vblank_get(dev, intel_crtc->pipe);
4911 if (ret) 4913 if (ret)