diff options
author | Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> | 2012-10-29 02:06:00 -0400 |
---|---|---|
committer | Simon Horman <horms@verge.net.au> | 2012-11-05 23:47:20 -0500 |
commit | 2864b19142c0f7aa44791499e159f9462c2e64be (patch) | |
tree | b5354abf7417457d2edaa47a0bdb5050c115ce37 | |
parent | ed9c0754cef1d9f81f70b3147189a5a1b4a307a8 (diff) |
ARM: shmobile: Remove SH7377 support
This is old CPU of shmobile, and the machine by which this CPU is
used cannot be obtained.
Therefore, remove SH7377 support.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Simon Horman <horms@verge.net.au>
-rw-r--r-- | arch/arm/boot/dts/sh7377.dtsi | 21 | ||||
-rw-r--r-- | arch/arm/mach-shmobile/Kconfig | 6 | ||||
-rw-r--r-- | arch/arm/mach-shmobile/Makefile | 3 | ||||
-rw-r--r-- | arch/arm/mach-shmobile/clock-sh7377.c | 366 | ||||
-rw-r--r-- | arch/arm/mach-shmobile/include/mach/common.h | 9 | ||||
-rw-r--r-- | arch/arm/mach-shmobile/include/mach/sh7377.h | 360 | ||||
-rw-r--r-- | arch/arm/mach-shmobile/intc-sh7377.c | 592 | ||||
-rw-r--r-- | arch/arm/mach-shmobile/pfc-sh7377.c | 1688 | ||||
-rw-r--r-- | arch/arm/mach-shmobile/setup-sh7377.c | 549 |
9 files changed, 0 insertions, 3594 deletions
diff --git a/arch/arm/boot/dts/sh7377.dtsi b/arch/arm/boot/dts/sh7377.dtsi deleted file mode 100644 index 767ee0796da..00000000000 --- a/arch/arm/boot/dts/sh7377.dtsi +++ /dev/null | |||
@@ -1,21 +0,0 @@ | |||
1 | /* | ||
2 | * Device Tree Source for the sh7377 SoC | ||
3 | * | ||
4 | * Copyright (C) 2012 Renesas Solutions Corp. | ||
5 | * | ||
6 | * This file is licensed under the terms of the GNU General Public License | ||
7 | * version 2. This program is licensed "as is" without any warranty of any | ||
8 | * kind, whether express or implied. | ||
9 | */ | ||
10 | |||
11 | /include/ "skeleton.dtsi" | ||
12 | |||
13 | / { | ||
14 | compatible = "renesas,sh7377"; | ||
15 | |||
16 | cpus { | ||
17 | cpu@0 { | ||
18 | compatible = "arm,cortex-a8"; | ||
19 | }; | ||
20 | }; | ||
21 | }; | ||
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index d20dab45547..546e40a9dca 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig | |||
@@ -2,12 +2,6 @@ if ARCH_SHMOBILE | |||
2 | 2 | ||
3 | comment "SH-Mobile System Type" | 3 | comment "SH-Mobile System Type" |
4 | 4 | ||
5 | config ARCH_SH7377 | ||
6 | bool "SH-Mobile G4 (SH7377)" | ||
7 | select ARCH_WANT_OPTIONAL_GPIOLIB | ||
8 | select CPU_V7 | ||
9 | select SH_CLK_CPG | ||
10 | |||
11 | config ARCH_SH7372 | 5 | config ARCH_SH7372 |
12 | bool "SH-Mobile AP4 (SH7372)" | 6 | bool "SH-Mobile AP4 (SH7372)" |
13 | select ARCH_WANT_OPTIONAL_GPIOLIB | 7 | select ARCH_WANT_OPTIONAL_GPIOLIB |
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 7c07a04c30f..f4fd247bde6 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile | |||
@@ -6,7 +6,6 @@ | |||
6 | obj-y := timer.o console.o clock.o | 6 | obj-y := timer.o console.o clock.o |
7 | 7 | ||
8 | # CPU objects | 8 | # CPU objects |
9 | obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7377.o intc-sh7377.o | ||
10 | obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o | 9 | obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o |
11 | obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o | 10 | obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o |
12 | obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o clock-r8a7740.o intc-r8a7740.o | 11 | obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o clock-r8a7740.o intc-r8a7740.o |
@@ -22,14 +21,12 @@ smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o | |||
22 | 21 | ||
23 | # Pinmux setup | 22 | # Pinmux setup |
24 | pfc-y := | 23 | pfc-y := |
25 | pfc-$(CONFIG_ARCH_SH7377) += pfc-sh7377.o | ||
26 | pfc-$(CONFIG_ARCH_SH7372) += pfc-sh7372.o | 24 | pfc-$(CONFIG_ARCH_SH7372) += pfc-sh7372.o |
27 | pfc-$(CONFIG_ARCH_SH73A0) += pfc-sh73a0.o | 25 | pfc-$(CONFIG_ARCH_SH73A0) += pfc-sh73a0.o |
28 | pfc-$(CONFIG_ARCH_R8A7740) += pfc-r8a7740.o | 26 | pfc-$(CONFIG_ARCH_R8A7740) += pfc-r8a7740.o |
29 | pfc-$(CONFIG_ARCH_R8A7779) += pfc-r8a7779.o | 27 | pfc-$(CONFIG_ARCH_R8A7779) += pfc-r8a7779.o |
30 | 28 | ||
31 | # IRQ objects | 29 | # IRQ objects |
32 | obj-$(CONFIG_ARCH_SH7377) += entry-intc.o | ||
33 | obj-$(CONFIG_ARCH_SH7372) += entry-intc.o | 30 | obj-$(CONFIG_ARCH_SH7372) += entry-intc.o |
34 | obj-$(CONFIG_ARCH_R8A7740) += entry-intc.o | 31 | obj-$(CONFIG_ARCH_R8A7740) += entry-intc.o |
35 | 32 | ||
diff --git a/arch/arm/mach-shmobile/clock-sh7377.c b/arch/arm/mach-shmobile/clock-sh7377.c deleted file mode 100644 index b8480d19e1c..00000000000 --- a/arch/arm/mach-shmobile/clock-sh7377.c +++ /dev/null | |||
@@ -1,366 +0,0 @@ | |||
1 | /* | ||
2 | * SH7377 clock framework support | ||
3 | * | ||
4 | * Copyright (C) 2010 Magnus Damm | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License | ||
9 | * | ||
10 | * This program is distributed in the hope that it will be useful, | ||
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
13 | * GNU General Public License for more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program; if not, write to the Free Software | ||
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
18 | */ | ||
19 | #include <linux/init.h> | ||
20 | #include <linux/kernel.h> | ||
21 | #include <linux/io.h> | ||
22 | #include <linux/sh_clk.h> | ||
23 | #include <linux/clkdev.h> | ||
24 | #include <mach/common.h> | ||
25 | |||
26 | /* SH7377 registers */ | ||
27 | #define RTFRQCR IOMEM(0xe6150000) | ||
28 | #define SYFRQCR IOMEM(0xe6150004) | ||
29 | #define CMFRQCR IOMEM(0xe61500E0) | ||
30 | #define VCLKCR1 IOMEM(0xe6150008) | ||
31 | #define VCLKCR2 IOMEM(0xe615000C) | ||
32 | #define VCLKCR3 IOMEM(0xe615001C) | ||
33 | #define FMSICKCR IOMEM(0xe6150010) | ||
34 | #define FMSOCKCR IOMEM(0xe6150014) | ||
35 | #define FSICKCR IOMEM(0xe6150018) | ||
36 | #define PLLC1CR IOMEM(0xe6150028) | ||
37 | #define PLLC2CR IOMEM(0xe615002C) | ||
38 | #define SUBUSBCKCR IOMEM(0xe6150080) | ||
39 | #define SPUCKCR IOMEM(0xe6150084) | ||
40 | #define MSUCKCR IOMEM(0xe6150088) | ||
41 | #define MVI3CKCR IOMEM(0xe6150090) | ||
42 | #define HDMICKCR IOMEM(0xe6150094) | ||
43 | #define MFCK1CR IOMEM(0xe6150098) | ||
44 | #define MFCK2CR IOMEM(0xe615009C) | ||
45 | #define DSITCKCR IOMEM(0xe6150060) | ||
46 | #define DSIPCKCR IOMEM(0xe6150064) | ||
47 | #define SMSTPCR0 IOMEM(0xe6150130) | ||
48 | #define SMSTPCR1 IOMEM(0xe6150134) | ||
49 | #define SMSTPCR2 IOMEM(0xe6150138) | ||
50 | #define SMSTPCR3 IOMEM(0xe615013C) | ||
51 | #define SMSTPCR4 IOMEM(0xe6150140) | ||
52 | |||
53 | /* Fixed 32 KHz root clock from EXTALR pin */ | ||
54 | static struct clk r_clk = { | ||
55 | .rate = 32768, | ||
56 | }; | ||
57 | |||
58 | /* | ||
59 | * 26MHz default rate for the EXTALC1 root input clock. | ||
60 | * If needed, reset this with clk_set_rate() from the platform code. | ||
61 | */ | ||
62 | struct clk sh7377_extalc1_clk = { | ||
63 | .rate = 26666666, | ||
64 | }; | ||
65 | |||
66 | /* | ||
67 | * 48MHz default rate for the EXTAL2 root input clock. | ||
68 | * If needed, reset this with clk_set_rate() from the platform code. | ||
69 | */ | ||
70 | struct clk sh7377_extal2_clk = { | ||
71 | .rate = 48000000, | ||
72 | }; | ||
73 | |||
74 | /* A fixed divide-by-2 block */ | ||
75 | static unsigned long div2_recalc(struct clk *clk) | ||
76 | { | ||
77 | return clk->parent->rate / 2; | ||
78 | } | ||
79 | |||
80 | static struct sh_clk_ops div2_clk_ops = { | ||
81 | .recalc = div2_recalc, | ||
82 | }; | ||
83 | |||
84 | /* Divide extalc1 by two */ | ||
85 | static struct clk extalc1_div2_clk = { | ||
86 | .ops = &div2_clk_ops, | ||
87 | .parent = &sh7377_extalc1_clk, | ||
88 | }; | ||
89 | |||
90 | /* Divide extal2 by two */ | ||
91 | static struct clk extal2_div2_clk = { | ||
92 | .ops = &div2_clk_ops, | ||
93 | .parent = &sh7377_extal2_clk, | ||
94 | }; | ||
95 | |||
96 | /* Divide extal2 by four */ | ||
97 | static struct clk extal2_div4_clk = { | ||
98 | .ops = &div2_clk_ops, | ||
99 | .parent = &extal2_div2_clk, | ||
100 | }; | ||
101 | |||
102 | /* PLLC1 */ | ||
103 | static unsigned long pllc1_recalc(struct clk *clk) | ||
104 | { | ||
105 | unsigned long mult = 1; | ||
106 | |||
107 | if (__raw_readl(PLLC1CR) & (1 << 14)) | ||
108 | mult = (((__raw_readl(RTFRQCR) >> 24) & 0x3f) + 1) * 2; | ||
109 | |||
110 | return clk->parent->rate * mult; | ||
111 | } | ||
112 | |||
113 | static struct sh_clk_ops pllc1_clk_ops = { | ||
114 | .recalc = pllc1_recalc, | ||
115 | }; | ||
116 | |||
117 | static struct clk pllc1_clk = { | ||
118 | .ops = &pllc1_clk_ops, | ||
119 | .flags = CLK_ENABLE_ON_INIT, | ||
120 | .parent = &extalc1_div2_clk, | ||
121 | }; | ||
122 | |||
123 | /* Divide PLLC1 by two */ | ||
124 | static struct clk pllc1_div2_clk = { | ||
125 | .ops = &div2_clk_ops, | ||
126 | .parent = &pllc1_clk, | ||
127 | }; | ||
128 | |||
129 | /* PLLC2 */ | ||
130 | static unsigned long pllc2_recalc(struct clk *clk) | ||
131 | { | ||
132 | unsigned long mult = 1; | ||
133 | |||
134 | if (__raw_readl(PLLC2CR) & (1 << 31)) | ||
135 | mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2; | ||
136 | |||
137 | return clk->parent->rate * mult; | ||
138 | } | ||
139 | |||
140 | static struct sh_clk_ops pllc2_clk_ops = { | ||
141 | .recalc = pllc2_recalc, | ||
142 | }; | ||
143 | |||
144 | static struct clk pllc2_clk = { | ||
145 | .ops = &pllc2_clk_ops, | ||
146 | .flags = CLK_ENABLE_ON_INIT, | ||
147 | .parent = &extalc1_div2_clk, | ||
148 | }; | ||
149 | |||
150 | static struct clk *main_clks[] = { | ||
151 | &r_clk, | ||
152 | &sh7377_extalc1_clk, | ||
153 | &sh7377_extal2_clk, | ||
154 | &extalc1_div2_clk, | ||
155 | &extal2_div2_clk, | ||
156 | &extal2_div4_clk, | ||
157 | &pllc1_clk, | ||
158 | &pllc1_div2_clk, | ||
159 | &pllc2_clk, | ||
160 | }; | ||
161 | |||
162 | static void div4_kick(struct clk *clk) | ||
163 | { | ||
164 | unsigned long value; | ||
165 | |||
166 | /* set KICK bit in SYFRQCR to update hardware setting */ | ||
167 | value = __raw_readl(SYFRQCR); | ||
168 | value |= (1 << 31); | ||
169 | __raw_writel(value, SYFRQCR); | ||
170 | } | ||
171 | |||
172 | static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, | ||
173 | 24, 32, 36, 48, 0, 72, 96, 0 }; | ||
174 | |||
175 | static struct clk_div_mult_table div4_div_mult_table = { | ||
176 | .divisors = divisors, | ||
177 | .nr_divisors = ARRAY_SIZE(divisors), | ||
178 | }; | ||
179 | |||
180 | static struct clk_div4_table div4_table = { | ||
181 | .div_mult_table = &div4_div_mult_table, | ||
182 | .kick = div4_kick, | ||
183 | }; | ||
184 | |||
185 | enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR, | ||
186 | DIV4_ZTR, DIV4_ZT, DIV4_Z, DIV4_HP, | ||
187 | DIV4_ZS, DIV4_ZB, DIV4_ZB3, DIV4_CP, DIV4_NR }; | ||
188 | |||
189 | #define DIV4(_reg, _bit, _mask, _flags) \ | ||
190 | SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags) | ||
191 | |||
192 | static struct clk div4_clks[DIV4_NR] = { | ||
193 | [DIV4_I] = DIV4(RTFRQCR, 20, 0x6fff, CLK_ENABLE_ON_INIT), | ||
194 | [DIV4_ZG] = DIV4(RTFRQCR, 16, 0x6fff, CLK_ENABLE_ON_INIT), | ||
195 | [DIV4_B] = DIV4(RTFRQCR, 8, 0x6fff, CLK_ENABLE_ON_INIT), | ||
196 | [DIV4_M1] = DIV4(RTFRQCR, 4, 0x6fff, CLK_ENABLE_ON_INIT), | ||
197 | [DIV4_CSIR] = DIV4(RTFRQCR, 0, 0x6fff, 0), | ||
198 | [DIV4_ZTR] = DIV4(SYFRQCR, 20, 0x6fff, 0), | ||
199 | [DIV4_ZT] = DIV4(SYFRQCR, 16, 0x6fff, 0), | ||
200 | [DIV4_Z] = DIV4(SYFRQCR, 12, 0x6fff, 0), | ||
201 | [DIV4_HP] = DIV4(SYFRQCR, 4, 0x6fff, 0), | ||
202 | [DIV4_ZS] = DIV4(CMFRQCR, 12, 0x6fff, 0), | ||
203 | [DIV4_ZB] = DIV4(CMFRQCR, 8, 0x6fff, 0), | ||
204 | [DIV4_ZB3] = DIV4(CMFRQCR, 4, 0x6fff, 0), | ||
205 | [DIV4_CP] = DIV4(CMFRQCR, 0, 0x6fff, 0), | ||
206 | }; | ||
207 | |||
208 | enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_FMSI, DIV6_FMSO, | ||
209 | DIV6_FSI, DIV6_SUB, DIV6_SPU, DIV6_MSU, DIV6_MVI3, DIV6_HDMI, | ||
210 | DIV6_MF1, DIV6_MF2, DIV6_DSIT, DIV6_DSIP, | ||
211 | DIV6_NR }; | ||
212 | |||
213 | static struct clk div6_clks[] = { | ||
214 | [DIV6_VCK1] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR1, 0), | ||
215 | [DIV6_VCK2] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR2, 0), | ||
216 | [DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0), | ||
217 | [DIV6_FMSI] = SH_CLK_DIV6(&pllc1_div2_clk, FMSICKCR, 0), | ||
218 | [DIV6_FMSO] = SH_CLK_DIV6(&pllc1_div2_clk, FMSOCKCR, 0), | ||
219 | [DIV6_FSI] = SH_CLK_DIV6(&pllc1_div2_clk, FSICKCR, 0), | ||
220 | [DIV6_SUB] = SH_CLK_DIV6(&sh7377_extal2_clk, SUBUSBCKCR, 0), | ||
221 | [DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0), | ||
222 | [DIV6_MSU] = SH_CLK_DIV6(&pllc1_div2_clk, MSUCKCR, 0), | ||
223 | [DIV6_MVI3] = SH_CLK_DIV6(&pllc1_div2_clk, MVI3CKCR, 0), | ||
224 | [DIV6_HDMI] = SH_CLK_DIV6(&pllc1_div2_clk, HDMICKCR, 0), | ||
225 | [DIV6_MF1] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK1CR, 0), | ||
226 | [DIV6_MF2] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK2CR, 0), | ||
227 | [DIV6_DSIT] = SH_CLK_DIV6(&pllc1_div2_clk, DSITCKCR, 0), | ||
228 | [DIV6_DSIP] = SH_CLK_DIV6(&pllc1_div2_clk, DSIPCKCR, 0), | ||
229 | }; | ||
230 | |||
231 | enum { MSTP001, | ||
232 | MSTP131, MSTP130, MSTP129, MSTP128, MSTP116, MSTP106, MSTP101, | ||
233 | MSTP223, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200, | ||
234 | MSTP331, MSTP329, MSTP325, MSTP323, MSTP322, | ||
235 | MSTP315, MSTP314, MSTP313, | ||
236 | MSTP403, | ||
237 | MSTP_NR }; | ||
238 | |||
239 | #define MSTP(_parent, _reg, _bit, _flags) \ | ||
240 | SH_CLK_MSTP32(_parent, _reg, _bit, _flags) | ||
241 | |||
242 | static struct clk mstp_clks[] = { | ||
243 | [MSTP001] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 1, 0), /* IIC2 */ | ||
244 | [MSTP131] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 31, 0), /* VEU3 */ | ||
245 | [MSTP130] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 30, 0), /* VEU2 */ | ||
246 | [MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* VEU1 */ | ||
247 | [MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* VEU0 */ | ||
248 | [MSTP116] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */ | ||
249 | [MSTP106] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 6, 0), /* JPU */ | ||
250 | [MSTP101] = MSTP(&div4_clks[DIV4_M1], SMSTPCR1, 1, 0), /* VPU */ | ||
251 | [MSTP223] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR2, 23, 0), /* SPU2 */ | ||
252 | [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */ | ||
253 | [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */ | ||
254 | [MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */ | ||
255 | [MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */ | ||
256 | [MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */ | ||
257 | [MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */ | ||
258 | [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */ | ||
259 | [MSTP331] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 31, 0), /* SCIFA6 */ | ||
260 | [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */ | ||
261 | [MSTP325] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 25, 0), /* IRDA */ | ||
262 | [MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */ | ||
263 | [MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */ | ||
264 | [MSTP315] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 15, 0), /* FLCTL */ | ||
265 | [MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */ | ||
266 | [MSTP313] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */ | ||
267 | [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */ | ||
268 | }; | ||
269 | |||
270 | static struct clk_lookup lookups[] = { | ||
271 | /* main clocks */ | ||
272 | CLKDEV_CON_ID("r_clk", &r_clk), | ||
273 | CLKDEV_CON_ID("extalc1", &sh7377_extalc1_clk), | ||
274 | CLKDEV_CON_ID("extal2", &sh7377_extal2_clk), | ||
275 | CLKDEV_CON_ID("extalc1_div2_clk", &extalc1_div2_clk), | ||
276 | CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk), | ||
277 | CLKDEV_CON_ID("extal2_div4_clk", &extal2_div4_clk), | ||
278 | CLKDEV_CON_ID("pllc1_clk", &pllc1_clk), | ||
279 | CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk), | ||
280 | CLKDEV_CON_ID("pllc2_clk", &pllc2_clk), | ||
281 | |||
282 | /* DIV4 clocks */ | ||
283 | CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]), | ||
284 | CLKDEV_CON_ID("zg_clk", &div4_clks[DIV4_ZG]), | ||
285 | CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]), | ||
286 | CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]), | ||
287 | CLKDEV_CON_ID("csir_clk", &div4_clks[DIV4_CSIR]), | ||
288 | CLKDEV_CON_ID("ztr_clk", &div4_clks[DIV4_ZTR]), | ||
289 | CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]), | ||
290 | CLKDEV_CON_ID("z_clk", &div4_clks[DIV4_Z]), | ||
291 | CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]), | ||
292 | CLKDEV_CON_ID("zs_clk", &div4_clks[DIV4_ZS]), | ||
293 | CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]), | ||
294 | CLKDEV_CON_ID("zb3_clk", &div4_clks[DIV4_ZB3]), | ||
295 | CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]), | ||
296 | |||
297 | /* DIV6 clocks */ | ||
298 | CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]), | ||
299 | CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]), | ||
300 | CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]), | ||
301 | CLKDEV_CON_ID("fmsi_clk", &div6_clks[DIV6_FMSI]), | ||
302 | CLKDEV_CON_ID("fmso_clk", &div6_clks[DIV6_FMSO]), | ||
303 | CLKDEV_CON_ID("fsi_clk", &div6_clks[DIV6_FSI]), | ||
304 | CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]), | ||
305 | CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]), | ||
306 | CLKDEV_CON_ID("msu_clk", &div6_clks[DIV6_MSU]), | ||
307 | CLKDEV_CON_ID("mvi3_clk", &div6_clks[DIV6_MVI3]), | ||
308 | CLKDEV_CON_ID("hdmi_clk", &div6_clks[DIV6_HDMI]), | ||
309 | CLKDEV_CON_ID("mf1_clk", &div6_clks[DIV6_MF1]), | ||
310 | CLKDEV_CON_ID("mf2_clk", &div6_clks[DIV6_MF2]), | ||
311 | CLKDEV_CON_ID("dsit_clk", &div6_clks[DIV6_DSIT]), | ||
312 | CLKDEV_CON_ID("dsip_clk", &div6_clks[DIV6_DSIP]), | ||
313 | |||
314 | /* MSTP32 clocks */ | ||
315 | CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */ | ||
316 | CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[MSTP131]), /* VEU3 */ | ||
317 | CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[MSTP130]), /* VEU2 */ | ||
318 | CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[MSTP129]), /* VEU1 */ | ||
319 | CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[MSTP128]), /* VEU0 */ | ||
320 | CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */ | ||
321 | CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[MSTP106]), /* JPU */ | ||
322 | CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[MSTP101]), /* VPU */ | ||
323 | CLKDEV_DEV_ID("uio_pdrv_genirq.6", &mstp_clks[MSTP223]), /* SPU2DSP0 */ | ||
324 | CLKDEV_DEV_ID("uio_pdrv_genirq.7", &mstp_clks[MSTP223]), /* SPU2DSP1 */ | ||
325 | CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */ | ||
326 | CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP206]), /* SCIFB */ | ||
327 | CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */ | ||
328 | CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */ | ||
329 | CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */ | ||
330 | CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */ | ||
331 | CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */ | ||
332 | CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */ | ||
333 | CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */ | ||
334 | CLKDEV_DEV_ID("sh_irda", &mstp_clks[MSTP325]), /* IRDA */ | ||
335 | CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */ | ||
336 | CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP322]), /* USBHS */ | ||
337 | CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[MSTP322]), /* USBHS */ | ||
338 | CLKDEV_DEV_ID("sh_flctl", &mstp_clks[MSTP315]), /* FLCTL */ | ||
339 | CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */ | ||
340 | CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */ | ||
341 | CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */ | ||
342 | }; | ||
343 | |||
344 | void __init sh7377_clock_init(void) | ||
345 | { | ||
346 | int k, ret = 0; | ||
347 | |||
348 | for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) | ||
349 | ret = clk_register(main_clks[k]); | ||
350 | |||
351 | if (!ret) | ||
352 | ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); | ||
353 | |||
354 | if (!ret) | ||
355 | ret = sh_clk_div6_register(div6_clks, DIV6_NR); | ||
356 | |||
357 | if (!ret) | ||
358 | ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); | ||
359 | |||
360 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); | ||
361 | |||
362 | if (!ret) | ||
363 | shmobile_clk_init(); | ||
364 | else | ||
365 | panic("failed to setup sh7377 clocks\n"); | ||
366 | } | ||
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index f96fc29e5ae..dfeca79e9e9 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h | |||
@@ -18,15 +18,6 @@ extern int shmobile_enter_wfi(struct cpuidle_device *dev, | |||
18 | struct cpuidle_driver *drv, int index); | 18 | struct cpuidle_driver *drv, int index); |
19 | extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv); | 19 | extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv); |
20 | 20 | ||
21 | extern void sh7377_init_irq(void); | ||
22 | extern void sh7377_map_io(void); | ||
23 | extern void sh7377_add_early_devices(void); | ||
24 | extern void sh7377_add_standard_devices(void); | ||
25 | extern void sh7377_clock_init(void); | ||
26 | extern void sh7377_pinmux_init(void); | ||
27 | extern struct clk sh7377_extalc1_clk; | ||
28 | extern struct clk sh7377_extal2_clk; | ||
29 | |||
30 | extern void sh7372_init_irq(void); | 21 | extern void sh7372_init_irq(void); |
31 | extern void sh7372_map_io(void); | 22 | extern void sh7372_map_io(void); |
32 | extern void sh7372_add_early_devices(void); | 23 | extern void sh7372_add_early_devices(void); |
diff --git a/arch/arm/mach-shmobile/include/mach/sh7377.h b/arch/arm/mach-shmobile/include/mach/sh7377.h deleted file mode 100644 index f580e227dd1..00000000000 --- a/arch/arm/mach-shmobile/include/mach/sh7377.h +++ /dev/null | |||
@@ -1,360 +0,0 @@ | |||
1 | #ifndef __ASM_SH7377_H__ | ||
2 | #define __ASM_SH7377_H__ | ||
3 | |||
4 | /* Pin Function Controller: | ||
5 | * GPIO_FN_xx - GPIO used to select pin function | ||
6 | * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU | ||
7 | */ | ||
8 | enum { | ||
9 | /* 55-1 -> 55-5 (GPIO) */ | ||
10 | GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4, | ||
11 | GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9, | ||
12 | |||
13 | GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14, | ||
14 | GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19, | ||
15 | |||
16 | GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24, | ||
17 | GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29, | ||
18 | |||
19 | GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34, | ||
20 | GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39, | ||
21 | |||
22 | GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44, | ||
23 | GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49, | ||
24 | |||
25 | GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54, | ||
26 | GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59, | ||
27 | |||
28 | GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64, | ||
29 | GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69, | ||
30 | |||
31 | GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74, | ||
32 | GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79, | ||
33 | |||
34 | GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84, | ||
35 | GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89, | ||
36 | |||
37 | GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94, | ||
38 | GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99, | ||
39 | |||
40 | GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104, | ||
41 | GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109, | ||
42 | |||
43 | GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114, | ||
44 | GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, | ||
45 | |||
46 | GPIO_PORT128, GPIO_PORT129, | ||
47 | |||
48 | GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134, | ||
49 | GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139, | ||
50 | |||
51 | GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144, | ||
52 | GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149, | ||
53 | |||
54 | GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154, | ||
55 | GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159, | ||
56 | |||
57 | GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164, | ||
58 | |||
59 | GPIO_PORT192, GPIO_PORT193, GPIO_PORT194, | ||
60 | GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199, | ||
61 | |||
62 | GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204, | ||
63 | GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209, | ||
64 | |||
65 | GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214, | ||
66 | GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219, | ||
67 | |||
68 | GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT223, GPIO_PORT224, | ||
69 | GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229, | ||
70 | |||
71 | GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234, | ||
72 | GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239, | ||
73 | |||
74 | GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244, | ||
75 | GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249, | ||
76 | |||
77 | GPIO_PORT250, GPIO_PORT251, GPIO_PORT252, GPIO_PORT253, GPIO_PORT254, | ||
78 | GPIO_PORT255, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259, | ||
79 | |||
80 | GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264, | ||
81 | |||
82 | /* Special Pull-up / Pull-down Functions */ | ||
83 | GPIO_FN_PORT66_KEYIN0_PU, GPIO_FN_PORT67_KEYIN1_PU, | ||
84 | GPIO_FN_PORT68_KEYIN2_PU, GPIO_FN_PORT69_KEYIN3_PU, | ||
85 | GPIO_FN_PORT70_KEYIN4_PU, GPIO_FN_PORT71_KEYIN5_PU, | ||
86 | GPIO_FN_PORT72_KEYIN6_PU, | ||
87 | |||
88 | /* 55-1 (FN) */ | ||
89 | GPIO_FN_VBUS_0, | ||
90 | GPIO_FN_CPORT0, | ||
91 | GPIO_FN_CPORT1, | ||
92 | GPIO_FN_CPORT2, | ||
93 | GPIO_FN_CPORT3, | ||
94 | GPIO_FN_CPORT4, | ||
95 | GPIO_FN_CPORT5, | ||
96 | GPIO_FN_CPORT6, | ||
97 | GPIO_FN_CPORT7, | ||
98 | GPIO_FN_CPORT8, | ||
99 | GPIO_FN_CPORT9, | ||
100 | GPIO_FN_CPORT10, | ||
101 | GPIO_FN_CPORT11, GPIO_FN_SIN2, | ||
102 | GPIO_FN_CPORT12, GPIO_FN_XCTS2, | ||
103 | GPIO_FN_CPORT13, GPIO_FN_RFSPO4, | ||
104 | GPIO_FN_CPORT14, GPIO_FN_RFSPO5, | ||
105 | GPIO_FN_CPORT15, GPIO_FN_SCIFA0_SCK, GPIO_FN_GPS_AGC2, | ||
106 | GPIO_FN_CPORT16, GPIO_FN_SCIFA0_TXD, GPIO_FN_GPS_AGC3, | ||
107 | GPIO_FN_CPORT17_IC_OE, GPIO_FN_SOUT2, | ||
108 | GPIO_FN_CPORT18, GPIO_FN_XRTS2, GPIO_FN_PORT19_VIO_CKO2, | ||
109 | GPIO_FN_CPORT19_MPORT1, | ||
110 | GPIO_FN_CPORT20, GPIO_FN_RFSPO6, | ||
111 | GPIO_FN_CPORT21, GPIO_FN_STATUS0, | ||
112 | GPIO_FN_CPORT22, GPIO_FN_STATUS1, | ||
113 | GPIO_FN_CPORT23, GPIO_FN_STATUS2, GPIO_FN_RFSPO7, | ||
114 | GPIO_FN_B_SYNLD1, | ||
115 | GPIO_FN_B_SYNLD2, GPIO_FN_SYSENMSK, | ||
116 | GPIO_FN_XMAINPS, | ||
117 | GPIO_FN_XDIVPS, | ||
118 | GPIO_FN_XIDRST, | ||
119 | GPIO_FN_IDCLK, GPIO_FN_IC_DP, | ||
120 | GPIO_FN_IDIO, GPIO_FN_IC_DM, | ||
121 | GPIO_FN_SOUT1, GPIO_FN_SCIFA4_TXD, GPIO_FN_M02_BERDAT, | ||
122 | GPIO_FN_SIN1, GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP, | ||
123 | GPIO_FN_XRTS1, GPIO_FN_SCIFA4_RTS, GPIO_FN_M03_BERCLK, | ||
124 | GPIO_FN_XCTS1, GPIO_FN_SCIFA4_CTS, | ||
125 | GPIO_FN_PCMCLKO, | ||
126 | GPIO_FN_SYNC8KO, | ||
127 | |||
128 | /* 55-2 (FN) */ | ||
129 | GPIO_FN_DNPCM_A, | ||
130 | GPIO_FN_UPPCM_A, | ||
131 | GPIO_FN_VACK, | ||
132 | GPIO_FN_XTALB1L, | ||
133 | GPIO_FN_GPS_AGC1, GPIO_FN_SCIFA0_RTS, | ||
134 | GPIO_FN_GPS_AGC4, GPIO_FN_SCIFA0_RXD, | ||
135 | GPIO_FN_GPS_PWRDOWN, GPIO_FN_SCIFA0_CTS, | ||
136 | GPIO_FN_GPS_IM, | ||
137 | GPIO_FN_GPS_IS, | ||
138 | GPIO_FN_GPS_QM, | ||
139 | GPIO_FN_GPS_QS, | ||
140 | GPIO_FN_FMSOCK, GPIO_FN_PORT49_IRDA_OUT, GPIO_FN_PORT49_IROUT, | ||
141 | GPIO_FN_FMSOOLR, GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2, GPIO_FN_IPORT3, | ||
142 | GPIO_FN_FMSIOLR, | ||
143 | GPIO_FN_FMSOOBT, GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3, GPIO_FN_OPORT1, | ||
144 | GPIO_FN_FMSIOBT, | ||
145 | GPIO_FN_FMSOSLD, GPIO_FN_BBIF2_TXD2, GPIO_FN_OPORT2, | ||
146 | GPIO_FN_FMSOILR, GPIO_FN_PORT53_IRDA_IN, GPIO_FN_TPU3TO3, | ||
147 | GPIO_FN_OPORT3, GPIO_FN_FMSIILR, | ||
148 | GPIO_FN_FMSOIBT, GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2, | ||
149 | GPIO_FN_FMSIIBT, | ||
150 | GPIO_FN_FMSISLD, GPIO_FN_MFG0_OUT1, GPIO_FN_TPU0TO0, | ||
151 | GPIO_FN_A0_EA0, GPIO_FN_BS, | ||
152 | GPIO_FN_A12_EA12, GPIO_FN_PORT58_VIO_CKOR, GPIO_FN_TPU4TO2, | ||
153 | GPIO_FN_A13_EA13, GPIO_FN_PORT59_IROUT, GPIO_FN_MFG0_OUT2, | ||
154 | GPIO_FN_TPU0TO1, | ||
155 | GPIO_FN_A14_EA14, GPIO_FN_PORT60_KEYOUT5, | ||
156 | GPIO_FN_A15_EA15, GPIO_FN_PORT61_KEYOUT4, | ||
157 | GPIO_FN_A16_EA16, GPIO_FN_PORT62_KEYOUT3, GPIO_FN_MSIOF0_SS1, | ||
158 | GPIO_FN_A17_EA17, GPIO_FN_PORT63_KEYOUT2, GPIO_FN_MSIOF0_TSYNC, | ||
159 | GPIO_FN_A18_EA18, GPIO_FN_PORT64_KEYOUT1, GPIO_FN_MSIOF0_TSCK, | ||
160 | GPIO_FN_A19_EA19, GPIO_FN_PORT65_KEYOUT0, GPIO_FN_MSIOF0_TXD, | ||
161 | GPIO_FN_A20_EA20, GPIO_FN_PORT66_KEYIN0, GPIO_FN_MSIOF0_RSCK, | ||
162 | GPIO_FN_A21_EA21, GPIO_FN_PORT67_KEYIN1, GPIO_FN_MSIOF0_RSYNC, | ||
163 | GPIO_FN_A22_EA22, GPIO_FN_PORT68_KEYIN2, GPIO_FN_MSIOF0_MCK0, | ||
164 | GPIO_FN_A23_EA23, GPIO_FN_PORT69_KEYIN3, GPIO_FN_MSIOF0_MCK1, | ||
165 | GPIO_FN_A24_EA24, GPIO_FN_PORT70_KEYIN4, GPIO_FN_MSIOF0_RXD, | ||
166 | GPIO_FN_A25_EA25, GPIO_FN_PORT71_KEYIN5, GPIO_FN_MSIOF0_SS2, | ||
167 | GPIO_FN_A26, GPIO_FN_PORT72_KEYIN6, | ||
168 | GPIO_FN_D0_ED0_NAF0, | ||
169 | GPIO_FN_D1_ED1_NAF1, | ||
170 | GPIO_FN_D2_ED2_NAF2, | ||
171 | GPIO_FN_D3_ED3_NAF3, | ||
172 | GPIO_FN_D4_ED4_NAF4, | ||
173 | GPIO_FN_D5_ED5_NAF5, | ||
174 | GPIO_FN_D6_ED6_NAF6, | ||
175 | GPIO_FN_D7_ED7_NAF7, | ||
176 | GPIO_FN_D8_ED8_NAF8, | ||
177 | GPIO_FN_D9_ED9_NAF9, | ||
178 | GPIO_FN_D10_ED10_NAF10, | ||
179 | GPIO_FN_D11_ED11_NAF11, | ||
180 | GPIO_FN_D12_ED12_NAF12, | ||
181 | GPIO_FN_D13_ED13_NAF13, | ||
182 | GPIO_FN_D14_ED14_NAF14, | ||
183 | GPIO_FN_D15_ED15_NAF15, | ||
184 | GPIO_FN_CS4, | ||
185 | GPIO_FN_CS5A, GPIO_FN_FMSICK, | ||
186 | GPIO_FN_CS5B, GPIO_FN_FCE1, | ||
187 | |||
188 | /* 55-3 (FN) */ | ||
189 | GPIO_FN_CS6B, GPIO_FN_XCS2, GPIO_FN_CS6A, GPIO_FN_DACK0, | ||
190 | GPIO_FN_FCE0, | ||
191 | GPIO_FN_WAIT, GPIO_FN_DREQ0, | ||
192 | GPIO_FN_RD_XRD, | ||
193 | GPIO_FN_WE0_XWR0_FWE, | ||
194 | GPIO_FN_WE1_XWR1, | ||
195 | GPIO_FN_FRB, | ||
196 | GPIO_FN_CKO, | ||
197 | GPIO_FN_NBRSTOUT, | ||
198 | GPIO_FN_NBRST, | ||
199 | GPIO_FN_GPS_EPPSIN, | ||
200 | GPIO_FN_LATCHPULSE, | ||
201 | GPIO_FN_LTESIGNAL, | ||
202 | GPIO_FN_LEGACYSTATE, | ||
203 | GPIO_FN_TCKON, | ||
204 | GPIO_FN_VIO_VD, GPIO_FN_PORT128_KEYOUT0, GPIO_FN_IPORT0, | ||
205 | GPIO_FN_VIO_HD, GPIO_FN_PORT129_KEYOUT1, GPIO_FN_IPORT1, | ||
206 | GPIO_FN_VIO_D0, GPIO_FN_PORT130_KEYOUT2, GPIO_FN_PORT130_MSIOF2_RXD, | ||
207 | GPIO_FN_VIO_D1, GPIO_FN_PORT131_KEYOUT3, GPIO_FN_PORT131_MSIOF2_SS1, | ||
208 | GPIO_FN_VIO_D2, GPIO_FN_PORT132_KEYOUT4, GPIO_FN_PORT132_MSIOF2_SS2, | ||
209 | GPIO_FN_VIO_D3, GPIO_FN_PORT133_KEYOUT5, GPIO_FN_PORT133_MSIOF2_TSYNC, | ||
210 | GPIO_FN_VIO_D4, GPIO_FN_PORT134_KEYIN0, GPIO_FN_PORT134_MSIOF2_TXD, | ||
211 | GPIO_FN_VIO_D5, GPIO_FN_PORT135_KEYIN1, GPIO_FN_PORT135_MSIOF2_TSCK, | ||
212 | GPIO_FN_VIO_D6, GPIO_FN_PORT136_KEYIN2, | ||
213 | GPIO_FN_VIO_D7, GPIO_FN_PORT137_KEYIN3, | ||
214 | GPIO_FN_VIO_D8, GPIO_FN_M9_SLCD_A01, GPIO_FN_PORT138_FSIAOMC, | ||
215 | GPIO_FN_VIO_D9, GPIO_FN_M10_SLCD_CK1, GPIO_FN_PORT139_FSIAOLR, | ||
216 | GPIO_FN_VIO_D10, GPIO_FN_M11_SLCD_SO1, GPIO_FN_TPU0TO2, | ||
217 | GPIO_FN_PORT140_FSIAOBT, | ||
218 | GPIO_FN_VIO_D11, GPIO_FN_M12_SLCD_CE1, GPIO_FN_TPU0TO3, | ||
219 | GPIO_FN_PORT141_FSIAOSLD, | ||
220 | GPIO_FN_VIO_D12, GPIO_FN_M13_BSW, GPIO_FN_PORT142_FSIACK, | ||
221 | GPIO_FN_VIO_D13, GPIO_FN_M14_GSW, GPIO_FN_PORT143_FSIAILR, | ||
222 | GPIO_FN_VIO_D14, GPIO_FN_M15_RSW, GPIO_FN_PORT144_FSIAIBT, | ||
223 | GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3, GPIO_FN_PORT145_FSIAISLD, | ||
224 | GPIO_FN_VIO_CLK, GPIO_FN_PORT146_KEYIN4, GPIO_FN_IPORT2, | ||
225 | GPIO_FN_VIO_FIELD, GPIO_FN_PORT147_KEYIN5, | ||
226 | GPIO_FN_VIO_CKO, GPIO_FN_PORT148_KEYIN6, | ||
227 | GPIO_FN_A27, GPIO_FN_RDWR_XWE, GPIO_FN_MFG0_IN1, | ||
228 | GPIO_FN_MFG0_IN2, | ||
229 | GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK, | ||
230 | GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC, | ||
231 | GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT153_MSIOF2_SS1, | ||
232 | GPIO_FN_SOUT3, GPIO_FN_SCIFA2_TXD1, GPIO_FN_MSIOF2_MCK0, | ||
233 | GPIO_FN_SIN3, GPIO_FN_SCIFA2_RXD1, GPIO_FN_MSIOF2_MCK1, | ||
234 | GPIO_FN_XRTS3, GPIO_FN_SCIFA2_RTS1, GPIO_FN_PORT156_MSIOF2_SS2, | ||
235 | GPIO_FN_XCTS3, GPIO_FN_SCIFA2_CTS1, GPIO_FN_PORT157_MSIOF2_RXD, | ||
236 | |||
237 | /* 55-4 (FN) */ | ||
238 | GPIO_FN_DINT, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3, | ||
239 | GPIO_FN_PORT159_SCIFB_SCK, GPIO_FN_PORT159_SCIFA5_SCK, GPIO_FN_NMI, | ||
240 | GPIO_FN_PORT160_SCIFB_TXD, GPIO_FN_PORT160_SCIFA5_TXD, GPIO_FN_SOUT0, | ||
241 | GPIO_FN_PORT161_SCIFB_CTS, GPIO_FN_PORT161_SCIFA5_CTS, GPIO_FN_XCTS0, | ||
242 | GPIO_FN_MFG3_IN2, | ||
243 | GPIO_FN_PORT162_SCIFB_RXD, GPIO_FN_PORT162_SCIFA5_RXD, GPIO_FN_SIN0, | ||
244 | GPIO_FN_MFG3_IN1, | ||
245 | GPIO_FN_PORT163_SCIFB_RTS, GPIO_FN_PORT163_SCIFA5_RTS, GPIO_FN_XRTS0, | ||
246 | GPIO_FN_MFG3_OUT1, | ||
247 | GPIO_FN_TPU3TO0, | ||
248 | GPIO_FN_LCDD0, GPIO_FN_PORT192_KEYOUT0, GPIO_FN_EXT_CKI, | ||
249 | GPIO_FN_LCDD1, GPIO_FN_PORT193_KEYOUT1, GPIO_FN_PORT193_SCIFA5_CTS, | ||
250 | GPIO_FN_BBIF2_TSYNC1, | ||
251 | GPIO_FN_LCDD2, GPIO_FN_PORT194_KEYOUT2, GPIO_FN_PORT194_SCIFA5_RTS, | ||
252 | GPIO_FN_BBIF2_TSCK1, | ||
253 | GPIO_FN_LCDD3, GPIO_FN_PORT195_KEYOUT3, GPIO_FN_PORT195_SCIFA5_RXD, | ||
254 | GPIO_FN_BBIF2_TXD1, | ||
255 | GPIO_FN_LCDD4, GPIO_FN_PORT196_KEYOUT4, GPIO_FN_PORT196_SCIFA5_TXD, | ||
256 | GPIO_FN_LCDD5, GPIO_FN_PORT197_KEYOUT5, GPIO_FN_PORT197_SCIFA5_SCK, | ||
257 | GPIO_FN_MFG2_OUT2, GPIO_FN_TPU2TO1, | ||
258 | GPIO_FN_LCDD6, GPIO_FN_XWR2, | ||
259 | GPIO_FN_LCDD7, GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2, GPIO_FN_XWR3, | ||
260 | GPIO_FN_LCDD8, GPIO_FN_PORT200_KEYIN0, GPIO_FN_VIO_DR0, GPIO_FN_D16, | ||
261 | GPIO_FN_ED16, | ||
262 | GPIO_FN_LCDD9, GPIO_FN_PORT201_KEYIN1, GPIO_FN_VIO_DR1, GPIO_FN_D17, | ||
263 | GPIO_FN_ED17, | ||
264 | GPIO_FN_LCDD10, GPIO_FN_PORT202_KEYIN2, GPIO_FN_VIO_DR2, GPIO_FN_D18, | ||
265 | GPIO_FN_ED18, | ||
266 | GPIO_FN_LCDD11, GPIO_FN_PORT203_KEYIN3, GPIO_FN_VIO_DR3, GPIO_FN_D19, | ||
267 | GPIO_FN_ED19, | ||
268 | GPIO_FN_LCDD12, GPIO_FN_PORT204_KEYIN4, GPIO_FN_VIO_DR4, GPIO_FN_D20, | ||
269 | GPIO_FN_ED20, | ||
270 | GPIO_FN_LCDD13, GPIO_FN_PORT205_KEYIN5, GPIO_FN_VIO_DR5, GPIO_FN_D21, | ||
271 | GPIO_FN_ED21, | ||
272 | GPIO_FN_LCDD14, GPIO_FN_PORT206_KEYIN6, GPIO_FN_VIO_DR6, GPIO_FN_D22, | ||
273 | GPIO_FN_ED22, | ||
274 | GPIO_FN_LCDD15, GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_PORT207_KEYOUT0, | ||
275 | GPIO_FN_VIO_DR7, | ||
276 | GPIO_FN_D23, GPIO_FN_ED23, | ||
277 | GPIO_FN_LCDD16, GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_PORT208_KEYOUT1, | ||
278 | GPIO_FN_VIO_VDR, | ||
279 | GPIO_FN_D24, GPIO_FN_ED24, | ||
280 | GPIO_FN_LCDD17, GPIO_FN_PORT209_KEYOUT2, GPIO_FN_VIO_HDR, GPIO_FN_D25, | ||
281 | GPIO_FN_ED25, | ||
282 | GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26, | ||
283 | GPIO_FN_ED26, | ||
284 | GPIO_FN_LCDD19, GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27, GPIO_FN_ED27, | ||
285 | GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28, | ||
286 | GPIO_FN_ED28, | ||
287 | GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29, | ||
288 | GPIO_FN_ED29, | ||
289 | GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30, | ||
290 | GPIO_FN_ED30, | ||
291 | GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31, | ||
292 | GPIO_FN_ED31, | ||
293 | GPIO_FN_LCDDCK, GPIO_FN_LCDWR, GPIO_FN_PORT216_KEYOUT3, | ||
294 | GPIO_FN_VIO_CLKR, | ||
295 | GPIO_FN_LCDRD, GPIO_FN_DACK2, GPIO_FN_MSIOF0L_TSYNC, | ||
296 | GPIO_FN_LCDHSYN, GPIO_FN_LCDCS, GPIO_FN_LCDCS2, GPIO_FN_DACK3, | ||
297 | GPIO_FN_PORT218_VIO_CKOR, GPIO_FN_PORT218_KEYOUT4, | ||
298 | GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_TSCK, | ||
299 | GPIO_FN_LCDVSYN, GPIO_FN_LCDVSYN2, GPIO_FN_PORT220_KEYOUT5, | ||
300 | GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_PWEN, GPIO_FN_MSIOF0L_RXD, | ||
301 | GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_OVCN, | ||
302 | GPIO_FN_MSIOF0L_TXD, | ||
303 | GPIO_FN_SCIFA1_TXD, GPIO_FN_OVCN2, | ||
304 | GPIO_FN_EXTLP, GPIO_FN_SCIFA1_SCK, GPIO_FN_USBTERM, | ||
305 | GPIO_FN_PORT226_VIO_CKO2, | ||
306 | GPIO_FN_SCIFA1_RTS, GPIO_FN_IDIN, | ||
307 | GPIO_FN_SCIFA1_RXD, | ||
308 | GPIO_FN_SCIFA1_CTS, GPIO_FN_MFG1_IN1, | ||
309 | GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA2_TXD2, GPIO_FN_PORT230_FSIAOMC, | ||
310 | GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA2_CTS2, GPIO_FN_PORT231_FSIAOLR, | ||
311 | GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA2_SCK2, GPIO_FN_PORT232_FSIAOBT, | ||
312 | GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA2_RXD2, GPIO_FN_GPS_VCOTRIG, | ||
313 | GPIO_FN_PORT233_FSIACK, | ||
314 | GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA2_RTS2, GPIO_FN_PORT234_FSIAOSLD, | ||
315 | GPIO_FN_MSIOF1_RSYNC, GPIO_FN_OPORT0, GPIO_FN_MFG1_IN2, | ||
316 | GPIO_FN_PORT235_FSIAILR, | ||
317 | GPIO_FN_MSIOF1_MCK0, GPIO_FN_I2C_SDA2, GPIO_FN_PORT236_FSIAIBT, | ||
318 | GPIO_FN_MSIOF1_MCK1, GPIO_FN_I2C_SCL2, GPIO_FN_PORT237_FSIAISLD, | ||
319 | GPIO_FN_MSIOF1_SS1, GPIO_FN_EDBGREQ3, | ||
320 | |||
321 | /* 55-5 (FN) */ | ||
322 | GPIO_FN_MSIOF1_SS2, | ||
323 | GPIO_FN_SCIFA6_TXD, | ||
324 | GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, | ||
325 | GPIO_FN_TPU4TO0, | ||
326 | GPIO_FN_PORT242_IRDA_IN, GPIO_FN_MFG4_IN2, | ||
327 | GPIO_FN_PORT243_IRDA_FIRSEL, GPIO_FN_PORT243_VIO_CKO2, | ||
328 | GPIO_FN_PORT244_SCIFA5_CTS, GPIO_FN_MFG2_IN1, GPIO_FN_PORT244_SCIFB_CTS, | ||
329 | GPIO_FN_PORT244_MSIOF2_RXD, | ||
330 | GPIO_FN_PORT245_SCIFA5_RTS, GPIO_FN_MFG2_IN2, GPIO_FN_PORT245_SCIFB_RTS, | ||
331 | GPIO_FN_PORT245_MSIOF2_TXD, | ||
332 | GPIO_FN_PORT246_SCIFA5_RXD, GPIO_FN_MFG1_OUT1, | ||
333 | GPIO_FN_PORT246_SCIFB_RXD, GPIO_FN_TPU1TO0, | ||
334 | GPIO_FN_PORT247_SCIFA5_TXD, GPIO_FN_MFG3_OUT2, | ||
335 | GPIO_FN_PORT247_SCIFB_TXD, GPIO_FN_TPU3TO1, | ||
336 | GPIO_FN_PORT248_SCIFA5_SCK, GPIO_FN_MFG2_OUT1, | ||
337 | GPIO_FN_PORT248_SCIFB_SCK, GPIO_FN_TPU2TO0, | ||
338 | GPIO_FN_PORT248_MSIOF2_TSCK, | ||
339 | GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, GPIO_FN_PORT249_MSIOF2_TSYNC, | ||
340 | GPIO_FN_SDHICLK0, GPIO_FN_TCK2_SWCLK_MC0, | ||
341 | GPIO_FN_SDHICD0, | ||
342 | GPIO_FN_SDHID0_0, GPIO_FN_TMS2_SWDIO_MC0, | ||
343 | GPIO_FN_SDHID0_1, GPIO_FN_TDO2_SWO0_MC0, | ||
344 | GPIO_FN_SDHID0_2, GPIO_FN_TDI2, | ||
345 | GPIO_FN_SDHID0_3, GPIO_FN_RTCK2_SWO1_MC0, | ||
346 | GPIO_FN_SDHICMD0, GPIO_FN_TRST2, | ||
347 | GPIO_FN_SDHIWP0, GPIO_FN_EDBGREQ2, | ||
348 | GPIO_FN_SDHICLK1, GPIO_FN_TCK3_SWCLK_MC1, | ||
349 | GPIO_FN_SDHID1_0, GPIO_FN_M11_SLCD_SO2, GPIO_FN_TS_SPSYNC2, | ||
350 | GPIO_FN_TMS3_SWDIO_MC1, | ||
351 | GPIO_FN_SDHID1_1, GPIO_FN_M9_SLCD_A02, GPIO_FN_TS_SDAT2, | ||
352 | GPIO_FN_TDO3_SWO0_MC1, | ||
353 | GPIO_FN_SDHID1_2, GPIO_FN_M10_SLCD_CK2, GPIO_FN_TS_SDEN2, GPIO_FN_TDI3, | ||
354 | GPIO_FN_SDHID1_3, GPIO_FN_M12_SLCD_CE2, GPIO_FN_TS_SCK2, | ||
355 | GPIO_FN_RTCK3_SWO1_MC1, | ||
356 | GPIO_FN_SDHICMD1, GPIO_FN_TRST3, | ||
357 | GPIO_FN_RESETOUTS, | ||
358 | }; | ||
359 | |||
360 | #endif /* __ASM_SH7377_H__ */ | ||
diff --git a/arch/arm/mach-shmobile/intc-sh7377.c b/arch/arm/mach-shmobile/intc-sh7377.c deleted file mode 100644 index b84a460a340..00000000000 --- a/arch/arm/mach-shmobile/intc-sh7377.c +++ /dev/null | |||
@@ -1,592 +0,0 @@ | |||
1 | /* | ||
2 | * sh7377 processor support - INTC hardware block | ||
3 | * | ||
4 | * Copyright (C) 2010 Magnus Damm | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; version 2 of the License. | ||
9 | * | ||
10 | * This program is distributed in the hope that it will be useful, | ||
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
13 | * GNU General Public License for more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program; if not, write to the Free Software | ||
17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
18 | */ | ||
19 | #include <linux/kernel.h> | ||
20 | #include <linux/init.h> | ||
21 | #include <linux/interrupt.h> | ||
22 | #include <linux/irq.h> | ||
23 | #include <linux/io.h> | ||
24 | #include <linux/sh_intc.h> | ||
25 | #include <mach/intc.h> | ||
26 | #include <mach/irqs.h> | ||
27 | #include <asm/mach-types.h> | ||
28 | #include <asm/mach/arch.h> | ||
29 | |||
30 | enum { | ||
31 | UNUSED_INTCA = 0, | ||
32 | ENABLED, | ||
33 | DISABLED, | ||
34 | |||
35 | /* interrupt sources INTCA */ | ||
36 | DIRC, | ||
37 | _2DG, | ||
38 | CRYPT_STD, | ||
39 | IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1, | ||
40 | AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMRX, | ||
41 | MFI_MFIM, MFI_MFIS, | ||
42 | BBIF1, BBIF2, | ||
43 | USBDMAC_USHDMI, | ||
44 | USBHS_USHI0, USBHS_USHI1, | ||
45 | _3DG_SGX540, | ||
46 | CMT1_CMT10, CMT1_CMT11, CMT1_CMT12, CMT1_CMT13, CMT2, CMT3, | ||
47 | KEYSC_KEY, | ||
48 | SCIFA0, SCIFA1, SCIFA2, SCIFA3, | ||
49 | MSIOF2, MSIOF1, | ||
50 | SCIFA4, SCIFA5, SCIFB, | ||
51 | FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, | ||
52 | SDHI0, | ||
53 | SDHI1, | ||
54 | MSU_MSU, MSU_MSU2, | ||
55 | IRREM, | ||
56 | MSUG, | ||
57 | IRDA, | ||
58 | TPU0, TPU1, TPU2, TPU3, TPU4, | ||
59 | LCRC, | ||
60 | PINTCA_PINT1, PINTCA_PINT2, | ||
61 | TTI20, | ||
62 | MISTY, | ||
63 | DDM, | ||
64 | RWDT0, RWDT1, | ||
65 | DMAC_1_DEI0, DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3, | ||
66 | DMAC_2_DEI4, DMAC_2_DEI5, DMAC_2_DADERR, | ||
67 | DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3, | ||
68 | DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR, | ||
69 | DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3, | ||
70 | DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR, | ||
71 | SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, | ||
72 | ICUSB_ICUSB0, ICUSB_ICUSB1, | ||
73 | ICUDMC_ICUDMC1, ICUDMC_ICUDMC2, | ||
74 | SPU2_SPU0, SPU2_SPU1, | ||
75 | FSI, | ||
76 | FMSI, | ||
77 | SCUV, | ||
78 | IPMMU_IPMMUB, | ||
79 | AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ, AP_ARM_DMAIRQ, AP_ARM_DMASIRQ, | ||
80 | MFIS2, | ||
81 | CPORTR2S, | ||
82 | CMT14, CMT15, | ||
83 | SCIFA6, | ||
84 | |||
85 | /* interrupt groups INTCA */ | ||
86 | DMAC_1, DMAC_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, SHWYSTAT, | ||
87 | AP_ARM1, AP_ARM2, USBHS, SPU2, FLCTL, IIC1, | ||
88 | ICUSB, ICUDMC | ||
89 | }; | ||
90 | |||
91 | static struct intc_vect intca_vectors[] __initdata = { | ||
92 | INTC_VECT(DIRC, 0x0560), | ||
93 | INTC_VECT(_2DG, 0x05e0), | ||
94 | INTC_VECT(CRYPT_STD, 0x0700), | ||
95 | INTC_VECT(IIC1_ALI1, 0x0780), INTC_VECT(IIC1_TACKI1, 0x07a0), | ||
96 | INTC_VECT(IIC1_WAITI1, 0x07c0), INTC_VECT(IIC1_DTEI1, 0x07e0), | ||
97 | INTC_VECT(AP_ARM_IRQPMU, 0x0800), INTC_VECT(AP_ARM_COMMTX, 0x0840), | ||
98 | INTC_VECT(AP_ARM_COMMRX, 0x0860), | ||
99 | INTC_VECT(MFI_MFIM, 0x0900), INTC_VECT(MFI_MFIS, 0x0920), | ||
100 | INTC_VECT(BBIF1, 0x0940), INTC_VECT(BBIF2, 0x0960), | ||
101 | INTC_VECT(USBDMAC_USHDMI, 0x0a00), | ||
102 | INTC_VECT(USBHS_USHI0, 0x0a20), INTC_VECT(USBHS_USHI1, 0x0a40), | ||
103 | INTC_VECT(_3DG_SGX540, 0x0a60), | ||
104 | INTC_VECT(CMT1_CMT10, 0x0b00), INTC_VECT(CMT1_CMT11, 0x0b20), | ||
105 | INTC_VECT(CMT1_CMT12, 0x0b40), INTC_VECT(CMT1_CMT13, 0x0b60), | ||
106 | INTC_VECT(CMT2, 0x0b80), INTC_VECT(CMT3, 0x0ba0), | ||
107 | INTC_VECT(KEYSC_KEY, 0x0be0), | ||
108 | INTC_VECT(SCIFA0, 0x0c00), INTC_VECT(SCIFA1, 0x0c20), | ||
109 | INTC_VECT(SCIFA2, 0x0c40), INTC_VECT(SCIFA3, 0x0c60), | ||
110 | INTC_VECT(MSIOF2, 0x0c80), INTC_VECT(MSIOF1, 0x0d00), | ||
111 | INTC_VECT(SCIFA4, 0x0d20), INTC_VECT(SCIFA5, 0x0d40), | ||
112 | INTC_VECT(SCIFB, 0x0d60), | ||
113 | INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0), | ||
114 | INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0), | ||
115 | INTC_VECT(SDHI0, 0x0e00), INTC_VECT(SDHI0, 0x0e20), | ||
116 | INTC_VECT(SDHI0, 0x0e40), INTC_VECT(SDHI0, 0x0e60), | ||
117 | INTC_VECT(SDHI1, 0x0e80), INTC_VECT(SDHI1, 0x0ea0), | ||
118 | INTC_VECT(SDHI1, 0x0ec0), INTC_VECT(SDHI1, 0x0ee0), | ||
119 | INTC_VECT(MSU_MSU, 0x0f20), INTC_VECT(MSU_MSU2, 0x0f40), | ||
120 | INTC_VECT(IRREM, 0x0f60), | ||
121 | INTC_VECT(MSUG, 0x0fa0), | ||
122 | INTC_VECT(IRDA, 0x0480), | ||
123 | INTC_VECT(TPU0, 0x04a0), INTC_VECT(TPU1, 0x04c0), | ||
124 | INTC_VECT(TPU2, 0x04e0), INTC_VECT(TPU3, 0x0500), | ||
125 | INTC_VECT(TPU4, 0x0520), | ||
126 | INTC_VECT(LCRC, 0x0540), | ||
127 | INTC_VECT(PINTCA_PINT1, 0x1000), INTC_VECT(PINTCA_PINT2, 0x1020), | ||
128 | INTC_VECT(TTI20, 0x1100), | ||
129 | INTC_VECT(MISTY, 0x1120), | ||
130 | INTC_VECT(DDM, 0x1140), | ||
131 | INTC_VECT(RWDT0, 0x1280), INTC_VECT(RWDT1, 0x12a0), | ||
132 | INTC_VECT(DMAC_1_DEI0, 0x2000), INTC_VECT(DMAC_1_DEI1, 0x2020), | ||
133 | INTC_VECT(DMAC_1_DEI2, 0x2040), INTC_VECT(DMAC_1_DEI3, 0x2060), | ||
134 | INTC_VECT(DMAC_2_DEI4, 0x2080), INTC_VECT(DMAC_2_DEI5, 0x20a0), | ||
135 | INTC_VECT(DMAC_2_DADERR, 0x20c0), | ||
136 | INTC_VECT(DMAC2_1_DEI0, 0x2100), INTC_VECT(DMAC2_1_DEI1, 0x2120), | ||
137 | INTC_VECT(DMAC2_1_DEI2, 0x2140), INTC_VECT(DMAC2_1_DEI3, 0x2160), | ||
138 | INTC_VECT(DMAC2_2_DEI4, 0x2180), INTC_VECT(DMAC2_2_DEI5, 0x21a0), | ||
139 | INTC_VECT(DMAC2_2_DADERR, 0x21c0), | ||
140 | INTC_VECT(DMAC3_1_DEI0, 0x2200), INTC_VECT(DMAC3_1_DEI1, 0x2220), | ||
141 | INTC_VECT(DMAC3_1_DEI2, 0x2240), INTC_VECT(DMAC3_1_DEI3, 0x2260), | ||
142 | INTC_VECT(DMAC3_2_DEI4, 0x2280), INTC_VECT(DMAC3_2_DEI5, 0x22a0), | ||
143 | INTC_VECT(DMAC3_2_DADERR, 0x22c0), | ||
144 | INTC_VECT(SHWYSTAT_RT, 0x1300), INTC_VECT(SHWYSTAT_HS, 0x1d20), | ||
145 | INTC_VECT(SHWYSTAT_COM, 0x1340), | ||
146 | INTC_VECT(ICUSB_ICUSB0, 0x1700), INTC_VECT(ICUSB_ICUSB1, 0x1720), | ||
147 | INTC_VECT(ICUDMC_ICUDMC1, 0x1780), INTC_VECT(ICUDMC_ICUDMC2, 0x17a0), | ||
148 | INTC_VECT(SPU2_SPU0, 0x1800), INTC_VECT(SPU2_SPU1, 0x1820), | ||
149 | INTC_VECT(FSI, 0x1840), | ||
150 | INTC_VECT(FMSI, 0x1860), | ||
151 | INTC_VECT(SCUV, 0x1880), | ||
152 | INTC_VECT(IPMMU_IPMMUB, 0x1900), | ||
153 | INTC_VECT(AP_ARM_CTIIRQ, 0x1980), | ||
154 | INTC_VECT(AP_ARM_DMAEXTERRIRQ, 0x19a0), | ||
155 | INTC_VECT(AP_ARM_DMAIRQ, 0x19c0), | ||
156 | INTC_VECT(AP_ARM_DMASIRQ, 0x19e0), | ||
157 | INTC_VECT(MFIS2, 0x1a00), | ||
158 | INTC_VECT(CPORTR2S, 0x1a20), | ||
159 | INTC_VECT(CMT14, 0x1a40), INTC_VECT(CMT15, 0x1a60), | ||
160 | INTC_VECT(SCIFA6, 0x1a80), | ||
161 | }; | ||
162 | |||
163 | static struct intc_group intca_groups[] __initdata = { | ||
164 | INTC_GROUP(DMAC_1, DMAC_1_DEI0, | ||
165 | DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3), | ||
166 | INTC_GROUP(DMAC_2, DMAC_2_DEI4, | ||
167 | DMAC_2_DEI5, DMAC_2_DADERR), | ||
168 | INTC_GROUP(DMAC2_1, DMAC2_1_DEI0, | ||
169 | DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3), | ||
170 | INTC_GROUP(DMAC2_2, DMAC2_2_DEI4, | ||
171 | DMAC2_2_DEI5, DMAC2_2_DADERR), | ||
172 | INTC_GROUP(DMAC3_1, DMAC3_1_DEI0, | ||
173 | DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3), | ||
174 | INTC_GROUP(DMAC3_2, DMAC3_2_DEI4, | ||
175 | DMAC3_2_DEI5, DMAC3_2_DADERR), | ||
176 | INTC_GROUP(AP_ARM1, AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMTX), | ||
177 | INTC_GROUP(USBHS, USBHS_USHI0, USBHS_USHI1), | ||
178 | INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1), | ||
179 | INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI, | ||
180 | FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), | ||
181 | INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1), | ||
182 | INTC_GROUP(SHWYSTAT, SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM), | ||
183 | INTC_GROUP(ICUSB, ICUSB_ICUSB0, ICUSB_ICUSB1), | ||
184 | INTC_GROUP(ICUDMC, ICUDMC_ICUDMC1, ICUDMC_ICUDMC2), | ||
185 | }; | ||
186 | |||
187 | static struct intc_mask_reg intca_mask_registers[] __initdata = { | ||
188 | { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */ | ||
189 | { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0, | ||
190 | AP_ARM_IRQPMU, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } }, | ||
191 | { 0xe6940084, 0xe69400c4, 8, /* IMR1A / IMCR1A */ | ||
192 | { _2DG, CRYPT_STD, DIRC, 0, | ||
193 | DMAC_1_DEI3, DMAC_1_DEI2, DMAC_1_DEI1, DMAC_1_DEI0 } }, | ||
194 | { 0xe6940088, 0xe69400c8, 8, /* IMR2A / IMCR2A */ | ||
195 | { PINTCA_PINT1, PINTCA_PINT2, 0, 0, | ||
196 | BBIF1, BBIF2, MFI_MFIS, MFI_MFIM } }, | ||
197 | { 0xe694008c, 0xe69400cc, 8, /* IMR3A / IMCR3A */ | ||
198 | { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0, | ||
199 | DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } }, | ||
200 | { 0xe6940090, 0xe69400d0, 8, /* IMR4A / IMCR4A */ | ||
201 | { DDM, 0, 0, 0, | ||
202 | 0, 0, 0, 0 } }, | ||
203 | { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */ | ||
204 | { KEYSC_KEY, DMAC_2_DADERR, DMAC_2_DEI5, DMAC_2_DEI4, | ||
205 | SCIFA3, SCIFA2, SCIFA1, SCIFA0 } }, | ||
206 | { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */ | ||
207 | { SCIFB, SCIFA5, SCIFA4, MSIOF1, | ||
208 | 0, 0, MSIOF2, 0 } }, | ||
209 | { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */ | ||
210 | { DISABLED, ENABLED, ENABLED, ENABLED, | ||
211 | FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, | ||
212 | { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */ | ||
213 | { DISABLED, ENABLED, ENABLED, ENABLED, | ||
214 | TTI20, USBDMAC_USHDMI, 0, MSUG } }, | ||
215 | { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */ | ||
216 | { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10, | ||
217 | CMT2, USBHS_USHI1, USBHS_USHI0, _3DG_SGX540 } }, | ||
218 | { 0xe69400a8, 0xe69400e8, 8, /* IMR10A / IMCR10A */ | ||
219 | { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4, | ||
220 | 0, 0, 0, 0 } }, | ||
221 | { 0xe69400ac, 0xe69400ec, 8, /* IMR11A / IMCR11A */ | ||
222 | { IIC1_DTEI1, IIC1_WAITI1, IIC1_TACKI1, IIC1_ALI1, | ||
223 | LCRC, MSU_MSU2, IRREM, MSU_MSU } }, | ||
224 | { 0xe69400b0, 0xe69400f0, 8, /* IMR12A / IMCR12A */ | ||
225 | { 0, 0, TPU0, TPU1, | ||
226 | TPU2, TPU3, TPU4, 0 } }, | ||
227 | { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */ | ||
228 | { 0, 0, 0, 0, | ||
229 | MISTY, CMT3, RWDT1, RWDT0 } }, | ||
230 | { 0xe6950080, 0xe69500c0, 8, /* IMR0A3 / IMCR0A3 */ | ||
231 | { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0, | ||
232 | 0, 0, 0, 0 } }, | ||
233 | { 0xe6950090, 0xe69500d0, 8, /* IMR4A3 / IMCR4A3 */ | ||
234 | { ICUSB_ICUSB0, ICUSB_ICUSB1, 0, 0, | ||
235 | ICUDMC_ICUDMC1, ICUDMC_ICUDMC2, 0, 0 } }, | ||
236 | { 0xe6950094, 0xe69500d4, 8, /* IMR5A3 / IMCR5A3 */ | ||
237 | { SPU2_SPU0, SPU2_SPU1, FSI, FMSI, | ||
238 | SCUV, 0, 0, 0 } }, | ||
239 | { 0xe6950098, 0xe69500d8, 8, /* IMR6A3 / IMCR6A3 */ | ||
240 | { IPMMU_IPMMUB, 0, 0, 0, | ||
241 | AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ, | ||
242 | AP_ARM_DMAIRQ, AP_ARM_DMASIRQ } }, | ||
243 | { 0xe695009c, 0xe69500dc, 8, /* IMR7A3 / IMCR7A3 */ | ||
244 | { MFIS2, CPORTR2S, CMT14, CMT15, | ||
245 | SCIFA6, 0, 0, 0 } }, | ||
246 | }; | ||
247 | |||
248 | static struct intc_prio_reg intca_prio_registers[] __initdata = { | ||
249 | { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, LCRC } }, | ||
250 | { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } }, | ||
251 | { 0xe6940008, 0, 16, 4, /* IPRCA */ { _2DG, CRYPT_STD, | ||
252 | CMT1_CMT11, AP_ARM1 } }, | ||
253 | { 0xe694000c, 0, 16, 4, /* IPRDA */ { PINTCA_PINT1, PINTCA_PINT2, | ||
254 | CMT1_CMT12, TPU4 } }, | ||
255 | { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC_1, MFI_MFIS, | ||
256 | MFI_MFIM, USBHS } }, | ||
257 | { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC_KEY, DMAC_2, | ||
258 | _3DG_SGX540, CMT1_CMT10 } }, | ||
259 | { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1, | ||
260 | SCIFA2, SCIFA3 } }, | ||
261 | { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBDMAC_USHDMI, | ||
262 | FLCTL, SDHI0 } }, | ||
263 | { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, MSU_MSU, IIC1 } }, | ||
264 | { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2, MSUG, TTI20 } }, | ||
265 | { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_CMT13, IRREM, SDHI1 } }, | ||
266 | { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, TPU1, TPU2, TPU3 } }, | ||
267 | { 0xe6940030, 0, 16, 4, /* IPRMA */ { MISTY, CMT3, RWDT1, RWDT0 } }, | ||
268 | { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, DDM } }, | ||
269 | { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, 0 } }, | ||
270 | { 0xe6950000, 0, 16, 4, /* IPRAA3 */ { SHWYSTAT, 0, 0, 0 } }, | ||
271 | { 0xe6950020, 0, 16, 4, /* IPRIA3 */ { ICUSB, 0, 0, 0 } }, | ||
272 | { 0xe6950024, 0, 16, 4, /* IPRJA3 */ { ICUDMC, 0, 0, 0 } }, | ||
273 | { 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } }, | ||
274 | { 0xe695002c, 0, 16, 4, /* IPRLA3 */ { SCUV, 0, 0, 0 } }, | ||
275 | { 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU_IPMMUB, 0, 0, 0 } }, | ||
276 | { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } }, | ||
277 | { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S, | ||
278 | CMT14, CMT15 } }, | ||
279 | { 0xe694003c, 0, 16, 4, /* IPRPA3 */ { SCIFA6, 0, 0, 0 } }, | ||
280 | }; | ||
281 | |||
282 | static struct intc_desc intca_desc __initdata = { | ||
283 | .name = "sh7377-intca", | ||
284 | .force_enable = ENABLED, | ||
285 | .force_disable = DISABLED, | ||
286 | .hw = INTC_HW_DESC(intca_vectors, intca_groups, | ||
287 | intca_mask_registers, intca_prio_registers, | ||
288 | NULL, NULL), | ||
289 | }; | ||
290 | |||
291 | INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000, | ||
292 | INTC_VECT, "sh7377-intca-irq-pins"); | ||
293 | |||
294 | /* this macro ignore entry which is also in INTCA */ | ||
295 | #define __IGNORE(a...) | ||
296 | #define __IGNORE0(a...) 0 | ||
297 | |||
298 | enum { | ||
299 | UNUSED_INTCS = 0, | ||
300 | |||
301 | INTCS, | ||
302 | |||
303 | /* interrupt sources INTCS */ | ||
304 | VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3, | ||
305 | RTDMAC1_1_DEI0, RTDMAC1_1_DEI1, RTDMAC1_1_DEI2, RTDMAC1_1_DEI3, | ||
306 | CEU, | ||
307 | BEU_BEU0, BEU_BEU1, BEU_BEU2, | ||
308 | __IGNORE(MFI) | ||
309 | __IGNORE(BBIF2) | ||
310 | VPU, | ||
311 | TSIF1, | ||
312 | __IGNORE(SGX540) | ||
313 | _2DDMAC, | ||
314 | IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2, | ||
315 | IPMMU_IPMMUR, IPMMU_IPMMUR2, | ||
316 | RTDMAC1_2_DEI4, RTDMAC1_2_DEI5, RTDMAC1_2_DADERR, | ||
317 | __IGNORE(KEYSC) | ||
318 | __IGNORE(TTI20) | ||
319 | __IGNORE(MSIOF) | ||
320 | IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0, | ||
321 | TMU_TUNI0, TMU_TUNI1, TMU_TUNI2, | ||
322 | CMT0, | ||
323 | TSIF0, | ||
324 | __IGNORE(CMT2) | ||
325 | LMB, | ||
326 | __IGNORE(MSUG) | ||
327 | __IGNORE(MSU_MSU, MSU_MSU2) | ||
328 | __IGNORE(CTI) | ||
329 | MVI3, | ||
330 | __IGNORE(RWDT0) | ||
331 | __IGNORE(RWDT1) | ||
332 | ICB, | ||
333 | PEP, | ||
334 | ASA, | ||
335 | __IGNORE(_2DG) | ||
336 | HQE, | ||
337 | JPU, | ||
338 | LCDC0, | ||
339 | __IGNORE(LCRC) | ||
340 | RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3, | ||
341 | RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR, | ||
342 | FRC, | ||
343 | LCDC1, | ||
344 | CSIRX, | ||
345 | DSITX_DSITX0, DSITX_DSITX1, | ||
346 | __IGNORE(SPU2_SPU0, SPU2_SPU1) | ||
347 | __IGNORE(FSI) | ||
348 | __IGNORE(FMSI) | ||
349 | __IGNORE(SCUV) | ||
350 | TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12, | ||
351 | TSIF2, | ||
352 | CMT4, | ||
353 | __IGNORE(MFIS2) | ||
354 | CPORTS2R, | ||
355 | |||
356 | /* interrupt groups INTCS */ | ||
357 | RTDMAC1_1, RTDMAC1_2, VEU, BEU, IIC0, __IGNORE(MSU) IPMMU, | ||
358 | IIC2, RTDMAC2_1, RTDMAC2_2, DSITX, __IGNORE(SPU2) TMU1, | ||
359 | }; | ||
360 | |||
361 | #define INTCS_INTVECT 0x0F80 | ||
362 | static struct intc_vect intcs_vectors[] __initdata = { | ||
363 | INTCS_VECT(VEU_VEU0, 0x0700), INTCS_VECT(VEU_VEU1, 0x0720), | ||
364 | INTCS_VECT(VEU_VEU2, 0x0740), INTCS_VECT(VEU_VEU3, 0x0760), | ||
365 | INTCS_VECT(RTDMAC1_1_DEI0, 0x0800), INTCS_VECT(RTDMAC1_1_DEI1, 0x0820), | ||
366 | INTCS_VECT(RTDMAC1_1_DEI2, 0x0840), INTCS_VECT(RTDMAC1_1_DEI3, 0x0860), | ||
367 | INTCS_VECT(CEU, 0x0880), | ||
368 | INTCS_VECT(BEU_BEU0, 0x08A0), | ||
369 | INTCS_VECT(BEU_BEU1, 0x08C0), | ||
370 | INTCS_VECT(BEU_BEU2, 0x08E0), | ||
371 | __IGNORE(INTCS_VECT(MFI, 0x0900)) | ||
372 | __IGNORE(INTCS_VECT(BBIF2, 0x0960)) | ||
373 | INTCS_VECT(VPU, 0x0980), | ||
374 | INTCS_VECT(TSIF1, 0x09A0), | ||
375 | __IGNORE(INTCS_VECT(SGX540, 0x09E0)) | ||
376 | INTCS_VECT(_2DDMAC, 0x0A00), | ||
377 | INTCS_VECT(IIC2_ALI2, 0x0A80), INTCS_VECT(IIC2_TACKI2, 0x0AA0), | ||
378 | INTCS_VECT(IIC2_WAITI2, 0x0AC0), INTCS_VECT(IIC2_DTEI2, 0x0AE0), | ||
379 | INTCS_VECT(IPMMU_IPMMUR, 0x0B00), INTCS_VECT(IPMMU_IPMMUR2, 0x0B20), | ||
380 | INTCS_VECT(RTDMAC1_2_DEI4, 0x0B80), | ||
381 | INTCS_VECT(RTDMAC1_2_DEI5, 0x0BA0), | ||
382 | INTCS_VECT(RTDMAC1_2_DADERR, 0x0BC0), | ||
383 | __IGNORE(INTCS_VECT(KEYSC 0x0BE0)) | ||
384 | __IGNORE(INTCS_VECT(TTI20, 0x0C80)) | ||
385 | __IGNORE(INTCS_VECT(MSIOF, 0x0D20)) | ||
386 | INTCS_VECT(IIC0_ALI0, 0x0E00), INTCS_VECT(IIC0_TACKI0, 0x0E20), | ||
387 | INTCS_VECT(IIC0_WAITI0, 0x0E40), INTCS_VECT(IIC0_DTEI0, 0x0E60), | ||
388 | INTCS_VECT(TMU_TUNI0, 0x0E80), | ||
389 | INTCS_VECT(TMU_TUNI1, 0x0EA0), | ||
390 | INTCS_VECT(TMU_TUNI2, 0x0EC0), | ||
391 | INTCS_VECT(CMT0, 0x0F00), | ||
392 | INTCS_VECT(TSIF0, 0x0F20), | ||
393 | __IGNORE(INTCS_VECT(CMT2, 0x0F40)) | ||
394 | INTCS_VECT(LMB, 0x0F60), | ||
395 | __IGNORE(INTCS_VECT(MSUG, 0x0F80)) | ||
396 | __IGNORE(INTCS_VECT(MSU_MSU, 0x0FA0)) | ||
397 | __IGNORE(INTCS_VECT(MSU_MSU2, 0x0FC0)) | ||
398 | __IGNORE(INTCS_VECT(CTI, 0x0400)) | ||
399 | INTCS_VECT(MVI3, 0x0420), | ||
400 | __IGNORE(INTCS_VECT(RWDT0, 0x0440)) | ||
401 | __IGNORE(INTCS_VECT(RWDT1, 0x0460)) | ||
402 | INTCS_VECT(ICB, 0x0480), | ||
403 | INTCS_VECT(PEP, 0x04A0), | ||
404 | INTCS_VECT(ASA, 0x04C0), | ||
405 | __IGNORE(INTCS_VECT(_2DG, 0x04E0)) | ||
406 | INTCS_VECT(HQE, 0x0540), | ||
407 | INTCS_VECT(JPU, 0x0560), | ||
408 | INTCS_VECT(LCDC0, 0x0580), | ||
409 | __IGNORE(INTCS_VECT(LCRC, 0x05A0)) | ||
410 | INTCS_VECT(RTDMAC2_1_DEI0, 0x1300), INTCS_VECT(RTDMAC2_1_DEI1, 0x1320), | ||
411 | INTCS_VECT(RTDMAC2_1_DEI2, 0x1340), INTCS_VECT(RTDMAC2_1_DEI3, 0x1360), | ||
412 | INTCS_VECT(RTDMAC2_2_DEI4, 0x1380), INTCS_VECT(RTDMAC2_2_DEI5, 0x13A0), | ||
413 | INTCS_VECT(RTDMAC2_2_DADERR, 0x13C0), | ||
414 | INTCS_VECT(FRC, 0x1700), | ||
415 | INTCS_VECT(LCDC1, 0x1780), | ||
416 | INTCS_VECT(CSIRX, 0x17A0), | ||
417 | INTCS_VECT(DSITX_DSITX0, 0x17C0), INTCS_VECT(DSITX_DSITX1, 0x17E0), | ||
418 | __IGNORE(INTCS_VECT(SPU2_SPU0, 0x1800)) | ||
419 | __IGNORE(INTCS_VECT(SPU2_SPU1, 0x1820)) | ||
420 | __IGNORE(INTCS_VECT(FSI, 0x1840)) | ||
421 | __IGNORE(INTCS_VECT(FMSI, 0x1860)) | ||
422 | __IGNORE(INTCS_VECT(SCUV, 0x1880)) | ||
423 | INTCS_VECT(TMU1_TUNI10, 0x1900), INTCS_VECT(TMU1_TUNI11, 0x1920), | ||
424 | INTCS_VECT(TMU1_TUNI12, 0x1940), | ||
425 | INTCS_VECT(TSIF2, 0x1960), | ||
426 | INTCS_VECT(CMT4, 0x1980), | ||
427 | __IGNORE(INTCS_VECT(MFIS2, 0x1A00)) | ||
428 | INTCS_VECT(CPORTS2R, 0x1A20), | ||
429 | |||
430 | INTC_VECT(INTCS, INTCS_INTVECT), | ||
431 | }; | ||
432 | |||
433 | static struct intc_group intcs_groups[] __initdata = { | ||
434 | INTC_GROUP(RTDMAC1_1, | ||
435 | RTDMAC1_1_DEI0, RTDMAC1_1_DEI1, | ||
436 | RTDMAC1_1_DEI2, RTDMAC1_1_DEI3), | ||
437 | INTC_GROUP(RTDMAC1_2, | ||
438 | RTDMAC1_2_DEI4, RTDMAC1_2_DEI5, RTDMAC1_2_DADERR), | ||
439 | INTC_GROUP(VEU, VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3), | ||
440 | INTC_GROUP(BEU, BEU_BEU0, BEU_BEU1, BEU_BEU2), | ||
441 | INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0), | ||
442 | __IGNORE(INTC_GROUP(MSU, MSU_MSU, MSU_MSU2)) | ||
443 | INTC_GROUP(IPMMU, IPMMU_IPMMUR, IPMMU_IPMMUR2), | ||
444 | INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2), | ||
445 | INTC_GROUP(RTDMAC2_1, | ||
446 | RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, | ||
447 | RTDMAC2_1_DEI2, RTDMAC2_1_DEI3), | ||
448 | INTC_GROUP(RTDMAC2_2, RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR), | ||
449 | INTC_GROUP(DSITX, DSITX_DSITX0, DSITX_DSITX1), | ||
450 | __IGNORE(INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1)) | ||
451 | INTC_GROUP(TMU1, TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12), | ||
452 | }; | ||
453 | |||
454 | static struct intc_mask_reg intcs_mask_registers[] __initdata = { | ||
455 | { 0xE6940184, 0xE69401C4, 8, /* IMR1AS / IMCR1AS */ | ||
456 | { BEU_BEU2, BEU_BEU1, BEU_BEU0, CEU, | ||
457 | VEU_VEU3, VEU_VEU2, VEU_VEU1, VEU_VEU0 } }, | ||
458 | { 0xE6940188, 0xE69401C8, 8, /* IMR2AS / IMCR2AS */ | ||
459 | { 0, 0, 0, VPU, | ||
460 | __IGNORE0(BBIF2), 0, 0, __IGNORE0(MFI) } }, | ||
461 | { 0xE694018C, 0xE69401CC, 8, /* IMR3AS / IMCR3AS */ | ||
462 | { 0, 0, 0, _2DDMAC, | ||
463 | __IGNORE0(_2DG), ASA, PEP, ICB } }, | ||
464 | { 0xE6940190, 0xE69401D0, 8, /* IMR4AS / IMCR4AS */ | ||
465 | { 0, 0, MVI3, __IGNORE0(CTI), | ||
466 | JPU, HQE, __IGNORE0(LCRC), LCDC0 } }, | ||
467 | { 0xE6940194, 0xE69401D4, 8, /* IMR5AS / IMCR5AS */ | ||
468 | { __IGNORE0(KEYSC), RTDMAC1_2_DADERR, RTDMAC1_2_DEI5, RTDMAC1_2_DEI4, | ||
469 | RTDMAC1_1_DEI3, RTDMAC1_1_DEI2, RTDMAC1_1_DEI1, RTDMAC1_1_DEI0 } }, | ||
470 | __IGNORE({ 0xE6940198, 0xE69401D8, 8, /* IMR6AS / IMCR6AS */ | ||
471 | { 0, 0, MSIOF, 0, | ||
472 | SGX540, 0, TTI20, 0 } }) | ||
473 | { 0xE694019C, 0xE69401DC, 8, /* IMR7AS / IMCR7AS */ | ||
474 | { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0, | ||
475 | 0, 0, 0, 0 } }, | ||
476 | __IGNORE({ 0xE69401A0, 0xE69401E0, 8, /* IMR8AS / IMCR8AS */ | ||
477 | { 0, 0, 0, 0, | ||
478 | 0, MSU_MSU, MSU_MSU2, MSUG } }) | ||
479 | { 0xE69401A4, 0xE69401E4, 8, /* IMR9AS / IMCR9AS */ | ||
480 | { __IGNORE0(RWDT1), __IGNORE0(RWDT0), __IGNORE0(CMT2), CMT0, | ||
481 | IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } }, | ||
482 | { 0xE69401A8, 0xE69401E8, 8, /* IMR10AS / IMCR10AS */ | ||
483 | { 0, 0, IPMMU_IPMMUR, IPMMU_IPMMUR2, | ||
484 | 0, 0, 0, 0 } }, | ||
485 | { 0xE69401AC, 0xE69401EC, 8, /* IMR11AS / IMCR11AS */ | ||
486 | { IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0, | ||
487 | 0, TSIF1, LMB, TSIF0 } }, | ||
488 | { 0xE6950180, 0xE69501C0, 8, /* IMR0AS3 / IMCR0AS3 */ | ||
489 | { RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3, | ||
490 | RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR, 0 } }, | ||
491 | { 0xE6950190, 0xE69501D0, 8, /* IMR4AS3 / IMCR4AS3 */ | ||
492 | { FRC, 0, 0, 0, | ||
493 | LCDC1, CSIRX, DSITX_DSITX0, DSITX_DSITX1 } }, | ||
494 | __IGNORE({ 0xE6950194, 0xE69501D4, 8, /* IMR5AS3 / IMCR5AS3 */ | ||
495 | {SPU2_SPU0, SPU2_SPU1, FSI, FMSI, | ||
496 | SCUV, 0, 0, 0 } }) | ||
497 | { 0xE6950198, 0xE69501D8, 8, /* IMR6AS3 / IMCR6AS3 */ | ||
498 | { TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12, TSIF2, | ||
499 | CMT4, 0, 0, 0 } }, | ||
500 | { 0xE695019C, 0xE69501DC, 8, /* IMR7AS3 / IMCR7AS3 */ | ||
501 | { __IGNORE0(MFIS2), CPORTS2R, 0, 0, | ||
502 | 0, 0, 0, 0 } }, | ||
503 | { 0xFFD20104, 0, 16, /* INTAMASK */ | ||
504 | { 0, 0, 0, 0, 0, 0, 0, 0, | ||
505 | 0, 0, 0, 0, 0, 0, 0, INTCS } } | ||
506 | }; | ||
507 | |||
508 | static struct intc_prio_reg intcs_prio_registers[] __initdata = { | ||
509 | /* IPRAS */ | ||
510 | { 0xFFD20000, 0, 16, 4, { __IGNORE0(CTI), MVI3, _2DDMAC, ICB } }, | ||
511 | /* IPRBS */ | ||
512 | { 0xFFD20004, 0, 16, 4, { JPU, LCDC0, 0, __IGNORE0(LCRC) } }, | ||
513 | /* IPRCS */ | ||
514 | __IGNORE({ 0xFFD20008, 0, 16, 4, { BBIF2, 0, 0, 0 } }) | ||
515 | /* IPRES */ | ||
516 | { 0xFFD20010, 0, 16, 4, { RTDMAC1_1, CEU, __IGNORE0(MFI), VPU } }, | ||
517 | /* IPRFS */ | ||
518 | { 0xFFD20014, 0, 16, 4, | ||
519 | { __IGNORE0(KEYSC), RTDMAC1_2, __IGNORE0(CMT2), CMT0 } }, | ||
520 | /* IPRGS */ | ||
521 | { 0xFFD20018, 0, 16, 4, { TMU_TUNI0, TMU_TUNI1, TMU_TUNI2, TSIF1 } }, | ||
522 | /* IPRHS */ | ||
523 | { 0xFFD2001C, 0, 16, 4, { __IGNORE0(TTI20), 0, VEU, BEU } }, | ||
524 | /* IPRIS */ | ||
525 | { 0xFFD20020, 0, 16, 4, { 0, __IGNORE0(MSIOF), TSIF0, IIC0 } }, | ||
526 | /* IPRJS */ | ||
527 | __IGNORE({ 0xFFD20024, 0, 16, 4, { 0, SGX540, MSUG, MSU } }) | ||
528 | /* IPRKS */ | ||
529 | { 0xFFD20028, 0, 16, 4, { __IGNORE0(_2DG), ASA, LMB, PEP } }, | ||
530 | /* IPRLS */ | ||
531 | { 0xFFD2002C, 0, 16, 4, { IPMMU, 0, 0, HQE } }, | ||
532 | /* IPRMS */ | ||
533 | { 0xFFD20030, 0, 16, 4, | ||
534 | { IIC2, 0, __IGNORE0(RWDT1), __IGNORE0(RWDT0) } }, | ||
535 | /* IPRAS3 */ | ||
536 | { 0xFFD50000, 0, 16, 4, { RTDMAC2_1, 0, 0, 0 } }, | ||
537 | /* IPRBS3 */ | ||
538 | { 0xFFD50004, 0, 16, 4, { RTDMAC2_2, 0, 0, 0 } }, | ||
539 | /* IPRIS3 */ | ||
540 | { 0xFFD50020, 0, 16, 4, { FRC, 0, 0, 0 } }, | ||
541 | /* IPRJS3 */ | ||
542 | { 0xFFD50024, 0, 16, 4, { LCDC1, CSIRX, DSITX, 0 } }, | ||
543 | /* IPRKS3 */ | ||
544 | __IGNORE({ 0xFFD50028, 0, 16, 4, { SPU2, 0, FSI, FMSI } }) | ||
545 | /* IPRLS3 */ | ||
546 | __IGNORE({ 0xFFD5002C, 0, 16, 4, { SCUV, 0, 0, 0 } }) | ||
547 | /* IPRMS3 */ | ||
548 | { 0xFFD50030, 0, 16, 4, { TMU1, 0, 0, TSIF2 } }, | ||
549 | /* IPRNS3 */ | ||
550 | { 0xFFD50034, 0, 16, 4, { CMT4, 0, 0, 0 } }, | ||
551 | /* IPROS3 */ | ||
552 | { 0xFFD50038, 0, 16, 4, { __IGNORE0(MFIS2), CPORTS2R, 0, 0 } }, | ||
553 | }; | ||
554 | |||
555 | static struct resource intcs_resources[] __initdata = { | ||
556 | [0] = { | ||
557 | .start = 0xffd20000, | ||
558 | .end = 0xffd500ff, | ||
559 | .flags = IORESOURCE_MEM, | ||
560 | } | ||
561 | }; | ||
562 | |||
563 | static struct intc_desc intcs_desc __initdata = { | ||
564 | .name = "sh7377-intcs", | ||
565 | .resource = intcs_resources, | ||
566 | .num_resources = ARRAY_SIZE(intcs_resources), | ||
567 | .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, | ||
568 | intcs_mask_registers, intcs_prio_registers, | ||
569 | NULL, NULL), | ||
570 | }; | ||
571 | |||
572 | static void intcs_demux(unsigned int irq, struct irq_desc *desc) | ||
573 | { | ||
574 | void __iomem *reg = (void *)irq_get_handler_data(irq); | ||
575 | unsigned int evtcodeas = ioread32(reg); | ||
576 | |||
577 | generic_handle_irq(intcs_evt2irq(evtcodeas)); | ||
578 | } | ||
579 | |||
580 | #define INTEVTSA 0xFFD20100 | ||
581 | void __init sh7377_init_irq(void) | ||
582 | { | ||
583 | void __iomem *intevtsa = ioremap_nocache(INTEVTSA, PAGE_SIZE); | ||
584 | |||
585 | register_intc_controller(&intca_desc); | ||
586 | register_intc_controller(&intca_irq_pins_desc); | ||
587 | register_intc_controller(&intcs_desc); | ||
588 | |||
589 | /* demux using INTEVTSA */ | ||
590 | irq_set_handler_data(evt2irq(INTCS_INTVECT), (void *)intevtsa); | ||
591 | irq_set_chained_handler(evt2irq(INTCS_INTVECT), intcs_demux); | ||
592 | } | ||
diff --git a/arch/arm/mach-shmobile/pfc-sh7377.c b/arch/arm/mach-shmobile/pfc-sh7377.c deleted file mode 100644 index f3117f67fa2..00000000000 --- a/arch/arm/mach-shmobile/pfc-sh7377.c +++ /dev/null | |||
@@ -1,1688 +0,0 @@ | |||
1 | /* | ||
2 | * sh7377 processor support - PFC hardware block | ||
3 | * | ||
4 | * Copyright (C) 2010 NISHIMOTO Hiroki | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or | ||
7 | * modify it under the terms of the GNU General Public License as | ||
8 | * published by the Free Software Foundation; version 2 of the | ||
9 | * License. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License | ||
17 | * along with this program; if not, write to the Free Software | ||
18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
19 | */ | ||
20 | #include <linux/init.h> | ||
21 | #include <linux/kernel.h> | ||
22 | #include <linux/sh_pfc.h> | ||
23 | #include <mach/sh7377.h> | ||
24 | |||
25 | #define CPU_ALL_PORT(fn, pfx, sfx) \ | ||
26 | PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \ | ||
27 | PORT_10(fn, pfx##10, sfx), \ | ||
28 | PORT_1(fn, pfx##110, sfx), PORT_1(fn, pfx##111, sfx), \ | ||
29 | PORT_1(fn, pfx##112, sfx), PORT_1(fn, pfx##113, sfx), \ | ||
30 | PORT_1(fn, pfx##114, sfx), PORT_1(fn, pfx##115, sfx), \ | ||
31 | PORT_1(fn, pfx##116, sfx), PORT_1(fn, pfx##117, sfx), \ | ||
32 | PORT_1(fn, pfx##118, sfx), \ | ||
33 | PORT_1(fn, pfx##128, sfx), PORT_1(fn, pfx##129, sfx), \ | ||
34 | PORT_10(fn, pfx##13, sfx), PORT_10(fn, pfx##14, sfx), \ | ||
35 | PORT_10(fn, pfx##15, sfx), \ | ||
36 | PORT_1(fn, pfx##160, sfx), PORT_1(fn, pfx##161, sfx), \ | ||
37 | PORT_1(fn, pfx##162, sfx), PORT_1(fn, pfx##163, sfx), \ | ||
38 | PORT_1(fn, pfx##164, sfx), \ | ||
39 | PORT_1(fn, pfx##192, sfx), PORT_1(fn, pfx##193, sfx), \ | ||
40 | PORT_1(fn, pfx##194, sfx), PORT_1(fn, pfx##195, sfx), \ | ||
41 | PORT_1(fn, pfx##196, sfx), PORT_1(fn, pfx##197, sfx), \ | ||
42 | PORT_1(fn, pfx##198, sfx), PORT_1(fn, pfx##199, sfx), \ | ||
43 | PORT_10(fn, pfx##20, sfx), PORT_10(fn, pfx##21, sfx), \ | ||
44 | PORT_10(fn, pfx##22, sfx), PORT_10(fn, pfx##23, sfx), \ | ||
45 | PORT_10(fn, pfx##24, sfx), PORT_10(fn, pfx##25, sfx), \ | ||
46 | PORT_1(fn, pfx##260, sfx), PORT_1(fn, pfx##261, sfx), \ | ||
47 | PORT_1(fn, pfx##262, sfx), PORT_1(fn, pfx##263, sfx), \ | ||
48 | PORT_1(fn, pfx##264, sfx) | ||
49 | |||
50 | enum { | ||
51 | PINMUX_RESERVED = 0, | ||
52 | |||
53 | PINMUX_DATA_BEGIN, | ||
54 | PORT_ALL(DATA), /* PORT0_DATA -> PORT264_DATA */ | ||
55 | PINMUX_DATA_END, | ||
56 | |||
57 | PINMUX_INPUT_BEGIN, | ||
58 | PORT_ALL(IN), /* PORT0_IN -> PORT264_IN */ | ||
59 | PINMUX_INPUT_END, | ||
60 | |||
61 | PINMUX_INPUT_PULLUP_BEGIN, | ||
62 | PORT_ALL(IN_PU), /* PORT0_IN_PU -> PORT264_IN_PU */ | ||
63 | PINMUX_INPUT_PULLUP_END, | ||
64 | |||
65 | PINMUX_INPUT_PULLDOWN_BEGIN, | ||
66 | PORT_ALL(IN_PD), /* PORT0_IN_PD -> PORT264_IN_PD */ | ||
67 | PINMUX_INPUT_PULLDOWN_END, | ||
68 | |||
69 | PINMUX_OUTPUT_BEGIN, | ||
70 | PORT_ALL(OUT), /* PORT0_OUT -> PORT264_OUT */ | ||
71 | PINMUX_OUTPUT_END, | ||
72 | |||
73 | PINMUX_FUNCTION_BEGIN, | ||
74 | PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT264_FN_IN */ | ||
75 | PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT264_FN_OUT */ | ||
76 | PORT_ALL(FN0), /* PORT0_FN0 -> PORT264_FN0 */ | ||
77 | PORT_ALL(FN1), /* PORT0_FN1 -> PORT264_FN1 */ | ||
78 | PORT_ALL(FN2), /* PORT0_FN2 -> PORT264_FN2 */ | ||
79 | PORT_ALL(FN3), /* PORT0_FN3 -> PORT264_FN3 */ | ||
80 | PORT_ALL(FN4), /* PORT0_FN4 -> PORT264_FN4 */ | ||
81 | PORT_ALL(FN5), /* PORT0_FN5 -> PORT264_FN5 */ | ||
82 | PORT_ALL(FN6), /* PORT0_FN6 -> PORT264_FN6 */ | ||
83 | PORT_ALL(FN7), /* PORT0_FN7 -> PORT264_FN7 */ | ||
84 | |||
85 | MSELBCR_MSEL17_1, MSELBCR_MSEL17_0, | ||
86 | MSELBCR_MSEL16_1, MSELBCR_MSEL16_0, | ||
87 | PINMUX_FUNCTION_END, | ||
88 | |||
89 | PINMUX_MARK_BEGIN, | ||
90 | /* Special Pull-up / Pull-down Functions */ | ||
91 | PORT66_KEYIN0_PU_MARK, PORT67_KEYIN1_PU_MARK, | ||
92 | PORT68_KEYIN2_PU_MARK, PORT69_KEYIN3_PU_MARK, | ||
93 | PORT70_KEYIN4_PU_MARK, PORT71_KEYIN5_PU_MARK, | ||
94 | PORT72_KEYIN6_PU_MARK, | ||
95 | |||
96 | /* 55-1 */ | ||
97 | VBUS_0_MARK, | ||
98 | CPORT0_MARK, | ||
99 | CPORT1_MARK, | ||
100 | CPORT2_MARK, | ||
101 | CPORT3_MARK, | ||
102 | CPORT4_MARK, | ||
103 | CPORT5_MARK, | ||
104 | CPORT6_MARK, | ||
105 | CPORT7_MARK, | ||
106 | CPORT8_MARK, | ||
107 | CPORT9_MARK, | ||
108 | CPORT10_MARK, | ||
109 | CPORT11_MARK, SIN2_MARK, | ||
110 | CPORT12_MARK, XCTS2_MARK, | ||
111 | CPORT13_MARK, RFSPO4_MARK, | ||
112 | CPORT14_MARK, RFSPO5_MARK, | ||
113 | CPORT15_MARK, SCIFA0_SCK_MARK, GPS_AGC2_MARK, | ||
114 | CPORT16_MARK, SCIFA0_TXD_MARK, GPS_AGC3_MARK, | ||
115 | CPORT17_IC_OE_MARK, SOUT2_MARK, | ||
116 | CPORT18_MARK, XRTS2_MARK, PORT19_VIO_CKO2_MARK, | ||
117 | CPORT19_MPORT1_MARK, | ||
118 | CPORT20_MARK, RFSPO6_MARK, | ||
119 | CPORT21_MARK, STATUS0_MARK, | ||
120 | CPORT22_MARK, STATUS1_MARK, | ||
121 | CPORT23_MARK, STATUS2_MARK, RFSPO7_MARK, | ||
122 | B_SYNLD1_MARK, | ||
123 | B_SYNLD2_MARK, SYSENMSK_MARK, | ||
124 | XMAINPS_MARK, | ||
125 | XDIVPS_MARK, | ||
126 | XIDRST_MARK, | ||
127 | IDCLK_MARK, IC_DP_MARK, | ||
128 | IDIO_MARK, IC_DM_MARK, | ||
129 | SOUT1_MARK, SCIFA4_TXD_MARK, M02_BERDAT_MARK, | ||
130 | SIN1_MARK, SCIFA4_RXD_MARK, XWUP_MARK, | ||
131 | XRTS1_MARK, SCIFA4_RTS_MARK, M03_BERCLK_MARK, | ||
132 | XCTS1_MARK, SCIFA4_CTS_MARK, | ||
133 | PCMCLKO_MARK, | ||
134 | SYNC8KO_MARK, | ||
135 | |||
136 | /* 55-2 */ | ||
137 | DNPCM_A_MARK, | ||
138 | UPPCM_A_MARK, | ||
139 | VACK_MARK, | ||
140 | XTALB1L_MARK, | ||
141 | GPS_AGC1_MARK, SCIFA0_RTS_MARK, | ||
142 | GPS_AGC4_MARK, SCIFA0_RXD_MARK, | ||
143 | GPS_PWRDOWN_MARK, SCIFA0_CTS_MARK, | ||
144 | GPS_IM_MARK, | ||
145 | GPS_IS_MARK, | ||
146 | GPS_QM_MARK, | ||
147 | GPS_QS_MARK, | ||
148 | FMSOCK_MARK, PORT49_IRDA_OUT_MARK, PORT49_IROUT_MARK, | ||
149 | FMSOOLR_MARK, BBIF2_TSYNC2_MARK, TPU2TO2_MARK, IPORT3_MARK, | ||
150 | FMSIOLR_MARK, | ||
151 | FMSOOBT_MARK, BBIF2_TSCK2_MARK, TPU2TO3_MARK, OPORT1_MARK, | ||
152 | FMSIOBT_MARK, | ||
153 | FMSOSLD_MARK, BBIF2_TXD2_MARK, OPORT2_MARK, | ||
154 | FMSOILR_MARK, PORT53_IRDA_IN_MARK, TPU3TO3_MARK, OPORT3_MARK, | ||
155 | FMSIILR_MARK, | ||
156 | FMSOIBT_MARK, PORT54_IRDA_FIRSEL_MARK, TPU3TO2_MARK, FMSIIBT_MARK, | ||
157 | FMSISLD_MARK, MFG0_OUT1_MARK, TPU0TO0_MARK, | ||
158 | A0_EA0_MARK, BS_MARK, | ||
159 | A12_EA12_MARK, PORT58_VIO_CKOR_MARK, TPU4TO2_MARK, | ||
160 | A13_EA13_MARK, PORT59_IROUT_MARK, MFG0_OUT2_MARK, TPU0TO1_MARK, | ||
161 | A14_EA14_MARK, PORT60_KEYOUT5_MARK, | ||
162 | A15_EA15_MARK, PORT61_KEYOUT4_MARK, | ||
163 | A16_EA16_MARK, PORT62_KEYOUT3_MARK, MSIOF0_SS1_MARK, | ||
164 | A17_EA17_MARK, PORT63_KEYOUT2_MARK, MSIOF0_TSYNC_MARK, | ||
165 | A18_EA18_MARK, PORT64_KEYOUT1_MARK, MSIOF0_TSCK_MARK, | ||
166 | A19_EA19_MARK, PORT65_KEYOUT0_MARK, MSIOF0_TXD_MARK, | ||
167 | A20_EA20_MARK, PORT66_KEYIN0_MARK, MSIOF0_RSCK_MARK, | ||
168 | A21_EA21_MARK, PORT67_KEYIN1_MARK, MSIOF0_RSYNC_MARK, | ||
169 | A22_EA22_MARK, PORT68_KEYIN2_MARK, MSIOF0_MCK0_MARK, | ||
170 | A23_EA23_MARK, PORT69_KEYIN3_MARK, MSIOF0_MCK1_MARK, | ||
171 | A24_EA24_MARK, PORT70_KEYIN4_MARK, MSIOF0_RXD_MARK, | ||
172 | A25_EA25_MARK, PORT71_KEYIN5_MARK, MSIOF0_SS2_MARK, | ||
173 | A26_MARK, PORT72_KEYIN6_MARK, | ||
174 | D0_ED0_NAF0_MARK, | ||
175 | D1_ED1_NAF1_MARK, | ||
176 | D2_ED2_NAF2_MARK, | ||
177 | D3_ED3_NAF3_MARK, | ||
178 | D4_ED4_NAF4_MARK, | ||
179 | D5_ED5_NAF5_MARK, | ||
180 | D6_ED6_NAF6_MARK, | ||
181 | D7_ED7_NAF7_MARK, | ||
182 | D8_ED8_NAF8_MARK, | ||
183 | D9_ED9_NAF9_MARK, | ||
184 | D10_ED10_NAF10_MARK, | ||
185 | D11_ED11_NAF11_MARK, | ||
186 | D12_ED12_NAF12_MARK, | ||
187 | D13_ED13_NAF13_MARK, | ||
188 | D14_ED14_NAF14_MARK, | ||
189 | D15_ED15_NAF15_MARK, | ||
190 | CS4_MARK, | ||
191 | CS5A_MARK, FMSICK_MARK, | ||
192 | CS5B_MARK, FCE1_MARK, | ||
193 | |||
194 | /* 55-3 */ | ||
195 | CS6B_MARK, XCS2_MARK, CS6A_MARK, DACK0_MARK, | ||
196 | FCE0_MARK, | ||
197 | WAIT_MARK, DREQ0_MARK, | ||
198 | RD_XRD_MARK, | ||
199 | WE0_XWR0_FWE_MARK, | ||
200 | WE1_XWR1_MARK, | ||
201 | FRB_MARK, | ||
202 | CKO_MARK, | ||
203 | NBRSTOUT_MARK, | ||
204 | NBRST_MARK, | ||
205 | GPS_EPPSIN_MARK, | ||
206 | LATCHPULSE_MARK, | ||
207 | LTESIGNAL_MARK, | ||
208 | LEGACYSTATE_MARK, | ||
209 | TCKON_MARK, | ||
210 | VIO_VD_MARK, PORT128_KEYOUT0_MARK, IPORT0_MARK, | ||
211 | VIO_HD_MARK, PORT129_KEYOUT1_MARK, IPORT1_MARK, | ||
212 | VIO_D0_MARK, PORT130_KEYOUT2_MARK, PORT130_MSIOF2_RXD_MARK, | ||
213 | VIO_D1_MARK, PORT131_KEYOUT3_MARK, PORT131_MSIOF2_SS1_MARK, | ||
214 | VIO_D2_MARK, PORT132_KEYOUT4_MARK, PORT132_MSIOF2_SS2_MARK, | ||
215 | VIO_D3_MARK, PORT133_KEYOUT5_MARK, PORT133_MSIOF2_TSYNC_MARK, | ||
216 | VIO_D4_MARK, PORT134_KEYIN0_MARK, PORT134_MSIOF2_TXD_MARK, | ||
217 | VIO_D5_MARK, PORT135_KEYIN1_MARK, PORT135_MSIOF2_TSCK_MARK, | ||
218 | VIO_D6_MARK, PORT136_KEYIN2_MARK, | ||
219 | VIO_D7_MARK, PORT137_KEYIN3_MARK, | ||
220 | VIO_D8_MARK, M9_SLCD_A01_MARK, PORT138_FSIAOMC_MARK, | ||
221 | VIO_D9_MARK, M10_SLCD_CK1_MARK, PORT139_FSIAOLR_MARK, | ||
222 | VIO_D10_MARK, M11_SLCD_SO1_MARK, TPU0TO2_MARK, PORT140_FSIAOBT_MARK, | ||
223 | VIO_D11_MARK, M12_SLCD_CE1_MARK, TPU0TO3_MARK, PORT141_FSIAOSLD_MARK, | ||
224 | VIO_D12_MARK, M13_BSW_MARK, PORT142_FSIACK_MARK, | ||
225 | VIO_D13_MARK, M14_GSW_MARK, PORT143_FSIAILR_MARK, | ||
226 | VIO_D14_MARK, M15_RSW_MARK, PORT144_FSIAIBT_MARK, | ||
227 | VIO_D15_MARK, TPU1TO3_MARK, PORT145_FSIAISLD_MARK, | ||
228 | VIO_CLK_MARK, PORT146_KEYIN4_MARK, IPORT2_MARK, | ||
229 | VIO_FIELD_MARK, PORT147_KEYIN5_MARK, | ||
230 | VIO_CKO_MARK, PORT148_KEYIN6_MARK, | ||
231 | A27_MARK, RDWR_XWE_MARK, MFG0_IN1_MARK, | ||
232 | MFG0_IN2_MARK, | ||
233 | TS_SPSYNC3_MARK, MSIOF2_RSCK_MARK, | ||
234 | TS_SDAT3_MARK, MSIOF2_RSYNC_MARK, | ||
235 | TPU1TO2_MARK, TS_SDEN3_MARK, PORT153_MSIOF2_SS1_MARK, | ||
236 | SOUT3_MARK, SCIFA2_TXD1_MARK, MSIOF2_MCK0_MARK, | ||
237 | SIN3_MARK, SCIFA2_RXD1_MARK, MSIOF2_MCK1_MARK, | ||
238 | XRTS3_MARK, SCIFA2_RTS1_MARK, PORT156_MSIOF2_SS2_MARK, | ||
239 | XCTS3_MARK, SCIFA2_CTS1_MARK, PORT157_MSIOF2_RXD_MARK, | ||
240 | |||
241 | /* 55-4 */ | ||
242 | DINT_MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK, | ||
243 | PORT159_SCIFB_SCK_MARK, PORT159_SCIFA5_SCK_MARK, NMI_MARK, | ||
244 | PORT160_SCIFB_TXD_MARK, PORT160_SCIFA5_TXD_MARK, SOUT0_MARK, | ||
245 | PORT161_SCIFB_CTS_MARK, PORT161_SCIFA5_CTS_MARK, XCTS0_MARK, | ||
246 | MFG3_IN2_MARK, | ||
247 | PORT162_SCIFB_RXD_MARK, PORT162_SCIFA5_RXD_MARK, SIN0_MARK, | ||
248 | MFG3_IN1_MARK, | ||
249 | PORT163_SCIFB_RTS_MARK, PORT163_SCIFA5_RTS_MARK, XRTS0_MARK, | ||
250 | MFG3_OUT1_MARK, TPU3TO0_MARK, | ||
251 | LCDD0_MARK, PORT192_KEYOUT0_MARK, EXT_CKI_MARK, | ||
252 | LCDD1_MARK, PORT193_KEYOUT1_MARK, PORT193_SCIFA5_CTS_MARK, | ||
253 | BBIF2_TSYNC1_MARK, | ||
254 | LCDD2_MARK, PORT194_KEYOUT2_MARK, PORT194_SCIFA5_RTS_MARK, | ||
255 | BBIF2_TSCK1_MARK, | ||
256 | LCDD3_MARK, PORT195_KEYOUT3_MARK, PORT195_SCIFA5_RXD_MARK, | ||
257 | BBIF2_TXD1_MARK, | ||
258 | LCDD4_MARK, PORT196_KEYOUT4_MARK, PORT196_SCIFA5_TXD_MARK, | ||
259 | LCDD5_MARK, PORT197_KEYOUT5_MARK, PORT197_SCIFA5_SCK_MARK, | ||
260 | MFG2_OUT2_MARK, | ||
261 | TPU2TO1_MARK, | ||
262 | LCDD6_MARK, XWR2_MARK, | ||
263 | LCDD7_MARK, TPU4TO1_MARK, MFG4_OUT2_MARK, XWR3_MARK, | ||
264 | LCDD8_MARK, PORT200_KEYIN0_MARK, VIO_DR0_MARK, D16_MARK, ED16_MARK, | ||
265 | LCDD9_MARK, PORT201_KEYIN1_MARK, VIO_DR1_MARK, D17_MARK, ED17_MARK, | ||
266 | LCDD10_MARK, PORT202_KEYIN2_MARK, VIO_DR2_MARK, D18_MARK, ED18_MARK, | ||
267 | LCDD11_MARK, PORT203_KEYIN3_MARK, VIO_DR3_MARK, D19_MARK, ED19_MARK, | ||
268 | LCDD12_MARK, PORT204_KEYIN4_MARK, VIO_DR4_MARK, D20_MARK, ED20_MARK, | ||
269 | LCDD13_MARK, PORT205_KEYIN5_MARK, VIO_DR5_MARK, D21_MARK, ED21_MARK, | ||
270 | LCDD14_MARK, PORT206_KEYIN6_MARK, VIO_DR6_MARK, D22_MARK, ED22_MARK, | ||
271 | LCDD15_MARK, PORT207_MSIOF0L_SS1_MARK, PORT207_KEYOUT0_MARK, | ||
272 | VIO_DR7_MARK, D23_MARK, ED23_MARK, | ||
273 | LCDD16_MARK, PORT208_MSIOF0L_SS2_MARK, PORT208_KEYOUT1_MARK, | ||
274 | VIO_VDR_MARK, D24_MARK, ED24_MARK, | ||
275 | LCDD17_MARK, PORT209_KEYOUT2_MARK, VIO_HDR_MARK, D25_MARK, ED25_MARK, | ||
276 | LCDD18_MARK, DREQ2_MARK, PORT210_MSIOF0L_SS1_MARK, D26_MARK, ED26_MARK, | ||
277 | LCDD19_MARK, PORT211_MSIOF0L_SS2_MARK, D27_MARK, ED27_MARK, | ||
278 | LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK, D28_MARK, ED28_MARK, | ||
279 | LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK, D29_MARK, ED29_MARK, | ||
280 | LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_RSCK_MARK, D30_MARK, ED30_MARK, | ||
281 | LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_RSYNC_MARK, D31_MARK, ED31_MARK, | ||
282 | LCDDCK_MARK, LCDWR_MARK, PORT216_KEYOUT3_MARK, VIO_CLKR_MARK, | ||
283 | LCDRD_MARK, DACK2_MARK, MSIOF0L_TSYNC_MARK, | ||
284 | LCDHSYN_MARK, LCDCS_MARK, LCDCS2_MARK, DACK3_MARK, | ||
285 | PORT218_VIO_CKOR_MARK, PORT218_KEYOUT4_MARK, | ||
286 | LCDDISP_MARK, LCDRS_MARK, DREQ3_MARK, MSIOF0L_TSCK_MARK, | ||
287 | LCDVSYN_MARK, LCDVSYN2_MARK, PORT220_KEYOUT5_MARK, | ||
288 | LCDLCLK_MARK, DREQ1_MARK, PWEN_MARK, MSIOF0L_RXD_MARK, | ||
289 | LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, OVCN_MARK, MSIOF0L_TXD_MARK, | ||
290 | SCIFA1_TXD_MARK, OVCN2_MARK, | ||
291 | EXTLP_MARK, SCIFA1_SCK_MARK, USBTERM_MARK, PORT226_VIO_CKO2_MARK, | ||
292 | SCIFA1_RTS_MARK, IDIN_MARK, | ||
293 | SCIFA1_RXD_MARK, | ||
294 | SCIFA1_CTS_MARK, MFG1_IN1_MARK, | ||
295 | MSIOF1_TXD_MARK, SCIFA2_TXD2_MARK, PORT230_FSIAOMC_MARK, | ||
296 | MSIOF1_TSYNC_MARK, SCIFA2_CTS2_MARK, PORT231_FSIAOLR_MARK, | ||
297 | MSIOF1_TSCK_MARK, SCIFA2_SCK2_MARK, PORT232_FSIAOBT_MARK, | ||
298 | MSIOF1_RXD_MARK, SCIFA2_RXD2_MARK, GPS_VCOTRIG_MARK, | ||
299 | PORT233_FSIACK_MARK, | ||
300 | MSIOF1_RSCK_MARK, SCIFA2_RTS2_MARK, PORT234_FSIAOSLD_MARK, | ||
301 | MSIOF1_RSYNC_MARK, OPORT0_MARK, MFG1_IN2_MARK, PORT235_FSIAILR_MARK, | ||
302 | MSIOF1_MCK0_MARK, I2C_SDA2_MARK, PORT236_FSIAIBT_MARK, | ||
303 | MSIOF1_MCK1_MARK, I2C_SCL2_MARK, PORT237_FSIAISLD_MARK, | ||
304 | MSIOF1_SS1_MARK, EDBGREQ3_MARK, | ||
305 | |||
306 | /* 55-5 */ | ||
307 | MSIOF1_SS2_MARK, | ||
308 | SCIFA6_TXD_MARK, | ||
309 | PORT241_IRDA_OUT_MARK, PORT241_IROUT_MARK, MFG4_OUT1_MARK, | ||
310 | TPU4TO0_MARK, | ||
311 | PORT242_IRDA_IN_MARK, MFG4_IN2_MARK, | ||
312 | PORT243_IRDA_FIRSEL_MARK, PORT243_VIO_CKO2_MARK, | ||
313 | PORT244_SCIFA5_CTS_MARK, MFG2_IN1_MARK, PORT244_SCIFB_CTS_MARK, | ||
314 | PORT244_MSIOF2_RXD_MARK, | ||
315 | PORT245_SCIFA5_RTS_MARK, MFG2_IN2_MARK, PORT245_SCIFB_RTS_MARK, | ||
316 | PORT245_MSIOF2_TXD_MARK, | ||
317 | PORT246_SCIFA5_RXD_MARK, MFG1_OUT1_MARK, PORT246_SCIFB_RXD_MARK, | ||
318 | TPU1TO0_MARK, | ||
319 | PORT247_SCIFA5_TXD_MARK, MFG3_OUT2_MARK, PORT247_SCIFB_TXD_MARK, | ||
320 | TPU3TO1_MARK, | ||
321 | PORT248_SCIFA5_SCK_MARK, MFG2_OUT1_MARK, PORT248_SCIFB_SCK_MARK, | ||
322 | TPU2TO0_MARK, | ||
323 | PORT248_MSIOF2_TSCK_MARK, | ||
324 | PORT249_IROUT_MARK, MFG4_IN1_MARK, PORT249_MSIOF2_TSYNC_MARK, | ||
325 | SDHICLK0_MARK, TCK2_SWCLK_MC0_MARK, | ||
326 | SDHICD0_MARK, | ||
327 | SDHID0_0_MARK, TMS2_SWDIO_MC0_MARK, | ||
328 | SDHID0_1_MARK, TDO2_SWO0_MC0_MARK, | ||
329 | SDHID0_2_MARK, TDI2_MARK, | ||
330 | SDHID0_3_MARK, RTCK2_SWO1_MC0_MARK, | ||
331 | SDHICMD0_MARK, TRST2_MARK, | ||
332 | SDHIWP0_MARK, EDBGREQ2_MARK, | ||
333 | SDHICLK1_MARK, TCK3_SWCLK_MC1_MARK, | ||
334 | SDHID1_0_MARK, M11_SLCD_SO2_MARK, TS_SPSYNC2_MARK, | ||
335 | TMS3_SWDIO_MC1_MARK, | ||
336 | SDHID1_1_MARK, M9_SLCD_A02_MARK, TS_SDAT2_MARK, TDO3_SWO0_MC1_MARK, | ||
337 | SDHID1_2_MARK, M10_SLCD_CK2_MARK, TS_SDEN2_MARK, TDI3_MARK, | ||
338 | SDHID1_3_MARK, M12_SLCD_CE2_MARK, TS_SCK2_MARK, RTCK3_SWO1_MC1_MARK, | ||
339 | SDHICMD1_MARK, TRST3_MARK, | ||
340 | RESETOUTS_MARK, | ||
341 | PINMUX_MARK_END, | ||
342 | }; | ||
343 | |||
344 | static pinmux_enum_t pinmux_data[] = { | ||
345 | /* specify valid pin states for each pin in GPIO mode */ | ||
346 | /* 55-1 (GPIO) */ | ||
347 | PORT_DATA_I_PD(0), PORT_DATA_I_PU(1), | ||
348 | PORT_DATA_I_PU(2), PORT_DATA_I_PU(3), | ||
349 | PORT_DATA_I_PU(4), PORT_DATA_I_PU(5), | ||
350 | PORT_DATA_I_PU(6), PORT_DATA_I_PU(7), | ||
351 | PORT_DATA_I_PU(8), PORT_DATA_I_PU(9), | ||
352 | PORT_DATA_I_PU(10), PORT_DATA_I_PU(11), | ||
353 | PORT_DATA_IO_PU(12), PORT_DATA_IO_PU(13), | ||
354 | PORT_DATA_IO_PU_PD(14), PORT_DATA_IO_PU_PD(15), | ||
355 | PORT_DATA_O(16), PORT_DATA_IO(17), | ||
356 | PORT_DATA_O(18), PORT_DATA_O(19), | ||
357 | PORT_DATA_O(20), PORT_DATA_O(21), | ||
358 | PORT_DATA_O(22), PORT_DATA_O(23), | ||
359 | PORT_DATA_O(24), PORT_DATA_I_PD(25), | ||
360 | PORT_DATA_I_PD(26), PORT_DATA_O(27), | ||
361 | PORT_DATA_O(28), PORT_DATA_O(29), | ||
362 | PORT_DATA_IO(30), PORT_DATA_IO_PU(31), | ||
363 | PORT_DATA_IO_PD(32), PORT_DATA_I_PU(33), | ||
364 | PORT_DATA_IO_PD(34), PORT_DATA_I_PU_PD(35), | ||
365 | PORT_DATA_O(36), PORT_DATA_IO(37), | ||
366 | |||
367 | /* 55-2 (GPIO) */ | ||
368 | PORT_DATA_O(38), PORT_DATA_I_PU(39), | ||
369 | PORT_DATA_I_PU_PD(40), PORT_DATA_O(41), | ||
370 | PORT_DATA_IO_PD(42), PORT_DATA_IO_PD(43), | ||
371 | PORT_DATA_IO_PD(44), PORT_DATA_I_PD(45), | ||
372 | PORT_DATA_I_PD(46), PORT_DATA_I_PD(47), | ||
373 | PORT_DATA_I_PD(48), PORT_DATA_IO_PU_PD(49), | ||
374 | PORT_DATA_IO_PD(50), PORT_DATA_IO_PD(51), | ||
375 | PORT_DATA_O(52), PORT_DATA_IO_PU_PD(53), | ||
376 | PORT_DATA_IO_PU_PD(54), PORT_DATA_IO_PD(55), | ||
377 | PORT_DATA_I_PU_PD(56), PORT_DATA_IO(57), | ||
378 | PORT_DATA_IO(58), PORT_DATA_IO(59), | ||
379 | PORT_DATA_IO(60), PORT_DATA_IO(61), | ||
380 | PORT_DATA_IO_PD(62), PORT_DATA_IO_PD(63), | ||
381 | PORT_DATA_IO_PD(64), PORT_DATA_IO_PD(65), | ||
382 | PORT_DATA_IO_PU_PD(66), PORT_DATA_IO_PU_PD(67), | ||
383 | PORT_DATA_IO_PU_PD(68), PORT_DATA_IO_PU_PD(69), | ||
384 | PORT_DATA_IO_PU_PD(70), PORT_DATA_IO_PU_PD(71), | ||
385 | PORT_DATA_IO_PU_PD(72), PORT_DATA_I_PU_PD(73), | ||
386 | PORT_DATA_IO_PU(74), PORT_DATA_IO_PU(75), | ||
387 | PORT_DATA_IO_PU(76), PORT_DATA_IO_PU(77), | ||
388 | PORT_DATA_IO_PU(78), PORT_DATA_IO_PU(79), | ||
389 | PORT_DATA_IO_PU(80), PORT_DATA_IO_PU(81), | ||
390 | PORT_DATA_IO_PU(82), PORT_DATA_IO_PU(83), | ||
391 | PORT_DATA_IO_PU(84), PORT_DATA_IO_PU(85), | ||
392 | PORT_DATA_IO_PU(86), PORT_DATA_IO_PU(87), | ||
393 | PORT_DATA_IO_PU(88), PORT_DATA_IO_PU(89), | ||
394 | PORT_DATA_O(90), PORT_DATA_IO_PU(91), | ||
395 | PORT_DATA_O(92), | ||
396 | |||
397 | /* 55-3 (GPIO) */ | ||
398 | PORT_DATA_IO_PU(93), | ||
399 | PORT_DATA_O(94), | ||
400 | PORT_DATA_I_PU_PD(95), | ||
401 | PORT_DATA_IO(96), PORT_DATA_IO(97), | ||
402 | PORT_DATA_IO(98), PORT_DATA_I_PU(99), | ||
403 | PORT_DATA_O(100), PORT_DATA_O(101), | ||
404 | PORT_DATA_I_PU(102), PORT_DATA_IO_PD(103), | ||
405 | PORT_DATA_I_PD(104), PORT_DATA_I_PD(105), | ||
406 | PORT_DATA_I_PD(106), PORT_DATA_I_PD(107), | ||
407 | PORT_DATA_I_PD(108), PORT_DATA_IO_PD(109), | ||
408 | PORT_DATA_IO_PD(110), PORT_DATA_I_PD(111), | ||
409 | PORT_DATA_IO_PD(112), PORT_DATA_IO_PD(113), | ||
410 | PORT_DATA_IO_PD(114), PORT_DATA_I_PD(115), | ||
411 | PORT_DATA_I_PD(116), PORT_DATA_IO_PD(117), | ||
412 | PORT_DATA_I_PD(118), PORT_DATA_IO_PD(128), | ||
413 | PORT_DATA_IO_PD(129), PORT_DATA_IO_PD(130), | ||
414 | PORT_DATA_IO_PD(131), PORT_DATA_IO_PD(132), | ||
415 | PORT_DATA_IO_PD(133), PORT_DATA_IO_PU_PD(134), | ||
416 | PORT_DATA_IO_PU_PD(135), PORT_DATA_IO_PU_PD(136), | ||
417 | PORT_DATA_IO_PU_PD(137), PORT_DATA_IO_PD(138), | ||
418 | PORT_DATA_IO_PD(139), PORT_DATA_IO_PD(140), | ||
419 | PORT_DATA_IO_PD(141), PORT_DATA_IO_PD(142), | ||
420 | PORT_DATA_IO_PD(143), PORT_DATA_IO_PU_PD(144), | ||
421 | PORT_DATA_IO_PD(145), PORT_DATA_IO_PU_PD(146), | ||
422 | PORT_DATA_IO_PU_PD(147), PORT_DATA_IO_PU_PD(148), | ||
423 | PORT_DATA_IO_PU_PD(149), PORT_DATA_I_PD(150), | ||
424 | PORT_DATA_IO_PU_PD(151), PORT_DATA_IO_PD(152), | ||
425 | PORT_DATA_IO_PD(153), PORT_DATA_IO_PD(154), | ||
426 | PORT_DATA_I_PD(155), PORT_DATA_IO_PU_PD(156), | ||
427 | PORT_DATA_I_PD(157), PORT_DATA_IO_PD(158), | ||
428 | |||
429 | /* 55-4 (GPIO) */ | ||
430 | PORT_DATA_IO_PU_PD(159), PORT_DATA_IO_PU_PD(160), | ||
431 | PORT_DATA_I_PU_PD(161), PORT_DATA_I_PU_PD(162), | ||
432 | PORT_DATA_IO_PU_PD(163), PORT_DATA_I_PU_PD(164), | ||
433 | PORT_DATA_IO_PD(192), PORT_DATA_IO_PD(193), | ||
434 | PORT_DATA_IO_PD(194), PORT_DATA_IO_PD(195), | ||
435 | PORT_DATA_IO_PD(196), PORT_DATA_IO_PD(197), | ||
436 | PORT_DATA_IO_PD(198), PORT_DATA_IO_PD(199), | ||
437 | PORT_DATA_IO_PU_PD(200), PORT_DATA_IO_PU_PD(201), | ||
438 | PORT_DATA_IO_PU_PD(202), PORT_DATA_IO_PU_PD(203), | ||
439 | PORT_DATA_IO_PU_PD(204), PORT_DATA_IO_PU_PD(205), | ||
440 | PORT_DATA_IO_PU_PD(206), PORT_DATA_IO_PD(207), | ||
441 | PORT_DATA_IO_PD(208), PORT_DATA_IO_PD(209), | ||
442 | PORT_DATA_IO_PD(210), PORT_DATA_IO_PD(211), | ||
443 | PORT_DATA_IO_PD(212), PORT_DATA_IO_PD(213), | ||
444 | PORT_DATA_IO_PD(214), PORT_DATA_IO_PD(215), | ||
445 | PORT_DATA_IO_PD(216), PORT_DATA_IO_PD(217), | ||
446 | PORT_DATA_O(218), PORT_DATA_IO_PD(219), | ||
447 | PORT_DATA_IO_PD(220), PORT_DATA_IO_PD(221), | ||
448 | PORT_DATA_IO_PU_PD(222), | ||
449 | PORT_DATA_I_PU_PD(223), PORT_DATA_I_PU_PD(224), | ||
450 | PORT_DATA_IO_PU_PD(225), PORT_DATA_O(226), | ||
451 | PORT_DATA_IO_PU_PD(227), PORT_DATA_I_PD(228), | ||
452 | PORT_DATA_I_PD(229), PORT_DATA_IO(230), | ||
453 | PORT_DATA_IO_PD(231), PORT_DATA_IO_PU_PD(232), | ||
454 | PORT_DATA_I_PD(233), PORT_DATA_IO_PU_PD(234), | ||
455 | PORT_DATA_IO_PU_PD(235), PORT_DATA_IO_PU_PD(236), | ||
456 | PORT_DATA_IO_PD(237), PORT_DATA_IO_PU_PD(238), | ||
457 | |||
458 | /* 55-5 (GPIO) */ | ||
459 | PORT_DATA_IO_PU_PD(239), PORT_DATA_IO_PU_PD(240), | ||
460 | PORT_DATA_O(241), PORT_DATA_I_PD(242), | ||
461 | PORT_DATA_IO_PU_PD(243), PORT_DATA_IO_PU_PD(244), | ||
462 | PORT_DATA_IO_PU_PD(245), PORT_DATA_IO_PU_PD(246), | ||
463 | PORT_DATA_IO_PU_PD(247), PORT_DATA_IO_PU_PD(248), | ||
464 | PORT_DATA_IO_PU_PD(249), PORT_DATA_IO_PD(250), | ||
465 | PORT_DATA_IO_PU_PD(251), PORT_DATA_IO_PU_PD(252), | ||
466 | PORT_DATA_IO_PU_PD(253), PORT_DATA_IO_PU_PD(254), | ||
467 | PORT_DATA_IO_PU_PD(255), PORT_DATA_IO_PU_PD(256), | ||
468 | PORT_DATA_IO_PU_PD(257), PORT_DATA_IO_PD(258), | ||
469 | PORT_DATA_IO_PU_PD(259), PORT_DATA_IO_PU_PD(260), | ||
470 | PORT_DATA_IO_PU_PD(261), PORT_DATA_IO_PU_PD(262), | ||
471 | PORT_DATA_IO_PU_PD(263), | ||
472 | |||
473 | /* Special Pull-up / Pull-down Functions */ | ||
474 | PINMUX_DATA(PORT66_KEYIN0_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0, | ||
475 | PORT66_FN2, PORT66_IN_PU), | ||
476 | PINMUX_DATA(PORT67_KEYIN1_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0, | ||
477 | PORT67_FN2, PORT67_IN_PU), | ||
478 | PINMUX_DATA(PORT68_KEYIN2_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0, | ||
479 | PORT68_FN2, PORT68_IN_PU), | ||
480 | PINMUX_DATA(PORT69_KEYIN3_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0, | ||
481 | PORT69_FN2, PORT69_IN_PU), | ||
482 | PINMUX_DATA(PORT70_KEYIN4_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0, | ||
483 | PORT70_FN2, PORT70_IN_PU), | ||
484 | PINMUX_DATA(PORT71_KEYIN5_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0, | ||
485 | PORT71_FN2, PORT71_IN_PU), | ||
486 | PINMUX_DATA(PORT72_KEYIN6_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0, | ||
487 | PORT72_FN2, PORT72_IN_PU), | ||
488 | |||
489 | |||
490 | /* 55-1 (FN) */ | ||
491 | PINMUX_DATA(VBUS_0_MARK, PORT0_FN1), | ||
492 | PINMUX_DATA(CPORT0_MARK, PORT1_FN1), | ||
493 | PINMUX_DATA(CPORT1_MARK, PORT2_FN1), | ||
494 | PINMUX_DATA(CPORT2_MARK, PORT3_FN1), | ||
495 | PINMUX_DATA(CPORT3_MARK, PORT4_FN1), | ||
496 | PINMUX_DATA(CPORT4_MARK, PORT5_FN1), | ||
497 | PINMUX_DATA(CPORT5_MARK, PORT6_FN1), | ||
498 | PINMUX_DATA(CPORT6_MARK, PORT7_FN1), | ||
499 | PINMUX_DATA(CPORT7_MARK, PORT8_FN1), | ||
500 | PINMUX_DATA(CPORT8_MARK, PORT9_FN1), | ||
501 | PINMUX_DATA(CPORT9_MARK, PORT10_FN1), | ||
502 | PINMUX_DATA(CPORT10_MARK, PORT11_FN1), | ||
503 | PINMUX_DATA(CPORT11_MARK, PORT12_FN1), | ||
504 | PINMUX_DATA(SIN2_MARK, PORT12_FN2), | ||
505 | PINMUX_DATA(CPORT12_MARK, PORT13_FN1), | ||
506 | PINMUX_DATA(XCTS2_MARK, PORT13_FN2), | ||
507 | PINMUX_DATA(CPORT13_MARK, PORT14_FN1), | ||
508 | PINMUX_DATA(RFSPO4_MARK, PORT14_FN2), | ||
509 | PINMUX_DATA(CPORT14_MARK, PORT15_FN1), | ||
510 | PINMUX_DATA(RFSPO5_MARK, PORT15_FN2), | ||
511 | PINMUX_DATA(CPORT15_MARK, PORT16_FN1), | ||
512 | PINMUX_DATA(SCIFA0_SCK_MARK, PORT16_FN2), | ||
513 | PINMUX_DATA(GPS_AGC2_MARK, PORT16_FN3), | ||
514 | PINMUX_DATA(CPORT16_MARK, PORT17_FN1), | ||
515 | PINMUX_DATA(SCIFA0_TXD_MARK, PORT17_FN2), | ||
516 | PINMUX_DATA(GPS_AGC3_MARK, PORT17_FN3), | ||
517 | PINMUX_DATA(CPORT17_IC_OE_MARK, PORT18_FN1), | ||
518 | PINMUX_DATA(SOUT2_MARK, PORT18_FN2), | ||
519 | PINMUX_DATA(CPORT18_MARK, PORT19_FN1), | ||
520 | PINMUX_DATA(XRTS2_MARK, PORT19_FN2), | ||
521 | PINMUX_DATA(PORT19_VIO_CKO2_MARK, PORT19_FN3), | ||
522 | PINMUX_DATA(CPORT19_MPORT1_MARK, PORT20_FN1), | ||
523 | PINMUX_DATA(CPORT20_MARK, PORT21_FN1), | ||
524 | PINMUX_DATA(RFSPO6_MARK, PORT21_FN2), | ||
525 | PINMUX_DATA(CPORT21_MARK, PORT22_FN1), | ||
526 | PINMUX_DATA(STATUS0_MARK, PORT22_FN2), | ||
527 | PINMUX_DATA(CPORT22_MARK, PORT23_FN1), | ||
528 | PINMUX_DATA(STATUS1_MARK, PORT23_FN2), | ||
529 | PINMUX_DATA(CPORT23_MARK, PORT24_FN1), | ||
530 | PINMUX_DATA(STATUS2_MARK, PORT24_FN2), | ||
531 | PINMUX_DATA(RFSPO7_MARK, PORT24_FN3), | ||
532 | PINMUX_DATA(B_SYNLD1_MARK, PORT25_FN1), | ||
533 | PINMUX_DATA(B_SYNLD2_MARK, PORT26_FN1), | ||
534 | PINMUX_DATA(SYSENMSK_MARK, PORT26_FN2), | ||
535 | PINMUX_DATA(XMAINPS_MARK, PORT27_FN1), | ||
536 | PINMUX_DATA(XDIVPS_MARK, PORT28_FN1), | ||
537 | PINMUX_DATA(XIDRST_MARK, PORT29_FN1), | ||
538 | PINMUX_DATA(IDCLK_MARK, PORT30_FN1), | ||
539 | PINMUX_DATA(IC_DP_MARK, PORT30_FN2), | ||
540 | PINMUX_DATA(IDIO_MARK, PORT31_FN1), | ||
541 | PINMUX_DATA(IC_DM_MARK, PORT31_FN2), | ||
542 | PINMUX_DATA(SOUT1_MARK, PORT32_FN1), | ||
543 | PINMUX_DATA(SCIFA4_TXD_MARK, PORT32_FN2), | ||
544 | PINMUX_DATA(M02_BERDAT_MARK, PORT32_FN3), | ||
545 | PINMUX_DATA(SIN1_MARK, PORT33_FN1), | ||
546 | PINMUX_DATA(SCIFA4_RXD_MARK, PORT33_FN2), | ||
547 | PINMUX_DATA(XWUP_MARK, PORT33_FN3), | ||
548 | PINMUX_DATA(XRTS1_MARK, PORT34_FN1), | ||
549 | PINMUX_DATA(SCIFA4_RTS_MARK, PORT34_FN2), | ||
550 | PINMUX_DATA(M03_BERCLK_MARK, PORT34_FN3), | ||
551 | PINMUX_DATA(XCTS1_MARK, PORT35_FN1), | ||
552 | PINMUX_DATA(SCIFA4_CTS_MARK, PORT35_FN2), | ||
553 | PINMUX_DATA(PCMCLKO_MARK, PORT36_FN1), | ||
554 | PINMUX_DATA(SYNC8KO_MARK, PORT37_FN1), | ||
555 | |||
556 | /* 55-2 (FN) */ | ||
557 | PINMUX_DATA(DNPCM_A_MARK, PORT38_FN1), | ||
558 | PINMUX_DATA(UPPCM_A_MARK, PORT39_FN1), | ||
559 | PINMUX_DATA(VACK_MARK, PORT40_FN1), | ||
560 | PINMUX_DATA(XTALB1L_MARK, PORT41_FN1), | ||
561 | PINMUX_DATA(GPS_AGC1_MARK, PORT42_FN1), | ||
562 | PINMUX_DATA(SCIFA0_RTS_MARK, PORT42_FN2), | ||
563 | PINMUX_DATA(GPS_AGC4_MARK, PORT43_FN1), | ||
564 | PINMUX_DATA(SCIFA0_RXD_MARK, PORT43_FN2), | ||
565 | PINMUX_DATA(GPS_PWRDOWN_MARK, PORT44_FN1), | ||
566 | PINMUX_DATA(SCIFA0_CTS_MARK, PORT44_FN2), | ||
567 | PINMUX_DATA(GPS_IM_MARK, PORT45_FN1), | ||
568 | PINMUX_DATA(GPS_IS_MARK, PORT46_FN1), | ||
569 | PINMUX_DATA(GPS_QM_MARK, PORT47_FN1), | ||
570 | PINMUX_DATA(GPS_QS_MARK, PORT48_FN1), | ||
571 | PINMUX_DATA(FMSOCK_MARK, PORT49_FN1), | ||
572 | PINMUX_DATA(PORT49_IRDA_OUT_MARK, PORT49_FN2), | ||
573 | PINMUX_DATA(PORT49_IROUT_MARK, PORT49_FN3), | ||
574 | PINMUX_DATA(FMSOOLR_MARK, PORT50_FN1), | ||
575 | PINMUX_DATA(BBIF2_TSYNC2_MARK, PORT50_FN2), | ||
576 | PINMUX_DATA(TPU2TO2_MARK, PORT50_FN3), | ||
577 | PINMUX_DATA(IPORT3_MARK, PORT50_FN4), | ||
578 | PINMUX_DATA(FMSIOLR_MARK, PORT50_FN5), | ||
579 | PINMUX_DATA(FMSOOBT_MARK, PORT51_FN1), | ||
580 | PINMUX_DATA(BBIF2_TSCK2_MARK, PORT51_FN2), | ||
581 | PINMUX_DATA(TPU2TO3_MARK, PORT51_FN3), | ||
582 | PINMUX_DATA(OPORT1_MARK, PORT51_FN4), | ||
583 | PINMUX_DATA(FMSIOBT_MARK, PORT51_FN5), | ||
584 | PINMUX_DATA(FMSOSLD_MARK, PORT52_FN1), | ||
585 | PINMUX_DATA(BBIF2_TXD2_MARK, PORT52_FN2), | ||
586 | PINMUX_DATA(OPORT2_MARK, PORT52_FN3), | ||
587 | PINMUX_DATA(FMSOILR_MARK, PORT53_FN1), | ||
588 | PINMUX_DATA(PORT53_IRDA_IN_MARK, PORT53_FN2), | ||
589 | PINMUX_DATA(TPU3TO3_MARK, PORT53_FN3), | ||
590 | PINMUX_DATA(OPORT3_MARK, PORT53_FN4), | ||
591 | PINMUX_DATA(FMSIILR_MARK, PORT53_FN5), | ||
592 | PINMUX_DATA(FMSOIBT_MARK, PORT54_FN1), | ||
593 | PINMUX_DATA(PORT54_IRDA_FIRSEL_MARK, PORT54_FN2), | ||
594 | PINMUX_DATA(TPU3TO2_MARK, PORT54_FN3), | ||
595 | PINMUX_DATA(FMSIIBT_MARK, PORT54_FN4), | ||
596 | PINMUX_DATA(FMSISLD_MARK, PORT55_FN1), | ||
597 | PINMUX_DATA(MFG0_OUT1_MARK, PORT55_FN2), | ||
598 | PINMUX_DATA(TPU0TO0_MARK, PORT55_FN3), | ||
599 | PINMUX_DATA(A0_EA0_MARK, PORT57_FN1), | ||
600 | PINMUX_DATA(BS_MARK, PORT57_FN2), | ||
601 | PINMUX_DATA(A12_EA12_MARK, PORT58_FN1), | ||
602 | PINMUX_DATA(PORT58_VIO_CKOR_MARK, PORT58_FN2), | ||
603 | PINMUX_DATA(TPU4TO2_MARK, PORT58_FN3), | ||
604 | PINMUX_DATA(A13_EA13_MARK, PORT59_FN1), | ||
605 | PINMUX_DATA(PORT59_IROUT_MARK, PORT59_FN2), | ||
606 | PINMUX_DATA(MFG0_OUT2_MARK, PORT59_FN3), | ||
607 | PINMUX_DATA(TPU0TO1_MARK, PORT59_FN4), | ||
608 | PINMUX_DATA(A14_EA14_MARK, PORT60_FN1), | ||
609 | PINMUX_DATA(PORT60_KEYOUT5_MARK, PORT60_FN2), | ||
610 | PINMUX_DATA(A15_EA15_MARK, PORT61_FN1), | ||
611 | PINMUX_DATA(PORT61_KEYOUT4_MARK, PORT61_FN2), | ||
612 | PINMUX_DATA(A16_EA16_MARK, PORT62_FN1), | ||
613 | PINMUX_DATA(PORT62_KEYOUT3_MARK, PORT62_FN2), | ||
614 | PINMUX_DATA(MSIOF0_SS1_MARK, PORT62_FN3), | ||
615 | PINMUX_DATA(A17_EA17_MARK, PORT63_FN1), | ||
616 | PINMUX_DATA(PORT63_KEYOUT2_MARK, PORT63_FN2), | ||
617 | PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT63_FN3), | ||
618 | PINMUX_DATA(A18_EA18_MARK, PORT64_FN1), | ||
619 | PINMUX_DATA(PORT64_KEYOUT1_MARK, PORT64_FN2), | ||
620 | PINMUX_DATA(MSIOF0_TSCK_MARK, PORT64_FN3), | ||
621 | PINMUX_DATA(A19_EA19_MARK, PORT65_FN1), | ||
622 | PINMUX_DATA(PORT65_KEYOUT0_MARK, PORT65_FN2), | ||
623 | PINMUX_DATA(MSIOF0_TXD_MARK, PORT65_FN3), | ||
624 | PINMUX_DATA(A20_EA20_MARK, PORT66_FN1), | ||
625 | PINMUX_DATA(PORT66_KEYIN0_MARK, PORT66_FN2), | ||
626 | PINMUX_DATA(MSIOF0_RSCK_MARK, PORT66_FN3), | ||
627 | PINMUX_DATA(A21_EA21_MARK, PORT67_FN1), | ||
628 | PINMUX_DATA(PORT67_KEYIN1_MARK, PORT67_FN2), | ||
629 | PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT67_FN3), | ||
630 | PINMUX_DATA(A22_EA22_MARK, PORT68_FN1), | ||
631 | PINMUX_DATA(PORT68_KEYIN2_MARK, PORT68_FN2), | ||
632 | PINMUX_DATA(MSIOF0_MCK0_MARK, PORT68_FN3), | ||
633 | PINMUX_DATA(A23_EA23_MARK, PORT69_FN1), | ||
634 | PINMUX_DATA(PORT69_KEYIN3_MARK, PORT69_FN2), | ||
635 | PINMUX_DATA(MSIOF0_MCK1_MARK, PORT69_FN3), | ||
636 | PINMUX_DATA(A24_EA24_MARK, PORT70_FN1), | ||
637 | PINMUX_DATA(PORT70_KEYIN4_MARK, PORT70_FN2), | ||
638 | PINMUX_DATA(MSIOF0_RXD_MARK, PORT70_FN3), | ||
639 | PINMUX_DATA(A25_EA25_MARK, PORT71_FN1), | ||
640 | PINMUX_DATA(PORT71_KEYIN5_MARK, PORT71_FN2), | ||
641 | PINMUX_DATA(MSIOF0_SS2_MARK, PORT71_FN3), | ||
642 | PINMUX_DATA(A26_MARK, PORT72_FN1), | ||
643 | PINMUX_DATA(PORT72_KEYIN6_MARK, PORT72_FN2), | ||
644 | PINMUX_DATA(D0_ED0_NAF0_MARK, PORT74_FN1), | ||
645 | PINMUX_DATA(D1_ED1_NAF1_MARK, PORT75_FN1), | ||
646 | PINMUX_DATA(D2_ED2_NAF2_MARK, PORT76_FN1), | ||
647 | PINMUX_DATA(D3_ED3_NAF3_MARK, PORT77_FN1), | ||
648 | PINMUX_DATA(D4_ED4_NAF4_MARK, PORT78_FN1), | ||
649 | PINMUX_DATA(D5_ED5_NAF5_MARK, PORT79_FN1), | ||
650 | PINMUX_DATA(D6_ED6_NAF6_MARK, PORT80_FN1), | ||
651 | PINMUX_DATA(D7_ED7_NAF7_MARK, PORT81_FN1), | ||
652 | PINMUX_DATA(D8_ED8_NAF8_MARK, PORT82_FN1), | ||
653 | PINMUX_DATA(D9_ED9_NAF9_MARK, PORT83_FN1), | ||
654 | PINMUX_DATA(D10_ED10_NAF10_MARK, PORT84_FN1), | ||
655 | PINMUX_DATA(D11_ED11_NAF11_MARK, PORT85_FN1), | ||
656 | PINMUX_DATA(D12_ED12_NAF12_MARK, PORT86_FN1), | ||
657 | PINMUX_DATA(D13_ED13_NAF13_MARK, PORT87_FN1), | ||
658 | PINMUX_DATA(D14_ED14_NAF14_MARK, PORT88_FN1), | ||
659 | PINMUX_DATA(D15_ED15_NAF15_MARK, PORT89_FN1), | ||
660 | PINMUX_DATA(CS4_MARK, PORT90_FN1), | ||
661 | PINMUX_DATA(CS5A_MARK, PORT91_FN1), | ||
662 | PINMUX_DATA(FMSICK_MARK, PORT91_FN2), | ||
663 | PINMUX_DATA(CS5B_MARK, PORT92_FN1), | ||
664 | PINMUX_DATA(FCE1_MARK, PORT92_FN2), | ||
665 | |||
666 | /* 55-3 (FN) */ | ||
667 | PINMUX_DATA(CS6B_MARK, PORT93_FN1), | ||
668 | PINMUX_DATA(XCS2_MARK, PORT93_FN2), | ||
669 | PINMUX_DATA(CS6A_MARK, PORT93_FN3), | ||
670 | PINMUX_DATA(DACK0_MARK, PORT93_FN4), | ||
671 | PINMUX_DATA(FCE0_MARK, PORT94_FN1), | ||
672 | PINMUX_DATA(WAIT_MARK, PORT95_FN1), | ||
673 | PINMUX_DATA(DREQ0_MARK, PORT95_FN2), | ||
674 | PINMUX_DATA(RD_XRD_MARK, PORT96_FN1), | ||
675 | PINMUX_DATA(WE0_XWR0_FWE_MARK, PORT97_FN1), | ||
676 | PINMUX_DATA(WE1_XWR1_MARK, PORT98_FN1), | ||
677 | PINMUX_DATA(FRB_MARK, PORT99_FN1), | ||
678 | PINMUX_DATA(CKO_MARK, PORT100_FN1), | ||
679 | PINMUX_DATA(NBRSTOUT_MARK, PORT101_FN1), | ||
680 | PINMUX_DATA(NBRST_MARK, PORT102_FN1), | ||
681 | PINMUX_DATA(GPS_EPPSIN_MARK, PORT106_FN1), | ||
682 | PINMUX_DATA(LATCHPULSE_MARK, PORT110_FN1), | ||
683 | PINMUX_DATA(LTESIGNAL_MARK, PORT111_FN1), | ||
684 | PINMUX_DATA(LEGACYSTATE_MARK, PORT112_FN1), | ||
685 | PINMUX_DATA(TCKON_MARK, PORT118_FN1), | ||
686 | PINMUX_DATA(VIO_VD_MARK, PORT128_FN1), | ||
687 | PINMUX_DATA(PORT128_KEYOUT0_MARK, PORT128_FN2), | ||
688 | PINMUX_DATA(IPORT0_MARK, PORT128_FN3), | ||
689 | PINMUX_DATA(VIO_HD_MARK, PORT129_FN1), | ||
690 | PINMUX_DATA(PORT129_KEYOUT1_MARK, PORT129_FN2), | ||
691 | PINMUX_DATA(IPORT1_MARK, PORT129_FN3), | ||
692 | PINMUX_DATA(VIO_D0_MARK, PORT130_FN1), | ||
693 | PINMUX_DATA(PORT130_KEYOUT2_MARK, PORT130_FN2), | ||
694 | PINMUX_DATA(PORT130_MSIOF2_RXD_MARK, PORT130_FN3), | ||
695 | PINMUX_DATA(VIO_D1_MARK, PORT131_FN1), | ||
696 | PINMUX_DATA(PORT131_KEYOUT3_MARK, PORT131_FN2), | ||
697 | PINMUX_DATA(PORT131_MSIOF2_SS1_MARK, PORT131_FN3), | ||
698 | PINMUX_DATA(VIO_D2_MARK, PORT132_FN1), | ||
699 | PINMUX_DATA(PORT132_KEYOUT4_MARK, PORT132_FN2), | ||
700 | PINMUX_DATA(PORT132_MSIOF2_SS2_MARK, PORT132_FN3), | ||
701 | PINMUX_DATA(VIO_D3_MARK, PORT133_FN1), | ||
702 | PINMUX_DATA(PORT133_KEYOUT5_MARK, PORT133_FN2), | ||
703 | PINMUX_DATA(PORT133_MSIOF2_TSYNC_MARK, PORT133_FN3), | ||
704 | PINMUX_DATA(VIO_D4_MARK, PORT134_FN1), | ||
705 | PINMUX_DATA(PORT134_KEYIN0_MARK, PORT134_FN2), | ||
706 | PINMUX_DATA(PORT134_MSIOF2_TXD_MARK, PORT134_FN3), | ||
707 | PINMUX_DATA(VIO_D5_MARK, PORT135_FN1), | ||
708 | PINMUX_DATA(PORT135_KEYIN1_MARK, PORT135_FN2), | ||
709 | PINMUX_DATA(PORT135_MSIOF2_TSCK_MARK, PORT135_FN3), | ||
710 | PINMUX_DATA(VIO_D6_MARK, PORT136_FN1), | ||
711 | PINMUX_DATA(PORT136_KEYIN2_MARK, PORT136_FN2), | ||
712 | PINMUX_DATA(VIO_D7_MARK, PORT137_FN1), | ||
713 | PINMUX_DATA(PORT137_KEYIN3_MARK, PORT137_FN2), | ||
714 | PINMUX_DATA(VIO_D8_MARK, PORT138_FN1), | ||
715 | PINMUX_DATA(M9_SLCD_A01_MARK, PORT138_FN2), | ||
716 | PINMUX_DATA(PORT138_FSIAOMC_MARK, PORT138_FN3), | ||
717 | PINMUX_DATA(VIO_D9_MARK, PORT139_FN1), | ||
718 | PINMUX_DATA(M10_SLCD_CK1_MARK, PORT139_FN2), | ||
719 | PINMUX_DATA(PORT139_FSIAOLR_MARK, PORT139_FN3), | ||
720 | PINMUX_DATA(VIO_D10_MARK, PORT140_FN1), | ||
721 | PINMUX_DATA(M11_SLCD_SO1_MARK, PORT140_FN2), | ||
722 | PINMUX_DATA(TPU0TO2_MARK, PORT140_FN3), | ||
723 | PINMUX_DATA(PORT140_FSIAOBT_MARK, PORT140_FN4), | ||
724 | PINMUX_DATA(VIO_D11_MARK, PORT141_FN1), | ||
725 | PINMUX_DATA(M12_SLCD_CE1_MARK, PORT141_FN2), | ||
726 | PINMUX_DATA(TPU0TO3_MARK, PORT141_FN3), | ||
727 | PINMUX_DATA(PORT141_FSIAOSLD_MARK, PORT141_FN4), | ||
728 | PINMUX_DATA(VIO_D12_MARK, PORT142_FN1), | ||
729 | PINMUX_DATA(M13_BSW_MARK, PORT142_FN2), | ||
730 | PINMUX_DATA(PORT142_FSIACK_MARK, PORT142_FN3), | ||
731 | PINMUX_DATA(VIO_D13_MARK, PORT143_FN1), | ||
732 | PINMUX_DATA(M14_GSW_MARK, PORT143_FN2), | ||
733 | PINMUX_DATA(PORT143_FSIAILR_MARK, PORT143_FN3), | ||
734 | PINMUX_DATA(VIO_D14_MARK, PORT144_FN1), | ||
735 | PINMUX_DATA(M15_RSW_MARK, PORT144_FN2), | ||
736 | PINMUX_DATA(PORT144_FSIAIBT_MARK, PORT144_FN3), | ||
737 | PINMUX_DATA(VIO_D15_MARK, PORT145_FN1), | ||
738 | PINMUX_DATA(TPU1TO3_MARK, PORT145_FN2), | ||
739 | PINMUX_DATA(PORT145_FSIAISLD_MARK, PORT145_FN3), | ||
740 | PINMUX_DATA(VIO_CLK_MARK, PORT146_FN1), | ||
741 | PINMUX_DATA(PORT146_KEYIN4_MARK, PORT146_FN2), | ||
742 | PINMUX_DATA(IPORT2_MARK, PORT146_FN3), | ||
743 | PINMUX_DATA(VIO_FIELD_MARK, PORT147_FN1), | ||
744 | PINMUX_DATA(PORT147_KEYIN5_MARK, PORT147_FN2), | ||
745 | PINMUX_DATA(VIO_CKO_MARK, PORT148_FN1), | ||
746 | PINMUX_DATA(PORT148_KEYIN6_MARK, PORT148_FN2), | ||
747 | PINMUX_DATA(A27_MARK, PORT149_FN1), | ||
748 | PINMUX_DATA(RDWR_XWE_MARK, PORT149_FN2), | ||
749 | PINMUX_DATA(MFG0_IN1_MARK, PORT149_FN3), | ||
750 | PINMUX_DATA(MFG0_IN2_MARK, PORT150_FN1), | ||
751 | PINMUX_DATA(TS_SPSYNC3_MARK, PORT151_FN1), | ||
752 | PINMUX_DATA(MSIOF2_RSCK_MARK, PORT151_FN2), | ||
753 | PINMUX_DATA(TS_SDAT3_MARK, PORT152_FN1), | ||
754 | PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT152_FN2), | ||
755 | PINMUX_DATA(TPU1TO2_MARK, PORT153_FN1), | ||
756 | PINMUX_DATA(TS_SDEN3_MARK, PORT153_FN2), | ||
757 | PINMUX_DATA(PORT153_MSIOF2_SS1_MARK, PORT153_FN3), | ||
758 | PINMUX_DATA(SOUT3_MARK, PORT154_FN1), | ||
759 | PINMUX_DATA(SCIFA2_TXD1_MARK, PORT154_FN2), | ||
760 | PINMUX_DATA(MSIOF2_MCK0_MARK, PORT154_FN3), | ||
761 | PINMUX_DATA(SIN3_MARK, PORT155_FN1), | ||
762 | PINMUX_DATA(SCIFA2_RXD1_MARK, PORT155_FN2), | ||
763 | PINMUX_DATA(MSIOF2_MCK1_MARK, PORT155_FN3), | ||
764 | PINMUX_DATA(XRTS3_MARK, PORT156_FN1), | ||
765 | PINMUX_DATA(SCIFA2_RTS1_MARK, PORT156_FN2), | ||
766 | PINMUX_DATA(PORT156_MSIOF2_SS2_MARK, PORT156_FN3), | ||
767 | PINMUX_DATA(XCTS3_MARK, PORT157_FN1), | ||
768 | PINMUX_DATA(SCIFA2_CTS1_MARK, PORT157_FN2), | ||
769 | PINMUX_DATA(PORT157_MSIOF2_RXD_MARK, PORT157_FN3), | ||
770 | |||
771 | /* 55-4 (FN) */ | ||
772 | PINMUX_DATA(DINT_MARK, PORT158_FN1), | ||
773 | PINMUX_DATA(SCIFA2_SCK1_MARK, PORT158_FN2), | ||
774 | PINMUX_DATA(TS_SCK3_MARK, PORT158_FN3), | ||
775 | PINMUX_DATA(PORT159_SCIFB_SCK_MARK, PORT159_FN1), | ||
776 | PINMUX_DATA(PORT159_SCIFA5_SCK_MARK, PORT159_FN2), | ||
777 | PINMUX_DATA(NMI_MARK, PORT159_FN3), | ||
778 | PINMUX_DATA(PORT160_SCIFB_TXD_MARK, PORT160_FN1), | ||
779 | PINMUX_DATA(PORT160_SCIFA5_TXD_MARK, PORT160_FN2), | ||
780 | PINMUX_DATA(SOUT0_MARK, PORT160_FN3), | ||
781 | PINMUX_DATA(PORT161_SCIFB_CTS_MARK, PORT161_FN1), | ||
782 | PINMUX_DATA(PORT161_SCIFA5_CTS_MARK, PORT161_FN2), | ||
783 | PINMUX_DATA(XCTS0_MARK, PORT161_FN3), | ||
784 | PINMUX_DATA(MFG3_IN2_MARK, PORT161_FN4), | ||
785 | PINMUX_DATA(PORT162_SCIFB_RXD_MARK, PORT162_FN1), | ||
786 | PINMUX_DATA(PORT162_SCIFA5_RXD_MARK, PORT162_FN2), | ||
787 | PINMUX_DATA(SIN0_MARK, PORT162_FN3), | ||
788 | PINMUX_DATA(MFG3_IN1_MARK, PORT162_FN4), | ||
789 | PINMUX_DATA(PORT163_SCIFB_RTS_MARK, PORT163_FN1), | ||
790 | PINMUX_DATA(PORT163_SCIFA5_RTS_MARK, PORT163_FN2), | ||
791 | PINMUX_DATA(XRTS0_MARK, PORT163_FN3), | ||
792 | PINMUX_DATA(MFG3_OUT1_MARK, PORT163_FN4), | ||
793 | PINMUX_DATA(TPU3TO0_MARK, PORT163_FN5), | ||
794 | PINMUX_DATA(LCDD0_MARK, PORT192_FN1), | ||
795 | PINMUX_DATA(PORT192_KEYOUT0_MARK, PORT192_FN2), | ||
796 | PINMUX_DATA(EXT_CKI_MARK, PORT192_FN3), | ||
797 | PINMUX_DATA(LCDD1_MARK, PORT193_FN1), | ||
798 | PINMUX_DATA(PORT193_KEYOUT1_MARK, PORT193_FN2), | ||
799 | PINMUX_DATA(PORT193_SCIFA5_CTS_MARK, PORT193_FN3), | ||
800 | PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT193_FN4), | ||
801 | PINMUX_DATA(LCDD2_MARK, PORT194_FN1), | ||
802 | PINMUX_DATA(PORT194_KEYOUT2_MARK, PORT194_FN2), | ||
803 | PINMUX_DATA(PORT194_SCIFA5_RTS_MARK, PORT194_FN3), | ||
804 | PINMUX_DATA(BBIF2_TSCK1_MARK, PORT194_FN4), | ||
805 | PINMUX_DATA(LCDD3_MARK, PORT195_FN1), | ||
806 | PINMUX_DATA(PORT195_KEYOUT3_MARK, PORT195_FN2), | ||
807 | PINMUX_DATA(PORT195_SCIFA5_RXD_MARK, PORT195_FN3), | ||
808 | PINMUX_DATA(BBIF2_TXD1_MARK, PORT195_FN4), | ||
809 | PINMUX_DATA(LCDD4_MARK, PORT196_FN1), | ||
810 | PINMUX_DATA(PORT196_KEYOUT4_MARK, PORT196_FN2), | ||
811 | PINMUX_DATA(PORT196_SCIFA5_TXD_MARK, PORT196_FN3), | ||
812 | PINMUX_DATA(LCDD5_MARK, PORT197_FN1), | ||
813 | PINMUX_DATA(PORT197_KEYOUT5_MARK, PORT197_FN2), | ||
814 | PINMUX_DATA(PORT197_SCIFA5_SCK_MARK, PORT197_FN3), | ||
815 | PINMUX_DATA(MFG2_OUT2_MARK, PORT197_FN4), | ||
816 | PINMUX_DATA(LCDD6_MARK, PORT198_FN1), | ||
817 | PINMUX_DATA(LCDD7_MARK, PORT199_FN1), | ||
818 | PINMUX_DATA(TPU4TO1_MARK, PORT199_FN2), | ||
819 | PINMUX_DATA(MFG4_OUT2_MARK, PORT199_FN3), | ||
820 | PINMUX_DATA(LCDD8_MARK, PORT200_FN1), | ||
821 | PINMUX_DATA(PORT200_KEYIN0_MARK, PORT200_FN2), | ||
822 | PINMUX_DATA(VIO_DR0_MARK, PORT200_FN3), | ||
823 | PINMUX_DATA(D16_MARK, PORT200_FN4), | ||
824 | PINMUX_DATA(LCDD9_MARK, PORT201_FN1), | ||
825 | PINMUX_DATA(PORT201_KEYIN1_MARK, PORT201_FN2), | ||
826 | PINMUX_DATA(VIO_DR1_MARK, PORT201_FN3), | ||
827 | PINMUX_DATA(D17_MARK, PORT201_FN4), | ||
828 | PINMUX_DATA(LCDD10_MARK, PORT202_FN1), | ||
829 | PINMUX_DATA(PORT202_KEYIN2_MARK, PORT202_FN2), | ||
830 | PINMUX_DATA(VIO_DR2_MARK, PORT202_FN3), | ||
831 | PINMUX_DATA(D18_MARK, PORT202_FN4), | ||
832 | PINMUX_DATA(LCDD11_MARK, PORT203_FN1), | ||
833 | PINMUX_DATA(PORT203_KEYIN3_MARK, PORT203_FN2), | ||
834 | PINMUX_DATA(VIO_DR3_MARK, PORT203_FN3), | ||
835 | PINMUX_DATA(D19_MARK, PORT203_FN4), | ||
836 | PINMUX_DATA(LCDD12_MARK, PORT204_FN1), | ||
837 | PINMUX_DATA(PORT204_KEYIN4_MARK, PORT204_FN2), | ||
838 | PINMUX_DATA(VIO_DR4_MARK, PORT204_FN3), | ||
839 | PINMUX_DATA(D20_MARK, PORT204_FN4), | ||
840 | PINMUX_DATA(LCDD13_MARK, PORT205_FN1), | ||
841 | PINMUX_DATA(PORT205_KEYIN5_MARK, PORT205_FN2), | ||
842 | PINMUX_DATA(VIO_DR5_MARK, PORT205_FN3), | ||
843 | PINMUX_DATA(D21_MARK, PORT205_FN4), | ||
844 | PINMUX_DATA(LCDD14_MARK, PORT206_FN1), | ||
845 | PINMUX_DATA(PORT206_KEYIN6_MARK, PORT206_FN2), | ||
846 | PINMUX_DATA(VIO_DR6_MARK, PORT206_FN3), | ||
847 | PINMUX_DATA(D22_MARK, PORT206_FN4), | ||
848 | PINMUX_DATA(LCDD15_MARK, PORT207_FN1), | ||
849 | PINMUX_DATA(PORT207_MSIOF0L_SS1_MARK, PORT207_FN2), | ||
850 | PINMUX_DATA(PORT207_KEYOUT0_MARK, PORT207_FN3), | ||
851 | PINMUX_DATA(VIO_DR7_MARK, PORT207_FN4), | ||
852 | PINMUX_DATA(D23_MARK, PORT207_FN5), | ||
853 | PINMUX_DATA(LCDD16_MARK, PORT208_FN1), | ||
854 | PINMUX_DATA(PORT208_MSIOF0L_SS2_MARK, PORT208_FN2), | ||
855 | PINMUX_DATA(PORT208_KEYOUT1_MARK, PORT208_FN3), | ||
856 | PINMUX_DATA(VIO_VDR_MARK, PORT208_FN4), | ||
857 | PINMUX_DATA(D24_MARK, PORT208_FN5), | ||
858 | PINMUX_DATA(LCDD17_MARK, PORT209_FN1), | ||
859 | PINMUX_DATA(PORT209_KEYOUT2_MARK, PORT209_FN2), | ||
860 | PINMUX_DATA(VIO_HDR_MARK, PORT209_FN3), | ||
861 | PINMUX_DATA(D25_MARK, PORT209_FN4), | ||
862 | PINMUX_DATA(LCDD18_MARK, PORT210_FN1), | ||
863 | PINMUX_DATA(DREQ2_MARK, PORT210_FN2), | ||
864 | PINMUX_DATA(PORT210_MSIOF0L_SS1_MARK, PORT210_FN3), | ||
865 | PINMUX_DATA(D26_MARK, PORT210_FN4), | ||
866 | PINMUX_DATA(LCDD19_MARK, PORT211_FN1), | ||
867 | PINMUX_DATA(PORT211_MSIOF0L_SS2_MARK, PORT211_FN2), | ||
868 | PINMUX_DATA(D27_MARK, PORT211_FN3), | ||
869 | PINMUX_DATA(LCDD20_MARK, PORT212_FN1), | ||
870 | PINMUX_DATA(TS_SPSYNC1_MARK, PORT212_FN2), | ||
871 | PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT212_FN3), | ||
872 | PINMUX_DATA(D28_MARK, PORT212_FN4), | ||
873 | PINMUX_DATA(LCDD21_MARK, PORT213_FN1), | ||
874 | PINMUX_DATA(TS_SDAT1_MARK, PORT213_FN2), | ||
875 | PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT213_FN3), | ||
876 | PINMUX_DATA(D29_MARK, PORT213_FN4), | ||
877 | PINMUX_DATA(LCDD22_MARK, PORT214_FN1), | ||
878 | PINMUX_DATA(TS_SDEN1_MARK, PORT214_FN2), | ||
879 | PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT214_FN3), | ||
880 | PINMUX_DATA(D30_MARK, PORT214_FN4), | ||
881 | PINMUX_DATA(LCDD23_MARK, PORT215_FN1), | ||
882 | PINMUX_DATA(TS_SCK1_MARK, PORT215_FN2), | ||
883 | PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT215_FN3), | ||
884 | PINMUX_DATA(D31_MARK, PORT215_FN4), | ||
885 | PINMUX_DATA(LCDDCK_MARK, PORT216_FN1), | ||
886 | PINMUX_DATA(LCDWR_MARK, PORT216_FN2), | ||
887 | PINMUX_DATA(PORT216_KEYOUT3_MARK, PORT216_FN3), | ||
888 | PINMUX_DATA(VIO_CLKR_MARK, PORT216_FN4), | ||
889 | PINMUX_DATA(LCDRD_MARK, PORT217_FN1), | ||
890 | PINMUX_DATA(DACK2_MARK, PORT217_FN2), | ||
891 | PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT217_FN3), | ||
892 | PINMUX_DATA(LCDHSYN_MARK, PORT218_FN1), | ||
893 | PINMUX_DATA(LCDCS_MARK, PORT218_FN2), | ||
894 | PINMUX_DATA(LCDCS2_MARK, PORT218_FN3), | ||
895 | PINMUX_DATA(DACK3_MARK, PORT218_FN4), | ||
896 | PINMUX_DATA(PORT218_VIO_CKOR_MARK, PORT218_FN5), | ||
897 | PINMUX_DATA(PORT218_KEYOUT4_MARK, PORT218_FN6), | ||
898 | PINMUX_DATA(LCDDISP_MARK, PORT219_FN1), | ||
899 | PINMUX_DATA(LCDRS_MARK, PORT219_FN2), | ||
900 | PINMUX_DATA(DREQ3_MARK, PORT219_FN3), | ||
901 | PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT219_FN4), | ||
902 | PINMUX_DATA(LCDVSYN_MARK, PORT220_FN1), | ||
903 | PINMUX_DATA(LCDVSYN2_MARK, PORT220_FN2), | ||
904 | PINMUX_DATA(PORT220_KEYOUT5_MARK, PORT220_FN3), | ||
905 | PINMUX_DATA(LCDLCLK_MARK, PORT221_FN1), | ||
906 | PINMUX_DATA(DREQ1_MARK, PORT221_FN2), | ||
907 | PINMUX_DATA(PWEN_MARK, PORT221_FN3), | ||
908 | PINMUX_DATA(MSIOF0L_RXD_MARK, PORT221_FN4), | ||
909 | PINMUX_DATA(LCDDON_MARK, PORT222_FN1), | ||
910 | PINMUX_DATA(LCDDON2_MARK, PORT222_FN2), | ||
911 | PINMUX_DATA(DACK1_MARK, PORT222_FN3), | ||
912 | PINMUX_DATA(OVCN_MARK, PORT222_FN4), | ||
913 | PINMUX_DATA(MSIOF0L_TXD_MARK, PORT222_FN5), | ||
914 | PINMUX_DATA(SCIFA1_TXD_MARK, PORT225_FN1), | ||
915 | PINMUX_DATA(OVCN2_MARK, PORT225_FN2), | ||
916 | PINMUX_DATA(EXTLP_MARK, PORT226_FN1), | ||
917 | PINMUX_DATA(SCIFA1_SCK_MARK, PORT226_FN2), | ||
918 | PINMUX_DATA(USBTERM_MARK, PORT226_FN3), | ||
919 | PINMUX_DATA(PORT226_VIO_CKO2_MARK, PORT226_FN4), | ||
920 | PINMUX_DATA(SCIFA1_RTS_MARK, PORT227_FN1), | ||
921 | PINMUX_DATA(IDIN_MARK, PORT227_FN2), | ||
922 | PINMUX_DATA(SCIFA1_RXD_MARK, PORT228_FN1), | ||
923 | PINMUX_DATA(SCIFA1_CTS_MARK, PORT229_FN1), | ||
924 | PINMUX_DATA(MFG1_IN1_MARK, PORT229_FN2), | ||
925 | PINMUX_DATA(MSIOF1_TXD_MARK, PORT230_FN1), | ||
926 | PINMUX_DATA(SCIFA2_TXD2_MARK, PORT230_FN2), | ||
927 | PINMUX_DATA(PORT230_FSIAOMC_MARK, PORT230_FN3), | ||
928 | PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT231_FN1), | ||
929 | PINMUX_DATA(SCIFA2_CTS2_MARK, PORT231_FN2), | ||
930 | PINMUX_DATA(PORT231_FSIAOLR_MARK, PORT231_FN3), | ||
931 | PINMUX_DATA(MSIOF1_TSCK_MARK, PORT232_FN1), | ||
932 | PINMUX_DATA(SCIFA2_SCK2_MARK, PORT232_FN2), | ||
933 | PINMUX_DATA(PORT232_FSIAOBT_MARK, PORT232_FN3), | ||
934 | PINMUX_DATA(MSIOF1_RXD_MARK, PORT233_FN1), | ||
935 | PINMUX_DATA(SCIFA2_RXD2_MARK, PORT233_FN2), | ||
936 | PINMUX_DATA(GPS_VCOTRIG_MARK, PORT233_FN3), | ||
937 | PINMUX_DATA(PORT233_FSIACK_MARK, PORT233_FN4), | ||
938 | PINMUX_DATA(MSIOF1_RSCK_MARK, PORT234_FN1), | ||
939 | PINMUX_DATA(SCIFA2_RTS2_MARK, PORT234_FN2), | ||
940 | PINMUX_DATA(PORT234_FSIAOSLD_MARK, PORT234_FN3), | ||
941 | PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT235_FN1), | ||
942 | PINMUX_DATA(OPORT0_MARK, PORT235_FN2), | ||
943 | PINMUX_DATA(MFG1_IN2_MARK, PORT235_FN3), | ||
944 | PINMUX_DATA(PORT235_FSIAILR_MARK, PORT235_FN4), | ||
945 | PINMUX_DATA(MSIOF1_MCK0_MARK, PORT236_FN1), | ||
946 | PINMUX_DATA(I2C_SDA2_MARK, PORT236_FN2), | ||
947 | PINMUX_DATA(PORT236_FSIAIBT_MARK, PORT236_FN3), | ||
948 | PINMUX_DATA(MSIOF1_MCK1_MARK, PORT237_FN1), | ||
949 | PINMUX_DATA(I2C_SCL2_MARK, PORT237_FN2), | ||
950 | PINMUX_DATA(PORT237_FSIAISLD_MARK, PORT237_FN3), | ||
951 | PINMUX_DATA(MSIOF1_SS1_MARK, PORT238_FN1), | ||
952 | PINMUX_DATA(EDBGREQ3_MARK, PORT238_FN2), | ||
953 | |||
954 | /* 55-5 (FN) */ | ||
955 | PINMUX_DATA(MSIOF1_SS2_MARK, PORT239_FN1), | ||
956 | PINMUX_DATA(SCIFA6_TXD_MARK, PORT240_FN1), | ||
957 | PINMUX_DATA(PORT241_IRDA_OUT_MARK, PORT241_FN1), | ||
958 | PINMUX_DATA(PORT241_IROUT_MARK, PORT241_FN2), | ||
959 | PINMUX_DATA(MFG4_OUT1_MARK, PORT241_FN3), | ||
960 | PINMUX_DATA(TPU4TO0_MARK, PORT241_FN4), | ||
961 | PINMUX_DATA(PORT242_IRDA_IN_MARK, PORT242_FN1), | ||
962 | PINMUX_DATA(MFG4_IN2_MARK, PORT242_FN2), | ||
963 | PINMUX_DATA(PORT243_IRDA_FIRSEL_MARK, PORT243_FN1), | ||
964 | PINMUX_DATA(PORT243_VIO_CKO2_MARK, PORT243_FN2), | ||
965 | PINMUX_DATA(PORT244_SCIFA5_CTS_MARK, PORT244_FN1), | ||
966 | PINMUX_DATA(MFG2_IN1_MARK, PORT244_FN2), | ||
967 | PINMUX_DATA(PORT244_SCIFB_CTS_MARK, PORT244_FN3), | ||
968 | PINMUX_DATA(PORT245_SCIFA5_RTS_MARK, PORT245_FN1), | ||
969 | PINMUX_DATA(MFG2_IN2_MARK, PORT245_FN2), | ||
970 | PINMUX_DATA(PORT245_SCIFB_RTS_MARK, PORT245_FN3), | ||
971 | PINMUX_DATA(PORT246_SCIFA5_RXD_MARK, PORT246_FN1), | ||
972 | PINMUX_DATA(MFG1_OUT1_MARK, PORT246_FN2), | ||
973 | PINMUX_DATA(PORT246_SCIFB_RXD_MARK, PORT246_FN3), | ||
974 | PINMUX_DATA(TPU1TO0_MARK, PORT246_FN4), | ||
975 | PINMUX_DATA(PORT247_SCIFA5_TXD_MARK, PORT247_FN1), | ||
976 | PINMUX_DATA(MFG3_OUT2_MARK, PORT247_FN2), | ||
977 | PINMUX_DATA(PORT247_SCIFB_TXD_MARK, PORT247_FN3), | ||
978 | PINMUX_DATA(TPU3TO1_MARK, PORT247_FN4), | ||
979 | PINMUX_DATA(PORT248_SCIFA5_SCK_MARK, PORT248_FN1), | ||
980 | PINMUX_DATA(MFG2_OUT1_MARK, PORT248_FN2), | ||
981 | PINMUX_DATA(PORT248_SCIFB_SCK_MARK, PORT248_FN3), | ||
982 | PINMUX_DATA(TPU2TO0_MARK, PORT248_FN4), | ||
983 | PINMUX_DATA(PORT249_IROUT_MARK, PORT249_FN1), | ||
984 | PINMUX_DATA(MFG4_IN1_MARK, PORT249_FN2), | ||
985 | PINMUX_DATA(SDHICLK0_MARK, PORT250_FN1), | ||
986 | PINMUX_DATA(TCK2_SWCLK_MC0_MARK, PORT250_FN2), | ||
987 | PINMUX_DATA(SDHICD0_MARK, PORT251_FN1), | ||
988 | PINMUX_DATA(SDHID0_0_MARK, PORT252_FN1), | ||
989 | PINMUX_DATA(TMS2_SWDIO_MC0_MARK, PORT252_FN2), | ||
990 | PINMUX_DATA(SDHID0_1_MARK, PORT253_FN1), | ||
991 | PINMUX_DATA(TDO2_SWO0_MC0_MARK, PORT253_FN2), | ||
992 | PINMUX_DATA(SDHID0_2_MARK, PORT254_FN1), | ||
993 | PINMUX_DATA(TDI2_MARK, PORT254_FN2), | ||
994 | PINMUX_DATA(SDHID0_3_MARK, PORT255_FN1), | ||
995 | PINMUX_DATA(RTCK2_SWO1_MC0_MARK, PORT255_FN2), | ||
996 | PINMUX_DATA(SDHICMD0_MARK, PORT256_FN1), | ||
997 | PINMUX_DATA(TRST2_MARK, PORT256_FN2), | ||
998 | PINMUX_DATA(SDHIWP0_MARK, PORT257_FN1), | ||
999 | PINMUX_DATA(EDBGREQ2_MARK, PORT257_FN2), | ||
1000 | PINMUX_DATA(SDHICLK1_MARK, PORT258_FN1), | ||
1001 | PINMUX_DATA(TCK3_SWCLK_MC1_MARK, PORT258_FN2), | ||
1002 | PINMUX_DATA(SDHID1_0_MARK, PORT259_FN1), | ||
1003 | PINMUX_DATA(M11_SLCD_SO2_MARK, PORT259_FN2), | ||
1004 | PINMUX_DATA(TS_SPSYNC2_MARK, PORT259_FN3), | ||
1005 | PINMUX_DATA(TMS3_SWDIO_MC1_MARK, PORT259_FN4), | ||
1006 | PINMUX_DATA(SDHID1_1_MARK, PORT260_FN1), | ||
1007 | PINMUX_DATA(M9_SLCD_A02_MARK, PORT260_FN2), | ||
1008 | PINMUX_DATA(TS_SDAT2_MARK, PORT260_FN3), | ||
1009 | PINMUX_DATA(TDO3_SWO0_MC1_MARK, PORT260_FN4), | ||
1010 | PINMUX_DATA(SDHID1_2_MARK, PORT261_FN1), | ||
1011 | PINMUX_DATA(M10_SLCD_CK2_MARK, PORT261_FN2), | ||
1012 | PINMUX_DATA(TS_SDEN2_MARK, PORT261_FN3), | ||
1013 | PINMUX_DATA(TDI3_MARK, PORT261_FN4), | ||
1014 | PINMUX_DATA(SDHID1_3_MARK, PORT262_FN1), | ||
1015 | PINMUX_DATA(M12_SLCD_CE2_MARK, PORT262_FN2), | ||
1016 | PINMUX_DATA(TS_SCK2_MARK, PORT262_FN3), | ||
1017 | PINMUX_DATA(RTCK3_SWO1_MC1_MARK, PORT262_FN4), | ||
1018 | PINMUX_DATA(SDHICMD1_MARK, PORT263_FN1), | ||
1019 | PINMUX_DATA(TRST3_MARK, PORT263_FN2), | ||
1020 | PINMUX_DATA(RESETOUTS_MARK, PORT264_FN1), | ||
1021 | }; | ||
1022 | |||
1023 | static struct pinmux_gpio pinmux_gpios[] = { | ||
1024 | /* 55-1 -> 55-5 (GPIO) */ | ||
1025 | GPIO_PORT_ALL(), | ||
1026 | |||
1027 | /* Special Pull-up / Pull-down Functions */ | ||
1028 | GPIO_FN(PORT66_KEYIN0_PU), GPIO_FN(PORT67_KEYIN1_PU), | ||
1029 | GPIO_FN(PORT68_KEYIN2_PU), GPIO_FN(PORT69_KEYIN3_PU), | ||
1030 | GPIO_FN(PORT70_KEYIN4_PU), GPIO_FN(PORT71_KEYIN5_PU), | ||
1031 | GPIO_FN(PORT72_KEYIN6_PU), | ||
1032 | |||
1033 | /* 55-1 (FN) */ | ||
1034 | GPIO_FN(VBUS_0), | ||
1035 | GPIO_FN(CPORT0), | ||
1036 | GPIO_FN(CPORT1), | ||
1037 | GPIO_FN(CPORT2), | ||
1038 | GPIO_FN(CPORT3), | ||
1039 | GPIO_FN(CPORT4), | ||
1040 | GPIO_FN(CPORT5), | ||
1041 | GPIO_FN(CPORT6), | ||
1042 | GPIO_FN(CPORT7), | ||
1043 | GPIO_FN(CPORT8), | ||
1044 | GPIO_FN(CPORT9), | ||
1045 | GPIO_FN(CPORT10), | ||
1046 | GPIO_FN(CPORT11), GPIO_FN(SIN2), | ||
1047 | GPIO_FN(CPORT12), GPIO_FN(XCTS2), | ||
1048 | GPIO_FN(CPORT13), GPIO_FN(RFSPO4), | ||
1049 | GPIO_FN(CPORT14), GPIO_FN(RFSPO5), | ||
1050 | GPIO_FN(CPORT15), GPIO_FN(SCIFA0_SCK), GPIO_FN(GPS_AGC2), | ||
1051 | GPIO_FN(CPORT16), GPIO_FN(SCIFA0_TXD), GPIO_FN(GPS_AGC3), | ||
1052 | GPIO_FN(CPORT17_IC_OE), GPIO_FN(SOUT2), | ||
1053 | GPIO_FN(CPORT18), GPIO_FN(XRTS2), GPIO_FN(PORT19_VIO_CKO2), | ||
1054 | GPIO_FN(CPORT19_MPORT1), | ||
1055 | GPIO_FN(CPORT20), GPIO_FN(RFSPO6), | ||
1056 | GPIO_FN(CPORT21), GPIO_FN(STATUS0), | ||
1057 | GPIO_FN(CPORT22), GPIO_FN(STATUS1), | ||
1058 | GPIO_FN(CPORT23), GPIO_FN(STATUS2), GPIO_FN(RFSPO7), | ||
1059 | GPIO_FN(B_SYNLD1), | ||
1060 | GPIO_FN(B_SYNLD2), GPIO_FN(SYSENMSK), | ||
1061 | GPIO_FN(XMAINPS), | ||
1062 | GPIO_FN(XDIVPS), | ||
1063 | GPIO_FN(XIDRST), | ||
1064 | GPIO_FN(IDCLK), GPIO_FN(IC_DP), | ||
1065 | GPIO_FN(IDIO), GPIO_FN(IC_DM), | ||
1066 | GPIO_FN(SOUT1), GPIO_FN(SCIFA4_TXD), GPIO_FN(M02_BERDAT), | ||
1067 | GPIO_FN(SIN1), GPIO_FN(SCIFA4_RXD), GPIO_FN(XWUP), | ||
1068 | GPIO_FN(XRTS1), GPIO_FN(SCIFA4_RTS), GPIO_FN(M03_BERCLK), | ||
1069 | GPIO_FN(XCTS1), GPIO_FN(SCIFA4_CTS), | ||
1070 | GPIO_FN(PCMCLKO), | ||
1071 | GPIO_FN(SYNC8KO), | ||
1072 | |||
1073 | /* 55-2 (FN) */ | ||
1074 | GPIO_FN(DNPCM_A), | ||
1075 | GPIO_FN(UPPCM_A), | ||
1076 | GPIO_FN(VACK), | ||
1077 | GPIO_FN(XTALB1L), | ||
1078 | GPIO_FN(GPS_AGC1), GPIO_FN(SCIFA0_RTS), | ||
1079 | GPIO_FN(GPS_AGC4), GPIO_FN(SCIFA0_RXD), | ||
1080 | GPIO_FN(GPS_PWRDOWN), GPIO_FN(SCIFA0_CTS), | ||
1081 | GPIO_FN(GPS_IM), | ||
1082 | GPIO_FN(GPS_IS), | ||
1083 | GPIO_FN(GPS_QM), | ||
1084 | GPIO_FN(GPS_QS), | ||
1085 | GPIO_FN(FMSOCK), GPIO_FN(PORT49_IRDA_OUT), GPIO_FN(PORT49_IROUT), | ||
1086 | GPIO_FN(FMSOOLR), GPIO_FN(BBIF2_TSYNC2), GPIO_FN(TPU2TO2), | ||
1087 | GPIO_FN(IPORT3), GPIO_FN(FMSIOLR), | ||
1088 | GPIO_FN(FMSOOBT), GPIO_FN(BBIF2_TSCK2), GPIO_FN(TPU2TO3), | ||
1089 | GPIO_FN(OPORT1), GPIO_FN(FMSIOBT), | ||
1090 | GPIO_FN(FMSOSLD), GPIO_FN(BBIF2_TXD2), GPIO_FN(OPORT2), | ||
1091 | GPIO_FN(FMSOILR), GPIO_FN(PORT53_IRDA_IN), GPIO_FN(TPU3TO3), | ||
1092 | GPIO_FN(OPORT3), GPIO_FN(FMSIILR), | ||
1093 | GPIO_FN(FMSOIBT), GPIO_FN(PORT54_IRDA_FIRSEL), GPIO_FN(TPU3TO2), | ||
1094 | GPIO_FN(FMSIIBT), | ||
1095 | GPIO_FN(FMSISLD), GPIO_FN(MFG0_OUT1), GPIO_FN(TPU0TO0), | ||
1096 | GPIO_FN(A0_EA0), GPIO_FN(BS), | ||
1097 | GPIO_FN(A12_EA12), GPIO_FN(PORT58_VIO_CKOR), GPIO_FN(TPU4TO2), | ||
1098 | GPIO_FN(A13_EA13), GPIO_FN(PORT59_IROUT), GPIO_FN(MFG0_OUT2), | ||
1099 | GPIO_FN(TPU0TO1), | ||
1100 | GPIO_FN(A14_EA14), GPIO_FN(PORT60_KEYOUT5), | ||
1101 | GPIO_FN(A15_EA15), GPIO_FN(PORT61_KEYOUT4), | ||
1102 | GPIO_FN(A16_EA16), GPIO_FN(PORT62_KEYOUT3), GPIO_FN(MSIOF0_SS1), | ||
1103 | GPIO_FN(A17_EA17), GPIO_FN(PORT63_KEYOUT2), GPIO_FN(MSIOF0_TSYNC), | ||
1104 | GPIO_FN(A18_EA18), GPIO_FN(PORT64_KEYOUT1), GPIO_FN(MSIOF0_TSCK), | ||
1105 | GPIO_FN(A19_EA19), GPIO_FN(PORT65_KEYOUT0), GPIO_FN(MSIOF0_TXD), | ||
1106 | GPIO_FN(A20_EA20), GPIO_FN(PORT66_KEYIN0), GPIO_FN(MSIOF0_RSCK), | ||
1107 | GPIO_FN(A21_EA21), GPIO_FN(PORT67_KEYIN1), GPIO_FN(MSIOF0_RSYNC), | ||
1108 | GPIO_FN(A22_EA22), GPIO_FN(PORT68_KEYIN2), GPIO_FN(MSIOF0_MCK0), | ||
1109 | GPIO_FN(A23_EA23), GPIO_FN(PORT69_KEYIN3), GPIO_FN(MSIOF0_MCK1), | ||
1110 | GPIO_FN(A24_EA24), GPIO_FN(PORT70_KEYIN4), GPIO_FN(MSIOF0_RXD), | ||
1111 | GPIO_FN(A25_EA25), GPIO_FN(PORT71_KEYIN5), GPIO_FN(MSIOF0_SS2), | ||
1112 | GPIO_FN(A26), GPIO_FN(PORT72_KEYIN6), | ||
1113 | GPIO_FN(D0_ED0_NAF0), | ||
1114 | GPIO_FN(D1_ED1_NAF1), | ||
1115 | GPIO_FN(D2_ED2_NAF2), | ||
1116 | GPIO_FN(D3_ED3_NAF3), | ||
1117 | GPIO_FN(D4_ED4_NAF4), | ||
1118 | GPIO_FN(D5_ED5_NAF5), | ||
1119 | GPIO_FN(D6_ED6_NAF6), | ||
1120 | GPIO_FN(D7_ED7_NAF7), | ||
1121 | GPIO_FN(D8_ED8_NAF8), | ||
1122 | GPIO_FN(D9_ED9_NAF9), | ||
1123 | GPIO_FN(D10_ED10_NAF10), | ||
1124 | GPIO_FN(D11_ED11_NAF11), | ||
1125 | GPIO_FN(D12_ED12_NAF12), | ||
1126 | GPIO_FN(D13_ED13_NAF13), | ||
1127 | GPIO_FN(D14_ED14_NAF14), | ||
1128 | GPIO_FN(D15_ED15_NAF15), | ||
1129 | GPIO_FN(CS4), | ||
1130 | GPIO_FN(CS5A), GPIO_FN(FMSICK), | ||
1131 | |||
1132 | /* 55-3 (FN) */ | ||
1133 | GPIO_FN(CS5B), GPIO_FN(FCE1), | ||
1134 | GPIO_FN(CS6B), GPIO_FN(XCS2), GPIO_FN(CS6A), GPIO_FN(DACK0), | ||
1135 | GPIO_FN(FCE0), | ||
1136 | GPIO_FN(WAIT), GPIO_FN(DREQ0), | ||
1137 | GPIO_FN(RD_XRD), | ||
1138 | GPIO_FN(WE0_XWR0_FWE), | ||
1139 | GPIO_FN(WE1_XWR1), | ||
1140 | GPIO_FN(FRB), | ||
1141 | GPIO_FN(CKO), | ||
1142 | GPIO_FN(NBRSTOUT), | ||
1143 | GPIO_FN(NBRST), | ||
1144 | GPIO_FN(GPS_EPPSIN), | ||
1145 | GPIO_FN(LATCHPULSE), | ||
1146 | GPIO_FN(LTESIGNAL), | ||
1147 | GPIO_FN(LEGACYSTATE), | ||
1148 | GPIO_FN(TCKON), | ||
1149 | GPIO_FN(VIO_VD), GPIO_FN(PORT128_KEYOUT0), GPIO_FN(IPORT0), | ||
1150 | GPIO_FN(VIO_HD), GPIO_FN(PORT129_KEYOUT1), GPIO_FN(IPORT1), | ||
1151 | GPIO_FN(VIO_D0), GPIO_FN(PORT130_KEYOUT2), GPIO_FN(PORT130_MSIOF2_RXD), | ||
1152 | GPIO_FN(VIO_D1), GPIO_FN(PORT131_KEYOUT3), GPIO_FN(PORT131_MSIOF2_SS1), | ||
1153 | GPIO_FN(VIO_D2), GPIO_FN(PORT132_KEYOUT4), GPIO_FN(PORT132_MSIOF2_SS2), | ||
1154 | GPIO_FN(VIO_D3), GPIO_FN(PORT133_KEYOUT5), | ||
1155 | GPIO_FN(PORT133_MSIOF2_TSYNC), | ||
1156 | GPIO_FN(VIO_D4), GPIO_FN(PORT134_KEYIN0), GPIO_FN(PORT134_MSIOF2_TXD), | ||
1157 | GPIO_FN(VIO_D5), GPIO_FN(PORT135_KEYIN1), GPIO_FN(PORT135_MSIOF2_TSCK), | ||
1158 | GPIO_FN(VIO_D6), GPIO_FN(PORT136_KEYIN2), | ||
1159 | GPIO_FN(VIO_D7), GPIO_FN(PORT137_KEYIN3), | ||
1160 | GPIO_FN(VIO_D8), GPIO_FN(M9_SLCD_A01), GPIO_FN(PORT138_FSIAOMC), | ||
1161 | GPIO_FN(VIO_D9), GPIO_FN(M10_SLCD_CK1), GPIO_FN(PORT139_FSIAOLR), | ||
1162 | GPIO_FN(VIO_D10), GPIO_FN(M11_SLCD_SO1), GPIO_FN(TPU0TO2), | ||
1163 | GPIO_FN(PORT140_FSIAOBT), | ||
1164 | GPIO_FN(VIO_D11), GPIO_FN(M12_SLCD_CE1), GPIO_FN(TPU0TO3), | ||
1165 | GPIO_FN(PORT141_FSIAOSLD), | ||
1166 | GPIO_FN(VIO_D12), GPIO_FN(M13_BSW), GPIO_FN(PORT142_FSIACK), | ||
1167 | GPIO_FN(VIO_D13), GPIO_FN(M14_GSW), GPIO_FN(PORT143_FSIAILR), | ||
1168 | GPIO_FN(VIO_D14), GPIO_FN(M15_RSW), GPIO_FN(PORT144_FSIAIBT), | ||
1169 | GPIO_FN(VIO_D15), GPIO_FN(TPU1TO3), GPIO_FN(PORT145_FSIAISLD), | ||
1170 | GPIO_FN(VIO_CLK), GPIO_FN(PORT146_KEYIN4), GPIO_FN(IPORT2), | ||
1171 | GPIO_FN(VIO_FIELD), GPIO_FN(PORT147_KEYIN5), | ||
1172 | GPIO_FN(VIO_CKO), GPIO_FN(PORT148_KEYIN6), | ||
1173 | GPIO_FN(A27), GPIO_FN(RDWR_XWE), GPIO_FN(MFG0_IN1), | ||
1174 | GPIO_FN(MFG0_IN2), | ||
1175 | GPIO_FN(TS_SPSYNC3), GPIO_FN(MSIOF2_RSCK), | ||
1176 | GPIO_FN(TS_SDAT3), GPIO_FN(MSIOF2_RSYNC), | ||
1177 | GPIO_FN(TPU1TO2), GPIO_FN(TS_SDEN3), GPIO_FN(PORT153_MSIOF2_SS1), | ||
1178 | GPIO_FN(SOUT3), GPIO_FN(SCIFA2_TXD1), GPIO_FN(MSIOF2_MCK0), | ||
1179 | GPIO_FN(SIN3), GPIO_FN(SCIFA2_RXD1), GPIO_FN(MSIOF2_MCK1), | ||
1180 | GPIO_FN(XRTS3), GPIO_FN(SCIFA2_RTS1), GPIO_FN(PORT156_MSIOF2_SS2), | ||
1181 | GPIO_FN(XCTS3), GPIO_FN(SCIFA2_CTS1), GPIO_FN(PORT157_MSIOF2_RXD), | ||
1182 | |||
1183 | /* 55-4 (FN) */ | ||
1184 | GPIO_FN(DINT), GPIO_FN(SCIFA2_SCK1), GPIO_FN(TS_SCK3), | ||
1185 | GPIO_FN(PORT159_SCIFB_SCK), GPIO_FN(PORT159_SCIFA5_SCK), GPIO_FN(NMI), | ||
1186 | GPIO_FN(PORT160_SCIFB_TXD), GPIO_FN(PORT160_SCIFA5_TXD), GPIO_FN(SOUT0), | ||
1187 | GPIO_FN(PORT161_SCIFB_CTS), GPIO_FN(PORT161_SCIFA5_CTS), GPIO_FN(XCTS0), | ||
1188 | GPIO_FN(MFG3_IN2), | ||
1189 | GPIO_FN(PORT162_SCIFB_RXD), GPIO_FN(PORT162_SCIFA5_RXD), GPIO_FN(SIN0), | ||
1190 | GPIO_FN(MFG3_IN1), | ||
1191 | GPIO_FN(PORT163_SCIFB_RTS), GPIO_FN(PORT163_SCIFA5_RTS), GPIO_FN(XRTS0), | ||
1192 | GPIO_FN(MFG3_OUT1), GPIO_FN(TPU3TO0), | ||
1193 | GPIO_FN(LCDD0), GPIO_FN(PORT192_KEYOUT0), GPIO_FN(EXT_CKI), | ||
1194 | GPIO_FN(LCDD1), GPIO_FN(PORT193_KEYOUT1), GPIO_FN(PORT193_SCIFA5_CTS), | ||
1195 | GPIO_FN(BBIF2_TSYNC1), | ||
1196 | GPIO_FN(LCDD2), GPIO_FN(PORT194_KEYOUT2), GPIO_FN(PORT194_SCIFA5_RTS), | ||
1197 | GPIO_FN(BBIF2_TSCK1), | ||
1198 | GPIO_FN(LCDD3), GPIO_FN(PORT195_KEYOUT3), GPIO_FN(PORT195_SCIFA5_RXD), | ||
1199 | GPIO_FN(BBIF2_TXD1), | ||
1200 | GPIO_FN(LCDD4), GPIO_FN(PORT196_KEYOUT4), GPIO_FN(PORT196_SCIFA5_TXD), | ||
1201 | GPIO_FN(LCDD5), GPIO_FN(PORT197_KEYOUT5), GPIO_FN(PORT197_SCIFA5_SCK), | ||
1202 | GPIO_FN(MFG2_OUT2), | ||
1203 | GPIO_FN(LCDD6), | ||
1204 | GPIO_FN(LCDD7), GPIO_FN(TPU4TO1), GPIO_FN(MFG4_OUT2), | ||
1205 | GPIO_FN(LCDD8), GPIO_FN(PORT200_KEYIN0), GPIO_FN(VIO_DR0), | ||
1206 | GPIO_FN(D16), | ||
1207 | GPIO_FN(LCDD9), GPIO_FN(PORT201_KEYIN1), GPIO_FN(VIO_DR1), | ||
1208 | GPIO_FN(D17), | ||
1209 | GPIO_FN(LCDD10), GPIO_FN(PORT202_KEYIN2), GPIO_FN(VIO_DR2), | ||
1210 | GPIO_FN(D18), | ||
1211 | GPIO_FN(LCDD11), GPIO_FN(PORT203_KEYIN3), GPIO_FN(VIO_DR3), | ||
1212 | GPIO_FN(D19), | ||
1213 | GPIO_FN(LCDD12), GPIO_FN(PORT204_KEYIN4), GPIO_FN(VIO_DR4), | ||
1214 | GPIO_FN(D20), | ||
1215 | GPIO_FN(LCDD13), GPIO_FN(PORT205_KEYIN5), GPIO_FN(VIO_DR5), | ||
1216 | GPIO_FN(D21), | ||
1217 | GPIO_FN(LCDD14), GPIO_FN(PORT206_KEYIN6), GPIO_FN(VIO_DR6), | ||
1218 | GPIO_FN(D22), | ||
1219 | GPIO_FN(LCDD15), GPIO_FN(PORT207_MSIOF0L_SS1), GPIO_FN(PORT207_KEYOUT0), | ||
1220 | GPIO_FN(VIO_DR7), GPIO_FN(D23), | ||
1221 | GPIO_FN(LCDD16), GPIO_FN(PORT208_MSIOF0L_SS2), GPIO_FN(PORT208_KEYOUT1), | ||
1222 | GPIO_FN(VIO_VDR), GPIO_FN(D24), | ||
1223 | GPIO_FN(LCDD17), GPIO_FN(PORT209_KEYOUT2), GPIO_FN(VIO_HDR), | ||
1224 | GPIO_FN(D25), | ||
1225 | GPIO_FN(LCDD18), GPIO_FN(DREQ2), GPIO_FN(PORT210_MSIOF0L_SS1), | ||
1226 | GPIO_FN(D26), | ||
1227 | GPIO_FN(LCDD19), GPIO_FN(PORT211_MSIOF0L_SS2), GPIO_FN(D27), | ||
1228 | GPIO_FN(LCDD20), GPIO_FN(TS_SPSYNC1), GPIO_FN(MSIOF0L_MCK0), | ||
1229 | GPIO_FN(D28), | ||
1230 | GPIO_FN(LCDD21), GPIO_FN(TS_SDAT1), GPIO_FN(MSIOF0L_MCK1), | ||
1231 | GPIO_FN(D29), | ||
1232 | GPIO_FN(LCDD22), GPIO_FN(TS_SDEN1), GPIO_FN(MSIOF0L_RSCK), | ||
1233 | GPIO_FN(D30), | ||
1234 | GPIO_FN(LCDD23), GPIO_FN(TS_SCK1), GPIO_FN(MSIOF0L_RSYNC), | ||
1235 | GPIO_FN(D31), | ||
1236 | GPIO_FN(LCDDCK), GPIO_FN(LCDWR), GPIO_FN(PORT216_KEYOUT3), | ||
1237 | GPIO_FN(VIO_CLKR), | ||
1238 | GPIO_FN(LCDRD), GPIO_FN(DACK2), GPIO_FN(MSIOF0L_TSYNC), | ||
1239 | GPIO_FN(LCDHSYN), GPIO_FN(LCDCS), GPIO_FN(LCDCS2), GPIO_FN(DACK3), | ||
1240 | GPIO_FN(PORT218_VIO_CKOR), GPIO_FN(PORT218_KEYOUT4), | ||
1241 | GPIO_FN(LCDDISP), GPIO_FN(LCDRS), GPIO_FN(DREQ3), GPIO_FN(MSIOF0L_TSCK), | ||
1242 | GPIO_FN(LCDVSYN), GPIO_FN(LCDVSYN2), GPIO_FN(PORT220_KEYOUT5), | ||
1243 | GPIO_FN(LCDLCLK), GPIO_FN(DREQ1), GPIO_FN(PWEN), GPIO_FN(MSIOF0L_RXD), | ||
1244 | GPIO_FN(LCDDON), GPIO_FN(LCDDON2), GPIO_FN(DACK1), GPIO_FN(OVCN), | ||
1245 | GPIO_FN(MSIOF0L_TXD), | ||
1246 | GPIO_FN(SCIFA1_TXD), GPIO_FN(OVCN2), | ||
1247 | GPIO_FN(EXTLP), GPIO_FN(SCIFA1_SCK), GPIO_FN(USBTERM), | ||
1248 | GPIO_FN(PORT226_VIO_CKO2), | ||
1249 | GPIO_FN(SCIFA1_RTS), GPIO_FN(IDIN), | ||
1250 | GPIO_FN(SCIFA1_RXD), | ||
1251 | GPIO_FN(SCIFA1_CTS), GPIO_FN(MFG1_IN1), | ||
1252 | GPIO_FN(MSIOF1_TXD), GPIO_FN(SCIFA2_TXD2), GPIO_FN(PORT230_FSIAOMC), | ||
1253 | GPIO_FN(MSIOF1_TSYNC), GPIO_FN(SCIFA2_CTS2), GPIO_FN(PORT231_FSIAOLR), | ||
1254 | GPIO_FN(MSIOF1_TSCK), GPIO_FN(SCIFA2_SCK2), GPIO_FN(PORT232_FSIAOBT), | ||
1255 | GPIO_FN(MSIOF1_RXD), GPIO_FN(SCIFA2_RXD2), GPIO_FN(GPS_VCOTRIG), | ||
1256 | GPIO_FN(PORT233_FSIACK), | ||
1257 | GPIO_FN(MSIOF1_RSCK), GPIO_FN(SCIFA2_RTS2), GPIO_FN(PORT234_FSIAOSLD), | ||
1258 | GPIO_FN(MSIOF1_RSYNC), GPIO_FN(OPORT0), GPIO_FN(MFG1_IN2), | ||
1259 | GPIO_FN(PORT235_FSIAILR), | ||
1260 | GPIO_FN(MSIOF1_MCK0), GPIO_FN(I2C_SDA2), GPIO_FN(PORT236_FSIAIBT), | ||
1261 | GPIO_FN(MSIOF1_MCK1), GPIO_FN(I2C_SCL2), GPIO_FN(PORT237_FSIAISLD), | ||
1262 | GPIO_FN(MSIOF1_SS1), GPIO_FN(EDBGREQ3), | ||
1263 | |||
1264 | /* 55-5 (FN) */ | ||
1265 | GPIO_FN(MSIOF1_SS2), | ||
1266 | GPIO_FN(SCIFA6_TXD), | ||
1267 | GPIO_FN(PORT241_IRDA_OUT), GPIO_FN(PORT241_IROUT), GPIO_FN(MFG4_OUT1), | ||
1268 | GPIO_FN(TPU4TO0), | ||
1269 | GPIO_FN(PORT242_IRDA_IN), GPIO_FN(MFG4_IN2), | ||
1270 | GPIO_FN(PORT243_IRDA_FIRSEL), GPIO_FN(PORT243_VIO_CKO2), | ||
1271 | GPIO_FN(PORT244_SCIFA5_CTS), GPIO_FN(MFG2_IN1), | ||
1272 | GPIO_FN(PORT244_SCIFB_CTS), | ||
1273 | GPIO_FN(PORT245_SCIFA5_RTS), GPIO_FN(MFG2_IN2), | ||
1274 | GPIO_FN(PORT245_SCIFB_RTS), | ||
1275 | GPIO_FN(PORT246_SCIFA5_RXD), GPIO_FN(MFG1_OUT1), | ||
1276 | GPIO_FN(PORT246_SCIFB_RXD), GPIO_FN(TPU1TO0), | ||
1277 | GPIO_FN(PORT247_SCIFA5_TXD), GPIO_FN(MFG3_OUT2), | ||
1278 | GPIO_FN(PORT247_SCIFB_TXD), GPIO_FN(TPU3TO1), | ||
1279 | GPIO_FN(PORT248_SCIFA5_SCK), GPIO_FN(MFG2_OUT1), | ||
1280 | GPIO_FN(PORT248_SCIFB_SCK), GPIO_FN(TPU2TO0), | ||
1281 | GPIO_FN(PORT249_IROUT), GPIO_FN(MFG4_IN1), | ||
1282 | GPIO_FN(SDHICLK0), GPIO_FN(TCK2_SWCLK_MC0), | ||
1283 | GPIO_FN(SDHICD0), | ||
1284 | GPIO_FN(SDHID0_0), GPIO_FN(TMS2_SWDIO_MC0), | ||
1285 | GPIO_FN(SDHID0_1), GPIO_FN(TDO2_SWO0_MC0), | ||
1286 | GPIO_FN(SDHID0_2), GPIO_FN(TDI2), | ||
1287 | GPIO_FN(SDHID0_3), GPIO_FN(RTCK2_SWO1_MC0), | ||
1288 | GPIO_FN(SDHICMD0), GPIO_FN(TRST2), | ||
1289 | GPIO_FN(SDHIWP0), GPIO_FN(EDBGREQ2), | ||
1290 | GPIO_FN(SDHICLK1), GPIO_FN(TCK3_SWCLK_MC1), | ||
1291 | GPIO_FN(SDHID1_0), GPIO_FN(M11_SLCD_SO2), GPIO_FN(TS_SPSYNC2), | ||
1292 | GPIO_FN(TMS3_SWDIO_MC1), | ||
1293 | GPIO_FN(SDHID1_1), GPIO_FN(M9_SLCD_A02), GPIO_FN(TS_SDAT2), | ||
1294 | GPIO_FN(TDO3_SWO0_MC1), | ||
1295 | GPIO_FN(SDHID1_2), GPIO_FN(M10_SLCD_CK2), GPIO_FN(TS_SDEN2), | ||
1296 | GPIO_FN(TDI3), | ||
1297 | GPIO_FN(SDHID1_3), GPIO_FN(M12_SLCD_CE2), GPIO_FN(TS_SCK2), | ||
1298 | GPIO_FN(RTCK3_SWO1_MC1), | ||
1299 | GPIO_FN(SDHICMD1), GPIO_FN(TRST3), | ||
1300 | GPIO_FN(RESETOUTS), | ||
1301 | }; | ||
1302 | |||
1303 | static struct pinmux_cfg_reg pinmux_config_regs[] = { | ||
1304 | PORTCR(0, 0xe6050000), /* PORT0CR */ | ||
1305 | PORTCR(1, 0xe6050001), /* PORT1CR */ | ||
1306 | PORTCR(2, 0xe6050002), /* PORT2CR */ | ||
1307 | PORTCR(3, 0xe6050003), /* PORT3CR */ | ||
1308 | PORTCR(4, 0xe6050004), /* PORT4CR */ | ||
1309 | PORTCR(5, 0xe6050005), /* PORT5CR */ | ||
1310 | PORTCR(6, 0xe6050006), /* PORT6CR */ | ||
1311 | PORTCR(7, 0xe6050007), /* PORT7CR */ | ||
1312 | PORTCR(8, 0xe6050008), /* PORT8CR */ | ||
1313 | PORTCR(9, 0xe6050009), /* PORT9CR */ | ||
1314 | |||
1315 | PORTCR(10, 0xe605000a), /* PORT10CR */ | ||
1316 | PORTCR(11, 0xe605000b), /* PORT11CR */ | ||
1317 | PORTCR(12, 0xe605000c), /* PORT12CR */ | ||
1318 | PORTCR(13, 0xe605000d), /* PORT13CR */ | ||
1319 | PORTCR(14, 0xe605000e), /* PORT14CR */ | ||
1320 | PORTCR(15, 0xe605000f), /* PORT15CR */ | ||
1321 | PORTCR(16, 0xe6050010), /* PORT16CR */ | ||
1322 | PORTCR(17, 0xe6050011), /* PORT17CR */ | ||
1323 | PORTCR(18, 0xe6050012), /* PORT18CR */ | ||
1324 | PORTCR(19, 0xe6050013), /* PORT19CR */ | ||
1325 | |||
1326 | PORTCR(20, 0xe6050014), /* PORT20CR */ | ||
1327 | PORTCR(21, 0xe6050015), /* PORT21CR */ | ||
1328 | PORTCR(22, 0xe6050016), /* PORT22CR */ | ||
1329 | PORTCR(23, 0xe6050017), /* PORT23CR */ | ||
1330 | PORTCR(24, 0xe6050018), /* PORT24CR */ | ||
1331 | PORTCR(25, 0xe6050019), /* PORT25CR */ | ||
1332 | PORTCR(26, 0xe605001a), /* PORT26CR */ | ||
1333 | PORTCR(27, 0xe605001b), /* PORT27CR */ | ||
1334 | PORTCR(28, 0xe605001c), /* PORT28CR */ | ||
1335 | PORTCR(29, 0xe605001d), /* PORT29CR */ | ||
1336 | |||
1337 | PORTCR(30, 0xe605001e), /* PORT30CR */ | ||
1338 | PORTCR(31, 0xe605001f), /* PORT31CR */ | ||
1339 | PORTCR(32, 0xe6050020), /* PORT32CR */ | ||
1340 | PORTCR(33, 0xe6050021), /* PORT33CR */ | ||
1341 | PORTCR(34, 0xe6050022), /* PORT34CR */ | ||
1342 | PORTCR(35, 0xe6050023), /* PORT35CR */ | ||
1343 | PORTCR(36, 0xe6050024), /* PORT36CR */ | ||
1344 | PORTCR(37, 0xe6050025), /* PORT37CR */ | ||
1345 | PORTCR(38, 0xe6050026), /* PORT38CR */ | ||
1346 | PORTCR(39, 0xe6050027), /* PORT39CR */ | ||
1347 | |||
1348 | PORTCR(40, 0xe6050028), /* PORT40CR */ | ||
1349 | PORTCR(41, 0xe6050029), /* PORT41CR */ | ||
1350 | PORTCR(42, 0xe605002a), /* PORT42CR */ | ||
1351 | PORTCR(43, 0xe605002b), /* PORT43CR */ | ||
1352 | PORTCR(44, 0xe605002c), /* PORT44CR */ | ||
1353 | PORTCR(45, 0xe605002d), /* PORT45CR */ | ||
1354 | PORTCR(46, 0xe605002e), /* PORT46CR */ | ||
1355 | PORTCR(47, 0xe605002f), /* PORT47CR */ | ||
1356 | PORTCR(48, 0xe6050030), /* PORT48CR */ | ||
1357 | PORTCR(49, 0xe6050031), /* PORT49CR */ | ||
1358 | |||
1359 | PORTCR(50, 0xe6050032), /* PORT50CR */ | ||
1360 | PORTCR(51, 0xe6050033), /* PORT51CR */ | ||
1361 | PORTCR(52, 0xe6050034), /* PORT52CR */ | ||
1362 | PORTCR(53, 0xe6050035), /* PORT53CR */ | ||
1363 | PORTCR(54, 0xe6050036), /* PORT54CR */ | ||
1364 | PORTCR(55, 0xe6050037), /* PORT55CR */ | ||
1365 | PORTCR(56, 0xe6050038), /* PORT56CR */ | ||
1366 | PORTCR(57, 0xe6050039), /* PORT57CR */ | ||
1367 | PORTCR(58, 0xe605003a), /* PORT58CR */ | ||
1368 | PORTCR(59, 0xe605003b), /* PORT59CR */ | ||
1369 | |||
1370 | PORTCR(60, 0xe605003c), /* PORT60CR */ | ||
1371 | PORTCR(61, 0xe605003d), /* PORT61CR */ | ||
1372 | PORTCR(62, 0xe605003e), /* PORT62CR */ | ||
1373 | PORTCR(63, 0xe605003f), /* PORT63CR */ | ||
1374 | PORTCR(64, 0xe6050040), /* PORT64CR */ | ||
1375 | PORTCR(65, 0xe6050041), /* PORT65CR */ | ||
1376 | PORTCR(66, 0xe6050042), /* PORT66CR */ | ||
1377 | PORTCR(67, 0xe6050043), /* PORT67CR */ | ||
1378 | PORTCR(68, 0xe6050044), /* PORT68CR */ | ||
1379 | PORTCR(69, 0xe6050045), /* PORT69CR */ | ||
1380 | |||
1381 | PORTCR(70, 0xe6050046), /* PORT70CR */ | ||
1382 | PORTCR(71, 0xe6050047), /* PORT71CR */ | ||
1383 | PORTCR(72, 0xe6050048), /* PORT72CR */ | ||
1384 | PORTCR(73, 0xe6050049), /* PORT73CR */ | ||
1385 | PORTCR(74, 0xe605004a), /* PORT74CR */ | ||
1386 | PORTCR(75, 0xe605004b), /* PORT75CR */ | ||
1387 | PORTCR(76, 0xe605004c), /* PORT76CR */ | ||
1388 | PORTCR(77, 0xe605004d), /* PORT77CR */ | ||
1389 | PORTCR(78, 0xe605004e), /* PORT78CR */ | ||
1390 | PORTCR(79, 0xe605004f), /* PORT79CR */ | ||
1391 | |||
1392 | PORTCR(80, 0xe6050050), /* PORT80CR */ | ||
1393 | PORTCR(81, 0xe6050051), /* PORT81CR */ | ||
1394 | PORTCR(82, 0xe6050052), /* PORT82CR */ | ||
1395 | PORTCR(83, 0xe6050053), /* PORT83CR */ | ||
1396 | PORTCR(84, 0xe6050054), /* PORT84CR */ | ||
1397 | PORTCR(85, 0xe6050055), /* PORT85CR */ | ||
1398 | PORTCR(86, 0xe6050056), /* PORT86CR */ | ||
1399 | PORTCR(87, 0xe6050057), /* PORT87CR */ | ||
1400 | PORTCR(88, 0xe6050058), /* PORT88CR */ | ||
1401 | PORTCR(89, 0xe6050059), /* PORT89CR */ | ||
1402 | |||
1403 | PORTCR(90, 0xe605005a), /* PORT90CR */ | ||
1404 | PORTCR(91, 0xe605005b), /* PORT91CR */ | ||
1405 | PORTCR(92, 0xe605005c), /* PORT92CR */ | ||
1406 | PORTCR(93, 0xe605005d), /* PORT93CR */ | ||
1407 | PORTCR(94, 0xe605005e), /* PORT94CR */ | ||
1408 | PORTCR(95, 0xe605005f), /* PORT95CR */ | ||
1409 | PORTCR(96, 0xe6050060), /* PORT96CR */ | ||
1410 | PORTCR(97, 0xe6050061), /* PORT97CR */ | ||
1411 | PORTCR(98, 0xe6050062), /* PORT98CR */ | ||
1412 | PORTCR(99, 0xe6050063), /* PORT99CR */ | ||
1413 | |||
1414 | PORTCR(100, 0xe6050064), /* PORT100CR */ | ||
1415 | PORTCR(101, 0xe6050065), /* PORT101CR */ | ||
1416 | PORTCR(102, 0xe6050066), /* PORT102CR */ | ||
1417 | PORTCR(103, 0xe6050067), /* PORT103CR */ | ||
1418 | PORTCR(104, 0xe6050068), /* PORT104CR */ | ||
1419 | PORTCR(105, 0xe6050069), /* PORT105CR */ | ||
1420 | PORTCR(106, 0xe605006a), /* PORT106CR */ | ||
1421 | PORTCR(107, 0xe605006b), /* PORT107CR */ | ||
1422 | PORTCR(108, 0xe605006c), /* PORT108CR */ | ||
1423 | PORTCR(109, 0xe605006d), /* PORT109CR */ | ||
1424 | |||
1425 | PORTCR(110, 0xe605006e), /* PORT110CR */ | ||
1426 | PORTCR(111, 0xe605006f), /* PORT111CR */ | ||
1427 | PORTCR(112, 0xe6050070), /* PORT112CR */ | ||
1428 | PORTCR(113, 0xe6050071), /* PORT113CR */ | ||
1429 | PORTCR(114, 0xe6050072), /* PORT114CR */ | ||
1430 | PORTCR(115, 0xe6050073), /* PORT115CR */ | ||
1431 | PORTCR(116, 0xe6050074), /* PORT116CR */ | ||
1432 | PORTCR(117, 0xe6050075), /* PORT117CR */ | ||
1433 | PORTCR(118, 0xe6050076), /* PORT118CR */ | ||
1434 | |||
1435 | PORTCR(128, 0xe6051080), /* PORT128CR */ | ||
1436 | PORTCR(129, 0xe6051081), /* PORT129CR */ | ||
1437 | |||
1438 | PORTCR(130, 0xe6051082), /* PORT130CR */ | ||
1439 | PORTCR(131, 0xe6051083), /* PORT131CR */ | ||
1440 | PORTCR(132, 0xe6051084), /* PORT132CR */ | ||
1441 | PORTCR(133, 0xe6051085), /* PORT133CR */ | ||
1442 | PORTCR(134, 0xe6051086), /* PORT134CR */ | ||
1443 | PORTCR(135, 0xe6051087), /* PORT135CR */ | ||
1444 | PORTCR(136, 0xe6051088), /* PORT136CR */ | ||
1445 | PORTCR(137, 0xe6051089), /* PORT137CR */ | ||
1446 | PORTCR(138, 0xe605108a), /* PORT138CR */ | ||
1447 | PORTCR(139, 0xe605108b), /* PORT139CR */ | ||
1448 | |||
1449 | PORTCR(140, 0xe605108c), /* PORT140CR */ | ||
1450 | PORTCR(141, 0xe605108d), /* PORT141CR */ | ||
1451 | PORTCR(142, 0xe605108e), /* PORT142CR */ | ||
1452 | PORTCR(143, 0xe605108f), /* PORT143CR */ | ||
1453 | PORTCR(144, 0xe6051090), /* PORT144CR */ | ||
1454 | PORTCR(145, 0xe6051091), /* PORT145CR */ | ||
1455 | PORTCR(146, 0xe6051092), /* PORT146CR */ | ||
1456 | PORTCR(147, 0xe6051093), /* PORT147CR */ | ||
1457 | PORTCR(148, 0xe6051094), /* PORT148CR */ | ||
1458 | PORTCR(149, 0xe6051095), /* PORT149CR */ | ||
1459 | |||
1460 | PORTCR(150, 0xe6051096), /* PORT150CR */ | ||
1461 | PORTCR(151, 0xe6051097), /* PORT151CR */ | ||
1462 | PORTCR(152, 0xe6051098), /* PORT152CR */ | ||
1463 | PORTCR(153, 0xe6051099), /* PORT153CR */ | ||
1464 | PORTCR(154, 0xe605109a), /* PORT154CR */ | ||
1465 | PORTCR(155, 0xe605109b), /* PORT155CR */ | ||
1466 | PORTCR(156, 0xe605109c), /* PORT156CR */ | ||
1467 | PORTCR(157, 0xe605109d), /* PORT157CR */ | ||
1468 | PORTCR(158, 0xe605109e), /* PORT158CR */ | ||
1469 | PORTCR(159, 0xe605109f), /* PORT159CR */ | ||
1470 | |||
1471 | PORTCR(160, 0xe60510a0), /* PORT160CR */ | ||
1472 | PORTCR(161, 0xe60510a1), /* PORT161CR */ | ||
1473 | PORTCR(162, 0xe60510a2), /* PORT162CR */ | ||
1474 | PORTCR(163, 0xe60510a3), /* PORT163CR */ | ||
1475 | PORTCR(164, 0xe60510a4), /* PORT164CR */ | ||
1476 | |||
1477 | PORTCR(192, 0xe60520c0), /* PORT192CR */ | ||
1478 | PORTCR(193, 0xe60520c1), /* PORT193CR */ | ||
1479 | PORTCR(194, 0xe60520c2), /* PORT194CR */ | ||
1480 | PORTCR(195, 0xe60520c3), /* PORT195CR */ | ||
1481 | PORTCR(196, 0xe60520c4), /* PORT196CR */ | ||
1482 | PORTCR(197, 0xe60520c5), /* PORT197CR */ | ||
1483 | PORTCR(198, 0xe60520c6), /* PORT198CR */ | ||
1484 | PORTCR(199, 0xe60520c7), /* PORT199CR */ | ||
1485 | |||
1486 | PORTCR(200, 0xe60520c8), /* PORT200CR */ | ||
1487 | PORTCR(201, 0xe60520c9), /* PORT201CR */ | ||
1488 | PORTCR(202, 0xe60520ca), /* PORT202CR */ | ||
1489 | PORTCR(203, 0xe60520cb), /* PORT203CR */ | ||
1490 | PORTCR(204, 0xe60520cc), /* PORT204CR */ | ||
1491 | PORTCR(205, 0xe60520cd), /* PORT205CR */ | ||
1492 | PORTCR(206, 0xe60520ce), /* PORT206CR */ | ||
1493 | PORTCR(207, 0xe60520cf), /* PORT207CR */ | ||
1494 | PORTCR(208, 0xe60520d0), /* PORT208CR */ | ||
1495 | PORTCR(209, 0xe60520d1), /* PORT209CR */ | ||
1496 | |||
1497 | PORTCR(210, 0xe60520d2), /* PORT210CR */ | ||
1498 | PORTCR(211, 0xe60520d3), /* PORT211CR */ | ||
1499 | PORTCR(212, 0xe60520d4), /* PORT212CR */ | ||
1500 | PORTCR(213, 0xe60520d5), /* PORT213CR */ | ||
1501 | PORTCR(214, 0xe60520d6), /* PORT214CR */ | ||
1502 | PORTCR(215, 0xe60520d7), /* PORT215CR */ | ||
1503 | PORTCR(216, 0xe60520d8), /* PORT216CR */ | ||
1504 | PORTCR(217, 0xe60520d9), /* PORT217CR */ | ||
1505 | PORTCR(218, 0xe60520da), /* PORT218CR */ | ||
1506 | PORTCR(219, 0xe60520db), /* PORT219CR */ | ||
1507 | |||
1508 | PORTCR(220, 0xe60520dc), /* PORT220CR */ | ||
1509 | PORTCR(221, 0xe60520dd), /* PORT221CR */ | ||
1510 | PORTCR(222, 0xe60520de), /* PORT222CR */ | ||
1511 | PORTCR(223, 0xe60520df), /* PORT223CR */ | ||
1512 | PORTCR(224, 0xe60520e0), /* PORT224CR */ | ||
1513 | PORTCR(225, 0xe60520e1), /* PORT225CR */ | ||
1514 | PORTCR(226, 0xe60520e2), /* PORT226CR */ | ||
1515 | PORTCR(227, 0xe60520e3), /* PORT227CR */ | ||
1516 | PORTCR(228, 0xe60520e4), /* PORT228CR */ | ||
1517 | PORTCR(229, 0xe60520e5), /* PORT229CR */ | ||
1518 | |||
1519 | PORTCR(230, 0xe60520e6), /* PORT230CR */ | ||
1520 | PORTCR(231, 0xe60520e7), /* PORT231CR */ | ||
1521 | PORTCR(232, 0xe60520e8), /* PORT232CR */ | ||
1522 | PORTCR(233, 0xe60520e9), /* PORT233CR */ | ||
1523 | PORTCR(234, 0xe60520ea), /* PORT234CR */ | ||
1524 | PORTCR(235, 0xe60520eb), /* PORT235CR */ | ||
1525 | PORTCR(236, 0xe60520ec), /* PORT236CR */ | ||
1526 | PORTCR(237, 0xe60520ed), /* PORT237CR */ | ||
1527 | PORTCR(238, 0xe60520ee), /* PORT238CR */ | ||
1528 | PORTCR(239, 0xe60520ef), /* PORT239CR */ | ||
1529 | |||
1530 | PORTCR(240, 0xe60520f0), /* PORT240CR */ | ||
1531 | PORTCR(241, 0xe60520f1), /* PORT241CR */ | ||
1532 | PORTCR(242, 0xe60520f2), /* PORT242CR */ | ||
1533 | PORTCR(243, 0xe60520f3), /* PORT243CR */ | ||
1534 | PORTCR(244, 0xe60520f4), /* PORT244CR */ | ||
1535 | PORTCR(245, 0xe60520f5), /* PORT245CR */ | ||
1536 | PORTCR(246, 0xe60520f6), /* PORT246CR */ | ||
1537 | PORTCR(247, 0xe60520f7), /* PORT247CR */ | ||
1538 | PORTCR(248, 0xe60520f8), /* PORT248CR */ | ||
1539 | PORTCR(249, 0xe60520f9), /* PORT249CR */ | ||
1540 | |||
1541 | PORTCR(250, 0xe60520fa), /* PORT250CR */ | ||
1542 | PORTCR(251, 0xe60520fb), /* PORT251CR */ | ||
1543 | PORTCR(252, 0xe60520fc), /* PORT252CR */ | ||
1544 | PORTCR(253, 0xe60520fd), /* PORT253CR */ | ||
1545 | PORTCR(254, 0xe60520fe), /* PORT254CR */ | ||
1546 | PORTCR(255, 0xe60520ff), /* PORT255CR */ | ||
1547 | PORTCR(256, 0xe6052100), /* PORT256CR */ | ||
1548 | PORTCR(257, 0xe6052101), /* PORT257CR */ | ||
1549 | PORTCR(258, 0xe6052102), /* PORT258CR */ | ||
1550 | PORTCR(259, 0xe6052103), /* PORT259CR */ | ||
1551 | |||
1552 | PORTCR(260, 0xe6052104), /* PORT260CR */ | ||
1553 | PORTCR(261, 0xe6052105), /* PORT261CR */ | ||
1554 | PORTCR(262, 0xe6052106), /* PORT262CR */ | ||
1555 | PORTCR(263, 0xe6052107), /* PORT263CR */ | ||
1556 | PORTCR(264, 0xe6052108), /* PORT264CR */ | ||
1557 | |||
1558 | { PINMUX_CFG_REG("MSELBCR", 0xe6058024, 32, 1) { | ||
1559 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1560 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1561 | MSELBCR_MSEL17_0, MSELBCR_MSEL17_1, | ||
1562 | MSELBCR_MSEL16_0, MSELBCR_MSEL16_1, | ||
1563 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | ||
1564 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } | ||
1565 | }, | ||
1566 | { }, | ||
1567 | }; | ||
1568 | |||
1569 | static struct pinmux_data_reg pinmux_data_regs[] = { | ||
1570 | { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) { | ||
1571 | PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA, | ||
1572 | PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA, | ||
1573 | PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA, | ||
1574 | PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA, | ||
1575 | PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA, | ||
1576 | PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA, | ||
1577 | PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA, | ||
1578 | PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA } | ||
1579 | }, | ||
1580 | { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054004, 32) { | ||
1581 | PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA, | ||
1582 | PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA, | ||
1583 | PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA, | ||
1584 | PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA, | ||
1585 | PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA, | ||
1586 | PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA, | ||
1587 | PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA, | ||
1588 | PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA } | ||
1589 | }, | ||
1590 | { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054008, 32) { | ||
1591 | PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA, | ||
1592 | PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA, | ||
1593 | PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA, | ||
1594 | PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA, | ||
1595 | PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA, | ||
1596 | PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA, | ||
1597 | PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA, | ||
1598 | PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA } | ||
1599 | }, | ||
1600 | { PINMUX_DATA_REG("PORTD127_096DR", 0xe605400C, 32) { | ||
1601 | 0, 0, 0, 0, | ||
1602 | 0, 0, 0, 0, | ||
1603 | 0, PORT118_DATA, PORT117_DATA, PORT116_DATA, | ||
1604 | PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA, | ||
1605 | PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA, | ||
1606 | PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA, | ||
1607 | PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA, | ||
1608 | PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA } | ||
1609 | }, | ||
1610 | { PINMUX_DATA_REG("PORTD159_128DR", 0xe6055000, 32) { | ||
1611 | PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA, | ||
1612 | PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA, | ||
1613 | PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA, | ||
1614 | PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA, | ||
1615 | PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA, | ||
1616 | PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA, | ||
1617 | PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA, | ||
1618 | PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA } | ||
1619 | }, | ||
1620 | { PINMUX_DATA_REG("PORTR191_160DR", 0xe6055004, 32) { | ||
1621 | 0, 0, 0, 0, | ||
1622 | 0, 0, 0, 0, | ||
1623 | 0, 0, 0, 0, | ||
1624 | 0, 0, 0, 0, | ||
1625 | 0, 0, 0, 0, | ||
1626 | 0, 0, 0, 0, | ||
1627 | 0, 0, 0, PORT164_DATA, | ||
1628 | PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA } | ||
1629 | }, | ||
1630 | { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056000, 32) { | ||
1631 | PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA, | ||
1632 | PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA, | ||
1633 | PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA, | ||
1634 | PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA, | ||
1635 | PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA, | ||
1636 | PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA, | ||
1637 | PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA, | ||
1638 | PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA } | ||
1639 | }, | ||
1640 | { PINMUX_DATA_REG("PORTU255_224DR", 0xe6056004, 32) { | ||
1641 | PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA, | ||
1642 | PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA, | ||
1643 | PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA, | ||
1644 | PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA, | ||
1645 | PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA, | ||
1646 | PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA, | ||
1647 | PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA, | ||
1648 | PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA } | ||
1649 | }, | ||
1650 | { PINMUX_DATA_REG("PORTU287_256DR", 0xe6056008, 32) { | ||
1651 | 0, 0, 0, 0, | ||
1652 | 0, 0, 0, 0, | ||
1653 | 0, 0, 0, 0, | ||
1654 | 0, 0, 0, 0, | ||
1655 | 0, 0, 0, 0, | ||
1656 | 0, 0, 0, PORT264_DATA, | ||
1657 | PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA, | ||
1658 | PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA } | ||
1659 | }, | ||
1660 | { }, | ||
1661 | }; | ||
1662 | |||
1663 | static struct pinmux_info sh7377_pinmux_info = { | ||
1664 | .name = "sh7377_pfc", | ||
1665 | .reserved_id = PINMUX_RESERVED, | ||
1666 | .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, | ||
1667 | .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, | ||
1668 | .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, | ||
1669 | .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END }, | ||
1670 | .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, | ||
1671 | .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, | ||
1672 | .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, | ||
1673 | |||
1674 | .first_gpio = GPIO_PORT0, | ||
1675 | .last_gpio = GPIO_FN_RESETOUTS, | ||
1676 | |||
1677 | .gpios = pinmux_gpios, | ||
1678 | .cfg_regs = pinmux_config_regs, | ||
1679 | .data_regs = pinmux_data_regs, | ||
1680 | |||
1681 | .gpio_data = pinmux_data, | ||
1682 | .gpio_data_size = ARRAY_SIZE(pinmux_data), | ||
1683 | }; | ||
1684 | |||
1685 | void sh7377_pinmux_init(void) | ||
1686 | { | ||
1687 | register_pinmux(&sh7377_pinmux_info); | ||
1688 | } | ||
diff --git a/arch/arm/mach-shmobile/setup-sh7377.c b/arch/arm/mach-shmobile/setup-sh7377.c deleted file mode 100644 index edcf98bb701..00000000000 --- a/arch/arm/mach-shmobile/setup-sh7377.c +++ /dev/null | |||
@@ -1,549 +0,0 @@ | |||
1 | /* | ||
2 | * sh7377 processor support | ||
3 | * | ||
4 | * Copyright (C) 2010 Magnus Damm | ||
5 | * Copyright (C) 2008 Yoshihiro Shimoda | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; version 2 of the License. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License | ||
17 | * along with this program; if not, write to the Free Software | ||
18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
19 | */ | ||
20 | #include <linux/kernel.h> | ||
21 | #include <linux/init.h> | ||
22 | #include <linux/interrupt.h> | ||
23 | #include <linux/irq.h> | ||
24 | #include <linux/platform_device.h> | ||
25 | #include <linux/of_platform.h> | ||
26 | #include <linux/uio_driver.h> | ||
27 | #include <linux/delay.h> | ||
28 | #include <linux/input.h> | ||
29 | #include <linux/io.h> | ||
30 | #include <linux/serial_sci.h> | ||
31 | #include <linux/sh_intc.h> | ||
32 | #include <linux/sh_timer.h> | ||
33 | #include <mach/hardware.h> | ||
34 | #include <mach/common.h> | ||
35 | #include <asm/mach/map.h> | ||
36 | #include <mach/irqs.h> | ||
37 | #include <asm/mach-types.h> | ||
38 | #include <asm/mach/arch.h> | ||
39 | #include <asm/mach/time.h> | ||
40 | |||
41 | static struct map_desc sh7377_io_desc[] __initdata = { | ||
42 | /* create a 1:1 entity map for 0xe6xxxxxx | ||
43 | * used by CPGA, INTC and PFC. | ||
44 | */ | ||
45 | { | ||
46 | .virtual = 0xe6000000, | ||
47 | .pfn = __phys_to_pfn(0xe6000000), | ||
48 | .length = 256 << 20, | ||
49 | .type = MT_DEVICE_NONSHARED | ||
50 | }, | ||
51 | }; | ||
52 | |||
53 | void __init sh7377_map_io(void) | ||
54 | { | ||
55 | iotable_init(sh7377_io_desc, ARRAY_SIZE(sh7377_io_desc)); | ||
56 | } | ||
57 | |||
58 | /* SCIFA0 */ | ||
59 | static struct plat_sci_port scif0_platform_data = { | ||
60 | .mapbase = 0xe6c40000, | ||
61 | .flags = UPF_BOOT_AUTOCONF, | ||
62 | .scscr = SCSCR_RE | SCSCR_TE, | ||
63 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
64 | .type = PORT_SCIFA, | ||
65 | .irqs = { evt2irq(0xc00), evt2irq(0xc00), | ||
66 | evt2irq(0xc00), evt2irq(0xc00) }, | ||
67 | }; | ||
68 | |||
69 | static struct platform_device scif0_device = { | ||
70 | .name = "sh-sci", | ||
71 | .id = 0, | ||
72 | .dev = { | ||
73 | .platform_data = &scif0_platform_data, | ||
74 | }, | ||
75 | }; | ||
76 | |||
77 | /* SCIFA1 */ | ||
78 | static struct plat_sci_port scif1_platform_data = { | ||
79 | .mapbase = 0xe6c50000, | ||
80 | .flags = UPF_BOOT_AUTOCONF, | ||
81 | .scscr = SCSCR_RE | SCSCR_TE, | ||
82 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
83 | .type = PORT_SCIFA, | ||
84 | .irqs = { evt2irq(0xc20), evt2irq(0xc20), | ||
85 | evt2irq(0xc20), evt2irq(0xc20) }, | ||
86 | }; | ||
87 | |||
88 | static struct platform_device scif1_device = { | ||
89 | .name = "sh-sci", | ||
90 | .id = 1, | ||
91 | .dev = { | ||
92 | .platform_data = &scif1_platform_data, | ||
93 | }, | ||
94 | }; | ||
95 | |||
96 | /* SCIFA2 */ | ||
97 | static struct plat_sci_port scif2_platform_data = { | ||
98 | .mapbase = 0xe6c60000, | ||
99 | .flags = UPF_BOOT_AUTOCONF, | ||
100 | .scscr = SCSCR_RE | SCSCR_TE, | ||
101 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
102 | .type = PORT_SCIFA, | ||
103 | .irqs = { evt2irq(0xc40), evt2irq(0xc40), | ||
104 | evt2irq(0xc40), evt2irq(0xc40) }, | ||
105 | }; | ||
106 | |||
107 | static struct platform_device scif2_device = { | ||
108 | .name = "sh-sci", | ||
109 | .id = 2, | ||
110 | .dev = { | ||
111 | .platform_data = &scif2_platform_data, | ||
112 | }, | ||
113 | }; | ||
114 | |||
115 | /* SCIFA3 */ | ||
116 | static struct plat_sci_port scif3_platform_data = { | ||
117 | .mapbase = 0xe6c70000, | ||
118 | .flags = UPF_BOOT_AUTOCONF, | ||
119 | .scscr = SCSCR_RE | SCSCR_TE, | ||
120 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
121 | .type = PORT_SCIFA, | ||
122 | .irqs = { evt2irq(0xc60), evt2irq(0xc60), | ||
123 | evt2irq(0xc60), evt2irq(0xc60) }, | ||
124 | }; | ||
125 | |||
126 | static struct platform_device scif3_device = { | ||
127 | .name = "sh-sci", | ||
128 | .id = 3, | ||
129 | .dev = { | ||
130 | .platform_data = &scif3_platform_data, | ||
131 | }, | ||
132 | }; | ||
133 | |||
134 | /* SCIFA4 */ | ||
135 | static struct plat_sci_port scif4_platform_data = { | ||
136 | .mapbase = 0xe6c80000, | ||
137 | .flags = UPF_BOOT_AUTOCONF, | ||
138 | .scscr = SCSCR_RE | SCSCR_TE, | ||
139 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
140 | .type = PORT_SCIFA, | ||
141 | .irqs = { evt2irq(0xd20), evt2irq(0xd20), | ||
142 | evt2irq(0xd20), evt2irq(0xd20) }, | ||
143 | }; | ||
144 | |||
145 | static struct platform_device scif4_device = { | ||
146 | .name = "sh-sci", | ||
147 | .id = 4, | ||
148 | .dev = { | ||
149 | .platform_data = &scif4_platform_data, | ||
150 | }, | ||
151 | }; | ||
152 | |||
153 | /* SCIFA5 */ | ||
154 | static struct plat_sci_port scif5_platform_data = { | ||
155 | .mapbase = 0xe6cb0000, | ||
156 | .flags = UPF_BOOT_AUTOCONF, | ||
157 | .scscr = SCSCR_RE | SCSCR_TE, | ||
158 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
159 | .type = PORT_SCIFA, | ||
160 | .irqs = { evt2irq(0xd40), evt2irq(0xd40), | ||
161 | evt2irq(0xd40), evt2irq(0xd40) }, | ||
162 | }; | ||
163 | |||
164 | static struct platform_device scif5_device = { | ||
165 | .name = "sh-sci", | ||
166 | .id = 5, | ||
167 | .dev = { | ||
168 | .platform_data = &scif5_platform_data, | ||
169 | }, | ||
170 | }; | ||
171 | |||
172 | /* SCIFA6 */ | ||
173 | static struct plat_sci_port scif6_platform_data = { | ||
174 | .mapbase = 0xe6cc0000, | ||
175 | .flags = UPF_BOOT_AUTOCONF, | ||
176 | .scscr = SCSCR_RE | SCSCR_TE, | ||
177 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
178 | .type = PORT_SCIFA, | ||
179 | .irqs = { intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80), | ||
180 | intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80) }, | ||
181 | }; | ||
182 | |||
183 | static struct platform_device scif6_device = { | ||
184 | .name = "sh-sci", | ||
185 | .id = 6, | ||
186 | .dev = { | ||
187 | .platform_data = &scif6_platform_data, | ||
188 | }, | ||
189 | }; | ||
190 | |||
191 | /* SCIFB */ | ||
192 | static struct plat_sci_port scif7_platform_data = { | ||
193 | .mapbase = 0xe6c30000, | ||
194 | .flags = UPF_BOOT_AUTOCONF, | ||
195 | .scscr = SCSCR_RE | SCSCR_TE, | ||
196 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
197 | .type = PORT_SCIFB, | ||
198 | .irqs = { evt2irq(0xd60), evt2irq(0xd60), | ||
199 | evt2irq(0xd60), evt2irq(0xd60) }, | ||
200 | }; | ||
201 | |||
202 | static struct platform_device scif7_device = { | ||
203 | .name = "sh-sci", | ||
204 | .id = 7, | ||
205 | .dev = { | ||
206 | .platform_data = &scif7_platform_data, | ||
207 | }, | ||
208 | }; | ||
209 | |||
210 | static struct sh_timer_config cmt10_platform_data = { | ||
211 | .name = "CMT10", | ||
212 | .channel_offset = 0x10, | ||
213 | .timer_bit = 0, | ||
214 | .clockevent_rating = 125, | ||
215 | .clocksource_rating = 125, | ||
216 | }; | ||
217 | |||
218 | static struct resource cmt10_resources[] = { | ||
219 | [0] = { | ||
220 | .name = "CMT10", | ||
221 | .start = 0xe6138010, | ||
222 | .end = 0xe613801b, | ||
223 | .flags = IORESOURCE_MEM, | ||
224 | }, | ||
225 | [1] = { | ||
226 | .start = evt2irq(0xb00), /* CMT1_CMT10 */ | ||
227 | .flags = IORESOURCE_IRQ, | ||
228 | }, | ||
229 | }; | ||
230 | |||
231 | static struct platform_device cmt10_device = { | ||
232 | .name = "sh_cmt", | ||
233 | .id = 10, | ||
234 | .dev = { | ||
235 | .platform_data = &cmt10_platform_data, | ||
236 | }, | ||
237 | .resource = cmt10_resources, | ||
238 | .num_resources = ARRAY_SIZE(cmt10_resources), | ||
239 | }; | ||
240 | |||
241 | /* VPU */ | ||
242 | static struct uio_info vpu_platform_data = { | ||
243 | .name = "VPU5HG", | ||
244 | .version = "0", | ||
245 | .irq = intcs_evt2irq(0x980), | ||
246 | }; | ||
247 | |||
248 | static struct resource vpu_resources[] = { | ||
249 | [0] = { | ||
250 | .name = "VPU", | ||
251 | .start = 0xfe900000, | ||
252 | .end = 0xfe900157, | ||
253 | .flags = IORESOURCE_MEM, | ||
254 | }, | ||
255 | }; | ||
256 | |||
257 | static struct platform_device vpu_device = { | ||
258 | .name = "uio_pdrv_genirq", | ||
259 | .id = 0, | ||
260 | .dev = { | ||
261 | .platform_data = &vpu_platform_data, | ||
262 | }, | ||
263 | .resource = vpu_resources, | ||
264 | .num_resources = ARRAY_SIZE(vpu_resources), | ||
265 | }; | ||
266 | |||
267 | /* VEU0 */ | ||
268 | static struct uio_info veu0_platform_data = { | ||
269 | .name = "VEU0", | ||
270 | .version = "0", | ||
271 | .irq = intcs_evt2irq(0x700), | ||
272 | }; | ||
273 | |||
274 | static struct resource veu0_resources[] = { | ||
275 | [0] = { | ||
276 | .name = "VEU0", | ||
277 | .start = 0xfe920000, | ||
278 | .end = 0xfe9200cb, | ||
279 | .flags = IORESOURCE_MEM, | ||
280 | }, | ||
281 | }; | ||
282 | |||
283 | static struct platform_device veu0_device = { | ||
284 | .name = "uio_pdrv_genirq", | ||
285 | .id = 1, | ||
286 | .dev = { | ||
287 | .platform_data = &veu0_platform_data, | ||
288 | }, | ||
289 | .resource = veu0_resources, | ||
290 | .num_resources = ARRAY_SIZE(veu0_resources), | ||
291 | }; | ||
292 | |||
293 | /* VEU1 */ | ||
294 | static struct uio_info veu1_platform_data = { | ||
295 | .name = "VEU1", | ||
296 | .version = "0", | ||
297 | .irq = intcs_evt2irq(0x720), | ||
298 | }; | ||
299 | |||
300 | static struct resource veu1_resources[] = { | ||
301 | [0] = { | ||
302 | .name = "VEU1", | ||
303 | .start = 0xfe924000, | ||
304 | .end = 0xfe9240cb, | ||
305 | .flags = IORESOURCE_MEM, | ||
306 | }, | ||
307 | }; | ||
308 | |||
309 | static struct platform_device veu1_device = { | ||
310 | .name = "uio_pdrv_genirq", | ||
311 | .id = 2, | ||
312 | .dev = { | ||
313 | .platform_data = &veu1_platform_data, | ||
314 | }, | ||
315 | .resource = veu1_resources, | ||
316 | .num_resources = ARRAY_SIZE(veu1_resources), | ||
317 | }; | ||
318 | |||
319 | /* VEU2 */ | ||
320 | static struct uio_info veu2_platform_data = { | ||
321 | .name = "VEU2", | ||
322 | .version = "0", | ||
323 | .irq = intcs_evt2irq(0x740), | ||
324 | }; | ||
325 | |||
326 | static struct resource veu2_resources[] = { | ||
327 | [0] = { | ||
328 | .name = "VEU2", | ||
329 | .start = 0xfe928000, | ||
330 | .end = 0xfe928307, | ||
331 | .flags = IORESOURCE_MEM, | ||
332 | }, | ||
333 | }; | ||
334 | |||
335 | static struct platform_device veu2_device = { | ||
336 | .name = "uio_pdrv_genirq", | ||
337 | .id = 3, | ||
338 | .dev = { | ||
339 | .platform_data = &veu2_platform_data, | ||
340 | }, | ||
341 | .resource = veu2_resources, | ||
342 | .num_resources = ARRAY_SIZE(veu2_resources), | ||
343 | }; | ||
344 | |||
345 | /* VEU3 */ | ||
346 | static struct uio_info veu3_platform_data = { | ||
347 | .name = "VEU3", | ||
348 | .version = "0", | ||
349 | .irq = intcs_evt2irq(0x760), | ||
350 | }; | ||
351 | |||
352 | static struct resource veu3_resources[] = { | ||
353 | [0] = { | ||
354 | .name = "VEU3", | ||
355 | .start = 0xfe92c000, | ||
356 | .end = 0xfe92c307, | ||
357 | .flags = IORESOURCE_MEM, | ||
358 | }, | ||
359 | }; | ||
360 | |||
361 | static struct platform_device veu3_device = { | ||
362 | .name = "uio_pdrv_genirq", | ||
363 | .id = 4, | ||
364 | .dev = { | ||
365 | .platform_data = &veu3_platform_data, | ||
366 | }, | ||
367 | .resource = veu3_resources, | ||
368 | .num_resources = ARRAY_SIZE(veu3_resources), | ||
369 | }; | ||
370 | |||
371 | /* JPU */ | ||
372 | static struct uio_info jpu_platform_data = { | ||
373 | .name = "JPU", | ||
374 | .version = "0", | ||
375 | .irq = intcs_evt2irq(0x560), | ||
376 | }; | ||
377 | |||
378 | static struct resource jpu_resources[] = { | ||
379 | [0] = { | ||
380 | .name = "JPU", | ||
381 | .start = 0xfe980000, | ||
382 | .end = 0xfe9902d3, | ||
383 | .flags = IORESOURCE_MEM, | ||
384 | }, | ||
385 | }; | ||
386 | |||
387 | static struct platform_device jpu_device = { | ||
388 | .name = "uio_pdrv_genirq", | ||
389 | .id = 5, | ||
390 | .dev = { | ||
391 | .platform_data = &jpu_platform_data, | ||
392 | }, | ||
393 | .resource = jpu_resources, | ||
394 | .num_resources = ARRAY_SIZE(jpu_resources), | ||
395 | }; | ||
396 | |||
397 | /* SPU2DSP0 */ | ||
398 | static struct uio_info spu0_platform_data = { | ||
399 | .name = "SPU2DSP0", | ||
400 | .version = "0", | ||
401 | .irq = evt2irq(0x1800), | ||
402 | }; | ||
403 | |||
404 | static struct resource spu0_resources[] = { | ||
405 | [0] = { | ||
406 | .name = "SPU2DSP0", | ||
407 | .start = 0xfe200000, | ||
408 | .end = 0xfe2fffff, | ||
409 | .flags = IORESOURCE_MEM, | ||
410 | }, | ||
411 | }; | ||
412 | |||
413 | static struct platform_device spu0_device = { | ||
414 | .name = "uio_pdrv_genirq", | ||
415 | .id = 6, | ||
416 | .dev = { | ||
417 | .platform_data = &spu0_platform_data, | ||
418 | }, | ||
419 | .resource = spu0_resources, | ||
420 | .num_resources = ARRAY_SIZE(spu0_resources), | ||
421 | }; | ||
422 | |||
423 | /* SPU2DSP1 */ | ||
424 | static struct uio_info spu1_platform_data = { | ||
425 | .name = "SPU2DSP1", | ||
426 | .version = "0", | ||
427 | .irq = evt2irq(0x1820), | ||
428 | }; | ||
429 | |||
430 | static struct resource spu1_resources[] = { | ||
431 | [0] = { | ||
432 | .name = "SPU2DSP1", | ||
433 | .start = 0xfe300000, | ||
434 | .end = 0xfe3fffff, | ||
435 | .flags = IORESOURCE_MEM, | ||
436 | }, | ||
437 | }; | ||
438 | |||
439 | static struct platform_device spu1_device = { | ||
440 | .name = "uio_pdrv_genirq", | ||
441 | .id = 7, | ||
442 | .dev = { | ||
443 | .platform_data = &spu1_platform_data, | ||
444 | }, | ||
445 | .resource = spu1_resources, | ||
446 | .num_resources = ARRAY_SIZE(spu1_resources), | ||
447 | }; | ||
448 | |||
449 | static struct platform_device *sh7377_early_devices[] __initdata = { | ||
450 | &scif0_device, | ||
451 | &scif1_device, | ||
452 | &scif2_device, | ||
453 | &scif3_device, | ||
454 | &scif4_device, | ||
455 | &scif5_device, | ||
456 | &scif6_device, | ||
457 | &scif7_device, | ||
458 | &cmt10_device, | ||
459 | }; | ||
460 | |||
461 | static struct platform_device *sh7377_devices[] __initdata = { | ||
462 | &vpu_device, | ||
463 | &veu0_device, | ||
464 | &veu1_device, | ||
465 | &veu2_device, | ||
466 | &veu3_device, | ||
467 | &jpu_device, | ||
468 | &spu0_device, | ||
469 | &spu1_device, | ||
470 | }; | ||
471 | |||
472 | void __init sh7377_add_standard_devices(void) | ||
473 | { | ||
474 | platform_add_devices(sh7377_early_devices, | ||
475 | ARRAY_SIZE(sh7377_early_devices)); | ||
476 | |||
477 | platform_add_devices(sh7377_devices, | ||
478 | ARRAY_SIZE(sh7377_devices)); | ||
479 | } | ||
480 | |||
481 | static void __init sh7377_earlytimer_init(void) | ||
482 | { | ||
483 | sh7377_clock_init(); | ||
484 | shmobile_earlytimer_init(); | ||
485 | } | ||
486 | |||
487 | #define SMSTPCR3 IOMEM(0xe615013c) | ||
488 | #define SMSTPCR3_CMT1 (1 << 29) | ||
489 | |||
490 | void __init sh7377_add_early_devices(void) | ||
491 | { | ||
492 | /* enable clock to CMT1 */ | ||
493 | __raw_writel(__raw_readl(SMSTPCR3) & ~SMSTPCR3_CMT1, SMSTPCR3); | ||
494 | |||
495 | early_platform_add_devices(sh7377_early_devices, | ||
496 | ARRAY_SIZE(sh7377_early_devices)); | ||
497 | |||
498 | /* setup early console here as well */ | ||
499 | shmobile_setup_console(); | ||
500 | |||
501 | /* override timer setup with soc-specific code */ | ||
502 | shmobile_timer.init = sh7377_earlytimer_init; | ||
503 | } | ||
504 | |||
505 | #ifdef CONFIG_USE_OF | ||
506 | |||
507 | void __init sh7377_add_early_devices_dt(void) | ||
508 | { | ||
509 | shmobile_setup_delay(600, 1, 3); /* Cortex-A8 @ 600MHz */ | ||
510 | |||
511 | early_platform_add_devices(sh7377_early_devices, | ||
512 | ARRAY_SIZE(sh7377_early_devices)); | ||
513 | |||
514 | /* setup early console here as well */ | ||
515 | shmobile_setup_console(); | ||
516 | } | ||
517 | |||
518 | static const struct of_dev_auxdata sh7377_auxdata_lookup[] __initconst = { | ||
519 | { } | ||
520 | }; | ||
521 | |||
522 | void __init sh7377_add_standard_devices_dt(void) | ||
523 | { | ||
524 | /* clocks are setup late during boot in the case of DT */ | ||
525 | sh7377_clock_init(); | ||
526 | |||
527 | platform_add_devices(sh7377_early_devices, | ||
528 | ARRAY_SIZE(sh7377_early_devices)); | ||
529 | |||
530 | of_platform_populate(NULL, of_default_bus_match_table, | ||
531 | sh7377_auxdata_lookup, NULL); | ||
532 | } | ||
533 | |||
534 | static const char *sh7377_boards_compat_dt[] __initdata = { | ||
535 | "renesas,sh7377", | ||
536 | NULL, | ||
537 | }; | ||
538 | |||
539 | DT_MACHINE_START(SH7377_DT, "Generic SH7377 (Flattened Device Tree)") | ||
540 | .map_io = sh7377_map_io, | ||
541 | .init_early = sh7377_add_early_devices_dt, | ||
542 | .init_irq = sh7377_init_irq, | ||
543 | .handle_irq = shmobile_handle_irq_intc, | ||
544 | .init_machine = sh7377_add_standard_devices_dt, | ||
545 | .timer = &shmobile_timer, | ||
546 | .dt_compat = sh7377_boards_compat_dt, | ||
547 | MACHINE_END | ||
548 | |||
549 | #endif /* CONFIG_USE_OF */ | ||