diff options
author | Yaniv Rosner <yanivr@broadcom.com> | 2012-04-03 21:28:57 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2012-04-04 18:24:22 -0400 |
commit | 25182fc22237f0fb1789c7ac9a79e871a1898ae5 (patch) | |
tree | 1c996bdd459106238f6c58107208cc118d4e5765 | |
parent | 6a51c0d17b8fb6ae300ba5bc42a020160944e1b2 (diff) |
bnx2x: Fix BCM578x0-SFI pre-emphasis settings
Fix 578x0-SFI pre-emphasis settings per HW recommendations to achieve better
link strength.
Signed-off-by: Yaniv Rosner <yanivr@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r-- | drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c index ce0b0c220e6..1e2fea37eec 100644 --- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c +++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c | |||
@@ -3994,13 +3994,13 @@ static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy, | |||
3994 | 3994 | ||
3995 | } else { | 3995 | } else { |
3996 | misc1_val |= 0x9; | 3996 | misc1_val |= 0x9; |
3997 | tap_val = ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | | 3997 | tap_val = ((0x0f << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | |
3998 | (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | | 3998 | (0x2b << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | |
3999 | (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET)); | 3999 | (0x02 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET)); |
4000 | tx_driver_val = | 4000 | tx_driver_val = |
4001 | ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | | 4001 | ((0x03 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | |
4002 | (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | | 4002 | (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | |
4003 | (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)); | 4003 | (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)); |
4004 | } | 4004 | } |
4005 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | 4005 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
4006 | MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val); | 4006 | MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val); |