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authorAlan Cox <alan@linux.intel.com>2009-10-06 10:51:10 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2009-12-11 15:23:08 -0500
commit1210db957aa4f213259fd4dc92fd6e9e8cfc3187 (patch)
tree7feda3d2909203026742835dcea1bee0716b9949
parent57aed3b4383a5c16217f805daf1bc93777ad9b39 (diff)
Staging: et131x: phy clean up
Clean up the phy code a bit so we can see what needs doing. This involves moving blocks around and making stuff static Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat
-rw-r--r--drivers/staging/et131x/et1310_phy.c1084
-rw-r--r--drivers/staging/et131x/et1310_phy.h30
2 files changed, 545 insertions, 569 deletions
diff --git a/drivers/staging/et131x/et1310_phy.c b/drivers/staging/et131x/et1310_phy.c
index 6b77c541df2..c1aedbb2469 100644
--- a/drivers/staging/et131x/et1310_phy.c
+++ b/drivers/staging/et131x/et1310_phy.c
@@ -109,12 +109,12 @@ static int et131x_xcvr_init(struct et131x_adapter *adapter);
109 * 109 *
110 * Returns 0 on success, errno on failure (as defined in errno.h) 110 * Returns 0 on success, errno on failure (as defined in errno.h)
111 */ 111 */
112int PhyMiRead(struct et131x_adapter *adapter, uint8_t xcvrAddr, 112int PhyMiRead(struct et131x_adapter *adapter, u8 xcvrAddr,
113 uint8_t xcvrReg, uint16_t *value) 113 u8 xcvrReg, u16 *value)
114{ 114{
115 struct _MAC_t __iomem *mac = &adapter->regs->mac; 115 struct _MAC_t __iomem *mac = &adapter->regs->mac;
116 int status = 0; 116 int status = 0;
117 uint32_t delay; 117 u32 delay;
118 u32 miiAddr; 118 u32 miiAddr;
119 u32 miiCmd; 119 u32 miiCmd;
120 u32 miiIndicator; 120 u32 miiIndicator;
@@ -174,14 +174,16 @@ int PhyMiRead(struct et131x_adapter *adapter, uint8_t xcvrAddr,
174 * @xcvrReg: the register to read 174 * @xcvrReg: the register to read
175 * @value: 16-bit value to write 175 * @value: 16-bit value to write
176 * 176 *
177 * FIXME: one caller in netdev still
178 *
177 * Return 0 on success, errno on failure (as defined in errno.h) 179 * Return 0 on success, errno on failure (as defined in errno.h)
178 */ 180 */
179int MiWrite(struct et131x_adapter *adapter, uint8_t xcvrReg, uint16_t value) 181int MiWrite(struct et131x_adapter *adapter, u8 xcvrReg, u16 value)
180{ 182{
181 struct _MAC_t __iomem *mac = &adapter->regs->mac; 183 struct _MAC_t __iomem *mac = &adapter->regs->mac;
182 int status = 0; 184 int status = 0;
183 uint8_t xcvrAddr = adapter->Stats.xcvr_addr; 185 u8 xcvrAddr = adapter->Stats.xcvr_addr;
184 uint32_t delay; 186 u32 delay;
185 u32 miiAddr; 187 u32 miiAddr;
186 u32 miiCmd; 188 u32 miiCmd;
187 u32 miiIndicator; 189 u32 miiIndicator;
@@ -210,7 +212,7 @@ int MiWrite(struct et131x_adapter *adapter, uint8_t xcvrReg, uint16_t value)
210 212
211 /* If we hit the max delay, we could not write the register */ 213 /* If we hit the max delay, we could not write the register */
212 if (delay == 100) { 214 if (delay == 100) {
213 uint16_t TempValue; 215 u16 TempValue;
214 216
215 dev_warn(&adapter->pdev->dev, 217 dev_warn(&adapter->pdev->dev,
216 "xcvrReg 0x%08x could not be written", xcvrReg); 218 "xcvrReg 0x%08x could not be written", xcvrReg);
@@ -244,22 +246,22 @@ int MiWrite(struct et131x_adapter *adapter, uint8_t xcvrReg, uint16_t value)
244int et131x_xcvr_find(struct et131x_adapter *adapter) 246int et131x_xcvr_find(struct et131x_adapter *adapter)
245{ 247{
246 int status = -ENODEV; 248 int status = -ENODEV;
247 uint8_t xcvr_addr; 249 u8 xcvr_addr;
248 MI_IDR1_t idr1; 250 MI_IDR1_t idr1;
249 MI_IDR2_t idr2; 251 MI_IDR2_t idr2;
250 uint32_t xcvr_id; 252 u32 xcvr_id;
251 253
252 /* We need to get xcvr id and address we just get the first one */ 254 /* We need to get xcvr id and address we just get the first one */
253 for (xcvr_addr = 0; xcvr_addr < 32; xcvr_addr++) { 255 for (xcvr_addr = 0; xcvr_addr < 32; xcvr_addr++) {
254 /* Read the ID from the PHY */ 256 /* Read the ID from the PHY */
255 PhyMiRead(adapter, xcvr_addr, 257 PhyMiRead(adapter, xcvr_addr,
256 (uint8_t) offsetof(MI_REGS_t, idr1), 258 (u8) offsetof(MI_REGS_t, idr1),
257 &idr1.value); 259 &idr1.value);
258 PhyMiRead(adapter, xcvr_addr, 260 PhyMiRead(adapter, xcvr_addr,
259 (uint8_t) offsetof(MI_REGS_t, idr2), 261 (u8) offsetof(MI_REGS_t, idr2),
260 &idr2.value); 262 &idr2.value);
261 263
262 xcvr_id = (uint32_t) ((idr1.value << 16) | idr2.value); 264 xcvr_id = (u32) ((idr1.value << 16) | idr2.value);
263 265
264 if ((idr1.value != 0) && (idr1.value != 0xffff)) { 266 if ((idr1.value != 0) && (idr1.value != 0xffff)) {
265 adapter->Stats.xcvr_id = xcvr_id; 267 adapter->Stats.xcvr_id = xcvr_id;
@@ -290,279 +292,317 @@ int et131x_setphy_normal(struct et131x_adapter *adapter)
290 return status; 292 return status;
291} 293}
292 294
293/** 295void ET1310_PhyReset(struct et131x_adapter *etdev)
294 * et131x_xcvr_init - Init the phy if we are setting it into force mode
295 * @adapter: pointer to our private adapter structure
296 *
297 * Returns 0 on success, errno on failure (as defined in errno.h)
298 */
299static int et131x_xcvr_init(struct et131x_adapter *adapter)
300{ 296{
301 int status = 0; 297 MiWrite(etdev, PHY_CONTROL, 0x8000);
302 MI_IMR_t imr; 298}
303 MI_ISR_t isr;
304 MI_LCR2_t lcr2;
305 299
306 /* Zero out the adapter structure variable representing BMSR */ 300void ET1310_PhyPowerDown(struct et131x_adapter *etdev, bool down)
307 adapter->Bmsr.value = 0; 301{
302 u16 data;
308 303
309 MiRead(adapter, (uint8_t) offsetof(MI_REGS_t, isr), &isr.value); 304 MiRead(etdev, PHY_CONTROL, &data);
310 305
311 MiRead(adapter, (uint8_t) offsetof(MI_REGS_t, imr), &imr.value); 306 if (down == false) {
307 /* Power UP */
308 data &= ~0x0800;
309 MiWrite(etdev, PHY_CONTROL, data);
310 } else {
311 /* Power DOWN */
312 data |= 0x0800;
313 MiWrite(etdev, PHY_CONTROL, data);
314 }
315}
312 316
313 /* Set the link status interrupt only. Bad behavior when link status 317static void ET1310_PhyAutoNeg(struct et131x_adapter *etdev, bool enable)
314 * and auto neg are set, we run into a nested interrupt problem 318{
315 */ 319 u16 data;
316 imr.bits.int_en = 0x1;
317 imr.bits.link_status = 0x1;
318 imr.bits.autoneg_status = 0x1;
319 320
320 MiWrite(adapter, (uint8_t) offsetof(MI_REGS_t, imr), imr.value); 321 MiRead(etdev, PHY_CONTROL, &data);
321 322
322 /* Set the LED behavior such that LED 1 indicates speed (off = 323 if (enable == true) {
323 * 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates 324 /* Autonegotiation ON */
324 * link and activity (on for link, blink off for activity). 325 data |= 0x1000;
325 * 326 MiWrite(etdev, PHY_CONTROL, data);
326 * NOTE: Some customizations have been added here for specific 327 } else {
327 * vendors; The LED behavior is now determined by vendor data in the 328 /* Autonegotiation OFF */
328 * EEPROM. However, the above description is the default. 329 data &= ~0x1000;
329 */ 330 MiWrite(etdev, PHY_CONTROL, data);
330 if ((adapter->eepromData[1] & 0x4) == 0) {
331 MiRead(adapter, (uint8_t) offsetof(MI_REGS_t, lcr2),
332 &lcr2.value);
333 if ((adapter->eepromData[1] & 0x8) == 0)
334 lcr2.bits.led_tx_rx = 0x3;
335 else
336 lcr2.bits.led_tx_rx = 0x4;
337 lcr2.bits.led_link = 0xa;
338 MiWrite(adapter, (uint8_t) offsetof(MI_REGS_t, lcr2),
339 lcr2.value);
340 } 331 }
332}
341 333
342 /* Determine if we need to go into a force mode and set it */ 334static void ET1310_PhyDuplexMode(struct et131x_adapter *etdev, u16 duplex)
343 if (adapter->AiForceSpeed == 0 && adapter->AiForceDpx == 0) { 335{
344 if ((adapter->RegistryFlowControl == TxOnly) || 336 u16 data;
345 (adapter->RegistryFlowControl == Both)) {
346 ET1310_PhyAccessMiBit(adapter,
347 TRUEPHY_BIT_SET, 4, 11, NULL);
348 } else {
349 ET1310_PhyAccessMiBit(adapter,
350 TRUEPHY_BIT_CLEAR, 4, 11, NULL);
351 }
352
353 if (adapter->RegistryFlowControl == Both) {
354 ET1310_PhyAccessMiBit(adapter,
355 TRUEPHY_BIT_SET, 4, 10, NULL);
356 } else {
357 ET1310_PhyAccessMiBit(adapter,
358 TRUEPHY_BIT_CLEAR, 4, 10, NULL);
359 }
360 337
361 /* Set the phy to autonegotiation */ 338 MiRead(etdev, PHY_CONTROL, &data);
362 ET1310_PhyAutoNeg(adapter, true);
363 339
364 /* NOTE - Do we need this? */ 340 if (duplex == TRUEPHY_DUPLEX_FULL) {
365 ET1310_PhyAccessMiBit(adapter, TRUEPHY_BIT_SET, 0, 9, NULL); 341 /* Set Full Duplex */
366 return status; 342 data |= 0x100;
343 MiWrite(etdev, PHY_CONTROL, data);
367 } else { 344 } else {
368 ET1310_PhyAutoNeg(adapter, false); 345 /* Set Half Duplex */
346 data &= ~0x100;
347 MiWrite(etdev, PHY_CONTROL, data);
348 }
349}
369 350
370 /* Set to the correct force mode. */ 351static void ET1310_PhySpeedSelect(struct et131x_adapter *etdev, u16 speed)
371 if (adapter->AiForceDpx != 1) { 352{
372 if ((adapter->RegistryFlowControl == TxOnly) || 353 u16 data;
373 (adapter->RegistryFlowControl == Both)) {
374 ET1310_PhyAccessMiBit(adapter,
375 TRUEPHY_BIT_SET, 4, 11,
376 NULL);
377 } else {
378 ET1310_PhyAccessMiBit(adapter,
379 TRUEPHY_BIT_CLEAR, 4, 11,
380 NULL);
381 }
382 354
383 if (adapter->RegistryFlowControl == Both) { 355 /* Read the PHY control register */
384 ET1310_PhyAccessMiBit(adapter, 356 MiRead(etdev, PHY_CONTROL, &data);
385 TRUEPHY_BIT_SET, 4, 10,
386 NULL);
387 } else {
388 ET1310_PhyAccessMiBit(adapter,
389 TRUEPHY_BIT_CLEAR, 4, 10,
390 NULL);
391 }
392 } else {
393 ET1310_PhyAccessMiBit(adapter,
394 TRUEPHY_BIT_CLEAR, 4, 10, NULL);
395 ET1310_PhyAccessMiBit(adapter,
396 TRUEPHY_BIT_CLEAR, 4, 11, NULL);
397 }
398 357
399 switch (adapter->AiForceSpeed) { 358 /* Clear all Speed settings (Bits 6, 13) */
400 case 10: 359 data &= ~0x2040;
401 if (adapter->AiForceDpx == 1)
402 TPAL_SetPhy10HalfDuplex(adapter);
403 else if (adapter->AiForceDpx == 2)
404 TPAL_SetPhy10FullDuplex(adapter);
405 else
406 TPAL_SetPhy10Force(adapter);
407 break;
408 case 100:
409 if (adapter->AiForceDpx == 1)
410 TPAL_SetPhy100HalfDuplex(adapter);
411 else if (adapter->AiForceDpx == 2)
412 TPAL_SetPhy100FullDuplex(adapter);
413 else
414 TPAL_SetPhy100Force(adapter);
415 break;
416 case 1000:
417 TPAL_SetPhy1000FullDuplex(adapter);
418 break;
419 }
420 360
421 return status; 361 /* Reset the speed bits based on user selection */
362 switch (speed) {
363 case TRUEPHY_SPEED_10MBPS:
364 /* Bits already cleared above, do nothing */
365 break;
366
367 case TRUEPHY_SPEED_100MBPS:
368 /* 100M == Set bit 13 */
369 data |= 0x2000;
370 break;
371
372 case TRUEPHY_SPEED_1000MBPS:
373 default:
374 data |= 0x0040;
375 break;
422 } 376 }
377
378 /* Write back the new speed */
379 MiWrite(etdev, PHY_CONTROL, data);
423} 380}
424 381
425void et131x_Mii_check(struct et131x_adapter *etdev, 382static void ET1310_PhyLinkStatus(struct et131x_adapter *etdev,
426 MI_BMSR_t bmsr, MI_BMSR_t bmsr_ints) 383 u8 *link_status,
384 u32 *autoneg,
385 u32 *linkspeed,
386 u32 *duplex_mode,
387 u32 *mdi_mdix,
388 u32 *masterslave, u32 *polarity)
427{ 389{
428 uint8_t link_status; 390 u16 mistatus = 0;
429 uint32_t autoneg_status; 391 u16 is1000BaseT = 0;
430 uint32_t speed; 392 u16 vmi_phystatus = 0;
431 uint32_t duplex; 393 u16 control = 0;
432 uint32_t mdi_mdix;
433 uint32_t masterslave;
434 uint32_t polarity;
435 unsigned long flags;
436 394
437 if (bmsr_ints.bits.link_status) { 395 MiRead(etdev, PHY_STATUS, &mistatus);
438 if (bmsr.bits.link_status) { 396 MiRead(etdev, PHY_1000_STATUS, &is1000BaseT);
439 etdev->PoMgmt.TransPhyComaModeOnBoot = 20; 397 MiRead(etdev, PHY_PHY_STATUS, &vmi_phystatus);
398 MiRead(etdev, PHY_CONTROL, &control);
440 399
441 /* Update our state variables and indicate the 400 if (link_status) {
442 * connected state 401 *link_status =
443 */ 402 (unsigned char)((vmi_phystatus & 0x0040) ? 1 : 0);
444 spin_lock_irqsave(&etdev->Lock, flags); 403 }
445 404
446 etdev->MediaState = NETIF_STATUS_MEDIA_CONNECT; 405 if (autoneg) {
447 etdev->Flags &= ~fMP_ADAPTER_LINK_DETECTION; 406 *autoneg =
407 (control & 0x1000) ? ((vmi_phystatus & 0x0020) ?
408 TRUEPHY_ANEG_COMPLETE :
409 TRUEPHY_ANEG_NOT_COMPLETE) :
410 TRUEPHY_ANEG_DISABLED;
411 }
448 412
449 spin_unlock_irqrestore(&etdev->Lock, flags); 413 if (linkspeed)
414 *linkspeed = (vmi_phystatus & 0x0300) >> 8;
450 415
451 netif_carrier_on(etdev->netdev); 416 if (duplex_mode)
452 } else { 417 *duplex_mode = (vmi_phystatus & 0x0080) >> 7;
453 dev_warn(&etdev->pdev->dev,
454 "Link down - cable problem ?\n");
455 418
456 if (etdev->linkspeed == TRUEPHY_SPEED_10MBPS) { 419 if (mdi_mdix)
457 /* NOTE - Is there a way to query this without 420 /* NOTE: Need to complete this */
458 * TruePHY? 421 *mdi_mdix = 0;
459 * && TRU_QueryCoreType(etdev->hTruePhy, 0) == EMI_TRUEPHY_A13O) {
460 */
461 uint16_t Register18;
462 422
463 MiRead(etdev, 0x12, &Register18); 423 if (masterslave) {
464 MiWrite(etdev, 0x12, Register18 | 0x4); 424 *masterslave =
465 MiWrite(etdev, 0x10, Register18 | 0x8402); 425 (is1000BaseT & 0x4000) ? TRUEPHY_CFG_MASTER :
466 MiWrite(etdev, 0x11, Register18 | 511); 426 TRUEPHY_CFG_SLAVE;
467 MiWrite(etdev, 0x12, Register18); 427 }
468 }
469 428
470 /* For the first N seconds of life, we are in "link 429 if (polarity) {
471 * detection" When we are in this state, we should 430 *polarity =
472 * only report "connected". When the LinkDetection 431 (vmi_phystatus & 0x0400) ? TRUEPHY_POLARITY_INVERTED :
473 * Timer expires, we can report disconnected (handled 432 TRUEPHY_POLARITY_NORMAL;
474 * in the LinkDetectionDPC). 433 }
475 */ 434}
476 if (!(etdev->Flags & fMP_ADAPTER_LINK_DETECTION) ||
477 (etdev->MediaState == NETIF_STATUS_MEDIA_DISCONNECT)) {
478 spin_lock_irqsave(&etdev->Lock, flags);
479 etdev->MediaState =
480 NETIF_STATUS_MEDIA_DISCONNECT;
481 spin_unlock_irqrestore(&etdev->Lock,
482 flags);
483 435
484 netif_carrier_off(etdev->netdev); 436static void ET1310_PhyAndOrReg(struct et131x_adapter *etdev,
485 } 437 u16 regnum, u16 andMask, u16 orMask)
438{
439 u16 reg;
486 440
487 etdev->linkspeed = 0; 441 /* Read the requested register */
488 etdev->duplex_mode = 0; 442 MiRead(etdev, regnum, &reg);
489 443
490 /* Free the packets being actively sent & stopped */ 444 /* Apply the AND mask */
491 et131x_free_busy_send_packets(etdev); 445 reg &= andMask;
492 446
493 /* Re-initialize the send structures */ 447 /* Apply the OR mask */
494 et131x_init_send(etdev); 448 reg |= orMask;
495 449
496 /* Reset the RFD list and re-start RU */ 450 /* Write the value back to the register */
497 et131x_reset_recv(etdev); 451 MiWrite(etdev, regnum, reg);
452}
498 453
499 /* 454/* Still used from _mac */
500 * Bring the device back to the state it was during 455void ET1310_PhyAccessMiBit(struct et131x_adapter *etdev, u16 action,
501 * init prior to autonegotiation being complete. This 456 u16 regnum, u16 bitnum, u8 *value)
502 * way, when we get the auto-neg complete interrupt, 457{
503 * we can complete init by calling ConfigMacREGS2. 458 u16 reg;
504 */ 459 u16 mask = 0;
505 et131x_soft_reset(etdev);
506 460
507 /* Setup ET1310 as per the documentation */ 461 /* Create a mask to isolate the requested bit */
508 et131x_adapter_setup(etdev); 462 mask = 0x0001 << bitnum;
509 463
510 /* Setup the PHY into coma mode until the cable is 464 /* Read the requested register */
511 * plugged back in 465 MiRead(etdev, regnum, &reg);
512 */ 466
513 if (etdev->RegistryPhyComa == 1) 467 switch (action) {
514 EnablePhyComa(etdev); 468 case TRUEPHY_BIT_READ:
515 } 469 if (value != NULL)
470 *value = (reg & mask) >> bitnum;
471 break;
472
473 case TRUEPHY_BIT_SET:
474 reg |= mask;
475 MiWrite(etdev, regnum, reg);
476 break;
477
478 case TRUEPHY_BIT_CLEAR:
479 reg &= ~mask;
480 MiWrite(etdev, regnum, reg);
481 break;
482
483 default:
484 break;
516 } 485 }
486}
517 487
518 if (bmsr_ints.bits.auto_neg_complete || 488void ET1310_PhyAdvertise1000BaseT(struct et131x_adapter *etdev,
519 (etdev->AiForceDpx == 3 && bmsr_ints.bits.link_status)) { 489 u16 duplex)
520 if (bmsr.bits.auto_neg_complete || etdev->AiForceDpx == 3) { 490{
521 ET1310_PhyLinkStatus(etdev, 491 u16 data;
522 &link_status, &autoneg_status,
523 &speed, &duplex, &mdi_mdix,
524 &masterslave, &polarity);
525 492
526 etdev->linkspeed = speed; 493 /* Read the PHY 1000 Base-T Control Register */
527 etdev->duplex_mode = duplex; 494 MiRead(etdev, PHY_1000_CONTROL, &data);
528 495
529 etdev->PoMgmt.TransPhyComaModeOnBoot = 20; 496 /* Clear Bits 8,9 */
497 data &= ~0x0300;
530 498
531 if (etdev->linkspeed == TRUEPHY_SPEED_10MBPS) { 499 switch (duplex) {
532 /* 500 case TRUEPHY_ADV_DUPLEX_NONE:
533 * NOTE - Is there a way to query this without 501 /* Duplex already cleared, do nothing */
534 * TruePHY? 502 break;
535 * && TRU_QueryCoreType(etdev->hTruePhy, 0)== EMI_TRUEPHY_A13O) {
536 */
537 uint16_t Register18;
538 503
539 MiRead(etdev, 0x12, &Register18); 504 case TRUEPHY_ADV_DUPLEX_FULL:
540 MiWrite(etdev, 0x12, Register18 | 0x4); 505 /* Set Bit 9 */
541 MiWrite(etdev, 0x10, Register18 | 0x8402); 506 data |= 0x0200;
542 MiWrite(etdev, 0x11, Register18 | 511); 507 break;
543 MiWrite(etdev, 0x12, Register18);
544 }
545 508
546 ConfigFlowControl(etdev); 509 case TRUEPHY_ADV_DUPLEX_HALF:
510 /* Set Bit 8 */
511 data |= 0x0100;
512 break;
547 513
548 if (etdev->linkspeed == TRUEPHY_SPEED_1000MBPS && 514 case TRUEPHY_ADV_DUPLEX_BOTH:
549 etdev->RegistryJumboPacket > 2048) 515 default:
550 ET1310_PhyAndOrReg(etdev, 0x16, 0xcfff, 516 data |= 0x0300;
551 0x2000); 517 break;
518 }
552 519
553 SetRxDmaTimer(etdev); 520 /* Write back advertisement */
554 ConfigMACRegs2(etdev); 521 MiWrite(etdev, PHY_1000_CONTROL, data);
555 } 522}
523
524static void ET1310_PhyAdvertise100BaseT(struct et131x_adapter *etdev,
525 u16 duplex)
526{
527 u16 data;
528
529 /* Read the Autonegotiation Register (10/100) */
530 MiRead(etdev, PHY_AUTO_ADVERTISEMENT, &data);
531
532 /* Clear bits 7,8 */
533 data &= ~0x0180;
534
535 switch (duplex) {
536 case TRUEPHY_ADV_DUPLEX_NONE:
537 /* Duplex already cleared, do nothing */
538 break;
539
540 case TRUEPHY_ADV_DUPLEX_FULL:
541 /* Set Bit 8 */
542 data |= 0x0100;
543 break;
544
545 case TRUEPHY_ADV_DUPLEX_HALF:
546 /* Set Bit 7 */
547 data |= 0x0080;
548 break;
549
550 case TRUEPHY_ADV_DUPLEX_BOTH:
551 default:
552 /* Set Bits 7,8 */
553 data |= 0x0180;
554 break;
555 }
556
557 /* Write back advertisement */
558 MiWrite(etdev, PHY_AUTO_ADVERTISEMENT, data);
559}
560
561static void ET1310_PhyAdvertise10BaseT(struct et131x_adapter *etdev,
562 u16 duplex)
563{
564 u16 data;
565
566 /* Read the Autonegotiation Register (10/100) */
567 MiRead(etdev, PHY_AUTO_ADVERTISEMENT, &data);
568
569 /* Clear bits 5,6 */
570 data &= ~0x0060;
571
572 switch (duplex) {
573 case TRUEPHY_ADV_DUPLEX_NONE:
574 /* Duplex already cleared, do nothing */
575 break;
576
577 case TRUEPHY_ADV_DUPLEX_FULL:
578 /* Set Bit 6 */
579 data |= 0x0040;
580 break;
581
582 case TRUEPHY_ADV_DUPLEX_HALF:
583 /* Set Bit 5 */
584 data |= 0x0020;
585 break;
586
587 case TRUEPHY_ADV_DUPLEX_BOTH:
588 default:
589 /* Set Bits 5,6 */
590 data |= 0x0060;
591 break;
556 } 592 }
593
594 /* Write back advertisement */
595 MiWrite(etdev, PHY_AUTO_ADVERTISEMENT, data);
557} 596}
558 597
598
559/** 599/**
560 * TPAL_SetPhy10HalfDuplex - Force the phy into 10 Base T Half Duplex mode. 600 * TPAL_SetPhy10HalfDuplex - Force the phy into 10 Base T Half Duplex mode.
561 * @etdev: pointer to the adapter structure 601 * @etdev: pointer to the adapter structure
562 * 602 *
563 * Also sets the MAC so it is syncd up properly 603 * Also sets the MAC so it is syncd up properly
564 */ 604 */
565void TPAL_SetPhy10HalfDuplex(struct et131x_adapter *etdev) 605static void TPAL_SetPhy10HalfDuplex(struct et131x_adapter *etdev)
566{ 606{
567 /* Power down PHY */ 607 /* Power down PHY */
568 ET1310_PhyPowerDown(etdev, 1); 608 ET1310_PhyPowerDown(etdev, 1);
@@ -585,7 +625,7 @@ void TPAL_SetPhy10HalfDuplex(struct et131x_adapter *etdev)
585 * 625 *
586 * Also sets the MAC so it is syncd up properly 626 * Also sets the MAC so it is syncd up properly
587 */ 627 */
588void TPAL_SetPhy10FullDuplex(struct et131x_adapter *etdev) 628static void TPAL_SetPhy10FullDuplex(struct et131x_adapter *etdev)
589{ 629{
590 /* Power down PHY */ 630 /* Power down PHY */
591 ET1310_PhyPowerDown(etdev, 1); 631 ET1310_PhyPowerDown(etdev, 1);
@@ -606,7 +646,7 @@ void TPAL_SetPhy10FullDuplex(struct et131x_adapter *etdev)
606 * TPAL_SetPhy10Force - Force Base-T FD mode WITHOUT using autonegotiation 646 * TPAL_SetPhy10Force - Force Base-T FD mode WITHOUT using autonegotiation
607 * @etdev: pointer to the adapter structure 647 * @etdev: pointer to the adapter structure
608 */ 648 */
609void TPAL_SetPhy10Force(struct et131x_adapter *etdev) 649static void TPAL_SetPhy10Force(struct et131x_adapter *etdev)
610{ 650{
611 /* Power down PHY */ 651 /* Power down PHY */
612 ET1310_PhyPowerDown(etdev, 1); 652 ET1310_PhyPowerDown(etdev, 1);
@@ -635,7 +675,7 @@ void TPAL_SetPhy10Force(struct et131x_adapter *etdev)
635 * 675 *
636 * Also sets the MAC so it is syncd up properly. 676 * Also sets the MAC so it is syncd up properly.
637 */ 677 */
638void TPAL_SetPhy100HalfDuplex(struct et131x_adapter *etdev) 678static void TPAL_SetPhy100HalfDuplex(struct et131x_adapter *etdev)
639{ 679{
640 /* Power down PHY */ 680 /* Power down PHY */
641 ET1310_PhyPowerDown(etdev, 1); 681 ET1310_PhyPowerDown(etdev, 1);
@@ -661,7 +701,7 @@ void TPAL_SetPhy100HalfDuplex(struct et131x_adapter *etdev)
661 * 701 *
662 * Also sets the MAC so it is syncd up properly 702 * Also sets the MAC so it is syncd up properly
663 */ 703 */
664void TPAL_SetPhy100FullDuplex(struct et131x_adapter *etdev) 704static void TPAL_SetPhy100FullDuplex(struct et131x_adapter *etdev)
665{ 705{
666 /* Power down PHY */ 706 /* Power down PHY */
667 ET1310_PhyPowerDown(etdev, 1); 707 ET1310_PhyPowerDown(etdev, 1);
@@ -682,7 +722,7 @@ void TPAL_SetPhy100FullDuplex(struct et131x_adapter *etdev)
682 * TPAL_SetPhy100Force - Force 100 BaseT FD mode WITHOUT using autonegotiation 722 * TPAL_SetPhy100Force - Force 100 BaseT FD mode WITHOUT using autonegotiation
683 * @etdev: pointer to the adapter structure 723 * @etdev: pointer to the adapter structure
684 */ 724 */
685void TPAL_SetPhy100Force(struct et131x_adapter *etdev) 725static void TPAL_SetPhy100Force(struct et131x_adapter *etdev)
686{ 726{
687 /* Power down PHY */ 727 /* Power down PHY */
688 ET1310_PhyPowerDown(etdev, 1); 728 ET1310_PhyPowerDown(etdev, 1);
@@ -711,7 +751,7 @@ void TPAL_SetPhy100Force(struct et131x_adapter *etdev)
711 * 751 *
712 * Also sets the MAC so it is syncd up properly. 752 * Also sets the MAC so it is syncd up properly.
713 */ 753 */
714void TPAL_SetPhy1000FullDuplex(struct et131x_adapter *etdev) 754static void TPAL_SetPhy1000FullDuplex(struct et131x_adapter *etdev)
715{ 755{
716 /* Power down PHY */ 756 /* Power down PHY */
717 ET1310_PhyPowerDown(etdev, 1); 757 ET1310_PhyPowerDown(etdev, 1);
@@ -732,7 +772,7 @@ void TPAL_SetPhy1000FullDuplex(struct et131x_adapter *etdev)
732 * TPAL_SetPhyAutoNeg - Set phy to autonegotiation mode. 772 * TPAL_SetPhyAutoNeg - Set phy to autonegotiation mode.
733 * @etdev: pointer to the adapter structure 773 * @etdev: pointer to the adapter structure
734 */ 774 */
735void TPAL_SetPhyAutoNeg(struct et131x_adapter *etdev) 775static void TPAL_SetPhyAutoNeg(struct et131x_adapter *etdev)
736{ 776{
737 /* Power down PHY */ 777 /* Power down PHY */
738 ET1310_PhyPowerDown(etdev, 1); 778 ET1310_PhyPowerDown(etdev, 1);
@@ -755,13 +795,276 @@ void TPAL_SetPhyAutoNeg(struct et131x_adapter *etdev)
755} 795}
756 796
757 797
798
799/**
800 * et131x_xcvr_init - Init the phy if we are setting it into force mode
801 * @adapter: pointer to our private adapter structure
802 *
803 * Returns 0 on success, errno on failure (as defined in errno.h)
804 */
805static int et131x_xcvr_init(struct et131x_adapter *adapter)
806{
807 int status = 0;
808 MI_IMR_t imr;
809 MI_ISR_t isr;
810 MI_LCR2_t lcr2;
811
812 /* Zero out the adapter structure variable representing BMSR */
813 adapter->Bmsr.value = 0;
814
815 MiRead(adapter, (u8) offsetof(MI_REGS_t, isr), &isr.value);
816
817 MiRead(adapter, (u8) offsetof(MI_REGS_t, imr), &imr.value);
818
819 /* Set the link status interrupt only. Bad behavior when link status
820 * and auto neg are set, we run into a nested interrupt problem
821 */
822 imr.bits.int_en = 0x1;
823 imr.bits.link_status = 0x1;
824 imr.bits.autoneg_status = 0x1;
825
826 MiWrite(adapter, (u8) offsetof(MI_REGS_t, imr), imr.value);
827
828 /* Set the LED behavior such that LED 1 indicates speed (off =
829 * 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates
830 * link and activity (on for link, blink off for activity).
831 *
832 * NOTE: Some customizations have been added here for specific
833 * vendors; The LED behavior is now determined by vendor data in the
834 * EEPROM. However, the above description is the default.
835 */
836 if ((adapter->eepromData[1] & 0x4) == 0) {
837 MiRead(adapter, (u8) offsetof(MI_REGS_t, lcr2),
838 &lcr2.value);
839 if ((adapter->eepromData[1] & 0x8) == 0)
840 lcr2.bits.led_tx_rx = 0x3;
841 else
842 lcr2.bits.led_tx_rx = 0x4;
843 lcr2.bits.led_link = 0xa;
844 MiWrite(adapter, (u8) offsetof(MI_REGS_t, lcr2),
845 lcr2.value);
846 }
847
848 /* Determine if we need to go into a force mode and set it */
849 if (adapter->AiForceSpeed == 0 && adapter->AiForceDpx == 0) {
850 if (adapter->RegistryFlowControl == TxOnly ||
851 adapter->RegistryFlowControl == Both)
852 ET1310_PhyAccessMiBit(adapter,
853 TRUEPHY_BIT_SET, 4, 11, NULL);
854 else
855 ET1310_PhyAccessMiBit(adapter,
856 TRUEPHY_BIT_CLEAR, 4, 11, NULL);
857
858 if (adapter->RegistryFlowControl == Both)
859 ET1310_PhyAccessMiBit(adapter,
860 TRUEPHY_BIT_SET, 4, 10, NULL);
861 else
862 ET1310_PhyAccessMiBit(adapter,
863 TRUEPHY_BIT_CLEAR, 4, 10, NULL);
864
865 /* Set the phy to autonegotiation */
866 ET1310_PhyAutoNeg(adapter, true);
867
868 /* NOTE - Do we need this? */
869 ET1310_PhyAccessMiBit(adapter, TRUEPHY_BIT_SET, 0, 9, NULL);
870 return status;
871 } else {
872 ET1310_PhyAutoNeg(adapter, false);
873
874 /* Set to the correct force mode. */
875 if (adapter->AiForceDpx != 1) {
876 if (adapter->RegistryFlowControl == TxOnly ||
877 adapter->RegistryFlowControl == Both)
878 ET1310_PhyAccessMiBit(adapter,
879 TRUEPHY_BIT_SET, 4, 11,
880 NULL);
881 else
882 ET1310_PhyAccessMiBit(adapter,
883 TRUEPHY_BIT_CLEAR, 4, 11,
884 NULL);
885
886 if (adapter->RegistryFlowControl == Both)
887 ET1310_PhyAccessMiBit(adapter,
888 TRUEPHY_BIT_SET, 4, 10,
889 NULL);
890 else
891 ET1310_PhyAccessMiBit(adapter,
892 TRUEPHY_BIT_CLEAR, 4, 10,
893 NULL);
894 } else {
895 ET1310_PhyAccessMiBit(adapter,
896 TRUEPHY_BIT_CLEAR, 4, 10, NULL);
897 ET1310_PhyAccessMiBit(adapter,
898 TRUEPHY_BIT_CLEAR, 4, 11, NULL);
899 }
900
901 switch (adapter->AiForceSpeed) {
902 case 10:
903 if (adapter->AiForceDpx == 1)
904 TPAL_SetPhy10HalfDuplex(adapter);
905 else if (adapter->AiForceDpx == 2)
906 TPAL_SetPhy10FullDuplex(adapter);
907 else
908 TPAL_SetPhy10Force(adapter);
909 break;
910 case 100:
911 if (adapter->AiForceDpx == 1)
912 TPAL_SetPhy100HalfDuplex(adapter);
913 else if (adapter->AiForceDpx == 2)
914 TPAL_SetPhy100FullDuplex(adapter);
915 else
916 TPAL_SetPhy100Force(adapter);
917 break;
918 case 1000:
919 TPAL_SetPhy1000FullDuplex(adapter);
920 break;
921 }
922
923 return status;
924 }
925}
926
927void et131x_Mii_check(struct et131x_adapter *etdev,
928 MI_BMSR_t bmsr, MI_BMSR_t bmsr_ints)
929{
930 u8 link_status;
931 u32 autoneg_status;
932 u32 speed;
933 u32 duplex;
934 u32 mdi_mdix;
935 u32 masterslave;
936 u32 polarity;
937 unsigned long flags;
938
939 if (bmsr_ints.bits.link_status) {
940 if (bmsr.bits.link_status) {
941 etdev->PoMgmt.TransPhyComaModeOnBoot = 20;
942
943 /* Update our state variables and indicate the
944 * connected state
945 */
946 spin_lock_irqsave(&etdev->Lock, flags);
947
948 etdev->MediaState = NETIF_STATUS_MEDIA_CONNECT;
949 etdev->Flags &= ~fMP_ADAPTER_LINK_DETECTION;
950
951 spin_unlock_irqrestore(&etdev->Lock, flags);
952
953 netif_carrier_on(etdev->netdev);
954 } else {
955 dev_warn(&etdev->pdev->dev,
956 "Link down - cable problem ?\n");
957
958 if (etdev->linkspeed == TRUEPHY_SPEED_10MBPS) {
959 /* NOTE - Is there a way to query this without
960 * TruePHY?
961 * && TRU_QueryCoreType(etdev->hTruePhy, 0) == EMI_TRUEPHY_A13O) {
962 */
963 u16 Register18;
964
965 MiRead(etdev, 0x12, &Register18);
966 MiWrite(etdev, 0x12, Register18 | 0x4);
967 MiWrite(etdev, 0x10, Register18 | 0x8402);
968 MiWrite(etdev, 0x11, Register18 | 511);
969 MiWrite(etdev, 0x12, Register18);
970 }
971
972 /* For the first N seconds of life, we are in "link
973 * detection" When we are in this state, we should
974 * only report "connected". When the LinkDetection
975 * Timer expires, we can report disconnected (handled
976 * in the LinkDetectionDPC).
977 */
978 if (!(etdev->Flags & fMP_ADAPTER_LINK_DETECTION) ||
979 (etdev->MediaState == NETIF_STATUS_MEDIA_DISCONNECT)) {
980 spin_lock_irqsave(&etdev->Lock, flags);
981 etdev->MediaState =
982 NETIF_STATUS_MEDIA_DISCONNECT;
983 spin_unlock_irqrestore(&etdev->Lock,
984 flags);
985
986 netif_carrier_off(etdev->netdev);
987 }
988
989 etdev->linkspeed = 0;
990 etdev->duplex_mode = 0;
991
992 /* Free the packets being actively sent & stopped */
993 et131x_free_busy_send_packets(etdev);
994
995 /* Re-initialize the send structures */
996 et131x_init_send(etdev);
997
998 /* Reset the RFD list and re-start RU */
999 et131x_reset_recv(etdev);
1000
1001 /*
1002 * Bring the device back to the state it was during
1003 * init prior to autonegotiation being complete. This
1004 * way, when we get the auto-neg complete interrupt,
1005 * we can complete init by calling ConfigMacREGS2.
1006 */
1007 et131x_soft_reset(etdev);
1008
1009 /* Setup ET1310 as per the documentation */
1010 et131x_adapter_setup(etdev);
1011
1012 /* Setup the PHY into coma mode until the cable is
1013 * plugged back in
1014 */
1015 if (etdev->RegistryPhyComa == 1)
1016 EnablePhyComa(etdev);
1017 }
1018 }
1019
1020 if (bmsr_ints.bits.auto_neg_complete ||
1021 (etdev->AiForceDpx == 3 && bmsr_ints.bits.link_status)) {
1022 if (bmsr.bits.auto_neg_complete || etdev->AiForceDpx == 3) {
1023 ET1310_PhyLinkStatus(etdev,
1024 &link_status, &autoneg_status,
1025 &speed, &duplex, &mdi_mdix,
1026 &masterslave, &polarity);
1027
1028 etdev->linkspeed = speed;
1029 etdev->duplex_mode = duplex;
1030
1031 etdev->PoMgmt.TransPhyComaModeOnBoot = 20;
1032
1033 if (etdev->linkspeed == TRUEPHY_SPEED_10MBPS) {
1034 /*
1035 * NOTE - Is there a way to query this without
1036 * TruePHY?
1037 * && TRU_QueryCoreType(etdev->hTruePhy, 0)== EMI_TRUEPHY_A13O) {
1038 */
1039 u16 Register18;
1040
1041 MiRead(etdev, 0x12, &Register18);
1042 MiWrite(etdev, 0x12, Register18 | 0x4);
1043 MiWrite(etdev, 0x10, Register18 | 0x8402);
1044 MiWrite(etdev, 0x11, Register18 | 511);
1045 MiWrite(etdev, 0x12, Register18);
1046 }
1047
1048 ConfigFlowControl(etdev);
1049
1050 if (etdev->linkspeed == TRUEPHY_SPEED_1000MBPS &&
1051 etdev->RegistryJumboPacket > 2048)
1052 ET1310_PhyAndOrReg(etdev, 0x16, 0xcfff,
1053 0x2000);
1054
1055 SetRxDmaTimer(etdev);
1056 ConfigMACRegs2(etdev);
1057 }
1058 }
1059}
1060
758/* 1061/*
759 * The routines which follow provide low-level access to the PHY, and are used 1062 * The routines which follow provide low-level access to the PHY, and are used
760 * primarily by the routines above (although there are a few places elsewhere 1063 * primarily by the routines above (although there are a few places elsewhere
761 * in the driver where this level of access is required). 1064 * in the driver where this level of access is required).
762 */ 1065 */
763 1066
764static const uint16_t ConfigPhy[25][2] = { 1067static const u16 ConfigPhy[25][2] = {
765 /* Reg Value Register */ 1068 /* Reg Value Register */
766 /* Addr */ 1069 /* Addr */
767 {0x880B, 0x0926}, /* AfeIfCreg4B1000Msbs */ 1070 {0x880B, 0x0926}, /* AfeIfCreg4B1000Msbs */
@@ -804,7 +1107,7 @@ static const uint16_t ConfigPhy[25][2] = {
804/* condensed version of the phy initialization routine */ 1107/* condensed version of the phy initialization routine */
805void ET1310_PhyInit(struct et131x_adapter *etdev) 1108void ET1310_PhyInit(struct et131x_adapter *etdev)
806{ 1109{
807 uint16_t data, index; 1110 u16 data, index;
808 1111
809 if (etdev == NULL) 1112 if (etdev == NULL)
810 return; 1113 return;
@@ -869,304 +1172,3 @@ void ET1310_PhyInit(struct et131x_adapter *etdev)
869 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002); 1172 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002);
870} 1173}
871 1174
872void ET1310_PhyReset(struct et131x_adapter *etdev)
873{
874 MiWrite(etdev, PHY_CONTROL, 0x8000);
875}
876
877void ET1310_PhyPowerDown(struct et131x_adapter *etdev, bool down)
878{
879 uint16_t data;
880
881 MiRead(etdev, PHY_CONTROL, &data);
882
883 if (down == false) {
884 /* Power UP */
885 data &= ~0x0800;
886 MiWrite(etdev, PHY_CONTROL, data);
887 } else {
888 /* Power DOWN */
889 data |= 0x0800;
890 MiWrite(etdev, PHY_CONTROL, data);
891 }
892}
893
894void ET1310_PhyAutoNeg(struct et131x_adapter *etdev, bool enable)
895{
896 uint16_t data;
897
898 MiRead(etdev, PHY_CONTROL, &data);
899
900 if (enable == true) {
901 /* Autonegotiation ON */
902 data |= 0x1000;
903 MiWrite(etdev, PHY_CONTROL, data);
904 } else {
905 /* Autonegotiation OFF */
906 data &= ~0x1000;
907 MiWrite(etdev, PHY_CONTROL, data);
908 }
909}
910
911void ET1310_PhyDuplexMode(struct et131x_adapter *etdev, uint16_t duplex)
912{
913 uint16_t data;
914
915 MiRead(etdev, PHY_CONTROL, &data);
916
917 if (duplex == TRUEPHY_DUPLEX_FULL) {
918 /* Set Full Duplex */
919 data |= 0x100;
920 MiWrite(etdev, PHY_CONTROL, data);
921 } else {
922 /* Set Half Duplex */
923 data &= ~0x100;
924 MiWrite(etdev, PHY_CONTROL, data);
925 }
926}
927
928void ET1310_PhySpeedSelect(struct et131x_adapter *etdev, uint16_t speed)
929{
930 uint16_t data;
931
932 /* Read the PHY control register */
933 MiRead(etdev, PHY_CONTROL, &data);
934
935 /* Clear all Speed settings (Bits 6, 13) */
936 data &= ~0x2040;
937
938 /* Reset the speed bits based on user selection */
939 switch (speed) {
940 case TRUEPHY_SPEED_10MBPS:
941 /* Bits already cleared above, do nothing */
942 break;
943
944 case TRUEPHY_SPEED_100MBPS:
945 /* 100M == Set bit 13 */
946 data |= 0x2000;
947 break;
948
949 case TRUEPHY_SPEED_1000MBPS:
950 default:
951 data |= 0x0040;
952 break;
953 }
954
955 /* Write back the new speed */
956 MiWrite(etdev, PHY_CONTROL, data);
957}
958
959void ET1310_PhyAdvertise1000BaseT(struct et131x_adapter *etdev,
960 uint16_t duplex)
961{
962 uint16_t data;
963
964 /* Read the PHY 1000 Base-T Control Register */
965 MiRead(etdev, PHY_1000_CONTROL, &data);
966
967 /* Clear Bits 8,9 */
968 data &= ~0x0300;
969
970 switch (duplex) {
971 case TRUEPHY_ADV_DUPLEX_NONE:
972 /* Duplex already cleared, do nothing */
973 break;
974
975 case TRUEPHY_ADV_DUPLEX_FULL:
976 /* Set Bit 9 */
977 data |= 0x0200;
978 break;
979
980 case TRUEPHY_ADV_DUPLEX_HALF:
981 /* Set Bit 8 */
982 data |= 0x0100;
983 break;
984
985 case TRUEPHY_ADV_DUPLEX_BOTH:
986 default:
987 data |= 0x0300;
988 break;
989 }
990
991 /* Write back advertisement */
992 MiWrite(etdev, PHY_1000_CONTROL, data);
993}
994
995void ET1310_PhyAdvertise100BaseT(struct et131x_adapter *etdev,
996 uint16_t duplex)
997{
998 uint16_t data;
999
1000 /* Read the Autonegotiation Register (10/100) */
1001 MiRead(etdev, PHY_AUTO_ADVERTISEMENT, &data);
1002
1003 /* Clear bits 7,8 */
1004 data &= ~0x0180;
1005
1006 switch (duplex) {
1007 case TRUEPHY_ADV_DUPLEX_NONE:
1008 /* Duplex already cleared, do nothing */
1009 break;
1010
1011 case TRUEPHY_ADV_DUPLEX_FULL:
1012 /* Set Bit 8 */
1013 data |= 0x0100;
1014 break;
1015
1016 case TRUEPHY_ADV_DUPLEX_HALF:
1017 /* Set Bit 7 */
1018 data |= 0x0080;
1019 break;
1020
1021 case TRUEPHY_ADV_DUPLEX_BOTH:
1022 default:
1023 /* Set Bits 7,8 */
1024 data |= 0x0180;
1025 break;
1026 }
1027
1028 /* Write back advertisement */
1029 MiWrite(etdev, PHY_AUTO_ADVERTISEMENT, data);
1030}
1031
1032void ET1310_PhyAdvertise10BaseT(struct et131x_adapter *etdev,
1033 uint16_t duplex)
1034{
1035 uint16_t data;
1036
1037 /* Read the Autonegotiation Register (10/100) */
1038 MiRead(etdev, PHY_AUTO_ADVERTISEMENT, &data);
1039
1040 /* Clear bits 5,6 */
1041 data &= ~0x0060;
1042
1043 switch (duplex) {
1044 case TRUEPHY_ADV_DUPLEX_NONE:
1045 /* Duplex already cleared, do nothing */
1046 break;
1047
1048 case TRUEPHY_ADV_DUPLEX_FULL:
1049 /* Set Bit 6 */
1050 data |= 0x0040;
1051 break;
1052
1053 case TRUEPHY_ADV_DUPLEX_HALF:
1054 /* Set Bit 5 */
1055 data |= 0x0020;
1056 break;
1057
1058 case TRUEPHY_ADV_DUPLEX_BOTH:
1059 default:
1060 /* Set Bits 5,6 */
1061 data |= 0x0060;
1062 break;
1063 }
1064
1065 /* Write back advertisement */
1066 MiWrite(etdev, PHY_AUTO_ADVERTISEMENT, data);
1067}
1068
1069void ET1310_PhyLinkStatus(struct et131x_adapter *etdev,
1070 uint8_t *link_status,
1071 uint32_t *autoneg,
1072 uint32_t *linkspeed,
1073 uint32_t *duplex_mode,
1074 uint32_t *mdi_mdix,
1075 uint32_t *masterslave, uint32_t *polarity)
1076{
1077 uint16_t mistatus = 0;
1078 uint16_t is1000BaseT = 0;
1079 uint16_t vmi_phystatus = 0;
1080 uint16_t control = 0;
1081
1082 MiRead(etdev, PHY_STATUS, &mistatus);
1083 MiRead(etdev, PHY_1000_STATUS, &is1000BaseT);
1084 MiRead(etdev, PHY_PHY_STATUS, &vmi_phystatus);
1085 MiRead(etdev, PHY_CONTROL, &control);
1086
1087 if (link_status) {
1088 *link_status =
1089 (unsigned char)((vmi_phystatus & 0x0040) ? 1 : 0);
1090 }
1091
1092 if (autoneg) {
1093 *autoneg =
1094 (control & 0x1000) ? ((vmi_phystatus & 0x0020) ?
1095 TRUEPHY_ANEG_COMPLETE :
1096 TRUEPHY_ANEG_NOT_COMPLETE) :
1097 TRUEPHY_ANEG_DISABLED;
1098 }
1099
1100 if (linkspeed)
1101 *linkspeed = (vmi_phystatus & 0x0300) >> 8;
1102
1103 if (duplex_mode)
1104 *duplex_mode = (vmi_phystatus & 0x0080) >> 7;
1105
1106 if (mdi_mdix)
1107 /* NOTE: Need to complete this */
1108 *mdi_mdix = 0;
1109
1110 if (masterslave) {
1111 *masterslave =
1112 (is1000BaseT & 0x4000) ? TRUEPHY_CFG_MASTER :
1113 TRUEPHY_CFG_SLAVE;
1114 }
1115
1116 if (polarity) {
1117 *polarity =
1118 (vmi_phystatus & 0x0400) ? TRUEPHY_POLARITY_INVERTED :
1119 TRUEPHY_POLARITY_NORMAL;
1120 }
1121}
1122
1123void ET1310_PhyAndOrReg(struct et131x_adapter *etdev,
1124 uint16_t regnum, uint16_t andMask, uint16_t orMask)
1125{
1126 uint16_t reg;
1127
1128 /* Read the requested register */
1129 MiRead(etdev, regnum, &reg);
1130
1131 /* Apply the AND mask */
1132 reg &= andMask;
1133
1134 /* Apply the OR mask */
1135 reg |= orMask;
1136
1137 /* Write the value back to the register */
1138 MiWrite(etdev, regnum, reg);
1139}
1140
1141void ET1310_PhyAccessMiBit(struct et131x_adapter *etdev, uint16_t action,
1142 uint16_t regnum, uint16_t bitnum, uint8_t *value)
1143{
1144 uint16_t reg;
1145 uint16_t mask = 0;
1146
1147 /* Create a mask to isolate the requested bit */
1148 mask = 0x0001 << bitnum;
1149
1150 /* Read the requested register */
1151 MiRead(etdev, regnum, &reg);
1152
1153 switch (action) {
1154 case TRUEPHY_BIT_READ:
1155 if (value != NULL)
1156 *value = (reg & mask) >> bitnum;
1157 break;
1158
1159 case TRUEPHY_BIT_SET:
1160 reg |= mask;
1161 MiWrite(etdev, regnum, reg);
1162 break;
1163
1164 case TRUEPHY_BIT_CLEAR:
1165 reg &= ~mask;
1166 MiWrite(etdev, regnum, reg);
1167 break;
1168
1169 default:
1170 break;
1171 }
1172}
diff --git a/drivers/staging/et131x/et1310_phy.h b/drivers/staging/et131x/et1310_phy.h
index 6978b25c7e1..0ea12378fda 100644
--- a/drivers/staging/et131x/et1310_phy.h
+++ b/drivers/staging/et131x/et1310_phy.h
@@ -739,25 +739,15 @@ typedef union _MI_LCR2_t {
739/* Forward declaration of the private adapter structure */ 739/* Forward declaration of the private adapter structure */
740struct et131x_adapter; 740struct et131x_adapter;
741 741
742/* OS Specific Functions*/
743void TPAL_SetPhy10HalfDuplex(struct et131x_adapter *adapter);
744void TPAL_SetPhy10FullDuplex(struct et131x_adapter *adapter);
745void TPAL_SetPhy10Force(struct et131x_adapter *pAdapter);
746void TPAL_SetPhy100HalfDuplex(struct et131x_adapter *adapter);
747void TPAL_SetPhy100FullDuplex(struct et131x_adapter *adapter);
748void TPAL_SetPhy100Force(struct et131x_adapter *pAdapter);
749void TPAL_SetPhy1000FullDuplex(struct et131x_adapter *adapter);
750void TPAL_SetPhyAutoNeg(struct et131x_adapter *adapter);
751
752/* Prototypes for ET1310_phy.c */ 742/* Prototypes for ET1310_phy.c */
753int et131x_xcvr_find(struct et131x_adapter *adapter); 743int et131x_xcvr_find(struct et131x_adapter *adapter);
754int et131x_setphy_normal(struct et131x_adapter *adapter); 744int et131x_setphy_normal(struct et131x_adapter *adapter);
755int32_t PhyMiRead(struct et131x_adapter *adapter,
756 u8 xcvrAddr, u8 xcvrReg, u16 *value);
757 745
758/* static inline function does not work because et131x_adapter is not always 746/* static inline function does not work because et131x_adapter is not always
759 * defined 747 * defined
760 */ 748 */
749int PhyMiRead(struct et131x_adapter *adapter, u8 xcvrAddr,
750 u8 xcvrReg, u16 *value);
761#define MiRead(adapter, xcvrReg, value) \ 751#define MiRead(adapter, xcvrReg, value) \
762 PhyMiRead((adapter), (adapter)->Stats.xcvr_addr, (xcvrReg), (value)) 752 PhyMiRead((adapter), (adapter)->Stats.xcvr_addr, (xcvrReg), (value))
763 753
@@ -857,24 +847,8 @@ void SetPhy_10BaseTHalfDuplex(struct et131x_adapter *adapter);
857void ET1310_PhyInit(struct et131x_adapter *adapter); 847void ET1310_PhyInit(struct et131x_adapter *adapter);
858void ET1310_PhyReset(struct et131x_adapter *adapter); 848void ET1310_PhyReset(struct et131x_adapter *adapter);
859void ET1310_PhyPowerDown(struct et131x_adapter *adapter, bool down); 849void ET1310_PhyPowerDown(struct et131x_adapter *adapter, bool down);
860void ET1310_PhyAutoNeg(struct et131x_adapter *adapter, bool enable);
861void ET1310_PhyDuplexMode(struct et131x_adapter *adapter, u16 duplex);
862void ET1310_PhySpeedSelect(struct et131x_adapter *adapter, u16 speed);
863void ET1310_PhyAdvertise1000BaseT(struct et131x_adapter *adapter, 850void ET1310_PhyAdvertise1000BaseT(struct et131x_adapter *adapter,
864 u16 duplex); 851 u16 duplex);
865void ET1310_PhyAdvertise100BaseT(struct et131x_adapter *adapter,
866 u16 duplex);
867void ET1310_PhyAdvertise10BaseT(struct et131x_adapter *adapter,
868 u16 duplex);
869void ET1310_PhyLinkStatus(struct et131x_adapter *adapter,
870 u8 *Link_status,
871 u32 *autoneg,
872 u32 *linkspeed,
873 u32 *duplex_mode,
874 u32 *mdi_mdix,
875 u32 *masterslave, u32 *polarity);
876void ET1310_PhyAndOrReg(struct et131x_adapter *adapter,
877 u16 regnum, u16 andMask, u16 orMask);
878void ET1310_PhyAccessMiBit(struct et131x_adapter *adapter, 852void ET1310_PhyAccessMiBit(struct et131x_adapter *adapter,
879 u16 action, 853 u16 action,
880 u16 regnum, u16 bitnum, u8 *value); 854 u16 regnum, u16 bitnum, u8 *value);
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-20 17:11:45 -0400