Merge branch 'devel-stable' into for-linus

34 files changed, 981 insertions, 723 deletions

diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
new file mode 100644
index 00000000000..f32494dbfe1
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -0,0 +1,77 @@
+* ARM CPUs binding description
+
+The device tree allows to describe the layout of CPUs in a system through
+the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
+defining properties for every cpu.
+
+Bindings for CPU nodes follow the ePAPR standard, available from:
+
+http://devicetree.org
+
+For the ARM architecture every CPU node must contain the following properties:
+
+- device_type:  must be "cpu"
+- reg:          property matching the CPU MPIDR[23:0] register bits
+                reg[31:24] bits must be set to 0
+- compatible:   should be one of:
+                "arm,arm1020"
+                "arm,arm1020e"
+                "arm,arm1022"
+                "arm,arm1026"
+                "arm,arm720"
+                "arm,arm740"
+                "arm,arm7tdmi"
+                "arm,arm920"
+                "arm,arm922"
+                "arm,arm925"
+                "arm,arm926"
+                "arm,arm940"
+                "arm,arm946"
+                "arm,arm9tdmi"
+                "arm,cortex-a5"
+                "arm,cortex-a7"
+                "arm,cortex-a8"
+                "arm,cortex-a9"
+                "arm,cortex-a15"
+                "arm,arm1136"
+                "arm,arm1156"
+                "arm,arm1176"
+                "arm,arm11mpcore"
+                "faraday,fa526"
+                "intel,sa110"
+                "intel,sa1100"
+                "marvell,feroceon"
+                "marvell,mohawk"
+                "marvell,xsc3"
+                "marvell,xscale"
+
+Example:
+
+        cpus {
+                #size-cells = <0>;
+                #address-cells = <1>;
+
+                CPU0: cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x0>;
+                };
+
+                CPU1: cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x1>;
+                };
+
+                CPU2: cpu@100 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x100>;
+                };
+
+                CPU3: cpu@101 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x101>;
+                };
+        };
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index aa526998418..36ae03a3f5d 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -70,6 +70,14 @@ struct gic_chip_data {
 static DEFINE_RAW_SPINLOCK(irq_controller_lock);
 
 /*
+ * The GIC mapping of CPU interfaces does not necessarily match
+ * the logical CPU numbering.  Let's use a mapping as returned
+ * by the GIC itself.
+ */
+#define NR_GIC_CPU_IF 8
+static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
+
+/*
  * Supported arch specific GIC irq extension.
  * Default make them NULL.
  */
@@ -238,11 +246,11 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
         unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
         u32 val, mask, bit;
 
-        if (cpu >= 8 || cpu >= nr_cpu_ids)
+        if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
                 return -EINVAL;
 
         mask = 0xff << shift;
-        bit = 1 << (cpu_logical_map(cpu) + shift);
+        bit = gic_cpu_map[cpu] << shift;
 
         raw_spin_lock(&irq_controller_lock);
         val = readl_relaxed(reg) & ~mask;
@@ -349,11 +357,6 @@ static void __init gic_dist_init(struct gic_chip_data *gic)
         u32 cpumask;
         unsigned int gic_irqs = gic->gic_irqs;
         void __iomem *base = gic_data_dist_base(gic);
-        u32 cpu = cpu_logical_map(smp_processor_id());
-
-        cpumask = 1 << cpu;
-        cpumask |= cpumask << 8;
-        cpumask |= cpumask << 16;
 
         writel_relaxed(0, base + GIC_DIST_CTRL);
 
@@ -366,6 +369,7 @@ static void __init gic_dist_init(struct gic_chip_data *gic)
         /*
          * Set all global interrupts to this CPU only.
          */
+        cpumask = readl_relaxed(base + GIC_DIST_TARGET + 0);
         for (i = 32; i < gic_irqs; i += 4)
                 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
 
@@ -389,9 +393,25 @@ static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
 {
         void __iomem *dist_base = gic_data_dist_base(gic);
         void __iomem *base = gic_data_cpu_base(gic);
+        unsigned int cpu_mask, cpu = smp_processor_id();
         int i;
 
         /*
+         * Get what the GIC says our CPU mask is.
+         */
+        BUG_ON(cpu >= NR_GIC_CPU_IF);
+        cpu_mask = readl_relaxed(dist_base + GIC_DIST_TARGET + 0);
+        gic_cpu_map[cpu] = cpu_mask;