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authorJongpill Lee <boyko.lee@samsung.com>2011-09-26 18:22:11 -0400
committerKukjin Kim <kgene.kim@samsung.com>2011-10-04 05:59:19 -0400
commit0dba4dc4d0bf2bd469b1ae7eae0a6ab26624bfe9 (patch)
tree6ea8c363fe88df4d94bfe40f7025fdaf12f665df
parent0513218222d15e4c3aad20747d21d4007b1c6a95 (diff)
ARM: EXYNOS4: Modify PMU register setting function
This patch modifies PMU register setting function to support the other EXYNOS4 SoCs. Signed-off-by: Jongpill Lee <boyko.lee@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat
-rw-r--r--arch/arm/mach-exynos4/include/mach/pmu.h7
-rw-r--r--arch/arm/mach-exynos4/include/mach/regs-pmu.h1
-rw-r--r--arch/arm/mach-exynos4/pmu.c239
3 files changed, 96 insertions, 151 deletions
diff --git a/arch/arm/mach-exynos4/include/mach/pmu.h b/arch/arm/mach-exynos4/include/mach/pmu.h
index a952904b010..632dd563013 100644
--- a/arch/arm/mach-exynos4/include/mach/pmu.h
+++ b/arch/arm/mach-exynos4/include/mach/pmu.h
@@ -13,6 +13,8 @@
13#ifndef __ASM_ARCH_PMU_H 13#ifndef __ASM_ARCH_PMU_H
14#define __ASM_ARCH_PMU_H __FILE__ 14#define __ASM_ARCH_PMU_H __FILE__
15 15
16#define PMU_TABLE_END NULL
17
16enum sys_powerdown { 18enum sys_powerdown {
17 SYS_AFTR, 19 SYS_AFTR,
18 SYS_LPA, 20 SYS_LPA,
@@ -20,6 +22,11 @@ enum sys_powerdown {
20 NUM_SYS_POWERDOWN, 22 NUM_SYS_POWERDOWN,
21}; 23};
22 24
25struct exynos4_pmu_conf {
26 void __iomem *reg;
27 unsigned int val[NUM_SYS_POWERDOWN];
28};
29
23extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode); 30extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode);
24 31
25#endif /* __ASM_ARCH_PMU_H */ 32#endif /* __ASM_ARCH_PMU_H */
diff --git a/arch/arm/mach-exynos4/include/mach/regs-pmu.h b/arch/arm/mach-exynos4/include/mach/regs-pmu.h
index 125ced2ad2f..f8c7360abff 100644
--- a/arch/arm/mach-exynos4/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-pmu.h
@@ -27,7 +27,6 @@
27#define S5P_USE_STANDBY_WFI1 (1 << 17) 27#define S5P_USE_STANDBY_WFI1 (1 << 17)
28#define S5P_USE_STANDBY_WFE0 (1 << 24) 28#define S5P_USE_STANDBY_WFE0 (1 << 24)
29#define S5P_USE_STANDBY_WFE1 (1 << 25) 29#define S5P_USE_STANDBY_WFE1 (1 << 25)
30#define S5P_USE_MASK ((0x3 << 16) | (0x3 << 24))
31 30
32#define S5P_SWRESET S5P_PMUREG(0x0400) 31#define S5P_SWRESET S5P_PMUREG(0x0400)
33 32
diff --git a/arch/arm/mach-exynos4/pmu.c b/arch/arm/mach-exynos4/pmu.c
index 7ea9eb2a20d..02bfa0d1bb9 100644
--- a/arch/arm/mach-exynos4/pmu.c
+++ b/arch/arm/mach-exynos4/pmu.c
@@ -16,160 +16,99 @@
16#include <mach/regs-clock.h> 16#include <mach/regs-clock.h>
17#include <mach/pmu.h> 17#include <mach/pmu.h>
18 18
19static void __iomem *sys_powerdown_reg[] = { 19static struct exynos4_pmu_conf *exynos4_pmu_config;
20 S5P_ARM_CORE0_LOWPWR,
21 S5P_DIS_IRQ_CORE0,
22 S5P_DIS_IRQ_CENTRAL0,
23 S5P_ARM_CORE1_LOWPWR,
24 S5P_DIS_IRQ_CORE1,
25 S5P_DIS_IRQ_CENTRAL1,
26 S5P_ARM_COMMON_LOWPWR,
27 S5P_L2_0_LOWPWR,
28 S5P_L2_1_LOWPWR,
29 S5P_CMU_ACLKSTOP_LOWPWR,
30 S5P_CMU_SCLKSTOP_LOWPWR,
31 S5P_CMU_RESET_LOWPWR,
32 S5P_APLL_SYSCLK_LOWPWR,
33 S5P_MPLL_SYSCLK_LOWPWR,
34 S5P_VPLL_SYSCLK_LOWPWR,
35 S5P_EPLL_SYSCLK_LOWPWR,
36 S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR,
37 S5P_CMU_RESET_GPSALIVE_LOWPWR,
38 S5P_CMU_CLKSTOP_CAM_LOWPWR,
39 S5P_CMU_CLKSTOP_TV_LOWPWR,
40 S5P_CMU_CLKSTOP_MFC_LOWPWR,
41 S5P_CMU_CLKSTOP_G3D_LOWPWR,
42 S5P_CMU_CLKSTOP_LCD0_LOWPWR,
43 S5P_CMU_CLKSTOP_LCD1_LOWPWR,
44 S5P_CMU_CLKSTOP_MAUDIO_LOWPWR,
45 S5P_CMU_CLKSTOP_GPS_LOWPWR,
46 S5P_CMU_RESET_CAM_LOWPWR,
47 S5P_CMU_RESET_TV_LOWPWR,
48 S5P_CMU_RESET_MFC_LOWPWR,
49 S5P_CMU_RESET_G3D_LOWPWR,
50 S5P_CMU_RESET_LCD0_LOWPWR,
51 S5P_CMU_RESET_LCD1_LOWPWR,
52 S5P_CMU_RESET_MAUDIO_LOWPWR,
53 S5P_CMU_RESET_GPS_LOWPWR,
54 S5P_TOP_BUS_LOWPWR,
55 S5P_TOP_RETENTION_LOWPWR,
56 S5P_TOP_PWR_LOWPWR,
57 S5P_LOGIC_RESET_LOWPWR,
58 S5P_ONENAND_MEM_LOWPWR,
59 S5P_MODIMIF_MEM_LOWPWR,
60 S5P_G2D_ACP_MEM_LOWPWR,
61 S5P_USBOTG_MEM_LOWPWR,
62 S5P_HSMMC_MEM_LOWPWR,
63 S5P_CSSYS_MEM_LOWPWR,
64 S5P_SECSS_MEM_LOWPWR,
65 S5P_PCIE_MEM_LOWPWR,
66 S5P_SATA_MEM_LOWPWR,
67 S5P_PAD_RETENTION_DRAM_LOWPWR,
68 S5P_PAD_RETENTION_MAUDIO_LOWPWR,
69 S5P_PAD_RETENTION_GPIO_LOWPWR,
70 S5P_PAD_RETENTION_UART_LOWPWR,
71 S5P_PAD_RETENTION_MMCA_LOWPWR,
72 S5P_PAD_RETENTION_MMCB_LOWPWR,
73 S5P_PAD_RETENTION_EBIA_LOWPWR,
74 S5P_PAD_RETENTION_EBIB_LOWPWR,
75 S5P_PAD_RETENTION_ISOLATION_LOWPWR,
76 S5P_PAD_RETENTION_ALV_SEL_LOWPWR,
77 S5P_XUSBXTI_LOWPWR,
78 S5P_XXTI_LOWPWR,
79 S5P_EXT_REGULATOR_LOWPWR,
80 S5P_GPIO_MODE_LOWPWR,
81 S5P_GPIO_MODE_MAUDIO_LOWPWR,
82 S5P_CAM_LOWPWR,
83 S5P_TV_LOWPWR,
84 S5P_MFC_LOWPWR,
85 S5P_G3D_LOWPWR,
86 S5P_LCD0_LOWPWR,
87 S5P_LCD1_LOWPWR,
88 S5P_MAUDIO_LOWPWR,
89 S5P_GPS_LOWPWR,
90 S5P_GPS_ALIVE_LOWPWR,
91};
92 20
93static const unsigned int sys_powerdown_val[][NUM_SYS_POWERDOWN] = { 21static struct exynos4_pmu_conf exynos4210_pmu_config[] = {
94 /* { AFTR, LPA, SLEEP }*/ 22 /* { .reg = address, .val = { AFTR, LPA, SLEEP } */
95 { 0, 0, 2 }, /* ARM_CORE0 */ 23 { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
96 { 0, 0, 0 }, /* ARM_DIS_IRQ_CORE0 */ 24 { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } },
97 { 0, 0, 0 }, /* ARM_DIS_IRQ_CENTRAL0 */ 25 { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } },
98 { 0, 0, 2 }, /* ARM_CORE1 */ 26 { S5P_ARM_CORE1_LOWPWR, { 0x0, 0x0, 0x2 } },
99 { 0, 0, 0 }, /* ARM_DIS_IRQ_CORE1 */ 27 { S5P_DIS_IRQ_CORE1, { 0x0, 0x0, 0x0 } },
100 { 0, 0, 0 }, /* ARM_DIS_IRQ_CENTRAL1 */ 28 { S5P_DIS_IRQ_CENTRAL1, { 0x0, 0x0, 0x0 } },
101 { 0, 0, 2 }, /* ARM_COMMON */ 29 { S5P_ARM_COMMON_LOWPWR, { 0x0, 0x0, 0x2 } },
102 { 2, 2, 3 }, /* ARM_CPU_L2_0 */ 30 { S5P_L2_0_LOWPWR, { 0x2, 0x2, 0x3 } },
103 { 2, 2, 3 }, /* ARM_CPU_L2_1 */ 31 { S5P_L2_1_LOWPWR, { 0x2, 0x2, 0x3 } },
104 { 1, 0, 0 }, /* CMU_ACLKSTOP */ 32 { S5P_CMU_ACLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } },
105 { 1, 0, 0 }, /* CMU_SCLKSTOP */ 33 { S5P_CMU_SCLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } },
106 { 1, 1, 0 }, /* CMU_RESET */ 34 { S5P_CMU_RESET_LOWPWR, { 0x1, 0x1, 0x0 } },
107 { 1, 0, 0 }, /* APLL_SYSCLK */ 35 { S5P_APLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
108 { 1, 0, 0 }, /* MPLL_SYSCLK */ 36 { S5P_MPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
109 { 1, 0, 0 }, /* VPLL_SYSCLK */ 37 { S5P_VPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
110 { 1, 1, 0 }, /* EPLL_SYSCLK */ 38 { S5P_EPLL_SYSCLK_LOWPWR, { 0x1, 0x1, 0x0 } },
111 { 1, 1, 0 }, /* CMU_CLKSTOP_GPS_ALIVE */ 39 { S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR, { 0x1, 0x1, 0x0 } },
112 { 1, 1, 0 }, /* CMU_RESET_GPS_ALIVE */ 40 { S5P_CMU_RESET_GPSALIVE_LOWPWR, { 0x1, 0x1, 0x0 } },
113 { 1, 1, 0 }, /* CMU_CLKSTOP_CAM */ 41 { S5P_CMU_CLKSTOP_CAM_LOWPWR, { 0x1, 0x1, 0x0 } },
114 { 1, 1, 0 }, /* CMU_CLKSTOP_TV */ 42 { S5P_CMU_CLKSTOP_TV_LOWPWR, { 0x1, 0x1, 0x0 } },
115 { 1, 1, 0 }, /* CMU_CLKSTOP_MFC */ 43 { S5P_CMU_CLKSTOP_MFC_LOWPWR, { 0x1, 0x1, 0x0 } },
116 { 1, 1, 0 }, /* CMU_CLKSTOP_G3D */ 44 { S5P_CMU_CLKSTOP_G3D_LOWPWR, { 0x1, 0x1, 0x0 } },
117 { 1, 1, 0 }, /* CMU_CLKSTOP_LCD0 */ 45 { S5P_CMU_CLKSTOP_LCD0_LOWPWR, { 0x1, 0x1, 0x0 } },
118 { 1, 1, 0 }, /* CMU_CLKSTOP_LCD1 */ 46 { S5P_CMU_CLKSTOP_LCD1_LOWPWR, { 0x1, 0x1, 0x0 } },
119 { 1, 1, 0 }, /* CMU_CLKSTOP_MAUDIO */ 47 { S5P_CMU_CLKSTOP_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
120 { 1, 1, 0 }, /* CMU_CLKSTOP_GPS */ 48 { S5P_CMU_CLKSTOP_GPS_LOWPWR, { 0x1, 0x1, 0x0 } },
121 { 1, 1, 0 }, /* CMU_RESET_CAM */ 49 { S5P_CMU_RESET_CAM_LOWPWR, { 0x1, 0x1, 0x0 } },
122 { 1, 1, 0 }, /* CMU_RESET_TV */ 50 { S5P_CMU_RESET_TV_LOWPWR, { 0x1, 0x1, 0x0 } },
123 { 1, 1, 0 }, /* CMU_RESET_MFC */ 51 { S5P_CMU_RESET_MFC_LOWPWR, { 0x1, 0x1, 0x0 } },
124 { 1, 1, 0 }, /* CMU_RESET_G3D */ 52 { S5P_CMU_RESET_G3D_LOWPWR, { 0x1, 0x1, 0x0 } },
125 { 1, 1, 0 }, /* CMU_RESET_LCD0 */ 53 { S5P_CMU_RESET_LCD0_LOWPWR, { 0x1, 0x1, 0x0 } },
126 { 1, 1, 0 }, /* CMU_RESET_LCD1 */ 54 { S5P_CMU_RESET_LCD1_LOWPWR, { 0x1, 0x1, 0x0 } },
127 { 1, 1, 0 }, /* CMU_RESET_MAUDIO */ 55 { S5P_CMU_RESET_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
128 { 1, 1, 0 }, /* CMU_RESET_GPS */ 56 { S5P_CMU_RESET_GPS_LOWPWR, { 0x1, 0x1, 0x0 } },
129 { 3, 0, 0 }, /* TOP_BUS */ 57 { S5P_TOP_BUS_LOWPWR, { 0x3, 0x0, 0x0 } },
130 { 1, 0, 1 }, /* TOP_RETENTION */ 58 { S5P_TOP_RETENTION_LOWPWR, { 0x1, 0x0, 0x1 } },
131 { 3, 0, 3 }, /* TOP_PWR */ 59 { S5P_TOP_PWR_LOWPWR, { 0x3, 0x0, 0x3 } },
132 { 1, 1, 0 }, /* LOGIC_RESET */ 60 { S5P_LOGIC_RESET_LOWPWR, { 0x1, 0x1, 0x0 } },
133 { 3, 0, 0 }, /* ONENAND_MEM */ 61 { S5P_ONENAND_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
134 { 3, 0, 0 }, /* MODIMIF_MEM */ 62 { S5P_MODIMIF_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
135 { 3, 0, 0 }, /* G2D_ACP_MEM */ 63 { S5P_G2D_ACP_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
136 { 3, 0, 0 }, /* USBOTG_MEM */ 64 { S5P_USBOTG_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
137 { 3, 0, 0 }, /* HSMMC_MEM */ 65 { S5P_HSMMC_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
138 { 3, 0, 0 }, /* CSSYS_MEM */ 66 { S5P_CSSYS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
139 { 3, 0, 0 }, /* SECSS_MEM */ 67 { S5P_SECSS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
140 { 3, 0, 0 }, /* PCIE_MEM */ 68 { S5P_PCIE_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
141 { 3, 0, 0 }, /* SATA_MEM */ 69 { S5P_SATA_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
142 { 1, 0, 0 }, /* PAD_RETENTION_DRAM */ 70 { S5P_PAD_RETENTION_DRAM_LOWPWR, { 0x1, 0x0, 0x0 } },
143 { 1, 1, 0 }, /* PAD_RETENTION_MAUDIO */ 71 { S5P_PAD_RETENTION_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
144 { 1, 0, 0 }, /* PAD_RETENTION_GPIO */ 72 { S5P_PAD_RETENTION_GPIO_LOWPWR, { 0x1, 0x0, 0x0 } },
145 { 1, 0, 0 }, /* PAD_RETENTION_UART */ 73 { S5P_PAD_RETENTION_UART_LOWPWR, { 0x1, 0x0, 0x0 } },
146 { 1, 0, 0 }, /* PAD_RETENTION_MMCA */ 74 { S5P_PAD_RETENTION_MMCA_LOWPWR, { 0x1, 0x0, 0x0 } },
147 { 1, 0, 0 }, /* PAD_RETENTION_MMCB */ 75 { S5P_PAD_RETENTION_MMCB_LOWPWR, { 0x1, 0x0, 0x0 } },
148 { 1, 0, 0 }, /* PAD_RETENTION_EBIA */ 76 { S5P_PAD_RETENTION_EBIA_LOWPWR, { 0x1, 0x0, 0x0 } },
149 { 1, 0, 0 }, /* PAD_RETENTION_EBIB */ 77 { S5P_PAD_RETENTION_EBIB_LOWPWR, { 0x1, 0x0, 0x0 } },
150 { 1, 0, 0 }, /* PAD_RETENTION_ISOLATION */ 78 { S5P_PAD_RETENTION_ISOLATION_LOWPWR, { 0x1, 0x0, 0x0 } },
151 { 1, 0, 0 }, /* PAD_RETENTION_ALV_SEL */ 79 { S5P_PAD_RETENTION_ALV_SEL_LOWPWR, { 0x1, 0x0, 0x0 } },
152 { 1, 1, 0 }, /* XUSBXTI */ 80 { S5P_XUSBXTI_LOWPWR, { 0x1, 0x1, 0x0 } },
153 { 1, 1, 0 }, /* XXTI */ 81 { S5P_XXTI_LOWPWR, { 0x1, 0x1, 0x0 } },
154 { 1, 1, 0 }, /* EXT_REGULATOR */ 82 { S5P_EXT_REGULATOR_LOWPWR, { 0x1, 0x1, 0x0 } },
155 { 1, 0, 0 }, /* GPIO_MODE */ 83 { S5P_GPIO_MODE_LOWPWR, { 0x1, 0x0, 0x0 } },
156 { 1, 1, 0 }, /* GPIO_MODE_MAUDIO */ 84 { S5P_GPIO_MODE_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
157 { 7, 0, 0 }, /* CAM */ 85 { S5P_CAM_LOWPWR, { 0x7, 0x0, 0x0 } },
158 { 7, 0, 0 }, /* TV */ 86 { S5P_TV_LOWPWR, { 0x7, 0x0, 0x0 } },
159 { 7, 0, 0 }, /* MFC */ 87 { S5P_MFC_LOWPWR, { 0x7, 0x0, 0x0 } },
160 { 7, 0, 0 }, /* G3D */ 88 { S5P_G3D_LOWPWR, { 0x7, 0x0, 0x0 } },
161 { 7, 0, 0 }, /* LCD0 */ 89 { S5P_LCD0_LOWPWR, { 0x7, 0x0, 0x0 } },
162 { 7, 0, 0 }, /* LCD1 */ 90 { S5P_LCD1_LOWPWR, { 0x7, 0x0, 0x0 } },
163 { 7, 7, 0 }, /* MAUDIO */ 91 { S5P_MAUDIO_LOWPWR, { 0x7, 0x7, 0x0 } },
164 { 7, 0, 0 }, /* GPS */ 92 { S5P_GPS_LOWPWR, { 0x7, 0x0, 0x0 } },
165 { 7, 0, 0 }, /* GPS_ALIVE */ 93 { S5P_GPS_ALIVE_LOWPWR, { 0x7, 0x0, 0x0 } },
94 { PMU_TABLE_END,},
166}; 95};
167 96
168void exynos4_sys_powerdown_conf(enum sys_powerdown mode) 97void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
169{ 98{
170 unsigned int count = ARRAY_SIZE(sys_powerdown_reg); 99 unsigned int i;
100
101 for (i = 0; (exynos4_pmu_config[i].reg != PMU_TABLE_END) ; i++)
102 __raw_writel(exynos4_pmu_config[i].val[mode],
103 exynos4_pmu_config[i].reg);
104}
105
106static int __init exynos4_pmu_init(void)
107{
108 exynos4_pmu_config = exynos4210_pmu_config;
109
110 pr_info("EXYNOS4210 PMU Initialize\n");
171 111
172 for (; count > 0; count--) 112 return 0;
173 __raw_writel(sys_powerdown_val[count - 1][mode],
174 sys_powerdown_reg[count - 1]);
175} 113}
114arch_initcall(exynos4_pmu_init);
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-28 07:30:30 -0400