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authorSeungwhan Youn <sw.youn@samsung.com>2010-10-19 05:08:08 -0400
committerKukjin Kim <kgene.kim@samsung.com>2010-10-25 03:10:33 -0400
commit06185c07621263ee1665d4a4e27a9782a677bcf9 (patch)
tree7706d9641e742de8ef5c2a37a5b8d6fae33ee9cd
parent8e0e9e295814d3d514bdfdef72ca271ebe862433 (diff)
ARM: S5P6442: Add DMA operation clock
This patch adds DMA operation clock which is disabled as default. Signed-off-by: Seungwhan Youn <sw.youn@samsung.com> Acked-by: Jassi Brar <jassi.brar@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
-rw-r--r--arch/arm/mach-s5p6442/clock.c28
-rw-r--r--arch/arm/mach-s5p6442/include/mach/regs-clock.h1
2 files changed, 29 insertions, 0 deletions
diff --git a/arch/arm/mach-s5p6442/clock.c b/arch/arm/mach-s5p6442/clock.c
index dcd20f17212..16d6e7e61b5 100644
--- a/arch/arm/mach-s5p6442/clock.c
+++ b/arch/arm/mach-s5p6442/clock.c
@@ -192,6 +192,11 @@ static struct clk clk_pclkd1 = {
192 .parent = &clk_hclkd1, 192 .parent = &clk_hclkd1,
193}; 193};
194 194
195int s5p6442_clk_ip0_ctrl(struct clk *clk, int enable)
196{
197 return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
198}
199
195int s5p6442_clk_ip3_ctrl(struct clk *clk, int enable) 200int s5p6442_clk_ip3_ctrl(struct clk *clk, int enable)
196{ 201{
197 return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable); 202 return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
@@ -335,6 +340,16 @@ void __init_or_cpufreq s5p6442_setup_clocks(void)
335 clk_pclkd1.rate = pclkd1; 340 clk_pclkd1.rate = pclkd1;
336} 341}
337 342
343static struct clk init_clocks_disable[] = {
344 {
345 .name = "pdma",
346 .id = -1,
347 .parent = &clk_pclkd1,
348 .enable = s5p6442_clk_ip0_ctrl,
349 .ctrlbit = (1 << 3),
350 },
351};
352
338static struct clk init_clocks[] = { 353static struct clk init_clocks[] = {
339 { 354 {
340 .name = "systimer", 355 .name = "systimer",
@@ -393,10 +408,23 @@ static struct clk *clks[] __initdata = {
393 408
394void __init s5p6442_register_clocks(void) 409void __init s5p6442_register_clocks(void)
395{ 410{
411 struct clk *clkptr;
412 int i, ret;
413
396 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); 414 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
397 415
398 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); 416 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
399 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); 417 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
400 418
419 clkptr = init_clocks_disable;
420 for (i = 0; i < ARRAY_SIZE(init_clocks_disable); i++, clkptr++) {
421 ret = s3c24xx_register_clock(clkptr);
422 if (ret < 0) {
423 printk(KERN_ERR "Fail to register clock %s (%d)\n",
424 clkptr->name, ret);
425 } else
426 (clkptr->enable)(clkptr, 0);
427 }
428
401 s3c_pwmclk_init(); 429 s3c_pwmclk_init();
402} 430}
diff --git a/arch/arm/mach-s5p6442/include/mach/regs-clock.h b/arch/arm/mach-s5p6442/include/mach/regs-clock.h
index d8360b5d4ec..00828a33699 100644
--- a/arch/arm/mach-s5p6442/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5p6442/include/mach/regs-clock.h
@@ -46,6 +46,7 @@
46#define S5P_CLK_DIV5 S5P_CLKREG(0x314) 46#define S5P_CLK_DIV5 S5P_CLKREG(0x314)
47#define S5P_CLK_DIV6 S5P_CLKREG(0x318) 47#define S5P_CLK_DIV6 S5P_CLKREG(0x318)
48 48
49#define S5P_CLKGATE_IP0 S5P_CLKREG(0x460)
49#define S5P_CLKGATE_IP3 S5P_CLKREG(0x46C) 50#define S5P_CLKGATE_IP3 S5P_CLKREG(0x46C)
50 51
51/* CLK_OUT */ 52/* CLK_OUT */