aboutsummaryrefslogblamecommitdiffstats
path: root/arch/arm/mach-mxc91231/clock.c
blob: ecfa37fef8ade52accc9f14a0839d4f6af9afea0 (plain) (tree)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642

































































































































































































































































































































































































































































































































































































































































                                                                                
#include <linux/clk.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>

#include <mach/clock.h>
#include <mach/hardware.h>
#include <mach/common.h>

#include <asm/clkdev.h>
#include <asm/bug.h>
#include <asm/div64.h>

#include "crm_regs.h"

#define CRM_SMALL_DIVIDER(base, name) \
	crm_small_divider(base, \
			  base ## _ ## name ## _OFFSET, \
			  base ## _ ## name ## _MASK)
#define CRM_1DIVIDER(base, name) \
	crm_divider(base, \
		    base ## _ ## name ## _OFFSET, \
		    base ## _ ## name ## _MASK, 1)
#define CRM_16DIVIDER(base, name) \
	crm_divider(base, \
		    base ## _ ## name ## _OFFSET, \
		    base ## _ ## name ## _MASK, 16)

static u32 crm_small_divider(void __iomem *reg, u8 offset, u32 mask)
{
	static const u32 crm_small_dividers[] = {
		2, 3, 4, 5, 6, 8, 10, 12
	};
	u8 idx;

	idx = (__raw_readl(reg) & mask) >> offset;
	if (idx > 7)
		return 1;

	return crm_small_dividers[idx];
}

static u32 crm_divider(void __iomem *reg, u8 offset, u32 mask, u32 z)
{
	u32 div;
	div = (__raw_readl(reg) & mask) >> offset;
	return div ? div : z;
}

static int _clk_1bit_enable(struct clk *clk)
{
	u32 reg;

	reg = __raw_readl(clk->enable_reg);
	reg |= 1 << clk->enable_shift;
	__raw_writel(reg, clk->enable_reg);

	return 0;
}

static void _clk_1bit_disable(struct clk *clk)
{
	u32 reg;

	reg = __raw_readl(clk->enable_reg);
	reg &= ~(1 << clk->enable_shift);
	__raw_writel(reg, clk->enable_reg);
}

static int _clk_3bit_enable(struct clk *clk)
{
	u32 reg;

	reg = __raw_readl(clk->enable_reg);
	reg |= 0x7 << clk->enable_shift;
	__raw_writel(reg, clk->enable_reg);

	return 0;
}

static void _clk_3bit_disable(struct clk *clk)
{
	u32 reg;

	reg = __raw_readl(clk->enable_reg);
	reg &= ~(0x7 << clk->enable_shift);
	__raw_writel(reg, clk->enable_reg);
}

static unsigned long ckih_rate;

static unsigned long clk_ckih_get_rate(struct clk *clk)
{
	return ckih_rate;
}

static struct clk ckih_clk = {
	.get_rate = clk_ckih_get_rate,
};

static unsigned long clk_ckih_x2_get_rate(struct clk *clk)
{
	return 2 * clk_get_rate(clk->parent);
}

static struct clk ckih_x2_clk = {
	.parent = &ckih_clk,
	.get_rate = clk_ckih_x2_get_rate,
};

static unsigned long clk_ckil_get_rate(struct clk *clk)
{
	return CKIL_CLK_FREQ;
}

static struct clk ckil_clk = {
	.get_rate = clk_ckil_get_rate,
};

/* plls stuff */
static struct clk mcu_pll_clk;
static struct clk dsp_pll_clk;
static struct clk usb_pll_clk;

static struct clk *pll_clk(u8 sel)
{
	switch (sel) {
	case 0:
		return &mcu_pll_clk;
	case 1:
		return &dsp_pll_clk;
	case 2:
		return &usb_pll_clk;
	}
	BUG();
}

static void __iomem *pll_base(struct clk *clk)
{
	if (clk == &mcu_pll_clk)
		return MXC_PLL0_BASE;
	else if (clk == &dsp_pll_clk)
		return MXC_PLL1_BASE;
	else if (clk == &usb_pll_clk)
		return MXC_PLL2_BASE;
	BUG();
}

static unsigned long clk_pll_get_rate(struct clk *clk)
{
	const void __iomem *pllbase;
	unsigned long dp_op, dp_mfd, dp_mfn, pll_hfsm, ref_clk, mfi;
	long mfn, mfn_abs, mfd, pdf;
	s64 temp;
	pllbase = pll_base(clk);

	pll_hfsm = __raw_readl(pllbase + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_HFSM;
	if (pll_hfsm == 0) {
		dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
		dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
		dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
	} else {
		dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);
		dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);
		dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);
	}

	pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
	mfi = (dp_op >> MXC_PLL_DP_OP_MFI_OFFSET) & MXC_PLL_DP_OP_PDF_MASK;
	mfi = (mfi <= 5) ? 5 : mfi;
	mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
	mfn = dp_mfn & MXC_PLL_DP_MFN_MASK;
	mfn = (mfn <= 0x4000000) ? mfn : (mfn - 0x10000000);

	if (mfn < 0)
		mfn_abs = -mfn;
	else
		mfn_abs = mfn;

/* XXX: actually this asumes that ckih is fed to pll, but spec says
 * that ckih_x2 is also possible. need to check this out.
 */
	ref_clk = clk_get_rate(&ckih_clk);

	ref_clk *= 2;
	ref_clk /= pdf + 1;

	temp = (u64) ref_clk * mfn_abs;
	do_div(temp, mfd);
	if (mfn < 0)
		temp = -temp;
	temp += ref_clk * mfi;

	return temp;
}

static int clk_pll_enable(struct clk *clk)
{
	void __iomem *ctl;
	u32 reg;

	ctl = pll_base(clk);
	reg = __raw_readl(ctl);
	reg |= (MXC_PLL_DP_CTL_RST | MXC_PLL_DP_CTL_UPEN);
	__raw_writel(reg, ctl);
	do {
		reg = __raw_readl(ctl);
	} while ((reg & MXC_PLL_DP_CTL_LRF) != MXC_PLL_DP_CTL_LRF);
	return 0;
}

static void clk_pll_disable(struct clk *clk)
{
	void __iomem *ctl;
	u32 reg;

	ctl = pll_base(clk);
	reg = __raw_readl(ctl);
	reg &= ~(MXC_PLL_DP_CTL_RST | MXC_PLL_DP_CTL_UPEN);
	__raw_writel(reg, ctl);
}

static struct clk mcu_pll_clk = {
	.parent = &ckih_clk,
	.get_rate = clk_pll_get_rate,
	.enable = clk_pll_enable,
	.disable = clk_pll_disable,
};

static struct clk dsp_pll_clk = {
	.parent = &ckih_clk,
	.get_rate = clk_pll_get_rate,
	.enable = clk_pll_enable,
	.disable = clk_pll_disable,
};

static struct clk usb_pll_clk = {
	.parent = &ckih_clk,
	.get_rate = clk_pll_get_rate,
	.enable = clk_pll_enable,
	.disable = clk_pll_disable,
};
/* plls stuff end */

/* ap_ref_clk stuff */
static struct clk ap_ref_clk;

static unsigned long clk_ap_ref_get_rate(struct clk *clk)
{
	u32 ascsr, acsr;
	u8 ap_pat_ref_div_2, ap_isel, acs, ads;

	ascsr = __raw_readl(MXC_CRMAP_ASCSR);
	acsr = __raw_readl(MXC_CRMAP_ACSR);

	/* 0 for ckih, 1 for ckih*2 */
	ap_isel = ascsr & MXC_CRMAP_ASCSR_APISEL;
	/* reg divider */
	ap_pat_ref_div_2 = (ascsr >> MXC_CRMAP_ASCSR_AP_PATDIV2_OFFSET) & 0x1;
	/* undocumented, 1 for disabling divider */
	ads = (acsr >> MXC_CRMAP_ACSR_ADS_OFFSET) & 0x1;
	/* 0 for pat_ref, 1 for divider out */
	acs = acsr & MXC_CRMAP_ACSR_ACS;

	if (acs & !ads)
		/* use divided clock */
		return clk_get_rate(clk->parent) / (ap_pat_ref_div_2 ? 2 : 1);

	return clk_get_rate(clk->parent) * (ap_isel ? 2 : 1);
}

static struct clk ap_ref_clk = {
	.parent = &ckih_clk,
	.get_rate = clk_ap_ref_get_rate,
};
/* ap_ref_clk stuff end */

/* ap_pre_dfs_clk stuff */
static struct clk ap_pre_dfs_clk;

static unsigned long clk_ap_pre_dfs_get_rate(struct clk *clk)
{
	u32 acsr, ascsr;

	acsr = __raw_readl(MXC_CRMAP_ACSR);
	ascsr = __raw_readl(MXC_CRMAP_ASCSR);

	if (acsr & MXC_CRMAP_ACSR_ACS) {
		u8 sel;
		sel = (ascsr & MXC_CRMAP_ASCSR_APSEL_MASK) >>
			MXC_CRMAP_ASCSR_APSEL_OFFSET;
		return clk_get_rate(pll_clk(sel)) /
			CRM_SMALL_DIVIDER(MXC_CRMAP_ACDR, ARMDIV);
	}
	return clk_get_rate(&ap_ref_clk);
}

static struct clk ap_pre_dfs_clk = {
	.get_rate = clk_ap_pre_dfs_get_rate,
};
/* ap_pre_dfs_clk stuff end */

/* usb_clk stuff */
static struct clk usb_clk;

static struct clk *clk_usb_parent(struct clk *clk)
{
	u32 acsr, ascsr;

	acsr = __raw_readl(MXC_CRMAP_ACSR);
	ascsr = __raw_readl(MXC_CRMAP_ASCSR);

	if (acsr & MXC_CRMAP_ACSR_ACS) {
		u8 sel;
		sel = (ascsr & MXC_CRMAP_ASCSR_USBSEL_MASK) >>
			MXC_CRMAP_ASCSR_USBSEL_OFFSET;
		return pll_clk(sel);
	}
	return &ap_ref_clk;
}

static unsigned long clk_usb_get_rate(struct clk *clk)
{
	return clk_get_rate(clk->parent) /
		CRM_SMALL_DIVIDER(MXC_CRMAP_ACDER2, USBDIV);
}

static struct clk usb_clk = {
	.enable_reg = MXC_CRMAP_ACDER2,
	.enable_shift = MXC_CRMAP_ACDER2_USBEN_OFFSET,
	.get_rate = clk_usb_get_rate,
	.enable = _clk_1bit_enable,
	.disable = _clk_1bit_disable,
};
/* usb_clk stuff end */

static unsigned long clk_ipg_get_rate(struct clk *clk)
{
	return clk_get_rate(clk->parent) / CRM_16DIVIDER(MXC_CRMAP_ACDR, IPDIV);
}

static unsigned long clk_ahb_get_rate(struct clk *clk)
{
	return clk_get_rate(clk->parent) /
		CRM_16DIVIDER(MXC_CRMAP_ACDR, AHBDIV);
}

static struct clk ipg_clk = {
	.parent = &ap_pre_dfs_clk,
	.get_rate = clk_ipg_get_rate,
};

static struct clk ahb_clk = {
	.parent = &ap_pre_dfs_clk,
	.get_rate = clk_ahb_get_rate,
};

/* perclk_clk stuff */
static struct clk perclk_clk;

static unsigned long clk_perclk_get_rate(struct clk *clk)
{
	u32 acder2;

	acder2 = __raw_readl(MXC_CRMAP_ACDER2);
	if (acder2 & MXC_CRMAP_ACDER2_BAUD_ISEL_MASK)
		return 2 * clk_get_rate(clk->parent);

	return clk_get_rate(clk->parent);
}

static struct clk perclk_clk = {
	.parent = &ckih_clk,
	.get_rate = clk_perclk_get_rate,
};
/* perclk_clk stuff end */

/* uart_clk stuff */
static struct clk uart_clk[];

static unsigned long clk_uart_get_rate(struct clk *clk)
{
	u32 div;

	switch (clk->id) {
	case 0:
	case 1:
		div = CRM_SMALL_DIVIDER(MXC_CRMAP_ACDER2, BAUDDIV);
		break;
	case 2:
		div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRA, UART3DIV);
		break;
	default:
		BUG();
	}
	return clk_get_rate(clk->parent) / div;
}

static struct clk uart_clk[] = {
	{
		.id = 0,
		.parent = &perclk_clk,
		.enable_reg = MXC_CRMAP_APRA,
		.enable_shift = MXC_CRMAP_APRA_UART1EN_OFFSET,
		.get_rate = clk_uart_get_rate,
		.enable = _clk_1bit_enable,
		.disable = _clk_1bit_disable,
	}, {
		.id = 1,
		.parent = &perclk_clk,
		.enable_reg = MXC_CRMAP_APRA,
		.enable_shift = MXC_CRMAP_APRA_UART2EN_OFFSET,
		.get_rate = clk_uart_get_rate,
		.enable = _clk_1bit_enable,
		.disable = _clk_1bit_disable,
	}, {
		.id = 2,
		.parent = &perclk_clk,
		.enable_reg = MXC_CRMAP_APRA,
		.enable_shift = MXC_CRMAP_APRA_UART3EN_OFFSET,
		.get_rate = clk_uart_get_rate,
		.enable = _clk_1bit_enable,
		.disable = _clk_1bit_disable,
	},
};
/* uart_clk stuff end */

/* sdhc_clk stuff */
static struct clk nfc_clk;

static unsigned long clk_nfc_get_rate(struct clk *clk)
{
	return clk_get_rate(clk->parent) /
		CRM_1DIVIDER(MXC_CRMAP_ACDER2, NFCDIV);
}

static struct clk nfc_clk = {
	.parent = &ahb_clk,
	.enable_reg = MXC_CRMAP_ACDER2,
	.enable_shift = MXC_CRMAP_ACDER2_NFCEN_OFFSET,
	.get_rate = clk_nfc_get_rate,
	.enable = _clk_1bit_enable,
	.disable = _clk_1bit_disable,
};
/* sdhc_clk stuff end */

/* sdhc_clk stuff */
static struct clk sdhc_clk[];

static struct clk *clk_sdhc_parent(struct clk *clk)
{
	u32 aprb;
	u8 sel;
	u32 mask;
	int offset;

	aprb = __raw_readl(MXC_CRMAP_APRB);

	switch (clk->id) {
	case 0:
		mask = MXC_CRMAP_APRB_SDHC1_ISEL_MASK;
		offset = MXC_CRMAP_APRB_SDHC1_ISEL_OFFSET;
		break;
	case 1:
		mask = MXC_CRMAP_APRB_SDHC2_ISEL_MASK;
		offset = MXC_CRMAP_APRB_SDHC2_ISEL_OFFSET;
		break;
	default:
		BUG();
	}
	sel = (aprb & mask) >> offset;

	switch (sel) {
	case 0:
		return &ckih_clk;
	case 1:
		return &ckih_x2_clk;
	}
	return &usb_clk;
}

static unsigned long clk_sdhc_get_rate(struct clk *clk)
{
	u32 div;

	switch (clk->id) {
	case 0:
		div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRB, SDHC1_DIV);
		break;
	case 1:
		div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRB, SDHC2_DIV);
		break;
	default:
		BUG();
	}

	return clk_get_rate(clk->parent) / div;
}

static int clk_sdhc_enable(struct clk *clk)
{
	u32 amlpmre1, aprb;

	amlpmre1 = __raw_readl(MXC_CRMAP_AMLPMRE1);
	aprb = __raw_readl(MXC_CRMAP_APRB);
	switch (clk->id) {
	case 0:
		amlpmre1 |= (0x7 << MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET);
		aprb |= (0x1 << MXC_CRMAP_APRB_SDHC1EN_OFFSET);
		break;
	case 1:
		amlpmre1 |= (0x7 << MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET);
		aprb |= (0x1 << MXC_CRMAP_APRB_SDHC2EN_OFFSET);
		break;
	}
	__raw_writel(amlpmre1, MXC_CRMAP_AMLPMRE1);
	__raw_writel(aprb, MXC_CRMAP_APRB);
	return 0;
}

static void clk_sdhc_disable(struct clk *clk)
{
	u32 amlpmre1, aprb;

	amlpmre1 = __raw_readl(MXC_CRMAP_AMLPMRE1);
	aprb = __raw_readl(MXC_CRMAP_APRB);
	switch (clk->id) {
	case 0:
		amlpmre1 &= ~(0x7 << MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET);
		aprb &= ~(0x1 << MXC_CRMAP_APRB_SDHC1EN_OFFSET);
		break;
	case 1:
		amlpmre1 &= ~(0x7 << MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET);
		aprb &= ~(0x1 << MXC_CRMAP_APRB_SDHC2EN_OFFSET);
		break;
	}
	__raw_writel(amlpmre1, MXC_CRMAP_AMLPMRE1);
	__raw_writel(aprb, MXC_CRMAP_APRB);
}

static struct clk sdhc_clk[] = {
	{
		.id = 0,
		.get_rate = clk_sdhc_get_rate,
		.enable = clk_sdhc_enable,
		.disable = clk_sdhc_disable,
	}, {
		.id = 1,
		.get_rate = clk_sdhc_get_rate,
		.enable = clk_sdhc_enable,
		.disable = clk_sdhc_disable,
	},
};
/* sdhc_clk stuff end */

/* wdog_clk stuff */
static struct clk wdog_clk[] = {
	{
		.id = 0,
		.parent = &ipg_clk,
		.enable_reg = MXC_CRMAP_AMLPMRD,
		.enable_shift = MXC_CRMAP_AMLPMRD_MLPMD7_OFFSET,
		.enable = _clk_3bit_enable,
		.disable = _clk_3bit_disable,
	}, {
		.id = 1,
		.parent = &ipg_clk,
		.enable_reg = MXC_CRMAP_AMLPMRD,
		.enable_shift = MXC_CRMAP_AMLPMRD_MLPMD3_OFFSET,
		.enable = _clk_3bit_enable,
		.disable = _clk_3bit_disable,
	},
};
/* wdog_clk stuff end */

/* gpt_clk stuff */
static struct clk gpt_clk = {
	.parent = &ipg_clk,
	.enable_reg = MXC_CRMAP_AMLPMRC,
	.enable_shift = MXC_CRMAP_AMLPMRC_MLPMC4_OFFSET,
	.enable = _clk_3bit_enable,
	.disable = _clk_3bit_disable,
};
/* gpt_clk stuff end */

/* cspi_clk stuff */
static struct clk cspi_clk[] = {
	{
		.id = 0,
		.parent = &ipg_clk,
		.enable_reg = MXC_CRMAP_AMLPMRE2,
		.enable_shift = MXC_CRMAP_AMLPMRE2_MLPME0_OFFSET,
		.enable = _clk_3bit_enable,
		.disable = _clk_3bit_disable,
	}, {
		.id = 1,
		.parent = &ipg_clk,
		.enable_reg = MXC_CRMAP_AMLPMRE1,
		.enable_shift = MXC_CRMAP_AMLPMRE1_MLPME6_OFFSET,
		.enable = _clk_3bit_enable,
		.disable = _clk_3bit_disable,
	},
};
/* cspi_clk stuff end */

#define _REGISTER_CLOCK(d, n, c) \
	{ \
		.dev_id = d, \
		.con_id = n, \
		.clk = &c, \
	},

static struct clk_lookup lookups[] = {
	_REGISTER_CLOCK("imx-uart.0", NULL, uart_clk[0])
	_REGISTER_CLOCK("imx-uart.1", NULL, uart_clk[1])
	_REGISTER_CLOCK("imx-uart.2", NULL, uart_clk[2])
	_REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc_clk[0])
	_REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc_clk[1])
	_REGISTER_CLOCK("mxc-wdt.0", NULL, wdog_clk[0])
	_REGISTER_CLOCK("spi_imx.0", NULL, cspi_clk[0])
	_REGISTER_CLOCK("spi_imx.1", NULL, cspi_clk[1])
};

int __init mxc91231_clocks_init(unsigned long fref)
{
	void __iomem *gpt_base;
	int i;

	ckih_rate = fref;

	usb_clk.parent = clk_usb_parent(&usb_clk);
	sdhc_clk[0].parent = clk_sdhc_parent(&sdhc_clk[0]);
	sdhc_clk[1].parent = clk_sdhc_parent(&sdhc_clk[1]);

	for (i = 0; i < ARRAY_SIZE(lookups); i++)
		clkdev_add(&lookups[i]);

	gpt_base = MXC91231_IO_ADDRESS(MXC91231_GPT1_BASE_ADDR);
	mxc_timer_init(&gpt_clk, gpt_base, MXC91231_INT_GPT);

	return 0;
}