diff options
Diffstat (limited to 'include/linux/ssb/ssb_driver_chipcommon.h')
| -rw-r--r-- | include/linux/ssb/ssb_driver_chipcommon.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/include/linux/ssb/ssb_driver_chipcommon.h b/include/linux/ssb/ssb_driver_chipcommon.h index 4e27acf0a92..2cdf249b4e5 100644 --- a/include/linux/ssb/ssb_driver_chipcommon.h +++ b/include/linux/ssb/ssb_driver_chipcommon.h | |||
| @@ -53,6 +53,7 @@ | |||
| 53 | #define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */ | 53 | #define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */ |
| 54 | #define SSB_CHIPCO_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */ | 54 | #define SSB_CHIPCO_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */ |
| 55 | #define SSB_CHIPCO_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */ | 55 | #define SSB_CHIPCO_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */ |
| 56 | #define SSB_CHIPCO_CAP_SPROM 0x40000000 /* SPROM present */ | ||
| 56 | #define SSB_CHIPCO_CORECTL 0x0008 | 57 | #define SSB_CHIPCO_CORECTL 0x0008 |
| 57 | #define SSB_CHIPCO_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */ | 58 | #define SSB_CHIPCO_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */ |
| 58 | #define SSB_CHIPCO_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */ | 59 | #define SSB_CHIPCO_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */ |
| @@ -385,6 +386,7 @@ | |||
| 385 | 386 | ||
| 386 | 387 | ||
| 387 | /** Chip specific Chip-Status register contents. */ | 388 | /** Chip specific Chip-Status register contents. */ |
| 389 | #define SSB_CHIPCO_CHST_4322_SPROM_EXISTS 0x00000040 /* SPROM present */ | ||
| 388 | #define SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL 0x00000003 | 390 | #define SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL 0x00000003 |
| 389 | #define SSB_CHIPCO_CHST_4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */ | 391 | #define SSB_CHIPCO_CHST_4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */ |
| 390 | #define SSB_CHIPCO_CHST_4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */ | 392 | #define SSB_CHIPCO_CHST_4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */ |
| @@ -398,6 +400,18 @@ | |||
| 398 | #define SSB_CHIPCO_CHST_4325_RCAL_VALUE_SHIFT 4 | 400 | #define SSB_CHIPCO_CHST_4325_RCAL_VALUE_SHIFT 4 |
| 399 | #define SSB_CHIPCO_CHST_4325_PMUTOP_2B 0x00000200 /* 1 for 2b, 0 for to 2a */ | 401 | #define SSB_CHIPCO_CHST_4325_PMUTOP_2B 0x00000200 /* 1 for 2b, 0 for to 2a */ |
| 400 | 402 | ||
| 403 | /** Macros to determine SPROM presence based on Chip-Status register. */ | ||
| 404 | #define SSB_CHIPCO_CHST_4312_SPROM_PRESENT(status) \ | ||
| 405 | ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \ | ||
| 406 | SSB_CHIPCO_CHST_4325_OTP_SEL) | ||
| 407 | #define SSB_CHIPCO_CHST_4322_SPROM_PRESENT(status) \ | ||
| 408 | (status & SSB_CHIPCO_CHST_4322_SPROM_EXISTS) | ||
| 409 | #define SSB_CHIPCO_CHST_4325_SPROM_PRESENT(status) \ | ||
| 410 | (((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \ | ||
| 411 | SSB_CHIPCO_CHST_4325_DEFCIS_SEL) && \ | ||
| 412 | ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \ | ||
| 413 | SSB_CHIPCO_CHST_4325_OTP_SEL)) | ||
| 414 | |||
| 401 | 415 | ||
| 402 | 416 | ||
| 403 | /** Clockcontrol masks and values **/ | 417 | /** Clockcontrol masks and values **/ |
| @@ -564,6 +578,7 @@ struct ssb_chipcommon_pmu { | |||
| 564 | struct ssb_chipcommon { | 578 | struct ssb_chipcommon { |
| 565 | struct ssb_device *dev; | 579 | struct ssb_device *dev; |
| 566 | u32 capabilities; | 580 | u32 capabilities; |
| 581 | u32 status; | ||
| 567 | /* Fast Powerup Delay constant */ | 582 | /* Fast Powerup Delay constant */ |
| 568 | u16 fast_pwrup_delay; | 583 | u16 fast_pwrup_delay; |
| 569 | struct ssb_chipcommon_pmu pmu; | 584 | struct ssb_chipcommon_pmu pmu; |
