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-rw-r--r--drivers/serial/sh-sci.h153
1 files changed, 0 insertions, 153 deletions
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h
index 4bc614e4221..b223d6cbf33 100644
--- a/drivers/serial/sh-sci.h
+++ b/drivers/serial/sh-sci.h
@@ -15,27 +15,17 @@
15 defined(CONFIG_CPU_SUBTYPE_SH7709) 15 defined(CONFIG_CPU_SUBTYPE_SH7709)
16# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */ 16# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
17# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */ 17# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
18# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
19#elif defined(CONFIG_CPU_SUBTYPE_SH7705) 18#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
20# define SCIF0 0xA4400000 19# define SCIF0 0xA4400000
21# define SCIF2 0xA4410000 20# define SCIF2 0xA4410000
22# define SCSMR_Ir 0xA44A0000
23# define IRDA_SCIF SCIF0
24# define SCPCR 0xA4000116 21# define SCPCR 0xA4000116
25# define SCPDR 0xA4000136 22# define SCPDR 0xA4000136
26
27/* Set the clock source,
28 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
29 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
30 */
31# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
32#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 23#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
33 defined(CONFIG_CPU_SUBTYPE_SH7721) || \ 24 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
34 defined(CONFIG_ARCH_SH73A0) || \ 25 defined(CONFIG_ARCH_SH73A0) || \
35 defined(CONFIG_ARCH_SH7367) || \ 26 defined(CONFIG_ARCH_SH7367) || \
36 defined(CONFIG_ARCH_SH7377) || \ 27 defined(CONFIG_ARCH_SH7377) || \
37 defined(CONFIG_ARCH_SH7372) 28 defined(CONFIG_ARCH_SH7372)
38# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
39# define PORT_PTCR 0xA405011EUL 29# define PORT_PTCR 0xA405011EUL
40# define PORT_PVCR 0xA4050122UL 30# define PORT_PVCR 0xA4050122UL
41# define SCIF_ORER 0x0200 /* overrun error bit */ 31# define SCIF_ORER 0x0200 /* overrun error bit */
@@ -43,7 +33,6 @@
43# define SCSPTR1 0xFFE0001C /* 8 bit SCIF */ 33# define SCSPTR1 0xFFE0001C /* 8 bit SCIF */
44# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ 34# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
45# define SCIF_ORER 0x0001 /* overrun error bit */ 35# define SCIF_ORER 0x0001 /* overrun error bit */
46# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
47#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ 36#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
48 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ 37 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
49 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ 38 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
@@ -53,39 +42,31 @@
53# define SCSPTR1 0xffe0001c /* 8 bit SCI */ 42# define SCSPTR1 0xffe0001c /* 8 bit SCI */
54# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ 43# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
55# define SCIF_ORER 0x0001 /* overrun error bit */ 44# define SCIF_ORER 0x0001 /* overrun error bit */
56# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
57 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
58 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
59#elif defined(CONFIG_CPU_SUBTYPE_SH7760) 45#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
60# define SCSPTR0 0xfe600024 /* 16 bit SCIF */ 46# define SCSPTR0 0xfe600024 /* 16 bit SCIF */
61# define SCSPTR1 0xfe610024 /* 16 bit SCIF */ 47# define SCSPTR1 0xfe610024 /* 16 bit SCIF */
62# define SCSPTR2 0xfe620024 /* 16 bit SCIF */ 48# define SCSPTR2 0xfe620024 /* 16 bit SCIF */
63# define SCIF_ORER 0x0001 /* overrun error bit */ 49# define SCIF_ORER 0x0001 /* overrun error bit */
64# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
65#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) 50#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
66# define SCSPTR0 0xA4400000 /* 16 bit SCIF */ 51# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
67# define SCIF_ORER 0x0001 /* overrun error bit */ 52# define SCIF_ORER 0x0001 /* overrun error bit */
68# define PACR 0xa4050100 53# define PACR 0xa4050100
69# define PBCR 0xa4050102 54# define PBCR 0xa4050102
70# define SCSCR_INIT(port) 0x3B
71#elif defined(CONFIG_CPU_SUBTYPE_SH7343) 55#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
72# define SCSPTR0 0xffe00010 /* 16 bit SCIF */ 56# define SCSPTR0 0xffe00010 /* 16 bit SCIF */
73# define SCSPTR1 0xffe10010 /* 16 bit SCIF */ 57# define SCSPTR1 0xffe10010 /* 16 bit SCIF */
74# define SCSPTR2 0xffe20010 /* 16 bit SCIF */ 58# define SCSPTR2 0xffe20010 /* 16 bit SCIF */
75# define SCSPTR3 0xffe30010 /* 16 bit SCIF */ 59# define SCSPTR3 0xffe30010 /* 16 bit SCIF */
76# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
77#elif defined(CONFIG_CPU_SUBTYPE_SH7722) 60#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
78# define PADR 0xA4050120 61# define PADR 0xA4050120
79# define PSDR 0xA405013e 62# define PSDR 0xA405013e
80# define PWDR 0xA4050166 63# define PWDR 0xA4050166
81# define PSCR 0xA405011E 64# define PSCR 0xA405011E
82# define SCIF_ORER 0x0001 /* overrun error bit */ 65# define SCIF_ORER 0x0001 /* overrun error bit */
83# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
84#elif defined(CONFIG_CPU_SUBTYPE_SH7366) 66#elif defined(CONFIG_CPU_SUBTYPE_SH7366)
85# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */ 67# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
86# define SCSPTR0 SCPDR0 68# define SCSPTR0 SCPDR0
87# define SCIF_ORER 0x0001 /* overrun error bit */ 69# define SCIF_ORER 0x0001 /* overrun error bit */
88# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
89#elif defined(CONFIG_CPU_SUBTYPE_SH7723) 70#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
90# define SCSPTR0 0xa4050160 71# define SCSPTR0 0xa4050160
91# define SCSPTR1 0xa405013e 72# define SCSPTR1 0xa405013e
@@ -94,62 +75,38 @@
94# define SCSPTR4 0xa4050128 75# define SCSPTR4 0xa4050128
95# define SCSPTR5 0xa4050128 76# define SCSPTR5 0xa4050128
96# define SCIF_ORER 0x0001 /* overrun error bit */ 77# define SCIF_ORER 0x0001 /* overrun error bit */
97# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
98#elif defined(CONFIG_CPU_SUBTYPE_SH7724) 78#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
99# define SCIF_ORER 0x0001 /* overrun error bit */ 79# define SCIF_ORER 0x0001 /* overrun error bit */
100# define SCSCR_INIT(port) ((port)->type == PORT_SCIFA ? \
101 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
102 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
103#elif defined(CONFIG_CPU_SUBTYPE_SH4_202) 80#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
104# define SCSPTR2 0xffe80020 /* 16 bit SCIF */ 81# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
105# define SCIF_ORER 0x0001 /* overrun error bit */ 82# define SCIF_ORER 0x0001 /* overrun error bit */
106# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
107#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) 83#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
108# define SCIF_BASE_ADDR 0x01030000
109# define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
110# define SCIF_PTR2_OFFS 0x0000020 84# define SCIF_PTR2_OFFS 0x0000020
111# define SCIF_LSR2_OFFS 0x0000024
112# define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */ 85# define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
113# define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
114# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
115#elif defined(CONFIG_H83007) || defined(CONFIG_H83068) 86#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
116# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
117# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) 87# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
118#elif defined(CONFIG_H8S2678) 88#elif defined(CONFIG_H8S2678)
119# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
120# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) 89# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
121#elif defined(CONFIG_CPU_SUBTYPE_SH7757) 90#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
122# define SCSPTR0 0xfe4b0020 91# define SCSPTR0 0xfe4b0020
123# define SCSPTR1 0xfe4b0020 92# define SCSPTR1 0xfe4b0020
124# define SCSPTR2 0xfe4b0020 93# define SCSPTR2 0xfe4b0020
125# define SCIF_ORER 0x0001 94# define SCIF_ORER 0x0001
126# define SCSCR_INIT(port) 0x38
127# define SCIF_ONLY 95# define SCIF_ONLY
128#elif defined(CONFIG_CPU_SUBTYPE_SH7763) 96#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
129# define SCSPTR0 0xffe00024 /* 16 bit SCIF */ 97# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
130# define SCSPTR1 0xffe08024 /* 16 bit SCIF */ 98# define SCSPTR1 0xffe08024 /* 16 bit SCIF */
131# define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */ 99# define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */
132# define SCIF_ORER 0x0001 /* overrun error bit */ 100# define SCIF_ORER 0x0001 /* overrun error bit */
133# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
134#elif defined(CONFIG_CPU_SUBTYPE_SH7770) 101#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
135# define SCSPTR0 0xff923020 /* 16 bit SCIF */ 102# define SCSPTR0 0xff923020 /* 16 bit SCIF */
136# define SCSPTR1 0xff924020 /* 16 bit SCIF */ 103# define SCSPTR1 0xff924020 /* 16 bit SCIF */
137# define SCSPTR2 0xff925020 /* 16 bit SCIF */ 104# define SCSPTR2 0xff925020 /* 16 bit SCIF */
138# define SCIF_ORER 0x0001 /* overrun error bit */ 105# define SCIF_ORER 0x0001 /* overrun error bit */
139# define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
140#elif defined(CONFIG_CPU_SUBTYPE_SH7780) 106#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
141# define SCSPTR0 0xffe00024 /* 16 bit SCIF */ 107# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
142# define SCSPTR1 0xffe10024 /* 16 bit SCIF */ 108# define SCSPTR1 0xffe10024 /* 16 bit SCIF */
143# define SCIF_ORER 0x0001 /* Overrun error bit */ 109# define SCIF_ORER 0x0001 /* Overrun error bit */
144
145#if defined(CONFIG_SH_SH2007)
146/* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=0 */
147# define SCSCR_INIT(port) 0x38
148#else
149/* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=1 */
150# define SCSCR_INIT(port) 0x3a
151#endif
152
153#elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \ 110#elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \
154 defined(CONFIG_CPU_SUBTYPE_SH7786) 111 defined(CONFIG_CPU_SUBTYPE_SH7786)
155# define SCSPTR0 0xffea0024 /* 16 bit SCIF */ 112# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
@@ -159,7 +116,6 @@
159# define SCSPTR4 0xffee0024 /* 16 bit SCIF */ 116# define SCSPTR4 0xffee0024 /* 16 bit SCIF */
160# define SCSPTR5 0xffef0024 /* 16 bit SCIF */ 117# define SCSPTR5 0xffef0024 /* 16 bit SCIF */
161# define SCIF_ORER 0x0001 /* Overrun error bit */ 118# define SCIF_ORER 0x0001 /* Overrun error bit */
162# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
163#elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \ 119#elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \
164 defined(CONFIG_CPU_SUBTYPE_SH7203) || \ 120 defined(CONFIG_CPU_SUBTYPE_SH7203) || \
165 defined(CONFIG_CPU_SUBTYPE_SH7206) || \ 121 defined(CONFIG_CPU_SUBTYPE_SH7206) || \
@@ -174,52 +130,21 @@
174# define SCSPTR6 0xfffeB020 /* 16 bit SCIF */ 130# define SCSPTR6 0xfffeB020 /* 16 bit SCIF */
175# define SCSPTR7 0xfffeB820 /* 16 bit SCIF */ 131# define SCSPTR7 0xfffeB820 /* 16 bit SCIF */
176# endif 132# endif
177# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
178#elif defined(CONFIG_CPU_SUBTYPE_SH7619) 133#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
179# define SCSPTR0 0xf8400020 /* 16 bit SCIF */ 134# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
180# define SCSPTR1 0xf8410020 /* 16 bit SCIF */ 135# define SCSPTR1 0xf8410020 /* 16 bit SCIF */
181# define SCSPTR2 0xf8420020 /* 16 bit SCIF */ 136# define SCSPTR2 0xf8420020 /* 16 bit SCIF */
182# define SCIF_ORER 0x0001 /* overrun error bit */ 137# define SCIF_ORER 0x0001 /* overrun error bit */
183# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
184#elif defined(CONFIG_CPU_SUBTYPE_SHX3) 138#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
185# define SCSPTR0 0xffc30020 /* 16 bit SCIF */ 139# define SCSPTR0 0xffc30020 /* 16 bit SCIF */
186# define SCSPTR1 0xffc40020 /* 16 bit SCIF */ 140# define SCSPTR1 0xffc40020 /* 16 bit SCIF */
187# define SCSPTR2 0xffc50020 /* 16 bit SCIF */ 141# define SCSPTR2 0xffc50020 /* 16 bit SCIF */
188# define SCSPTR3 0xffc60020 /* 16 bit SCIF */ 142# define SCSPTR3 0xffc60020 /* 16 bit SCIF */
189# define SCIF_ORER 0x0001 /* Overrun error bit */ 143# define SCIF_ORER 0x0001 /* Overrun error bit */
190# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
191#else 144#else
192# error CPU subtype not defined 145# error CPU subtype not defined
193#endif 146#endif
194 147
195/* SCSCR */
196#define SCI_CTRL_FLAGS_TIE 0x80 /* all */
197#define SCI_CTRL_FLAGS_RIE 0x40 /* all */
198#define SCI_CTRL_FLAGS_TE 0x20 /* all */
199#define SCI_CTRL_FLAGS_RE 0x10 /* all */
200#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
201 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
202 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
203 defined(CONFIG_CPU_SUBTYPE_SH7722) || \
204 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
205 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
206 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
207 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
208 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
209 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
210 defined(CONFIG_CPU_SUBTYPE_SH7786) || \
211 defined(CONFIG_CPU_SUBTYPE_SHX3)
212#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
213#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
214#define SCI_CTRL_FLAGS_REIE ((port)->type == PORT_SCIFA ? 0 : 8)
215#else
216#define SCI_CTRL_FLAGS_REIE 0
217#endif
218/* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
219/* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
220/* SCI_CTRL_FLAGS_CKE1 0x02 * all */
221/* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
222
223/* SCxSR SCI */ 148/* SCxSR SCI */
224#define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 149#define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
225#define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 150#define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
@@ -300,23 +225,11 @@
300/* SCFCR */ 225/* SCFCR */
301#define SCFCR_RFRST 0x0002 226#define SCFCR_RFRST 0x0002
302#define SCFCR_TFRST 0x0004 227#define SCFCR_TFRST 0x0004
303#define SCFCR_TCRST 0x4000
304#define SCFCR_MCE 0x0008 228#define SCFCR_MCE 0x0008
305 229
306#define SCI_MAJOR 204 230#define SCI_MAJOR 204
307#define SCI_MINOR_START 8 231#define SCI_MINOR_START 8
308 232
309/* Generic serial flags */
310#define SCI_RX_THROTTLE 0x0000001
311
312#define SCI_MAGIC 0xbabeface
313
314/*
315 * Events are used to schedule things to happen at timer-interrupt
316 * time, instead of at rs interrupt time.
317 */
318#define SCI_EVENT_WRITE_WAKEUP 0
319
320#define SCI_IN(size, offset) \ 233#define SCI_IN(size, offset) \
321 if ((size) == 8) { \ 234 if ((size) == 8) { \
322 return ioread8(port->membase + (offset)); \ 235 return ioread8(port->membase + (offset)); \
@@ -445,8 +358,6 @@
445SCIF_FNS(SCSMR, 0x00, 16) 358SCIF_FNS(SCSMR, 0x00, 16)
446SCIF_FNS(SCBRR, 0x04, 8) 359SCIF_FNS(SCBRR, 0x04, 8)
447SCIF_FNS(SCSCR, 0x08, 16) 360SCIF_FNS(SCSCR, 0x08, 16)
448SCIF_FNS(SCTDSR, 0x0c, 8)
449SCIF_FNS(SCFER, 0x10, 16)
450SCIF_FNS(SCxSR, 0x14, 16) 361SCIF_FNS(SCxSR, 0x14, 16)
451SCIF_FNS(SCFCR, 0x18, 16) 362SCIF_FNS(SCFCR, 0x18, 16)
452SCIF_FNS(SCFDR, 0x1c, 16) 363SCIF_FNS(SCFDR, 0x1c, 16)
@@ -476,8 +387,6 @@ SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8)
476SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16) 387SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16)
477SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8) 388SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8)
478SCIx_FNS(SCSPTR, 0, 0, 0, 0) 389SCIx_FNS(SCSPTR, 0, 0, 0, 0)
479SCIF_FNS(SCTDSR, 0x0c, 8)
480SCIF_FNS(SCFER, 0x10, 16)
481SCIF_FNS(SCFCR, 0x18, 16) 390SCIF_FNS(SCFCR, 0x18, 16)
482SCIF_FNS(SCFDR, 0x1c, 16) 391SCIF_FNS(SCFDR, 0x1c, 16)
483SCIF_FNS(SCLSR, 0x24, 16) 392SCIF_FNS(SCLSR, 0x24, 16)
@@ -503,7 +412,6 @@ SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
503#elif defined(CONFIG_CPU_SUBTYPE_SH7763) 412#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
504SCIF_FNS(SCFDR, 0, 0, 0x1C, 16) 413SCIF_FNS(SCFDR, 0, 0, 0x1C, 16)
505SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16) 414SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16)
506SCIF_FNS(SCLSR2, 0, 0, 0x24, 16)
507SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) 415SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
508SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) 416SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
509SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) 417SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
@@ -597,64 +505,3 @@ static inline int sci_rxd_in(struct uart_port *port)
597 return 1; 505 return 1;
598} 506}
599#endif 507#endif
600
601/*
602 * Values for the BitRate Register (SCBRR)
603 *
604 * The values are actually divisors for a frequency which can
605 * be internal to the SH3 (14.7456MHz) or derived from an external
606 * clock source. This driver assumes the internal clock is used;
607 * to support using an external clock source, config options or
608 * possibly command-line options would need to be added.
609 *
610 * Also, to support speeds below 2400 (why?) the lower 2 bits of
611 * the SCSMR register would also need to be set to non-zero values.
612 *
613 * -- Greg Banks 27Feb2000
614 *
615 * Answer: The SCBRR register is only eight bits, and the value in
616 * it gets larger with lower baud rates. At around 2400 (depending on
617 * the peripherial module clock) you run out of bits. However the
618 * lower two bits of SCSMR allow the module clock to be divided down,
619 * scaling the value which is needed in SCBRR.
620 *
621 * -- Stuart Menefy - 23 May 2000
622 *
623 * I meant, why would anyone bother with bitrates below 2400.
624 *
625 * -- Greg Banks - 7Jul2000
626 *
627 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper
628 * tape reader as a console!
629 *
630 * -- Mitch Davis - 15 Jul 2000
631 */
632
633#if (defined(CONFIG_CPU_SUBTYPE_SH7780) || \
634 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
635 defined(CONFIG_CPU_SUBTYPE_SH7786)) && \
636 !defined(CONFIG_SH_SH2007)
637#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
638#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
639 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
640 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
641 defined(CONFIG_ARCH_SH73A0) || \
642 defined(CONFIG_ARCH_SH7367) || \
643 defined(CONFIG_ARCH_SH7377) || \
644 defined(CONFIG_ARCH_SH7372)
645#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
646#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
647 defined(CONFIG_CPU_SUBTYPE_SH7724)
648static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
649{
650 if (port->type == PORT_SCIF)
651 return (clk+16*bps)/(32*bps)-1;
652 else
653 return ((clk*2)+16*bps)/(16*bps)-1;
654}
655#define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
656#elif defined(__H8300H__) || defined(__H8300S__)
657#define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
658#else /* Generic SH */
659#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
660#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-25 15:20:21 -0400