1 files changed, 8 insertions, 20 deletions

diff --git a/drivers/net/wireless/rt2x00/rt2800pci.c b/drivers/net/wireless/rt2x00/rt2800pci.c
index 55cd3e1f75b..dab7dc16a6c 100644
--- a/drivers/net/wireless/rt2x00/rt2800pci.c
+++ b/drivers/net/wireless/rt2x00/rt2800pci.c
@@ -426,7 +426,6 @@ static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
 static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
                                  enum dev_state state)
 {
-        int mask = (state == STATE_RADIO_IRQ_ON);
         u32 reg;
         unsigned long flags;
 
@@ -448,25 +447,14 @@ static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
         }
 
         spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
-        rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
-        rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, 0);
-        rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, 0);
-        rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
-        rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, 0);
-        rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, 0);
-        rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, 0);
-        rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, 0);
-        rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, 0);
-        rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, 0);
-        rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, 0);
-        rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, 0);
-        rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
-        rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
-        rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
-        rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
-        rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, 0);
-        rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, 0);
-        rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, 0);
+        reg = 0;
+        if (state == STATE_RADIO_IRQ_ON) {
+                rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, 1);
+                rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, 1);
+                rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, 1);
+                rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, 1);
+                rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, 1);
+        }
         rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
         spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);