aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/i915/intel_display.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c725
1 files changed, 379 insertions, 346 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5ec10e02341..40cc5da264a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -29,6 +29,7 @@
29#include <linux/i2c.h> 29#include <linux/i2c.h>
30#include <linux/kernel.h> 30#include <linux/kernel.h>
31#include <linux/slab.h> 31#include <linux/slab.h>
32#include <linux/vgaarb.h>
32#include "drmP.h" 33#include "drmP.h"
33#include "intel_drv.h" 34#include "intel_drv.h"
34#include "i915_drm.h" 35#include "i915_drm.h"
@@ -976,14 +977,70 @@ intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
976 return true; 977 return true;
977} 978}
978 979
979void 980/**
980intel_wait_for_vblank(struct drm_device *dev) 981 * intel_wait_for_vblank - wait for vblank on a given pipe
982 * @dev: drm device
983 * @pipe: pipe to wait for
984 *
985 * Wait for vblank to occur on a given pipe. Needed for various bits of
986 * mode setting code.
987 */
988void intel_wait_for_vblank(struct drm_device *dev, int pipe)
981{ 989{
982 /* Wait for 20ms, i.e. one cycle at 50hz. */ 990 struct drm_i915_private *dev_priv = dev->dev_private;
983 if (in_dbg_master()) 991 int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
984 mdelay(20); /* The kernel debugger cannot call msleep() */ 992
985 else 993 /* Clear existing vblank status. Note this will clear any other
986 msleep(20); 994 * sticky status fields as well.
995 *
996 * This races with i915_driver_irq_handler() with the result
997 * that either function could miss a vblank event. Here it is not
998 * fatal, as we will either wait upon the next vblank interrupt or
999 * timeout. Generally speaking intel_wait_for_vblank() is only
1000 * called during modeset at which time the GPU should be idle and
1001 * should *not* be performing page flips and thus not waiting on
1002 * vblanks...
1003 * Currently, the result of us stealing a vblank from the irq
1004 * handler is that a single frame will be skipped during swapbuffers.
1005 */
1006 I915_WRITE(pipestat_reg,
1007 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1008
1009 /* Wait for vblank interrupt bit to set */
1010 if (wait_for((I915_READ(pipestat_reg) &
1011 PIPE_VBLANK_INTERRUPT_STATUS),
1012 50, 0))
1013 DRM_DEBUG_KMS("vblank wait timed out\n");
1014}
1015
1016/**
1017 * intel_wait_for_vblank_off - wait for vblank after disabling a pipe
1018 * @dev: drm device
1019 * @pipe: pipe to wait for
1020 *
1021 * After disabling a pipe, we can't wait for vblank in the usual way,
1022 * spinning on the vblank interrupt status bit, since we won't actually
1023 * see an interrupt when the pipe is disabled.
1024 *
1025 * So this function waits for the display line value to settle (it
1026 * usually ends up stopping at the start of the next frame).
1027 */
1028void intel_wait_for_vblank_off(struct drm_device *dev, int pipe)
1029{
1030 struct drm_i915_private *dev_priv = dev->dev_private;
1031 int pipedsl_reg = (pipe == 0 ? PIPEADSL : PIPEBDSL);
1032 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1033 u32 last_line;
1034
1035 /* Wait for the display line to settle */
1036 do {
1037 last_line = I915_READ(pipedsl_reg) & DSL_LINEMASK;
1038 mdelay(5);
1039 } while (((I915_READ(pipedsl_reg) & DSL_LINEMASK) != last_line) &&
1040 time_after(timeout, jiffies));
1041
1042 if (time_after(jiffies, timeout))
1043 DRM_DEBUG_KMS("vblank wait timed out\n");
987} 1044}
988 1045
989/* Parameters have changed, update FBC info */ 1046/* Parameters have changed, update FBC info */
@@ -1037,7 +1094,6 @@ static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1037void i8xx_disable_fbc(struct drm_device *dev) 1094void i8xx_disable_fbc(struct drm_device *dev)
1038{ 1095{
1039 struct drm_i915_private *dev_priv = dev->dev_private; 1096 struct drm_i915_private *dev_priv = dev->dev_private;
1040 unsigned long timeout = jiffies + msecs_to_jiffies(1);
1041 u32 fbc_ctl; 1097 u32 fbc_ctl;
1042 1098
1043 if (!I915_HAS_FBC(dev)) 1099 if (!I915_HAS_FBC(dev))
@@ -1052,16 +1108,11 @@ void i8xx_disable_fbc(struct drm_device *dev)
1052 I915_WRITE(FBC_CONTROL, fbc_ctl); 1108 I915_WRITE(FBC_CONTROL, fbc_ctl);
1053 1109
1054 /* Wait for compressing bit to clear */ 1110 /* Wait for compressing bit to clear */
1055 while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) { 1111 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10, 0)) {
1056 if (time_after(jiffies, timeout)) { 1112 DRM_DEBUG_KMS("FBC idle timed out\n");
1057 DRM_DEBUG_DRIVER("FBC idle timed out\n"); 1113 return;
1058 break;
1059 }
1060 ; /* do nothing */
1061 } 1114 }
1062 1115
1063 intel_wait_for_vblank(dev);
1064
1065 DRM_DEBUG_KMS("disabled FBC\n"); 1116 DRM_DEBUG_KMS("disabled FBC\n");
1066} 1117}
1067 1118
@@ -1118,7 +1169,6 @@ void g4x_disable_fbc(struct drm_device *dev)
1118 dpfc_ctl = I915_READ(DPFC_CONTROL); 1169 dpfc_ctl = I915_READ(DPFC_CONTROL);
1119 dpfc_ctl &= ~DPFC_CTL_EN; 1170 dpfc_ctl &= ~DPFC_CTL_EN;
1120 I915_WRITE(DPFC_CONTROL, dpfc_ctl); 1171 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1121 intel_wait_for_vblank(dev);
1122 1172
1123 DRM_DEBUG_KMS("disabled FBC\n"); 1173 DRM_DEBUG_KMS("disabled FBC\n");
1124} 1174}
@@ -1179,7 +1229,6 @@ void ironlake_disable_fbc(struct drm_device *dev)
1179 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); 1229 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1180 dpfc_ctl &= ~DPFC_CTL_EN; 1230 dpfc_ctl &= ~DPFC_CTL_EN;
1181 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); 1231 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1182 intel_wait_for_vblank(dev);
1183 1232
1184 DRM_DEBUG_KMS("disabled FBC\n"); 1233 DRM_DEBUG_KMS("disabled FBC\n");
1185} 1234}
@@ -1453,7 +1502,7 @@ intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1453 dspcntr &= ~DISPPLANE_TILED; 1502 dspcntr &= ~DISPPLANE_TILED;
1454 } 1503 }
1455 1504
1456 if (IS_IRONLAKE(dev)) 1505 if (HAS_PCH_SPLIT(dev))
1457 /* must disable */ 1506 /* must disable */
1458 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; 1507 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1459 1508
@@ -1462,23 +1511,22 @@ intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1462 Start = obj_priv->gtt_offset; 1511 Start = obj_priv->gtt_offset;
1463 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8); 1512 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1464 1513
1465 DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y); 1514 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1515 Start, Offset, x, y, fb->pitch);
1466 I915_WRITE(dspstride, fb->pitch); 1516 I915_WRITE(dspstride, fb->pitch);
1467 if (IS_I965G(dev)) { 1517 if (IS_I965G(dev)) {
1468 I915_WRITE(dspbase, Offset);
1469 I915_READ(dspbase);
1470 I915_WRITE(dspsurf, Start); 1518 I915_WRITE(dspsurf, Start);
1471 I915_READ(dspsurf);
1472 I915_WRITE(dsptileoff, (y << 16) | x); 1519 I915_WRITE(dsptileoff, (y << 16) | x);
1520 I915_WRITE(dspbase, Offset);
1473 } else { 1521 } else {
1474 I915_WRITE(dspbase, Start + Offset); 1522 I915_WRITE(dspbase, Start + Offset);
1475 I915_READ(dspbase);
1476 } 1523 }
1524 POSTING_READ(dspbase);
1477 1525
1478 if ((IS_I965G(dev) || plane == 0)) 1526 if (IS_I965G(dev) || plane == 0)
1479 intel_update_fbc(crtc, &crtc->mode); 1527 intel_update_fbc(crtc, &crtc->mode);
1480 1528
1481 intel_wait_for_vblank(dev); 1529 intel_wait_for_vblank(dev, intel_crtc->pipe);
1482 intel_increase_pllclock(crtc, true); 1530 intel_increase_pllclock(crtc, true);
1483 1531
1484 return 0; 1532 return 0;
@@ -1489,7 +1537,6 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1489 struct drm_framebuffer *old_fb) 1537 struct drm_framebuffer *old_fb)
1490{ 1538{
1491 struct drm_device *dev = crtc->dev; 1539 struct drm_device *dev = crtc->dev;
1492 struct drm_i915_private *dev_priv = dev->dev_private;
1493 struct drm_i915_master_private *master_priv; 1540 struct drm_i915_master_private *master_priv;
1494 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1541 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1495 struct intel_framebuffer *intel_fb; 1542 struct intel_framebuffer *intel_fb;
@@ -1497,13 +1544,6 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1497 struct drm_gem_object *obj; 1544 struct drm_gem_object *obj;
1498 int pipe = intel_crtc->pipe; 1545 int pipe = intel_crtc->pipe;
1499 int plane = intel_crtc->plane; 1546 int plane = intel_crtc->plane;
1500 unsigned long Start, Offset;
1501 int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1502 int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1503 int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1504 int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1505 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1506 u32 dspcntr;
1507 int ret; 1547 int ret;
1508 1548
1509 /* no fb bound */ 1549 /* no fb bound */
@@ -1539,73 +1579,18 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1539 return ret; 1579 return ret;
1540 } 1580 }
1541 1581
1542 dspcntr = I915_READ(dspcntr_reg); 1582 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y);
1543 /* Mask out pixel format bits in case we change it */ 1583 if (ret) {
1544 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1545 switch (crtc->fb->bits_per_pixel) {
1546 case 8:
1547 dspcntr |= DISPPLANE_8BPP;
1548 break;
1549 case 16:
1550 if (crtc->fb->depth == 15)
1551 dspcntr |= DISPPLANE_15_16BPP;
1552 else
1553 dspcntr |= DISPPLANE_16BPP;
1554 break;
1555 case 24:
1556 case 32:
1557 if (crtc->fb->depth == 30)
1558 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1559 else
1560 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1561 break;
1562 default:
1563 DRM_ERROR("Unknown color depth\n");
1564 i915_gem_object_unpin(obj); 1584 i915_gem_object_unpin(obj);
1565 mutex_unlock(&dev->struct_mutex); 1585 mutex_unlock(&dev->struct_mutex);
1566 return -EINVAL; 1586 return ret;
1567 }
1568 if (IS_I965G(dev)) {
1569 if (obj_priv->tiling_mode != I915_TILING_NONE)
1570 dspcntr |= DISPPLANE_TILED;
1571 else
1572 dspcntr &= ~DISPPLANE_TILED;
1573 }
1574
1575 if (HAS_PCH_SPLIT(dev))
1576 /* must disable */
1577 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1578
1579 I915_WRITE(dspcntr_reg, dspcntr);
1580
1581 Start = obj_priv->gtt_offset;
1582 Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1583
1584 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1585 Start, Offset, x, y, crtc->fb->pitch);
1586 I915_WRITE(dspstride, crtc->fb->pitch);
1587 if (IS_I965G(dev)) {
1588 I915_WRITE(dspbase, Offset);
1589 I915_READ(dspbase);
1590 I915_WRITE(dspsurf, Start);
1591 I915_READ(dspsurf);
1592 I915_WRITE(dsptileoff, (y << 16) | x);
1593 } else {
1594 I915_WRITE(dspbase, Start + Offset);
1595 I915_READ(dspbase);
1596 } 1587 }
1597 1588
1598 if ((IS_I965G(dev) || plane == 0))
1599 intel_update_fbc(crtc, &crtc->mode);
1600
1601 intel_wait_for_vblank(dev);
1602
1603 if (old_fb) { 1589 if (old_fb) {
1604 intel_fb = to_intel_framebuffer(old_fb); 1590 intel_fb = to_intel_framebuffer(old_fb);
1605 obj_priv = to_intel_bo(intel_fb->obj); 1591 obj_priv = to_intel_bo(intel_fb->obj);
1606 i915_gem_object_unpin(intel_fb->obj); 1592 i915_gem_object_unpin(intel_fb->obj);
1607 } 1593 }
1608 intel_increase_pllclock(crtc, true);
1609 1594
1610 mutex_unlock(&dev->struct_mutex); 1595 mutex_unlock(&dev->struct_mutex);
1611 1596
@@ -1627,54 +1612,6 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1627 return 0; 1612 return 0;
1628} 1613}
1629 1614
1630/* Disable the VGA plane that we never use */
1631static void i915_disable_vga (struct drm_device *dev)
1632{
1633 struct drm_i915_private *dev_priv = dev->dev_private;
1634 u8 sr1;
1635 u32 vga_reg;
1636
1637 if (HAS_PCH_SPLIT(dev))
1638 vga_reg = CPU_VGACNTRL;
1639 else
1640 vga_reg = VGACNTRL;
1641
1642 if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1643 return;
1644
1645 I915_WRITE8(VGA_SR_INDEX, 1);
1646 sr1 = I915_READ8(VGA_SR_DATA);
1647 I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1648 udelay(100);
1649
1650 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1651}
1652
1653static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1654{
1655 struct drm_device *dev = crtc->dev;
1656 struct drm_i915_private *dev_priv = dev->dev_private;
1657 u32 dpa_ctl;
1658
1659 DRM_DEBUG_KMS("\n");
1660 dpa_ctl = I915_READ(DP_A);
1661 dpa_ctl &= ~DP_PLL_ENABLE;
1662 I915_WRITE(DP_A, dpa_ctl);
1663}
1664
1665static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1666{
1667 struct drm_device *dev = crtc->dev;
1668 struct drm_i915_private *dev_priv = dev->dev_private;
1669 u32 dpa_ctl;
1670
1671 dpa_ctl = I915_READ(DP_A);
1672 dpa_ctl |= DP_PLL_ENABLE;
1673 I915_WRITE(DP_A, dpa_ctl);
1674 udelay(200);
1675}
1676
1677
1678static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock) 1615static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1679{ 1616{
1680 struct drm_device *dev = crtc->dev; 1617 struct drm_device *dev = crtc->dev;
@@ -1928,9 +1865,6 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1928 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL; 1865 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1929 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL; 1866 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1930 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF; 1867 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1931 int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1932 int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1933 int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1934 int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B; 1868 int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1935 int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B; 1869 int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1936 int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B; 1870 int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
@@ -1945,7 +1879,6 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1945 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B; 1879 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1946 int trans_dpll_sel = (pipe == 0) ? 0 : 1; 1880 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1947 u32 temp; 1881 u32 temp;
1948 int n;
1949 u32 pipe_bpc; 1882 u32 pipe_bpc;
1950 1883
1951 temp = I915_READ(pipeconf_reg); 1884 temp = I915_READ(pipeconf_reg);
@@ -1958,7 +1891,7 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1958 case DRM_MODE_DPMS_ON: 1891 case DRM_MODE_DPMS_ON:
1959 case DRM_MODE_DPMS_STANDBY: 1892 case DRM_MODE_DPMS_STANDBY:
1960 case DRM_MODE_DPMS_SUSPEND: 1893 case DRM_MODE_DPMS_SUSPEND:
1961 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe); 1894 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
1962 1895
1963 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 1896 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1964 temp = I915_READ(PCH_LVDS); 1897 temp = I915_READ(PCH_LVDS);
@@ -1968,10 +1901,7 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1968 } 1901 }
1969 } 1902 }
1970 1903
1971 if (HAS_eDP) { 1904 if (!HAS_eDP) {
1972 /* enable eDP PLL */
1973 ironlake_enable_pll_edp(crtc);
1974 } else {
1975 1905
1976 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ 1906 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1977 temp = I915_READ(fdi_rx_reg); 1907 temp = I915_READ(fdi_rx_reg);
@@ -2003,17 +1933,19 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2003 } 1933 }
2004 1934
2005 /* Enable panel fitting for LVDS */ 1935 /* Enable panel fitting for LVDS */
2006 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) 1936 if (dev_priv->pch_pf_size &&
2007 || HAS_eDP || intel_pch_has_edp(crtc)) { 1937 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
2008 temp = I915_READ(pf_ctl_reg); 1938 || HAS_eDP || intel_pch_has_edp(crtc))) {
2009 I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3); 1939 /* Force use of hard-coded filter coefficients
2010 1940 * as some pre-programmed values are broken,
2011 /* currently full aspect */ 1941 * e.g. x201.
2012 I915_WRITE(pf_win_pos, 0); 1942 */
2013 1943 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
2014 I915_WRITE(pf_win_size, 1944 PF_ENABLE | PF_FILTER_MED_3x3);
2015 (dev_priv->panel_fixed_mode->hdisplay << 16) | 1945 I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
2016 (dev_priv->panel_fixed_mode->vdisplay)); 1946 dev_priv->pch_pf_pos);
1947 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
1948 dev_priv->pch_pf_size);
2017 } 1949 }
2018 1950
2019 /* Enable CPU pipe */ 1951 /* Enable CPU pipe */
@@ -2097,9 +2029,10 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2097 int reg; 2029 int reg;
2098 2030
2099 reg = I915_READ(trans_dp_ctl); 2031 reg = I915_READ(trans_dp_ctl);
2100 reg &= ~TRANS_DP_PORT_SEL_MASK; 2032 reg &= ~(TRANS_DP_PORT_SEL_MASK |
2101 reg = TRANS_DP_OUTPUT_ENABLE | 2033 TRANS_DP_SYNC_MASK);
2102 TRANS_DP_ENH_FRAMING; 2034 reg |= (TRANS_DP_OUTPUT_ENABLE |
2035 TRANS_DP_ENH_FRAMING);
2103 2036
2104 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) 2037 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2105 reg |= TRANS_DP_HSYNC_ACTIVE_HIGH; 2038 reg |= TRANS_DP_HSYNC_ACTIVE_HIGH;
@@ -2137,18 +2070,17 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2137 I915_WRITE(transconf_reg, temp | TRANS_ENABLE); 2070 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
2138 I915_READ(transconf_reg); 2071 I915_READ(transconf_reg);
2139 2072
2140 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0) 2073 if (wait_for(I915_READ(transconf_reg) & TRANS_STATE_ENABLE, 100, 1))
2141 ; 2074 DRM_ERROR("failed to enable transcoder\n");
2142
2143 } 2075 }
2144 2076
2145 intel_crtc_load_lut(crtc); 2077 intel_crtc_load_lut(crtc);
2146 2078
2147 intel_update_fbc(crtc, &crtc->mode); 2079 intel_update_fbc(crtc, &crtc->mode);
2080 break;
2148 2081
2149 break;
2150 case DRM_MODE_DPMS_OFF: 2082 case DRM_MODE_DPMS_OFF:
2151 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe); 2083 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2152 2084
2153 drm_vblank_off(dev, pipe); 2085 drm_vblank_off(dev, pipe);
2154 /* Disable display plane */ 2086 /* Disable display plane */
@@ -2164,40 +2096,22 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2164 dev_priv->display.disable_fbc) 2096 dev_priv->display.disable_fbc)
2165 dev_priv->display.disable_fbc(dev); 2097 dev_priv->display.disable_fbc(dev);
2166 2098
2167 i915_disable_vga(dev);
2168
2169 /* disable cpu pipe, disable after all planes disabled */ 2099 /* disable cpu pipe, disable after all planes disabled */
2170 temp = I915_READ(pipeconf_reg); 2100 temp = I915_READ(pipeconf_reg);
2171 if ((temp & PIPEACONF_ENABLE) != 0) { 2101 if ((temp & PIPEACONF_ENABLE) != 0) {
2172 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE); 2102 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2173 I915_READ(pipeconf_reg); 2103
2174 n = 0;
2175 /* wait for cpu pipe off, pipe state */ 2104 /* wait for cpu pipe off, pipe state */
2176 while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) { 2105 if (wait_for((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) == 0, 50, 1))
2177 n++; 2106 DRM_ERROR("failed to turn off cpu pipe\n");
2178 if (n < 60) {
2179 udelay(500);
2180 continue;
2181 } else {
2182 DRM_DEBUG_KMS("pipe %d off delay\n",
2183 pipe);
2184 break;
2185 }
2186 }
2187 } else 2107 } else
2188 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); 2108 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
2189 2109
2190 udelay(100); 2110 udelay(100);
2191 2111
2192 /* Disable PF */ 2112 /* Disable PF */
2193 temp = I915_READ(pf_ctl_reg); 2113 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
2194 if ((temp & PF_ENABLE) != 0) { 2114 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
2195 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
2196 I915_READ(pf_ctl_reg);
2197 }
2198 I915_WRITE(pf_win_size, 0);
2199 POSTING_READ(pf_win_size);
2200
2201 2115
2202 /* disable CPU FDI tx and PCH FDI rx */ 2116 /* disable CPU FDI tx and PCH FDI rx */
2203 temp = I915_READ(fdi_tx_reg); 2117 temp = I915_READ(fdi_tx_reg);
@@ -2244,20 +2158,10 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2244 temp = I915_READ(transconf_reg); 2158 temp = I915_READ(transconf_reg);
2245 if ((temp & TRANS_ENABLE) != 0) { 2159 if ((temp & TRANS_ENABLE) != 0) {
2246 I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE); 2160 I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
2247 I915_READ(transconf_reg); 2161
2248 n = 0;
2249 /* wait for PCH transcoder off, transcoder state */ 2162 /* wait for PCH transcoder off, transcoder state */
2250 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) { 2163 if (wait_for((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0, 50, 1))
2251 n++; 2164 DRM_ERROR("failed to disable transcoder\n");
2252 if (n < 60) {
2253 udelay(500);
2254 continue;
2255 } else {
2256 DRM_DEBUG_KMS("transcoder %d off "
2257 "delay\n", pipe);
2258 break;
2259 }
2260 }
2261 } 2165 }
2262 2166
2263 temp = I915_READ(transconf_reg); 2167 temp = I915_READ(transconf_reg);
@@ -2294,10 +2198,6 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2294 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE); 2198 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2295 I915_READ(pch_dpll_reg); 2199 I915_READ(pch_dpll_reg);
2296 2200
2297 if (HAS_eDP) {
2298 ironlake_disable_pll_edp(crtc);
2299 }
2300
2301 /* Switch from PCDclk to Rawclk */ 2201 /* Switch from PCDclk to Rawclk */
2302 temp = I915_READ(fdi_rx_reg); 2202 temp = I915_READ(fdi_rx_reg);
2303 temp &= ~FDI_SEL_PCDCLK; 2203 temp &= ~FDI_SEL_PCDCLK;
@@ -2372,8 +2272,6 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2372 case DRM_MODE_DPMS_ON: 2272 case DRM_MODE_DPMS_ON:
2373 case DRM_MODE_DPMS_STANDBY: 2273 case DRM_MODE_DPMS_STANDBY:
2374 case DRM_MODE_DPMS_SUSPEND: 2274 case DRM_MODE_DPMS_SUSPEND:
2375 intel_update_watermarks(dev);
2376
2377 /* Enable the DPLL */ 2275 /* Enable the DPLL */
2378 temp = I915_READ(dpll_reg); 2276 temp = I915_READ(dpll_reg);
2379 if ((temp & DPLL_VCO_ENABLE) == 0) { 2277 if ((temp & DPLL_VCO_ENABLE) == 0) {
@@ -2413,8 +2311,6 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2413 intel_crtc_dpms_overlay(intel_crtc, true); 2311 intel_crtc_dpms_overlay(intel_crtc, true);
2414 break; 2312 break;
2415 case DRM_MODE_DPMS_OFF: 2313 case DRM_MODE_DPMS_OFF:
2416 intel_update_watermarks(dev);
2417
2418 /* Give the overlay scaler a chance to disable if it's on this pipe */ 2314 /* Give the overlay scaler a chance to disable if it's on this pipe */
2419 intel_crtc_dpms_overlay(intel_crtc, false); 2315 intel_crtc_dpms_overlay(intel_crtc, false);
2420 drm_vblank_off(dev, pipe); 2316 drm_vblank_off(dev, pipe);
@@ -2423,9 +2319,6 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2423 dev_priv->display.disable_fbc) 2319 dev_priv->display.disable_fbc)
2424 dev_priv->display.disable_fbc(dev); 2320 dev_priv->display.disable_fbc(dev);
2425 2321
2426 /* Disable the VGA plane that we never use */
2427 i915_disable_vga(dev);
2428
2429 /* Disable display plane */ 2322 /* Disable display plane */
2430 temp = I915_READ(dspcntr_reg); 2323 temp = I915_READ(dspcntr_reg);
2431 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { 2324 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
@@ -2435,10 +2328,8 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2435 I915_READ(dspbase_reg); 2328 I915_READ(dspbase_reg);
2436 } 2329 }
2437 2330
2438 if (!IS_I9XX(dev)) { 2331 /* Wait for vblank for the disable to take effect */
2439 /* Wait for vblank for the disable to take effect */ 2332 intel_wait_for_vblank_off(dev, pipe);
2440 intel_wait_for_vblank(dev);
2441 }
2442 2333
2443 /* Don't disable pipe A or pipe A PLLs if needed */ 2334 /* Don't disable pipe A or pipe A PLLs if needed */
2444 if (pipeconf_reg == PIPEACONF && 2335 if (pipeconf_reg == PIPEACONF &&
@@ -2453,7 +2344,7 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2453 } 2344 }
2454 2345
2455 /* Wait for vblank for the disable to take effect. */ 2346 /* Wait for vblank for the disable to take effect. */
2456 intel_wait_for_vblank(dev); 2347 intel_wait_for_vblank_off(dev, pipe);
2457 2348
2458 temp = I915_READ(dpll_reg); 2349 temp = I915_READ(dpll_reg);
2459 if ((temp & DPLL_VCO_ENABLE) != 0) { 2350 if ((temp & DPLL_VCO_ENABLE) != 0) {
@@ -2469,9 +2360,6 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2469 2360
2470/** 2361/**
2471 * Sets the power management mode of the pipe and plane. 2362 * Sets the power management mode of the pipe and plane.
2472 *
2473 * This code should probably grow support for turning the cursor off and back
2474 * on appropriately at the same time as we're turning the pipe off/on.
2475 */ 2363 */
2476static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) 2364static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2477{ 2365{
@@ -2482,9 +2370,29 @@ static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2482 int pipe = intel_crtc->pipe; 2370 int pipe = intel_crtc->pipe;
2483 bool enabled; 2371 bool enabled;
2484 2372
2485 dev_priv->display.dpms(crtc, mode); 2373 if (intel_crtc->dpms_mode == mode)
2374 return;
2486 2375
2487 intel_crtc->dpms_mode = mode; 2376 intel_crtc->dpms_mode = mode;
2377 intel_crtc->cursor_on = mode == DRM_MODE_DPMS_ON;
2378
2379 /* When switching on the display, ensure that SR is disabled
2380 * with multiple pipes prior to enabling to new pipe.
2381 *
2382 * When switching off the display, make sure the cursor is
2383 * properly hidden prior to disabling the pipe.
2384 */
2385 if (mode == DRM_MODE_DPMS_ON)
2386 intel_update_watermarks(dev);
2387 else
2388 intel_crtc_update_cursor(crtc);
2389
2390 dev_priv->display.dpms(crtc, mode);
2391
2392 if (mode == DRM_MODE_DPMS_ON)
2393 intel_crtc_update_cursor(crtc);
2394 else
2395 intel_update_watermarks(dev);
2488 2396
2489 if (!dev->primary->master) 2397 if (!dev->primary->master)
2490 return; 2398 return;
@@ -2536,6 +2444,20 @@ void intel_encoder_commit (struct drm_encoder *encoder)
2536 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); 2444 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2537} 2445}
2538 2446
2447void intel_encoder_destroy(struct drm_encoder *encoder)
2448{
2449 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
2450
2451 if (intel_encoder->ddc_bus)
2452 intel_i2c_destroy(intel_encoder->ddc_bus);
2453
2454 if (intel_encoder->i2c_bus)
2455 intel_i2c_destroy(intel_encoder->i2c_bus);
2456
2457 drm_encoder_cleanup(encoder);
2458 kfree(intel_encoder);
2459}
2460
2539static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, 2461static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2540 struct drm_display_mode *mode, 2462 struct drm_display_mode *mode,
2541 struct drm_display_mode *adjusted_mode) 2463 struct drm_display_mode *adjusted_mode)
@@ -2867,7 +2789,7 @@ struct cxsr_latency {
2867 unsigned long cursor_hpll_disable; 2789 unsigned long cursor_hpll_disable;
2868}; 2790};
2869 2791
2870static struct cxsr_latency cxsr_latency_table[] = { 2792static const struct cxsr_latency cxsr_latency_table[] = {
2871 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ 2793 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2872 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ 2794 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2873 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ 2795 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
@@ -2905,11 +2827,13 @@ static struct cxsr_latency cxsr_latency_table[] = {
2905 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ 2827 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
2906}; 2828};
2907 2829
2908static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int is_ddr3, 2830static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2909 int fsb, int mem) 2831 int is_ddr3,
2832 int fsb,
2833 int mem)
2910{ 2834{
2835 const struct cxsr_latency *latency;
2911 int i; 2836 int i;
2912 struct cxsr_latency *latency;
2913 2837
2914 if (fsb == 0 || mem == 0) 2838 if (fsb == 0 || mem == 0)
2915 return NULL; 2839 return NULL;
@@ -2930,13 +2854,9 @@ static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int is_ddr3,
2930static void pineview_disable_cxsr(struct drm_device *dev) 2854static void pineview_disable_cxsr(struct drm_device *dev)
2931{ 2855{
2932 struct drm_i915_private *dev_priv = dev->dev_private; 2856 struct drm_i915_private *dev_priv = dev->dev_private;
2933 u32 reg;
2934 2857
2935 /* deactivate cxsr */ 2858 /* deactivate cxsr */
2936 reg = I915_READ(DSPFW3); 2859 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
2937 reg &= ~(PINEVIEW_SELF_REFRESH_EN);
2938 I915_WRITE(DSPFW3, reg);
2939 DRM_INFO("Big FIFO is disabled\n");
2940} 2860}
2941 2861
2942/* 2862/*
@@ -3024,12 +2944,12 @@ static void pineview_update_wm(struct drm_device *dev, int planea_clock,
3024 int pixel_size) 2944 int pixel_size)
3025{ 2945{
3026 struct drm_i915_private *dev_priv = dev->dev_private; 2946 struct drm_i915_private *dev_priv = dev->dev_private;
2947 const struct cxsr_latency *latency;
3027 u32 reg; 2948 u32 reg;
3028 unsigned long wm; 2949 unsigned long wm;
3029 struct cxsr_latency *latency;
3030 int sr_clock; 2950 int sr_clock;
3031 2951
3032 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, 2952 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3033 dev_priv->fsb_freq, dev_priv->mem_freq); 2953 dev_priv->fsb_freq, dev_priv->mem_freq);
3034 if (!latency) { 2954 if (!latency) {
3035 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); 2955 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
@@ -3075,9 +2995,8 @@ static void pineview_update_wm(struct drm_device *dev, int planea_clock,
3075 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); 2995 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3076 2996
3077 /* activate cxsr */ 2997 /* activate cxsr */
3078 reg = I915_READ(DSPFW3); 2998 I915_WRITE(DSPFW3,
3079 reg |= PINEVIEW_SELF_REFRESH_EN; 2999 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3080 I915_WRITE(DSPFW3, reg);
3081 DRM_DEBUG_KMS("Self-refresh is enabled\n"); 3000 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3082 } else { 3001 } else {
3083 pineview_disable_cxsr(dev); 3002 pineview_disable_cxsr(dev);
@@ -3354,12 +3273,11 @@ static void ironlake_update_wm(struct drm_device *dev, int planea_clock,
3354 int line_count; 3273 int line_count;
3355 int planea_htotal = 0, planeb_htotal = 0; 3274 int planea_htotal = 0, planeb_htotal = 0;
3356 struct drm_crtc *crtc; 3275 struct drm_crtc *crtc;
3357 struct intel_crtc *intel_crtc;
3358 3276
3359 /* Need htotal for all active display plane */ 3277 /* Need htotal for all active display plane */
3360 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 3278 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3361 intel_crtc = to_intel_crtc(crtc); 3279 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3362 if (crtc->enabled) { 3280 if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) {
3363 if (intel_crtc->plane == 0) 3281 if (intel_crtc->plane == 0)
3364 planea_htotal = crtc->mode.htotal; 3282 planea_htotal = crtc->mode.htotal;
3365 else 3283 else
@@ -3519,7 +3437,6 @@ static void intel_update_watermarks(struct drm_device *dev)
3519{ 3437{
3520 struct drm_i915_private *dev_priv = dev->dev_private; 3438 struct drm_i915_private *dev_priv = dev->dev_private;
3521 struct drm_crtc *crtc; 3439 struct drm_crtc *crtc;
3522 struct intel_crtc *intel_crtc;
3523 int sr_hdisplay = 0; 3440 int sr_hdisplay = 0;
3524 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0; 3441 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3525 int enabled = 0, pixel_size = 0; 3442 int enabled = 0, pixel_size = 0;
@@ -3530,8 +3447,8 @@ static void intel_update_watermarks(struct drm_device *dev)
3530 3447
3531 /* Get the clock config from both planes */ 3448 /* Get the clock config from both planes */
3532 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 3449 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3533 intel_crtc = to_intel_crtc(crtc); 3450 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3534 if (crtc->enabled) { 3451 if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) {
3535 enabled++; 3452 enabled++;
3536 if (intel_crtc->plane == 0) { 3453 if (intel_crtc->plane == 0) {
3537 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n", 3454 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
@@ -3589,10 +3506,9 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3589 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf; 3506 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
3590 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false; 3507 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3591 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; 3508 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3592 bool is_edp = false; 3509 struct intel_encoder *has_edp_encoder = NULL;
3593 struct drm_mode_config *mode_config = &dev->mode_config; 3510 struct drm_mode_config *mode_config = &dev->mode_config;
3594 struct drm_encoder *encoder; 3511 struct drm_encoder *encoder;
3595 struct intel_encoder *intel_encoder = NULL;
3596 const intel_limit_t *limit; 3512 const intel_limit_t *limit;
3597 int ret; 3513 int ret;
3598 struct fdi_m_n m_n = {0}; 3514 struct fdi_m_n m_n = {0};
@@ -3613,12 +3529,12 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3613 drm_vblank_pre_modeset(dev, pipe); 3529 drm_vblank_pre_modeset(dev, pipe);
3614 3530
3615 list_for_each_entry(encoder, &mode_config->encoder_list, head) { 3531 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
3532 struct intel_encoder *intel_encoder;
3616 3533
3617 if (!encoder || encoder->crtc != crtc) 3534 if (encoder->crtc != crtc)
3618 continue; 3535 continue;
3619 3536
3620 intel_encoder = enc_to_intel_encoder(encoder); 3537 intel_encoder = enc_to_intel_encoder(encoder);
3621
3622 switch (intel_encoder->type) { 3538 switch (intel_encoder->type) {
3623 case INTEL_OUTPUT_LVDS: 3539 case INTEL_OUTPUT_LVDS:
3624 is_lvds = true; 3540 is_lvds = true;
@@ -3642,7 +3558,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3642 is_dp = true; 3558 is_dp = true;
3643 break; 3559 break;
3644 case INTEL_OUTPUT_EDP: 3560 case INTEL_OUTPUT_EDP:
3645 is_edp = true; 3561 has_edp_encoder = intel_encoder;
3646 break; 3562 break;
3647 } 3563 }
3648 3564
@@ -3720,10 +3636,10 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3720 int lane = 0, link_bw, bpp; 3636 int lane = 0, link_bw, bpp;
3721 /* eDP doesn't require FDI link, so just set DP M/N 3637 /* eDP doesn't require FDI link, so just set DP M/N
3722 according to current link config */ 3638 according to current link config */
3723 if (is_edp) { 3639 if (has_edp_encoder) {
3724 target_clock = mode->clock; 3640 target_clock = mode->clock;
3725 intel_edp_link_config(intel_encoder, 3641 intel_edp_link_config(has_edp_encoder,
3726 &lane, &link_bw); 3642 &lane, &link_bw);
3727 } else { 3643 } else {
3728 /* DP over FDI requires target mode clock 3644 /* DP over FDI requires target mode clock
3729 instead of link clock */ 3645 instead of link clock */
@@ -3744,7 +3660,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3744 temp |= PIPE_8BPC; 3660 temp |= PIPE_8BPC;
3745 else 3661 else
3746 temp |= PIPE_6BPC; 3662 temp |= PIPE_6BPC;
3747 } else if (is_edp || (is_dp && intel_pch_has_edp(crtc))) { 3663 } else if (has_edp_encoder || (is_dp && intel_pch_has_edp(crtc))) {
3748 switch (dev_priv->edp_bpp/3) { 3664 switch (dev_priv->edp_bpp/3) {
3749 case 8: 3665 case 8:
3750 temp |= PIPE_8BPC; 3666 temp |= PIPE_8BPC;
@@ -3817,7 +3733,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3817 3733
3818 udelay(200); 3734 udelay(200);
3819 3735
3820 if (is_edp) { 3736 if (has_edp_encoder) {
3821 if (dev_priv->lvds_use_ssc) { 3737 if (dev_priv->lvds_use_ssc) {
3822 temp |= DREF_SSC1_ENABLE; 3738 temp |= DREF_SSC1_ENABLE;
3823 I915_WRITE(PCH_DREF_CONTROL, temp); 3739 I915_WRITE(PCH_DREF_CONTROL, temp);
@@ -3966,9 +3882,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3966 dpll_reg = pch_dpll_reg; 3882 dpll_reg = pch_dpll_reg;
3967 } 3883 }
3968 3884
3969 if (is_edp) { 3885 if (!has_edp_encoder) {
3970 ironlake_disable_pll_edp(crtc);
3971 } else if ((dpll & DPLL_VCO_ENABLE)) {
3972 I915_WRITE(fp_reg, fp); 3886 I915_WRITE(fp_reg, fp);
3973 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE); 3887 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3974 I915_READ(dpll_reg); 3888 I915_READ(dpll_reg);
@@ -4063,7 +3977,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
4063 } 3977 }
4064 } 3978 }
4065 3979
4066 if (!is_edp) { 3980 if (!has_edp_encoder) {
4067 I915_WRITE(fp_reg, fp); 3981 I915_WRITE(fp_reg, fp);
4068 I915_WRITE(dpll_reg, dpll); 3982 I915_WRITE(dpll_reg, dpll);
4069 I915_READ(dpll_reg); 3983 I915_READ(dpll_reg);
@@ -4142,7 +4056,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
4142 I915_WRITE(link_m1_reg, m_n.link_m); 4056 I915_WRITE(link_m1_reg, m_n.link_m);
4143 I915_WRITE(link_n1_reg, m_n.link_n); 4057 I915_WRITE(link_n1_reg, m_n.link_n);
4144 4058
4145 if (is_edp) { 4059 if (has_edp_encoder) {
4146 ironlake_set_pll_edp(crtc, adjusted_mode->clock); 4060 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4147 } else { 4061 } else {
4148 /* enable FDI RX PLL too */ 4062 /* enable FDI RX PLL too */
@@ -4167,7 +4081,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
4167 I915_WRITE(pipeconf_reg, pipeconf); 4081 I915_WRITE(pipeconf_reg, pipeconf);
4168 I915_READ(pipeconf_reg); 4082 I915_READ(pipeconf_reg);
4169 4083
4170 intel_wait_for_vblank(dev); 4084 intel_wait_for_vblank(dev, pipe);
4171 4085
4172 if (IS_IRONLAKE(dev)) { 4086 if (IS_IRONLAKE(dev)) {
4173 /* enable address swizzle for tiling buffer */ 4087 /* enable address swizzle for tiling buffer */
@@ -4180,9 +4094,6 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
4180 /* Flush the plane changes */ 4094 /* Flush the plane changes */
4181 ret = intel_pipe_set_base(crtc, x, y, old_fb); 4095 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4182 4096
4183 if ((IS_I965G(dev) || plane == 0))
4184 intel_update_fbc(crtc, &crtc->mode);
4185
4186 intel_update_watermarks(dev); 4097 intel_update_watermarks(dev);
4187 4098
4188 drm_vblank_post_modeset(dev, pipe); 4099 drm_vblank_post_modeset(dev, pipe);
@@ -4216,6 +4127,62 @@ void intel_crtc_load_lut(struct drm_crtc *crtc)
4216 } 4127 }
4217} 4128}
4218 4129
4130static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4131{
4132 struct drm_device *dev = crtc->dev;
4133 struct drm_i915_private *dev_priv = dev->dev_private;
4134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4135 bool visible = base != 0;
4136 u32 cntl;
4137
4138 if (intel_crtc->cursor_visible == visible)
4139 return;
4140
4141 cntl = I915_READ(CURACNTR);
4142 if (visible) {
4143 /* On these chipsets we can only modify the base whilst
4144 * the cursor is disabled.
4145 */
4146 I915_WRITE(CURABASE, base);
4147
4148 cntl &= ~(CURSOR_FORMAT_MASK);
4149 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4150 cntl |= CURSOR_ENABLE |
4151 CURSOR_GAMMA_ENABLE |
4152 CURSOR_FORMAT_ARGB;
4153 } else
4154 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4155 I915_WRITE(CURACNTR, cntl);
4156
4157 intel_crtc->cursor_visible = visible;
4158}
4159
4160static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4161{
4162 struct drm_device *dev = crtc->dev;
4163 struct drm_i915_private *dev_priv = dev->dev_private;
4164 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4165 int pipe = intel_crtc->pipe;
4166 bool visible = base != 0;
4167
4168 if (intel_crtc->cursor_visible != visible) {
4169 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4170 if (base) {
4171 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4172 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4173 cntl |= pipe << 28; /* Connect to correct pipe */
4174 } else {
4175 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4176 cntl |= CURSOR_MODE_DISABLE;
4177 }
4178 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4179
4180 intel_crtc->cursor_visible = visible;
4181 }
4182 /* and commit changes on next vblank */
4183 I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4184}
4185
4219/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ 4186/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4220static void intel_crtc_update_cursor(struct drm_crtc *crtc) 4187static void intel_crtc_update_cursor(struct drm_crtc *crtc)
4221{ 4188{
@@ -4225,12 +4192,12 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc)
4225 int pipe = intel_crtc->pipe; 4192 int pipe = intel_crtc->pipe;
4226 int x = intel_crtc->cursor_x; 4193 int x = intel_crtc->cursor_x;
4227 int y = intel_crtc->cursor_y; 4194 int y = intel_crtc->cursor_y;
4228 uint32_t base, pos; 4195 u32 base, pos;
4229 bool visible; 4196 bool visible;
4230 4197
4231 pos = 0; 4198 pos = 0;
4232 4199
4233 if (crtc->fb) { 4200 if (intel_crtc->cursor_on && crtc->fb) {
4234 base = intel_crtc->cursor_addr; 4201 base = intel_crtc->cursor_addr;
4235 if (x > (int) crtc->fb->width) 4202 if (x > (int) crtc->fb->width)
4236 base = 0; 4203 base = 0;
@@ -4259,37 +4226,14 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc)
4259 pos |= y << CURSOR_Y_SHIFT; 4226 pos |= y << CURSOR_Y_SHIFT;
4260 4227
4261 visible = base != 0; 4228 visible = base != 0;
4262 if (!visible && !intel_crtc->cursor_visble) 4229 if (!visible && !intel_crtc->cursor_visible)
4263 return; 4230 return;
4264 4231
4265 I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos); 4232 I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4266 if (intel_crtc->cursor_visble != visible) { 4233 if (IS_845G(dev) || IS_I865G(dev))
4267 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR); 4234 i845_update_cursor(crtc, base);
4268 if (base) { 4235 else
4269 /* Hooray for CUR*CNTR differences */ 4236 i9xx_update_cursor(crtc, base);
4270 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
4271 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4272 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4273 cntl |= pipe << 28; /* Connect to correct pipe */
4274 } else {
4275 cntl &= ~(CURSOR_FORMAT_MASK);
4276 cntl |= CURSOR_ENABLE;
4277 cntl |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
4278 }
4279 } else {
4280 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
4281 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4282 cntl |= CURSOR_MODE_DISABLE;
4283 } else {
4284 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4285 }
4286 }
4287 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4288
4289 intel_crtc->cursor_visble = visible;
4290 }
4291 /* and commit changes on next vblank */
4292 I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4293 4237
4294 if (visible) 4238 if (visible)
4295 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj); 4239 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
@@ -4354,8 +4298,10 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4354 4298
4355 addr = obj_priv->gtt_offset; 4299 addr = obj_priv->gtt_offset;
4356 } else { 4300 } else {
4301 int align = IS_I830(dev) ? 16 * 1024 : 256;
4357 ret = i915_gem_attach_phys_object(dev, bo, 4302 ret = i915_gem_attach_phys_object(dev, bo,
4358 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1); 4303 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4304 align);
4359 if (ret) { 4305 if (ret) {
4360 DRM_ERROR("failed to attach phys object\n"); 4306 DRM_ERROR("failed to attach phys object\n");
4361 goto fail_locked; 4307 goto fail_locked;
@@ -4544,7 +4490,7 @@ struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4544 encoder_funcs->commit(encoder); 4490 encoder_funcs->commit(encoder);
4545 } 4491 }
4546 /* let the connector get through one full cycle before testing */ 4492 /* let the connector get through one full cycle before testing */
4547 intel_wait_for_vblank(dev); 4493 intel_wait_for_vblank(dev, intel_crtc->pipe);
4548 4494
4549 return crtc; 4495 return crtc;
4550} 4496}
@@ -4749,7 +4695,7 @@ static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
4749 dpll &= ~DISPLAY_RATE_SELECT_FPA1; 4695 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4750 I915_WRITE(dpll_reg, dpll); 4696 I915_WRITE(dpll_reg, dpll);
4751 dpll = I915_READ(dpll_reg); 4697 dpll = I915_READ(dpll_reg);
4752 intel_wait_for_vblank(dev); 4698 intel_wait_for_vblank(dev, pipe);
4753 dpll = I915_READ(dpll_reg); 4699 dpll = I915_READ(dpll_reg);
4754 if (dpll & DISPLAY_RATE_SELECT_FPA1) 4700 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4755 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); 4701 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
@@ -4793,7 +4739,7 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc)
4793 dpll |= DISPLAY_RATE_SELECT_FPA1; 4739 dpll |= DISPLAY_RATE_SELECT_FPA1;
4794 I915_WRITE(dpll_reg, dpll); 4740 I915_WRITE(dpll_reg, dpll);
4795 dpll = I915_READ(dpll_reg); 4741 dpll = I915_READ(dpll_reg);
4796 intel_wait_for_vblank(dev); 4742 intel_wait_for_vblank(dev, pipe);
4797 dpll = I915_READ(dpll_reg); 4743 dpll = I915_READ(dpll_reg);
4798 if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) 4744 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4799 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); 4745 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
@@ -4916,15 +4862,6 @@ static void intel_crtc_destroy(struct drm_crtc *crtc)
4916 kfree(intel_crtc); 4862 kfree(intel_crtc);
4917} 4863}
4918 4864
4919struct intel_unpin_work {
4920 struct work_struct work;
4921 struct drm_device *dev;
4922 struct drm_gem_object *old_fb_obj;
4923 struct drm_gem_object *pending_flip_obj;
4924 struct drm_pending_vblank_event *event;
4925 int pending;
4926};
4927
4928static void intel_unpin_work_fn(struct work_struct *__work) 4865static void intel_unpin_work_fn(struct work_struct *__work)
4929{ 4866{
4930 struct intel_unpin_work *work = 4867 struct intel_unpin_work *work =
@@ -5012,7 +4949,8 @@ void intel_prepare_page_flip(struct drm_device *dev, int plane)
5012 4949
5013 spin_lock_irqsave(&dev->event_lock, flags); 4950 spin_lock_irqsave(&dev->event_lock, flags);
5014 if (intel_crtc->unpin_work) { 4951 if (intel_crtc->unpin_work) {
5015 intel_crtc->unpin_work->pending = 1; 4952 if ((++intel_crtc->unpin_work->pending) > 1)
4953 DRM_ERROR("Prepared flip multiple times\n");
5016 } else { 4954 } else {
5017 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n"); 4955 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5018 } 4956 }
@@ -5031,9 +4969,9 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
5031 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4969 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5032 struct intel_unpin_work *work; 4970 struct intel_unpin_work *work;
5033 unsigned long flags, offset; 4971 unsigned long flags, offset;
5034 int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC; 4972 int pipe = intel_crtc->pipe;
5035 int ret, pipesrc; 4973 u32 pf, pipesrc;
5036 u32 flip_mask; 4974 int ret;
5037 4975
5038 work = kzalloc(sizeof *work, GFP_KERNEL); 4976 work = kzalloc(sizeof *work, GFP_KERNEL);
5039 if (work == NULL) 4977 if (work == NULL)
@@ -5082,34 +5020,73 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
5082 atomic_inc(&obj_priv->pending_flip); 5020 atomic_inc(&obj_priv->pending_flip);
5083 work->pending_flip_obj = obj; 5021 work->pending_flip_obj = obj;
5084 5022
5085 if (intel_crtc->plane) 5023 if (IS_GEN3(dev) || IS_GEN2(dev)) {
5086 flip_mask = I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; 5024 u32 flip_mask;
5087 else
5088 flip_mask = I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
5089 5025
5090 /* Wait for any previous flip to finish */ 5026 if (intel_crtc->plane)
5091 if (IS_GEN3(dev)) 5027 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5092 while (I915_READ(ISR) & flip_mask) 5028 else
5093 ; 5029 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5030
5031 BEGIN_LP_RING(2);
5032 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5033 OUT_RING(0);
5034 ADVANCE_LP_RING();
5035 }
5036
5037 work->enable_stall_check = true;
5094 5038
5095 /* Offset into the new buffer for cases of shared fbs between CRTCs */ 5039 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5096 offset = obj_priv->gtt_offset; 5040 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
5097 offset += (crtc->y * fb->pitch) + (crtc->x * (fb->bits_per_pixel) / 8);
5098 5041
5099 BEGIN_LP_RING(4); 5042 BEGIN_LP_RING(4);
5100 if (IS_I965G(dev)) { 5043 switch(INTEL_INFO(dev)->gen) {
5044 case 2:
5101 OUT_RING(MI_DISPLAY_FLIP | 5045 OUT_RING(MI_DISPLAY_FLIP |
5102 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 5046 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5103 OUT_RING(fb->pitch); 5047 OUT_RING(fb->pitch);
5104 OUT_RING(offset | obj_priv->tiling_mode); 5048 OUT_RING(obj_priv->gtt_offset + offset);
5105 pipesrc = I915_READ(pipesrc_reg); 5049 OUT_RING(MI_NOOP);
5106 OUT_RING(pipesrc & 0x0fff0fff); 5050 break;
5107 } else { 5051
5052 case 3:
5108 OUT_RING(MI_DISPLAY_FLIP_I915 | 5053 OUT_RING(MI_DISPLAY_FLIP_I915 |
5109 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 5054 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5110 OUT_RING(fb->pitch); 5055 OUT_RING(fb->pitch);
5111 OUT_RING(offset); 5056 OUT_RING(obj_priv->gtt_offset + offset);
5112 OUT_RING(MI_NOOP); 5057 OUT_RING(MI_NOOP);
5058 break;
5059
5060 case 4:
5061 case 5:
5062 /* i965+ uses the linear or tiled offsets from the
5063 * Display Registers (which do not change across a page-flip)
5064 * so we need only reprogram the base address.
5065 */
5066 OUT_RING(MI_DISPLAY_FLIP |
5067 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5068 OUT_RING(fb->pitch);
5069 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
5070
5071 /* XXX Enabling the panel-fitter across page-flip is so far
5072 * untested on non-native modes, so ignore it for now.
5073 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5074 */
5075 pf = 0;
5076 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5077 OUT_RING(pf | pipesrc);
5078 break;
5079
5080 case 6:
5081 OUT_RING(MI_DISPLAY_FLIP |
5082 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5083 OUT_RING(fb->pitch | obj_priv->tiling_mode);
5084 OUT_RING(obj_priv->gtt_offset);
5085
5086 pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5087 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5088 OUT_RING(pf | pipesrc);
5089 break;
5113 } 5090 }
5114 ADVANCE_LP_RING(); 5091 ADVANCE_LP_RING();
5115 5092
@@ -5190,7 +5167,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
5190 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; 5167 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5191 5168
5192 intel_crtc->cursor_addr = 0; 5169 intel_crtc->cursor_addr = 0;
5193 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF; 5170 intel_crtc->dpms_mode = -1;
5194 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); 5171 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5195 5172
5196 intel_crtc->busy = false; 5173 intel_crtc->busy = false;
@@ -5432,37 +5409,37 @@ static const struct drm_mode_config_funcs intel_mode_funcs = {
5432}; 5409};
5433 5410
5434static struct drm_gem_object * 5411static struct drm_gem_object *
5435intel_alloc_power_context(struct drm_device *dev) 5412intel_alloc_context_page(struct drm_device *dev)
5436{ 5413{
5437 struct drm_gem_object *pwrctx; 5414 struct drm_gem_object *ctx;
5438 int ret; 5415 int ret;
5439 5416
5440 pwrctx = i915_gem_alloc_object(dev, 4096); 5417 ctx = i915_gem_alloc_object(dev, 4096);
5441 if (!pwrctx) { 5418 if (!ctx) {
5442 DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); 5419 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5443 return NULL; 5420 return NULL;
5444 } 5421 }
5445 5422
5446 mutex_lock(&dev->struct_mutex); 5423 mutex_lock(&dev->struct_mutex);
5447 ret = i915_gem_object_pin(pwrctx, 4096); 5424 ret = i915_gem_object_pin(ctx, 4096);
5448 if (ret) { 5425 if (ret) {
5449 DRM_ERROR("failed to pin power context: %d\n", ret); 5426 DRM_ERROR("failed to pin power context: %d\n", ret);
5450 goto err_unref; 5427 goto err_unref;
5451 } 5428 }
5452 5429
5453 ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1); 5430 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
5454 if (ret) { 5431 if (ret) {
5455 DRM_ERROR("failed to set-domain on power context: %d\n", ret); 5432 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5456 goto err_unpin; 5433 goto err_unpin;
5457 } 5434 }
5458 mutex_unlock(&dev->struct_mutex); 5435 mutex_unlock(&dev->struct_mutex);
5459 5436
5460 return pwrctx; 5437 return ctx;
5461 5438
5462err_unpin: 5439err_unpin:
5463 i915_gem_object_unpin(pwrctx); 5440 i915_gem_object_unpin(ctx);
5464err_unref: 5441err_unref:
5465 drm_gem_object_unreference(pwrctx); 5442 drm_gem_object_unreference(ctx);
5466 mutex_unlock(&dev->struct_mutex); 5443 mutex_unlock(&dev->struct_mutex);
5467 return NULL; 5444 return NULL;
5468} 5445}
@@ -5494,7 +5471,6 @@ void ironlake_enable_drps(struct drm_device *dev)
5494 struct drm_i915_private *dev_priv = dev->dev_private; 5471 struct drm_i915_private *dev_priv = dev->dev_private;
5495 u32 rgvmodectl = I915_READ(MEMMODECTL); 5472 u32 rgvmodectl = I915_READ(MEMMODECTL);
5496 u8 fmax, fmin, fstart, vstart; 5473 u8 fmax, fmin, fstart, vstart;
5497 int i = 0;
5498 5474
5499 /* 100ms RC evaluation intervals */ 5475 /* 100ms RC evaluation intervals */
5500 I915_WRITE(RCUPEI, 100000); 5476 I915_WRITE(RCUPEI, 100000);
@@ -5538,13 +5514,8 @@ void ironlake_enable_drps(struct drm_device *dev)
5538 rgvmodectl |= MEMMODE_SWMODE_EN; 5514 rgvmodectl |= MEMMODE_SWMODE_EN;
5539 I915_WRITE(MEMMODECTL, rgvmodectl); 5515 I915_WRITE(MEMMODECTL, rgvmodectl);
5540 5516
5541 while (I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) { 5517 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 1, 0))
5542 if (i++ > 100) { 5518 DRM_ERROR("stuck trying to change perf mode\n");
5543 DRM_ERROR("stuck trying to change perf mode\n");
5544 break;
5545 }
5546 msleep(1);
5547 }
5548 msleep(1); 5519 msleep(1);
5549 5520
5550 ironlake_set_drps(dev, fstart); 5521 ironlake_set_drps(dev, fstart);
@@ -5725,7 +5696,8 @@ void intel_init_clock_gating(struct drm_device *dev)
5725 ILK_DPFC_DIS2 | 5696 ILK_DPFC_DIS2 |
5726 ILK_CLK_FBC); 5697 ILK_CLK_FBC);
5727 } 5698 }
5728 return; 5699 if (IS_GEN6(dev))
5700 return;
5729 } else if (IS_G4X(dev)) { 5701 } else if (IS_G4X(dev)) {
5730 uint32_t dspclk_gate; 5702 uint32_t dspclk_gate;
5731 I915_WRITE(RENCLK_GATE_D1, 0); 5703 I915_WRITE(RENCLK_GATE_D1, 0);
@@ -5768,6 +5740,31 @@ void intel_init_clock_gating(struct drm_device *dev)
5768 * GPU can automatically power down the render unit if given a page 5740 * GPU can automatically power down the render unit if given a page
5769 * to save state. 5741 * to save state.
5770 */ 5742 */
5743 if (IS_IRONLAKE_M(dev)) {
5744 if (dev_priv->renderctx == NULL)
5745 dev_priv->renderctx = intel_alloc_context_page(dev);
5746 if (dev_priv->renderctx) {
5747 struct drm_i915_gem_object *obj_priv;
5748 obj_priv = to_intel_bo(dev_priv->renderctx);
5749 if (obj_priv) {
5750 BEGIN_LP_RING(4);
5751 OUT_RING(MI_SET_CONTEXT);
5752 OUT_RING(obj_priv->gtt_offset |
5753 MI_MM_SPACE_GTT |
5754 MI_SAVE_EXT_STATE_EN |
5755 MI_RESTORE_EXT_STATE_EN |
5756 MI_RESTORE_INHIBIT);
5757 OUT_RING(MI_NOOP);
5758 OUT_RING(MI_FLUSH);
5759 ADVANCE_LP_RING();
5760 }
5761 } else {
5762 DRM_DEBUG_KMS("Failed to allocate render context."
5763 "Disable RC6\n");
5764 return;
5765 }
5766 }
5767
5771 if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) { 5768 if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5772 struct drm_i915_gem_object *obj_priv = NULL; 5769 struct drm_i915_gem_object *obj_priv = NULL;
5773 5770
@@ -5776,7 +5773,7 @@ void intel_init_clock_gating(struct drm_device *dev)
5776 } else { 5773 } else {
5777 struct drm_gem_object *pwrctx; 5774 struct drm_gem_object *pwrctx;
5778 5775
5779 pwrctx = intel_alloc_power_context(dev); 5776 pwrctx = intel_alloc_context_page(dev);
5780 if (pwrctx) { 5777 if (pwrctx) {
5781 dev_priv->pwrctx = pwrctx; 5778 dev_priv->pwrctx = pwrctx;
5782 obj_priv = to_intel_bo(pwrctx); 5779 obj_priv = to_intel_bo(pwrctx);
@@ -5948,6 +5945,29 @@ static void intel_init_quirks(struct drm_device *dev)
5948 } 5945 }
5949} 5946}
5950 5947
5948/* Disable the VGA plane that we never use */
5949static void i915_disable_vga(struct drm_device *dev)
5950{
5951 struct drm_i915_private *dev_priv = dev->dev_private;
5952 u8 sr1;
5953 u32 vga_reg;
5954
5955 if (HAS_PCH_SPLIT(dev))
5956 vga_reg = CPU_VGACNTRL;
5957 else
5958 vga_reg = VGACNTRL;
5959
5960 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
5961 outb(1, VGA_SR_INDEX);
5962 sr1 = inb(VGA_SR_DATA);
5963 outb(sr1 | 1<<5, VGA_SR_DATA);
5964 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
5965 udelay(300);
5966
5967 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
5968 POSTING_READ(vga_reg);
5969}
5970
5951void intel_modeset_init(struct drm_device *dev) 5971void intel_modeset_init(struct drm_device *dev)
5952{ 5972{
5953 struct drm_i915_private *dev_priv = dev->dev_private; 5973 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -5996,6 +6016,9 @@ void intel_modeset_init(struct drm_device *dev)
5996 6016
5997 intel_init_clock_gating(dev); 6017 intel_init_clock_gating(dev);
5998 6018
6019 /* Just disable it once at startup */
6020 i915_disable_vga(dev);
6021
5999 if (IS_IRONLAKE_M(dev)) { 6022 if (IS_IRONLAKE_M(dev)) {
6000 ironlake_enable_drps(dev); 6023 ironlake_enable_drps(dev);
6001 intel_init_emon(dev); 6024 intel_init_emon(dev);
@@ -6034,6 +6057,16 @@ void intel_modeset_cleanup(struct drm_device *dev)
6034 if (dev_priv->display.disable_fbc) 6057 if (dev_priv->display.disable_fbc)
6035 dev_priv->display.disable_fbc(dev); 6058 dev_priv->display.disable_fbc(dev);
6036 6059
6060 if (dev_priv->renderctx) {
6061 struct drm_i915_gem_object *obj_priv;
6062
6063 obj_priv = to_intel_bo(dev_priv->renderctx);
6064 I915_WRITE(CCID, obj_priv->gtt_offset &~ CCID_EN);
6065 I915_READ(CCID);
6066 i915_gem_object_unpin(dev_priv->renderctx);
6067 drm_gem_object_unreference(dev_priv->renderctx);
6068 }
6069
6037 if (dev_priv->pwrctx) { 6070 if (dev_priv->pwrctx) {
6038 struct drm_i915_gem_object *obj_priv; 6071 struct drm_i915_gem_object *obj_priv;
6039 6072
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-25 10:37:02 -0400