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-rw-r--r--arch/sh/include/asm/io.h61
1 files changed, 9 insertions, 52 deletions
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
index 89ab2c57a4c..28c5aa58bb4 100644
--- a/arch/sh/include/asm/io.h
+++ b/arch/sh/include/asm/io.h
@@ -11,11 +11,6 @@
11 * 11 *
12 * While read{b,w,l,q} and write{b,w,l,q} contain memory barriers 12 * While read{b,w,l,q} and write{b,w,l,q} contain memory barriers
13 * automatically, there are also __raw versions, which do not. 13 * automatically, there are also __raw versions, which do not.
14 *
15 * Historically, we have also had ctrl_in{b,w,l,q}/ctrl_out{b,w,l,q} for
16 * SuperH specific I/O (raw I/O to on-chip CPU peripherals). In practice
17 * these have the same semantics as the __raw variants, and as such, all
18 * new code should be using the __raw versions.
19 */ 14 */
20#include <linux/errno.h> 15#include <linux/errno.h>
21#include <asm/cache.h> 16#include <asm/cache.h>
@@ -231,52 +226,6 @@ __BUILD_IOPORT_STRING(q, u64)
231 226
232#endif 227#endif
233 228
234/*
235 * Legacy SuperH on-chip I/O functions
236 *
237 * These are all deprecated, all new (and especially cross-platform) code
238 * should be using the __raw_xxx() routines directly.
239 */
240static inline u8 __deprecated ctrl_inb(unsigned long addr)
241{
242 return __raw_readb(addr);
243}
244
245static inline u16 __deprecated ctrl_inw(unsigned long addr)
246{
247 return __raw_readw(addr);
248}
249
250static inline u32 __deprecated ctrl_inl(unsigned long addr)
251{
252 return __raw_readl(addr);
253}
254
255static inline u64 __deprecated ctrl_inq(unsigned long addr)
256{
257 return __raw_readq(addr);
258}
259
260static inline void __deprecated ctrl_outb(u8 v, unsigned long addr)
261{
262 __raw_writeb(v, addr);
263}
264
265static inline void __deprecated ctrl_outw(u16 v, unsigned long addr)
266{
267 __raw_writew(v, addr);
268}
269
270static inline void __deprecated ctrl_outl(u32 v, unsigned long addr)
271{
272 __raw_writel(v, addr);
273}
274
275static inline void __deprecated ctrl_outq(u64 v, unsigned long addr)
276{
277 __raw_writeq(v, addr);
278}
279
280#define IO_SPACE_LIMIT 0xffffffff 229#define IO_SPACE_LIMIT 0xffffffff
281 230
282/* synco on SH-4A, otherwise a nop */ 231/* synco on SH-4A, otherwise a nop */
@@ -341,7 +290,15 @@ __ioremap_29bit(phys_addr_t offset, unsigned long size, pgprot_t prot)
341 * mapping must be done by the PMB or by using page tables. 290 * mapping must be done by the PMB or by using page tables.
342 */ 291 */
343 if (likely(PXSEG(offset) < P3SEG && PXSEG(last_addr) < P3SEG)) { 292 if (likely(PXSEG(offset) < P3SEG && PXSEG(last_addr) < P3SEG)) {
344 if (unlikely(pgprot_val(prot) & _PAGE_CACHABLE)) 293 u64 flags = pgprot_val(prot);
294
295 /*
296 * Anything using the legacy PTEA space attributes needs
297 * to be kicked down to page table mappings.
298 */
299 if (unlikely(flags & _PAGE_PCC_MASK))
300 return NULL;
301 if (unlikely(flags & _PAGE_CACHABLE))
345 return (void __iomem *)P1SEGADDR(offset); 302 return (void __iomem *)P1SEGADDR(offset);
346 303
347 return (void __iomem *)P2SEGADDR(offset); 304 return (void __iomem *)P2SEGADDR(offset);